1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com)
7 ;; http://www.verilog.com
9 ;; AUTO features, signal, modsig; by: Wilson Snyder
10 ;; (wsnyder@wsnyder.org)
11 ;; http://www.veripool.com
12 ;; Keywords: languages
14 ;; This file is part of GNU Emacs.
16 ;; GNU Emacs is free software; you can redistribute it and/or modify
17 ;; it under the terms of the GNU General Public License as published by
18 ;; the Free Software Foundation; either version 3, or (at your option)
21 ;; GNU Emacs is distributed in the hope that it will be useful,
22 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ;; GNU General Public License for more details.
26 ;; You should have received a copy of the GNU General Public License
27 ;; along with GNU Emacs; see the file COPYING. If not, write to the
28 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
29 ;; Boston, MA 02110-1301, USA.
33 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of emacs
38 ;; A major mode for editing Verilog HDL source code. When you have
39 ;; entered Verilog mode, you may get more info by pressing C-h m. You
40 ;; may also get online help describing various functions by: C-h f
41 ;; <Name of function you want described>
43 ;; KNOWN BUGS / BUG REPORTS
44 ;; =======================
46 ;; Verilog is a rapidly evolving language, and hence this mode is
47 ;; under continuous development. Hence this is beta code, and likely
48 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
49 ;; Please use verilog-submit-bug-report to submit a report; type C-c
50 ;; C-b to invoke this and as a result I will have a much easier time
51 ;; of reproducing the bug you find, and hence fixing it.
53 ;; INSTALLING THE MODE
54 ;; ===================
56 ;; An older version of this mode may be already installed as a part of
57 ;; your environment, and one method of updating would be to update
58 ;; your emacs environment. Sometimes this is difficult for local
59 ;; political/control reasons, and hence you can always install a
60 ;; private copy (or even a shared copy) which overrides the system
63 ;; You can get step by step help in installing this file by going to
64 ;; <http://www.verilog.com/emacs_install.html>
66 ;; The short list of installation instructions are: To set up
67 ;; automatic verilog mode, put this file in your load path, and put
68 ;; the following in code (please un comment it first!) in your
69 ;; .emacs, or in your site's site-load.el
71 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
72 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
73 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
75 ;; If you want to customize Verilog mode to fit your needs better,
76 ;; you may add these lines (the values of the variables presented
77 ;; here are the defaults). Note also that if you use an emacs that
78 ;; supports custom, it's probably better to use the custom menu to
81 ;; Be sure to examine at the help for verilog-auto, and the other
82 ;; verilog-auto-* functions for some major coding time savers.
84 ; ;; User customization for Verilog mode
85 ; (setq verilog-indent-level 3
86 ; verilog-indent-level-module 3
87 ; verilog-indent-level-declaration 3
88 ; verilog-indent-level-behavioral 3
89 ; verilog-indent-level-directive 1
90 ; verilog-case-indent 2
91 ; verilog-auto-newline t
92 ; verilog-auto-indent-on-newline t
93 ; verilog-tab-always-indent t
94 ; verilog-auto-endcomments t
95 ; verilog-minimum-comment-distance 40
96 ; verilog-indent-begin-after-if t
97 ; verilog-auto-lineup '(all)
98 ; verilog-highlight-p1800-keywords nil
99 ; verilog-linter "my_lint_shell_command"
109 ;; This variable will always hold the version number of the mode
110 (defconst verilog-mode-version
"377"
111 "Version of this verilog mode.")
112 (defconst verilog-mode-release-date
"2007-12-07"
113 "Version of this verilog mode.")
115 (defun verilog-version ()
116 "Inform caller of the version of this file."
118 (message (concat "Using verilog-mode version " verilog-mode-version
) ))
120 ;; Insure we have certain packages, and deal with it if we don't
132 (require 'regexp-opt
)
135 (load "skeleton") ;; bug in 19.28 through 19.30 skeleton.el, not provided.
143 (defmacro when
(cond &rest body
)
144 (list 'if cond
(cons 'progn body
))))
147 (if (fboundp 'unless
)
149 (defmacro unless
(cond &rest body
)
150 (cons 'if
(cons cond
(cons nil body
)))))
153 (if (fboundp 'store-match-data
)
155 (defmacro store-match-data
(&rest args
) nil
))
158 (if (boundp 'current-menubar
)
161 (defmacro set-buffer-menubar
(&rest args
) nil
)
162 (defmacro add-submenu
(&rest args
) nil
))
166 (if (fboundp 'zmacs-activate-region
)
168 (defmacro zmacs-activate-region
(&rest args
) nil
))
171 (if (fboundp 'char-before
)
173 (defmacro char-before
(&rest body
)
174 (char-after (1- (point)))))
176 ;; Requires to define variables that would be "free" warnings
190 (if (fboundp 'dinotrace-unannotate-all
)
192 (defun dinotrace-unannotate-all (&rest args
) nil
))
195 (if (fboundp 'customize-apropos
)
197 (defun customize-apropos (&rest args
) nil
))
200 (if (fboundp 'match-string-no-properties
)
202 (defsubst match-string-no-properties
(num &optional string
)
203 "Return string of text matched by last search, without text properties.
204 NUM specifies which parenthesized expression in the last regexp.
205 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
206 Zero means the entire text matched by the whole regexp or whole string.
207 STRING should be given if the last search was by `string-match' on STRING."
208 (if (match-beginning num
)
211 (substring string
(match-beginning num
) (match-end num
))))
212 (set-text-properties 0 (length result
) nil result
)
214 (buffer-substring-no-properties (match-beginning num
)
219 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
220 nil
;; We've got what we needed
221 ;; We have the old custom-library, hack around it!
222 (defmacro defgroup
(&rest args
) nil
)
223 (defmacro customize
(&rest args
)
224 (message "Sorry, Customize is not available with this version of emacs"))
225 (defmacro defcustom
(var value doc
&rest args
)
226 `(defvar ,var
,value
,doc
))
228 (if (fboundp 'defface
)
230 (defmacro defface
(var values doc
&rest args
)
234 (if (and (featurep 'custom
) (fboundp 'customize-group
))
235 nil
;; We've got what we needed
236 ;; We have an intermediate custom-library, hack around it!
237 (defmacro customize-group
(var &rest args
)
242 ;; Provide a regular expression optimization routine, using regexp-opt
243 ;; if provided by the user's elisp libraries
245 (if (fboundp 'regexp-opt
)
246 ;; regexp-opt is defined, does it take 3 or 2 arguments?
247 (if (fboundp 'function-max-args
)
248 (let ((args (function-max-args `regexp-opt
)))
250 ((eq args
3) ;; It takes 3
251 (condition-case nil
; Hide this defun from emacses
252 ;with just a two input regexp
253 (defun verilog-regexp-opt (a b
)
254 "Deal with differing number of required arguments for `regexp-opt'.
255 Call 'regexp-opt' on A and B."
260 ((eq args
2) ;; It takes 2
261 (defun verilog-regexp-opt (a b
)
262 "Call 'regexp-opt' on A and B."
266 ;; We can't tell; assume it takes 2
267 (defun verilog-regexp-opt (a b
)
268 "Call 'regexp-opt' on A and B."
271 ;; There is no regexp-opt, provide our own
272 (defun verilog-regexp-opt (strings &optional paren shy
)
273 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
274 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
277 (defun verilog-regexp-words (a)
278 "Call 'regexp-opt' with word delimiters for the words A."
279 (concat "\\<" (verilog-regexp-opt a t
) "\\>"))
281 (defun verilog-customize ()
282 "Link to customize screen for Verilog."
284 (customize-group 'verilog-mode
))
286 (defun verilog-font-customize ()
287 "Link to customize fonts used for Verilog."
289 (customize-apropos "font-lock-*" 'faces
))
291 (defgroup verilog-mode nil
292 "Facilitates easy editing of Verilog source text"
295 ; (defgroup verilog-mode-fonts nil
296 ; "Facilitates easy customization fonts used in Verilog source text"
297 ; :link '(customize-apropos "font-lock-*" 'faces)
298 ; :group 'verilog-mode)
300 (defgroup verilog-mode-indent nil
301 "Customize indentation and highlighting of verilog source text"
302 :group
'verilog-mode
)
304 (defgroup verilog-mode-actions nil
305 "Customize actions on verilog source text"
306 :group
'verilog-mode
)
308 (defgroup verilog-mode-auto nil
309 "Customize AUTO actions when expanding verilog source text"
310 :group
'verilog-mode
)
312 (defcustom verilog-linter
313 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
314 "*Unix program and arguments to call to run a lint checker on verilog source.
315 Depending on the `verilog-set-compile-command', this may be invoked when
316 you type \\[compile]. When the compile completes, \\[next-error] will take
317 you to the next lint error."
319 :group
'verilog-mode-actions
)
321 (defcustom verilog-coverage
322 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
323 "*Program and arguments to use to annotate for coverage verilog source.
324 Depending on the `verilog-set-compile-command', this may be invoked when
325 you type \\[compile]. When the compile completes, \\[next-error] will take
326 you to the next lint error."
328 :group
'verilog-mode-actions
)
330 (defcustom verilog-simulator
331 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
332 "*Program and arguments to use to interpret verilog source.
333 Depending on the `verilog-set-compile-command', this may be invoked when
334 you type \\[compile]. When the compile completes, \\[next-error] will take
335 you to the next lint error."
337 :group
'verilog-mode-actions
)
339 (defcustom verilog-compiler
340 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
341 "*Program and arguments to use to compile verilog source.
342 Depending on the `verilog-set-compile-command', this may be invoked when
343 you type \\[compile]. When the compile completes, \\[next-error] will take
344 you to the next lint error."
346 :group
'verilog-mode-actions
)
348 (defvar verilog-tool
'verilog-linter
349 "Which tool to use for building compiler-command.
350 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
351 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
352 menu. See `verilog-set-compile-command' for more information.")
354 (defcustom verilog-highlight-translate-off nil
355 "*Non-nil means background-highlight code excluded from translation.
356 That is, all code between \"// synopsys translate_off\" and
357 \"// synopsys translate_on\" is highlighted using a different background color
358 \(face `verilog-font-lock-translate-off-face').
360 Note: This will slow down on-the-fly fontification (and thus editing).
362 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
363 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
365 :group
'verilog-mode-indent
)
367 (defcustom verilog-indent-level
3
368 "*Indentation of Verilog statements with respect to containing block."
369 :group
'verilog-mode-indent
372 (defcustom verilog-indent-level-module
3
373 "*Indentation of Module level Verilog statements. (eg always, initial)
374 Set to 0 to get initial and always statements lined up on the left side of
376 :group
'verilog-mode-indent
379 (defcustom verilog-indent-level-declaration
3
380 "*Indentation of declarations with respect to containing block.
381 Set to 0 to get them list right under containing block."
382 :group
'verilog-mode-indent
385 (defcustom verilog-indent-declaration-macros nil
386 "*How to treat macro expansions in a declaration.
391 If non nil, treat as:
395 :group
'verilog-mode-indent
398 (defcustom verilog-indent-lists t
399 "*How to treat indenting items in a list.
400 If t (the default), indent as:
401 always @( posedge a or
405 always @( posedge a or
407 :group
'verilog-mode-indent
410 (defcustom verilog-indent-level-behavioral
3
411 "*Absolute indentation of first begin in a task or function block.
412 Set to 0 to get such code to start at the left side of the screen."
413 :group
'verilog-mode-indent
416 (defcustom verilog-indent-level-directive
1
417 "*Indentation to add to each level of `ifdef declarations.
418 Set to 0 to have all directives start at the left side of the screen."
419 :group
'verilog-mode-indent
422 (defcustom verilog-cexp-indent
2
423 "*Indentation of Verilog statements split across lines."
424 :group
'verilog-mode-indent
427 (defcustom verilog-case-indent
2
428 "*Indentation for case statements."
429 :group
'verilog-mode-indent
432 (defcustom verilog-auto-newline t
433 "*True means automatically newline after semicolons."
434 :group
'verilog-mode-indent
437 (defcustom verilog-auto-indent-on-newline t
438 "*True means automatically indent line after newline."
439 :group
'verilog-mode-indent
442 (defcustom verilog-tab-always-indent t
443 "*True means TAB should always re-indent the current line.
444 Nil means TAB will only reindent when at the beginning of the line."
445 :group
'verilog-mode-indent
448 (defcustom verilog-tab-to-comment nil
449 "*True means TAB moves to the right hand column in preparation for a comment."
450 :group
'verilog-mode-actions
453 (defcustom verilog-indent-begin-after-if t
454 "*If true, indent begin statements following if, else, while, for and repeat.
455 Otherwise, line them up."
456 :group
'verilog-mode-indent
460 (defcustom verilog-align-ifelse nil
461 "*If true, align `else' under matching `if'.
462 Otherwise else is lined up with first character on line holding matching if."
463 :group
'verilog-mode-indent
466 (defcustom verilog-minimum-comment-distance
10
467 "*Minimum distance (in lines) between begin and end required before a comment.
468 Setting this variable to zero results in every end acquiring a comment; the
469 default avoids too many redundant comments in tight quarters"
470 :group
'verilog-mode-indent
473 (defcustom verilog-auto-lineup
'(declaration)
474 "*Algorithm for lining up statements on multiple lines.
476 If this list contains the symbol 'all', then all line ups described below
479 If this list contains the symbol 'declaration', then declarations are lined up
480 with any preceding declarations, taking into account widths and the like, so
481 for example the code:
488 If this list contains the symbol 'assignment', then assignments are lined up
489 with any preceding assignments, so for example the code
490 a_long_variable = b + c;
493 a_long_variable = b + c;
496 ;; The following is not implemented:
497 ;If this list contains the symbol 'case', then case items are lined up
498 ;with any preceding case items, so for example the code
500 ; a_long_state : a = 3;
505 ; a_long_state : a = 3;
510 :group
'verilog-mode-indent
513 (defcustom verilog-highlight-p1800-keywords nil
514 "*If true highlight words newly reserved by IEEE-1800 in
515 verilog-font-lock-p1800-face in order to gently suggest changing where
516 these words are used as variables to something else. Nil means highlight
517 these words as appropriate for the SystemVerilog IEEE-1800 standard. Note
518 that changing this will require restarting emacs to see the effect as font
519 color choices are cached by emacs"
520 :group
'verilog-mode-indent
523 (defcustom verilog-auto-endcomments t
524 "*True means insert a comment /* ... */ after 'end's.
525 The name of the function or case will be set between the braces."
526 :group
'verilog-mode-actions
529 (defcustom verilog-auto-read-includes nil
530 "*True means to automatically read includes before AUTOs.
531 This will do a `verilog-read-defines' and `verilog-read-includes' before
532 each AUTO expansion. This makes it easier to embed defines and includes,
533 but can result in very slow reading times if there are many or large
535 :group
'verilog-mode-actions
538 (defcustom verilog-auto-save-policy nil
539 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
540 A value of `force' will always do a \\[verilog-auto] automatically if
541 needed on every save. A value of `detect' will do \\[verilog-auto]
542 automatically when it thinks necessary. A value of `ask' will query the
543 user when it thinks updating is needed.
545 You should not rely on the 'ask or 'detect policies, they are safeguards
546 only. They do not detect when AUTOINSTs need to be updated because a
547 sub-module's port list has changed."
548 :group
'verilog-mode-actions
549 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
551 (defcustom verilog-auto-star-expand t
552 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
553 They will be expanded in the same way as if there was a AUTOINST in the
554 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
555 :group
'verilog-mode-actions
558 (defcustom verilog-auto-star-save nil
559 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
560 Nil indicates direct connections will be removed before saving. Only
561 meaningful to those created due to `verilog-auto-star-expand' being set.
563 Instead of setting this, you may want to use /*AUTOINST*/, which will
565 :group
'verilog-mode-actions
568 (defvar verilog-auto-update-tick nil
569 "Modification tick at which autos were last performed.")
571 (defvar verilog-auto-last-file-locals nil
572 "Text from file-local-variables during last evaluation.")
574 (defvar verilog-error-regexp-add-didit nil
)
575 (defvar verilog-error-regexp nil
)
576 (setq verilog-error-regexp-add-didit nil
580 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
581 ; Most SureFire tools
582 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
584 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
585 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
587 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
588 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
590 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
591 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
592 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
593 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
595 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
596 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
598 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
599 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
600 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
602 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
604 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
606 ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
609 (defvar verilog-error-font-lock-keywords
611 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
612 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
614 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
615 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
618 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
619 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
621 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
622 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
624 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
625 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
627 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
628 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
630 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
631 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
633 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
634 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
636 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
637 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
639 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
640 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
642 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t
)
643 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t
)
645 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t
)
646 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t
)
648 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t
)
649 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
651 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t
)
652 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t
)
654 "*Keywords to also highlight in Verilog *compilation* buffers."
657 (defcustom verilog-library-flags
'("")
658 "*List of standard Verilog arguments to use for /*AUTOINST*/.
659 These arguments are used to find files for `verilog-auto', and match
660 the flags accepted by a standard Verilog-XL simulator.
662 -f filename Reads more `verilog-library-flags' from the filename.
663 +incdir+dir Adds the directory to `verilog-library-directories'.
664 -Idir Adds the directory to `verilog-library-directories'.
665 -y dir Adds the directory to `verilog-library-directories'.
666 +libext+.v Adds the extensions to `verilog-library-extensions'.
667 -v filename Adds the filename to `verilog-library-files'.
669 filename Adds the filename to `verilog-library-files'.
670 This is not recommended, -v is a better choice.
672 You might want these defined in each file; put at the *END* of your file
676 // verilog-library-flags:(\"-y dir -y otherdir\")
679 Verilog-mode attempts to detect changes to this local variable, but they
680 are only insured to be correct when the file is first visited. Thus if you
681 have problems, use \\[find-alternate-file] RET to have these take effect.
683 See also the variables mentioned above."
684 :group
'verilog-mode-auto
685 :type
'(repeat string
))
687 (defcustom verilog-library-directories
'(".")
688 "*List of directories when looking for files for /*AUTOINST*/.
689 The directory may be relative to the current file, or absolute.
690 Environment variables are also expanded in the directory names.
691 Having at least the current directory is a good idea.
693 You might want these defined in each file; put at the *END* of your file
697 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
700 Verilog-mode attempts to detect changes to this local variable, but they
701 are only insured to be correct when the file is first visited. Thus if you
702 have problems, use \\[find-alternate-file] RET to have these take effect.
704 See also `verilog-library-flags', `verilog-library-files'
705 and `verilog-library-extensions'."
706 :group
'verilog-mode-auto
707 :type
'(repeat file
))
709 (defcustom verilog-library-files
'()
710 "*List of files to search for modules when looking for AUTOINST files.
711 This is a complete path, usually to a technology file with many standard
714 You might want these defined in each file; put at the *END* of your file
718 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
721 Verilog-mode attempts to detect changes to this local variable, but they
722 are only insured to be correct when the file is first visited. Thus if you
723 have problems, use \\[find-alternate-file] RET to have these take effect.
725 See also `verilog-library-flags', `verilog-library-directories'."
726 :group
'verilog-mode-auto
727 :type
'(repeat directory
))
729 (defcustom verilog-library-extensions
'(".v")
730 "*List of extensions to use when looking for files for /*AUTOINST*/.
731 See also `verilog-library-flags', `verilog-library-directories'."
732 :type
'(repeat string
)
733 :group
'verilog-mode-auto
)
735 (defcustom verilog-active-low-regexp nil
736 "*If set, treat signals matching this regexp as active low.
737 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
738 you will probably also need `verilog-auto-reset-widths' set."
739 :group
'verilog-mode-auto
742 (defcustom verilog-auto-sense-include-inputs nil
743 "*If true, AUTOSENSE should include all inputs.
744 If nil, only inputs that are NOT output signals in the same block are
747 :group
'verilog-mode-auto
)
749 (defcustom verilog-auto-sense-defines-constant nil
750 "*If true, AUTOSENSE should assume all defines represent constants.
751 When true, the defines will not be included in sensitivity lists. To
752 maintain compatibility with other sites, this should be set at the bottom
753 of each verilog file that requires it, rather than being set globally."
755 :group
'verilog-mode-auto
)
757 (defcustom verilog-auto-reset-widths t
758 "*If true, AUTORESET should determine the width of signals.
759 This is then used to set the width of the zero (32'h0 for example). This
760 is required by some lint tools that aren't smart enough to ignore widths of
761 the constant zero. This may result in ugly code when parameters determine
762 the MSB or LSB of a signal inside a AUTORESET."
764 :group
'verilog-mode-auto
)
766 (defcustom verilog-assignment-delay
""
767 "*Text used for delays in delayed assignments. Add a trailing space if set."
769 :group
'verilog-mode-auto
)
771 (defcustom verilog-auto-inst-vector t
772 "*If true, when creating default ports with AUTOINST, use bus subscripts.
773 If nil, skip the subscript when it matches the entire bus as declared in
774 the module (AUTOWIRE signals always are subscripted, you must manually
775 declare the wire to have the subscripts removed.) Nil may speed up some
776 simulators, but is less general and harder to read, so avoid."
777 :group
'verilog-mode-auto
780 (defcustom verilog-auto-inst-template-numbers nil
781 "*If true, when creating templated ports with AUTOINST, add a comment.
782 The comment will add the line number of the template that was used for that
783 port declaration. Setting this aids in debugging, but nil is suggested for
784 regular use to prevent large numbers of merge conflicts."
785 :group
'verilog-mode-auto
788 (defvar verilog-auto-inst-column
40
789 "Column number for first part of auto-inst.")
791 (defcustom verilog-auto-input-ignore-regexp nil
792 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
793 See the \\[verilog-faq] for examples on using this."
794 :group
'verilog-mode-auto
797 (defcustom verilog-auto-inout-ignore-regexp nil
798 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
799 See the \\[verilog-faq] for examples on using this."
800 :group
'verilog-mode-auto
803 (defcustom verilog-auto-output-ignore-regexp nil
804 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
805 See the \\[verilog-faq] for examples on using this."
806 :group
'verilog-mode-auto
809 (defcustom verilog-auto-unused-ignore-regexp nil
810 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
811 See the \\[verilog-faq] for examples on using this."
812 :group
'verilog-mode-auto
815 (defcustom verilog-typedef-regexp nil
816 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
817 For example, \"_t$\" matches typedefs named with _t, as in the C language."
818 :group
'verilog-mode-auto
821 (defcustom verilog-mode-hook
'verilog-set-compile-command
822 "*Hook (List of functions) run after verilog mode is loaded."
824 :group
'verilog-mode
)
826 (defcustom verilog-auto-hook nil
827 "*Hook run after `verilog-mode' updates AUTOs."
829 :group
'verilog-mode-auto
)
831 (defcustom verilog-before-auto-hook nil
832 "*Hook run before `verilog-mode' updates AUTOs."
834 :group
'verilog-mode-auto
)
836 (defcustom verilog-delete-auto-hook nil
837 "*Hook run after `verilog-mode' deletes AUTOs."
839 :group
'verilog-mode-auto
)
841 (defcustom verilog-before-delete-auto-hook nil
842 "*Hook run before `verilog-mode' deletes AUTOs."
844 :group
'verilog-mode-auto
)
846 (defcustom verilog-getopt-flags-hook nil
847 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
849 :group
'verilog-mode-auto
)
851 (defcustom verilog-before-getopt-flags-hook nil
852 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
854 :group
'verilog-mode-auto
)
856 (defvar verilog-imenu-generic-expression
857 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
858 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
859 "Imenu expression for Verilog-mode. See `imenu-generic-expression'.")
862 ;; provide a verilog-header function.
863 ;; Customization variables:
865 (defvar verilog-date-scientific-format nil
866 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
867 If nil, in European format (e.g. 17.09.1997). The brain-dead American
868 format (e.g. 09/17/1997) is not supported.")
870 (defvar verilog-company nil
871 "*Default name of Company for verilog header.
872 If set will become buffer local.")
874 (defvar verilog-project nil
875 "*Default name of Project for verilog header.
876 If set will become buffer local.")
878 (defvar verilog-mode-map
879 (let ((map (make-sparse-keymap)))
880 (define-key map
";" 'electric-verilog-semi
)
881 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
882 (define-key map
":" 'electric-verilog-colon
)
883 ;;(define-key map "=" 'electric-verilog-equal)
884 (define-key map
"\`" 'electric-verilog-tick
)
885 (define-key map
"\t" 'electric-verilog-tab
)
886 (define-key map
"\r" 'electric-verilog-terminate-line
)
887 ;; backspace/delete key bindings
888 (define-key map
[backspace] 'backward-delete-char-untabify)
889 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
890 (define-key map [delete] 'delete-char)
891 (define-key map [(meta delete)] 'kill-word))
892 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
893 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
894 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
895 (define-key map "\M-\t" 'verilog-complete-word)
896 (define-key map "\M-?" 'verilog-show-completions)
897 (define-key map [(meta control h)] 'verilog-mark-defun)
898 (define-key map "\C-c\`" 'verilog-lint-off)
899 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
900 (define-key map "\C-c\C-r" 'verilog-label-be)
901 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
902 (define-key map "\C-c=" 'verilog-pretty-expr)
903 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
904 (define-key map "\M-*" 'verilog-star-comment)
905 (define-key map "\C-c\C-c" 'verilog-comment-region)
906 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
907 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
908 (define-key map "\M-\C-e" 'verilog-end-of-defun)
909 (define-key map "\C-c\C-d" 'verilog-goto-defun)
910 (define-key map "\C-c\C-k" 'verilog-delete-auto)
911 (define-key map "\C-c\C-a" 'verilog-auto)
912 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
913 (define-key map "\C-c\C-z" 'verilog-inject-auto)
914 (define-key map "\C-c\C-e" 'verilog-expand-vector)
915 (define-key map "\C-c\C-h" 'verilog-header)
917 "Keymap used in Verilog mode.")
920 (defvar verilog-xemacs-menu
922 ("Choose Compilation Action"
925 (setq verilog-tool nil)
926 (verilog-set-compile-command))
928 :selected (equal verilog-tool nil)]
931 (setq verilog-tool 'verilog-linter)
932 (verilog-set-compile-command))
934 :selected (equal verilog-tool `verilog-linter)]
937 (setq verilog-tool 'verilog-coverage)
938 (verilog-set-compile-command))
940 :selected (equal verilog-tool `verilog-coverage)]
943 (setq verilog-tool 'verilog-simulator)
944 (verilog-set-compile-command))
946 :selected (equal verilog-tool `verilog-simulator)]
949 (setq verilog-tool 'verilog-compiler)
950 (verilog-set-compile-command))
952 :selected (equal verilog-tool `verilog-compiler)]
955 ["Beginning of function" verilog-beg-of-defun t]
956 ["End of function" verilog-end-of-defun t]
957 ["Mark function" verilog-mark-defun t]
958 ["Goto function/module" verilog-goto-defun t]
959 ["Move to beginning of block" electric-verilog-backward-sexp t]
960 ["Move to end of block" electric-verilog-forward-sexp t]
963 ["Comment Region" verilog-comment-region t]
964 ["UnComment Region" verilog-uncomment-region t]
965 ["Multi-line comment insert" verilog-star-comment t]
966 ["Lint error to comment" verilog-lint-off t]
969 ["Compile" compile t]
970 ["AUTO, Save, Compile" verilog-auto-save-compile t]
971 ["Next Compile Error" next-error t]
972 ["Ignore Lint Warning at point" verilog-lint-off t]
974 ["Line up declarations around point" verilog-pretty-declarations t]
975 ["Line up equations around point" verilog-pretty-expr t]
976 ["Redo/insert comments on every end" verilog-label-be t]
977 ["Expand [x:y] vector line" verilog-expand-vector t]
978 ["Insert begin-end block" verilog-insert-block t]
979 ["Complete word" verilog-complete-word t]
981 ["Recompute AUTOs" verilog-auto t]
982 ["Kill AUTOs" verilog-delete-auto t]
983 ["Inject AUTOs" verilog-inject-auto t]
985 ["AUTO General" (describe-function 'verilog-auto) t]
986 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) t]
987 ["AUTO Library Path" (describe-variable 'verilog-library-directories) t]
988 ["AUTO Library Files" (describe-variable 'verilog-library-files) t]
989 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t]
990 ["AUTO `define Reading" (describe-function 'verilog-read-defines) t]
991 ["AUTO `include Reading" (describe-function 'verilog-read-includes) t]
992 ["AUTOARG" (describe-function 'verilog-auto-arg) t]
993 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t]
994 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t]
995 ["AUTOINOUT" (describe-function 'verilog-auto-inout) t]
996 ["AUTOINPUT" (describe-function 'verilog-auto-input) t]
997 ["AUTOINST" (describe-function 'verilog-auto-inst) t]
998 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) t]
999 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t]
1000 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t]
1001 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t]
1002 ["AUTOREG" (describe-function 'verilog-auto-reg) t]
1003 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t]
1004 ["AUTORESET" (describe-function 'verilog-auto-reset) t]
1005 ["AUTOSENSE" (describe-function 'verilog-auto-sense) t]
1006 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t]
1007 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) t]
1008 ["AUTOWIRE" (describe-function 'verilog-auto-wire) t]
1011 ["Submit bug report" verilog-submit-bug-report t]
1012 ["Version and FAQ" verilog-faq t]
1013 ["Customize Verilog Mode..." verilog-customize t]
1014 ["Customize Verilog Fonts & Colors" verilog-font-customize t]
1016 "Emacs menu for VERILOG mode."
1018 (defvar verilog-statement-menu
1020 ["Header" verilog-sk-header t]
1021 ["Comment" verilog-sk-comment t]
1023 ["Module" verilog-sk-module t]
1024 ["Primitive" verilog-sk-primitive t]
1026 ["Input" verilog-sk-input t]
1027 ["Output" verilog-sk-output t]
1028 ["Inout" verilog-sk-inout t]
1029 ["Wire" verilog-sk-wire t]
1030 ["Reg" verilog-sk-reg t]
1031 ["Define thing under point as a register" verilog-sk-define-signal t]
1033 ["Initial" verilog-sk-initial t]
1034 ["Always" verilog-sk-always t]
1035 ["Function" verilog-sk-function t]
1036 ["Task" verilog-sk-task t]
1037 ["Specify" verilog-sk-specify t]
1038 ["Generate" verilog-sk-generate t]
1040 ["Begin" verilog-sk-begin t]
1041 ["If" verilog-sk-if t]
1042 ["(if) else" verilog-sk-else-if t]
1043 ["For" verilog-sk-for t]
1044 ["While" verilog-sk-while t]
1045 ["Fork" verilog-sk-fork t]
1046 ["Repeat" verilog-sk-repeat t]
1047 ["Case" verilog-sk-case t]
1048 ["Casex" verilog-sk-casex t]
1049 ["Casez" verilog-sk-casez t]
1051 "Menu for statement templates in Verilog."
1054 (easy-menu-define verilog-menu verilog-mode-map "Menu for Verilog mode"
1055 verilog-xemacs-menu)
1056 (easy-menu-define verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1057 verilog-statement-menu)
1059 (defvar verilog-mode-abbrev-table nil
1060 "Abbrev table in use in Verilog-mode buffers.")
1062 (define-abbrev-table 'verilog-mode-abbrev-table ())
1068 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1069 "Replace occurrences of FROM-STRING with TO-STRING.
1070 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1071 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1072 will break, as the o's continuously replace. xa -> x works ok though."
1073 ;; Hopefully soon to a emacs built-in
1075 (while (string-match from-string string start)
1076 (setq string (replace-match to-string fixedcase literal string)
1077 start (min (length string) (match-end 0))))
1080 (defsubst verilog-string-remove-spaces (string)
1081 "Remove spaces surrounding STRING."
1083 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1084 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1087 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1088 ; checkdoc-params: (REGEXP BOUND NOERROR)
1089 "Like `re-search-forward', but skips over match in comments or strings."
1090 (store-match-data '(nil nil))
1092 (re-search-forward REGEXP BOUND NOERROR)
1093 (and (verilog-skip-forward-comment-or-string)
1095 (store-match-data '(nil nil))
1102 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1103 ; checkdoc-params: (REGEXP BOUND NOERROR)
1104 "Like `re-search-backward', but skips over match in comments or strings."
1105 (store-match-data '(nil nil))
1107 (re-search-backward REGEXP BOUND NOERROR)
1108 (and (verilog-skip-backward-comment-or-string)
1110 (store-match-data '(nil nil))
1117 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1118 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1119 but trashes match data and is faster for REGEXP that doesn't match often.
1120 This may at some point use text properties to ignore comments,
1121 so there may be a large up front penalty for the first search."
1123 (while (and (not pt)
1124 (re-search-forward regexp bound noerror))
1125 (if (not (verilog-inside-comment-p))
1126 (setq pt (match-end 0))))
1129 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1130 ; checkdoc-params: (REGEXP BOUND NOERROR)
1131 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1132 but trashes match data and is faster for REGEXP that doesn't match often.
1133 This may at some point use text properties to ignore comments,
1134 so there may be a large up front penalty for the first search."
1136 (while (and (not pt)
1137 (re-search-backward regexp bound noerror))
1138 (if (not (verilog-inside-comment-p))
1139 (setq pt (match-end 0))))
1142 (defsubst verilog-get-beg-of-line (&optional arg)
1144 (beginning-of-line arg)
1147 (defsubst verilog-get-end-of-line (&optional arg)
1152 (defsubst verilog-within-string ()
1154 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1156 ;; compilation program
1157 (defun verilog-set-compile-command ()
1158 "Function to compute shell command to compile verilog.
1160 This reads `verilog-tool' and sets `compile-command'. This specifies the
1161 program that executes when you type \\[compile] or
1162 \\[verilog-auto-save-compile].
1164 By default `verilog-tool' uses a Makefile if one exists in the current
1165 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
1166 `verilog-simulator', or `verilog-compiler' variables, as selected with the
1167 Verilog -> \"Choose Compilation Action\" menu.
1169 You should set `verilog-tool' or the other variables to the path and
1170 arguments for your Verilog simulator. For example:
1173 \"(cd /tmp; surecov %s)\".
1175 In the former case, the path to the current buffer is concat'ed to the
1176 value of `verilog-tool'; in the later, the path to the current buffer is
1177 substituted for the %s.
1179 Where __FILE__ appears in the string, the buffer-file-name of the current
1180 buffer, without the directory portion, will be substituted."
1183 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1184 (file-exists-p "Makefile"))
1185 (make-local-variable 'compile-command)
1186 (setq compile-command "make "))
1188 (make-local-variable 'compile-command)
1189 (setq compile-command
1191 (if (string-match "%s" (eval verilog-tool))
1192 (format (eval verilog-tool) (or buffer-file-name ""))
1193 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1195 (verilog-modify-compile-command))
1197 (defun verilog-modify-compile-command ()
1198 "Replace meta-information in `compile-command'.
1199 Where __FILE__ appears in the string, the current buffer's file-name,
1200 without the directory portion, will be substituted."
1202 (stringp compile-command)
1203 (string-match "\\b__FILE__\\b" compile-command))
1204 (make-local-variable 'compile-command)
1205 (setq compile-command
1206 (verilog-string-replace-matches
1207 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
1208 t t compile-command))))
1210 (defun verilog-error-regexp-add ()
1211 "Add the messages to the `compilation-error-regexp-alist'.
1212 Called by `compilation-mode-hook'. This allows \\[next-error] to find the errors."
1213 (if (not verilog-error-regexp-add-didit)
1215 (setq verilog-error-regexp-add-didit t)
1216 (setq-default compilation-error-regexp-alist
1217 (append verilog-error-regexp
1218 (default-value 'compilation-error-regexp-alist)))
1219 ;; Could be buffer local at this point; maybe also in let; change all three
1220 (setq compilation-error-regexp-alist (default-value 'compilation-error-regexp-alist))
1221 (set (make-local-variable 'compilation-error-regexp-alist)
1222 (default-value 'compilation-error-regexp-alist))
1225 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
1227 (defconst verilog-directive-re
1228 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
1229 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1230 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1231 ;; "`time_scale" "`undef" "`while"
1232 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
1234 (defconst verilog-directive-begin
1235 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1237 (defconst verilog-directive-middle
1238 "\\<`\\(else\\|default\\|case\\)\\>")
1240 (defconst verilog-directive-end
1241 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1243 (defconst verilog-directive-re-1
1244 (concat "[ \t]*" verilog-directive-re))
1247 ;; Regular expressions used to calculate indent, etc.
1249 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
1250 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
1258 (defconst verilog-no-indent-begin-re
1259 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1261 (defconst verilog-ends-re
1262 ;; Parenthesis indicate type of keyword found
1264 "\\(\\<else\\>\\)\\|" ; 1
1265 "\\(\\<if\\>\\)\\|" ; 2
1266 "\\(\\<end\\>\\)\\|" ; 3
1267 "\\(\\<endcase\\>\\)\\|" ; 4
1268 "\\(\\<endfunction\\>\\)\\|" ; 5
1269 "\\(\\<endtask\\>\\)\\|" ; 6
1270 "\\(\\<endspecify\\>\\)\\|" ; 7
1271 "\\(\\<endtable\\>\\)\\|" ; 8
1272 "\\(\\<endgenerate\\>\\)\\|" ; 9
1273 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
1274 "\\(\\<endclass\\>\\)\\|" ; 11
1275 "\\(\\<endgroup\\>\\)" ; 12
1278 (defconst verilog-auto-end-comment-lines-re
1279 ;; Matches to names in this list cause auto-end-commentation
1281 verilog-directive-re "\\)\\|\\("
1283 (verilog-regexp-words
1311 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1312 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1313 (defconst verilog-end-block-ordered-re
1314 ;; Parenthesis indicate type of keyword found
1315 (concat "\\(\\<endcase\\>\\)\\|" ; 1
1316 "\\(\\<end\\>\\)\\|" ; 2
1317 "\\(\\<end" ; 3, but not used
1318 "\\(" ; 4, but not used
1319 "\\(function\\)\\|" ; 5
1321 "\\(module\\)\\|" ; 7
1322 "\\(primitive\\)\\|" ; 8
1323 "\\(interface\\)\\|" ; 9
1324 "\\(package\\)\\|" ; 10
1325 "\\(class\\)\\|" ; 11
1326 "\\(group\\)\\|" ; 12
1327 "\\(program\\)\\|" ; 13
1328 "\\(sequence\\)\\|" ; 14
1329 "\\(clocking\\)\\|" ; 15
1331 (defconst verilog-end-block-re
1333 (verilog-regexp-words
1335 `("end" ;; closes begin
1336 "endcase" ;; closes any of case, casex casez or randcase
1337 "join" "join_any" "join_none" ;; closes fork
1355 (defconst verilog-endcomment-reason-re
1356 ;; Parenthesis indicate type of keyword found
1358 "\\(\\<fork\\>\\)\\|"
1359 "\\(\\<begin\\>\\)\\|"
1361 "\\(\\<clocking\\>\\)\\|"
1362 "\\(\\<else\\>\\)\\|"
1363 "\\(\\<end\\>.*\\<else\\>\\)\\|"
1364 "\\(\\<task\\>\\)\\|"
1365 "\\(\\<function\\>\\)\\|"
1366 "\\(\\<initial\\>\\)\\|"
1367 "\\(\\<interface\\>\\)\\|"
1368 "\\(\\<package\\>\\)\\|"
1369 "\\(\\<final\\>\\)\\|"
1370 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
1371 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
1372 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
1373 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
1375 "\\(\\<while\\>\\)\\|"
1376 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
1377 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
1380 (defconst verilog-named-block-re "begin[ \t]*:")
1382 ;; These words begin a block which can occur inside a module which should be indented,
1383 ;; and closed with the respective word from the end-block list
1385 (defconst verilog-beg-block-re
1387 (verilog-regexp-words
1389 "case" "casex" "casez" "randcase"
1399 ;; These are the same words, in a specific order in the regular
1400 ;; expression so that matching will work nicely for
1401 ;; verilog-forward-sexp and verilog-calc-indent
1403 (defconst verilog-beg-block-re-ordered
1406 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2
1407 ;; "\\|\\(randcase\\|case[xz]?\\)" ; 2
1411 "\\|\\(specify\\)" ;6
1412 "\\|\\(function\\)" ;7
1414 "\\|\\(generate\\)" ;9
1415 "\\|\\(covergroup\\)" ;10
1416 "\\|\\(property\\)" ;11
1417 "\\|\\(\\(rand\\)?sequence\\)" ;12
1418 "\\|\\(clocking\\)" ;13
1421 (defconst verilog-end-block-ordered-rry
1422 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1423 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
1424 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1425 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
1426 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
1427 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
1428 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
1429 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
1430 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
1431 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
1432 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
1433 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
1434 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
1437 (defconst verilog-nameable-item-re
1439 (verilog-regexp-words
1442 "join" "join_any" "join_none"
1459 (defconst verilog-declaration-opener
1461 (verilog-regexp-words
1462 `("module" "begin" "task" "function"))))
1464 (defconst verilog-declaration-prefix-re
1466 (verilog-regexp-words
1469 "inout" "input" "output" "ref"
1471 "const" "static" "protected" "local"
1473 "localparam" "parameter" "var"
1477 (defconst verilog-declaration-core-re
1479 (verilog-regexp-words
1481 ;; integer_atom_type
1482 "byte" "shortint" "int" "longint" "integer" "time"
1483 ;; integer_vector_type
1486 "shortreal" "real" "realtime"
1488 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
1490 "string" "event" "chandle" "virtual" "enum" "genvar"
1493 "mailbox" "semaphore"
1495 (defconst verilog-declaration-re
1496 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
1497 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
1498 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
1499 (defconst verilog-optional-signed-range-re
1501 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
1502 (defconst verilog-macroexp-re "`\\sw+")
1504 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
1505 (defconst verilog-declaration-re-2-no-macro
1506 (concat "\\s-*" verilog-declaration-re
1507 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1509 (defconst verilog-declaration-re-2-macro
1510 (concat "\\s-*" verilog-declaration-re
1511 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1512 "\\|\\(" verilog-macroexp-re "\\)"
1514 (defconst verilog-declaration-re-1-macro
1515 (concat "^" verilog-declaration-re-2-macro))
1517 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
1519 (defconst verilog-defun-re
1520 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
1521 (defconst verilog-end-defun-re
1522 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
1523 (defconst verilog-zero-indent-re
1524 (concat verilog-defun-re "\\|" verilog-end-defun-re))
1526 (defconst verilog-behavioral-block-beg-re
1527 (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|"
1528 "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)"))
1530 (defconst verilog-indent-re
1532 (verilog-regexp-words
1535 "always" "always_latch" "always_ff" "always_comb"
1537 ; "unique" "priority"
1538 "case" "casex" "casez" "randcase" "endcase"
1540 "clocking" "endclocking"
1541 "config" "endconfig"
1542 "covergroup" "endgroup"
1543 "fork" "join" "join_any" "join_none"
1544 "function" "endfunction"
1546 "generate" "endgenerate"
1548 "interface" "endinterface"
1549 "module" "macromodule" "endmodule"
1550 "package" "endpackage"
1551 "primitive" "endprimative"
1552 "program" "endprogram"
1553 "property" "endproperty"
1554 "sequence" "randsequence" "endsequence"
1555 "specify" "endspecify"
1561 "`if" "`ifdef" "`ifndef" "`else" "`endif"
1562 "`while" "`endwhile"
1567 "`protect" "`endprotect"
1568 "`switch" "`endswitch"
1573 (defconst verilog-defun-level-re
1575 (verilog-regexp-words
1577 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
1578 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
1581 (defconst verilog-defun-level-not-generate-re
1583 (verilog-regexp-words
1585 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
1587 (defconst verilog-cpp-level-re
1589 (verilog-regexp-words
1591 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
1593 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
1594 (defconst verilog-extended-complete-re
1595 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
1596 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
1597 "\\|" verilog-extended-case-re ))
1598 (defconst verilog-basic-complete-re
1600 (verilog-regexp-words
1602 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
1603 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
1604 "if" "for" "forever" "foreach" "else" "parameter" "do"
1606 (defconst verilog-complete-reg
1608 verilog-extended-complete-re
1610 verilog-basic-complete-re))
1612 (defconst verilog-end-statement-re
1613 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
1614 verilog-end-block-re "\\)"))
1616 (defconst verilog-endcase-re
1617 (concat verilog-case-re "\\|"
1622 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
1623 "String used to mark beginning of excluded text.")
1624 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
1625 "String used to mark end of excluded text.")
1626 (defconst verilog-preprocessor-re
1628 (verilog-regexp-words
1630 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
1633 (defconst verilog-keywords
1634 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
1635 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1636 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1637 "`time_scale" "`undef" "`while"
1639 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
1640 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
1641 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
1642 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
1643 "config" "const" "constraint" "context" "continue" "cover"
1644 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
1645 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
1646 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
1647 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
1648 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
1649 "endtask" "enum" "event" "expect" "export" "extends" "extern"
1650 "final" "first_match" "for" "force" "foreach" "forever" "fork"
1651 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
1652 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
1653 "include" "initial" "inout" "input" "inside" "instance" "int"
1654 "integer" "interface" "intersect" "join" "join_any" "join_none"
1655 "large" "liblist" "library" "local" "localparam" "logic"
1656 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
1657 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
1658 "notif0" "notif1" "null" "or" "output" "package" "packed"
1659 "parameter" "pmos" "posedge" "primitive" "priority" "program"
1660 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
1661 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1662 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
1663 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
1664 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
1665 "showcancelled" "signed" "small" "solve" "specify" "specparam"
1666 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
1667 "supply1" "table" "tagged" "task" "this" "throughout" "time"
1668 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
1669 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
1670 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
1671 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
1672 "wire" "with" "within" "wor" "xnor" "xor"
1674 "List of Verilog keywords.")
1677 (defconst verilog-emacs-features
1678 ;; Documentation at the bottom
1679 (let ((major (and (boundp 'emacs-major-version)
1680 emacs-major-version))
1681 (minor (and (boundp 'emacs-minor-version)
1682 emacs-minor-version))
1683 flavor comments flock-syntax)
1684 ;; figure out version numbers if not already discovered
1685 (and (or (not major) (not minor))
1686 (string-match "\\([0-9]+\\).\\([0-9]+\\)" emacs-version)
1687 (setq major (string-to-int (substring emacs-version
1690 minor (string-to-int (substring emacs-version
1693 (if (not (and major minor))
1694 (error "Cannot figure out the major and minor version numbers"))
1695 ;; calculate the major version
1697 ((= major 4) (setq major 'v18)) ;Epoch 4
1698 ((= major 18) (setq major 'v18)) ;Emacs 18
1699 ((= major 19) (setq major 'v19 ;Emacs 19
1700 flavor (if (or (string-match "Lucid" emacs-version)
1701 (string-match "XEmacs" emacs-version))
1703 ((> major 19) (setq major 'v20
1704 flavor (if (or (string-match "Lucid" emacs-version)
1705 (string-match "XEmacs" emacs-version))
1708 (t (error "Cannot recognize major version number: %s" major)))
1709 ;; XEmacs 19 uses 8-bit modify-syntax-entry flags, as do all
1710 ;; patched Emacs 19, Emacs 18, Epoch 4's. Only Emacs 19 uses a
1711 ;; 1-bit flag. Let's be as smart as we can about figuring this
1713 (if (or (eq major 'v20) (eq major 'v19))
1714 (let ((table (copy-syntax-table)))
1715 (modify-syntax-entry ?a ". 12345678" table)
1717 ;; XEmacs pre 20 and Emacs pre 19.30 use vectors for syntax tables.
1719 (if (= (logand (lsh (aref table ?a) -16) 255) 255)
1720 (setq comments '8-bit)
1721 (setq comments '1-bit)))
1722 ;; XEmacs 20 is known to be 8-bit
1723 ((eq flavor 'XEmacs) (setq comments '8-bit))
1724 ;; Emacs 19.30 and beyond are known to be 1-bit
1725 ((eq flavor 'FSF) (setq comments '1-bit))
1726 ;; Don't know what this is
1727 (t (error "Couldn't figure out syntax table format"))
1729 ;; Emacs 18 has no support for dual comments
1730 (setq comments 'no-dual-comments))
1731 ;; determine whether to use old or new font lock syntax
1732 ;; We can assume 8-bit syntax table emacsen support new syntax, otherwise
1733 ;; look for version > 19.30
1735 (if (or (equal comments '8-bit)
1737 (and (equal major 'v19) (> minor 30)))
1738 'flock-syntax-after-1930
1739 'flock-syntax-before-1930))
1740 ;; lets do some minimal sanity checking.
1742 ;; Emacs before 19.6 had bugs
1743 (and (eq major 'v19) (eq flavor 'XEmacs) (< minor 6))
1744 ;; Emacs 19 before 19.21 has known bugs
1745 (and (eq major 'v19) (eq flavor 'FSF) (< minor 21))
1747 (with-output-to-temp-buffer "*verilog-mode warnings*"
1749 "The version of Emacs that you are running, %s,
1750 has known bugs in its syntax parsing routines which will affect the
1751 performance of verilog-mode. You should strongly consider upgrading to the
1752 latest available version. verilog-mode may continue to work, after a
1753 fashion, but strange indentation errors could be encountered."
1755 ;; Emacs 18, with no patch is not too good
1756 (if (and (eq major 'v18) (eq comments 'no-dual-comments))
1757 (with-output-to-temp-buffer "*verilog-mode warnings*"
1759 "The version of Emacs 18 you are running, %s,
1760 has known deficiencies in its ability to handle the dual verilog
1761 \(and C++) comments, (e.g. the // and /* */ comments). This will
1762 not be much of a problem for you if you only use the /* */ comments,
1763 but you really should strongly consider upgrading to one of the latest
1764 Emacs 19's. In Emacs 18, you may also experience performance degradations.
1765 Emacs 19 has some new built-in routines which will speed things up for you.
1766 Because of these inherent problems, verilog-mode is not supported
1769 ;; Emacs 18 with the syntax patches are no longer supported
1770 (if (and (eq major 'v18) (not (eq comments 'no-dual-comments)))
1771 (with-output-to-temp-buffer "*verilog-mode warnings*"
1773 "You are running a syntax patched Emacs 18 variant. While this should
1774 work for you, you may want to consider upgrading to Emacs 19.
1775 The syntax patches are no longer supported either for verilog-mode."))))
1776 (list major comments flock-syntax))
1777 "A list of features extant in the Emacs you are using.
1778 There are many flavors of Emacs out there, each with different
1779 features supporting those needed by `verilog-mode'. Here's the current
1780 supported list, along with the values for this variable:
1782 Vanilla Emacs 18/Epoch 4: (v18 no-dual-comments flock-syntax-before-1930)
1783 Emacs 18/Epoch 4 (patch2): (v18 8-bit flock-syntax-after-1930)
1784 XEmacs (formerly Lucid) 19: (v19 8-bit flock-syntax-after-1930)
1785 XEmacs 20: (v20 8-bit flock-syntax-after-1930)
1786 Emacs 19.1-19.30: (v19 8-bit flock-syntax-before-1930)
1787 Emacs 19.31-19.xx: (v19 8-bit flock-syntax-after-1930)
1788 Emacs20 : (v20 1-bit flock-syntax-after-1930).")
1790 (defconst verilog-comment-start-regexp "//\\|/\\*"
1791 "Dual comment value for `comment-start-regexp'.")
1793 (defun verilog-populate-syntax-table (table)
1794 "Populate the syntax TABLE."
1795 (modify-syntax-entry ?\\ "\\" table)
1796 (modify-syntax-entry ?+ "." table)
1797 (modify-syntax-entry ?- "." table)
1798 (modify-syntax-entry ?= "." table)
1799 (modify-syntax-entry ?% "." table)
1800 (modify-syntax-entry ?< "." table)
1801 (modify-syntax-entry ?> "." table)
1802 (modify-syntax-entry ?& "." table)
1803 (modify-syntax-entry ?| "." table)
1804 (modify-syntax-entry ?` "w" table)
1805 (modify-syntax-entry ?_ "w" table)
1806 (modify-syntax-entry ?\' "." table)
1809 (defun verilog-setup-dual-comments (table)
1810 "Set up TABLE to handle block and line style comments."
1812 ((memq '8-bit verilog-emacs-features)
1813 ;; XEmacs (formerly Lucid) has the best implementation
1814 (modify-syntax-entry ?/ ". 1456" table)
1815 (modify-syntax-entry ?* ". 23" table)
1816 (modify-syntax-entry ?\n "> b" table)
1818 ((memq '1-bit verilog-emacs-features)
1819 ;; Emacs 19 does things differently, but we can work with it
1820 (modify-syntax-entry ?/ ". 124b" table)
1821 (modify-syntax-entry ?* ". 23" table)
1822 (modify-syntax-entry ?\n "> b" table)
1826 (defvar verilog-mode-syntax-table nil
1827 "Syntax table used in `verilog-mode' buffers.")
1829 (defconst verilog-font-lock-keywords nil
1830 "Default highlighting for Verilog mode.")
1832 (defconst verilog-font-lock-keywords-1 nil
1833 "Subdued level highlighting for Verilog mode.")
1835 (defconst verilog-font-lock-keywords-2 nil
1836 "Medium level highlighting for Verilog mode.
1837 See also `verilog-font-lock-extra-types'.")
1839 (defconst verilog-font-lock-keywords-3 nil
1840 "Gaudy level highlighting for Verilog mode.
1841 See also `verilog-font-lock-extra-types'.")
1842 (defvar verilog-font-lock-translate-off-face
1843 'verilog-font-lock-translate-off-face
1844 "Font to use for translated off regions.")
1845 (defface verilog-font-lock-translate-off-face
1848 (:background "gray90" :italic t ))
1851 (:background "gray10" :italic t ))
1852 (((class grayscale) (background light))
1853 (:foreground "DimGray" :italic t))
1854 (((class grayscale) (background dark))
1855 (:foreground "LightGray" :italic t))
1857 "Font lock mode face used to background highlight translate-off regions."
1858 :group 'font-lock-highlighting-faces)
1860 (defvar verilog-font-lock-p1800-face
1861 'verilog-font-lock-p1800-face
1862 "Font to use for p1800 keywords.")
1863 (defface verilog-font-lock-p1800-face
1866 (:foreground "DarkOrange3" :bold t ))
1869 (:foreground "orange1" :bold t ))
1871 "Font lock mode face used to highlight P1800 keywords."
1872 :group 'font-lock-highlighting-faces)
1874 (defvar verilog-font-lock-ams-face
1875 'verilog-font-lock-ams-face
1876 "Font to use for Analog/Mixed Signal keywords.")
1877 (defface verilog-font-lock-ams-face
1880 (:foreground "Purple" :bold t ))
1883 (:foreground "orange1" :bold t ))
1885 "Font lock mode face used to highlight AMS keywords."
1886 :group 'font-lock-highlighting-faces)
1888 (let* ((verilog-type-font-keywords
1892 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
1893 "event" "genvar" "inout" "input" "integer" "localparam"
1894 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
1895 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
1896 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
1897 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
1898 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
1899 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
1900 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
1903 (verilog-pragma-keywords
1906 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
1909 (verilog-p1800-keywords
1912 '("alias" "assert" "assume" "automatic" "before" "bind"
1913 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
1914 "clocking" "config" "const" "constraint" "context" "continue"
1915 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
1916 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
1917 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
1918 "expect" "export" "extends" "extern" "first_match" "foreach"
1919 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
1920 "illegal_bins" "import" "incdir" "include" "inside" "instance"
1921 "int" "intersect" "large" "liblist" "library" "local" "longint"
1922 "matches" "medium" "modport" "new" "noshowcancelled" "null"
1923 "packed" "program" "property" "protected" "pull0" "pull1"
1924 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1925 "randcase" "randsequence" "ref" "release" "return" "scalared"
1926 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
1927 "specparam" "static" "string" "strong0" "strong1" "struct"
1928 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
1929 "type" "union" "unsigned" "use" "var" "virtual" "void"
1930 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
1933 (verilog-ams-keywords
1936 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
1937 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
1938 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
1939 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
1940 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
1941 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
1942 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
1943 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
1944 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
1945 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
1946 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
1948 (verilog-font-keywords
1952 "assign" "begin" "case" "casex" "casez" "randcase" "deassign"
1953 "default" "disable" "else" "end" "endcase" "endfunction"
1954 "endgenerate" "endinterface" "endmodule" "endprimitive"
1955 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
1956 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
1957 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
1958 "package" "endpackage" "always" "always_comb" "always_ff"
1959 "always_latch" "posedge" "primitive" "priority" "release"
1960 "repeat" "specify" "table" "task" "unique" "wait" "while"
1961 "class" "program" "endclass" "endprogram"
1964 (setq verilog-font-lock-keywords
1966 ;; Fontify all builtin keywords
1967 (concat "\\<\\(" verilog-font-keywords "\\|"
1968 ;; And user/system tasks and functions
1969 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
1971 ;; Fontify all types
1972 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
1973 'font-lock-type-face)
1974 ;; Fontify IEEE-P1800 keywords appropriately
1975 (if verilog-highlight-p1800-keywords
1976 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
1977 'verilog-font-lock-p1800-face)
1978 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
1979 'font-lock-type-face))
1980 ;; Fontify Verilog-AMS keywords
1981 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
1982 'verilog-font-lock-ams-face)
1985 (setq verilog-font-lock-keywords-1
1986 (append verilog-font-lock-keywords
1988 ;; Fontify module definitions
1990 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
1991 '(1 font-lock-keyword-face)
1992 '(3 font-lock-function-name-face 'prepend))
1993 ;; Fontify function definitions
1995 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
1996 '(1 font-lock-keyword-face)
1997 '(3 font-lock-reference-face prepend)
1999 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
2000 (1 font-lock-keyword-face)
2001 (2 font-lock-reference-face append)
2003 '("\\<function\\>\\s-+\\(\\sw+\\)"
2004 1 'font-lock-reference-face append)
2007 (setq verilog-font-lock-keywords-2
2008 (append verilog-font-lock-keywords-1
2011 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
2012 ;; Fontify escaped names
2013 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
2014 ;; Fontify macro definitions/ uses
2015 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
2016 'font-lock-preprocessor-face
2017 'font-lock-type-face))
2018 ;; Fontify delays/numbers
2019 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2020 0 font-lock-type-face append)
2021 ;; Fontify instantiation names
2022 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
2026 (setq verilog-font-lock-keywords-3
2027 (append verilog-font-lock-keywords-2
2028 (when verilog-highlight-translate-off
2030 ;; Fontify things in translate off regions
2031 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
2038 (defun verilog-inside-comment-p ()
2039 "Check if point inside a nested comment."
2041 (let ((st-point (point)) hitbeg)
2042 (or (search-backward "//" (verilog-get-beg-of-line) t)
2044 ;; This is for tricky case //*, we keep searching if /* is proceeded by // on same line
2045 (while (and (setq hitbeg (search-backward "/*" nil t))
2046 (progn (forward-char 1) (search-backward "//" (verilog-get-beg-of-line) t))))
2048 (not (search-forward "*/" st-point t)))))))
2050 (defun verilog-declaration-end ()
2051 (search-forward ";"))
2053 (defun verilog-point-text (&optional pointnum)
2054 "Return text describing where POINTNUM or current point is (for errors).
2055 Use filename, if current buffer being edited shorten to just buffer name."
2056 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2060 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2062 (defun electric-verilog-backward-sexp ()
2063 "Move backward over a sexp."
2065 ;; before that see if we are in a comment
2066 (verilog-backward-sexp)
2068 (defun electric-verilog-forward-sexp ()
2069 "Move backward over a sexp."
2071 ;; before that see if we are in a comment
2072 (verilog-forward-sexp)
2074 ;;;used by hs-minor-mode
2075 (defun verilog-forward-sexp-function (arg)
2077 (verilog-backward-sexp)
2078 (verilog-forward-sexp)))
2081 (defun verilog-backward-sexp ()
2087 (if (not (looking-at "\\<"))
2090 ((verilog-skip-backward-comment-or-string)
2092 ((looking-at "\\<else\\>")
2094 verilog-end-block-re
2095 "\\|\\(\\<else\\>\\)"
2098 (while (and (not found)
2099 (verilog-re-search-backward reg nil 'move))
2101 ((match-end 1) ; matched verilog-end-block-re
2102 ; try to leap back to matching outward block by striding across
2103 ; indent level changing tokens then immediately
2104 ; previous line governs indentation.
2105 (verilog-leap-to-head))
2106 ((match-end 2) ; else, we're in deep
2107 (setq elsec (1+ elsec)))
2108 ((match-end 3) ; found it
2109 (setq elsec (1- elsec))
2111 ;; Now previous line describes syntax
2117 ((looking-at verilog-end-block-re)
2118 (verilog-leap-to-head))
2119 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2122 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
2124 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
2126 (verilog-re-search-backward "\\<class\\>" nil 'move))
2128 (verilog-re-search-backward "\\<program\\>" nil 'move))
2130 (verilog-re-search-backward "\\<interface\\>" nil 'move))
2132 (verilog-re-search-backward "\\<package\\>" nil 'move))
2135 (backward-sexp 1))))
2142 (defun verilog-forward-sexp ()
2146 (if (not (looking-at "\\<"))
2149 ((verilog-skip-forward-comment-or-string)
2150 (verilog-forward-syntactic-ws)
2152 ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
2154 ((match-end 1) ; end
2155 ;; Search forward for matching begin
2156 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2157 ((match-end 2) ; endcase
2158 ;; Search forward for matching case
2159 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2161 ((match-end 3) ; join
2162 ;; Search forward for matching fork
2163 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
2164 ((match-end 4) ; endclass
2165 ;; Search forward for matching class
2166 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2167 ((match-end 5) ; endtable
2168 ;; Search forward for matching table
2169 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
2170 ((match-end 6) ; endspecify
2171 ;; Search forward for matching specify
2172 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2173 ((match-end 7) ; endfunction
2174 ;; Search forward for matching function
2175 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
2176 ((match-end 8) ; endtask
2177 ;; Search forward for matching task
2178 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
2179 ((match-end 9) ; endgenerate
2180 ;; Search forward for matching generate
2181 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2182 ((match-end 10) ; endgroup
2183 ;; Search forward for matching covergroup
2184 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2185 ((match-end 11) ; endproperty
2186 ;; Search forward for matching property
2187 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2188 ((match-end 12) ; endsequence
2189 ;; Search forward for matching sequence
2190 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2191 (setq md 3) ; 3 to get to endsequence in the reg above
2193 ((match-end 13) ; endclocking
2194 ;; Search forward for matching clocking
2195 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))
2197 (if (forward-word 1)
2200 (while (verilog-re-search-forward reg nil 'move)
2202 ((match-end md) ; the closer in reg, so we are climbing out
2203 (setq nest (1- nest))
2204 (if (= 0 nest) ; we are out!
2206 ((match-end 1) ; the opener in reg, so we are deeper now
2207 (setq nest (1+ nest)))))
2210 ((looking-at (concat
2211 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2212 "\\(\\<primitive\\>\\)\\|"
2213 "\\(\\<class\\>\\)\\|"
2214 "\\(\\<program\\>\\)\\|"
2215 "\\(\\<interface\\>\\)\\|"
2216 "\\(\\<package\\>\\)"))
2219 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
2221 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
2223 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
2225 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
2227 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
2229 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
2232 (if (= (following-char) ?\) )
2234 (forward-sexp 1)))))
2237 (if (= (following-char) ?\) )
2243 (defun verilog-declaration-beg ()
2244 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2246 (require 'font-lock)
2247 (defvar verilog-need-fld 1)
2248 (defvar font-lock-defaults-alist nil) ;In case we are XEmacs
2250 (defun verilog-font-lock-init ()
2251 "Initialize fontification."
2252 ;; highlight keywords and standardized types, attributes, enumeration
2253 ;; values, and subprograms
2254 (setq verilog-font-lock-keywords-3
2255 (append verilog-font-lock-keywords-2
2256 (when verilog-highlight-translate-off
2258 ;; Fontify things in translate off regions
2259 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
2263 (put 'verilog-mode 'font-lock-defaults
2264 '((verilog-font-lock-keywords
2265 verilog-font-lock-keywords-1
2266 verilog-font-lock-keywords-2
2267 verilog-font-lock-keywords-3
2269 nil ;; nil means highlight strings & comments as well as keywords
2270 nil ;; nil means keywords must match case
2271 nil ;; syntax table handled elsewhere
2272 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
2274 (if verilog-need-fld
2275 (let ((verilog-mode-defaults
2276 '((verilog-font-lock-keywords
2277 verilog-font-lock-keywords-1
2278 verilog-font-lock-keywords-2
2279 verilog-font-lock-keywords-3
2281 nil ;; nil means highlight strings & comments as well as keywords
2282 nil ;; nil means keywords must match case
2283 nil ;; syntax table handled elsewhere
2284 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
2286 (setq font-lock-defaults-alist
2288 font-lock-defaults-alist
2289 (list (cons 'verilog-mode verilog-mode-defaults))))
2290 (setq verilog-need-fld 0))))
2292 ;; initialize fontification for Verilog Mode
2293 (verilog-font-lock-init)
2295 (defconst verilog-startup-message-lines
2296 '("Please use \\[verilog-submit-bug-report] to report bugs."
2297 "Visit http://www.verilog.com to check for updates"
2299 (defconst verilog-startup-message-displayed t)
2300 (defun verilog-display-startup-message ()
2301 (if (not verilog-startup-message-displayed)
2303 (let ((lines verilog-startup-message-lines))
2304 (message "verilog-mode version %s, released %s; type \\[describe-mode] for help"
2305 verilog-mode-version verilog-mode-release-date)
2306 (setq verilog-startup-message-displayed t)
2307 (while (and (sit-for 4) lines)
2308 (message (substitute-command-keys (car lines)))
2309 (setq lines (cdr lines)))))
2315 (defvar verilog-which-tool 1)
2317 (defun verilog-mode ()
2318 "Major mode for editing Verilog code.
2319 \\<verilog-mode-map>
2320 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
2321 AUTOs can improve coding efficiency.
2323 Use \\[verilog-faq] for a pointer to frequently asked questions.
2325 NEWLINE, TAB indents for Verilog code.
2326 Delete converts tabs to spaces as it moves back.
2328 Supports highlighting.
2330 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
2331 with no args, if that value is non-nil.
2333 Variables controlling indentation/edit style:
2335 variable `verilog-indent-level' (default 3)
2336 Indentation of Verilog statements with respect to containing block.
2337 `verilog-indent-level-module' (default 3)
2338 Absolute indentation of Module level Verilog statements.
2339 Set to 0 to get initial and always statements lined up
2340 on the left side of your screen.
2341 `verilog-indent-level-declaration' (default 3)
2342 Indentation of declarations with respect to containing block.
2343 Set to 0 to get them list right under containing block.
2344 `verilog-indent-level-behavioral' (default 3)
2345 Indentation of first begin in a task or function block
2346 Set to 0 to get such code to lined up underneath the task or function keyword
2347 `verilog-indent-level-directive' (default 1)
2348 Indentation of `ifdef/`endif blocks
2349 `verilog-cexp-indent' (default 1)
2350 Indentation of Verilog statements broken across lines i.e.:
2353 `verilog-case-indent' (default 2)
2354 Indentation for case statements.
2355 `verilog-auto-newline' (default nil)
2356 Non-nil means automatically newline after semicolons and the punctuation
2358 `verilog-auto-indent-on-newline' (default t)
2359 Non-nil means automatically indent line after newline
2360 `verilog-tab-always-indent' (default t)
2361 Non-nil means TAB in Verilog mode should always reindent the current line,
2362 regardless of where in the line point is when the TAB command is used.
2363 `verilog-indent-begin-after-if' (default t)
2364 Non-nil means to indent begin statements following a preceding
2365 if, else, while, for and repeat statements, if any. otherwise,
2366 the begin is lined up with the preceding token. If t, you get:
2368 begin // amount of indent based on `verilog-cexp-indent'
2372 `verilog-auto-endcomments' (default t)
2373 Non-nil means a comment /* ... */ is set after the ends which ends
2374 cases, tasks, functions and modules.
2375 The type and name of the object will be set between the braces.
2376 `verilog-minimum-comment-distance' (default 10)
2377 Minimum distance (in lines) between begin and end required before a comment
2378 will be inserted. Setting this variable to zero results in every
2379 end acquiring a comment; the default avoids too many redundant
2380 comments in tight quarters.
2381 `verilog-auto-lineup' (default `(all))
2382 List of contexts where auto lineup of code should be done.
2384 Variables controlling other actions:
2386 `verilog-linter' (default surelint)
2387 Unix program to call to run the lint checker. This is the default
2388 command for \\[compile-command] and \\[verilog-auto-save-compile].
2390 See \\[customize] for the complete list of variables.
2392 AUTO expansion functions are, in part:
2394 \\[verilog-auto] Expand AUTO statements.
2395 \\[verilog-delete-auto] Remove the AUTOs.
2396 \\[verilog-inject-auto] Insert AUTOs for the first time.
2398 Some other functions are:
2400 \\[verilog-complete-word] Complete word with appropriate possibilities.
2401 \\[verilog-mark-defun] Mark function.
2402 \\[verilog-beg-of-defun] Move to beginning of current function.
2403 \\[verilog-end-of-defun] Move to end of current function.
2404 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
2406 \\[verilog-comment-region] Put marked area in a comment.
2407 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
2408 \\[verilog-insert-block] Insert begin ... end;.
2409 \\[verilog-star-comment] Insert /* ... */.
2411 \\[verilog-sk-always] Insert a always @(AS) begin .. end block.
2412 \\[verilog-sk-begin] Insert a begin .. end block.
2413 \\[verilog-sk-case] Insert a case block, prompting for details.
2414 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
2415 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
2416 \\[verilog-sk-header] Insert a nice header block at the top of file.
2417 \\[verilog-sk-initial] Insert an initial begin .. end block.
2418 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
2419 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
2420 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
2421 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
2422 \\[verilog-sk-specify] Insert a specify .. endspecify block.
2423 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
2424 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
2425 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
2426 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
2427 \\[verilog-sk-if] Insert an if (..) begin .. end block.
2428 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
2429 \\[verilog-sk-comment] Insert a comment block.
2430 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
2431 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
2432 \\[verilog-sk-input] Insert an input declaration, prompting for details.
2433 \\[verilog-sk-output] Insert an output declaration, prompting for details.
2434 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
2435 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
2436 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
2437 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
2438 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
2440 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
2441 Key bindings specific to `verilog-mode-map' are:
2443 \\{verilog-mode-map}"
2445 (kill-all-local-variables)
2446 (use-local-map verilog-mode-map)
2447 (setq major-mode 'verilog-mode)
2448 (setq mode-name "Verilog")
2449 (setq local-abbrev-table verilog-mode-abbrev-table)
2450 (setq verilog-mode-syntax-table (make-syntax-table))
2451 (verilog-populate-syntax-table verilog-mode-syntax-table)
2452 (set (make-local-variable 'beginning-of-defun-function)
2453 'verilog-beg-of-defun)
2454 (set (make-local-variable 'end-of-defun-function)
2455 'verilog-end-of-defun)
2456 ;; add extra comment syntax
2457 (verilog-setup-dual-comments verilog-mode-syntax-table)
2458 (set-syntax-table verilog-mode-syntax-table)
2459 (make-local-variable 'indent-line-function)
2460 (setq indent-line-function 'verilog-indent-line-relative)
2461 (setq comment-indent-function 'verilog-comment-indent)
2462 (make-local-variable 'parse-sexp-ignore-comments)
2463 (setq parse-sexp-ignore-comments nil)
2464 (make-local-variable 'comment-start)
2465 (make-local-variable 'comment-end)
2466 (make-local-variable 'comment-multi-line)
2467 (make-local-variable 'comment-start-skip)
2468 (setq comment-start "// "
2470 comment-start-skip "/\\*+ *\\|// *"
2471 comment-multi-line nil)
2472 ;; Set up for compilation
2473 (setq verilog-which-tool 1)
2474 (setq verilog-tool 'verilog-linter)
2475 (verilog-set-compile-command)
2476 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
2477 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
2480 (when (featurep 'xemacs)
2481 (when (and current-menubar
2482 (not (assoc "Verilog" current-menubar)))
2483 ;; (set-buffer-menubar (copy-sequence current-menubar))
2484 (add-submenu nil verilog-xemacs-menu)
2485 (add-submenu nil verilog-stmt-menu)
2487 ;; Stuff for GNU emacs
2488 (make-local-variable 'font-lock-defaults)
2489 ;;------------------------------------------------------------
2490 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
2491 ;; all buffer local:
2492 (make-local-hook 'font-lock-mode-hook)
2493 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20
2494 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
2495 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20
2496 (make-local-hook 'after-change-functions)
2497 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
2499 ;; Tell imenu how to handle verilog.
2500 (make-local-variable 'imenu-generic-expression)
2501 (setq imenu-generic-expression verilog-imenu-generic-expression)
2503 (unless (assq 'verilog-mode hs-special-modes-alist)
2504 (setq hs-special-modes-alist
2505 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
2506 verilog-forward-sexp-function)
2507 hs-special-modes-alist)))
2508 ;; Display version splash information.
2509 (verilog-display-startup-message)
2512 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
2513 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
2514 ;; (verilog-getopt-flags)
2515 (run-hooks 'verilog-mode-hook))
2519 ;; Electric functions
2521 (defun electric-verilog-terminate-line (&optional arg)
2522 "Terminate line and indent next line.
2523 With optional ARG, remove existing end of line comments."
2525 ;; before that see if we are in a comment
2528 (parse-partial-sexp (point-min) (point)))))
2530 ((nth 7 state) ; Inside // comment
2533 (delete-horizontal-space)
2537 (insert-string "// ")
2538 (beginning-of-line)))
2539 (verilog-indent-line))
2540 ((nth 4 state) ; Inside any comment (hence /**/)
2542 (verilog-more-comment))
2544 ;; First, check if current line should be indented
2546 (delete-horizontal-space)
2548 (skip-chars-forward " \t")
2549 (if (looking-at verilog-auto-end-comment-lines-re)
2550 (let ((indent-str (verilog-indent-line)))
2551 ;; Maybe we should set some endcomments
2552 (if verilog-auto-endcomments
2553 (verilog-set-auto-endcomments indent-str arg))
2555 (delete-horizontal-space)
2562 (delete-horizontal-space)
2567 ;; see if we should line up assignments
2569 (if (or (memq 'all verilog-auto-lineup)
2570 (memq 'assignments verilog-auto-lineup))
2571 (verilog-pretty-expr)
2578 (if verilog-auto-indent-on-newline
2579 (verilog-indent-line))
2585 (defun electric-verilog-terminate-and-indent ()
2586 "Insert a newline and indent for the next statement."
2588 (electric-verilog-terminate-line 1))
2590 (defun electric-verilog-semi ()
2591 "Insert `;' character and reindent the line."
2593 (insert last-command-char)
2595 (if (or (verilog-in-comment-or-string-p)
2596 (verilog-in-escaped-name-p))
2600 (verilog-forward-ws&directives)
2601 (verilog-indent-line)
2603 (if (and verilog-auto-newline
2604 (not (verilog-parenthesis-depth)))
2605 (electric-verilog-terminate-line))))
2607 (defun electric-verilog-semi-with-comment ()
2608 "Insert `;' character, reindent the line and indent for comment."
2613 (verilog-indent-line))
2614 (indent-for-comment))
2616 (defun electric-verilog-colon ()
2617 "Insert `:' and do all indentations except line indent on this line."
2619 (insert last-command-char)
2620 ;; Do nothing if within string.
2622 (verilog-within-string)
2623 (not (verilog-in-case-region-p)))
2627 (lim (progn (verilog-beg-of-statement) (point))))
2629 (verilog-backward-case-item lim)
2630 (verilog-indent-line)))
2631 ;; (let ((verilog-tab-always-indent nil))
2632 ;; (verilog-indent-line))
2635 ;;(defun electric-verilog-equal ()
2636 ;; "Insert `=', and do indentation if within block."
2638 ;; (insert last-command-char)
2639 ;; Could auto line up expressions, but not yet
2640 ;; (if (eq (car (verilog-calculate-indent)) 'block)
2641 ;; (let ((verilog-tab-always-indent nil))
2642 ;; (verilog-indent-command)))
2645 (defun electric-verilog-tick ()
2646 "Insert back-tick, and indent to column 0 if this is a CPP directive."
2648 (insert last-command-char)
2652 (looking-at verilog-directive-re-1))
2653 (verilog-indent-line))))
2655 (defun electric-verilog-tab ()
2656 "Function called when TAB is pressed in Verilog mode."
2658 ;; If verilog-tab-always-indent, indent the beginning of the line.
2659 (if (or verilog-tab-always-indent
2661 (skip-chars-backward " \t")
2663 (let* ((oldpnt (point))
2667 (skip-chars-forward " \t")
2668 (verilog-indent-line)
2669 (back-to-indentation)
2671 (if (< (point) boi-point)
2672 (back-to-indentation)
2673 (cond ((not verilog-tab-to-comment))
2677 (indent-for-comment)
2678 (when (and (eolp) (= oldpnt (point)))
2679 ; kill existing comment
2681 (re-search-forward comment-start-skip oldpnt 'move)
2682 (goto-char (match-beginning 0))
2683 (skip-chars-backward " \t")
2684 (kill-region (point) oldpnt)
2687 (progn (insert "\t"))))
2692 ;; Interactive functions
2695 (defun verilog-indent-buffer ()
2696 "Indent-region the entire buffer as Verilog code.
2697 To call this from the command line, see \\[verilog-batch-indent]."
2700 (indent-region (point-min) (point-max) nil))
2702 (defun verilog-insert-block ()
2703 "Insert Verilog begin ... end; block in the code with right indentation."
2705 (verilog-indent-line)
2707 (electric-verilog-terminate-line)
2709 (electric-verilog-terminate-line)
2712 (verilog-indent-line)))
2714 (defun verilog-star-comment ()
2715 "Insert Verilog star comment at point."
2717 (verilog-indent-line)
2725 (defun verilog-insert-indices (MAX)
2726 "Insert a set of indices at into the rectangle.
2727 The upper left corner is defined by the current point. Indices always
2728 begin with 0 and extend to the MAX - 1. If no prefix arg is given, the
2729 user is prompted for a value. The indices are surrounded by square brackets
2730 \[]. For example, the following code with the point located after the first
2737 a = b ==> insert-indices ==> a[ 4] = b
2743 (interactive "NMAX?")
2748 (insert (format "[%3d]" n)))
2753 (defun verilog-generate-numbers (MAX)
2754 "Insert a set of generated numbers into a rectangle.
2755 The upper left corner is defined by point. The numbers are padded to three
2756 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
2757 is supplied, then the user is prompted for the MAX number. consider the
2758 following code fragment:
2764 buf buf ==> insert-indices ==> buf buf004
2770 (interactive "NMAX?")
2775 (insert (format "%3.3d" n)))
2779 (defun verilog-mark-defun ()
2780 "Mark the current verilog function (or procedure).
2781 This puts the mark at the end, and point at the beginning."
2784 (verilog-end-of-defun)
2786 (verilog-beg-of-defun)
2787 (zmacs-activate-region))
2789 (defun verilog-comment-region (start end)
2790 ; checkdoc-params: (start end)
2791 "Put the region into a Verilog comment.
2792 The comments that are in this area are \"deformed\":
2793 `*)' becomes `!(*' and `}' becomes `!{'.
2794 These deformed comments are returned to normal if you use
2795 \\[verilog-uncomment-region] to undo the commenting.
2797 The commented area starts with `verilog-exclude-str-start', and ends with
2798 `verilog-exclude-str-end'. But if you change these variables,
2799 \\[verilog-uncomment-region] won't recognize the comments."
2802 ;; Insert start and endcomments
2804 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
2805 (not (save-excursion (skip-chars-backward " \t") (bolp))))
2807 (beginning-of-line))
2808 (insert verilog-exclude-str-end)
2813 (insert verilog-exclude-str-start)
2815 ;; Replace end-comments within commented area
2818 (while (re-search-backward "\\*/" start t)
2819 (replace-match "*-/" t t)))
2821 (let ((s+1 (1+ start)))
2822 (while (re-search-backward "/\\*" s+1 t)
2823 (replace-match "/-*" t t))))
2826 (defun verilog-uncomment-region ()
2827 "Uncomment a commented area; change deformed comments back to normal.
2828 This command does nothing if the pointer is not in a commented
2829 area. See also `verilog-comment-region'."
2832 (let ((start (point))
2834 ;; Find the boundaries of the comment
2836 (setq start (progn (search-backward verilog-exclude-str-start nil t)
2838 (setq end (progn (search-forward verilog-exclude-str-end nil t)
2840 ;; Check if we're really inside a comment
2841 (if (or (equal start (point)) (<= end (point)))
2842 (message "Not standing within commented area.")
2844 ;; Remove endcomment
2847 (let ((pos (point)))
2849 (delete-region pos (1+ (point))))
2850 ;; Change comments back to normal
2852 (while (re-search-backward "\\*-/" start t)
2853 (replace-match "*/" t t)))
2855 (while (re-search-backward "/-\\*" start t)
2856 (replace-match "/*" t t)))
2857 ;; Remove start comment
2860 (let ((pos (point)))
2862 (delete-region pos (1+ (point)))))))))
2864 (defun verilog-beg-of-defun ()
2865 "Move backward to the beginning of the current function or procedure."
2867 (verilog-re-search-backward verilog-defun-re nil 'move))
2869 (defun verilog-end-of-defun ()
2870 "Move forward to the end of the current function or procedure."
2872 (verilog-re-search-forward verilog-end-defun-re nil 'move))
2874 (defun verilog-get-beg-of-defun (&optional warn)
2876 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
2879 (error "%s: Can't find module beginning" (verilog-point-text))
2881 (defun verilog-get-end-of-defun (&optional warn)
2883 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
2886 (error "%s: Can't find endmodule" (verilog-point-text))
2889 (defun verilog-label-be (&optional arg)
2890 "Label matching begin ... end, fork ... join and case ... endcase statements.
2891 With ARG, first kill any existing labels."
2896 (verilog-beg-of-defun)
2899 (verilog-end-of-defun)
2902 (goto-char (marker-position b))
2904 (message "Relabeling module..."))
2906 (> (marker-position e) (point))
2907 (verilog-re-search-forward
2909 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
2910 "\\|\\(`endif\\)\\|\\(`else\\)")
2912 (goto-char (match-beginning 0))
2913 (let ((indent-str (verilog-indent-line)))
2914 (verilog-set-auto-endcomments indent-str 't)
2916 (delete-horizontal-space)
2919 (if (= 9 (% cnt 10))
2920 (message "%d..." cnt))
2926 (message "%d lines auto commented" cnt))
2929 (defun verilog-beg-of-statement ()
2930 "Move backward to beginning of statement."
2932 ;; Move back token by token until we see the end
2933 ;; of some ealier line.
2935 ;; If the current point does not begin a new
2936 ;; statement, as in the character ahead of us is a ';', or SOF
2937 ;; or the string after us unambiguosly starts a statement,
2938 ;; or the token before us unambiguously ends a statement,
2939 ;; then move back a token and test again.
2942 (= (preceding-char) ?\;)
2947 (looking-at verilog-extended-complete-re)
2948 (not (save-excursion
2949 (verilog-backward-token)
2950 (looking-at verilog-extended-complete-re)))
2952 (looking-at verilog-basic-complete-re)
2954 (verilog-backward-token)
2956 (looking-at verilog-end-block-re)
2957 (looking-at verilog-preprocessor-re)))
2959 (verilog-backward-syntactic-ws)
2960 (verilog-backward-token))
2961 ;; Now point is where the previous line ended.
2962 (verilog-forward-syntactic-ws))
2964 (defun verilog-beg-of-statement-1 ()
2965 "Move backward to beginning of statement."
2969 (while (and (not (looking-at verilog-complete-reg))
2971 (verilog-backward-token)
2972 (not (looking-at verilog-complete-reg))
2973 (verilog-backward-syntactic-ws)
2976 (not (= (preceding-char) ?\;))))
2978 (verilog-forward-ws&directives)))
2980 (defun verilog-end-of-statement ()
2981 "Move forward to end of current statement."
2984 (or (looking-at verilog-beg-block-re)
2985 ;; Skip to end of statement
2986 (setq pos (catch 'found
2989 (verilog-skip-forward-comment-or-string)
2990 (cond ((looking-at "[ \t]*;")
2991 (skip-chars-forward "^;")
2993 (throw 'found (point)))
2996 (looking-at verilog-beg-block-re))
2997 (goto-char (match-beginning 0))
2999 ((looking-at "[ \t]*)")
3000 (throw 'found (point)))
3002 (throw 'found (point))))))))
3004 ;; Skip a whole block
3007 (verilog-re-search-forward verilog-end-statement-re nil 'move)
3008 (setq nest (if (match-end 1)
3012 (throw 'found (point)))
3014 (throw 'found (verilog-end-of-statement))))))
3017 (defun verilog-in-case-region-p ()
3018 "Return TRUE if in a case region;
3019 more specifically, point @ in the line foo : @ begin"
3023 (progn (verilog-forward-syntactic-ws)
3024 (looking-at "\\<begin\\>"))
3025 (progn (verilog-backward-syntactic-ws)
3026 (= (preceding-char) ?\:)))
3030 (verilog-re-search-backward
3031 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
3032 "\\(\\<endcase\\>\\)\\>")
3036 (setq nest (1+ nest)))
3040 (setq nest (1- nest)))
3042 (throw 'found (= nest 0)))
3045 (defun verilog-in-struct-region-p ()
3046 "Return TRUE if in a struct region;
3047 more specifically, in a list after a struct|union keyword"
3050 (let* ((state (parse-partial-sexp (point-min) (point)))
3051 (depth (nth 0 state)))
3053 (progn (backward-up-list depth)
3054 (verilog-beg-of-statement)
3055 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")
3062 (defun verilog-in-generate-region-p ()
3063 "Return TRUE if in a generate region;
3064 more specifically, after a generate and before an endgenerate"
3066 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3072 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
3074 ((match-end 1) ; generate
3075 (setq nest (1- nest)))
3076 ((match-end 2) ; endgenerate
3077 (setq nest (1+ nest)))
3080 (= nest 0) )) ; return nest
3082 (defun verilog-in-fork-region-p ()
3083 "Return true if between a fork and join."
3085 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3091 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
3093 ((match-end 1) ; fork
3094 (setq nest (1- nest)))
3095 ((match-end 2) ; join
3096 (setq nest (1+ nest)))
3099 (= nest 0) )) ; return nest
3101 (defun verilog-backward-case-item (lim)
3102 "Skip backward to nearest enclosing case item.
3103 Limit search to point LIM."
3109 (verilog-re-search-backward verilog-endcomment-reason-re
3112 ;; Try to find the real :
3113 (if (save-excursion (search-backward ":" lim1 t))
3119 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
3123 (setq colon (1+ colon))
3125 (error "%s: unbalanced [" (verilog-point-text))))
3127 (setq colon (1- colon)))
3130 (setq colon (1+ colon)))
3132 ;; Skip back to beginning of case item
3133 (skip-chars-backward "\t ")
3134 (verilog-skip-backward-comment-or-string)
3139 (verilog-re-search-backward
3140 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
3144 (goto-char (match-end 1))
3145 (verilog-forward-ws&directives)
3146 (if (looking-at "(")
3149 (verilog-forward-ws&directives)))
3152 (goto-char (match-end 0))
3153 (verilog-forward-ws&directives)
3156 (error "Malformed case item")
3158 (setq str (buffer-substring b e))
3162 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3163 (setq str (concat (substring str 0 e) "...")))
3172 (defun kill-existing-comment ()
3173 "Kill auto comment on this line."
3181 (search-forward "//" e t))))
3183 (delete-region (- b 2) e)))))
3185 (defconst verilog-directive-nest-re
3186 (concat "\\(`else\\>\\)\\|"
3187 "\\(`endif\\>\\)\\|"
3189 "\\(`ifdef\\>\\)\\|"
3190 "\\(`ifndef\\>\\)"))
3191 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3192 "Add ending comment with given INDENT-STR.
3193 With KILL-EXISTING-COMMENT, remove what was there before.
3194 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3195 Insert `// case expr ' if this line ends a case block.
3196 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3197 Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME."
3200 (; Comment close preprocessor directives
3202 (looking-at "\\(`endif\\)\\|\\(`else\\)")
3203 (or kill-existing-comment
3204 (not (save-excursion
3206 (search-backward "//" (verilog-get-beg-of-line) t)))))
3209 (else (if (match-end 2) "!" " "))
3212 (if kill-existing-comment
3213 (kill-existing-comment))
3214 (delete-horizontal-space)
3217 (while (and (/= nest 0)
3218 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3220 ((match-end 1) ; `else
3223 ((match-end 2) ; `endif
3224 (setq nest (1+ nest)))
3225 ((match-end 3) ; `if
3226 (setq nest (1- nest)))
3227 ((match-end 4) ; `ifdef
3228 (setq nest (1- nest)))
3229 ((match-end 5) ; `ifndef
3230 (setq nest (1- nest)))
3238 (skip-chars-forward "^ \t")
3239 (verilog-forward-syntactic-ws)
3242 (skip-chars-forward "a-zA-Z0-9_")
3246 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3247 (insert (concat " // " else m " " (buffer-substring b e))))
3249 (insert " // unmatched `else or `endif")
3253 (; Comment close case/class/function/task/module and named block
3254 (and (looking-at "\\<end")
3255 (or kill-existing-comment
3256 (not (save-excursion
3258 (search-backward "//" (verilog-get-beg-of-line) t)))))
3259 (let ((type (car indent-str)))
3260 (unless (eq type 'declaration)
3261 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3262 (if (looking-at verilog-end-block-ordered-re)
3264 (;- This is a case block; search back for the start of this case
3265 (match-end 1) ;; of verilog-end-block-ordered-re
3268 (str "UNMATCHED!!"))
3270 (verilog-leap-to-head)
3272 ((looking-at "\\<randcase\\>")
3273 (setq str "randcase")
3277 (goto-char (match-end 1))
3280 (setq s (match-beginning 1))
3281 (setq f (progn (end-of-line)
3283 (setq str (buffer-substring s f)))
3285 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
3287 (verilog-get-expr))))))
3289 (if kill-existing-comment
3290 (kill-existing-comment))
3291 (delete-horizontal-space)
3292 (insert (concat " // " str ))
3296 (;- This is a begin..end block
3297 (match-end 2) ;; of verilog-end-block-ordered-re
3298 (let ((str " // UNMATCHED !!")
3305 (verilog-leap-to-head)
3306 (setq there (point))
3307 (if (not (match-end 0))
3311 (if kill-existing-comment
3312 (kill-existing-comment))
3313 (delete-horizontal-space)
3318 (save-excursion (verilog-beg-of-defun) (point)))
3322 (;-- handle named block differently
3323 (looking-at verilog-named-block-re)
3324 (search-forward ":")
3325 (setq there (point))
3326 (setq str (verilog-get-expr))
3328 (setq str (concat " // block: " str )))
3330 ((verilog-in-case-region-p) ;-- handle case item differently
3332 (setq str (verilog-backward-case-item lim))
3333 (setq there (point))
3335 (setq str (concat " // case: " str )))
3337 (;- try to find "reason" for this begin
3341 (verilog-backward-token)
3342 (verilog-beg-of-statement-1)
3346 ((looking-at verilog-endcomment-reason-re)
3347 (setq there (match-end 0))
3349 (buffer-substring (match-beginning 0) (match-end 0)) " "))
3355 (if (and (verilog-continued-line)
3356 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
3358 (goto-char (match-end 0))
3359 (setq there (point))
3362 (buffer-substring (match-beginning 0) (match-end 0)) " "
3363 (verilog-get-expr))))
3369 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
3372 (while (verilog-re-search-backward reg nil 'move)
3374 ((match-end 1) ; begin
3375 (setq nest (1- nest)))
3376 ((match-end 2) ; end
3377 (setq nest (1+ nest)))
3381 (goto-char (match-end 0))
3382 (setq there (point))
3384 (setq str (verilog-get-expr))
3385 (setq str (concat " // else: !if" str ))
3394 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
3397 (while (verilog-re-search-backward reg nil 'move)
3399 ((match-end 1) ; begin
3400 (setq nest (1- nest)))
3401 ((match-end 2) ; end
3402 (setq nest (1+ nest)))
3406 (goto-char (match-end 0))
3407 (setq there (point))
3409 (setq str (verilog-get-expr))
3410 (setq str (concat " // else: !if" str ))
3415 (;- task/function/initial et cetera
3418 (goto-char (match-end 0))
3419 (setq there (point))
3421 (setq str (verilog-get-expr))
3422 (setq str (concat " // " cntx str )))
3425 (setq str " // auto-endcomment confused "))
3429 (verilog-in-case-region-p) ;-- handle case item differently
3431 (setq there (point))
3433 (setq str (verilog-backward-case-item lim))))
3435 (setq str (concat " // case: " str )))
3437 ((verilog-in-fork-region-p)
3439 (setq str " // fork branch" ))
3441 ((looking-at "\\<end\\>")
3444 (verilog-forward-syntactic-ws)
3446 (setq str (verilog-get-expr))
3447 (setq str (concat " // " cntx str )))
3452 (if kill-existing-comment
3453 (kill-existing-comment))
3454 (delete-horizontal-space)
3456 (> (count-lines here there) verilog-minimum-comment-distance))
3460 (;- this is endclass, which can be nested
3461 (match-end 11) ;; of verilog-end-block-ordered-re
3464 ( reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
3469 (while (verilog-re-search-backward reg nil 'move)
3471 ((match-end 3) ; endclass
3473 (setq string "unmatched endclass")
3476 ((match-end 2) ; endclass
3477 (setq nest (1+ nest)))
3479 ((match-end 1) ; class
3480 (setq nest (1- nest))
3483 (goto-char (match-end 0))
3486 (skip-chars-forward "^ \t")
3487 (verilog-forward-ws&directives)
3490 (skip-chars-forward "a-zA-Z0-9_")
3492 (setq string (buffer-substring b e)))
3496 (insert (concat " // " string )))
3499 (;- this is end{function,generate,task,module,primitive,table,generate}
3500 ;- which can not be nested.
3502 (let (string reg (width nil))
3504 (if kill-existing-comment
3506 (kill-existing-comment)))
3507 (delete-horizontal-space)
3510 ((match-end 5) ;; of verilog-end-block-ordered-re
3511 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
3512 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")
3514 ((match-end 6) ;; of verilog-end-block-ordered-re
3515 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
3516 ((match-end 7) ;; of verilog-end-block-ordered-re
3517 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
3518 ((match-end 8) ;; of verilog-end-block-ordered-re
3519 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3520 ((match-end 9) ;; of verilog-end-block-ordered-re
3521 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
3522 ((match-end 10) ;; of verilog-end-block-ordered-re
3523 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3524 ((match-end 11) ;; of verilog-end-block-ordered-re
3525 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3526 ((match-end 12) ;; of verilog-end-block-ordered-re
3527 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3528 ((match-end 13) ;; of verilog-end-block-ordered-re
3529 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3530 ((match-end 14) ;; of verilog-end-block-ordered-re
3531 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3532 ((match-end 15) ;; of verilog-end-block-ordered-re
3533 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
3535 (t (error "Problem in verilog-set-auto-endcomments"))
3539 (verilog-re-search-backward reg nil 'move)
3543 (skip-chars-forward "^ \t")
3544 (verilog-forward-ws&directives)
3545 (if (and width (looking-at width))
3547 (goto-char (match-end 0))
3548 (verilog-forward-ws&directives)
3552 (skip-chars-forward "a-zA-Z0-9_")
3554 (setq string (buffer-substring b e)))
3557 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
3559 (insert (concat " // " string )))
3562 (defun verilog-get-expr()
3563 "Grab expression at point, e.g, case ( a | b & (c ^d))"
3565 (verilog-forward-syntactic-ws)
3566 (skip-chars-forward " \t")
3572 (verilog-forward-syntactic-ws)
3573 (if (looking-at "(")
3576 (while (and (/= par 0)
3577 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3580 (setq par (1+ par)))
3582 (setq par (1- par)))))))
3586 (while (and (/= par 0)
3587 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3590 (setq par (1+ par)))
3592 (setq par (1- par)))))
3596 (while (and (/= par 0)
3597 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
3600 (setq par (1+ par)))
3602 (setq par (1- par)))))
3603 (verilog-forward-syntactic-ws)
3604 (skip-chars-forward "^ \t\n\f")
3606 ((looking-at "/[/\\*]")
3609 (skip-chars-forward "^: \t\n\f")
3612 (str (buffer-substring b e)))
3613 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3614 (setq str (concat (substring str 0 e) "...")))
3617 (defun verilog-expand-vector ()
3618 "Take a signal vector on the current line and expand it to multiple lines.
3619 Useful for creating tri's and other expanded fields."
3621 (verilog-expand-vector-internal "[" "]"))
3623 (defun verilog-expand-vector-internal (bra ket)
3624 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
3627 (let ((signal-string (buffer-substring (point)
3629 (end-of-line) (point)))))
3630 (if (string-match (concat "\\(.*\\)"
3632 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
3634 "\\(.*\\)$") signal-string)
3635 (let* ((sig-head (match-string 1 signal-string))
3636 (vec-start (string-to-int (match-string 2 signal-string)))
3637 (vec-end (if (= (match-beginning 3) (match-end 3))
3639 (string-to-int (substring signal-string (1+ (match-beginning 3)) (match-end 3)))))
3640 (vec-range (if (= (match-beginning 4) (match-end 4))
3642 (string-to-int (substring signal-string (+ 2 (match-beginning 4)) (match-end 4)))))
3643 (sig-tail (match-string 5 signal-string))
3648 (let ((tmp vec-start))
3649 (setq vec-start vec-end
3651 vec-range (- vec-range))))
3652 (if (< vec-end vec-start)
3653 (while (<= vec-end vec-start)
3654 (setq vec (append vec (list vec-start)))
3655 (setq vec-start (- vec-start vec-range)))
3656 (while (<= vec-start vec-end)
3657 (setq vec (append vec (list vec-start)))
3658 (setq vec-start (+ vec-start vec-range))))
3660 ;; Delete current line
3661 (delete-region (point) (progn (forward-line 0) (point)))
3665 (insert (concat sig-head bra (int-to-string (car vec)) ket sig-tail "\n"))
3666 (setq vec (cdr vec)))
3671 (defun verilog-strip-comments ()
3672 "Strip all comments from the verilog code."
3674 (goto-char (point-min))
3675 (while (re-search-forward "//" nil t)
3676 (if (verilog-within-string)
3677 (re-search-forward "\"" nil t)
3678 (if (verilog-in-star-comment-p)
3679 (re-search-forward "\*/" nil t)
3680 (let ((bpt (- (point) 2)))
3682 (delete-region bpt (point))))))
3684 (goto-char (point-min))
3685 (while (re-search-forward "/\\*" nil t)
3686 (if (verilog-within-string)
3687 (re-search-forward "\"" nil t)
3688 (let ((bpt (- (point) 2)))
3689 (re-search-forward "\\*/")
3690 (delete-region bpt (point))))))
3692 (defun verilog-one-line ()
3693 "Convert structural verilog instances to occupy one line."
3695 (goto-char (point-min))
3696 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
3697 (replace-match "\\1 " nil nil)))
3699 (defun verilog-linter-name ()
3700 "Return name of linter, either surelint or verilint."
3701 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3703 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3705 (cond ((equal compile-word1 "surelint") `surelint)
3706 ((equal compile-word1 "verilint") `verilint)
3707 ((equal lint-word1 "surelint") `surelint)
3708 ((equal lint-word1 "verilint") `verilint)
3709 (t `surelint)))) ;; back compatibility
3711 (defun verilog-lint-off ()
3712 "Convert a Verilog linter warning line into a disable statement.
3714 pci_bfm_null.v, line 46: Unused input: pci_rst_
3715 becomes a comment for the appropriate tool.
3717 The first word of the `compile-command' or `verilog-linter'
3718 variables are used to determine which product is being used.
3720 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
3722 (let ((linter (verilog-linter-name)))
3723 (cond ((equal linter `surelint)
3724 (verilog-surelint-off))
3725 ((equal linter `verilint)
3726 (verilog-verilint-off))
3727 (t (error "Linter name not set")))))
3729 (defun verilog-surelint-off ()
3730 "Convert a SureLint warning line into a disable statement.
3731 Run from Verilog source window; assumes there is a *compile* buffer
3732 with point set appropriately.
3735 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
3737 // surefire lint_line_off UDDONX"
3740 (switch-to-buffer compilation-last-buffer)
3743 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
3744 (let* ((code (match-string 2))
3745 (file (match-string 3))
3746 (line (match-string 4))
3747 (buffer (get-file-buffer file))
3752 (and (file-exists-p file)
3753 (find-file-noselect file)))
3755 (let* ((pop-up-windows t))
3756 (let ((name (expand-file-name
3758 (format "Find this error in: (default %s) "
3761 (if (file-directory-p name)
3762 (setq name (expand-file-name filename name)))
3764 (and (file-exists-p name)
3765 (find-file-noselect name))))))))
3766 (switch-to-buffer buffer)
3767 (goto-line (string-to-number line))
3771 ((verilog-in-slash-comment-p)
3772 (re-search-backward "//")
3774 ((looking-at "// surefire lint_off_line ")
3775 (goto-char (match-end 0))
3776 (let ((lim (save-excursion (end-of-line) (point))))
3777 (if (re-search-forward code lim 'move)
3779 (insert-string (concat " " code)))))
3782 ((verilog-in-star-comment-p)
3783 (re-search-backward "/\*")
3784 (insert-string (format " // surefire lint_off_line %6s" code ))
3787 (insert-string (format " // surefire lint_off_line %6s" code ))
3790 (defun verilog-verilint-off ()
3791 "Convert a Verilint warning line into a disable statement.
3794 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
3796 //Verilint 240 off // WARNING: Unused input"
3800 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
3801 (replace-match (format
3802 ;; %3s makes numbers 1-999 line up nicely
3803 "\\1//Verilint %3s off // WARNING: \\3"
3806 (verilog-indent-line))))
3808 (defun verilog-auto-save-compile ()
3809 "Update automatics with \\[verilog-auto], save the buffer, and compile."
3811 (verilog-auto) ; Always do it for safety
3813 (compile compile-command))
3821 (defmacro verilog-batch-error-wrapper (&rest body)
3822 "Execute BODY and add error prefix to any errors found.
3823 This lets programs calling batch mode to easily extract error messages."
3824 `(condition-case err
3827 (error "%%Error: %s%s" (error-message-string err)
3828 (if (featurep 'xemacs) "\n" ""))))) ;; xemacs forgets to add a newline
3830 (defun verilog-batch-execute-func (funref)
3831 "Internal processing of a batch command, running FUNREF on all command arguments."
3832 (verilog-batch-error-wrapper
3833 ;; General globals needed
3834 (setq make-backup-files nil)
3835 (setq-default make-backup-files nil)
3836 (setq enable-local-variables t)
3837 (setq enable-local-eval t)
3838 ;; Make sure any sub-files we read get proper mode
3839 (setq default-major-mode `verilog-mode)
3840 ;; Ditto files already read in
3841 (mapcar '(lambda (buf)
3842 (when (buffer-file-name buf)
3847 ;; Process the files
3848 (mapcar '(lambda (buf)
3849 (when (buffer-file-name buf)
3851 (if (not (file-exists-p (buffer-file-name buf)))
3852 (error (concat "File not found: " (buffer-file-name buf))))
3853 (message (concat "Processing " (buffer-file-name buf)))
3859 (defun verilog-batch-auto ()
3860 "For use with --batch, perform automatic expansions as a stand-alone tool.
3861 This sets up the appropriate Verilog-Mode environment, updates automatics
3862 with \\[verilog-auto] on all command-line files, and saves the buffers.
3863 For proper results, multiple filenames need to be passed on the command
3864 line in bottom-up order."
3865 (unless noninteractive
3866 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3867 (verilog-batch-execute-func `verilog-auto))
3869 (defun verilog-batch-delete-auto ()
3870 "For use with --batch, perform automatic deletion as a stand-alone tool.
3871 This sets up the appropriate Verilog-Mode environment, deletes automatics
3872 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
3873 (unless noninteractive
3874 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3875 (verilog-batch-execute-func `verilog-delete-auto))
3877 (defun verilog-batch-inject-auto ()
3878 "For use with --batch, perform automatic injection as a stand-alone tool.
3879 This sets up the appropriate Verilog-Mode environment, injects new automatics
3880 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
3881 For proper results, multiple filenames need to be passed on the command
3882 line in bottom-up order."
3883 (unless noninteractive
3884 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3885 (verilog-batch-execute-func `verilog-inject-auto))
3887 (defun verilog-batch-indent ()
3888 "For use with --batch, reindent an a entire file as a stand-alone tool.
3889 This sets up the appropriate Verilog-Mode environment, calls
3890 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
3891 (unless noninteractive
3892 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
3893 (verilog-batch-execute-func `verilog-indent-buffer))
3899 (defconst verilog-indent-alist
3900 '((block . (+ ind verilog-indent-level))
3901 (case . (+ ind verilog-case-indent))
3902 (cparenexp . (+ ind verilog-indent-level))
3903 (cexp . (+ ind verilog-cexp-indent))
3904 (defun . verilog-indent-level-module)
3905 (declaration . verilog-indent-level-declaration)
3906 (directive . (verilog-calculate-indent-directive))
3907 (tf . verilog-indent-level)
3908 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
3911 (comment . (verilog-comment-indent))
3915 (defun verilog-continued-line-1 (lim)
3916 "Return true if this is a continued line.
3917 Set point to where line starts. Limit search to point LIM."
3918 (let ((continued 't))
3919 (if (eq 0 (forward-line -1))
3922 (verilog-backward-ws&directives lim)
3924 (setq continued nil)
3925 (setq continued (verilog-backward-token))))
3926 (setq continued nil))
3929 (defun verilog-calculate-indent ()
3930 "Calculate the indent of the current Verilog line.
3931 Examine previous lines. Once a line is found that is definitive as to the
3932 type of the current line, return that lines' indent level and its
3933 type. Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
3935 (let* ((starting_position (point))
3937 (begin (looking-at "[ \t]*begin\\>"))
3938 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
3939 (type (catch 'nesting
3940 ;; Keep working backwards until we can figure out
3941 ;; what type of statement this is.
3942 ;; Basically we need to figure out
3943 ;; 1) if this is a continuation of the previous line;
3944 ;; 2) are we in a block scope (begin..end)
3946 ;; if we are in a comment, done.
3947 (if (verilog-in-star-comment-p)
3948 (throw 'nesting 'comment))
3950 ;; if we have a directive, done.
3951 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
3952 (throw 'nesting 'directive))
3954 ;; unless we are in the newfangled coverpoint or constraint blocks
3955 ;; if we are in a parenthesized list, and the user likes to indent these, return.
3957 verilog-indent-lists
3958 (not (verilog-in-coverage))
3961 (throw 'nesting 'block))
3964 ;; See if we are continuing a previous line
3966 ;; trap out if we crawl off the top of the buffer
3967 (if (bobp) (throw 'nesting 'cpp))
3969 (if (verilog-continued-line-1 lim)
3972 (not (looking-at verilog-complete-reg))
3973 (verilog-continued-line-1 lim))
3974 (progn (goto-char sp)
3975 (throw 'nesting 'cexp))
3980 (not verilog-indent-begin-after-if)
3981 (looking-at verilog-no-indent-begin-re))
3984 (skip-chars-forward " \t")
3985 (throw 'nesting 'statement))
3987 (throw 'nesting 'cexp))))
3988 ;; not a continued line
3989 (goto-char starting_position))
3991 (if (looking-at "\\<else\\>")
3992 ;; search back for governing if, striding across begin..end pairs
3995 (while (verilog-re-search-backward verilog-ends-re nil 'move)
3997 ((match-end 1) ; else, we're in deep
3998 (setq elsec (1+ elsec)))
4000 (setq elsec (1- elsec))
4002 (if verilog-align-ifelse
4003 (throw 'nesting 'statement)
4004 (progn ;; back up to first word on this line
4006 (verilog-forward-syntactic-ws)
4007 (throw 'nesting 'statement)))))
4009 ; try to leap back to matching outward block by striding across
4010 ; indent level changing tokens then immediately
4011 ; previous line governs indentation.
4012 (let (( reg) (nest 1))
4013 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
4015 ((match-end 3) ; end
4016 ;; Search back for matching begin
4017 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
4018 ((match-end 4) ; endcase
4019 ;; Search back for matching case
4020 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4021 ((match-end 5) ; endfunction
4022 ;; Search back for matching function
4023 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4024 ((match-end 6) ; endtask
4025 ;; Search back for matching task
4026 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4027 ((match-end 7) ; endspecify
4028 ;; Search back for matching specify
4029 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4030 ((match-end 8) ; endtable
4031 ;; Search back for matching table
4032 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4033 ((match-end 9) ; endgenerate
4034 ;; Search back for matching generate
4035 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4036 ((match-end 10) ; joins
4037 ;; Search back for matching fork
4038 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
4039 ((match-end 11) ; class
4040 ;; Search back for matching class
4041 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4042 ((match-end 12) ; covergroup
4043 ;; Search back for matching covergroup
4044 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4047 (while (verilog-re-search-backward reg nil 'move)
4049 ((match-end 1) ; begin
4050 (setq nest (1- nest))
4053 ((match-end 2) ; end
4054 (setq nest (1+ nest)))))
4058 (throw 'nesting (verilog-calc-1))
4063 ;; Return type of block and indent level.
4066 (if (> par 0) ; Unclosed Parenthesis
4067 (list 'cparenexp par)
4070 (list type (verilog-case-indent-level)))
4071 ((eq type 'statement)
4072 (list type (current-column)))
4076 (list type (verilog-current-indent-level)))))
4078 (defun verilog-wai ()
4079 "Show matching nesting block for debugging."
4082 (let ((nesting (verilog-calc-1)))
4083 (message "You are at nesting %s" nesting))))
4085 (defun verilog-calc-1 ()
4087 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
4089 ((equal (char-after) ?\{)
4090 (if (verilog-at-constraint-p)
4091 (throw 'nesting 'block)
4093 ((equal (char-after) ?\})
4095 (let ((there (verilog-at-close-constraint-p)))
4096 (if there (goto-char there))))
4098 ((looking-at verilog-beg-block-re-ordered)
4100 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4101 (let ((here (point)))
4102 (verilog-beg-of-statement)
4103 (if (looking-at verilog-extended-case-re)
4104 (throw 'nesting 'case)
4106 (throw 'nesting 'case))
4108 ;; need to consider typedef struct here...
4109 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
4110 ; *sigh* These words have an optional prefix:
4111 ; extern {virtual|protected}? function a();
4112 ; assert property (p_1);
4113 ; typedef class foo;
4114 ; and we don't want to confuse this with
4119 (let ((here (point)))
4121 (verilog-beg-of-statement)
4122 (if (= (point) here)
4123 (throw 'nesting 'block))
4125 (t (throw 'nesting 'block))))
4127 ((looking-at verilog-end-block-re)
4128 (verilog-leap-to-head)
4129 (if (verilog-in-case-region-p)
4131 (verilog-leap-to-case-head)
4132 (if (looking-at verilog-case-re)
4133 (throw 'nesting 'case)))))
4135 ((looking-at (if (verilog-in-generate-region-p)
4136 verilog-defun-level-not-generate-re
4137 verilog-defun-level-re))
4138 (throw 'nesting 'defun))
4140 ((looking-at verilog-cpp-level-re)
4141 (throw 'nesting 'cpp))
4144 (throw 'nesting 'cpp))
4146 (throw 'nesting 'cpp)
4150 (defun verilog-calculate-indent-directive ()
4151 "Return indentation level for directive.
4152 For speed, the searcher looks at the last directive, not the indent
4153 of the appropriate enclosing block."
4154 (let ((base -1) ;; Indent of the line that determines our indentation
4155 (ind 0) ;; Relative offset caused by other directives (like `endif on same line as `else)
4157 ;; Start at current location, scan back for another directive
4161 (while (and (< base 0)
4162 (verilog-re-search-backward verilog-directive-re nil t))
4163 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
4164 (setq base (current-indentation))
4166 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4167 (setq ind (- ind verilog-indent-level-directive)))
4168 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4169 (setq ind (+ ind verilog-indent-level-directive)))
4170 ((looking-at verilog-directive-begin)
4171 (setq ind (+ ind verilog-indent-level-directive)))))
4172 ;; Adjust indent to starting indent of critical line
4173 (setq ind (max 0 (+ ind base))))
4177 (skip-chars-forward " \t")
4178 (cond ((or (looking-at verilog-directive-middle)
4179 (looking-at verilog-directive-end))
4180 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
4183 (defun verilog-leap-to-case-head ()
4186 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
4189 (setq nest (1- nest)))
4191 (setq nest (1+ nest)))
4196 (defun verilog-leap-to-head ()
4197 "Move point to the head of this block; jump from end to matching begin,
4198 from endcase to matching case, and so on."
4203 ((looking-at "\\<end\\>")
4204 ;; 1: Search back for matching begin
4205 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4206 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4207 ((looking-at "\\<endcase\\>")
4208 ;; 2: Search back for matching case
4209 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
4210 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
4211 ;; 3: Search back for matching fork
4212 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4213 ((looking-at "\\<endclass\\>")
4214 ;; 4: Search back for matching class
4215 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4216 ((looking-at "\\<endtable\\>")
4217 ;; 5: Search back for matching table
4218 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4219 ((looking-at "\\<endspecify\\>")
4220 ;; 6: Search back for matching specify
4221 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4222 ((looking-at "\\<endfunction\\>")
4223 ;; 7: Search back for matching function
4224 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4225 ((looking-at "\\<endgenerate\\>")
4226 ;; 8: Search back for matching generate
4227 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4228 ((looking-at "\\<endtask\\>")
4229 ;; 9: Search back for matching task
4230 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4231 ((looking-at "\\<endgroup\\>")
4232 ;; 10: Search back for matching covergroup
4233 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4234 ((looking-at "\\<endproperty\\>")
4235 ;; 11: Search back for matching property
4236 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
4237 ((looking-at "\\<endinterface\\>")
4238 ;; 12: Search back for matching interface
4239 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
4240 ((looking-at "\\<endsequence\\>")
4241 ;; 12: Search back for matching sequence
4242 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
4243 ((looking-at "\\<endclocking\\>")
4244 ;; 12: Search back for matching clocking
4245 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))
4250 (while (verilog-re-search-backward reg nil 'move)
4252 ((match-end 1) ; begin
4253 (setq nest (1- nest))
4255 ;; Now previous line describes syntax
4260 ((match-end 2) ; end
4261 (setq nest (1+ nest)))
4263 ;; endcase, jump to case
4265 (setq nest (1+ nest))
4267 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4269 ;; join, jump to fork
4271 (setq nest (1+ nest))
4273 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4276 (defun verilog-continued-line ()
4277 "Return true if this is a continued line.
4278 Set point to where line starts"
4279 (let ((continued 't))
4280 (if (eq 0 (forward-line -1))
4283 (verilog-backward-ws&directives)
4285 (setq continued nil)
4286 (while (and continued
4288 (skip-chars-backward " \t")
4290 (setq continued (verilog-backward-token))
4293 (setq continued nil))
4296 (defun verilog-backward-token ()
4297 "Step backward token, returning true if we are now at an end of line token."
4299 (verilog-backward-syntactic-ws)
4303 (;-- Anything ending in a ; is complete
4304 (= (preceding-char) ?\;)
4306 (; If a "}" is prefixed by a ";", then this is a complete statement
4307 ; i.e.: constraint foo { a = b; }
4308 (= (preceding-char) ?\})
4311 (verilog-at-close-constraint-p))
4313 (;-- constraint foo { a = b }
4314 ; is a complete statement. *sigh*
4315 (= (preceding-char) ?\{)
4318 (not (verilog-at-constraint-p)))
4320 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
4321 ; also could be simply '@(foo)'
4323 ; (b, ... which ISN'T complete
4324 ;;;; Do we need this???
4325 (= (preceding-char) ?\))
4328 (backward-up-list 1)
4329 (verilog-backward-syntactic-ws)
4330 (let ((back (point)))
4333 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
4334 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
4338 ((= (preceding-char) ?\@)
4341 (verilog-backward-token)
4342 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
4343 ((= (preceding-char) ?\#)
4349 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
4353 ((looking-at "\\<else\\>")
4355 ((looking-at verilog-indent-re)
4360 (verilog-backward-syntactic-ws)
4362 ((= (preceding-char) ?\:)
4364 (verilog-backward-syntactic-ws)
4366 (if (looking-at verilog-nameable-item-re )
4370 ((= (preceding-char) ?\#)
4373 ((= (preceding-char) ?\`)
4382 (defun verilog-backward-syntactic-ws (&optional bound)
4383 "Backward skip over syntactic whitespace for Emacs 19.
4384 Optional BOUND limits search."
4386 (let* ((bound (or bound (point-min))) (here bound) )
4387 (if (< bound (point))
4389 (narrow-to-region bound (point))
4390 (while (/= here (point))
4392 (verilog-skip-backward-comments)
4397 (defun verilog-forward-syntactic-ws (&optional bound)
4398 "Forward skip over syntactic whitespace for Emacs 19.
4399 Optional BOUND limits search."
4401 (let* ((bound (or bound (point-max)))
4404 (if (> bound (point))
4406 (narrow-to-region (point) bound)
4407 (while (/= here (point))
4409 (forward-comment (buffer-size))
4413 (defun verilog-backward-ws&directives (&optional bound)
4414 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
4415 Optional BOUND limits search."
4417 (let* ((bound (or bound (point-min)))
4420 (if (< bound (point))
4424 (parse-partial-sexp (point-min) (point)))))
4426 ((nth 7 state) ;; in // comment
4427 (verilog-re-search-backward "//" nil 'move)
4428 (skip-chars-backward "/"))
4429 ((nth 4 state) ;; in /* */ comment
4430 (verilog-re-search-backward "/\*" nil 'move))))
4431 (narrow-to-region bound (point))
4432 (while (/= here (point))
4434 (verilog-skip-backward-comments)
4439 ((verilog-within-translate-off)
4440 (verilog-back-to-start-translate-off (point-min)))
4441 ((looking-at verilog-directive-re-1)
4445 (if p (goto-char p))
4449 (defun verilog-forward-ws&directives (&optional bound)
4450 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
4451 Optional BOUND limits search."
4453 (let* ((bound (or bound (point-max)))
4457 (if (> bound (point))
4461 (parse-partial-sexp (point-min) (point)))))
4463 ((nth 7 state) ;; in // comment
4464 (verilog-re-search-forward "//" nil 'move))
4465 ((nth 4 state) ;; in /* */ comment
4466 (verilog-re-search-forward "/\*" nil 'move))))
4467 (narrow-to-region (point) bound)
4468 (while (/= here (point))
4471 (forward-comment (buffer-size))
4474 (if (looking-at verilog-directive-re-1)
4477 (beginning-of-line 2))
4481 (defun verilog-in-comment-p ()
4482 "Return true if in a star or // comment."
4485 (parse-partial-sexp (point-min) (point)))))
4486 (or (nth 4 state) (nth 7 state))))
4488 (defun verilog-in-star-comment-p ()
4489 "Return true if in a star comment."
4492 (parse-partial-sexp (point-min) (point)))))
4494 (nth 4 state) ; t if in a comment of style a // or b /**/
4496 (nth 7 state) ; t if in a comment of style b /**/
4499 (defun verilog-in-slash-comment-p ()
4500 "Return true if in a slash comment."
4503 (parse-partial-sexp (point-min) (point)))))
4506 (defun verilog-in-comment-or-string-p ()
4507 "Return true if in a string or comment."
4510 (parse-partial-sexp (point-min) (point)))))
4511 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
4513 (defun verilog-in-escaped-name-p ()
4514 "Return true if in an escaped name."
4517 (skip-chars-backward "^ \t\n\f")
4518 (if (equal (char-after (point) ) ?\\ )
4522 (defun verilog-in-paren ()
4523 "Return true if in a parenthetical expression."
4526 (parse-partial-sexp (point-min) (point)))))
4527 (> (nth 0 state) 0 )))
4529 (defun verilog-in-coverage ()
4530 "Return true if in a constraint or coverpoint expression."
4533 (if (verilog-in-paren)
4535 (backward-up-list 1)
4536 (verilog-at-constraint-p)
4539 (defun verilog-at-close-constraint-p ()
4540 "If at the } that closes a constraint or covergroup, return true."
4542 (equal (char-after) ?\})
4546 (verilog-backward-ws&directives)
4547 (if (equal (char-before) ?\;)
4551 (defun verilog-at-constraint-p ()
4552 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
4555 (equal (char-after) ?\{)
4557 (progn (backward-char 1)
4558 (verilog-backward-ws&directives)
4559 (equal (char-before) ?\;))
4562 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
4568 (defun verilog-parenthesis-depth ()
4569 "Return non zero if in parenthetical-expression."
4571 (nth 1 (parse-partial-sexp (point-min) (point)))))
4574 (defun verilog-skip-forward-comment-or-string ()
4575 "Return true if in a string or comment."
4578 (parse-partial-sexp (point-min) (point)))))
4580 ((nth 3 state) ;Inside string
4581 (goto-char (nth 3 state))
4583 ((nth 7 state) ;Inside // comment
4586 ((nth 4 state) ;Inside any comment (hence /**/)
4587 (search-forward "*/"))
4591 (defun verilog-skip-backward-comment-or-string ()
4592 "Return true if in a string or comment."
4595 (parse-partial-sexp (point-min) (point)))))
4597 ((nth 3 state) ;Inside string
4598 (search-backward "\"")
4600 ((nth 7 state) ;Inside // comment
4601 (search-backward "//")
4602 (skip-chars-backward "/")
4604 ((nth 4 state) ;Inside /* */ comment
4605 (search-backward "/*")
4610 (defun verilog-skip-backward-comments ()
4611 "Return true if a comment was skipped."
4617 (parse-partial-sexp (point-min) (point)))))
4619 ((nth 7 state) ;Inside // comment
4620 (search-backward "//")
4621 (skip-chars-backward "/")
4622 (skip-chars-backward " \t\n\f")
4624 ((nth 4 state) ;Inside /* */ comment
4625 (search-backward "/*")
4626 (skip-chars-backward " \t\n\f")
4629 (= (char-before) ?\/)
4630 (= (char-before (1- (point))) ?\*)
4632 (goto-char (- (point) 2))
4635 (skip-chars-backward " \t\n\f")
4638 (defun verilog-skip-forward-comment-p ()
4639 "If in comment, move to end and return true."
4644 (parse-partial-sexp (point-min) (point))))
4648 ((nth 7 state) ;Inside // comment
4652 ((nth 4 state) ;Inside any comment
4657 (defun verilog-indent-line-relative ()
4658 "Cheap version of indent line.
4659 Only look at a few lines to determine indent level."
4663 (if (looking-at "^[ \t]*$")
4664 (cond ;- A blank line; No need to be too smart.
4666 (setq indent-str (list 'cpp 0)))
4667 ((verilog-continued-line)
4668 (let ((sp1 (point)))
4669 (if (verilog-continued-line)
4670 (progn (goto-char sp)
4671 (setq indent-str (list 'statement (verilog-current-indent-level))))
4673 (setq indent-str (list 'block (verilog-current-indent-level)))))
4676 (setq indent-str (verilog-calculate-indent))))
4677 (progn (skip-chars-forward " \t")
4678 (setq indent-str (verilog-calculate-indent))))
4679 (verilog-do-indent indent-str)))
4681 (defun verilog-indent-line ()
4682 "Indent for special part of code."
4683 (verilog-do-indent (verilog-calculate-indent)))
4685 (defun verilog-do-indent (indent-str)
4686 (let ((type (car indent-str))
4687 (ind (car (cdr indent-str))))
4689 (; handle continued exp
4691 (let ((here (point)))
4692 (verilog-backward-syntactic-ws)
4695 (= (preceding-char) ?\,)
4696 (= (preceding-char) ?\])
4698 (verilog-beg-of-statement-1)
4699 (looking-at verilog-declaration-re)))
4704 (verilog-beg-of-statement-1)
4706 (if (looking-at verilog-declaration-re)
4707 (progn ;; we have multiple words
4708 (goto-char (match-end 0))
4709 (skip-chars-forward " \t")
4711 ((and verilog-indent-declaration-macros
4712 (= (following-char) ?\`))
4716 (skip-chars-forward " \t")))
4717 ((= (following-char) ?\[)
4720 (backward-up-list -1)
4721 (skip-chars-forward " \t")))
4726 (+ (current-column) verilog-cexp-indent))
4729 (indent-line-to val))
4731 ((= (preceding-char) ?\) )
4733 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4734 (indent-line-to val)))
4738 (verilog-beg-of-statement-1)
4739 (if (and (< (point) here)
4740 (verilog-re-search-forward "=[ \\t]*" here 'move))
4741 (setq val (current-column))
4742 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
4744 (indent-line-to val)))
4747 (; handle inside parenthetical expressions
4748 (eq type 'cparenexp)
4749 (let ((val (save-excursion
4750 (backward-up-list 1)
4752 (skip-chars-forward " \t")
4754 (indent-line-to val)
4755 (if (and (not (verilog-in-struct-region-p))
4756 (looking-at verilog-declaration-re))
4757 (verilog-indent-declaration ind))
4760 (;-- Handle the ends
4762 (looking-at verilog-end-block-re )
4763 (verilog-at-close-constraint-p))
4764 (let ((val (if (eq type 'statement)
4765 (- ind verilog-indent-level)
4767 (indent-line-to val)))
4769 (;-- Case -- maybe line 'em up
4770 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
4773 ((looking-at "\\<endcase\\>")
4774 (indent-line-to ind))
4776 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4777 (indent-line-to val))))))
4780 (and (eq type 'defun)
4781 (looking-at verilog-zero-indent-re))
4788 (looking-at verilog-declaration-re))
4789 (verilog-indent-declaration ind))
4791 (;-- Everything else
4793 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4794 (indent-line-to val)))
4796 (if (looking-at "[ \t]+$")
4797 (skip-chars-forward " \t"))
4798 indent-str ; Return indent data
4801 (defun verilog-current-indent-level ()
4802 "Return the indent-level the current statement has."
4806 (setq par-pos (verilog-parenthesis-depth))
4810 (setq par-pos (verilog-parenthesis-depth)))
4811 (skip-chars-forward " \t")
4814 (defun verilog-case-indent-level ()
4815 "Return the indent-level the current statement has.
4816 Do not count named blocks or case-statements."
4818 (skip-chars-forward " \t")
4820 ((looking-at verilog-named-block-re)
4822 ((and (not (looking-at verilog-case-re))
4823 (looking-at "^[^:;]+[ \t]*:"))
4824 (verilog-re-search-forward ":" nil t)
4825 (skip-chars-forward " \t")
4828 (current-column)))))
4830 (defun verilog-indent-comment ()
4831 "Indent current line as comment."
4834 ((verilog-in-star-comment-p)
4836 (re-search-backward "/\\*" nil t)
4837 (1+(current-column))))
4842 (re-search-backward "//" nil t)
4845 (indent-line-to stcol)
4848 (defun verilog-more-comment ()
4849 "Make more comment lines like the previous."
4853 ((verilog-in-star-comment-p)
4856 (re-search-backward "/\\*" nil t)
4857 (1+(current-column))))
4862 (re-search-backward "//" nil t)
4870 (skip-chars-forward " \t")
4874 (defun verilog-comment-indent (&optional arg)
4875 "Return the column number the line should be indented to.
4876 ARG is ignored, for `comment-indent-function' compatibility."
4878 ((verilog-in-star-comment-p)
4880 (re-search-backward "/\\*" nil t)
4881 (1+(current-column))))
4886 (re-search-backward "//" nil t)
4887 (current-column)))))
4891 (defun verilog-pretty-declarations ()
4892 "Line up declarations around point."
4896 (verilog-beg-of-statement-1)
4897 (looking-at verilog-declaration-re))
4898 (let* ((m1 (make-marker))
4901 ;; Start of declaration range
4904 (verilog-beg-of-statement-1)
4905 (while (looking-at verilog-declaration-re)
4908 (verilog-backward-syntactic-ws)
4910 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
4912 ;; End of declaration range
4916 (verilog-end-of-statement)
4917 (setq e (point)) ;Might be on last line
4918 (verilog-forward-syntactic-ws)
4919 (while (looking-at verilog-declaration-re)
4921 (verilog-end-of-statement)
4923 (verilog-forward-syntactic-ws))
4925 (edpos (set-marker (make-marker) end))
4930 (verilog-do-indent (verilog-calculate-indent))
4931 (verilog-forward-ws&directives)
4936 (if (> (- end start) 100)
4937 (message "Lining up declarations..(please stand by)"))
4938 ;; Get the beginning of line indent first
4939 (while (progn (setq e (marker-position edpos))
4942 ( (save-excursion (skip-chars-backward " \t")
4944 (verilog-forward-ws&directives)
4945 (indent-line-to base-ind)
4946 (verilog-forward-ws&directives)
4947 (verilog-re-search-forward "[ \t\n\f]" e 'move)
4951 (verilog-re-search-forward "[ \t\n\f]" e 'move)
4956 ;; Now find biggest prefix
4957 (setq ind (verilog-get-lineup-indent start edpos))
4958 ;; Now indent each line.
4960 (while (progn (setq e (marker-position edpos))
4961 (setq r (- e (point)))
4966 ((or (and verilog-indent-declaration-macros
4967 (looking-at verilog-declaration-re-1-macro))
4968 (looking-at verilog-declaration-re-1-no-macro))
4969 (let ((p (match-end 0)))
4971 (if (verilog-re-search-forward "[[#`]" p 'move)
4975 (goto-char (marker-position m1))
4982 ((verilog-continued-line-1 start)
4984 (indent-line-to ind))
4985 (t ; Must be comment or white space
4987 (verilog-forward-ws&directives)
4993 (defun verilog-pretty-expr (&optional myre)
4994 "Line up expressions around point."
4995 (interactive "sRegular Expression: ((<|:)?=) ")
4997 (if (or (eq myre nil)
4998 (string-equal myre ""))
4999 (setq myre "\\(<\\|:\\)?="))
5000 ; (setq myre (concat "\\(^[^;" myre "]*\\)\\([" myre "]\\)"))
5001 (setq myre (concat "\\(^[^;#:?=]*\\)\\([" myre "]\\)"))
5003 (if (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
5005 (let* ((here (point))
5011 (verilog-backward-syntactic-ws)
5013 (while (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
5018 (verilog-backward-syntactic-ws)
5020 ) ;Ack, need to grok `define
5026 (setq e (point)) ;Might be on last line
5027 (verilog-forward-syntactic-ws)
5029 (while (and (not(looking-at (concat "^\\s-*" verilog-complete-reg)))
5033 (verilog-forward-syntactic-ws)
5037 (edpos (set-marker (make-marker) end))
5041 (verilog-do-indent (verilog-calculate-indent))
5042 (if (> (- end start) 100)
5043 (message "Lining up expressions..(please stand by)"))
5045 ;; Set indent to minimum throughout region
5046 (while (< (point) (marker-position edpos))
5048 (verilog-just-one-space myre)
5050 (verilog-forward-syntactic-ws)
5053 ;; Now find biggest prefix
5054 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
5056 ;; Now indent each line.
5058 (while (progn (setq e (marker-position edpos))
5059 (setq r (- e (point)))
5065 (goto-char (match-end 1))
5066 (if (eq (char-after) ?=)
5067 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
5071 ((verilog-continued-line-1 start)
5073 (indent-line-to ind))
5074 (t ; Must be comment or white space
5076 (verilog-forward-ws&directives)
5083 (defun verilog-just-one-space (myre)
5084 "Remove extra spaces around regular expression MYRE."
5086 (if (and (not(looking-at verilog-complete-reg))
5088 (let ((p1 (match-end 1))
5092 (if (looking-at "\\s-") (just-one-space) )
5095 (if (looking-at "\\s-") (just-one-space))
5100 (defun verilog-indent-declaration (baseind)
5101 "Indent current lines as declaration.
5102 Line up the variable names based on previous declaration's indentation.
5103 BASEIND is the base indent to offset everything."
5105 (let ((pos (point-marker))
5106 (lim (save-excursion
5107 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
5108 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
5114 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5115 (indent-line-to val)
5117 ;; Use previous declaration (in this module) as template.
5118 (if (or (memq 'all verilog-auto-lineup)
5119 (memq 'declaration verilog-auto-lineup))
5120 (if (verilog-re-search-backward
5121 (or (and verilog-indent-declaration-macros
5122 verilog-declaration-re-1-macro)
5123 verilog-declaration-re-1-no-macro) lim t)
5125 (goto-char (match-end 0))
5126 (skip-chars-forward " \t")
5127 (setq ind (current-column))
5129 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5130 (indent-line-to val)
5131 (if (and verilog-indent-declaration-macros
5132 (looking-at verilog-declaration-re-2-macro))
5133 (let ((p (match-end 0)))
5135 (if (verilog-re-search-forward "[[#`]" p 'move)
5139 (goto-char (marker-position m1))
5143 (if (/= (current-column) ind)
5148 (if (looking-at verilog-declaration-re-2-no-macro)
5149 (let ((p (match-end 0)))
5151 (if (verilog-re-search-forward "[[`#]" p 'move)
5155 (goto-char (marker-position m1))
5158 (if (/= (current-column) ind)
5170 (defun verilog-get-lineup-indent (b edpos)
5171 "Return the indent level that will line up several lines within the region.
5172 Region is defined by B and EDPOS."
5176 ;; Get rightmost position
5177 (while (progn (setq e (marker-position edpos))
5179 (if (verilog-re-search-forward
5180 (or (and verilog-indent-declaration-macros
5181 verilog-declaration-re-1-macro)
5182 verilog-declaration-re-1-no-macro) e 'move)
5184 (goto-char (match-end 0))
5185 (verilog-backward-syntactic-ws)
5186 (if (> (current-column) ind)
5187 (setq ind (current-column)))
5188 (goto-char (match-end 0)))))
5191 ;; No lineup-string found
5194 (skip-chars-backward " \t")
5195 (1+ (current-column))))))
5197 (defun verilog-get-lineup-indent-2 (myre b edpos)
5198 "Return the indent level that will line up several lines within the region."
5202 ;; Get rightmost position
5203 (while (progn (setq e (marker-position edpos))
5205 (if (verilog-re-search-forward myre e 'move)
5207 (goto-char (match-end 0))
5208 (verilog-backward-syntactic-ws)
5209 (if (> (current-column) ind)
5210 (setq ind (current-column)))
5211 (goto-char (match-end 0)))))
5214 ;; No lineup-string found
5217 (skip-chars-backward " \t")
5218 (1+ (current-column))))))
5220 (defun verilog-comment-depth (type val)
5221 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
5229 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
5231 (replace-match " /* -# ## */")
5235 (insert " /* ## ## */"))))
5238 (format "%s %d" type val))))
5244 (defvar verilog-str nil)
5245 (defvar verilog-all nil)
5246 (defvar verilog-pred nil)
5247 (defvar verilog-buffer-to-use nil)
5248 (defvar verilog-flag nil)
5249 (defvar verilog-toggle-completions nil
5250 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
5251 Repeated use of \\[verilog-complete-word] will show you all of them.
5252 Normally, when there is more than one possible completion,
5253 it displays a list of all possible completions.")
5256 (defvar verilog-type-keywords
5258 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
5259 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
5260 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
5261 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
5262 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
5263 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
5265 "*Keywords for types used when completing a word in a declaration or parmlist.
5266 \(eg. integer, real, reg...)")
5268 (defvar verilog-cpp-keywords
5269 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
5271 "*Keywords to complete when at first word of a line in declarative scope.
5272 \(eg. initial, always, begin, assign.)
5273 The procedures and variables defined within the Verilog program
5274 will be completed runtime and should not be added to this list.")
5276 (defvar verilog-defun-keywords
5279 "always" "always_comb" "always_ff" "always_latch" "assign"
5280 "begin" "end" "generate" "endgenerate" "module" "endmodule"
5281 "specify" "endspecify" "function" "endfunction" "initial" "final"
5282 "task" "endtask" "primitive" "endprimitive"
5284 verilog-type-keywords)
5285 "*Keywords to complete when at first word of a line in declarative scope.
5286 \(eg. initial, always, begin, assign.)
5287 The procedures and variables defined within the Verilog program
5288 will be completed runtime and should not be added to this list.")
5290 (defvar verilog-block-keywords
5292 "begin" "break" "case" "continue" "else" "end" "endfunction"
5293 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
5294 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
5296 "*Keywords to complete when at first word of a line in behavioral scope.
5297 \(eg. begin, if, then, else, for, fork.)
5298 The procedures and variables defined within the Verilog program
5299 will be completed runtime and should not be added to this list.")
5301 (defvar verilog-tf-keywords
5302 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
5303 "*Keywords to complete when at first word of a line in a task or function.
5304 \(eg. begin, if, then, else, for, fork.)
5305 The procedures and variables defined within the Verilog program
5306 will be completed runtime and should not be added to this list.")
5308 (defvar verilog-case-keywords
5309 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
5310 "*Keywords to complete when at first word of a line in case scope.
5311 \(eg. begin, if, then, else, for, fork.)
5312 The procedures and variables defined within the Verilog program
5313 will be completed runtime and should not be added to this list.")
5315 (defvar verilog-separator-keywords
5316 '("else" "then" "begin")
5317 "*Keywords to complete when NOT standing at the first word of a statement.
5319 Variables and function names defined within the
5320 Verilog program are completed runtime and should not be added to this list.")
5322 (defun verilog-string-diff (str1 str2)
5323 "Return index of first letter where STR1 and STR2 differs."
5327 (if (or (> (1+ diff) (length str1))
5328 (> (1+ diff) (length str2)))
5330 (or (equal (aref str1 diff) (aref str2 diff))
5332 (setq diff (1+ diff))))))
5334 ;; Calculate all possible completions for functions if argument is `function',
5335 ;; completions for procedures if argument is `procedure' or both functions and
5336 ;; procedures otherwise.
5338 (defun verilog-func-completion (type)
5339 "Build regular expression for module/task/function names.
5340 TYPE is 'module, 'tf for task or function, or t if unknown."
5341 (if (string= verilog-str "")
5342 (setq verilog-str "[a-zA-Z_]"))
5343 (let ((verilog-str (concat (cond
5344 ((eq type 'module) "\\<\\(module\\)\\s +")
5345 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
5346 (t "\\<\\(task\\|function\\|module\\)\\s +"))
5347 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
5350 (if (not (looking-at verilog-defun-re))
5351 (verilog-re-search-backward verilog-defun-re nil t))
5354 ;; Search through all reachable functions
5355 (goto-char (point-min))
5356 (while (verilog-re-search-forward verilog-str (point-max) t)
5357 (progn (setq match (buffer-substring (match-beginning 2)
5359 (if (or (null verilog-pred)
5360 (funcall verilog-pred match))
5361 (setq verilog-all (cons match verilog-all)))))
5362 (if (match-beginning 0)
5363 (goto-char (match-beginning 0)))))
5365 (defun verilog-get-completion-decl (end)
5366 "Macro for searching through current declaration (var, type or const)
5367 for matches of `str' and adding the occurrence tp `all' through point END."
5368 (let ((re (or (and verilog-indent-declaration-macros
5369 verilog-declaration-re-2-macro)
5370 verilog-declaration-re-2-no-macro))
5373 (while (and (< (point) end)
5374 (verilog-re-search-forward re end t))
5375 ;; Traverse current line
5376 (setq decl-end (save-excursion (verilog-declaration-end)))
5377 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
5378 (not (match-end 1)))
5379 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
5380 (if (string-match (concat "\\<" verilog-str) match)
5381 (if (or (null verilog-pred)
5382 (funcall verilog-pred match))
5383 (setq verilog-all (cons match verilog-all)))))
5390 (defun verilog-type-completion ()
5391 "Calculate all possible completions for types."
5392 (let ((start (point))
5394 ;; Search for all reachable type declarations
5395 (while (or (verilog-beg-of-defun)
5396 (setq goon (not goon)))
5398 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
5401 (verilog-re-search-forward
5402 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
5404 (not (match-end 1)))
5405 ;; Check current type declaration
5406 (verilog-get-completion-decl start))))))
5408 (defun verilog-var-completion ()
5409 "Calculate all possible completions for variables (or constants)."
5410 (let ((start (point)))
5411 ;; Search for all reachable var declarations
5412 (verilog-beg-of-defun)
5414 ;; Check var declarations
5415 (verilog-get-completion-decl start))))
5417 (defun verilog-keyword-completion (keyword-list)
5418 "Give list of all possible completions of keywords in KEYWORD-LIST."
5419 (mapcar '(lambda (s)
5420 (if (string-match (concat "\\<" verilog-str) s)
5421 (if (or (null verilog-pred)
5422 (funcall verilog-pred s))
5423 (setq verilog-all (cons s verilog-all)))))
5427 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
5428 "Function passed to `completing-read', `try-completion' or `all-completions'.
5429 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
5430 must be a function to be called for every match to check if this should
5431 really be a match. If VERILOG-FLAG is t, the function returns a list of all
5432 possible completions. If VERILOG-FLAG is nil it returns a string, the
5433 longest possible completion, or t if STR is an exact match. If VERILOG-FLAG
5434 is 'lambda, the function returns t if STR is an exact match, nil
5437 (let ((verilog-all nil))
5438 ;; Set buffer to use for searching labels. This should be set
5439 ;; within functions which use verilog-completions
5440 (set-buffer verilog-buffer-to-use)
5442 ;; Determine what should be completed
5443 (let ((state (car (verilog-calculate-indent))))
5444 (cond ((eq state 'defun)
5445 (save-excursion (verilog-var-completion))
5446 (verilog-func-completion 'module)
5447 (verilog-keyword-completion verilog-defun-keywords))
5449 ((eq state 'behavioral)
5450 (save-excursion (verilog-var-completion))
5451 (verilog-func-completion 'module)
5452 (verilog-keyword-completion verilog-defun-keywords))
5455 (save-excursion (verilog-var-completion))
5456 (verilog-func-completion 'tf)
5457 (verilog-keyword-completion verilog-block-keywords))
5460 (save-excursion (verilog-var-completion))
5461 (verilog-func-completion 'tf)
5462 (verilog-keyword-completion verilog-case-keywords))
5465 (save-excursion (verilog-var-completion))
5466 (verilog-func-completion 'tf)
5467 (verilog-keyword-completion verilog-tf-keywords))
5470 (save-excursion (verilog-var-completion))
5471 (verilog-keyword-completion verilog-cpp-keywords))
5473 ((eq state 'cparenexp)
5474 (save-excursion (verilog-var-completion)))
5477 (save-excursion (verilog-var-completion))
5478 (verilog-func-completion 'both)
5479 (verilog-keyword-completion verilog-separator-keywords))))
5481 ;; Now we have built a list of all matches. Give response to caller
5482 (verilog-completion-response))))
5484 (defun verilog-completion-response ()
5485 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
5486 ;; This was not called by all-completions
5487 (if (null verilog-all)
5488 ;; Return nil if there was no matching label
5490 ;; Get longest string common in the labels
5491 (let* ((elm (cdr verilog-all))
5492 (match (car verilog-all))
5493 (min (length match))
5495 (if (string= match verilog-str)
5496 ;; Return t if first match was an exact match
5498 (while (not (null elm))
5499 ;; Find longest common string
5500 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
5503 (setq match (substring match 0 min))))
5504 ;; Terminate with match=t if this is an exact match
5505 (if (string= (car elm) verilog-str)
5509 (setq elm (cdr elm)))))
5510 ;; If this is a test just for exact match, return nil ot t
5511 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
5514 ;; If flag is t, this was called by all-completions. Return
5515 ;; list of all possible completions
5519 (defvar verilog-last-word-numb 0)
5520 (defvar verilog-last-word-shown nil)
5521 (defvar verilog-last-completions nil)
5523 (defun verilog-complete-word ()
5524 "Complete word at current point.
5525 \(See also `verilog-toggle-completions', `verilog-type-keywords',
5526 and `verilog-separator-keywords'.)"
5528 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5529 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5530 (verilog-str (buffer-substring b e))
5531 ;; The following variable is used in verilog-completion
5532 (verilog-buffer-to-use (current-buffer))
5533 (allcomp (if (and verilog-toggle-completions
5534 (string= verilog-last-word-shown verilog-str))
5535 verilog-last-completions
5536 (all-completions verilog-str 'verilog-completion)))
5537 (match (if verilog-toggle-completions
5539 verilog-str (mapcar '(lambda (elm)
5540 (cons elm 0)) allcomp)))))
5541 ;; Delete old string
5544 ;; Toggle-completions inserts whole labels
5545 (if verilog-toggle-completions
5547 ;; Update entry number in list
5548 (setq verilog-last-completions allcomp
5549 verilog-last-word-numb
5550 (if (>= verilog-last-word-numb (1- (length allcomp)))
5552 (1+ verilog-last-word-numb)))
5553 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
5554 ;; Display next match or same string if no match was found
5555 (if (not (null allcomp))
5556 (insert "" verilog-last-word-shown)
5557 (insert "" verilog-str)
5558 (message "(No match)")))
5559 ;; The other form of completion does not necessarily do that.
5561 ;; Insert match if found, or the original string if no match
5562 (if (or (null match) (equal match 't))
5563 (progn (insert "" verilog-str)
5564 (message "(No match)"))
5566 ;; Give message about current status of completion
5567 (cond ((equal match 't)
5568 (if (not (null (cdr allcomp)))
5569 (message "(Complete but not unique)")
5570 (message "(Sole completion)")))
5571 ;; Display buffer if the current completion didn't help
5572 ;; on completing the label.
5573 ((and (not (null (cdr allcomp))) (= (length verilog-str)
5575 (with-output-to-temp-buffer "*Completions*"
5576 (display-completion-list allcomp))
5577 ;; Wait for a key press. Then delete *Completion* window
5578 (momentary-string-display "" (point))
5579 (delete-window (get-buffer-window (get-buffer "*Completions*")))
5582 (defun verilog-show-completions ()
5583 "Show all possible completions at current point."
5585 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5586 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5587 (verilog-str (buffer-substring b e))
5588 ;; The following variable is used in verilog-completion
5589 (verilog-buffer-to-use (current-buffer))
5590 (allcomp (if (and verilog-toggle-completions
5591 (string= verilog-last-word-shown verilog-str))
5592 verilog-last-completions
5593 (all-completions verilog-str 'verilog-completion))))
5594 ;; Show possible completions in a temporary buffer.
5595 (with-output-to-temp-buffer "*Completions*"
5596 (display-completion-list allcomp))
5597 ;; Wait for a key press. Then delete *Completion* window
5598 (momentary-string-display "" (point))
5599 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
5602 (defun verilog-get-default-symbol ()
5603 "Return symbol around current point as a string."
5605 (buffer-substring (progn
5606 (skip-chars-backward " \t")
5607 (skip-chars-backward "a-zA-Z0-9_")
5610 (skip-chars-forward "a-zA-Z0-9_")
5613 (defun verilog-build-defun-re (str &optional arg)
5614 "Return function/task/module starting with STR as regular expression.
5615 With optional second ARG non-nil, STR is the complete name of the instruction."
5617 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
5618 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
5620 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
5621 "Function passed to `completing-read', `try-completion' or `all-completions'.
5622 Returns a completion on any function name based on VERILOG-STR prefix. If
5623 VERILOG-PRED is non-nil, it must be a function to be called for every match
5624 to check if this should really be a match. If VERILOG-FLAG is t, the
5625 function returns a list of all possible completions. If it is nil it
5626 returns a string, the longest possible completion, or t if VERILOG-STR is
5627 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
5628 VERILOG-STR is an exact match, nil otherwise."
5630 (let ((verilog-all nil)
5633 ;; Set buffer to use for searching labels. This should be set
5634 ;; within functions which use verilog-completions
5635 (set-buffer verilog-buffer-to-use)
5637 (let ((verilog-str verilog-str))
5638 ;; Build regular expression for functions
5639 (if (string= verilog-str "")
5640 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
5641 (setq verilog-str (verilog-build-defun-re verilog-str)))
5642 (goto-char (point-min))
5644 ;; Build a list of all possible completions
5645 (while (verilog-re-search-forward verilog-str nil t)
5646 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
5647 (if (or (null verilog-pred)
5648 (funcall verilog-pred match))
5649 (setq verilog-all (cons match verilog-all)))))
5651 ;; Now we have built a list of all matches. Give response to caller
5652 (verilog-completion-response))))
5654 (defun verilog-goto-defun ()
5655 "Move to specified Verilog module/task/function.
5656 The default is a name found in the buffer around point.
5657 If search fails, other files are checked based on
5658 `verilog-library-flags'."
5660 (let* ((default (verilog-get-default-symbol))
5661 ;; The following variable is used in verilog-comp-function
5662 (verilog-buffer-to-use (current-buffer))
5663 (label (if (not (string= default ""))
5664 ;; Do completion with default
5665 (completing-read (concat "Label: (default " default ") ")
5666 'verilog-comp-defun nil nil "")
5667 ;; There is no default value. Complete without it
5668 (completing-read "Label: "
5669 'verilog-comp-defun nil nil "")))
5671 ;; If there was no response on prompt, use default value
5672 (if (string= label "")
5673 (setq label default))
5674 ;; Goto right place in buffer if label is not an empty string
5675 (or (string= label "")
5678 (goto-char (point-min))
5679 (setq pt (re-search-forward (verilog-build-defun-re label t) nil t)))
5682 (beginning-of-line))
5684 (verilog-goto-defun-file label)
5687 ;; Eliminate compile warning
5689 (if (not (boundp 'occur-pos-list))
5690 (defvar occur-pos-list nil "Backward compatibility occur positions.")))
5692 (defun verilog-showscopes ()
5693 "List all scopes in this module."
5695 (let ((buffer (current-buffer))
5699 (prevpos (point-min))
5700 (final-context-start (make-marker))
5701 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")
5703 (with-output-to-temp-buffer "*Occur*"
5705 (message (format "Searching for %s ..." regexp))
5706 ;; Find next match, but give up if prev match was at end of buffer.
5707 (while (and (not (= prevpos (point-max)))
5708 (verilog-re-search-forward regexp nil t))
5709 (goto-char (match-beginning 0))
5712 (setq linenum (+ linenum (count-lines prevpos (point)))))
5713 (setq prevpos (point))
5714 (goto-char (match-end 0))
5715 (let* ((start (save-excursion
5716 (goto-char (match-beginning 0))
5717 (forward-line (if (< nlines 0) nlines (- nlines)))
5719 (end (save-excursion
5720 (goto-char (match-end 0))
5722 (forward-line (1+ nlines))
5725 (tag (format "%3d" linenum))
5726 (empty (make-string (length tag) ?\ ))
5729 (setq tem (make-marker))
5730 (set-marker tem (point))
5731 (set-buffer standard-output)
5732 (setq occur-pos-list (cons tem occur-pos-list))
5733 (or first (zerop nlines)
5734 (insert "--------\n"))
5736 (insert-buffer-substring buffer start end)
5737 (backward-char (- end start))
5738 (setq tem (if (< nlines 0) (- nlines) nlines))
5742 (setq tem (1- tem)))
5743 (let ((this-linenum linenum))
5744 (set-marker final-context-start
5745 (+ (point) (- (match-end 0) (match-beginning 0))))
5746 (while (< (point) final-context-start)
5748 (setq tag (format "%3d" this-linenum)))
5749 (insert tag ?:)))))))
5750 (set-buffer-modified-p nil))))
5753 ;; Highlight helper functions
5754 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
5755 (defun verilog-within-translate-off ()
5756 "Return point if within translate-off region, else nil."
5757 (and (save-excursion
5759 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
5761 (equal "off" (match-string 2))
5764 (defun verilog-start-translate-off (limit)
5765 "Return point before translate-off directive if before LIMIT, else nil."
5766 (when (re-search-forward
5767 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5769 (match-beginning 0)))
5771 (defun verilog-back-to-start-translate-off (limit)
5772 "Return point before translate-off directive if before LIMIT, else nil."
5773 (when (re-search-backward
5774 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5776 (match-beginning 0)))
5778 (defun verilog-end-translate-off (limit)
5779 "Return point after translate-on directive if before LIMIT, else nil."
5781 (re-search-forward (concat
5782 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
5784 (defun verilog-match-translate-off (limit)
5785 "Match a translate-off block, setting `match-data' and returning t, else nil.
5786 Bound search by LIMIT."
5787 (when (< (point) limit)
5788 (let ((start (or (verilog-within-translate-off)
5789 (verilog-start-translate-off limit)))
5790 (case-fold-search t))
5792 (let ((end (or (verilog-end-translate-off limit) limit)))
5793 (set-match-data (list start end))
5794 (goto-char end))))))
5796 (defun verilog-font-lock-match-item (limit)
5797 "Match, and move over, any declaration item after point.
5798 Bound search by LIMIT. Adapted from
5799 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
5802 (narrow-to-region (point-min) limit)
5804 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
5806 (goto-char (match-end 1))
5807 ;; move to next item
5808 (if (looking-at "\\(\\s-*,\\)")
5809 (goto-char (match-end 1))
5814 ;; Added by Subbu Meiyappan for Header
5816 (defun verilog-header ()
5817 "Insert a standard Verilog file header."
5819 (let ((start (point)))
5821 //-----------------------------------------------------------------------------
5823 // Project : <project>
5824 //-----------------------------------------------------------------------------
5825 // File : <filename>
5826 // Author : <author>
5827 // Created : <credate>
5828 // Last modified : <moddate>
5829 //-----------------------------------------------------------------------------
5832 //-----------------------------------------------------------------------------
5833 // Copyright (c) <copydate> by <company> This model is the confidential and
5834 // proprietary property of <company> and the possession or use of this
5835 // file requires a written license from <company>.
5836 //------------------------------------------------------------------------------
5837 // Modification history :
5839 //-----------------------------------------------------------------------------
5843 (search-forward "<filename>")
5844 (replace-match (buffer-name) t t)
5845 (search-forward "<author>") (replace-match "" t t)
5846 (insert (user-full-name))
5847 (insert " <" (user-login-name) "@" (system-name) ">")
5848 (search-forward "<credate>") (replace-match "" t t)
5850 (search-forward "<moddate>") (replace-match "" t t)
5852 (search-forward "<copydate>") (replace-match "" t t)
5854 (search-forward "<modhist>") (replace-match "" t t)
5856 (insert " : created")
5859 (setq string (read-string "title: "))
5860 (search-forward "<title>")
5861 (replace-match string t t)
5862 (setq string (read-string "project: " verilog-project))
5863 (make-variable-buffer-local 'verilog-project)
5864 (setq verilog-project string)
5865 (search-forward "<project>")
5866 (replace-match string t t)
5867 (setq string (read-string "Company: " verilog-company))
5868 (make-variable-buffer-local 'verilog-company)
5869 (setq verilog-company string)
5870 (search-forward "<company>")
5871 (replace-match string t t)
5872 (search-forward "<company>")
5873 (replace-match string t t)
5874 (search-forward "<company>")
5875 (replace-match string t t)
5876 (search-backward "<description>")
5877 (replace-match "" t t)
5880 ;; verilog-header Uses the insert-date function
5882 (defun insert-date ()
5883 "Insert date from the system."
5886 (setq timpos (point))
5887 (if verilog-date-scientific-format
5888 (shell-command "date \"+@%Y/%m/%d\"" t)
5889 (shell-command "date \"+@%d.%m.%Y\"" t))
5890 (search-forward "@")
5891 (delete-region timpos (point))
5895 (defun insert-year ()
5896 "Insert year from the system."
5899 (setq timpos (point))
5900 (shell-command "date \"+@%Y\"" t)
5901 (search-forward "@")
5902 (delete-region timpos (point))
5908 ;; Signal list parsing
5911 ;; Elements of a signal list
5912 (defsubst verilog-sig-name (sig)
5914 (defsubst verilog-sig-bits (sig)
5916 (defsubst verilog-sig-comment (sig)
5918 (defsubst verilog-sig-memory (sig)
5920 (defsubst verilog-sig-enum (sig)
5922 (defsubst verilog-sig-signed (sig)
5924 (defsubst verilog-sig-type (sig)
5926 (defsubst verilog-sig-multidim (sig)
5928 (defsubst verilog-sig-multidim-string (sig)
5929 (if (verilog-sig-multidim sig)
5930 (let ((str "") (args (verilog-sig-multidim sig)))
5932 (setq str (concat str (car args)))
5933 (setq args (cdr args)))
5935 (defsubst verilog-sig-width (sig)
5936 (verilog-make-width-expression (verilog-sig-bits sig)))
5938 (defsubst verilog-alw-get-inputs (sigs)
5940 (defsubst verilog-alw-get-outputs (sigs)
5942 (defsubst verilog-alw-get-uses-delayed (sigs)
5945 (defun verilog-signals-not-in (in-list not-list)
5946 "Return list of signals in IN-LIST that aren't also in NOT-LIST,
5947 and also remove any duplicates in IN-LIST.
5948 Signals must be in standard (base vector) form."
5951 (if (not (or (assoc (car (car in-list)) not-list)
5952 (assoc (car (car in-list)) out-list)))
5953 (setq out-list (cons (car in-list) out-list)))
5954 (setq in-list (cdr in-list)))
5955 (nreverse out-list)))
5956 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5958 (defun verilog-signals-in (in-list other-list)
5959 "Return list of signals in IN-LIST that are also in OTHER-LIST.
5960 Signals must be in standard (base vector) form."
5963 (if (assoc (car (car in-list)) other-list)
5964 (setq out-list (cons (car in-list) out-list)))
5965 (setq in-list (cdr in-list)))
5966 (nreverse out-list)))
5967 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5969 (defun verilog-signals-memory (in-list)
5970 "Return list of signals in IN-LIST that are memoried (multidimensional)."
5973 (if (nth 3 (car in-list))
5974 (setq out-list (cons (car in-list) out-list)))
5975 (setq in-list (cdr in-list)))
5977 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
5979 (defun verilog-signals-sort-compare (a b)
5980 "Compare signal A and B for sorting."
5981 (string< (car a) (car b)))
5983 (defun verilog-signals-not-params (in-list)
5984 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
5987 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
5988 (setq out-list (cons (car in-list) out-list)))
5989 (setq in-list (cdr in-list)))
5990 (nreverse out-list)))
5992 (defun verilog-signals-combine-bus (in-list)
5993 "Return a list of signals in IN-LIST, with busses combined.
5994 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
5997 sig highbit lowbit ; Temp information about current signal
5998 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
5999 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
6001 ;; Shove signals so duplicated signals will be adjacent
6002 (setq in-list (sort in-list `verilog-signals-sort-compare))
6004 (setq sig (car in-list))
6005 ;; No current signal; form from existing details
6007 (setq sv-name (verilog-sig-name sig)
6010 sv-comment (verilog-sig-comment sig)
6011 sv-memory (verilog-sig-memory sig)
6012 sv-enum (verilog-sig-enum sig)
6013 sv-signed (verilog-sig-signed sig)
6014 sv-type (verilog-sig-type sig)
6015 sv-multidim (verilog-sig-multidim sig)
6019 ;; Extract bus details
6020 (setq bus (verilog-sig-bits sig))
6022 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
6023 (setq highbit (string-to-int (match-string 1 bus))
6024 lowbit (string-to-int (match-string 2 bus))))
6025 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
6026 (setq highbit (string-to-int (match-string 1 bus))
6028 ;; Combine bits in bus
6030 (setq sv-highbit (max highbit sv-highbit)
6031 sv-lowbit (min lowbit sv-lowbit))
6032 (setq sv-highbit highbit
6035 ;; String, probably something like `preproc:0
6036 (setq sv-busstring bus)))
6037 ;; Peek ahead to next signal
6038 (setq in-list (cdr in-list))
6039 (setq sig (car in-list))
6040 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
6041 ;; Combine with this signal
6042 (when (and sv-busstring (not (equal sv-busstring (verilog-sig-bits sig))))
6043 (when nil ;; Debugging
6044 (message (concat "Warning, can't merge into single bus "
6046 ", the AUTOs may be wrong")))
6047 (setq buswarn ", Couldn't Merge"))
6048 (if (verilog-sig-comment sig) (setq combo ", ..."))
6049 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
6050 sv-enum (or sv-enum (verilog-sig-enum sig))
6051 sv-signed (or sv-signed (verilog-sig-signed sig))
6052 sv-type (or sv-type (verilog-sig-type sig))
6053 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
6054 ;; Doesn't match next signal, add to queue, zero in prep for next
6055 ;; Note sig may also be nil for the last signal in the list
6061 (concat "[" (int-to-string sv-highbit) ":" (int-to-string sv-lowbit) "]")))
6062 (concat sv-comment combo buswarn)
6063 sv-memory sv-enum sv-signed sv-type sv-multidim)
6070 (defun verilog-sig-tieoff (sig &optional no-width)
6071 "Return tieoff expression for given SIGNAL, with appropriate width.
6072 Ignore width if optional NO-WIDTH is set."
6073 (let* ((width (if no-width nil (verilog-sig-width sig))))
6075 (if (and verilog-active-low-regexp
6076 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
6080 ((string-match "^[0-9]+$" width)
6081 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
6083 (concat "{" width "{1'b0}}"))))))
6086 ;; Port/Wire/Etc Reading
6089 (defun verilog-read-inst-backward-name ()
6090 "Internal. Move point back to beginning of inst-name."
6091 (verilog-backward-open-paren)
6094 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
6095 (cond ((looking-at ")")
6096 (verilog-backward-open-paren))
6097 (t (setq done t)))))
6098 (while (looking-at "\\]")
6099 (verilog-backward-open-bracket)
6100 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
6101 (skip-chars-backward "a-zA-Z0-9`_$"))
6103 (defun verilog-read-inst-module ()
6104 "Return module_name when point is inside instantiation."
6106 (verilog-read-inst-backward-name)
6107 ;; Skip over instantiation name
6108 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6109 ;; Check for parameterized instantiations
6110 (when (looking-at ")")
6111 (verilog-backward-open-paren)
6112 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
6113 (skip-chars-backward "a-zA-Z0-9'_$")
6114 (looking-at "[a-zA-Z0-9`_\$]+")
6115 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6116 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6118 (defun verilog-read-inst-name ()
6119 "Return instance_name when point is inside instantiation."
6121 (verilog-read-inst-backward-name)
6122 (looking-at "[a-zA-Z0-9`_\$]+")
6123 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6124 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6126 (defun verilog-read-module-name ()
6127 "Return module name when after its ( or ;."
6129 (re-search-backward "[(;]")
6130 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
6131 (skip-chars-backward "a-zA-Z0-9`_$")
6132 (looking-at "[a-zA-Z0-9`_\$]+")
6133 ;; Important: don't use match string, this must work with emacs 19 font-lock on
6134 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6136 (defun verilog-read-auto-params (num-param &optional max-param)
6137 "Return parameter list inside auto.
6138 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
6141 ;; /*AUTOPUNT("parameter", "parameter")*/
6142 (search-backward "(")
6143 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
6144 (setq olist (cons (match-string 1) olist))
6145 (goto-char (match-end 0))))
6146 (or (eq nil num-param)
6147 (<= num-param (length olist))
6148 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
6149 (if (eq max-param nil) (setq max-param num-param))
6150 (or (eq nil max-param)
6151 (>= max-param (length olist))
6152 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
6155 (defun verilog-read-decls ()
6156 "Compute signal declaration information for the current module at point.
6157 Return a array of [outputs inouts inputs wire reg assign const]."
6158 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
6159 (functask 0) (paren 0) (sig-paren 0)
6160 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
6161 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
6163 (verilog-beg-of-defun)
6164 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
6165 (while (< (point) end-mod-point)
6166 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
6169 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6170 (setq enum (match-string 1)))
6171 (search-forward "\n"))
6172 ((looking-at "/\\*")
6174 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6175 (setq enum (match-string 1)))
6176 (or (search-forward "*/")
6177 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6178 ((looking-at "(\\*")
6180 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
6181 (search-forward "*)")
6182 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6183 ((eq ?\" (following-char))
6184 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
6185 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6186 ((eq ?\; (following-char))
6187 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
6189 ((eq ?= (following-char))
6190 (setq rvalue t newsig nil)
6192 ((and (or rvalue sig-paren)
6193 (cond ((and (eq ?, (following-char))
6194 (eq paren sig-paren))
6198 ;; ,'s can occur inside {} & funcs
6199 ((looking-at "[{(]")
6200 (setq paren (1+ paren))
6203 ((looking-at "[})]")
6204 (setq paren (1- paren))
6206 (when (< paren sig-paren)
6207 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
6210 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
6211 (goto-char (match-end 0))
6212 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
6213 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
6214 (vec ;; Multidimensional
6215 (setq multidim (cons vec multidim))
6216 (setq vec (verilog-string-replace-matches
6217 "\\s-+" "" nil nil (match-string 1))))
6219 (setq vec (verilog-string-replace-matches
6220 "\\s-+" "" nil nil (match-string 1))))))
6221 ;; Normal or escaped identifier -- note we remember the \ if escaped
6222 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
6223 (goto-char (match-end 0))
6224 (setq keywd (match-string 1))
6225 (when (string-match "^\\\\" keywd)
6226 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
6227 (cond ((equal keywd "input")
6228 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6229 expect-signal 'sigs-in io t))
6230 ((equal keywd "output")
6231 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6232 expect-signal 'sigs-out io t))
6233 ((equal keywd "inout")
6234 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6235 expect-signal 'sigs-inout io t))
6236 ((or (equal keywd "wire")
6238 (equal keywd "tri0")
6239 (equal keywd "tri1"))
6240 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6241 expect-signal 'sigs-wire)))
6242 ((or (equal keywd "reg")
6243 (equal keywd "trireg"))
6244 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6245 expect-signal 'sigs-reg)))
6246 ((equal keywd "assign")
6247 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6248 expect-signal 'sigs-assign))
6249 ((or (equal keywd "supply0")
6250 (equal keywd "supply1")
6251 (equal keywd "supply")
6252 (equal keywd "localparam"))
6253 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6254 expect-signal 'sigs-const)))
6255 ((or (equal keywd "parameter"))
6256 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6257 expect-signal 'sigs-gparam)))
6258 ((equal keywd "signed")
6259 (setq signed "signed"))
6260 ((or (equal keywd "function")
6261 (equal keywd "task"))
6262 (setq functask (1+ functask)))
6263 ((or (equal keywd "endfunction")
6264 (equal keywd "endtask"))
6265 (setq functask (1- functask)))
6266 ((or (equal keywd "`ifdef")
6267 (equal keywd "`ifndef"))
6269 ((verilog-typedef-name-p keywd)
6270 (setq typedefed keywd))
6274 (eq paren sig-paren)
6275 (not (member keywd verilog-keywords)))
6276 ;; Add new signal to expect-signal's variable
6277 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
6278 (set expect-signal (cons newsig
6279 (symbol-value expect-signal))))))
6282 (skip-syntax-forward " "))
6284 (vector (nreverse sigs-out)
6285 (nreverse sigs-inout)
6287 (nreverse sigs-wire)
6289 (nreverse sigs-assign)
6290 (nreverse sigs-const)
6291 (nreverse sigs-gparam)
6294 (defvar sigs-in nil) ; Prevent compile warning
6295 (defvar sigs-inout nil) ; Prevent compile warning
6296 (defvar sigs-out nil) ; Prevent compile warning
6298 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
6299 "For verilog-read-sub-decls-line, add a signal."
6302 (setq port (verilog-symbol-detick-denumber port))
6303 (setq sig (verilog-symbol-detick-denumber sig))
6304 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
6305 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
6306 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
6307 (unless (or (not sig)
6308 (equal sig "")) ;; Ignore .foo(1'b1) assignments
6309 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
6310 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
6311 (verilog-sig-signed portdata)
6312 (verilog-sig-type portdata)
6315 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
6316 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
6317 (verilog-sig-signed portdata)
6318 (verilog-sig-type portdata)
6321 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
6322 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
6323 (verilog-sig-signed portdata)
6324 (verilog-sig-type portdata)
6327 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
6330 (defun verilog-read-sub-decls-line (submodi comment)
6331 "For read-sub-decls, read lines of port defs until none match anymore.
6332 Return the list of signals found, using submodi to look up each port."
6333 (let (done port sig vec multidim)
6338 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
6339 (setq port (match-string 1))
6340 (goto-char (match-end 0)))
6341 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
6342 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
6343 (goto-char (match-end 0)))
6344 ((looking-at "\\s-*\\.[^(]*(")
6345 (setq port nil) ;; skip this line
6346 (goto-char (match-end 0)))
6348 (setq port nil done t))) ;; Unknown, ignore rest of line
6352 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
6353 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
6355 ; We intentionally ignore (non-escaped) signals with .s in them
6356 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
6357 ((looking-at "\\([^[({).]*\\)\\s-*)")
6358 (setq sig (verilog-string-remove-spaces (match-string 1))
6360 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
6361 (setq sig (verilog-string-remove-spaces (match-string 1))
6362 vec (match-string 2)))
6363 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
6364 (setq sig (verilog-string-remove-spaces (match-string 1))
6366 (let ((parse (match-string 2)))
6367 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
6368 (when vec (setq multidim (cons vec multidim)))
6369 (setq vec (match-string 1 parse))
6370 (setq parse (match-string 2 parse)))))
6371 ((looking-at "{\\(.*\\)}.*\\s-*)")
6372 (let ((mlst (split-string (match-string 1) ","))
6374 (while (setq mstr (pop mlst))
6375 ;;(unless noninteractive (message "sig: %s " mstr))
6377 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
6378 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6380 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
6382 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
6383 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6384 vec (match-string 2 mstr))
6385 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
6390 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
6394 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
6396 (forward-line 1)))))
6398 (defun verilog-read-sub-decls ()
6399 "Internally parse signals going to modules under this module.
6400 Return a array of [ outputs inouts inputs ] signals for modules that are
6401 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
6402 is a output, then SIG will be included in the list.
6404 This only works on instantiations created with /*AUTOINST*/ converted by
6405 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
6406 component library to determine connectivity of the design.
6408 One work around for this problem is to manually create // Inputs and //
6409 Outputs comments above subcell signals, for example:
6411 module1 instance1x (
6417 (let ((end-mod-point (verilog-get-end-of-defun t))
6418 st-point end-inst-point
6419 ;; below 3 modified by verilog-read-sub-decls-line
6420 sigs-out sigs-inout sigs-in)
6421 (verilog-beg-of-defun)
6422 (while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
6424 (goto-char (match-beginning 0))
6425 (unless (verilog-inside-comment-p)
6426 ;; Attempt to snarf a comment
6427 (let* ((submod (verilog-read-inst-module))
6428 (inst (verilog-read-inst-name))
6429 (comment (concat inst " of " submod ".v")) submodi)
6430 (when (setq submodi (verilog-modi-lookup submod t))
6431 ;; This could have used a list created by verilog-auto-inst
6432 ;; However I want it to be runnable even on user's manually added signals
6433 (verilog-backward-open-paren)
6434 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
6436 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
6437 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
6438 (goto-char st-point)
6439 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
6440 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
6441 (goto-char st-point)
6442 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
6443 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
6445 ;; Combine duplicate bits
6446 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
6447 (vector (verilog-signals-combine-bus (nreverse sigs-out))
6448 (verilog-signals-combine-bus (nreverse sigs-inout))
6449 (verilog-signals-combine-bus (nreverse sigs-in))))))
6451 (defun verilog-read-inst-pins ()
6452 "Return a array of [ pins ] for the current instantiation at point.
6453 For example if declare A A (.B(SIG)) then B will be included in the list."
6455 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
6457 (verilog-backward-open-paren)
6458 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
6459 (setq pin (match-string 1))
6460 (unless (verilog-inside-comment-p)
6461 (setq pins (cons (list pin) pins))
6462 (when (looking-at "(")
6466 (defun verilog-read-arg-pins ()
6467 "Return a array of [ pins ] for the current argument declaration at point."
6469 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
6471 (verilog-backward-open-paren)
6472 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
6473 (setq pin (match-string 1))
6474 (unless (verilog-inside-comment-p)
6475 (setq pins (cons (list pin) pins))))
6478 (defun verilog-read-auto-constants (beg end-mod-point)
6479 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
6482 (let (sig-list tpl-end-pt)
6484 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
6485 (if (not (looking-at "\\s *("))
6486 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
6487 (search-forward "(" end-mod-point)
6488 (setq tpl-end-pt (save-excursion
6490 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6493 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
6494 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
6497 (defun verilog-read-auto-lisp (start end)
6498 "Look for and evaluate a AUTO_LISP between START and END."
6501 (while (re-search-forward "\\<AUTO_LISP(" end t)
6503 (let* ((beg-pt (prog1 (point)
6504 (forward-sexp 1))) ;; Closing paren
6506 (eval-region beg-pt end-pt nil)))))
6509 ;; These are passed in a let, not global
6510 (if (not (boundp 'sigs-in))
6511 (defvar sigs-in nil) (defvar sigs-out nil)
6512 (defvar got-sig nil) (defvar got-rvalue nil) (defvar uses-delayed nil)))
6514 (defun verilog-read-always-signals-recurse
6515 (exit-keywd rvalue ignore-next)
6516 "Recursive routine for parentheses/bracket matching.
6517 EXIT-KEYWD is expression to stop at, nil if top level.
6518 RVALUE is true if at right hand side of equal.
6519 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
6520 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
6521 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
6522 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
6523 (while (not (or (eobp) gotend))
6526 (search-forward "\n"))
6527 ((looking-at "/\\*")
6528 (or (search-forward "*/")
6529 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6530 ((looking-at "(\\*")
6531 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6532 (search-forward "*)")
6533 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6534 (t (setq keywd (buffer-substring-no-properties
6536 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6539 sig-last-tolk sig-tolk
6541 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
6544 (or (re-search-forward "[^\\]\"" nil t)
6545 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6546 ;; else at top level loop, keep parsing
6547 ((and end-else-check (equal keywd "else"))
6548 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
6549 ;; no forward movement, want to see else in lower loop
6550 (setq end-else-check nil))
6551 ;; End at top level loop
6552 ((and end-else-check (looking-at "[^ \t\n\f]"))
6553 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
6556 ((and exit-keywd (equal keywd exit-keywd))
6558 (forward-char (length keywd)))
6559 ;; Standard tokens...
6561 (setq ignore-next nil rvalue semi-rvalue)
6562 ;; Final statement at top level loop?
6563 (when (not exit-keywd)
6564 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
6565 (setq end-else-check t))
6568 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
6569 (goto-char (match-end 0))
6571 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
6572 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
6573 (setq ignore-next nil rvalue nil))
6574 ((equal "?" exit-keywd) ;; x?y:z rvalue
6576 (got-sig ;; label: statement
6577 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
6578 ((not rvalue) ;; begin label
6579 (setq ignore-next t rvalue nil)))
6582 (if (eq (char-before) ?< )
6583 (setq uses-delayed 1))
6584 (setq ignore-next nil rvalue t)
6588 (verilog-read-always-signals-recurse ":" rvalue nil))
6591 (verilog-read-always-signals-recurse "]" t nil))
6594 (cond (sig-last-tolk ;; Function call; zap last signal
6595 (setq got-sig nil)))
6596 (cond ((equal last-keywd "for")
6597 (verilog-read-always-signals-recurse ";" nil nil)
6598 (verilog-read-always-signals-recurse ";" t nil)
6599 (verilog-read-always-signals-recurse ")" nil nil))
6600 (t (verilog-read-always-signals-recurse ")" t nil))))
6601 ((equal keywd "begin")
6602 (skip-syntax-forward "w_")
6603 (verilog-read-always-signals-recurse "end" nil nil)
6604 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
6605 (setq ignore-next nil rvalue semi-rvalue)
6606 (if (not exit-keywd) (setq end-else-check t)))
6607 ((or (equal keywd "case")
6608 (equal keywd "casex")
6609 (equal keywd "casez"))
6610 (skip-syntax-forward "w_")
6611 (verilog-read-always-signals-recurse "endcase" t nil)
6612 (setq ignore-next nil rvalue semi-rvalue)
6613 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
6614 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
6615 (cond ((or (equal keywd "`ifdef")
6616 (equal keywd "`ifndef"))
6617 (setq ignore-next t))
6619 (member keywd verilog-keywords)
6620 (string-match "^\\$" keywd)) ;; PLI task
6621 (setq ignore-next nil))
6623 (setq keywd (verilog-symbol-detick-denumber keywd))
6625 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6626 (setq sigs-out (cons got-sig sigs-out)))
6627 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6629 (setq got-rvalue rvalue
6630 got-sig (if (or (not keywd)
6631 (assoc keywd (if got-rvalue sigs-in sigs-out)))
6632 nil (list keywd nil nil))
6634 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6637 ;; End of non-comment token
6638 (setq last-keywd keywd)
6640 (skip-syntax-forward " "))
6641 ;; Append the final pending signal
6643 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6644 (setq sigs-out (cons got-sig sigs-out)))
6645 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6647 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
6650 (defun verilog-read-always-signals ()
6651 "Parse always block at point and return list of (outputs inout inputs)."
6656 uses-delayed) ;; Found signal/rvalue; push if not function
6657 (search-forward ")")
6658 (verilog-read-always-signals-recurse nil nil nil)
6659 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
6660 ;; Return what was found
6661 (list sigs-out nil sigs-in uses-delayed))))
6663 (defun verilog-read-instants ()
6664 "Parse module at point and return list of ( ( file instance ) ... )."
6665 (verilog-beg-of-defun)
6666 (let* ((end-mod-point (verilog-get-end-of-defun t))
6668 (instants-list nil))
6670 (while (< (point) end-mod-point)
6671 ;; Stay at level 0, no comments
6673 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
6674 (or (> (car state) 0) ; in parens
6675 (nth 5 state) ; comment
6679 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
6680 ;;(if (looking-at "^\\(.+\\)$")
6681 (let ((module (match-string 1))
6682 (instant (match-string 2)))
6683 (if (not (member module verilog-keywords))
6684 (setq instants-list (cons (list module instant) instants-list)))))
6690 (defun verilog-read-auto-template (module)
6691 "Look for a auto_template for the instantiation of the given MODULE.
6692 If found returns the signal name connections. Return REGEXP and
6693 list of ( (signal_name connection_name)... )"
6696 (let ((tpl-regexp "\\([0-9]+\\)")
6699 tpl-sig-list tpl-wild-list tpl-end-pt rep)
6701 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
6703 (goto-char (point-min))
6704 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
6705 (goto-char (match-end 0))
6707 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
6708 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
6709 (setq tpl-regexp (match-string 1))
6710 (goto-char (match-end 0)))
6711 (search-forward "(")
6712 ;; Parse lines in the template
6713 (when verilog-auto-inst-template-numbers
6715 (goto-char (point-min))
6716 (while (search-forward "AUTO_TEMPLATE" nil t)
6717 (setq templateno (1+ templateno)))))
6718 (setq tpl-end-pt (save-excursion
6720 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6724 (while (< (point) tpl-end-pt)
6725 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6726 (setq tpl-sig-list (cons (list
6727 (match-string-no-properties 1)
6728 (match-string-no-properties 2)
6731 (goto-char (match-end 0)))
6734 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last
6735 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6736 (setq rep (match-string-no-properties 3))
6737 (goto-char (match-end 0))
6741 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
6747 ((looking-at "[ \t\f]+")
6748 (goto-char (match-end 0)))
6750 (setq lineno (1+ lineno))
6751 (goto-char (match-end 0)))
6753 (search-forward "\n"))
6754 ((looking-at "/\\*")
6756 (or (search-forward "*/")
6757 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6759 (error "%s: AUTO_TEMPLATE parsing error: %s"
6760 (verilog-point-text)
6761 (progn (looking-at ".*$") (match-string 0))))
6765 (list tpl-sig-list tpl-wild-list)))
6766 ;; If no template found
6767 (t (vector tpl-regexp nil))))))
6768 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
6770 (defun verilog-set-define (defname defvalue &optional buffer enumname)
6771 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
6772 Optionally associate it with the specified enumeration ENUMNAME."
6774 (set-buffer (or buffer (current-buffer)))
6775 (let ((mac (intern (concat "vh-" defname))))
6776 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6777 ;; Need to define to a constant if no value given
6778 (set (make-variable-buffer-local mac)
6779 (if (equal defvalue "") "1" defvalue)))
6781 (let ((enumvar (intern (concat "venum-" enumname))))
6782 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6783 (make-variable-buffer-local enumvar)
6784 (add-to-list enumvar defname)))
6787 (defun verilog-read-defines (&optional filename recurse subcall)
6788 "Read `defines and parameters for the current file, or optional FILENAME.
6789 If the filename is provided, `verilog-library-flags' will be used to
6790 resolve it. If optional RECURSE is non-nil, recurse through `includes.
6792 Parameters must be simple assignments to constants, or have their own
6793 \"parameter\" label rather than a list of parameters. Thus:
6795 parameter X = 5, Y = 10; // Ok
6796 parameter X = {1'b1, 2'h2}; // Ok
6797 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
6799 Defines must be simple text substitutions, one on a line, starting
6800 at the beginning of the line. Any ifdefs or multiline comments around the
6803 Defines are stored inside Emacs variables using the name vh-{definename}.
6805 This function is useful for setting vh-* variables. The file variables
6806 feature can be used to set defines that `verilog-mode' can see; put at the
6807 *END* of your file something like:
6810 // vh-macro:\"macro_definition\"
6813 If macros are defined earlier in the same file and you want their values,
6814 you can read them automatically (provided `enable-local-eval' is on):
6817 // eval:(verilog-read-defines)
6818 // eval:(verilog-read-defines \"group_standard_includes.v\")
6821 Note these are only read when the file is first visited, you must use
6822 \\[find-alternate-file] RET to have these take effect after editing them!
6824 If you want to disable the \"Process `eval' or hook local variables\"
6825 warning message, you need to add to your .emacs file:
6827 (setq enable-local-eval t)"
6828 (let ((origbuf (current-buffer)))
6830 (unless subcall (verilog-getopt-flags))
6832 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
6834 (set-buffer (find-file-noselect (car fns)))
6835 (error (concat (verilog-point-text)
6836 ": Can't find verilog-read-defines file: " filename)))))
6838 (goto-char (point-min))
6839 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6840 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
6841 (unless (verilog-inside-comment-p)
6842 (verilog-read-defines inc recurse t)))))
6844 ;; note we don't use verilog-re... it's faster this way, and that
6845 ;; function has problems when comments are at the end of the define
6846 (goto-char (point-min))
6847 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
6848 (let ((defname (match-string-no-properties 1))
6849 (defvalue (match-string-no-properties 2)))
6850 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
6851 (verilog-set-define defname defvalue origbuf)))
6852 ;; Hack: Read parameters
6853 (goto-char (point-min))
6854 (while (re-search-forward
6855 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
6856 (let ((var (match-string-no-properties 4))
6857 (val (match-string-no-properties 5))
6859 ;; The primary way of getting defines is verilog-read-decls
6860 ;; However, that isn't called yet for included files, so we'll add another scheme
6861 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6862 (setq enumname (match-string-no-properties 1)))
6864 (verilog-set-define var val origbuf enumname))
6865 (forward-comment 999)
6866 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
6867 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
6868 (goto-char (match-end 0))
6869 (forward-comment 999))))
6872 (defun verilog-read-includes ()
6873 "Read `includes for the current file.
6874 This will find all of the `includes which are at the beginning of lines,
6875 ignoring any ifdefs or multiline comments around them.
6876 `verilog-read-defines' is then performed on the current and each included
6879 It is often useful put at the *END* of your file something like:
6882 // eval:(verilog-read-defines)
6883 // eval:(verilog-read-includes)
6886 Note includes are only read when the file is first visited, you must use
6887 \\[find-alternate-file] RET to have these take effect after editing them!
6889 It is good to get in the habit of including all needed files in each .v
6890 file that needs it, rather than waiting for compile time. This will aid
6891 this process, Verilint, and readability. To prevent defining the same
6892 variable over and over when many modules are compiled together, put a test
6893 around the inside each include file:
6896 `ifdef _FOO_V // include if not already included
6899 ... contents of file
6901 ;;slow: (verilog-read-defines nil t))
6903 (verilog-getopt-flags)
6904 (goto-char (point-min))
6905 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6906 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
6907 (verilog-read-defines inc nil t)))))
6909 (defun verilog-read-signals (&optional start end)
6910 "Return a simple list of all possible signals in the file.
6911 Bounded by optional region from START to END. Overly aggressive but fast.
6912 Some macros and such are also found and included. For dinotrace.el"
6913 (let (sigs-all keywd)
6914 (progn;save-excursion
6915 (goto-char (or start (point-min)))
6916 (setq end (or end (point-max)))
6917 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
6921 (search-forward "\n"))
6922 ((looking-at "/\\*")
6923 (search-forward "*/"))
6924 ((looking-at "(\\*")
6925 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6926 (search-forward "*)")))
6927 ((eq ?\" (following-char))
6928 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
6929 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
6930 (goto-char (match-end 0))
6931 (setq keywd (match-string-no-properties 1))
6932 (or (member keywd verilog-keywords)
6933 (member keywd sigs-all)
6934 (setq sigs-all (cons keywd sigs-all))))
6935 (t (forward-char 1)))
6941 ;; Argument file parsing
6944 (defun verilog-getopt (arglist)
6945 "Parse -f, -v etc arguments in ARGLIST list or string."
6946 (unless (listp arglist) (setq arglist (list arglist)))
6947 (let ((space-args '())
6949 ;; Split on spaces, so users can pass whole command lines
6951 (setq arg (car arglist)
6952 arglist (cdr arglist))
6953 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
6954 (setq space-args (append space-args
6955 (list (match-string-no-properties 1 arg))))
6956 (setq arg (match-string 2 arg))))
6959 (setq arg (car space-args)
6960 space-args (cdr space-args))
6964 (setq next-param arg))
6966 (setq next-param arg))
6968 (setq next-param arg))
6969 ;; +libext+(ext1)+(ext2)...
6970 ((string-match "^\\+libext\\+\\(.*\\)" arg)
6971 (setq arg (match-string 1 arg))
6972 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
6973 (verilog-add-list-unique `verilog-library-extensions
6974 (match-string 1 arg))
6975 (setq arg (match-string 2 arg))))
6977 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
6978 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
6979 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
6980 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
6981 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
6983 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
6984 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
6985 (verilog-add-list-unique `verilog-library-directories
6986 (match-string 1 arg)))
6988 ((equal "+librescan" arg))
6989 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
6990 ;; Second parameters
6991 ((equal next-param "-f")
6992 (setq next-param nil)
6993 (verilog-getopt-file arg))
6994 ((equal next-param "-v")
6995 (setq next-param nil)
6996 (verilog-add-list-unique `verilog-library-files arg))
6997 ((equal next-param "-y")
6998 (setq next-param nil)
6999 (verilog-add-list-unique `verilog-library-directories arg))
7001 ((string-match "^[^-+]" arg)
7002 (verilog-add-list-unique `verilog-library-files arg))
7003 ;; Default - ignore; no warning
7008 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
7010 (defun verilog-getopt-file (filename)
7011 "Read verilog options from the specified FILENAME."
7013 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
7014 (orig-buffer (current-buffer))
7017 (set-buffer (find-file-noselect (car fns)))
7018 (error (concat (verilog-point-text)
7019 "Can't find verilog-getopt-file -f file: " filename)))
7020 (goto-char (point-min))
7022 (setq line (buffer-substring (point)
7023 (save-excursion (end-of-line) (point))))
7025 (when (string-match "//" line)
7026 (setq line (substring line 0 (match-beginning 0))))
7028 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
7029 (verilog-getopt line))))))
7031 (defun verilog-getopt-flags ()
7032 "Convert `verilog-library-flags' into standard library variables."
7033 ;; If the flags are local, then all the outputs should be local also
7034 (when (local-variable-p `verilog-library-flags (current-buffer))
7035 (make-variable-buffer-local 'verilog-library-extensions)
7036 (make-variable-buffer-local 'verilog-library-directories)
7037 (make-variable-buffer-local 'verilog-library-files)
7038 (make-variable-buffer-local 'verilog-library-flags))
7039 ;; Allow user to customize
7040 (run-hooks 'verilog-before-getopt-flags-hook)
7041 ;; Process arguments
7042 (verilog-getopt verilog-library-flags)
7043 ;; Allow user to customize
7044 (run-hooks 'verilog-getopt-flags-hook))
7046 (defun verilog-add-list-unique (varref object)
7047 "Append to VARREF list the given OBJECT,
7048 unless it is already a member of the variable's list"
7049 (unless (member object (symbol-value varref))
7050 (set varref (append (symbol-value varref) (list object))))
7052 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
7056 ;; Module name lookup
7059 (defun verilog-module-inside-filename-p (module filename)
7060 "Return point if MODULE is specified inside FILENAME, else nil.
7061 Allows version control to check out the file if need be."
7062 (and (or (file-exists-p filename)
7065 (fboundp 'vc-backend)
7067 (vc-backend filename)))
7070 (set-buffer (find-file-noselect filename))
7071 (goto-char (point-min))
7073 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
7074 (verilog-re-search-forward-quick "\\<module\\>" nil t)
7075 (verilog-re-search-forward-quick "[(;]" nil t))
7076 (if (equal module (verilog-read-module-name))
7080 (defun verilog-is-number (symbol)
7081 "Return true if SYMBOL is number-like."
7082 (or (string-match "^[0-9 \t:]+$" symbol)
7083 (string-match "^[---]*[0-9]+$" symbol)
7084 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)
7087 (defun verilog-symbol-detick (symbol wing-it)
7088 "Return a expanded SYMBOL name without any defines.
7089 If the variable vh-{symbol} is defined, return that value.
7090 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
7091 (while (and symbol (string-match "^`" symbol))
7092 (setq symbol (substring symbol 1))
7094 (if (boundp (intern (concat "vh-" symbol)))
7095 ;; Emacs has a bug where boundp on a buffer-local
7096 ;; variable in only one buffer returns t in another.
7097 ;; This can confuse, so check for nil.
7098 (let ((val (eval (intern (concat "vh-" symbol)))))
7100 (if wing-it symbol nil)
7102 (if wing-it symbol nil))))
7104 ;;(verilog-symbol-detick "`mod" nil)
7106 (defun verilog-symbol-detick-denumber (symbol)
7107 "Return SYMBOL with defines converted and any numbers dropped to nil."
7108 (when (string-match "^`" symbol)
7109 ;; This only will work if the define is a simple signal, not
7110 ;; something like a[b]. Sorry, it should be substituted into the parser
7112 (verilog-string-replace-matches
7113 "\[[^0-9: \t]+\]" "" nil nil
7114 (or (verilog-symbol-detick symbol nil)
7115 (if verilog-auto-sense-defines-constant
7118 (if (verilog-is-number symbol)
7122 (defun verilog-symbol-detick-text (text)
7123 "Return TEXT with any without any known defines.
7124 If the variable vh-{symbol} is defined, substitute that value."
7125 (let ((ok t) symbol val)
7126 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
7127 (setq symbol (match-string 1 text))
7130 (boundp (intern (concat "vh-" symbol)))
7131 ;; Emacs has a bug where boundp on a buffer-local
7132 ;; variable in only one buffer returns t in another.
7133 ;; This can confuse, so check for nil.
7134 (setq val (eval (intern (concat "vh-" symbol)))))
7135 (setq text (replace-match val nil nil text)))
7136 (t (setq ok nil)))))
7138 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
7140 (defun verilog-expand-dirnames (&optional dirnames)
7141 "Return a list of existing directories given a list of wildcarded DIRNAMES.
7142 Or, just the existing dirnames themselves if there are no wildcards."
7144 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
7145 (setq dirnames (reverse dirnames)) ; not nreverse
7147 pattern dirfile dirfiles dirname root filename rest)
7149 (setq dirname (substitute-in-file-name (car dirnames))
7150 dirnames (cdr dirnames))
7151 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
7152 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
7155 (setq root (match-string 1 dirname)
7156 filename (match-string 2 dirname)
7157 rest (match-string 3 dirname)
7159 ;; now replace those * and ? with .+ and .
7160 ;; use ^ and /> to get only whole file names
7161 ;;verilog-string-replace-matches
7162 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
7163 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
7165 ;; Unfortunately allows abc/*/rtl to match abc/rtl
7166 ;; because abc/.. shows up in dirfiles. Solutions welcome.
7167 dirfiles (if (file-directory-p root) ; Ignore version control external
7168 (directory-files root t pattern nil)))
7170 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
7171 dirfiles (cdr dirfiles))
7172 (if (file-directory-p dirfile)
7173 (setq dirlist (cons dirfile dirlist))))
7177 (if (file-directory-p dirname)
7178 (setq dirlist (cons dirname dirlist))))
7181 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
7183 (defun verilog-library-filenames (filename current &optional check-ext)
7184 "Return a search path to find the given FILENAME name.
7185 Uses the CURRENT filename, `verilog-library-directories' and
7186 `verilog-library-extensions' variables to build the path.
7187 With optional CHECK-EXT also check `verilog-library-extensions'."
7188 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
7191 (let ((ckext (if check-ext verilog-library-extensions `(""))))
7193 (setq fn (expand-file-name
7194 (concat filename (car ckext))
7195 (expand-file-name (car ckdir) (file-name-directory current))))
7196 (if (file-exists-p fn)
7197 (setq outlist (cons fn outlist)))
7198 (setq ckext (cdr ckext))))
7199 (setq ckdir (cdr ckdir)))
7200 (nreverse outlist)))
7202 (defun verilog-module-filenames (module current)
7203 "Return a search path to find the given MODULE name.
7204 Uses the CURRENT filename, `verilog-library-extensions',
7205 `verilog-library-directories' and `verilog-library-files'
7206 variables to build the path."
7207 ;; Return search locations for it
7208 (append (list current) ; first, current buffer
7209 (verilog-library-filenames module current t)
7210 verilog-library-files)) ; finally, any libraries
7213 ;; Module Information
7215 ;; Many of these functions work on "modi" a module information structure
7216 ;; A modi is: [module-name-string file-name begin-point]
7218 (defvar verilog-cache-enabled t
7219 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
7221 (defvar verilog-modi-cache-list nil
7222 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
7223 For speeding up verilog-modi-get-* commands.
7226 (defvar verilog-modi-cache-preserve-tick nil
7227 "Modification tick after which the cache is still considered valid.
7228 Use verilog-preserve-cache's to set")
7229 (defvar verilog-modi-cache-preserve-buffer nil
7230 "Modification tick after which the cache is still considered valid.
7231 Use verilog-preserve-cache's to set")
7233 (defun verilog-modi-current ()
7234 "Return the modi structure for the module currently at point."
7236 ;; read current module's name
7238 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7239 (verilog-re-search-forward-quick "(" nil nil)
7240 (setq name (verilog-read-module-name))
7243 (vector name (or (buffer-file-name) (current-buffer)) pt)))
7245 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
7246 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
7247 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
7248 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
7250 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
7251 "Find the file and point at which MODULE is defined.
7252 If ALLOW-CACHE is set, check and remember cache of previous lookups.
7253 Return modi if successful, else print message unless IGNORE-ERROR is true."
7254 (let* ((current (or (buffer-file-name) (current-buffer))))
7255 (cond ((and verilog-modi-lookup-last-modi
7256 verilog-cache-enabled
7258 (equal verilog-modi-lookup-last-mod module)
7259 (equal verilog-modi-lookup-last-current current)
7260 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
7263 (t (let* ((realmod (verilog-symbol-detick module t))
7264 (orig-filenames (verilog-module-filenames realmod current))
7265 (filenames orig-filenames)
7267 (while (and filenames (not pt))
7268 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
7269 (setq filenames (cdr filenames))))
7270 (cond (pt (setq verilog-modi-lookup-last-modi
7271 (vector realmod (car filenames) pt)))
7272 (t (setq verilog-modi-lookup-last-modi nil)
7274 (error (concat (verilog-point-text)
7275 ": Can't locate " module " module definition"
7276 (if (not (equal module realmod))
7277 (concat " (Expanded macro to " realmod ")")
7279 "\n Check the verilog-library-directories variable."
7280 "\n I looked in (if not listed, doesn't exist):\n\t"
7281 (mapconcat 'concat orig-filenames "\n\t")))))
7283 (setq verilog-modi-lookup-last-mod module
7284 verilog-modi-lookup-last-current current
7285 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
7286 verilog-modi-lookup-last-modi
7289 (defsubst verilog-modi-name (modi)
7291 (defsubst verilog-modi-file-or-buffer (modi)
7293 (defsubst verilog-modi-point (modi)
7296 (defun verilog-modi-filename (modi)
7297 "Filename of MODI, or name of buffer if its never been saved."
7298 (if (bufferp (verilog-modi-file-or-buffer modi))
7299 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
7300 (buffer-name (verilog-modi-file-or-buffer modi)))
7301 (verilog-modi-file-or-buffer modi)))
7303 (defun verilog-modi-goto (modi)
7304 "Move point/buffer to specified MODI."
7305 (or modi (error "Passed unfound modi to goto, check earlier"))
7306 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
7307 (verilog-modi-file-or-buffer modi)
7308 (find-file-noselect (verilog-modi-file-or-buffer modi))))
7309 (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax
7311 (goto-char (verilog-modi-point modi)))
7313 (defun verilog-goto-defun-file (module)
7314 "Move point to the file at which a given MODULE is defined."
7315 (interactive "sGoto File for Module: ")
7316 (let* ((modi (verilog-modi-lookup module nil)))
7318 (verilog-modi-goto modi)
7319 (switch-to-buffer (current-buffer)))))
7321 (defun verilog-modi-cache-results (modi function)
7322 "Run on MODI the given FUNCTION. Locate the module in a file.
7323 Cache the output of function so next call may have faster access."
7324 (let (func-returns fass)
7326 (verilog-modi-goto modi)
7327 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
7328 verilog-modi-cache-list))
7329 ;; Destroy caching when incorrect; Modified or file changed
7330 (not (and verilog-cache-enabled
7331 (or (equal (buffer-modified-tick) (nth 1 fass))
7332 (and verilog-modi-cache-preserve-tick
7333 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
7334 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
7335 (equal (visited-file-modtime) (nth 2 fass)))))
7336 (setq verilog-modi-cache-list nil
7340 (setq func-returns (nth 3 fass)))
7343 ;; Clear then restore any hilighting to make emacs19 happy
7344 (let ((fontlocked (when (and (boundp 'font-lock-mode)
7346 (font-lock-mode nil)
7348 (setq func-returns (funcall function))
7349 (when fontlocked (font-lock-mode t)))
7350 ;; Cache for next time
7351 (make-variable-buffer-local 'verilog-modi-cache-list)
7352 (setq verilog-modi-cache-list
7353 (cons (list (list (verilog-modi-name modi) function)
7354 (buffer-modified-tick)
7355 (visited-file-modtime)
7357 verilog-modi-cache-list)))
7362 (defun verilog-modi-cache-add (modi function element sig-list)
7363 "Add function return results to the module cache.
7364 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
7365 function now contains the additional SIG-LIST parameters."
7368 (verilog-modi-goto modi)
7369 (if (setq fass (assoc (list (verilog-modi-name modi) function)
7370 verilog-modi-cache-list))
7371 (let ((func-returns (nth 3 fass)))
7372 (aset func-returns element
7373 (append sig-list (aref func-returns element))))))))
7375 (defmacro verilog-preserve-cache (&rest body)
7376 "Execute the BODY forms, allowing cache preservation within BODY.
7377 This means that changes to the buffer will not result in the cache being
7378 flushed. If the changes affect the modsig state, they must call the
7379 modsig-cache-add-* function, else the results of later calls may be
7380 incorrect. Without this, changes are assumed to be adding/removing signals
7381 and invalidating the cache."
7382 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
7383 (verilog-modi-cache-preserve-buffer (current-buffer)))
7386 (defsubst verilog-modi-get-decls (modi)
7387 (verilog-modi-cache-results modi 'verilog-read-decls))
7389 (defsubst verilog-modi-get-sub-decls (modi)
7390 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
7392 ;; Signal reading for given module
7393 ;; Note these all take modi's - as returned from the verilog-modi-current function
7394 (defsubst verilog-modi-get-outputs (modi)
7395 (aref (verilog-modi-get-decls modi) 0))
7396 (defsubst verilog-modi-get-inouts (modi)
7397 (aref (verilog-modi-get-decls modi) 1))
7398 (defsubst verilog-modi-get-inputs (modi)
7399 (aref (verilog-modi-get-decls modi) 2))
7400 (defsubst verilog-modi-get-wires (modi)
7401 (aref (verilog-modi-get-decls modi) 3))
7402 (defsubst verilog-modi-get-regs (modi)
7403 (aref (verilog-modi-get-decls modi) 4))
7404 (defsubst verilog-modi-get-assigns (modi)
7405 (aref (verilog-modi-get-decls modi) 5))
7406 (defsubst verilog-modi-get-consts (modi)
7407 (aref (verilog-modi-get-decls modi) 6))
7408 (defsubst verilog-modi-get-gparams (modi)
7409 (aref (verilog-modi-get-decls modi) 7))
7410 (defsubst verilog-modi-get-sub-outputs (modi)
7411 (aref (verilog-modi-get-sub-decls modi) 0))
7412 (defsubst verilog-modi-get-sub-inouts (modi)
7413 (aref (verilog-modi-get-sub-decls modi) 1))
7414 (defsubst verilog-modi-get-sub-inputs (modi)
7415 (aref (verilog-modi-get-sub-decls modi) 2))
7418 (defun verilog-signals-matching-enum (in-list enum)
7419 "Return all signals in IN-LIST matching the given ENUM."
7422 (if (equal (verilog-sig-enum (car in-list)) enum)
7423 (setq out-list (cons (car in-list) out-list)))
7424 (setq in-list (cdr in-list)))
7426 (let* ((enumvar (intern (concat "venum-" enum)))
7427 (enumlist (and (boundp enumvar) (eval enumvar))))
7429 (add-to-list 'out-list (list (car enumlist)))
7430 (setq enumlist (cdr enumlist))))
7431 (nreverse out-list)))
7433 (defun verilog-signals-not-matching-regexp (in-list regexp)
7434 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
7439 (if (not (string-match regexp (verilog-sig-name (car in-list))))
7440 (setq out-list (cons (car in-list) out-list)))
7441 (setq in-list (cdr in-list)))
7442 (nreverse out-list))))
7445 (defun verilog-modi-get-signals (modi)
7447 (verilog-modi-get-outputs modi)
7448 (verilog-modi-get-inouts modi)
7449 (verilog-modi-get-inputs modi)
7450 (verilog-modi-get-wires modi)
7451 (verilog-modi-get-regs modi)
7452 (verilog-modi-get-assigns modi)
7453 (verilog-modi-get-consts modi)
7454 (verilog-modi-get-gparams modi)))
7456 (defun verilog-modi-get-ports (modi)
7458 (verilog-modi-get-outputs modi)
7459 (verilog-modi-get-inouts modi)
7460 (verilog-modi-get-inputs modi)))
7462 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
7463 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
7464 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
7465 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
7466 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
7467 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
7468 (defsubst verilog-modi-cache-add-wires (modi sig-list)
7469 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
7470 (defsubst verilog-modi-cache-add-regs (modi sig-list)
7471 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
7473 (defun verilog-signals-from-signame (signame-list)
7474 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
7475 (mapcar (function (lambda (name) (list name nil nil)))
7479 ;; Auto creation utilities
7482 (defun verilog-auto-search-do (search-for func)
7483 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7484 (goto-char (point-min))
7485 (while (search-forward search-for nil t)
7486 (if (not (save-excursion
7487 (goto-char (match-beginning 0))
7488 (verilog-inside-comment-p)))
7491 (defun verilog-auto-re-search-do (search-for func)
7492 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7493 (goto-char (point-min))
7494 (while (re-search-forward search-for nil t)
7495 (if (not (save-excursion
7496 (goto-char (match-beginning 0))
7497 (verilog-inside-comment-p)))
7500 (defun verilog-insert-one-definition (sig type indent-pt)
7501 "Print out a definition for SIGNAL of the given TYPE,
7502 with appropriate INDENT-PT indentation."
7503 (indent-to indent-pt)
7505 (when (verilog-sig-signed sig)
7506 (insert " " (verilog-sig-signed sig)))
7507 (when (verilog-sig-multidim sig)
7508 (insert " " (verilog-sig-multidim-string sig)))
7509 (when (verilog-sig-bits sig)
7510 (insert " " (verilog-sig-bits sig)))
7511 (indent-to (max 24 (+ indent-pt 16)))
7512 (unless (= (char-syntax (preceding-char)) ?\ )
7513 (insert " ")) ; Need space between "]name" if indent-to did nothing
7514 (insert (verilog-sig-name sig)))
7516 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
7517 "Print out a definition for a list of SIGS of the given DIRECTION,
7518 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
7519 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
7521 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
7523 (let ((sig (car sigs)))
7524 (verilog-insert-one-definition
7526 ;; Want "type x" or "output type x", not "wire type x"
7527 (cond ((verilog-sig-type sig)
7529 (if (not (equal direction "wire"))
7530 (concat direction " "))
7531 (verilog-sig-type sig)))
7534 (insert (if v2k "," ";"))
7535 (if (or (not (verilog-sig-comment sig))
7536 (equal "" (verilog-sig-comment sig)))
7538 (indent-to (max 48 (+ indent-pt 40)))
7539 (insert (concat "// " (verilog-sig-comment sig) "\n")))
7540 (setq sigs (cdr sigs)))))
7543 (if (not (boundp 'indent-pt))
7544 (defvar indent-pt nil "Local used by insert-indent")))
7546 (defun verilog-insert-indent (&rest stuff)
7547 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
7548 Presumes that any newlines end a list element."
7549 (let ((need-indent t))
7551 (if need-indent (indent-to indent-pt))
7552 (setq need-indent nil)
7553 (insert (car stuff))
7554 (setq need-indent (string-match "\n$" (car stuff))
7555 stuff (cdr stuff)))))
7556 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
7558 (defun verilog-repair-open-comma ()
7559 "If backwards-from-point is other than a open parenthesis insert comma."
7561 (verilog-backward-syntactic-ws)
7562 (when (save-excursion
7564 (and (not (looking-at "[(,]"))
7566 (verilog-re-search-backward "[(`]" nil t)
7570 (defun verilog-repair-close-comma ()
7571 "If point is at a comma followed by a close parenthesis, fix it.
7572 This repairs those mis-inserted by a AUTOARG."
7573 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
7575 (verilog-forward-close-paren)
7577 (verilog-backward-syntactic-ws)
7579 (when (looking-at ",")
7582 (defun verilog-get-list (start end)
7583 "Return the elements of a comma separated list between START and END."
7585 (let ((my-list (list))
7588 (while (< (point) end)
7589 (when (re-search-forward "\\([^,{]+\\)" end t)
7590 (setq my-string (verilog-string-remove-spaces (match-string 1)))
7591 (setq my-list (nconc my-list (list my-string) ))
7592 (goto-char (match-end 0))))
7595 (defun verilog-make-width-expression (range-exp)
7596 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
7598 (cond ((not range-exp)
7601 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
7602 (setq range-exp (match-string 1 range-exp)))
7603 (cond ((not range-exp)
7605 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" range-exp)
7606 (int-to-string (1+ (abs (- (string-to-int (match-string 1 range-exp))
7607 (string-to-int (match-string 2 range-exp)))))))
7608 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
7609 (concat "(1+(" (match-string 1 range-exp)
7611 (if (equal "0" (match-string 2 range-exp)) ;; Don't bother with -(0)
7613 (concat "-(" (match-string 2 range-exp) ")"))
7616 ;;(verilog-make-width-expression "`A:`B")
7618 (defun verilog-typedef-name-p (variable-name)
7619 "Return true if the VARIABLE-NAME is a type definition."
7620 (when verilog-typedef-regexp
7621 (string-match verilog-typedef-regexp variable-name)))
7627 (defun verilog-delete-autos-lined ()
7628 "Delete autos that occupy multiple lines, between begin and end comments."
7632 (looking-at "\\s-*// Beginning")
7633 (search-forward "// End of automatic" nil t))
7636 (delete-region pt (point))
7640 (defun verilog-forward-close-paren ()
7641 "Find the close parenthesis that match the current point,
7642 ignore other close parenthesis with matching open parens"
7645 (unless (verilog-re-search-forward-quick "[()]" nil t)
7646 (error "%s: Mismatching ()" (verilog-point-text)))
7647 (cond ((= (preceding-char) ?\( )
7648 (setq parens (1+ parens)))
7649 ((= (preceding-char) ?\) )
7650 (setq parens (1- parens)))))))
7652 (defun verilog-backward-open-paren ()
7653 "Find the open parenthesis that match the current point,
7654 ignore other open parenthesis with matching close parens"
7657 (unless (verilog-re-search-backward-quick "[()]" nil t)
7658 (error "%s: Mismatching ()" (verilog-point-text)))
7659 (cond ((= (following-char) ?\) )
7660 (setq parens (1+ parens)))
7661 ((= (following-char) ?\( )
7662 (setq parens (1- parens)))))))
7664 (defun verilog-backward-open-bracket ()
7665 "Find the open bracket that match the current point,
7666 ignore other open bracket with matching close bracket"
7669 (unless (verilog-re-search-backward-quick "[][]" nil t)
7670 (error "%s: Mismatching []" (verilog-point-text)))
7671 (cond ((= (following-char) ?\] )
7672 (setq parens (1+ parens)))
7673 ((= (following-char) ?\[ )
7674 (setq parens (1- parens)))))))
7676 (defun verilog-delete-to-paren ()
7677 "Delete the automatic inst/sense/arg created by autos.
7678 Deletion stops at the matching end parenthesis."
7679 (delete-region (point)
7681 (verilog-backward-open-paren)
7682 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7686 (defun verilog-auto-star-safe ()
7687 "Return if a .* AUTOINST is safe to delete or expand.
7688 It was created by the AUTOS themselves, or by the user."
7689 (and verilog-auto-star-expand
7690 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
7692 (defun verilog-delete-auto-star-all ()
7693 "Delete a .* AUTOINST, if it is safe."
7694 (when (verilog-auto-star-safe)
7695 (verilog-delete-to-paren)))
7697 (defun verilog-delete-auto-star-implicit ()
7698 "Delete all .* implicit connections created by `verilog-auto-star'.
7699 This function will be called automatically at save unless
7700 `verilog-auto-star-save' is set, any non-templated expanded pins will be
7703 (let (paren-pt indent have-close-paren)
7705 (goto-char (point-min))
7706 ;; We need to match these even outside of comments.
7707 ;; For reasonable performance, we don't check if inside comments, sorry.
7708 (while (re-search-forward "// Implicit \\.\\*" nil t)
7709 (setq paren-pt (point))
7711 (setq have-close-paren
7713 (when (search-forward ");" paren-pt t)
7714 (setq indent (current-indentation))
7716 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
7717 (when have-close-paren
7718 ;; Delete extra commentary
7722 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
7723 (delete-region (match-beginning 0) (match-end 0))))
7724 ;; If it is simple, we can put the ); on the same line as the last text
7725 (let ((rtn-pt (point)))
7727 (while (progn (backward-char 1)
7728 (looking-at "[ \t\n\f]")))
7729 (when (looking-at ",")
7730 (delete-region (+ 1 (point)) rtn-pt))))
7734 ;; Still need to kill final comma - always is one as we put one after the .*
7735 (re-search-backward ",")
7736 (delete-char 1))))))
7738 (defun verilog-delete-auto ()
7739 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
7740 Use \\[verilog-auto] to re-insert the updated AUTOs.
7742 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
7743 called before and after this function, respectively."
7746 (if (buffer-file-name)
7747 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
7748 ;; Allow user to customize
7749 (run-hooks 'verilog-before-delete-auto-hook)
7751 ;; Remove those that have multi-line insertions
7752 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/"
7753 'verilog-delete-autos-lined)
7754 ;; Remove those that have multi-line insertions with parameters
7755 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/"
7756 'verilog-delete-autos-lined)
7757 ;; Remove those that are in parenthesis
7758 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/"
7759 'verilog-delete-to-paren)
7760 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
7761 (verilog-auto-re-search-do "\\.\\*"
7762 'verilog-delete-auto-star-all)
7763 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
7764 (goto-char (point-min))
7765 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
7769 (run-hooks 'verilog-delete-auto-hook)))
7775 (defun verilog-inject-auto ()
7776 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
7778 Any always @ blocks with sensitivity lists that match computed lists will
7779 be replaced with /*AS*/ comments.
7781 Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with
7782 have identical names will be deleted.
7784 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
7785 support adding new ports. You may wish to delete older ports yourself.
7789 module ex_inject (i, o);
7795 cell cell (.foobar(baz),
7799 Typing \\[verilog-inject-auto] will make this into:
7801 module ex_inject (i, o/*AUTOARG*/
7806 always @ (/*AS*/i or j)
7808 cell cell (.foobar(baz),
7816 (defun verilog-inject-arg ()
7817 "Inject AUTOARG into new code. See `verilog-inject-auto'."
7818 ;; Presume one module per file.
7820 (goto-char (point-min))
7821 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
7822 (let ((endmodp (save-excursion
7823 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
7825 ;; See if there's already a comment .. inside a comment so not verilog-re-search
7826 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
7827 (verilog-re-search-forward-quick ";" nil t)
7829 (verilog-backward-syntactic-ws)
7830 (backward-char 1) ; Moves to paren that closes argdecl's
7831 (when (looking-at ")")
7832 (insert "/*AUTOARG*/")))))))
7834 (defun verilog-inject-sense ()
7835 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
7837 (goto-char (point-min))
7838 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
7839 (let ((start-pt (point))
7840 (modi (verilog-modi-current))
7845 (backward-char 1) ;; End )
7846 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
7847 (setq pre-sigs (verilog-signals-from-signame
7848 (verilog-read-signals start-pt (point)))
7849 got-sigs (verilog-auto-sense-sigs modi nil))
7850 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
7851 (verilog-signals-not-in got-sigs pre-sigs)))
7852 (delete-region start-pt (point))
7853 (insert "/*AS*/")))))))
7855 (defun verilog-inject-inst ()
7856 "Inject AUTOINST into new code. See `verilog-inject-auto'."
7858 (goto-char (point-min))
7859 ;; It's hard to distinguish modules; we'll instead search for pins.
7860 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
7861 (verilog-backward-open-paren) ;; Inst start
7863 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
7865 (verilog-forward-close-paren)) ;; Parameters done
7868 (let ((indent-pt (+ (current-column)))
7869 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
7870 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
7871 (goto-char end-pt)) ;; Already there, continue search with next instance
7873 ;; Delete identical interconnect
7874 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
7875 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
7876 (delete-region (match-beginning 0) (match-end 0))
7877 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
7878 (while (or (looking-at "[ \t\n\f,]+")
7879 (looking-at "//[^\n]*"))
7880 (delete-region (match-beginning 0) (match-end 0))
7881 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
7882 (verilog-forward-close-paren)
7884 ;; Not verilog-re-search, as we don't want to strip comments
7885 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
7886 (delete-region (match-beginning 0) (match-end 0)))
7888 (indent-to indent-pt)
7889 (insert "/*AUTOINST*/")))))))))
7895 (defun verilog-auto-save-check ()
7896 "On saving see if we need auto update."
7897 (cond ((not verilog-auto-save-policy)) ; disabled
7898 ((not (save-excursion
7900 (let ((case-fold-search nil))
7901 (goto-char (point-min))
7902 (re-search-forward "AUTO" nil t))))))
7903 ((eq verilog-auto-save-policy 'force)
7905 ((not (buffer-modified-p)))
7906 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
7907 ((eq verilog-auto-save-policy 'detect)
7910 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
7912 ;; Don't ask again if didn't update
7913 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
7915 (when (not verilog-auto-star-save)
7916 (verilog-delete-auto-star-implicit))
7917 nil) ;; Always return nil -- we don't write the file ourselves
7919 (defun verilog-auto-read-locals ()
7920 "Return file local variable segment at bottom of file."
7922 (goto-char (point-max))
7923 (if (re-search-backward "Local Variables:" nil t)
7924 (buffer-substring-no-properties (point) (point-max))
7927 (defun verilog-auto-reeval-locals (&optional force)
7928 "Read file local variable segment at bottom of file if it has changed.
7929 If FORCE, always reread it."
7930 (make-variable-buffer-local 'verilog-auto-last-file-locals)
7931 (let ((curlocal (verilog-auto-read-locals)))
7932 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
7933 (setq verilog-auto-last-file-locals curlocal)
7934 ;; Note this may cause this function to be recursively invoked.
7935 ;; The above when statement will prevent it from recursing forever.
7936 (hack-local-variables)
7943 (defun verilog-auto-arg-ports (sigs message indent-pt)
7944 "Print a list of ports for a AUTOINST.
7945 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
7948 (indent-to indent-pt)
7952 (indent-to indent-pt)
7954 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
7956 (indent-to indent-pt))
7958 (insert (verilog-sig-name (car sigs)) ",")
7959 (setq sigs (cdr sigs)
7962 (defun verilog-auto-arg ()
7963 "Expand AUTOARG statements.
7964 Replace the argument declarations at the beginning of the
7965 module with ones automatically derived from input and output
7966 statements. This can be dangerous if the module is instantiated
7967 using position-based connections, so use only name-based when
7968 instantiating the resulting module. Long lines are split based
7969 on the `fill-column', see \\[set-fill-column].
7972 Concatenation and outputting partial busses is not supported.
7974 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
7978 module ex_arg (/*AUTOARG*/);
7983 Typing \\[verilog-auto] will make this into:
7985 module ex_arg (/*AUTOARG*/
7995 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
7996 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
7997 conservative guess on adding a comma for the first signal, if you have any
7998 ifdefs or complicated expressions before the AUTOARG you will need to
7999 choose the comma yourself.
8001 Avoid declaring ports manually, as it makes code harder to maintain."
8003 (let ((modi (verilog-modi-current))
8004 (skip-pins (aref (verilog-read-arg-pins) 0)))
8005 (verilog-repair-open-comma)
8006 (verilog-auto-arg-ports (verilog-signals-not-in
8007 (verilog-modi-get-outputs modi)
8010 verilog-indent-level-declaration)
8011 (verilog-auto-arg-ports (verilog-signals-not-in
8012 (verilog-modi-get-inouts modi)
8015 verilog-indent-level-declaration)
8016 (verilog-auto-arg-ports (verilog-signals-not-in
8017 (verilog-modi-get-inputs modi)
8020 verilog-indent-level-declaration)
8021 (verilog-repair-close-comma)
8022 (unless (eq (char-before) ?/ )
8024 (indent-to verilog-indent-level-declaration)
8027 (defun verilog-auto-inst-port-map (port-st)
8030 (defvar vector-skip-list nil) ; Prevent compile warning
8031 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
8032 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8033 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
8034 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
8035 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
8037 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
8038 "Print out a instantiation connection for this PORT-ST.
8039 Insert to INDENT-PT, use template TPL-LIST.
8040 @ are instantiation numbers, replaced with TPL-NUM.
8041 @\"(expression @)\" are evaluated, with @ as a variable."
8042 (let* ((port (verilog-sig-name port-st))
8043 (tpl-ass (or (assoc port (car tpl-list))
8044 (verilog-auto-inst-port-map port-st)))
8045 ;; vl-* are documented for user use
8046 (vl-name (verilog-sig-name port-st))
8047 (vl-width (verilog-sig-width port-st))
8048 (vl-bits (if (or verilog-auto-inst-vector
8049 (not (assoc port vector-skip-list))
8050 (not (equal (verilog-sig-bits port-st)
8051 (verilog-sig-bits (assoc port vector-skip-list)))))
8052 (or (verilog-sig-bits port-st) "")
8054 ;; Default if not found
8055 (tpl-net (if (verilog-sig-multidim port-st)
8056 (concat port "/*" (verilog-sig-multidim-string port-st)
8058 (concat port vl-bits)))
8059 (case-fold-search nil))
8061 (cond (tpl-ass ; Template of exact port name
8062 (setq tpl-net (nth 1 tpl-ass)))
8063 ((nth 1 tpl-list) ; Wildcards in template, search them
8064 (let ((wildcards (nth 1 tpl-list)))
8066 (when (string-match (nth 0 (car wildcards)) port)
8067 (setq tpl-ass (car wildcards) ; so allow @ parsing
8068 tpl-net (replace-match (nth 1 (car wildcards))
8070 (setq wildcards (cdr wildcards))))))
8071 ;; Parse Templated variable
8073 ;; Evaluate @"(lispcode)"
8074 (when (string-match "@\".*[^\\]\"" tpl-net)
8075 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
8078 (substring tpl-net 0 (match-beginning 0))
8080 (let* ((expr (match-string 1 tpl-net))
8083 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
8084 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
8085 (prin1 (eval (car (read-from-string expr)))
8086 (lambda (ch) ())))))
8087 (if (numberp value) (setq value (number-to-string value)))
8090 (substring tpl-net (match-end 0))))))
8091 ;; Replace @ and [] magic variables in final output
8092 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8093 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))
8095 (indent-to indent-pt)
8097 (indent-to verilog-auto-inst-column)
8098 (insert "(" tpl-net "),")
8100 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8101 verilog-auto-inst-column))
8102 (insert " // Templated")
8103 (when verilog-auto-inst-template-numbers
8104 (insert " T" (int-to-string (nth 2 tpl-ass))
8105 " L" (int-to-string (nth 3 tpl-ass)))))
8107 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8108 verilog-auto-inst-column))
8109 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
8111 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
8112 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
8113 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
8115 (defun verilog-auto-inst-first ()
8116 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
8117 ;; Do we need a trailing comma?
8118 ;; There maybe a ifdef or something similar before us. What a mess. Thus
8119 ;; to avoid trouble we only insert on preceeding ) or *.
8120 ;; Insert first port on new line
8121 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
8123 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
8124 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
8128 (defun verilog-auto-star ()
8129 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
8131 If `verilog-auto-star-expand' is set, .* pins are treated if they were
8132 AUTOINST statements, otherwise they are ignored. For safety, Verilog-Mode
8133 will also ignore any .* that are not last in your pin list (this prevents
8134 it from deleting pins following the .* when it expands the AUTOINST.)
8136 On writing your file, unless `verilog-auto-star-save' is set, any
8137 non-templated expanded pins will be removed. You may do this at any time
8138 with \\[verilog-delete-auto-star-implicit].
8140 If you are converting a module to use .* for the first time, you may wish
8141 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
8143 See `verilog-auto-inst' for examples, templates, and more information."
8144 (when (verilog-auto-star-safe)
8145 (verilog-auto-inst)))
8147 (defun verilog-auto-inst ()
8148 "Expand AUTOINST statements, as part of \\[verilog-auto].
8149 Replace the pin connections to an instantiation with ones
8150 automatically derived from the module header of the instantiated netlist.
8152 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
8153 and delete them before saving unless `verilog-auto-star-save' is set.
8154 See `verilog-auto-star' for more information.
8157 Module names must be resolvable to filenames by adding a
8158 `verilog-library-extensions', and being found in the same directory, or
8159 by changing the variable `verilog-library-flags' or
8160 `verilog-library-directories'. Macros `modname are translated through the
8161 vh-{name} Emacs variable, if that is not found, it just ignores the `.
8163 In templates you must have one signal per line, ending in a ), or ));,
8164 and have proper () nesting, including a final ); to end the template.
8166 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8168 SystemVerilog multidimmensional input/output has only experimental support.
8170 For example, first take the submodule inst.v:
8175 wire [31:0] o = {32{i}};
8178 This is then used in a upper level module:
8180 module ex_inst (o,i)
8183 inst inst (/*AUTOINST*/);
8186 Typing \\[verilog-auto] will make this into:
8188 module ex_inst (o,i)
8191 inst inst (/*AUTOINST*/
8198 Where the list of inputs and outputs came from the inst module.
8202 Unless you are instantiating a module multiple times, or the module is
8203 something trivial like a adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
8204 It just makes for unmaintainable code. To sanitize signal names, try
8205 vrename from http://www.veripool.com
8207 When you need to violate this suggestion there are two ways to list
8208 exceptions, placing them before the AUTOINST, or using templates.
8210 Any ports defined before the /*AUTOINST*/ are not included in the list of
8211 automatics. This is similar to making a template as described below, but
8212 is restricted to simple connections just like you normally make. Also note
8213 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
8214 you have the appropriate // Input or // Output comment, and exactly the
8215 same line formatting as AUTOINST itself uses.
8217 inst inst (// Inputs
8218 .i (my_i_dont_mess_with_it),
8226 For multiple instantiations based upon a single template, create a
8227 commented out template:
8229 /* instantiating_module_name AUTO_TEMPLATE (
8234 Templates go ABOVE the instantiation(s). When a instantiation is
8235 expanded `verilog-mode' simply searches up for the closest template.
8236 Thus you can have multiple templates for the same module, just alternate
8237 between the template for a instantiation and the instantiation itself.
8239 The module name must be the same as the name of the module in the
8240 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
8241 words and capitalized. Only signals that must be different for each
8242 instantiation need to be listed.
8244 Inside a template, a [] in a connection name (with nothing else inside
8245 the brackets) will be replaced by the same bus subscript as it is being
8246 connected to, or the [] will be removed if it is a single bit signal.
8247 Generally it is a good idea to do this for all connections in a template,
8248 as then they will work for any width signal, and with AUTOWIRE. See
8249 PTL_BUS becoming PTL_BUSNEW below.
8251 If you have a complicated template, set `verilog-auto-inst-template-numbers'
8252 to see which regexps are matching. Don't leave that mode set after
8253 debugging is completed though, it will result in lots of extra differences
8254 and merge conflicts.
8258 /* psm_mas AUTO_TEMPLATE (
8259 .ptl_bus (ptl_busnew[]),
8262 psm_mas ms2m (/*AUTOINST*/);
8264 Typing \\[verilog-auto] will make this into:
8266 psm_mas ms2m (/*AUTOINST*/
8268 .NotInTemplate (NotInTemplate),
8269 .ptl_bus (ptl_busnew[3:0]), // Templated
8274 It is common to instantiate a cell multiple times, so templates make it
8275 trivial to substitute part of the cell name into the connection name.
8277 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
8279 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
8283 If no regular expression is provided immediately after the AUTO_TEMPLATE
8284 keyword, then the @ character in any connection names will be replaced
8285 with the instantiation number; the first digits found in the cell's
8288 If a regular expression is provided, the @ character will be replaced
8289 with the first \(\) grouping that matches against the cell name. Using a
8290 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
8291 regexp is provided. If you use multiple layers of parenthesis,
8292 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
8293 characters after test and before _, whereas
8294 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
8299 /* psm_mas AUTO_TEMPLATE (
8300 .ptl_mapvalidx (ptl_mapvalid[@]),
8301 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
8304 psm_mas ms2m (/*AUTOINST*/);
8306 Typing \\[verilog-auto] will make this into:
8308 psm_mas ms2m (/*AUTOINST*/
8310 .ptl_mapvalidx (ptl_mapvalid[2]),
8311 .ptl_mapvalidp1x (ptl_mapvalid[3]));
8313 Note the @ character was replaced with the 2 from \"ms2m\".
8315 Alternatively, using a regular expression for @:
8317 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
8318 .ptl_mapvalidx (@_ptl_mapvalid),
8319 .ptl_mapvalidp1x (ptl_mapvalid_@),
8322 psm_mas ms2_FOO (/*AUTOINST*/);
8323 psm_mas ms2_BAR (/*AUTOINST*/);
8325 Typing \\[verilog-auto] will make this into:
8327 psm_mas ms2_FOO (/*AUTOINST*/
8329 .ptl_mapvalidx (FOO_ptl_mapvalid),
8330 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
8331 psm_mas ms2_BAR (/*AUTOINST*/
8333 .ptl_mapvalidx (BAR_ptl_mapvalid),
8334 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
8339 A template entry of the form
8341 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
8343 will apply a Emacs style regular expression search for any port beginning
8344 in pci_req followed by numbers and ending in _l and connecting that to
8345 the pci_req_jtag_[] net, with the bus subscript coming from what matches
8346 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
8348 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
8349 does the same thing. (Note a @ in the connection/replacement text is
8350 completely different -- still use \\1 there!) Thus this is the same as
8353 .pci_req@_l (pci_req_jtag_[\\1]),
8355 Here's another example to remove the _l, useful when naming conventions
8356 specify _ alone to mean active low. Note the use of [] to keep the bus
8359 .\\(.*\\)_l (\\1_[]),
8363 First any regular expression template is expanded.
8365 If the syntax @\"( ... )\" is found in a connection, the expression in
8366 quotes will be evaluated as a Lisp expression, with @ replaced by the
8367 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
8368 4 into the brackets. Quote all double-quotes inside the expression with
8369 a leading backslash (\\\"). There are special variables defined that are
8370 useful in these Lisp functions:
8372 vl-name Name portion of the input/output port
8373 vl-bits Bus bits portion of the input/output port ('[2:0]')
8374 vl-width Width of the input/output port ('3' for [2:0])
8375 May be a (...) expression if bits isn't a constant.
8376 vl-dir Direction of the pin input/output/inout.
8377 vl-cell-type Module name/type of the cell ('psm_mas')
8378 vl-cell-name Instance name of the cell ('ms2m')
8380 Normal Lisp variables may be used in expressions. See
8381 `verilog-read-defines' which can set vh-{definename} variables for use
8382 here. Also, any comments of the form:
8384 /*AUTO_LISP(setq foo 1)*/
8386 will evaluate any Lisp expression inside the parenthesis between the
8387 beginning of the buffer and the point of the AUTOINST. This allows
8388 functions to be defined or variables to be changed between instantiations.
8390 Note that when using lisp expressions errors may occur when @ is not a
8391 number, you may need to use the standard Emacs Lisp functions
8392 `number-to-string' and `string-to-number'.
8394 After the evaluation is completed, @ substitution and [] substitution
8399 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
8400 (indent-pt (save-excursion (verilog-backward-open-paren)
8401 (1+ (current-column))))
8402 (verilog-auto-inst-column (max verilog-auto-inst-column
8403 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8404 (modi (verilog-modi-current))
8405 (vector-skip-list (unless verilog-auto-inst-vector
8406 (verilog-modi-get-signals modi)))
8407 submod submodi inst skip-pins tpl-list tpl-num did-first)
8408 ;; Find module name that is instantiated
8409 (setq submod (verilog-read-inst-module)
8410 inst (verilog-read-inst-name)
8413 skip-pins (aref (verilog-read-inst-pins) 0))
8415 ;; Parse any AUTO_LISP() before here
8416 (verilog-read-auto-lisp (point-min) pt)
8418 ;; Lookup position, etc of submodule
8419 ;; Note this may raise an error
8420 (when (setq submodi (verilog-modi-lookup submod t))
8421 ;; If there's a number in the instantiation, it may be a argument to the
8422 ;; automatic variable instantiation program.
8423 (let* ((tpl-info (verilog-read-auto-template submod))
8424 (tpl-regexp (aref tpl-info 0)))
8425 (setq tpl-num (if (string-match tpl-regexp inst)
8426 (match-string 1 inst)
8428 tpl-list (aref tpl-info 1)))
8429 ;; Find submodule's signals and dump
8430 (let ((sig-list (verilog-signals-not-in
8431 (verilog-modi-get-outputs submodi)
8435 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8436 (indent-to indent-pt)
8437 (insert "// Outputs\n") ;; Note these are searched for in verilog-read-sub-decls
8438 (mapcar (function (lambda (port)
8439 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
8441 (let ((sig-list (verilog-signals-not-in
8442 (verilog-modi-get-inouts submodi)
8446 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8447 (indent-to indent-pt)
8448 (insert "// Inouts\n")
8449 (mapcar (function (lambda (port)
8450 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
8452 (let ((sig-list (verilog-signals-not-in
8453 (verilog-modi-get-inputs submodi)
8457 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8458 (indent-to indent-pt)
8459 (insert "// Inputs\n")
8460 (mapcar (function (lambda (port)
8461 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
8466 (re-search-backward "," pt t)
8469 (search-forward "\n") ;; Added by inst-port
8470 (delete-backward-char 1)
8471 (if (search-forward ")" nil t) ;; From user, moved up a line
8472 (delete-backward-char 1))
8473 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
8474 (delete-backward-char 1))
8478 (defun verilog-auto-inst-param ()
8479 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
8480 Replace the parameter connections to an instantiation with ones
8481 automatically derived from the module header of the instantiated netlist.
8483 See \\[verilog-auto-inst] for limitations, and templates to customize the
8486 For example, first take the submodule inst.v:
8492 This is then used in a upper level module:
8494 module ex_inst (o,i)
8496 inst #(/*AUTOINSTPARAM*/)
8497 inst (/*AUTOINST*/);
8500 Typing \\[verilog-auto] will make this into:
8502 module ex_inst (o,i)
8505 inst (/*AUTOINSTPARAM*/
8508 inst (/*AUTOINST*/);
8511 Where the list of parameter connections come from the inst module.
8515 You can customize the parameter connections using AUTO_TEMPLATEs,
8516 just as you would with \\[verilog-auto-inst]."
8520 (indent-pt (save-excursion (verilog-backward-open-paren)
8521 (1+ (current-column))))
8522 (verilog-auto-inst-column (max verilog-auto-inst-column
8523 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8524 (modi (verilog-modi-current))
8525 (vector-skip-list (unless verilog-auto-inst-vector
8526 (verilog-modi-get-signals modi)))
8527 submod submodi inst skip-pins tpl-list tpl-num did-first)
8528 ;; Find module name that is instantiated
8529 (setq submod (save-excursion
8530 ;; Get to the point where AUTOINST normally is to read the module
8531 (verilog-re-search-forward-quick "[(;]" nil nil)
8532 (verilog-read-inst-module))
8533 inst (save-excursion
8534 ;; Get to the point where AUTOINST normally is to read the module
8535 (verilog-re-search-forward-quick "[(;]" nil nil)
8536 (verilog-read-inst-name))
8539 skip-pins (aref (verilog-read-inst-pins) 0))
8541 ;; Parse any AUTO_LISP() before here
8542 (verilog-read-auto-lisp (point-min) pt)
8544 ;; Lookup position, etc of submodule
8545 ;; Note this may raise an error
8546 (when (setq submodi (verilog-modi-lookup submod t))
8547 ;; If there's a number in the instantiation, it may be a argument to the
8548 ;; automatic variable instantiation program.
8549 (let* ((tpl-info (verilog-read-auto-template submod))
8550 (tpl-regexp (aref tpl-info 0)))
8551 (setq tpl-num (if (string-match tpl-regexp inst)
8552 (match-string 1 inst)
8554 tpl-list (aref tpl-info 1)))
8555 ;; Find submodule's signals and dump
8556 (let ((sig-list (verilog-signals-not-in
8557 (verilog-modi-get-gparams submodi)
8559 (vl-dir "parameter"))
8561 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8562 (indent-to indent-pt)
8563 (insert "// Parameters\n") ;; Note these are searched for in verilog-read-sub-decls
8564 (mapcar (function (lambda (port)
8565 (verilog-auto-inst-port port indent-pt tpl-list tpl-num nil)))
8570 (re-search-backward "," pt t)
8573 (search-forward "\n") ;; Added by inst-port
8574 (delete-backward-char 1)
8575 (if (search-forward ")" nil t) ;; From user, moved up a line
8576 (delete-backward-char 1))
8580 (defun verilog-auto-reg ()
8581 "Expand AUTOREG statements, as part of \\[verilog-auto].
8582 Make reg statements for any output that isn't already declared,
8583 and isn't a wire output from a block.
8586 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8588 This does NOT work on memories, declare those yourself.
8599 Typing \\[verilog-auto] will make this into:
8605 // Beginning of automatic regs (for this module's undeclared outputs)
8607 // End of automatics
8611 ;; Point must be at insertion point.
8612 (let* ((indent-pt (current-indentation))
8613 (modi (verilog-modi-current))
8614 (sig-list (verilog-signals-not-in
8615 (verilog-modi-get-outputs modi)
8616 (append (verilog-modi-get-wires modi)
8617 (verilog-modi-get-regs modi)
8618 (verilog-modi-get-assigns modi)
8619 (verilog-modi-get-consts modi)
8620 (verilog-modi-get-gparams modi)
8621 (verilog-modi-get-sub-outputs modi)
8622 (verilog-modi-get-sub-inouts modi)
8626 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
8627 (verilog-insert-definition sig-list "reg" indent-pt nil)
8628 (verilog-modi-cache-add-regs modi sig-list)
8629 (verilog-insert-indent "// End of automatics\n"))
8632 (defun verilog-auto-reg-input ()
8633 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
8634 Make reg statements instantiation inputs that aren't already declared.
8635 This is useful for making a top level shell for testing the module that is
8639 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
8641 This does NOT work on memories, declare those yourself.
8643 An example (see `verilog-auto-inst' for what else is going on here):
8645 module ex_reg_input (o,i)
8649 inst inst (/*AUTOINST*/);
8652 Typing \\[verilog-auto] will make this into:
8654 module ex_reg_input (o,i)
8658 // Beginning of automatic reg inputs (for undeclared ...
8659 reg [31:0] iv; // From inst of inst.v
8660 // End of automatics
8661 inst inst (/*AUTOINST*/
8668 ;; Point must be at insertion point.
8669 (let* ((indent-pt (current-indentation))
8670 (modi (verilog-modi-current))
8671 (sig-list (verilog-signals-combine-bus
8672 (verilog-signals-not-in
8673 (append (verilog-modi-get-sub-inputs modi)
8674 (verilog-modi-get-sub-inouts modi))
8675 (verilog-modi-get-signals modi)
8679 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
8680 (verilog-insert-definition sig-list "reg" indent-pt nil)
8681 (verilog-modi-cache-add-regs modi sig-list)
8682 (verilog-insert-indent "// End of automatics\n"))
8685 (defun verilog-auto-wire ()
8686 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
8687 Make wire statements for instantiations outputs that aren't
8691 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
8692 and all busses must have widths, such as those from AUTOINST, or using []
8695 This does NOT work on memories or SystemVerilog .name connections,
8696 declare those yourself.
8698 Verilog-mode will add \"Couldn't Merge\" comments to signals it cannot
8699 determine how to bus together. This occurs when you have ports with
8700 non-numeric or non-sequential bus subscripts. If Verilog-Mode
8701 mis-guessed, you'll have to declare them yourself.
8703 An example (see `verilog-auto-inst' for what else is going on here):
8705 module ex_wire (o,i)
8709 inst inst (/*AUTOINST*/);
8712 Typing \\[verilog-auto] will make this into:
8714 module ex_wire (o,i)
8718 // Beginning of automatic wires
8719 wire [31:0] ov; // From inst of inst.v
8720 // End of automatics
8721 inst inst (/*AUTOINST*/
8729 ;; Point must be at insertion point.
8730 (let* ((indent-pt (current-indentation))
8731 (modi (verilog-modi-current))
8732 (sig-list (verilog-signals-combine-bus
8733 (verilog-signals-not-in
8734 (append (verilog-modi-get-sub-outputs modi)
8735 (verilog-modi-get-sub-inouts modi))
8736 (verilog-modi-get-signals modi)
8740 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
8741 (verilog-insert-definition sig-list "wire" indent-pt nil)
8742 (verilog-modi-cache-add-wires modi sig-list)
8743 (verilog-insert-indent "// End of automatics\n")
8744 (when nil ;; Too slow on huge modules, plus makes everyone's module change
8747 (verilog-pretty-declarations)
8749 (verilog-pretty-expr "//")))
8752 (defun verilog-auto-output ()
8753 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
8754 Make output statements for any output signal from an /*AUTOINST*/ that
8755 isn't a input to another AUTOINST. This is useful for modules which
8756 only instantiate other modules.
8759 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8761 If placed inside the parenthesis of a module declaration, it creates
8762 Verilog 2001 style, else uses Verilog 1995 style.
8764 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8765 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8767 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8769 Signals matching `verilog-auto-output-ignore-regexp' are not included.
8771 An example (see `verilog-auto-inst' for what else is going on here):
8773 module ex_output (ov,i)
8776 inst inst (/*AUTOINST*/);
8779 Typing \\[verilog-auto] will make this into:
8781 module ex_output (ov,i)
8784 // Beginning of automatic outputs (from unused autoinst outputs)
8785 output [31:0] ov; // From inst of inst.v
8786 // End of automatics
8787 inst inst (/*AUTOINST*/
8794 ;; Point must be at insertion point.
8795 (let* ((indent-pt (current-indentation))
8796 (v2k (verilog-in-paren))
8797 (modi (verilog-modi-current))
8798 (sig-list (verilog-signals-not-in
8799 (verilog-modi-get-sub-outputs modi)
8800 (append (verilog-modi-get-outputs modi)
8801 (verilog-modi-get-inouts modi)
8802 (verilog-modi-get-sub-inputs modi)
8803 (verilog-modi-get-sub-inouts modi)
8805 (setq sig-list (verilog-signals-not-matching-regexp
8806 sig-list verilog-auto-output-ignore-regexp))
8808 (when v2k (verilog-repair-open-comma))
8810 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
8811 (verilog-insert-definition sig-list "output" indent-pt v2k)
8812 (verilog-modi-cache-add-outputs modi sig-list)
8813 (verilog-insert-indent "// End of automatics\n"))
8814 (when v2k (verilog-repair-close-comma))
8817 (defun verilog-auto-output-every ()
8818 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
8819 Make output statements for any signals that aren't primary inputs or
8820 outputs already. This makes every signal in the design a output. This is
8821 useful to get Synopsys to preserve every signal in the design, since it
8822 won't optimize away the outputs.
8826 module ex_output_every (o,i,tempa,tempb)
8835 Typing \\[verilog-auto] will make this into:
8837 module ex_output_every (o,i,tempa,tempb)
8841 // Beginning of automatic outputs (every signal)
8844 // End of automatics
8850 ;;Point must be at insertion point
8851 (let* ((indent-pt (current-indentation))
8852 (v2k (verilog-in-paren))
8853 (modi (verilog-modi-current))
8854 (sig-list (verilog-signals-combine-bus
8855 (verilog-signals-not-in
8856 (verilog-modi-get-signals modi)
8857 (verilog-modi-get-ports modi)
8860 (when v2k (verilog-repair-open-comma))
8862 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
8863 (verilog-insert-definition sig-list "output" indent-pt v2k)
8864 (verilog-modi-cache-add-outputs modi sig-list)
8865 (verilog-insert-indent "// End of automatics\n"))
8866 (when v2k (verilog-repair-close-comma))
8869 (defun verilog-auto-input ()
8870 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
8871 Make input statements for any input signal into an /*AUTOINST*/ that
8872 isn't declared elsewhere inside the module. This is useful for modules which
8873 only instantiate other modules.
8876 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8878 If placed inside the parenthesis of a module declaration, it creates
8879 Verilog 2001 style, else uses Verilog 1995 style.
8881 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8882 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8884 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8886 Signals matching `verilog-auto-input-ignore-regexp' are not included.
8888 An example (see `verilog-auto-inst' for what else is going on here):
8890 module ex_input (ov,i)
8893 inst inst (/*AUTOINST*/);
8896 Typing \\[verilog-auto] will make this into:
8898 module ex_input (ov,i)
8901 // Beginning of automatic inputs (from unused autoinst inputs)
8902 input i; // From inst of inst.v
8903 // End of automatics
8904 inst inst (/*AUTOINST*/
8911 (let* ((indent-pt (current-indentation))
8912 (v2k (verilog-in-paren))
8913 (modi (verilog-modi-current))
8914 (sig-list (verilog-signals-not-in
8915 (verilog-modi-get-sub-inputs modi)
8916 (append (verilog-modi-get-inputs modi)
8917 (verilog-modi-get-inouts modi)
8918 (verilog-modi-get-wires modi)
8919 (verilog-modi-get-regs modi)
8920 (verilog-modi-get-consts modi)
8921 (verilog-modi-get-gparams modi)
8922 (verilog-modi-get-sub-outputs modi)
8923 (verilog-modi-get-sub-inouts modi)
8925 (setq sig-list (verilog-signals-not-matching-regexp
8926 sig-list verilog-auto-input-ignore-regexp))
8928 (when v2k (verilog-repair-open-comma))
8930 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
8931 (verilog-insert-definition sig-list "input" indent-pt v2k)
8932 (verilog-modi-cache-add-inputs modi sig-list)
8933 (verilog-insert-indent "// End of automatics\n"))
8934 (when v2k (verilog-repair-close-comma))
8937 (defun verilog-auto-inout ()
8938 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
8939 Make inout statements for any inout signal in an /*AUTOINST*/ that
8940 isn't declared elsewhere inside the module.
8943 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8945 If placed inside the parenthesis of a module declaration, it creates
8946 Verilog 2001 style, else uses Verilog 1995 style.
8948 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8949 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8951 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8953 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
8955 An example (see `verilog-auto-inst' for what else is going on here):
8957 module ex_inout (ov,i)
8960 inst inst (/*AUTOINST*/);
8963 Typing \\[verilog-auto] will make this into:
8965 module ex_inout (ov,i)
8968 // Beginning of automatic inouts (from unused autoinst inouts)
8969 inout [31:0] ov; // From inst of inst.v
8970 // End of automatics
8971 inst inst (/*AUTOINST*/
8978 ;; Point must be at insertion point.
8979 (let* ((indent-pt (current-indentation))
8980 (v2k (verilog-in-paren))
8981 (modi (verilog-modi-current))
8982 (sig-list (verilog-signals-not-in
8983 (verilog-modi-get-sub-inouts modi)
8984 (append (verilog-modi-get-outputs modi)
8985 (verilog-modi-get-inouts modi)
8986 (verilog-modi-get-inputs modi)
8987 (verilog-modi-get-sub-inputs modi)
8988 (verilog-modi-get-sub-outputs modi)
8990 (setq sig-list (verilog-signals-not-matching-regexp
8991 sig-list verilog-auto-inout-ignore-regexp))
8993 (when v2k (verilog-repair-open-comma))
8995 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
8996 (verilog-insert-definition sig-list "inout" indent-pt v2k)
8997 (verilog-modi-cache-add-inouts modi sig-list)
8998 (verilog-insert-indent "// End of automatics\n"))
8999 (when v2k (verilog-repair-close-comma))
9002 (defun verilog-auto-inout-module ()
9003 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
9004 Take input/output/inout statements from the specified module and insert
9005 into the current module. This is useful for making null templates and
9006 shell modules which need to have identical I/O with another module. Any
9007 I/O which are already defined in this module will not be redefined.
9010 If placed inside the parenthesis of a module declaration, it creates
9011 Verilog 2001 style, else uses Verilog 1995 style.
9013 Concatenation and outputting partial busses is not supported.
9015 Module names must be resolvable to filenames. See `verilog-auto-inst'.
9017 Signals are not inserted in the same order as in the original module,
9018 though they will appear to be in the same order to a AUTOINST
9019 instantiating either module.
9023 module ex_shell (/*AUTOARG*/)
9024 /*AUTOINOUTMODULE(\"ex_main\")*/
9027 module ex_main (i,o,io)
9033 Typing \\[verilog-auto] will make this into:
9035 module ex_shell (/*AUTOARG*/i,o,io)
9036 /*AUTOINOUTMODULE(\"ex_main\")*/
9037 // Beginning of automatic in/out/inouts (from specific module)
9041 // End of automatics
9044 (let* ((submod (car (verilog-read-auto-params 1))) submodi)
9045 ;; Lookup position, etc of co-module
9046 ;; Note this may raise an error
9047 (when (setq submodi (verilog-modi-lookup submod t))
9048 (let* ((indent-pt (current-indentation))
9049 (v2k (verilog-in-paren))
9050 (modi (verilog-modi-current))
9051 (sig-list-i (verilog-signals-not-in
9052 (verilog-modi-get-inputs submodi)
9053 (append (verilog-modi-get-inputs modi))))
9054 (sig-list-o (verilog-signals-not-in
9055 (verilog-modi-get-outputs submodi)
9056 (append (verilog-modi-get-outputs modi))))
9057 (sig-list-io (verilog-signals-not-in
9058 (verilog-modi-get-inouts submodi)
9059 (append (verilog-modi-get-inouts modi)))))
9061 (when v2k (verilog-repair-open-comma))
9062 (when (or sig-list-i sig-list-o sig-list-io)
9063 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
9064 ;; Don't sort them so a upper AUTOINST will match the main module
9065 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
9066 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
9067 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
9068 (verilog-modi-cache-add-inputs modi sig-list-i)
9069 (verilog-modi-cache-add-outputs modi sig-list-o)
9070 (verilog-modi-cache-add-inouts modi sig-list-io)
9071 (verilog-insert-indent "// End of automatics\n"))
9072 (when v2k (verilog-repair-close-comma))
9075 (defun verilog-auto-sense-sigs (modi presense-sigs)
9076 "Return list of signals for current AUTOSENSE block."
9077 (let* ((sigss (verilog-read-always-signals))
9078 (sig-list (verilog-signals-not-params
9079 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
9080 (append (and (not verilog-auto-sense-include-inputs)
9081 (verilog-alw-get-outputs sigss))
9082 (verilog-modi-get-consts modi)
9083 (verilog-modi-get-gparams modi)
9087 (defun verilog-auto-sense ()
9088 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
9089 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
9090 with one automatically derived from all inputs declared in the always
9091 statement. Signals that are generated within the same always block are NOT
9092 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
9093 Long lines are split based on the `fill-column', see \\[set-fill-column].
9096 Verilog does not allow memories (multidimensional arrays) in sensitivity
9097 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
9100 AUTOSENSE cannot always determine if a `define is a constant or a signal
9101 (it could be in a include file for example). If a `define or other signal
9102 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
9103 declaration anywhere in the module (parenthesis are required):
9105 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
9107 Better yet, use a parameter, which will be understood to be constant
9111 If AUTOSENSE makes a mistake, please report it. (First try putting
9112 a begin/end after your always!) As a workaround, if a signal that
9113 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
9114 If a signal should be in the sensitivity list wasn't, placing it before
9115 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
9116 autos are updated (or added if it occurs there already).
9120 always @ (/*AUTOSENSE*/) begin
9121 /* AUTO_CONSTANT (`constant) */
9122 outin = ina | inb | `constant;
9126 Typing \\[verilog-auto] will make this into:
9128 always @ (/*AUTOSENSE*/ina or inb) begin
9129 /* AUTO_CONSTANT (`constant) */
9130 outin = ina | inb | `constant;
9135 (let* ((start-pt (save-excursion
9136 (verilog-re-search-backward "(" nil t)
9138 (indent-pt (save-excursion
9139 (or (and (goto-char start-pt) (1+ (current-column)))
9140 (current-indentation))))
9141 (modi (verilog-modi-current))
9142 (sig-memories (verilog-signals-memory
9144 (verilog-modi-get-regs modi)
9145 (verilog-modi-get-wires modi))))
9146 sig-list not-first presense-sigs)
9147 ;; Read signals in always, eliminate outputs from sense list
9148 (setq presense-sigs (verilog-signals-from-signame
9150 (verilog-read-signals start-pt (point)))))
9151 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
9153 (let ((tlen (length sig-list)))
9154 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
9155 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
9156 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
9157 (save-excursion (goto-char (point))
9158 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9159 (verilog-re-search-backward "\\s-" start-pt t)
9160 (while (looking-at "\\s-`endif")
9161 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9162 (verilog-re-search-backward "\\s-" start-pt t))
9163 (not (looking-at "\\s-or\\b"))))
9165 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9167 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
9169 (indent-to indent-pt)
9170 (if not-first (insert "or ")))
9171 (not-first (insert " or ")))
9172 (insert (verilog-sig-name (car sig-list)))
9173 (setq sig-list (cdr sig-list)
9177 (defun verilog-auto-reset ()
9178 "Expand AUTORESET statements, as part of \\[verilog-auto].
9179 Replace the /*AUTORESET*/ comment with code to initialize all
9180 registers set elsewhere in the always block.
9183 AUTORESET will not clear memories.
9185 AUTORESET uses <= if there are any <= in the block, else it uses =.
9187 /*AUTORESET*/ presumes that any signals mentioned between the previous
9188 begin/case/if statement and the AUTORESET comment are being reset manually
9189 and should not be automatically reset. This includes omitting any signals
9190 used on the right hand side of assignments.
9192 By default, AUTORESET will include the width of the signal in the autos,
9193 this is a recent change. To control this behavior, see
9194 `verilog-auto-reset-widths'.
9196 AUTORESET ties signals to deasserted, which is presumed to be zero.
9197 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9202 always @(posedge clk or negedge reset_l) begin
9214 Typing \\[verilog-auto] will make this into:
9216 always @(posedge core_clk or negedge reset_l) begin
9220 // Beginning of autoreset for uninitialized flops
9223 // End of automatics
9235 (let* ((indent-pt (current-indentation))
9236 (modi (verilog-modi-current))
9237 (all-list (verilog-modi-get-signals modi))
9238 sigss sig-list prereset-sigs assignment-str)
9239 ;; Read signals in always, eliminate outputs from reset list
9240 (setq prereset-sigs (verilog-signals-from-signame
9242 (verilog-read-signals
9244 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
9248 (verilog-re-search-backward "@" nil t)
9249 (setq sigss (verilog-read-always-signals)))
9250 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
9251 (concat " <= " verilog-assignment-delay)
9253 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
9255 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9258 (indent-to indent-pt)
9259 (insert "// Beginning of autoreset for uninitialized flops\n");
9260 (indent-to indent-pt)
9262 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
9264 (insert (verilog-sig-name sig)
9266 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
9268 (indent-to indent-pt)
9269 (setq sig-list (cdr sig-list))))
9270 (insert "// End of automatics"))
9273 (defun verilog-auto-tieoff ()
9274 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
9275 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
9276 signals to deasserted.
9278 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
9279 input/output list as another module, but no internals. Specifically, it
9280 finds all outputs in the module, and if that input is not otherwise declared
9281 as a register or wire, creates a tieoff.
9283 AUTORESET ties signals to deasserted, which is presumed to be zero.
9284 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9287 An example of making a stub for another module:
9289 module FooStub (/*AUTOINST*/);
9290 /*AUTOINOUTMODULE(\"Foo\")*/
9292 // verilator lint_off UNUSED
9293 wire _unused_ok = &{1'b0,
9296 // verilator lint_on UNUSED
9299 Typing \\[verilog-auto] will make this into:
9301 module FooStub (/*AUTOINST*/...);
9302 /*AUTOINOUTMODULE(\"Foo\")*/
9303 // Beginning of autotieoff
9305 // End of automatics
9308 // Beginning of autotieoff
9309 wire [2:0] foo = 3'b0;
9310 // End of automatics
9316 (let* ((indent-pt (current-indentation))
9317 (modi (verilog-modi-current))
9318 (sig-list (verilog-signals-not-in
9319 (verilog-modi-get-outputs modi)
9320 (append (verilog-modi-get-wires modi)
9321 (verilog-modi-get-regs modi)
9322 (verilog-modi-get-assigns modi)
9323 (verilog-modi-get-consts modi)
9324 (verilog-modi-get-gparams modi)
9325 (verilog-modi-get-sub-outputs modi)
9326 (verilog-modi-get-sub-inouts modi)
9330 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
9331 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9332 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
9334 (let ((sig (car sig-list)))
9335 (verilog-insert-one-definition sig "wire" indent-pt)
9336 (indent-to (max 48 (+ indent-pt 40)))
9337 (insert "= " (verilog-sig-tieoff sig)
9339 (setq sig-list (cdr sig-list))))
9340 (verilog-insert-indent "// End of automatics\n")
9343 (defun verilog-auto-unused ()
9344 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
9345 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
9346 input and inout signals.
9348 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
9349 input/output list as another module, but no internals. Specifically, it
9350 finds all inputs and inouts in the module, and if that input is not otherwise
9351 used, adds it to a comma separated list.
9353 The comma separated list is intended to be used to create a _unused_ok
9354 signal. Using the exact name \"_unused_ok\" for name of the temporary
9355 signal is recommended as it will insure maximum forward compatibility, it
9356 also makes lint warnings easy to understand; ignore any unused warnings
9357 with \"unused\" in the signal name.
9359 To reduce simulation time, the _unused_ok signal should be forced to a
9360 constant to prevent wiggling. The easiest thing to do is use a
9361 reduction-and with 1'b0 as shown.
9363 This way all unused signals are in one place, making it convenient to add
9364 your tool's specific pragmas around the assignment to disable any unused
9367 You can add signals you do not want included in AUTOUNUSED with
9368 `verilog-auto-unused-ignore-regexp'.
9370 An example of making a stub for another module:
9372 module FooStub (/*AUTOINST*/);
9373 /*AUTOINOUTMODULE(\"Foo\")*/
9375 // verilator lint_off UNUSED
9376 wire _unused_ok = &{1'b0,
9379 // verilator lint_on UNUSED
9382 Typing \\[verilog-auto] will make this into:
9385 // verilator lint_off UNUSED
9386 wire _unused_ok = &{1'b0,
9388 // Beginning of automatics
9392 // End of automatics
9394 // verilator lint_on UNUSED
9399 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
9400 (modi (verilog-modi-current))
9401 (sig-list (verilog-signals-not-in
9402 (append (verilog-modi-get-inputs modi)
9403 (verilog-modi-get-inouts modi))
9404 (append (verilog-modi-get-sub-inputs modi)
9405 (verilog-modi-get-sub-inouts modi)
9407 (setq sig-list (verilog-signals-not-matching-regexp
9408 sig-list verilog-auto-unused-ignore-regexp))
9411 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
9412 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9414 (let ((sig (car sig-list)))
9415 (indent-to indent-pt)
9416 (insert (verilog-sig-name sig) ",\n")
9417 (setq sig-list (cdr sig-list))))
9418 (verilog-insert-indent "// End of automatics\n")
9421 (defun verilog-enum-ascii (signm elim-regexp)
9422 "Convert a enum name SIGNM to a ascii string for insertion.
9423 Remove user provided prefix ELIM-REGEXP."
9424 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
9425 (let ((case-fold-search t))
9426 ;; All upper becomes all lower for readability
9427 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
9429 (defun verilog-auto-ascii-enum ()
9430 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
9431 Create a register to contain the ASCII decode of a enumerated signal type.
9432 This will allow trace viewers to show the ASCII name of states.
9434 First, parameters are built into a enumeration using the synopsys enum
9435 comment. The comment must be between the keyword and the symbol.
9436 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
9438 Next, registers which that enum applies to are also tagged with the same
9439 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
9442 Finally, a AUTOASCIIENUM command is used.
9444 The first parameter is the name of the signal to be decoded.
9446 The second parameter is the name to store the ASCII code into. For the
9447 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
9448 a signal that is just for simulation, and the magic characters _ascii
9449 tell viewers like Dinotrace to display in ASCII format.
9451 The final optional parameter is a string which will be removed from the
9456 //== State enumeration
9457 parameter [2:0] // synopsys enum state_info
9461 //== State variables
9462 reg [2:0] /* synopsys enum state_info */
9463 state_r; /* synopsys state_vector state_r */
9464 reg [2:0] /* synopsys enum state_info */
9467 //== ASCII state decoding
9469 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9471 Typing \\[verilog-auto] will make this into:
9473 ... same front matter ...
9475 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9476 // Beginning of automatic ASCII enum decoding
9477 reg [39:0] state_ascii_r; // Decode of state_r
9478 always @(state_r) begin
9480 SM_IDLE: state_ascii_r = \"idle \";
9481 SM_SEND: state_ascii_r = \"send \";
9482 SM_WAIT1: state_ascii_r = \"wait1\";
9483 default: state_ascii_r = \"%Erro\";
9486 // End of automatics"
9488 (let* ((params (verilog-read-auto-params 2 3))
9489 (undecode-name (nth 0 params))
9490 (ascii-name (nth 1 params))
9491 (elim-regexp (nth 2 params))
9493 (indent-pt (current-indentation))
9494 (modi (verilog-modi-current))
9496 (sig-list-consts (append (verilog-modi-get-consts modi)
9497 (verilog-modi-get-gparams modi)))
9498 (sig-list-all (append (verilog-modi-get-regs modi)
9499 (verilog-modi-get-outputs modi)
9500 (verilog-modi-get-inouts modi)
9501 (verilog-modi-get-inputs modi)
9502 (verilog-modi-get-wires modi)))
9504 (undecode-sig (or (assoc undecode-name sig-list-all)
9505 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
9506 (undecode-enum (or (verilog-sig-enum undecode-sig)
9507 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
9509 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
9510 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
9515 ;; Find number of ascii chars needed
9516 (let ((tmp-sigs enum-sigs))
9518 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
9519 ascii-chars (max ascii-chars (length (verilog-enum-ascii
9520 (verilog-sig-name (car tmp-sigs))
9522 tmp-sigs (cdr tmp-sigs))))
9525 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
9526 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
9527 (concat "Decode of " undecode-name) nil nil))))
9528 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
9529 (verilog-modi-cache-add-regs modi decode-sig-list))
9531 (verilog-insert-indent "always @(" undecode-name ") begin\n")
9532 (setq indent-pt (+ indent-pt verilog-indent-level))
9533 (indent-to indent-pt)
9534 (insert "case ({" undecode-name "})\n")
9535 (setq indent-pt (+ indent-pt verilog-case-indent))
9537 (let ((tmp-sigs enum-sigs)
9538 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
9539 ascii-name ascii-chars))
9540 (errname (substring "%Error" 0 (min 6 ascii-chars))))
9542 (verilog-insert-indent
9543 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
9544 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
9546 (setq tmp-sigs (cdr tmp-sigs)))
9547 (verilog-insert-indent (format chrfmt "default:" errname)))
9549 (setq indent-pt (- indent-pt verilog-case-indent))
9550 (verilog-insert-indent "endcase\n")
9551 (setq indent-pt (- indent-pt verilog-indent-level))
9552 (verilog-insert-indent "end\n"
9553 "// End of automatics\n")
9556 (defun verilog-auto-templated-rel ()
9557 "Replace Templated relative line numbers with absolute line numbers.
9558 Internal use only. This hacks around the line numbers in AUTOINST Templates
9559 being different from the final output's line numbering."
9560 (let ((templateno 0) (template-line (list 0)))
9561 ;; Find line number each template is on
9562 (goto-char (point-min))
9563 (while (search-forward "AUTO_TEMPLATE" nil t)
9564 (setq templateno (1+ templateno))
9565 (setq template-line (cons (count-lines (point-min) (point)) template-line)))
9566 (setq template-line (nreverse template-line))
9567 ;; Replace T# L# with absolute line number
9568 (goto-char (point-min))
9569 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
9570 (replace-match (concat " Templated "
9571 (int-to-string (+ (nth (string-to-int (match-string 1))
9573 (string-to-int (match-string 2)))))
9581 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
9582 "Expand AUTO statements.
9583 Look for any /*AUTO...*/ commands in the code, as used in
9584 instantiations or argument headers. Update the list of signals
9585 following the /*AUTO...*/ command.
9587 Use \\[verilog-delete-auto] to remove the AUTOs.
9589 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
9591 Use \\[verilog-faq] for a pointer to frequently asked questions.
9593 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
9594 called before and after this function, respectively.
9597 module (/*AUTOARG*/)
9602 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
9604 You can also update the AUTOs from the shell using:
9605 emacs --batch <filenames.v> -f verilog-batch-auto
9606 Or fix indentation with:
9607 emacs --batch <filenames.v> -f verilog-batch-indent
9608 Likewise, you can delete or inject AUTOs with:
9609 emacs --batch <filenames.v> -f verilog-batch-delete-auto
9610 emacs --batch <filenames.v> -f verilog-batch-inject-auto
9612 Using \\[describe-function], see also:
9613 `verilog-auto-arg' for AUTOARG module instantiations
9614 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
9615 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
9616 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
9617 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
9618 `verilog-auto-inst' for AUTOINST instantiation pins
9619 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
9620 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
9621 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
9622 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
9623 `verilog-auto-reg' for AUTOREG registers
9624 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
9625 `verilog-auto-reset' for AUTORESET flop resets
9626 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
9627 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
9628 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
9629 `verilog-auto-wire' for AUTOWIRE instantiation wires
9631 `verilog-read-defines' for reading `define values
9632 `verilog-read-includes' for reading `includes
9634 If you have bugs with these autos, try contacting the AUTOAUTHOR
9635 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
9637 (unless noninteractive (message "Updating AUTOs..."))
9638 (if (featurep 'dinotrace)
9639 (dinotrace-unannotate-all))
9640 (let ((oldbuf (if (not (buffer-modified-p))
9642 ;; Before version 20, match-string with font-lock returns a
9643 ;; vector that is not equal to the string. IE if on "input"
9644 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
9645 (fontlocked (when (and (boundp 'font-lock-mode)
9647 (font-lock-mode nil)
9651 ;; If we're not in verilog-mode, change syntax table so parsing works right
9652 (unless (eq major-mode `verilog-mode) (verilog-mode))
9653 ;; Allow user to customize
9654 (run-hooks 'verilog-before-auto-hook)
9655 ;; Try to save the user from needing to revert-file to reread file local-variables
9656 (verilog-auto-reeval-locals)
9657 (verilog-read-auto-lisp (point-min) (point-max))
9658 (verilog-getopt-flags)
9659 ;; These two may seem obvious to do always, but on large includes it can be way too slow
9660 (when verilog-auto-read-includes
9661 (verilog-read-includes)
9662 (verilog-read-defines nil nil t))
9663 ;; This particular ordering is important
9664 ;; INST: Lower modules correct, no internal dependencies, FIRST
9665 (verilog-preserve-cache
9666 ;; Clear existing autos else we'll be screwed by existing ones
9667 (verilog-delete-auto)
9668 ;; Injection if appropriate
9670 (verilog-inject-inst)
9671 (verilog-inject-sense)
9672 (verilog-inject-arg))
9674 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
9675 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
9676 (verilog-auto-search-do ".*" 'verilog-auto-star)
9677 ;; Doesn't matter when done, but combine it with a common changer
9678 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
9679 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
9680 ;; Must be done before autoin/out as creates a reg
9681 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
9683 ;; first in/outs from other files
9684 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
9685 ;; next in/outs which need previous sucked inputs first
9686 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
9687 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
9688 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout)
9689 ;; Then tie off those in/outs
9690 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
9691 ;; Wires/regs must be after inputs/outputs
9692 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
9693 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
9694 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
9695 ;; outputevery needs AUTOOUTPUTs done first
9696 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
9697 ;; After we've created all new variables
9698 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
9699 ;; Must be after all inputs outputs are generated
9700 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
9701 ;; Fix line numbers (comments only)
9702 (verilog-auto-templated-rel)
9705 (run-hooks 'verilog-auto-hook)
9707 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
9709 ;; If end result is same as when started, clear modified flag
9710 (cond ((and oldbuf (equal oldbuf (buffer-string)))
9711 (set-buffer-modified-p nil)
9712 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
9713 (t (unless noninteractive (message "Updating AUTOs...done")))))
9716 ;; Restore font-lock
9717 (when fontlocked (font-lock-mode t)))
9722 ;; Skeleton based code insertion
9724 (defvar verilog-template-map
9725 (let ((map (make-sparse-keymap)))
9726 (define-key map "a" 'verilog-sk-always)
9727 (define-key map "b" 'verilog-sk-begin)
9728 (define-key map "c" 'verilog-sk-case)
9729 (define-key map "f" 'verilog-sk-for)
9730 (define-key map "g" 'verilog-sk-generate)
9731 (define-key map "h" 'verilog-sk-header)
9732 (define-key map "i" 'verilog-sk-initial)
9733 (define-key map "j" 'verilog-sk-fork)
9734 (define-key map "m" 'verilog-sk-module)
9735 (define-key map "p" 'verilog-sk-primitive)
9736 (define-key map "r" 'verilog-sk-repeat)
9737 (define-key map "s" 'verilog-sk-specify)
9738 (define-key map "t" 'verilog-sk-task)
9739 (define-key map "w" 'verilog-sk-while)
9740 (define-key map "x" 'verilog-sk-casex)
9741 (define-key map "z" 'verilog-sk-casez)
9742 (define-key map "?" 'verilog-sk-if)
9743 (define-key map ":" 'verilog-sk-else-if)
9744 (define-key map "/" 'verilog-sk-comment)
9745 (define-key map "A" 'verilog-sk-assign)
9746 (define-key map "F" 'verilog-sk-function)
9747 (define-key map "I" 'verilog-sk-input)
9748 (define-key map "O" 'verilog-sk-output)
9749 (define-key map "S" 'verilog-sk-state-machine)
9750 (define-key map "=" 'verilog-sk-inout)
9751 (define-key map "W" 'verilog-sk-wire)
9752 (define-key map "R" 'verilog-sk-reg)
9753 (define-key map "D" 'verilog-sk-define-signal)
9755 "Keymap used in Verilog mode for smart template operations.")
9759 ;; Place the templates into Verilog Mode. They may be inserted under any key.
9760 ;; C-c C-t will be the default. If you use templates a lot, you
9761 ;; may want to consider moving the binding to another key in your .emacs
9764 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
9765 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
9767 ;;; ---- statement skeletons ------------------------------------------
9769 (define-skeleton verilog-sk-prompt-condition
9770 "Prompt for the loop condition."
9771 "[condition]: " str )
9773 (define-skeleton verilog-sk-prompt-init
9774 "Prompt for the loop init statement."
9775 "[initial statement]: " str )
9777 (define-skeleton verilog-sk-prompt-inc
9778 "Prompt for the loop increment statement."
9779 "[increment statement]: " str )
9781 (define-skeleton verilog-sk-prompt-name
9782 "Prompt for the name of something."
9785 (define-skeleton verilog-sk-prompt-clock
9786 "Prompt for the name of something."
9787 "name and edge of clock(s): " str)
9789 (defvar verilog-sk-reset nil)
9790 (defun verilog-sk-prompt-reset ()
9791 "Prompt for the name of a state machine reset."
9792 (setq verilog-sk-reset (read-input "name of reset: " "rst")))
9795 (define-skeleton verilog-sk-prompt-state-selector
9796 "Prompt for the name of a state machine selector."
9797 "name of selector (eg {a,b,c,d}): " str )
9799 (define-skeleton verilog-sk-prompt-output
9800 "Prompt for the name of something."
9803 (define-skeleton verilog-sk-prompt-msb
9804 "Prompt for least significant bit specification."
9805 "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 )
9807 (define-skeleton verilog-sk-prompt-lsb
9808 "Prompt for least significant bit specification."
9811 (defvar verilog-sk-p nil)
9812 (define-skeleton verilog-sk-prompt-width
9813 "Prompt for a width specification."
9816 (setq verilog-sk-p (point))
9817 (verilog-sk-prompt-msb)
9818 (if (> (point) verilog-sk-p) "] " " ")))
9820 (defun verilog-sk-header ()
9821 "Insert a descriptive header at the top of the file."
9824 (goto-char (point-min))
9825 (verilog-sk-header-tmpl)))
9827 (define-skeleton verilog-sk-header-tmpl
9828 "Insert a comment block containing the module title, author, etc."
9830 "// -*- Mode: Verilog -*-"
9831 "\n// Filename : " (buffer-name)
9832 "\n// Description : " str
9833 "\n// Author : " (user-full-name)
9834 "\n// Created On : " (current-time-string)
9835 "\n// Last Modified By: ."
9836 "\n// Last Modified On: ."
9837 "\n// Update Count : 0"
9838 "\n// Status : Unknown, Use with caution!"
9841 (define-skeleton verilog-sk-module
9842 "Insert a module definition."
9844 > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
9846 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
9848 (define-skeleton verilog-sk-primitive
9849 "Insert a task definition."
9851 > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
9853 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
9855 (define-skeleton verilog-sk-task
9856 "Insert a task definition."
9858 > "task " (verilog-sk-prompt-name) & ?; \n
9862 > (- verilog-indent-level-behavioral) "end" \n
9863 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
9865 (define-skeleton verilog-sk-function
9866 "Insert a function definition."
9868 > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n
9872 > (- verilog-indent-level-behavioral) "end" \n
9873 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
9875 (define-skeleton verilog-sk-always
9876 "Insert always block. Uses the minibuffer to prompt
9877 for sensitivity list."
9879 > "always @ ( /*AUTOSENSE*/ ) begin\n"
9881 > (- verilog-indent-level-behavioral) "end" \n >
9884 (define-skeleton verilog-sk-initial
9885 "Insert an initial block."
9889 > (- verilog-indent-level-behavioral) "end" \n > )
9891 (define-skeleton verilog-sk-specify
9892 "Insert specify block. "
9896 > (- verilog-indent-level-behavioral) "endspecify" \n > )
9898 (define-skeleton verilog-sk-generate
9899 "Insert generate block. "
9903 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
9905 (define-skeleton verilog-sk-begin
9906 "Insert begin end block. Uses the minibuffer to prompt for name"
9908 > "begin" (verilog-sk-prompt-name) \n
9910 > (- verilog-indent-level-behavioral) "end"
9913 (define-skeleton verilog-sk-fork
9914 "Insert an fork join block."
9919 > (- verilog-indent-level-behavioral) "end" \n
9922 > (- verilog-indent-level-behavioral) "end" \n
9923 > (- verilog-indent-level-behavioral) "join" \n
9927 (define-skeleton verilog-sk-case
9928 "Build skeleton case statement, prompting for the selector expression,
9929 and the case items."
9930 "[selector expression]: "
9931 > "case (" str ") " \n
9932 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9933 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9935 (define-skeleton verilog-sk-casex
9936 "Build skeleton casex statement, prompting for the selector expression,
9937 and the case items."
9938 "[selector expression]: "
9939 > "casex (" str ") " \n
9940 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9941 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9943 (define-skeleton verilog-sk-casez
9944 "Build skeleton casez statement, prompting for the selector expression,
9945 and the case items."
9946 "[selector expression]: "
9947 > "casez (" str ") " \n
9948 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9949 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9951 (define-skeleton verilog-sk-if
9952 "Insert a skeleton if statement."
9953 > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n
9955 > (- verilog-indent-level-behavioral) "end " \n )
9957 (define-skeleton verilog-sk-else-if
9958 "Insert a skeleton else if statement."
9959 > (verilog-indent-line) "else if ("
9960 (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
9962 > "end" (progn (electric-verilog-terminate-line) nil))
9964 (define-skeleton verilog-sk-datadef
9965 "Common routine to get data definition"
9967 (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
9969 (define-skeleton verilog-sk-input
9970 "Insert an input definition."
9972 > "input [" (verilog-sk-datadef))
9974 (define-skeleton verilog-sk-output
9975 "Insert an output definition."
9977 > "output [" (verilog-sk-datadef))
9979 (define-skeleton verilog-sk-inout
9980 "Insert an inout definition."
9982 > "inout [" (verilog-sk-datadef))
9984 (defvar verilog-sk-signal nil)
9985 (define-skeleton verilog-sk-def-reg
9986 "Insert a reg definition."
9988 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
9990 (defun verilog-sk-define-signal ()
9991 "Insert a definition of signal under point at top of module."
9994 (sig-re "[a-zA-Z0-9_]*")
9995 (v1 (buffer-substring
9997 (skip-chars-backward sig-re)
10000 (skip-chars-forward sig-re)
10003 (if (not (member v1 verilog-keywords))
10005 (setq verilog-sk-signal v1)
10006 (verilog-beg-of-defun)
10007 (verilog-end-of-statement)
10008 (verilog-forward-syntactic-ws)
10009 (verilog-sk-def-reg)
10010 (message "signal at point is %s" v1))
10011 (message "object at point (%s) is a keyword" v1))
10016 (define-skeleton verilog-sk-wire
10017 "Insert a wire definition."
10019 > "wire [" (verilog-sk-datadef))
10021 (define-skeleton verilog-sk-reg
10022 "Insert a reg definition."
10024 > "reg [" (verilog-sk-datadef))
10026 (define-skeleton verilog-sk-assign
10027 "Insert a skeleton assign statement."
10029 > "assign " (verilog-sk-prompt-name) " = " _ ";" \n)
10031 (define-skeleton verilog-sk-while
10032 "Insert a skeleton while loop statement."
10034 > "while (" (verilog-sk-prompt-condition) ") begin" \n
10036 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10038 (define-skeleton verilog-sk-repeat
10039 "Insert a skeleton repeat loop statement."
10041 > "repeat (" (verilog-sk-prompt-condition) ") begin" \n
10043 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10045 (define-skeleton verilog-sk-for
10046 "Insert a skeleton while loop statement."
10049 (verilog-sk-prompt-init) "; "
10050 (verilog-sk-prompt-condition) "; "
10051 (verilog-sk-prompt-inc)
10054 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10056 (define-skeleton verilog-sk-comment
10057 "Inserts three comment lines, making a display comment."
10063 (define-skeleton verilog-sk-state-machine
10064 "Insert a state machine definition."
10065 "Name of state variable: "
10066 '(setq input "state")
10067 > "// State registers for " str | -23 \n
10068 '(setq verilog-sk-state str)
10069 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
10072 > "// State FF for " verilog-sk-state \n
10073 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
10074 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
10075 > verilog-sk-state " = next_" verilog-sk-state ?; \n
10076 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
10078 > "// Next State Logic for " verilog-sk-state \n
10079 > "always @ ( /*AUTOSENSE*/ ) begin\n"
10080 > "case (" (verilog-sk-prompt-state-selector) ") " \n
10081 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
10082 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
10083 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
10085 ;; Eliminate compile warning
10087 (if (not (boundp 'mode-popup-menu))
10088 (defvar mode-popup-menu nil "Compatibility with XEmacs.")))
10090 ;; ---- add menu 'Statements' in Verilog mode (MH)
10091 (defun verilog-add-statement-menu ()
10092 "Add the menu 'Statements' to the menu bar in Verilog mode."
10093 (if (featurep 'xemacs)
10095 (easy-menu-add verilog-stmt-menu)
10096 (easy-menu-add verilog-menu)
10097 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))))
10099 (add-hook 'verilog-mode-hook 'verilog-add-statement-menu)
10104 ;; Include file loading with mouse/return event
10106 ;; idea & first impl.: M. Rouat (eldo-mode.el)
10107 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
10109 (if (featurep 'xemacs)
10111 (require 'lucid)) ;; what else can we do ??
10113 (defconst verilog-include-file-regexp
10114 "^`include\\s-+\"\\([^\n\"]*\\)\""
10115 "Regexp that matches the include file.")
10117 (defvar verilog-mode-mouse-map
10118 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
10119 (set-keymap-parent map verilog-mode-map)
10120 ;; mouse button bindings
10121 (define-key map "\r" 'verilog-load-file-at-point)
10122 (if (featurep 'xemacs)
10123 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
10124 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
10125 (if (featurep 'xemacs)
10126 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
10127 (define-key map [S-mouse-2] 'mouse-yank-at-click))
10129 "Map containing mouse bindings for `verilog-mode'.")
10132 (defun verilog-colorize-include-files (beg end old-len)
10133 "This function colorizes included files when the mouse passes over them.
10134 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
10139 (setq end-point (verilog-get-end-of-line))
10141 (beginning-of-line) ; scan entire line !
10142 ;; delete overlays existing on this line
10143 (let ((overlays (overlays-in (point) end-point)))
10146 (overlay-get (car overlays) 'detachable)
10147 (overlay-get (car overlays) 'verilog-include-file))
10148 (delete-overlay (car overlays)))
10149 (setq overlays (cdr overlays)))) ; let
10150 ;; make new ones, could reuse deleted one ?
10151 (while (search-forward-regexp verilog-include-file-regexp end-point t)
10153 (goto-char (match-beginning 1))
10154 (setq ov (make-overlay (match-beginning 1) (match-end 1)))
10155 (overlay-put ov 'start-closed 't)
10156 (overlay-put ov 'end-closed 't)
10157 (overlay-put ov 'evaporate 't)
10158 (overlay-put ov 'verilog-include-file 't)
10159 (overlay-put ov 'mouse-face 'highlight)
10160 (overlay-put ov 'local-map verilog-mode-mouse-map)))))))
10163 (defun verilog-colorize-include-files-buffer ()
10164 "Colorize a include file."
10167 (let ((overlays (overlays-in (point-min) (point-max))))
10170 (overlay-get (car overlays) 'detachable)
10171 (overlay-get (car overlays) 'verilog-include-file))
10172 (delete-overlay (car overlays)))
10173 (setq overlays (cdr overlays)))) ; let
10175 (verilog-colorize-include-files (point-min) (point-max) nil))
10177 ;; ffap-at-mouse isn't useful for verilog mode. It uses library paths.
10178 ;; so define this function to do more or less the same as ffap-at-mouse
10179 ;; but first resolve filename...
10180 (defun verilog-load-file-at-mouse (event)
10181 "Load file under button 2 click's EVENT.
10182 Files are checked based on `verilog-library-directories'."
10184 (save-excursion ;; implement a verilog specific ffap-at-mouse
10185 (mouse-set-point event)
10186 (beginning-of-line)
10187 (if (looking-at verilog-include-file-regexp)
10188 (if (and (car (verilog-library-filenames
10189 (match-string 1) (buffer-file-name)))
10190 (file-readable-p (car (verilog-library-filenames
10191 (match-string 1) (buffer-file-name)))))
10192 (find-file (car (verilog-library-filenames
10193 (match-string 1) (buffer-file-name))))
10196 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
10197 (match-string 1))))
10200 ;; ffap isn't useable for verilog mode. It uses library paths.
10201 ;; so define this function to do more or less the same as ffap
10202 ;; but first resolve filename...
10203 (defun verilog-load-file-at-point ()
10204 "Load file under point.
10205 Files are checked based on `verilog-library-directories'."
10207 (save-excursion ;; implement a verilog specific ffap
10208 (beginning-of-line)
10209 (if (looking-at verilog-include-file-regexp)
10211 (car (verilog-library-filenames
10212 (match-string 1) (buffer-file-name)))
10213 (file-readable-p (car (verilog-library-filenames
10214 (match-string 1) (buffer-file-name)))))
10215 (find-file (car (verilog-library-filenames
10216 (match-string 1) (buffer-file-name))))))
10224 (defun verilog-faq ()
10225 "Tell the user their current version, and where to get the FAQ etc."
10227 (with-output-to-temp-buffer "*verilog-mode help*"
10228 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
10230 (princ "For new releases, see http://www.verilog.com\n")
10232 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
10234 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
10237 (defun verilog-submit-bug-report ()
10238 "Submit via mail a bug report on verilog-mode.el."
10240 (let ((reporter-prompt-for-summary-p t))
10241 (reporter-submit-bug-report
10243 (concat "verilog-mode v" verilog-mode-version)
10245 verilog-align-ifelse
10246 verilog-auto-endcomments
10248 verilog-auto-indent-on-newline
10249 verilog-auto-inst-vector
10250 verilog-auto-inst-template-numbers
10251 verilog-auto-lineup
10252 verilog-auto-newline
10253 verilog-auto-save-policy
10254 verilog-auto-sense-defines-constant
10255 verilog-auto-sense-include-inputs
10256 verilog-before-auto-hook
10257 verilog-case-indent
10258 verilog-cexp-indent
10261 verilog-highlight-translate-off
10262 verilog-indent-begin-after-if
10263 verilog-indent-declaration-macros
10264 verilog-indent-level
10265 verilog-indent-level-behavioral
10266 verilog-indent-level-declaration
10267 verilog-indent-level-directive
10268 verilog-indent-level-module
10269 verilog-indent-lists
10270 verilog-library-flags
10271 verilog-library-directories
10272 verilog-library-extensions
10273 verilog-library-files
10275 verilog-minimum-comment-distance
10278 verilog-tab-always-indent
10279 verilog-tab-to-comment
10284 I want to report a bug. I've read the `Bugs' section of `Info' on
10285 Emacs, so I know how to make a clear and unambiguous report. To get
10286 to that Info section, I typed
10288 M-x info RET m " invocation-name " RET m bugs RET
10290 Before I go further, I want to say that Verilog mode has changed my life.
10291 I save so much time, my files are colored nicely, my co workers respect
10292 my coding ability... until now. I'd really appreciate anything you
10293 could do to help me out with this minor deficiency in the product.
10295 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
10296 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
10297 You may also want to look at the Verilog-Mode FAQ, see
10298 http://www.veripool.com/verilog-mode-faq.html.
10300 To reproduce the bug, start a fresh Emacs via " invocation-name "
10301 -no-init-file -no-site-file'. In a new buffer, in verilog mode, type
10302 the code included below.
10304 Given those lines, I expected [[Fill in here]] to happen;
10305 but instead, [[Fill in here]] happens!.
10307 == The code: =="))))
10309 (provide 'verilog-mode)
10311 ;; Local Variables:
10312 ;; checkdoc-permit-comma-termination-flag:t
10313 ;; checkdoc-force-docstrings-flag:nil
10316 ;;; verilog-mode.el ends here