1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
4 ;; 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
6 ;; Author: Michael McNamara (mac@verilog.com)
7 ;; http://www.verilog.com
9 ;; AUTO features, signal, modsig; by: Wilson Snyder
10 ;; (wsnyder@wsnyder.org)
11 ;; http://www.veripool.com
12 ;; Keywords: languages
14 ;; This code supports Emacs 21.1 and later
15 ;; And XEmacs 21.1 and later
16 ;; Please do not make changes that break Emacs 21. Thanks!
20 ;; This file is part of GNU Emacs.
22 ;; GNU Emacs is free software; you can redistribute it and/or modify
23 ;; it under the terms of the GNU General Public License as published by
24 ;; the Free Software Foundation; either version 3, or (at your option)
27 ;; GNU Emacs is distributed in the hope that it will be useful,
28 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
29 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 ;; GNU General Public License for more details.
32 ;; You should have received a copy of the GNU General Public License
33 ;; along with GNU Emacs; see the file COPYING. If not, write to the
34 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
35 ;; Boston, MA 02110-1301, USA.
39 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs
44 ;; A major mode for editing Verilog HDL source code. When you have
45 ;; entered Verilog mode, you may get more info by pressing C-h m. You
46 ;; may also get online help describing various functions by: C-h f
47 ;; <Name of function you want described>
49 ;; KNOWN BUGS / BUG REPORTS
50 ;; =======================
52 ;; Verilog is a rapidly evolving language, and hence this mode is
53 ;; under continuous development. Hence this is beta code, and likely
54 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
55 ;; Please use verilog-submit-bug-report to submit a report; type C-c
56 ;; C-b to invoke this and as a result I will have a much easier time
57 ;; of reproducing the bug you find, and hence fixing it.
59 ;; INSTALLING THE MODE
60 ;; ===================
62 ;; An older version of this mode may be already installed as a part of
63 ;; your environment, and one method of updating would be to update
64 ;; your Emacs environment. Sometimes this is difficult for local
65 ;; political/control reasons, and hence you can always install a
66 ;; private copy (or even a shared copy) which overrides the system
69 ;; You can get step by step help in installing this file by going to
70 ;; <http://www.verilog.com/emacs_install.html>
72 ;; The short list of installation instructions are: To set up
73 ;; automatic Verilog mode, put this file in your load path, and put
74 ;; the following in code (please un comment it first!) in your
75 ;; .emacs, or in your site's site-load.el
77 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
78 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
79 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
81 ;; If you want to customize Verilog mode to fit your needs better,
82 ;; you may add these lines (the values of the variables presented
83 ;; here are the defaults). Note also that if you use an Emacs that
84 ;; supports custom, it's probably better to use the custom menu to
87 ;; Be sure to examine at the help for verilog-auto, and the other
88 ;; verilog-auto-* functions for some major coding time savers.
90 ; ;; User customization for Verilog mode
91 ; (setq verilog-indent-level 3
92 ; verilog-indent-level-module 3
93 ; verilog-indent-level-declaration 3
94 ; verilog-indent-level-behavioral 3
95 ; verilog-indent-level-directive 1
96 ; verilog-case-indent 2
97 ; verilog-auto-newline t
98 ; verilog-auto-indent-on-newline t
99 ; verilog-tab-always-indent t
100 ; verilog-auto-endcomments t
101 ; verilog-minimum-comment-distance 40
102 ; verilog-indent-begin-after-if t
103 ; verilog-auto-lineup '(all)
104 ; verilog-highlight-p1800-keywords nil
105 ; verilog-linter "my_lint_shell_command"
112 ;; See commit history at http://www.veripool.com/verilog-mode.html
113 ;; (This section is required to appease checkdoc.)
117 ;; This variable will always hold the version number of the mode
118 (defconst verilog-mode-version
"404"
119 "Version of this Verilog mode.")
120 (defconst verilog-mode-release-date
"2008-03-02-GNU"
121 "Release date of this Verilog mode.")
122 (defconst verilog-mode-release-emacs t
123 "If non-nil, this version of Verilog mode was released with Emacs itself.")
125 (defun verilog-version ()
126 "Inform caller of the version of this file."
128 (message "Using verilog-mode version %s" verilog-mode-version
))
130 ;; Insure we have certain packages, and deal with it if we don't
131 ;; Be sure to note which Emacs flavor and version added each feature.
133 ;; The below were disabled when GNU Emacs 22 was released;
134 ;; perhaps some still need to be there to support Emacs 21.
135 (when (featurep 'xemacs
)
140 (require 'regexp-opt
)
142 ;; Bug in 19.28 through 19.30 skeleton.el, not provided.
149 (defmacro when
(cond &rest body
)
150 (list 'if cond
(cons 'progn body
))))
153 (if (fboundp 'unless
)
155 (defmacro unless
(cond &rest body
)
156 (cons 'if
(cons cond
(cons nil body
)))))
159 (if (fboundp 'store-match-data
)
161 (defmacro store-match-data
(&rest args
) nil
))
164 (if (fboundp 'char-before
)
166 (defmacro char-before
(&rest body
)
167 (char-after (1- (point)))))
173 (if (fboundp 'match-string-no-properties
)
175 (defsubst match-string-no-properties
(num &optional string
)
176 "Return string of text matched by last search, without text properties.
177 NUM specifies which parenthesized expression in the last regexp.
178 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
179 Zero means the entire text matched by the whole regexp or whole string.
180 STRING should be given if the last search was by `string-match' on STRING."
181 (if (match-beginning num
)
185 (match-beginning num
) (match-end num
))))
186 (set-text-properties 0 (length result
) nil result
)
188 (buffer-substring-no-properties (match-beginning num
)
193 (if (and (featurep 'custom
) (fboundp 'custom-declare-variable
))
194 nil
;; We've got what we needed
195 ;; We have the old custom-library, hack around it!
196 (defmacro defgroup
(&rest args
) nil
)
197 (defmacro customize
(&rest args
)
199 "Sorry, Customize is not available with this version of Emacs"))
200 (defmacro defcustom
(var value doc
&rest args
)
201 `(defvar ,var
,value
,doc
))
203 (if (fboundp 'defface
)
205 (defmacro defface
(var values doc
&rest args
)
209 (if (and (featurep 'custom
) (fboundp 'customize-group
))
210 nil
;; We've got what we needed
211 ;; We have an intermediate custom-library, hack around it!
212 (defmacro customize-group
(var &rest args
)
216 ;; Provide a regular expression optimization routine, using regexp-opt
217 ;; if provided by the user's elisp libraries
219 ;; The below were disabled when GNU Emacs 22 was released;
220 ;; perhaps some still need to be there to support Emacs 21.
221 (if (featurep 'xemacs
)
222 (if (fboundp 'regexp-opt
)
223 ;; regexp-opt is defined, does it take 3 or 2 arguments?
224 (if (fboundp 'function-max-args
)
225 (let ((args (function-max-args `regexp-opt
)))
227 ((eq args
3) ;; It takes 3
228 (condition-case nil
; Hide this defun from emacses
229 ;with just a two input regexp
230 (defun verilog-regexp-opt (a b
)
231 "Deal with differing number of required arguments for `regexp-opt'.
232 Call 'regexp-opt' on A and B."
236 ((eq args
2) ;; It takes 2
237 (defun verilog-regexp-opt (a b
)
238 "Call 'regexp-opt' on A and B."
242 ;; We can't tell; assume it takes 2
243 (defun verilog-regexp-opt (a b
)
244 "Call 'regexp-opt' on A and B."
247 ;; There is no regexp-opt, provide our own
248 (defun verilog-regexp-opt (strings &optional paren shy
)
249 (let ((open (if paren
"\\(" "")) (close (if paren
"\\)" "")))
250 (concat open
(mapconcat 'regexp-quote strings
"\\|") close
)))
253 (defalias 'verilog-regexp-opt
'regexp-opt
)))
256 (defun verilog-regexp-words (a)
257 "Call 'regexp-opt' with word delimiters for the words A."
258 (concat "\\<" (verilog-regexp-opt a t
) "\\>")))
260 (defun verilog-easy-menu-filter (menu)
261 "Filter a easy-menu-define to support new features."
262 (cond ((not (featurep 'xemacs
))
263 menu
) ;; GNU Emacs - passthru
264 ;; Xemacs doesn't support :help. Strip it.
265 ;; Recursively filter the a submenu
267 (mapcar 'verilog-easy-menu-filter menu
))
268 ;; Look for [:help "blah"] and remove
270 (let ((i 0) (out []))
271 (while (< i
(length menu
))
272 (if (equal `:help
(aref menu i
))
274 (setq out
(vconcat out
(vector (aref menu i
)))
277 (t menu
))) ;; Default - ok
278 ;;(verilog-easy-menu-filter
279 ;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
280 ;; "----" ["MB" nil :help "Help MB"]))
282 (defun verilog-customize ()
283 "Customize variables and other settings used by Verilog-Mode."
285 (customize-group 'verilog-mode
))
287 (defun verilog-font-customize ()
288 "Customize fonts used by Verilog-Mode."
290 (if (fboundp 'customize-apropos
)
291 (customize-apropos "font-lock-*" 'faces
)))
293 (defun verilog-booleanp (value)
294 "Return t if VALUE is boolean.
295 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
296 This function may be removed when Emacs 21 is no longer supported."
297 (or (equal value t
) (equal value nil
)))
299 (defalias 'verilog-syntax-ppss
300 (if (fboundp 'syntax-ppss
) 'syntax-ppss
301 (lambda (&optional pos
) (parse-partial-sexp (point-min) (or pos
(point))))))
303 (defgroup verilog-mode nil
304 "Facilitates easy editing of Verilog source text."
308 ; (defgroup verilog-mode-fonts nil
309 ; "Facilitates easy customization fonts used in Verilog source text"
310 ; :link '(customize-apropos "font-lock-*" 'faces)
311 ; :group 'verilog-mode)
313 (defgroup verilog-mode-indent nil
314 "Customize indentation and highlighting of Verilog source text."
315 :group
'verilog-mode
)
317 (defgroup verilog-mode-actions nil
318 "Customize actions on Verilog source text."
319 :group
'verilog-mode
)
321 (defgroup verilog-mode-auto nil
322 "Customize AUTO actions when expanding Verilog source text."
323 :group
'verilog-mode
)
325 (defcustom verilog-linter
326 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
327 "*Unix program and arguments to call to run a lint checker on Verilog source.
328 Depending on the `verilog-set-compile-command', this may be invoked when
329 you type \\[compile]. When the compile completes, \\[next-error] will take
330 you to the next lint error."
332 :group
'verilog-mode-actions
)
333 ;; We don't mark it safe, as it's used as a shell command
335 (defcustom verilog-coverage
336 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
337 "*Program and arguments to use to annotate for coverage Verilog source.
338 Depending on the `verilog-set-compile-command', this may be invoked when
339 you type \\[compile]. When the compile completes, \\[next-error] will take
340 you to the next lint error."
342 :group
'verilog-mode-actions
)
343 ;; We don't mark it safe, as it's used as a shell command
345 (defcustom verilog-simulator
346 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
347 "*Program and arguments to use to interpret Verilog source.
348 Depending on the `verilog-set-compile-command', this may be invoked when
349 you type \\[compile]. When the compile completes, \\[next-error] will take
350 you to the next lint error."
352 :group
'verilog-mode-actions
)
353 ;; We don't mark it safe, as it's used as a shell command
355 (defcustom verilog-compiler
356 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
357 "*Program and arguments to use to compile Verilog source.
358 Depending on the `verilog-set-compile-command', this may be invoked when
359 you type \\[compile]. When the compile completes, \\[next-error] will take
360 you to the next lint error."
362 :group
'verilog-mode-actions
)
363 ;; We don't mark it safe, as it's used as a shell command
365 (defvar verilog-tool
'verilog-linter
366 "Which tool to use for building compiler-command.
367 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
368 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
369 menu. See `verilog-set-compile-command' for more information.")
371 (defcustom verilog-highlight-translate-off nil
372 "*Non-nil means background-highlight code excluded from translation.
373 That is, all code between \"// synopsys translate_off\" and
374 \"// synopsys translate_on\" is highlighted using a different background color
375 \(face `verilog-font-lock-translate-off-face').
377 Note: This will slow down on-the-fly fontification (and thus editing).
379 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
380 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
382 :group
'verilog-mode-indent
)
383 ;; Note we don't use :safe, as that would break on Emacsen before 22.0.
384 (put 'verilog-highlight-translate-off
'safe-local-variable
'verilog-booleanp
)
386 (defcustom verilog-indent-level
3
387 "*Indentation of Verilog statements with respect to containing block."
388 :group
'verilog-mode-indent
390 (put 'verilog-indent-level
'safe-local-variable
'integerp
)
392 (defcustom verilog-indent-level-module
3
393 "*Indentation of Module level Verilog statements (eg always, initial).
394 Set to 0 to get initial and always statements lined up on the left side of
396 :group
'verilog-mode-indent
398 (put 'verilog-indent-level-module
'safe-local-variable
'integerp
)
400 (defcustom verilog-indent-level-declaration
3
401 "*Indentation of declarations with respect to containing block.
402 Set to 0 to get them list right under containing block."
403 :group
'verilog-mode-indent
405 (put 'verilog-indent-level-declaration
'safe-local-variable
'integerp
)
407 (defcustom verilog-indent-declaration-macros nil
408 "*How to treat macro expansions in a declaration.
413 If non nil, treat as:
417 :group
'verilog-mode-indent
419 (put 'verilog-indent-declaration-macros
'safe-local-variable
'verilog-booleanp
)
421 (defcustom verilog-indent-lists t
422 "*How to treat indenting items in a list.
423 If t (the default), indent as:
424 always @( posedge a or
428 always @( posedge a or
430 :group
'verilog-mode-indent
432 (put 'verilog-indent-lists
'safe-local-variable
'verilog-booleanp
)
434 (defcustom verilog-indent-level-behavioral
3
435 "*Absolute indentation of first begin in a task or function block.
436 Set to 0 to get such code to start at the left side of the screen."
437 :group
'verilog-mode-indent
439 (put 'verilog-indent-level-behavioral
'safe-local-variable
'integerp
)
441 (defcustom verilog-indent-level-directive
1
442 "*Indentation to add to each level of `ifdef declarations.
443 Set to 0 to have all directives start at the left side of the screen."
444 :group
'verilog-mode-indent
446 (put 'verilog-indent-level-directive
'safe-local-variable
'integerp
)
448 (defcustom verilog-cexp-indent
2
449 "*Indentation of Verilog statements split across lines."
450 :group
'verilog-mode-indent
452 (put 'verilog-cexp-indent
'safe-local-variable
'integerp
)
454 (defcustom verilog-case-indent
2
455 "*Indentation for case statements."
456 :group
'verilog-mode-indent
458 (put 'verilog-case-indent
'safe-local-variable
'integerp
)
460 (defcustom verilog-auto-newline t
461 "*True means automatically newline after semicolons."
462 :group
'verilog-mode-indent
464 (put 'verilog-auto-newline
'safe-local-variable
'verilog-booleanp
)
466 (defcustom verilog-auto-indent-on-newline t
467 "*True means automatically indent line after newline."
468 :group
'verilog-mode-indent
470 (put 'verilog-auto-indent-on-newline
'safe-local-variable
'verilog-booleanp
)
472 (defcustom verilog-tab-always-indent t
473 "*True means TAB should always re-indent the current line.
474 A nil value means TAB will only reindent when at the beginning of the line."
475 :group
'verilog-mode-indent
477 (put 'verilog-tab-always-indent
'safe-local-variable
'verilog-booleanp
)
479 (defcustom verilog-tab-to-comment nil
480 "*True means TAB moves to the right hand column in preparation for a comment."
481 :group
'verilog-mode-actions
483 (put 'verilog-tab-to-comment
'safe-local-variable
'verilog-booleanp
)
485 (defcustom verilog-indent-begin-after-if t
486 "*If true, indent begin statements following if, else, while, for and repeat.
487 Otherwise, line them up."
488 :group
'verilog-mode-indent
490 (put 'verilog-indent-begin-after-if
'safe-local-variable
'verilog-booleanp
)
493 (defcustom verilog-align-ifelse nil
494 "*If true, align `else' under matching `if'.
495 Otherwise else is lined up with first character on line holding matching if."
496 :group
'verilog-mode-indent
498 (put 'verilog-align-ifelse
'safe-local-variable
'verilog-booleanp
)
500 (defcustom verilog-minimum-comment-distance
10
501 "*Minimum distance (in lines) between begin and end required before a comment.
502 Setting this variable to zero results in every end acquiring a comment; the
503 default avoids too many redundant comments in tight quarters."
504 :group
'verilog-mode-indent
506 (put 'verilog-minimum-comment-distance
'safe-local-variable
'integerp
)
508 (defcustom verilog-auto-lineup
'(declaration)
509 "*Algorithm for lining up statements on multiple lines.
511 If this list contains the symbol 'all', then all line ups described below
514 If this list contains the symbol 'declaration', then declarations are lined up
515 with any preceding declarations, taking into account widths and the like, so
516 for example the code:
523 If this list contains the symbol 'assignment', then assignments are lined up
524 with any preceding assignments, so for example the code
525 a_long_variable = b + c;
528 a_long_variable = b + c;
531 ;; The following is not implemented:
532 ;If this list contains the symbol 'case', then case items are lined up
533 ;with any preceding case items, so for example the code
535 ; a_long_state : a = 3;
540 ; a_long_state : a = 3;
545 :group
'verilog-mode-indent
547 (put 'verilog-auto-lineup
'safe-local-variable
'listp
)
549 (defcustom verilog-highlight-p1800-keywords nil
550 "*True means highlight words newly reserved by IEEE-1800.
551 These will appear in `verilog-font-lock-p1800-face' in order to gently
552 suggest changing where these words are used as variables to something else.
553 A nil value means highlight these words as appropriate for the SystemVerilog
554 IEEE-1800 standard. Note that changing this will require restarting Emacs
555 to see the effect as font color choices are cached by Emacs."
556 :group
'verilog-mode-indent
558 (put 'verilog-highlight-p1800-keywords
'safe-local-variable
'verilog-booleanp
)
560 (defcustom verilog-highlight-grouping-keywords nil
561 "*True means highlight grouping keywords 'begin' and 'end' more dramatically.
562 If false, these words are in the font-lock-type-face; if True then they are in
563 `verilog-font-lock-ams-face'. Some find that special highlighting on these
564 grouping constructs allow the structure of the code to be understood at a glance."
565 :group
'verilog-mode-indent
567 (put 'verilog-highlight-grouping-keywords
'safe-local-variable
'verilog-booleanp
)
569 (defcustom verilog-auto-endcomments t
570 "*True means insert a comment /* ... */ after 'end's.
571 The name of the function or case will be set between the braces."
572 :group
'verilog-mode-actions
574 (put 'verilog-auto-endcomments
'safe-local-variable
'verilog-booleanp
)
576 (defcustom verilog-auto-read-includes nil
577 "*True means to automatically read includes before AUTOs.
578 This will do a `verilog-read-defines' and `verilog-read-includes' before
579 each AUTO expansion. This makes it easier to embed defines and includes,
580 but can result in very slow reading times if there are many or large
582 :group
'verilog-mode-actions
584 (put 'verilog-auto-read-includes
'safe-local-variable
'verilog-booleanp
)
586 (defcustom verilog-auto-save-policy nil
587 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
588 A value of `force' will always do a \\[verilog-auto] automatically if
589 needed on every save. A value of `detect' will do \\[verilog-auto]
590 automatically when it thinks necessary. A value of `ask' will query the
591 user when it thinks updating is needed.
593 You should not rely on the 'ask or 'detect policies, they are safeguards
594 only. They do not detect when AUTOINSTs need to be updated because a
595 sub-module's port list has changed."
596 :group
'verilog-mode-actions
597 :type
'(choice (const nil
) (const ask
) (const detect
) (const force
)))
599 (defcustom verilog-auto-star-expand t
600 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
601 They will be expanded in the same way as if there was a AUTOINST in the
602 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
603 :group
'verilog-mode-actions
605 (put 'verilog-auto-star-expand
'safe-local-variable
'verilog-booleanp
)
607 (defcustom verilog-auto-star-save nil
608 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
609 A nil value indicates direct connections will be removed before saving.
610 Only meaningful to those created due to `verilog-auto-star-expand' being set.
612 Instead of setting this, you may want to use /*AUTOINST*/, which will
614 :group
'verilog-mode-actions
616 (put 'verilog-auto-star-save
'safe-local-variable
'verilog-booleanp
)
618 (defvar verilog-auto-update-tick nil
619 "Modification tick at which autos were last performed.")
621 (defvar verilog-auto-last-file-locals nil
622 "Text from file-local-variables during last evaluation.")
624 (defvar verilog-error-regexp-add-didit nil
)
625 (defvar verilog-error-regexp nil
)
626 (setq verilog-error-regexp-add-didit nil
630 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
631 ; Most SureFire tools
632 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
634 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
635 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
637 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
638 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
640 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
641 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
642 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
643 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
645 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
646 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
648 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
649 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
650 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
652 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
654 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
656 ; "*List of regexps for Verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
659 (defvar verilog-error-font-lock-keywords
661 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t
)
662 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t
)
664 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t
)
665 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t
)
668 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
669 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
671 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
672 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t
)
674 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t
)
675 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t
)
677 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t
)
678 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t
)
680 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
681 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t
)
683 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
684 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t
)
686 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t
)
687 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t
)
689 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
690 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t
)
692 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t
)
693 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t
)
695 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t
)
696 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t
)
698 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t
)
699 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t
)
701 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t
)
702 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t
)
704 "*Keywords to also highlight in Verilog *compilation* buffers.")
706 (defcustom verilog-library-flags
'("")
707 "*List of standard Verilog arguments to use for /*AUTOINST*/.
708 These arguments are used to find files for `verilog-auto', and match
709 the flags accepted by a standard Verilog-XL simulator.
711 -f filename Reads more `verilog-library-flags' from the filename.
712 +incdir+dir Adds the directory to `verilog-library-directories'.
713 -Idir Adds the directory to `verilog-library-directories'.
714 -y dir Adds the directory to `verilog-library-directories'.
715 +libext+.v Adds the extensions to `verilog-library-extensions'.
716 -v filename Adds the filename to `verilog-library-files'.
718 filename Adds the filename to `verilog-library-files'.
719 This is not recommended, -v is a better choice.
721 You might want these defined in each file; put at the *END* of your file
725 // verilog-library-flags:(\"-y dir -y otherdir\")
728 Verilog-mode attempts to detect changes to this local variable, but they
729 are only insured to be correct when the file is first visited. Thus if you
730 have problems, use \\[find-alternate-file] RET to have these take effect.
732 See also the variables mentioned above."
733 :group
'verilog-mode-auto
734 :type
'(repeat string
))
735 (put 'verilog-library-flags
'safe-local-variable
'listp
)
737 (defcustom verilog-library-directories
'(".")
738 "*List of directories when looking for files for /*AUTOINST*/.
739 The directory may be relative to the current file, or absolute.
740 Environment variables are also expanded in the directory names.
741 Having at least the current directory is a good idea.
743 You might want these defined in each file; put at the *END* of your file
747 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
750 Verilog-mode attempts to detect changes to this local variable, but they
751 are only insured to be correct when the file is first visited. Thus if you
752 have problems, use \\[find-alternate-file] RET to have these take effect.
754 See also `verilog-library-flags', `verilog-library-files'
755 and `verilog-library-extensions'."
756 :group
'verilog-mode-auto
757 :type
'(repeat file
))
758 (put 'verilog-library-directories
'safe-local-variable
'listp
)
760 (defcustom verilog-library-files
'()
761 "*List of files to search for modules.
762 AUTOINST will use this when it needs to resolve a module name.
763 This is a complete path, usually to a technology file with many standard
766 You might want these defined in each file; put at the *END* of your file
770 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
773 Verilog-mode attempts to detect changes to this local variable, but they
774 are only insured to be correct when the file is first visited. Thus if you
775 have problems, use \\[find-alternate-file] RET to have these take effect.
777 See also `verilog-library-flags', `verilog-library-directories'."
778 :group
'verilog-mode-auto
779 :type
'(repeat directory
))
780 (put 'verilog-library-files
'safe-local-variable
'listp
)
782 (defcustom verilog-library-extensions
'(".v")
783 "*List of extensions to use when looking for files for /*AUTOINST*/.
784 See also `verilog-library-flags', `verilog-library-directories'."
785 :type
'(repeat string
)
786 :group
'verilog-mode-auto
)
787 (put 'verilog-library-extensions
'safe-local-variable
'listp
)
789 (defcustom verilog-active-low-regexp nil
790 "*If set, treat signals matching this regexp as active low.
791 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
792 you will probably also need `verilog-auto-reset-widths' set."
793 :group
'verilog-mode-auto
795 (put 'verilog-active-low-regexp
'safe-local-variable
'stringp
)
797 (defcustom verilog-auto-sense-include-inputs nil
798 "*If true, AUTOSENSE should include all inputs.
799 If nil, only inputs that are NOT output signals in the same block are
801 :group
'verilog-mode-auto
803 (put 'verilog-auto-sense-include-inputs
'safe-local-variable
'verilog-booleanp
)
805 (defcustom verilog-auto-sense-defines-constant nil
806 "*If true, AUTOSENSE should assume all defines represent constants.
807 When true, the defines will not be included in sensitivity lists. To
808 maintain compatibility with other sites, this should be set at the bottom
809 of each Verilog file that requires it, rather than being set globally."
810 :group
'verilog-mode-auto
812 (put 'verilog-auto-sense-defines-constant
'safe-local-variable
'verilog-booleanp
)
814 (defcustom verilog-auto-reset-widths t
815 "*If true, AUTORESET should determine the width of signals.
816 This is then used to set the width of the zero (32'h0 for example). This
817 is required by some lint tools that aren't smart enough to ignore widths of
818 the constant zero. This may result in ugly code when parameters determine
819 the MSB or LSB of a signal inside an AUTORESET."
821 :group
'verilog-mode-auto
)
822 (put 'verilog-auto-reset-widths
'safe-local-variable
'verilog-booleanp
)
824 (defcustom verilog-assignment-delay
""
825 "*Text used for delays in delayed assignments. Add a trailing space if set."
826 :group
'verilog-mode-auto
828 (put 'verilog-assignment-delay
'safe-local-variable
'stringp
)
830 (defcustom verilog-auto-inst-vector t
831 "*If true, when creating default ports with AUTOINST, use bus subscripts.
832 If nil, skip the subscript when it matches the entire bus as declared in
833 the module (AUTOWIRE signals always are subscripted, you must manually
834 declare the wire to have the subscripts removed.) Setting this to nil may
835 speed up some simulators, but is less general and harder to read, so avoid."
836 :group
'verilog-mode-auto
838 (put 'verilog-auto-inst-vector
'safe-local-variable
'verilog-booleanp
)
840 (defcustom verilog-auto-inst-template-numbers nil
841 "*If true, when creating templated ports with AUTOINST, add a comment.
842 The comment will add the line number of the template that was used for that
843 port declaration. Setting this aids in debugging, but nil is suggested for
844 regular use to prevent large numbers of merge conflicts."
845 :group
'verilog-mode-auto
847 (put 'verilog-auto-inst-template-numbers
'safe-local-variable
'verilog-booleanp
)
849 (defvar verilog-auto-inst-column
40
850 "Column number for first part of auto-inst.")
852 (defcustom verilog-auto-input-ignore-regexp nil
853 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
854 See the \\[verilog-faq] for examples on using this."
855 :group
'verilog-mode-auto
857 (put 'verilog-auto-input-ignore-regexp
'safe-local-variable
'stringp
)
859 (defcustom verilog-auto-inout-ignore-regexp nil
860 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
861 See the \\[verilog-faq] for examples on using this."
862 :group
'verilog-mode-auto
864 (put 'verilog-auto-inout-ignore-regexp
'safe-local-variable
'stringp
)
866 (defcustom verilog-auto-output-ignore-regexp nil
867 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
868 See the \\[verilog-faq] for examples on using this."
869 :group
'verilog-mode-auto
871 (put 'verilog-auto-output-ignore-regexp
'safe-local-variable
'stringp
)
873 (defcustom verilog-auto-unused-ignore-regexp nil
874 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
875 See the \\[verilog-faq] for examples on using this."
876 :group
'verilog-mode-auto
878 (put 'verilog-auto-unused-ignore-regexp
'safe-local-variable
'stringp
)
880 (defcustom verilog-typedef-regexp nil
881 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
882 For example, \"_t$\" matches typedefs named with _t, as in the C language."
883 :group
'verilog-mode-auto
885 (put 'verilog-typedef-regexp
'safe-local-variable
'stringp
)
887 (defcustom verilog-mode-hook
'verilog-set-compile-command
888 "*Hook run after Verilog mode is loaded."
890 :group
'verilog-mode
)
892 (defcustom verilog-auto-hook nil
893 "*Hook run after `verilog-mode' updates AUTOs."
894 :group
'verilog-mode-auto
897 (defcustom verilog-before-auto-hook nil
898 "*Hook run before `verilog-mode' updates AUTOs."
899 :group
'verilog-mode-auto
902 (defcustom verilog-delete-auto-hook nil
903 "*Hook run after `verilog-mode' deletes AUTOs."
904 :group
'verilog-mode-auto
907 (defcustom verilog-before-delete-auto-hook nil
908 "*Hook run before `verilog-mode' deletes AUTOs."
909 :group
'verilog-mode-auto
912 (defcustom verilog-getopt-flags-hook nil
913 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
914 :group
'verilog-mode-auto
917 (defcustom verilog-before-getopt-flags-hook nil
918 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
919 :group
'verilog-mode-auto
922 (defvar verilog-imenu-generic-expression
923 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
924 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
925 "Imenu expression for Verilog mode. See `imenu-generic-expression'.")
928 ;; provide a verilog-header function.
929 ;; Customization variables:
931 (defvar verilog-date-scientific-format nil
932 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
933 If nil, in European format (e.g. 17.09.1997). The brain-dead American
934 format (e.g. 09/17/1997) is not supported.")
936 (defvar verilog-company nil
937 "*Default name of Company for Verilog header.
938 If set will become buffer local.")
939 (make-variable-buffer-local 'verilog-company
)
941 (defvar verilog-project nil
942 "*Default name of Project for Verilog header.
943 If set will become buffer local.")
944 (make-variable-buffer-local 'verilog-project
)
946 (defvar verilog-mode-map
947 (let ((map (make-sparse-keymap)))
948 (define-key map
";" 'electric-verilog-semi
)
949 (define-key map
[(control 59)] 'electric-verilog-semi-with-comment
)
950 (define-key map
":" 'electric-verilog-colon
)
951 ;;(define-key map "=" 'electric-verilog-equal)
952 (define-key map
"\`" 'electric-verilog-tick
)
953 (define-key map
"\t" 'electric-verilog-tab
)
954 (define-key map
"\r" 'electric-verilog-terminate-line
)
955 ;; backspace/delete key bindings
956 (define-key map
[backspace] 'backward-delete-char-untabify)
957 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
958 (define-key map [delete] 'delete-char)
959 (define-key map [(meta delete)] 'kill-word))
960 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
961 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
962 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
963 (define-key map "\M-\t" 'verilog-complete-word)
964 (define-key map "\M-?" 'verilog-show-completions)
965 (define-key map "\C-c\`" 'verilog-lint-off)
966 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
967 (define-key map "\C-c\C-r" 'verilog-label-be)
968 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
969 (define-key map "\C-c=" 'verilog-pretty-expr)
970 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
971 (define-key map "\M-*" 'verilog-star-comment)
972 (define-key map "\C-c\C-c" 'verilog-comment-region)
973 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
974 (when (featurep 'xemacs)
975 (define-key map [(meta control h)] 'verilog-mark-defun)
976 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
977 (define-key map "\M-\C-e" 'verilog-end-of-defun))
978 (define-key map "\C-c\C-d" 'verilog-goto-defun)
979 (define-key map "\C-c\C-k" 'verilog-delete-auto)
980 (define-key map "\C-c\C-a" 'verilog-auto)
981 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
982 (define-key map "\C-c\C-z" 'verilog-inject-auto)
983 (define-key map "\C-c\C-e" 'verilog-expand-vector)
984 (define-key map "\C-c\C-h" 'verilog-header)
986 "Keymap used in Verilog mode.")
990 verilog-menu verilog-mode-map "Menu for Verilog mode"
991 (verilog-easy-menu-filter
993 ("Choose Compilation Action"
996 (setq verilog-tool nil)
997 (verilog-set-compile-command))
999 :selected (equal verilog-tool nil)
1000 :help "When invoking compilation, use compile-command"]
1003 (setq verilog-tool 'verilog-linter)
1004 (verilog-set-compile-command))
1006 :selected (equal verilog-tool `verilog-linter)
1007 :help "When invoking compilation, use lint checker"]
1010 (setq verilog-tool 'verilog-coverage)
1011 (verilog-set-compile-command))
1013 :selected (equal verilog-tool `verilog-coverage)
1014 :help "When invoking compilation, annotate for coverage"]
1017 (setq verilog-tool 'verilog-simulator)
1018 (verilog-set-compile-command))
1020 :selected (equal verilog-tool `verilog-simulator)
1021 :help "When invoking compilation, interpret Verilog source"]
1024 (setq verilog-tool 'verilog-compiler)
1025 (verilog-set-compile-command))
1027 :selected (equal verilog-tool `verilog-compiler)
1028 :help "When invoking compilation, compile Verilog source"]
1031 ["Beginning of function" verilog-beg-of-defun
1033 :help "Move backward to the beginning of the current function or procedure"]
1034 ["End of function" verilog-end-of-defun
1036 :help "Move forward to the end of the current function or procedure"]
1037 ["Mark function" verilog-mark-defun
1039 :help "Mark the current Verilog function or procedure"]
1040 ["Goto function/module" verilog-goto-defun
1041 :help "Move to specified Verilog module/task/function"]
1042 ["Move to beginning of block" electric-verilog-backward-sexp
1043 :help "Move backward over one balanced expression"]
1044 ["Move to end of block" electric-verilog-forward-sexp
1045 :help "Move forward over one balanced expression"]
1048 ["Comment Region" verilog-comment-region
1049 :help "Put marked area into a comment"]
1050 ["UnComment Region" verilog-uncomment-region
1051 :help "Uncomment an area commented with Comment Region"]
1052 ["Multi-line comment insert" verilog-star-comment
1053 :help "Insert Verilog /* */ comment at point"]
1054 ["Lint error to comment" verilog-lint-off
1055 :help "Convert a Verilog linter warning line into a disable statement"]
1059 :help "Perform compilation-action (above) on the current buffer"]
1060 ["AUTO, Save, Compile" verilog-auto-save-compile
1061 :help "Recompute AUTOs, save buffer, and compile"]
1062 ["Next Compile Error" next-error
1063 :help "Visit next compilation error message and corresponding source code"]
1064 ["Ignore Lint Warning at point" verilog-lint-off
1065 :help "Convert a Verilog linter warning line into a disable statement"]
1067 ["Line up declarations around point" verilog-pretty-declarations
1068 :help "Line up declarations around point"]
1069 ["Line up equations around point" verilog-pretty-expr
1070 :help "Line up expressions around point"]
1071 ["Redo/insert comments on every end" verilog-label-be
1072 :help "Label matching begin ... end statements"]
1073 ["Expand [x:y] vector line" verilog-expand-vector
1074 :help "Take a signal vector on the current line and expand it to multiple lines"]
1075 ["Insert begin-end block" verilog-insert-block
1076 :help "Insert begin ... end"]
1077 ["Complete word" verilog-complete-word
1078 :help "Complete word at point"]
1080 ["Recompute AUTOs" verilog-auto
1081 :help "Expand AUTO meta-comment statements"]
1082 ["Kill AUTOs" verilog-delete-auto
1083 :help "Remove AUTO expansions"]
1084 ["Inject AUTOs" verilog-inject-auto
1085 :help "Inject AUTOs into legacy non-AUTO buffer"]
1087 ["AUTO General" (describe-function 'verilog-auto)
1088 :help "Help introduction on AUTOs"]
1089 ["AUTO Library Flags" (describe-variable 'verilog-library-flags)
1090 :help "Help on verilog-library-flags"]
1091 ["AUTO Library Path" (describe-variable 'verilog-library-directories)
1092 :help "Help on verilog-library-directories"]
1093 ["AUTO Library Files" (describe-variable 'verilog-library-files)
1094 :help "Help on verilog-library-files"]
1095 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
1096 :help "Help on verilog-library-extensions"]
1097 ["AUTO `define Reading" (describe-function 'verilog-read-defines)
1098 :help "Help on reading `defines"]
1099 ["AUTO `include Reading" (describe-function 'verilog-read-includes)
1100 :help "Help on parsing `includes"]
1101 ["AUTOARG" (describe-function 'verilog-auto-arg)
1102 :help "Help on AUTOARG - declaring module port list"]
1103 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
1104 :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
1105 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
1106 :help "Help on AUTOINOUTMODULE - copying i/o from another file"]
1107 ["AUTOINOUT" (describe-function 'verilog-auto-inout)
1108 :help "Help on AUTOINOUT - adding inouts from cells"]
1109 ["AUTOINPUT" (describe-function 'verilog-auto-input)
1110 :help "Help on AUTOINPUT - adding inputs from cells"]
1111 ["AUTOINST" (describe-function 'verilog-auto-inst)
1112 :help "Help on AUTOINST - adding pins for cells"]
1113 ["AUTOINST (.*)" (describe-function 'verilog-auto-star)
1114 :help "Help on expanding Verilog-2001 .* pins"]
1115 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
1116 :help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
1117 ["AUTOOUTPUT" (describe-function 'verilog-auto-output)
1118 :help "Help on AUTOOUTPUT - adding outputs from cells"]
1119 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
1120 :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
1121 ["AUTOREG" (describe-function 'verilog-auto-reg)
1122 :help "Help on AUTOREG - declaring registers for non-wires"]
1123 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
1124 :help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
1125 ["AUTORESET" (describe-function 'verilog-auto-reset)
1126 :help "Help on AUTORESET - resetting always blocks"]
1127 ["AUTOSENSE" (describe-function 'verilog-auto-sense)
1128 :help "Help on AUTOSENSE - sensitivity lists for always blocks"]
1129 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
1130 :help "Help on AUTOTIEOFF - tieing off unused outputs"]
1131 ["AUTOUNUSED" (describe-function 'verilog-auto-unused)
1132 :help "Help on AUTOUNUSED - terminating unused inputs"]
1133 ["AUTOWIRE" (describe-function 'verilog-auto-wire)
1134 :help "Help on AUTOWIRE - declaring wires for cells"]
1137 ["Submit bug report" verilog-submit-bug-report
1138 :help "Submit via mail a bug report on verilog-mode.el"]
1139 ["Version and FAQ" verilog-faq
1140 :help "Show the current version, and where to get the FAQ etc"]
1141 ["Customize Verilog Mode..." verilog-customize
1142 :help "Customize variables and other settings used by Verilog-Mode"]
1143 ["Customize Verilog Fonts & Colors" verilog-font-customize
1144 :help "Customize fonts used by Verilog-Mode."])))
1147 verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
1148 (verilog-easy-menu-filter
1150 ["Header" verilog-sk-header
1151 :help "Insert a header block at the top of file"]
1152 ["Comment" verilog-sk-comment
1153 :help "Insert a comment block"]
1155 ["Module" verilog-sk-module
1156 :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
1157 ["Primitive" verilog-sk-primitive
1158 :help "Insert a primitive .. (.. );.. endprimitive block"]
1160 ["Input" verilog-sk-input
1161 :help "Insert an input declaration"]
1162 ["Output" verilog-sk-output
1163 :help "Insert an output declaration"]
1164 ["Inout" verilog-sk-inout
1165 :help "Insert an inout declaration"]
1166 ["Wire" verilog-sk-wire
1167 :help "Insert a wire declaration"]
1168 ["Reg" verilog-sk-reg
1169 :help "Insert a register declaration"]
1170 ["Define thing under point as a register" verilog-sk-define-signal
1171 :help "Define signal under point as a register at the top of the module"]
1173 ["Initial" verilog-sk-initial
1174 :help "Insert an initial begin .. end block"]
1175 ["Always" verilog-sk-always
1176 :help "Insert an always @(AS) begin .. end block"]
1177 ["Function" verilog-sk-function
1178 :help "Insert a function .. begin .. end endfunction block"]
1179 ["Task" verilog-sk-task
1180 :help "Insert a task .. begin .. end endtask block"]
1181 ["Specify" verilog-sk-specify
1182 :help "Insert a specify .. endspecify block"]
1183 ["Generate" verilog-sk-generate
1184 :help "Insert a generate .. endgenerate block"]
1186 ["Begin" verilog-sk-begin
1187 :help "Insert a begin .. end block"]
1189 :help "Insert an if (..) begin .. end block"]
1190 ["(if) else" verilog-sk-else-if
1191 :help "Insert an else if (..) begin .. end block"]
1192 ["For" verilog-sk-for
1193 :help "Insert a for (...) begin .. end block"]
1194 ["While" verilog-sk-while
1195 :help "Insert a while (...) begin .. end block"]
1196 ["Fork" verilog-sk-fork
1197 :help "Insert a fork begin .. end .. join block"]
1198 ["Repeat" verilog-sk-repeat
1199 :help "Insert a repeat (..) begin .. end block"]
1200 ["Case" verilog-sk-case
1201 :help "Insert a case block, prompting for details"]
1202 ["Casex" verilog-sk-casex
1203 :help "Insert a casex (...) item: begin.. end endcase block"]
1204 ["Casez" verilog-sk-casez
1205 :help "Insert a casez (...) item: begin.. end endcase block"])))
1207 (defvar verilog-mode-abbrev-table nil
1208 "Abbrev table in use in Verilog-mode buffers.")
1210 (define-abbrev-table 'verilog-mode-abbrev-table ())
1216 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
1217 "Replace occurrences of FROM-STRING with TO-STRING.
1218 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
1219 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
1220 will break, as the o's continuously replace. xa -> x works ok though."
1221 ;; Hopefully soon to a emacs built-in
1223 (while (string-match from-string string start)
1224 (setq string (replace-match to-string fixedcase literal string)
1225 start (min (length string) (match-end 0))))
1228 (defsubst verilog-string-remove-spaces (string)
1229 "Remove spaces surrounding STRING."
1231 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
1232 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
1235 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
1236 ; checkdoc-params: (REGEXP BOUND NOERROR)
1237 "Like `re-search-forward', but skips over match in comments or strings."
1238 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
1240 (re-search-forward REGEXP BOUND NOERROR)
1241 (and (verilog-skip-forward-comment-or-string)
1243 (store-match-data '(nil nil))
1249 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
1250 ; checkdoc-params: (REGEXP BOUND NOERROR)
1251 "Like `re-search-backward', but skips over match in comments or strings."
1252 (store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
1254 (re-search-backward REGEXP BOUND NOERROR)
1255 (and (verilog-skip-backward-comment-or-string)
1257 (store-match-data '(nil nil))
1263 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
1264 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
1265 but trashes match data and is faster for REGEXP that doesn't match often.
1266 This may at some point use text properties to ignore comments,
1267 so there may be a large up front penalty for the first search."
1269 (while (and (not pt)
1270 (re-search-forward regexp bound noerror))
1271 (if (not (verilog-inside-comment-p))
1272 (setq pt (match-end 0))))
1275 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
1276 ; checkdoc-params: (REGEXP BOUND NOERROR)
1277 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
1278 but trashes match data and is faster for REGEXP that doesn't match often.
1279 This may at some point use text properties to ignore comments,
1280 so there may be a large up front penalty for the first search."
1282 (while (and (not pt)
1283 (re-search-backward regexp bound noerror))
1284 (if (not (verilog-inside-comment-p))
1285 (setq pt (match-end 0))))
1288 (defsubst verilog-get-beg-of-line (&optional arg)
1290 (beginning-of-line arg)
1293 (defsubst verilog-get-end-of-line (&optional arg)
1298 (defsubst verilog-within-string ()
1300 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
1302 (defvar compile-command)
1304 ;; compilation program
1305 (defun verilog-set-compile-command ()
1306 "Function to compute shell command to compile Verilog.
1308 This reads `verilog-tool' and sets `compile-command'. This specifies the
1309 program that executes when you type \\[compile] or
1310 \\[verilog-auto-save-compile].
1312 By default `verilog-tool' uses a Makefile if one exists in the current
1313 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
1314 `verilog-simulator', or `verilog-compiler' variables, as selected with the
1315 Verilog -> \"Choose Compilation Action\" menu.
1317 You should set `verilog-tool' or the other variables to the path and
1318 arguments for your Verilog simulator. For example:
1321 \"(cd /tmp; surecov %s)\".
1323 In the former case, the path to the current buffer is concat'ed to the
1324 value of `verilog-tool'; in the later, the path to the current buffer is
1325 substituted for the %s.
1327 Where __FILE__ appears in the string, the `buffer-file-name' of the
1328 current buffer, without the directory portion, will be substituted."
1331 ((or (file-exists-p "makefile") ;If there is a makefile, use it
1332 (file-exists-p "Makefile"))
1333 (make-local-variable 'compile-command)
1334 (setq compile-command "make "))
1336 (make-local-variable 'compile-command)
1337 (setq compile-command
1339 (if (string-match "%s" (eval verilog-tool))
1340 (format (eval verilog-tool) (or buffer-file-name ""))
1341 (concat (eval verilog-tool) " " (or buffer-file-name "")))
1343 (verilog-modify-compile-command))
1345 (defun verilog-modify-compile-command ()
1346 "Replace meta-information in `compile-command'.
1347 Where __FILE__ appears in the string, the current buffer's file-name,
1348 without the directory portion, will be substituted."
1350 (stringp compile-command)
1351 (string-match "\\b__FILE__\\b" compile-command))
1352 (make-local-variable 'compile-command)
1353 (setq compile-command
1354 (verilog-string-replace-matches
1355 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
1356 t t compile-command))))
1358 ;; Following code only gets called from compilation-mode-hook.
1359 (defvar compilation-error-regexp-alist)
1361 (defun verilog-error-regexp-add ()
1362 "Add the messages to the `compilation-error-regexp-alist'.
1363 Called by `compilation-mode-hook'. This allows \\[next-error] to
1365 (if (not verilog-error-regexp-add-didit)
1367 (setq verilog-error-regexp-add-didit t)
1368 (setq-default compilation-error-regexp-alist
1369 (append verilog-error-regexp
1370 (default-value 'compilation-error-regexp-alist)))
1371 ;; Could be buffer local at this point; maybe also in let; change all three
1372 (setq compilation-error-regexp-alist
1373 (default-value 'compilation-error-regexp-alist))
1374 (set (make-local-variable 'compilation-error-regexp-alist)
1375 (default-value 'compilation-error-regexp-alist)))))
1377 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
1379 (defconst verilog-directive-re
1380 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
1381 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1382 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1383 ;; "`time_scale" "`undef" "`while"
1384 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
1386 (defconst verilog-directive-begin
1387 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
1389 (defconst verilog-directive-middle
1390 "\\<`\\(else\\|default\\|case\\)\\>")
1392 (defconst verilog-directive-end
1393 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
1395 (defconst verilog-directive-re-1
1396 (concat "[ \t]*" verilog-directive-re))
1399 ;; Regular expressions used to calculate indent, etc.
1401 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
1402 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
1410 (defconst verilog-no-indent-begin-re
1411 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
1413 (defconst verilog-ends-re
1414 ;; Parenthesis indicate type of keyword found
1416 "\\(\\<else\\>\\)\\|" ; 1
1417 "\\(\\<if\\>\\)\\|" ; 2
1418 "\\(\\<end\\>\\)\\|" ; 3
1419 "\\(\\<endcase\\>\\)\\|" ; 4
1420 "\\(\\<endfunction\\>\\)\\|" ; 5
1421 "\\(\\<endtask\\>\\)\\|" ; 6
1422 "\\(\\<endspecify\\>\\)\\|" ; 7
1423 "\\(\\<endtable\\>\\)\\|" ; 8
1424 "\\(\\<endgenerate\\>\\)\\|" ; 9
1425 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
1426 "\\(\\<endclass\\>\\)\\|" ; 11
1427 "\\(\\<endgroup\\>\\)" ; 12
1430 (defconst verilog-auto-end-comment-lines-re
1431 ;; Matches to names in this list cause auto-end-commentation
1433 verilog-directive-re "\\)\\|\\("
1435 (verilog-regexp-words
1463 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
1464 ;;; verilog-end-block-ordered-re matches exactly the same strings.
1465 (defconst verilog-end-block-ordered-re
1466 ;; Parenthesis indicate type of keyword found
1467 (concat "\\(\\<endcase\\>\\)\\|" ; 1
1468 "\\(\\<end\\>\\)\\|" ; 2
1469 "\\(\\<end" ; 3, but not used
1470 "\\(" ; 4, but not used
1471 "\\(function\\)\\|" ; 5
1473 "\\(module\\)\\|" ; 7
1474 "\\(primitive\\)\\|" ; 8
1475 "\\(interface\\)\\|" ; 9
1476 "\\(package\\)\\|" ; 10
1477 "\\(class\\)\\|" ; 11
1478 "\\(group\\)\\|" ; 12
1479 "\\(program\\)\\|" ; 13
1480 "\\(sequence\\)\\|" ; 14
1481 "\\(clocking\\)\\|" ; 15
1483 (defconst verilog-end-block-re
1485 (verilog-regexp-words
1487 `("end" ;; closes begin
1488 "endcase" ;; closes any of case, casex casez or randcase
1489 "join" "join_any" "join_none" ;; closes fork
1506 (defconst verilog-endcomment-reason-re
1507 ;; Parenthesis indicate type of keyword found
1509 "\\(\\<fork\\>\\)\\|"
1510 "\\(\\<begin\\>\\)\\|"
1512 "\\(\\<clocking\\>\\)\\|"
1513 "\\(\\<else\\>\\)\\|"
1514 "\\(\\<end\\>.*\\<else\\>\\)\\|"
1515 "\\(\\<task\\>\\)\\|"
1516 "\\(\\<function\\>\\)\\|"
1517 "\\(\\<initial\\>\\)\\|"
1518 "\\(\\<interface\\>\\)\\|"
1519 "\\(\\<package\\>\\)\\|"
1520 "\\(\\<final\\>\\)\\|"
1521 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
1522 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
1523 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
1524 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
1526 "\\(\\<while\\>\\)\\|"
1527 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
1528 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
1531 (defconst verilog-named-block-re "begin[ \t]*:")
1533 ;; These words begin a block which can occur inside a module which should be indented,
1534 ;; and closed with the respective word from the end-block list
1536 (defconst verilog-beg-block-re
1538 (verilog-regexp-words
1540 "case" "casex" "casez" "randcase"
1550 ;; These are the same words, in a specific order in the regular
1551 ;; expression so that matching will work nicely for
1552 ;; verilog-forward-sexp and verilog-calc-indent
1554 (defconst verilog-beg-block-re-ordered
1557 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2,3
1558 "\\|\\(\\(disable\\s-+\\)?fork\\)" ;4
1561 "\\|\\(specify\\)" ;7
1562 "\\|\\(function\\)" ;8
1564 "\\|\\(generate\\)" ;10
1565 "\\|\\(covergroup\\)" ;11
1566 "\\|\\(property\\)" ;12
1567 "\\|\\(\\(rand\\)?sequence\\)" ;13
1568 "\\|\\(clocking\\)" ;14
1571 (defconst verilog-end-block-ordered-rry
1572 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1573 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
1574 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
1575 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
1576 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
1577 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
1578 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
1579 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
1580 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
1581 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
1582 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
1583 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
1584 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
1587 (defconst verilog-nameable-item-re
1589 (verilog-regexp-words
1592 "join" "join_any" "join_none"
1609 (defconst verilog-declaration-opener
1611 (verilog-regexp-words
1612 `("module" "begin" "task" "function"))))
1614 (defconst verilog-declaration-prefix-re
1616 (verilog-regexp-words
1619 "inout" "input" "output" "ref"
1621 "const" "static" "protected" "local"
1623 "localparam" "parameter" "var"
1627 (defconst verilog-declaration-core-re
1629 (verilog-regexp-words
1631 ;; port direction (by themselves)
1632 "inout" "input" "output"
1633 ;; integer_atom_type
1634 "byte" "shortint" "int" "longint" "integer" "time"
1635 ;; integer_vector_type
1638 "shortreal" "real" "realtime"
1640 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
1642 "string" "event" "chandle" "virtual" "enum" "genvar"
1645 "mailbox" "semaphore"
1647 (defconst verilog-declaration-re
1648 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
1649 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
1650 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
1651 (defconst verilog-optional-signed-range-re
1653 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
1654 (defconst verilog-macroexp-re "`\\sw+")
1656 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
1657 (defconst verilog-declaration-re-2-no-macro
1658 (concat "\\s-*" verilog-declaration-re
1659 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1661 (defconst verilog-declaration-re-2-macro
1662 (concat "\\s-*" verilog-declaration-re
1663 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
1664 "\\|\\(" verilog-macroexp-re "\\)"
1666 (defconst verilog-declaration-re-1-macro
1667 (concat "^" verilog-declaration-re-2-macro))
1669 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
1671 (defconst verilog-defun-re
1672 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
1673 (defconst verilog-end-defun-re
1674 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
1675 (defconst verilog-zero-indent-re
1676 (concat verilog-defun-re "\\|" verilog-end-defun-re))
1678 (defconst verilog-behavioral-block-beg-re
1679 (eval-when-compile (verilog-regexp-words `("initial" "final" "always" "always_comb" "always_latch" "always_ff"
1680 "function" "task"))))
1682 (defconst verilog-indent-re
1684 (verilog-regexp-words
1687 "always" "always_latch" "always_ff" "always_comb"
1689 ; "unique" "priority"
1690 "case" "casex" "casez" "randcase" "endcase"
1692 "clocking" "endclocking"
1693 "config" "endconfig"
1694 "covergroup" "endgroup"
1695 "fork" "join" "join_any" "join_none"
1696 "function" "endfunction"
1698 "generate" "endgenerate"
1700 "interface" "endinterface"
1701 "module" "macromodule" "endmodule"
1702 "package" "endpackage"
1703 "primitive" "endprimative"
1704 "program" "endprogram"
1705 "property" "endproperty"
1706 "sequence" "randsequence" "endsequence"
1707 "specify" "endspecify"
1713 "`if" "`ifdef" "`ifndef" "`else" "`endif"
1714 "`while" "`endwhile"
1719 "`protect" "`endprotect"
1720 "`switch" "`endswitch"
1725 (defconst verilog-defun-level-re
1727 (verilog-regexp-words
1729 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
1730 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
1733 (defconst verilog-defun-level-not-generate-re
1735 (verilog-regexp-words
1737 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
1739 (defconst verilog-cpp-level-re
1741 (verilog-regexp-words
1743 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
1745 (defconst verilog-disable-fork-re "disable\\s-+fork")
1746 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
1747 (defconst verilog-extended-complete-re
1748 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
1749 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
1750 "\\|" verilog-extended-case-re ))
1751 (defconst verilog-basic-complete-re
1753 (verilog-regexp-words
1755 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
1756 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
1757 "if" "for" "forever" "foreach" "else" "parameter" "do"
1759 (defconst verilog-complete-reg
1761 verilog-extended-complete-re
1763 verilog-basic-complete-re))
1765 (defconst verilog-end-statement-re
1766 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
1767 verilog-end-block-re "\\)"))
1769 (defconst verilog-endcase-re
1770 (concat verilog-case-re "\\|"
1775 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
1776 "String used to mark beginning of excluded text.")
1777 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
1778 "String used to mark end of excluded text.")
1779 (defconst verilog-preprocessor-re
1781 (verilog-regexp-words
1783 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
1786 (defconst verilog-keywords
1787 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
1788 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
1789 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
1790 "`time_scale" "`undef" "`while"
1792 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
1793 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
1794 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
1795 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
1796 "config" "const" "constraint" "context" "continue" "cover"
1797 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
1798 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
1799 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
1800 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
1801 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
1802 "endtask" "enum" "event" "expect" "export" "extends" "extern"
1803 "final" "first_match" "for" "force" "foreach" "forever" "fork"
1804 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
1805 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
1806 "include" "initial" "inout" "input" "inside" "instance" "int"
1807 "integer" "interface" "intersect" "join" "join_any" "join_none"
1808 "large" "liblist" "library" "local" "localparam" "logic"
1809 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
1810 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
1811 "notif0" "notif1" "null" "or" "output" "package" "packed"
1812 "parameter" "pmos" "posedge" "primitive" "priority" "program"
1813 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
1814 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1815 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
1816 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
1817 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
1818 "showcancelled" "signed" "small" "solve" "specify" "specparam"
1819 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
1820 "supply1" "table" "tagged" "task" "this" "throughout" "time"
1821 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
1822 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
1823 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
1824 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
1825 "wire" "with" "within" "wor" "xnor" "xor"
1827 "List of Verilog keywords.")
1829 (defconst verilog-comment-start-regexp "//\\|/\\*"
1830 "Dual comment value for `comment-start-regexp'.")
1832 (defvar verilog-mode-syntax-table
1833 (let ((table (make-syntax-table)))
1834 ;; Populate the syntax TABLE.
1835 (modify-syntax-entry ?\\ "\\" table)
1836 (modify-syntax-entry ?+ "." table)
1837 (modify-syntax-entry ?- "." table)
1838 (modify-syntax-entry ?= "." table)
1839 (modify-syntax-entry ?% "." table)
1840 (modify-syntax-entry ?< "." table)
1841 (modify-syntax-entry ?> "." table)
1842 (modify-syntax-entry ?& "." table)
1843 (modify-syntax-entry ?| "." table)
1844 (modify-syntax-entry ?` "w" table)
1845 (modify-syntax-entry ?_ "w" table)
1846 (modify-syntax-entry ?\' "." table)
1848 ;; Set up TABLE to handle block and line style comments.
1849 (if (featurep 'xemacs)
1851 ;; XEmacs (formerly Lucid) has the best implementation
1852 (modify-syntax-entry ?/ ". 1456" table)
1853 (modify-syntax-entry ?* ". 23" table)
1854 (modify-syntax-entry ?\n "> b" table))
1855 ;; Emacs does things differently, but we can work with it
1856 (modify-syntax-entry ?/ ". 124b" table)
1857 (modify-syntax-entry ?* ". 23" table)
1858 (modify-syntax-entry ?\n "> b" table))
1860 "Syntax table used in Verilog mode buffers.")
1862 (defvar verilog-font-lock-keywords nil
1863 "Default highlighting for Verilog mode.")
1865 (defvar verilog-font-lock-keywords-1 nil
1866 "Subdued level highlighting for Verilog mode.")
1868 (defvar verilog-font-lock-keywords-2 nil
1869 "Medium level highlighting for Verilog mode.
1870 See also `verilog-font-lock-extra-types'.")
1872 (defvar verilog-font-lock-keywords-3 nil
1873 "Gaudy level highlighting for Verilog mode.
1874 See also `verilog-font-lock-extra-types'.")
1875 (defvar verilog-font-lock-translate-off-face
1876 'verilog-font-lock-translate-off-face
1877 "Font to use for translated off regions.")
1878 (defface verilog-font-lock-translate-off-face
1881 (:background "gray90" :italic t ))
1884 (:background "gray10" :italic t ))
1885 (((class grayscale) (background light))
1886 (:foreground "DimGray" :italic t))
1887 (((class grayscale) (background dark))
1888 (:foreground "LightGray" :italic t))
1890 "Font lock mode face used to background highlight translate-off regions."
1891 :group 'font-lock-highlighting-faces)
1893 (defvar verilog-font-lock-p1800-face
1894 'verilog-font-lock-p1800-face
1895 "Font to use for p1800 keywords.")
1896 (defface verilog-font-lock-p1800-face
1899 (:foreground "DarkOrange3" :bold t ))
1902 (:foreground "orange1" :bold t ))
1904 "Font lock mode face used to highlight P1800 keywords."
1905 :group 'font-lock-highlighting-faces)
1907 (defvar verilog-font-lock-ams-face
1908 'verilog-font-lock-ams-face
1909 "Font to use for Analog/Mixed Signal keywords.")
1910 (defface verilog-font-lock-ams-face
1913 (:foreground "Purple" :bold t ))
1916 (:foreground "orange1" :bold t ))
1918 "Font lock mode face used to highlight AMS keywords."
1919 :group 'font-lock-highlighting-faces)
1921 (defvar verilog-font-grouping-keywords-face
1922 'verilog-font-lock-grouping-keywords-face
1923 "Font to use for Verilog Grouping Keywords (such as begin..end).")
1924 (defface verilog-font-lock-grouping-keywords-face
1927 (:foreground "red4" :bold t ))
1930 (:foreground "red4" :bold t ))
1932 "Font lock mode face used to highlight verilog grouping keywords."
1933 :group 'font-lock-highlighting-faces)
1935 (let* ((verilog-type-font-keywords
1939 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
1940 "event" "genvar" "inout" "input" "integer" "localparam"
1941 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
1942 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
1943 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
1944 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
1945 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
1946 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
1947 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
1950 (verilog-pragma-keywords
1953 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
1956 (verilog-p1800-keywords
1959 '("alias" "assert" "assume" "automatic" "before" "bind"
1960 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
1961 "clocking" "config" "const" "constraint" "context" "continue"
1962 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
1963 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
1964 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
1965 "expect" "export" "extends" "extern" "first_match" "foreach"
1966 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
1967 "illegal_bins" "import" "incdir" "include" "inside" "instance"
1968 "int" "intersect" "large" "liblist" "library" "local" "longint"
1969 "matches" "medium" "modport" "new" "noshowcancelled" "null"
1970 "packed" "program" "property" "protected" "pull0" "pull1"
1971 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
1972 "randcase" "randsequence" "ref" "release" "return" "scalared"
1973 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
1974 "specparam" "static" "string" "strong0" "strong1" "struct"
1975 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
1976 "type" "union" "unsigned" "use" "var" "virtual" "void"
1977 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
1980 (verilog-ams-keywords
1983 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
1984 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
1985 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
1986 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
1987 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
1988 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
1989 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
1990 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
1991 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
1992 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
1993 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
1995 (verilog-font-keywords
1999 "assign" "case" "casex" "casez" "randcase" "deassign"
2000 "default" "disable" "else" "endcase" "endfunction"
2001 "endgenerate" "endinterface" "endmodule" "endprimitive"
2002 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
2003 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
2004 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
2005 "package" "endpackage" "always" "always_comb" "always_ff"
2006 "always_latch" "posedge" "primitive" "priority" "release"
2007 "repeat" "specify" "table" "task" "unique" "wait" "while"
2008 "class" "program" "endclass" "endprogram"
2011 (verilog-font-grouping-keywords
2014 '( "begin" "end" ) nil ))))
2016 (setq verilog-font-lock-keywords
2018 ;; Fontify all builtin keywords
2019 (concat "\\<\\(" verilog-font-keywords "\\|"
2020 ;; And user/system tasks and functions
2021 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
2023 ;; Fontify all types
2024 (if verilog-highlight-grouping-keywords
2025 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2026 'verilog-font-lock-ams-face)
2027 (cons (concat "\\<\\(" verilog-font-grouping-keywords "\\)\\>")
2028 'font-lock-type-face))
2029 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
2030 'font-lock-type-face)
2031 ;; Fontify IEEE-P1800 keywords appropriately
2032 (if verilog-highlight-p1800-keywords
2033 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2034 'verilog-font-lock-p1800-face)
2035 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
2036 'font-lock-type-face))
2037 ;; Fontify Verilog-AMS keywords
2038 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
2039 'verilog-font-lock-ams-face)))
2041 (setq verilog-font-lock-keywords-1
2042 (append verilog-font-lock-keywords
2044 ;; Fontify module definitions
2046 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
2047 '(1 font-lock-keyword-face)
2048 '(3 font-lock-function-name-face 'prepend))
2049 ;; Fontify function definitions
2051 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
2052 '(1 font-lock-keyword-face)
2053 '(3 font-lock-reference-face prepend))
2054 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
2055 (1 font-lock-keyword-face)
2056 (2 font-lock-reference-face append))
2057 '("\\<function\\>\\s-+\\(\\sw+\\)"
2058 1 'font-lock-reference-face append))))
2060 (setq verilog-font-lock-keywords-2
2061 (append verilog-font-lock-keywords-1
2064 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
2065 ;; Fontify escaped names
2066 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
2067 ;; Fontify macro definitions/ uses
2068 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
2069 'font-lock-preprocessor-face
2070 'font-lock-type-face))
2071 ;; Fontify delays/numbers
2072 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
2073 0 font-lock-type-face append)
2074 ;; Fontify instantiation names
2075 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
2078 (setq verilog-font-lock-keywords-3
2079 (append verilog-font-lock-keywords-2
2080 (when verilog-highlight-translate-off
2082 ;; Fontify things in translate off regions
2083 '(verilog-match-translate-off
2084 (0 'verilog-font-lock-translate-off-face prepend))
2088 (defun verilog-inside-comment-p ()
2089 "Check if point inside a nested comment."
2091 (let ((st-point (point)) hitbeg)
2092 (or (search-backward "//" (verilog-get-beg-of-line) t)
2094 ;; This is for tricky case //*, we keep searching if /*
2095 ;; is proceeded by // on same line.
2097 (and (setq hitbeg (search-backward "/*" nil t))
2100 (search-backward "//" (verilog-get-beg-of-line) t))))
2102 (not (search-forward "*/" st-point t)))))))
2104 (defun verilog-declaration-end ()
2105 (search-forward ";"))
2107 (defun verilog-point-text (&optional pointnum)
2108 "Return text describing where POINTNUM or current point is (for errors).
2109 Use filename, if current buffer being edited shorten to just buffer name."
2110 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
2114 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
2116 (defun electric-verilog-backward-sexp ()
2117 "Move backward over one balanced expression."
2119 ;; before that see if we are in a comment
2120 (verilog-backward-sexp))
2122 (defun electric-verilog-forward-sexp ()
2123 "Move forward over one balanced expression."
2125 ;; before that see if we are in a comment
2126 (verilog-forward-sexp))
2128 ;;;used by hs-minor-mode
2129 (defun verilog-forward-sexp-function (arg)
2131 (verilog-backward-sexp)
2132 (verilog-forward-sexp)))
2135 (defun verilog-backward-sexp ()
2140 (if (not (looking-at "\\<"))
2143 ((verilog-skip-backward-comment-or-string))
2144 ((looking-at "\\<else\\>")
2146 verilog-end-block-re
2147 "\\|\\(\\<else\\>\\)"
2148 "\\|\\(\\<if\\>\\)"))
2149 (while (and (not found)
2150 (verilog-re-search-backward reg nil 'move))
2152 ((match-end 1) ; matched verilog-end-block-re
2153 ; try to leap back to matching outward block by striding across
2154 ; indent level changing tokens then immediately
2155 ; previous line governs indentation.
2156 (verilog-leap-to-head))
2157 ((match-end 2) ; else, we're in deep
2158 (setq elsec (1+ elsec)))
2159 ((match-end 3) ; found it
2160 (setq elsec (1- elsec))
2162 ;; Now previous line describes syntax
2163 (setq found 't))))))
2164 ((looking-at verilog-end-block-re)
2165 (verilog-leap-to-head))
2166 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
2169 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
2171 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
2173 (verilog-re-search-backward "\\<class\\>" nil 'move))
2175 (verilog-re-search-backward "\\<program\\>" nil 'move))
2177 (verilog-re-search-backward "\\<interface\\>" nil 'move))
2179 (verilog-re-search-backward "\\<package\\>" nil 'move))
2182 (backward-sexp 1))))
2187 (defun verilog-forward-sexp ()
2191 (if (not (looking-at "\\<"))
2194 ((verilog-skip-forward-comment-or-string)
2195 (verilog-forward-syntactic-ws))
2196 ((looking-at verilog-beg-block-re-ordered) ;; begin|(case)|xx|(fork)|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
2198 ((match-end 1) ; end
2199 ;; Search forward for matching begin
2200 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
2201 ((match-end 2) ; endcase
2202 ;; Search forward for matching case
2203 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
2204 (setq md 3) ;; ender is third item in regexp
2206 ((match-end 4) ; join
2207 ;; might be "disable fork"
2209 (looking-at verilog-disable-fork-re)
2210 (and (looking-at "fork")
2213 (looking-at verilog-disable-fork-re))))
2215 (goto-char (match-end 0))
2219 ;; Search forward for matching fork
2220 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))))
2221 ((match-end 5) ; endclass
2222 ;; Search forward for matching class
2223 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
2224 ((match-end 6) ; endtable
2225 ;; Search forward for matching table
2226 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
2227 ((match-end 7) ; endspecify
2228 ;; Search forward for matching specify
2229 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
2230 ((match-end 8) ; endfunction
2231 ;; Search forward for matching function
2232 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
2233 ((match-end 9) ; endtask
2234 ;; Search forward for matching task
2235 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
2236 ((match-end 10) ; endgenerate
2237 ;; Search forward for matching generate
2238 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
2239 ((match-end 11) ; endgroup
2240 ;; Search forward for matching covergroup
2241 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
2242 ((match-end 12) ; endproperty
2243 ;; Search forward for matching property
2244 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
2245 ((match-end 13) ; endsequence
2246 ;; Search forward for matching sequence
2247 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
2248 (setq md 3)) ; 3 to get to endsequence in the reg above
2249 ((match-end 14) ; endclocking
2250 ;; Search forward for matching clocking
2251 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" )))
2256 (while (verilog-re-search-forward reg nil 'move)
2258 ((match-end md) ; the closer in reg, so we are climbing out
2259 (setq nest (1- nest))
2260 (if (= 0 nest) ; we are out!
2262 ((match-end 1) ; the opener in reg, so we are deeper now
2263 (setq nest (1+ nest)))))))))
2264 ((looking-at (concat
2265 "\\(\\<\\(macro\\)?module\\>\\)\\|"
2266 "\\(\\<primitive\\>\\)\\|"
2267 "\\(\\<class\\>\\)\\|"
2268 "\\(\\<program\\>\\)\\|"
2269 "\\(\\<interface\\>\\)\\|"
2270 "\\(\\<package\\>\\)"))
2273 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
2275 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
2277 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
2279 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
2281 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
2283 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
2286 (if (= (following-char) ?\) )
2288 (forward-sexp 1)))))
2291 (if (= (following-char) ?\) )
2293 (forward-sexp 1))))))
2295 (defun verilog-declaration-beg ()
2296 (verilog-re-search-backward verilog-declaration-re (bobp) t))
2298 (defun verilog-font-lock-init ()
2299 "Initialize fontification."
2300 ;; highlight keywords and standardized types, attributes, enumeration
2301 ;; values, and subprograms
2302 (setq verilog-font-lock-keywords-3
2303 (append verilog-font-lock-keywords-2
2304 (when verilog-highlight-translate-off
2306 ;; Fontify things in translate off regions
2307 '(verilog-match-translate-off
2308 (0 'verilog-font-lock-translate-off-face prepend))))))
2309 (put 'verilog-mode 'font-lock-defaults
2310 '((verilog-font-lock-keywords
2311 verilog-font-lock-keywords-1
2312 verilog-font-lock-keywords-2
2313 verilog-font-lock-keywords-3)
2314 nil ; nil means highlight strings & comments as well as keywords
2315 nil ; nil means keywords must match case
2316 nil ; syntax table handled elsewhere
2317 ;; Function to move to beginning of reasonable region to highlight
2318 verilog-beg-of-defun)))
2320 ;; initialize fontification for Verilog Mode
2321 (verilog-font-lock-init)
2327 (defvar verilog-which-tool 1)
2329 (defun verilog-mode ()
2330 "Major mode for editing Verilog code.
2331 \\<verilog-mode-map>
2332 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
2333 AUTOs can improve coding efficiency.
2335 Use \\[verilog-faq] for a pointer to frequently asked questions.
2337 NEWLINE, TAB indents for Verilog code.
2338 Delete converts tabs to spaces as it moves back.
2340 Supports highlighting.
2342 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
2343 with no args, if that value is non-nil.
2345 Variables controlling indentation/edit style:
2347 variable `verilog-indent-level' (default 3)
2348 Indentation of Verilog statements with respect to containing block.
2349 `verilog-indent-level-module' (default 3)
2350 Absolute indentation of Module level Verilog statements.
2351 Set to 0 to get initial and always statements lined up
2352 on the left side of your screen.
2353 `verilog-indent-level-declaration' (default 3)
2354 Indentation of declarations with respect to containing block.
2355 Set to 0 to get them list right under containing block.
2356 `verilog-indent-level-behavioral' (default 3)
2357 Indentation of first begin in a task or function block
2358 Set to 0 to get such code to lined up underneath the task or
2360 `verilog-indent-level-directive' (default 1)
2361 Indentation of `ifdef/`endif blocks.
2362 `verilog-cexp-indent' (default 1)
2363 Indentation of Verilog statements broken across lines i.e.:
2366 `verilog-case-indent' (default 2)
2367 Indentation for case statements.
2368 `verilog-auto-newline' (default nil)
2369 Non-nil means automatically newline after semicolons and the punctuation
2371 `verilog-auto-indent-on-newline' (default t)
2372 Non-nil means automatically indent line after newline.
2373 `verilog-tab-always-indent' (default t)
2374 Non-nil means TAB in Verilog mode should always reindent the current line,
2375 regardless of where in the line point is when the TAB command is used.
2376 `verilog-indent-begin-after-if' (default t)
2377 Non-nil means to indent begin statements following a preceding
2378 if, else, while, for and repeat statements, if any. Otherwise,
2379 the begin is lined up with the preceding token. If t, you get:
2381 begin // amount of indent based on `verilog-cexp-indent'
2385 `verilog-auto-endcomments' (default t)
2386 Non-nil means a comment /* ... */ is set after the ends which ends
2387 cases, tasks, functions and modules.
2388 The type and name of the object will be set between the braces.
2389 `verilog-minimum-comment-distance' (default 10)
2390 Minimum distance (in lines) between begin and end required before a comment
2391 will be inserted. Setting this variable to zero results in every
2392 end acquiring a comment; the default avoids too many redundant
2393 comments in tight quarters.
2394 `verilog-auto-lineup' (default `(all))
2395 List of contexts where auto lineup of code should be done.
2397 Variables controlling other actions:
2399 `verilog-linter' (default surelint)
2400 Unix program to call to run the lint checker. This is the default
2401 command for \\[compile-command] and \\[verilog-auto-save-compile].
2403 See \\[customize] for the complete list of variables.
2405 AUTO expansion functions are, in part:
2407 \\[verilog-auto] Expand AUTO statements.
2408 \\[verilog-delete-auto] Remove the AUTOs.
2409 \\[verilog-inject-auto] Insert AUTOs for the first time.
2411 Some other functions are:
2413 \\[verilog-complete-word] Complete word with appropriate possibilities.
2414 \\[verilog-mark-defun] Mark function.
2415 \\[verilog-beg-of-defun] Move to beginning of current function.
2416 \\[verilog-end-of-defun] Move to end of current function.
2417 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
2419 \\[verilog-comment-region] Put marked area in a comment.
2420 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
2421 \\[verilog-insert-block] Insert begin ... end.
2422 \\[verilog-star-comment] Insert /* ... */.
2424 \\[verilog-sk-always] Insert an always @(AS) begin .. end block.
2425 \\[verilog-sk-begin] Insert a begin .. end block.
2426 \\[verilog-sk-case] Insert a case block, prompting for details.
2427 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
2428 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
2429 \\[verilog-sk-header] Insert a header block at the top of file.
2430 \\[verilog-sk-initial] Insert an initial begin .. end block.
2431 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
2432 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
2433 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
2434 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
2435 \\[verilog-sk-specify] Insert a specify .. endspecify block.
2436 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
2437 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
2438 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
2439 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
2440 \\[verilog-sk-if] Insert an if (..) begin .. end block.
2441 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
2442 \\[verilog-sk-comment] Insert a comment block.
2443 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
2444 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
2445 \\[verilog-sk-input] Insert an input declaration, prompting for details.
2446 \\[verilog-sk-output] Insert an output declaration, prompting for details.
2447 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
2448 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
2449 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
2450 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
2451 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
2453 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
2454 Key bindings specific to `verilog-mode-map' are:
2456 \\{verilog-mode-map}"
2458 (kill-all-local-variables)
2459 (use-local-map verilog-mode-map)
2460 (setq major-mode 'verilog-mode)
2461 (setq mode-name "Verilog")
2462 (setq local-abbrev-table verilog-mode-abbrev-table)
2463 (set (make-local-variable 'beginning-of-defun-function)
2464 'verilog-beg-of-defun)
2465 (set (make-local-variable 'end-of-defun-function)
2466 'verilog-end-of-defun)
2467 (set-syntax-table verilog-mode-syntax-table)
2468 (make-local-variable 'indent-line-function)
2469 (setq indent-line-function 'verilog-indent-line-relative)
2470 (setq comment-indent-function 'verilog-comment-indent)
2471 (make-local-variable 'parse-sexp-ignore-comments)
2472 (setq parse-sexp-ignore-comments nil)
2473 (make-local-variable 'comment-start)
2474 (make-local-variable 'comment-end)
2475 (make-local-variable 'comment-multi-line)
2476 (make-local-variable 'comment-start-skip)
2477 (setq comment-start "// "
2479 comment-start-skip "/\\*+ *\\|// *"
2480 comment-multi-line nil)
2481 ;; Set up for compilation
2482 (setq verilog-which-tool 1)
2483 (setq verilog-tool 'verilog-linter)
2484 (verilog-set-compile-command)
2485 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
2486 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
2489 (when (featurep 'xemacs)
2490 (easy-menu-add verilog-stmt-menu)
2491 (easy-menu-add verilog-menu)
2492 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))
2494 ;; Stuff for GNU Emacs
2495 (set (make-local-variable 'font-lock-defaults)
2496 '((verilog-font-lock-keywords verilog-font-lock-keywords-1
2497 verilog-font-lock-keywords-2
2498 verilog-font-lock-keywords-3)
2499 nil nil nil verilog-beg-of-defun))
2500 ;;------------------------------------------------------------
2501 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
2502 ;; all buffer local:
2503 (when (featurep 'xemacs)
2504 (make-local-hook 'font-lock-mode-hook)
2505 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in Emacs
2506 (make-local-hook 'after-change-functions))
2507 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
2508 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in Emacs
2509 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
2511 ;; Tell imenu how to handle Verilog.
2512 (make-local-variable 'imenu-generic-expression)
2513 (setq imenu-generic-expression verilog-imenu-generic-expression)
2515 (unless (assq 'verilog-mode hs-special-modes-alist)
2516 (setq hs-special-modes-alist
2517 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
2518 verilog-forward-sexp-function)
2519 hs-special-modes-alist)))
2522 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
2523 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
2524 ;; (verilog-getopt-flags)
2525 (run-hooks 'verilog-mode-hook))
2529 ;; Electric functions
2531 (defun electric-verilog-terminate-line (&optional arg)
2532 "Terminate line and indent next line.
2533 With optional ARG, remove existing end of line comments."
2535 ;; before that see if we are in a comment
2536 (let ((state (save-excursion (verilog-syntax-ppss))))
2538 ((nth 7 state) ; Inside // comment
2541 (delete-horizontal-space)
2546 (beginning-of-line)))
2547 (verilog-indent-line))
2548 ((nth 4 state) ; Inside any comment (hence /**/)
2550 (verilog-more-comment))
2552 ;; First, check if current line should be indented
2554 (delete-horizontal-space)
2556 (skip-chars-forward " \t")
2557 (if (looking-at verilog-auto-end-comment-lines-re)
2558 (let ((indent-str (verilog-indent-line)))
2559 ;; Maybe we should set some endcomments
2560 (if verilog-auto-endcomments
2561 (verilog-set-auto-endcomments indent-str arg))
2563 (delete-horizontal-space)
2570 (delete-horizontal-space)
2572 ;; see if we should line up assignments
2574 (if (or (memq 'all verilog-auto-lineup)
2575 (memq 'assignments verilog-auto-lineup))
2576 (verilog-pretty-expr))
2580 (if verilog-auto-indent-on-newline
2581 (verilog-indent-line)))
2585 (defun electric-verilog-terminate-and-indent ()
2586 "Insert a newline and indent for the next statement."
2588 (electric-verilog-terminate-line 1))
2590 (defun electric-verilog-semi ()
2591 "Insert `;' character and reindent the line."
2593 (insert last-command-char)
2595 (if (or (verilog-in-comment-or-string-p)
2596 (verilog-in-escaped-name-p))
2600 (verilog-forward-ws&directives)
2601 (verilog-indent-line))
2602 (if (and verilog-auto-newline
2603 (not (verilog-parenthesis-depth)))
2604 (electric-verilog-terminate-line))))
2606 (defun electric-verilog-semi-with-comment ()
2607 "Insert `;' character, reindent the line and indent for comment."
2612 (verilog-indent-line))
2613 (indent-for-comment))
2615 (defun electric-verilog-colon ()
2616 "Insert `:' and do all indentations except line indent on this line."
2618 (insert last-command-char)
2619 ;; Do nothing if within string.
2621 (verilog-within-string)
2622 (not (verilog-in-case-region-p)))
2626 (lim (progn (verilog-beg-of-statement) (point))))
2628 (verilog-backward-case-item lim)
2629 (verilog-indent-line)))
2630 ;; (let ((verilog-tab-always-indent nil))
2631 ;; (verilog-indent-line))
2634 ;;(defun electric-verilog-equal ()
2635 ;; "Insert `=', and do indentation if within block."
2637 ;; (insert last-command-char)
2638 ;; Could auto line up expressions, but not yet
2639 ;; (if (eq (car (verilog-calculate-indent)) 'block)
2640 ;; (let ((verilog-tab-always-indent nil))
2641 ;; (verilog-indent-command)))
2644 (defun electric-verilog-tick ()
2645 "Insert back-tick, and indent to column 0 if this is a CPP directive."
2647 (insert last-command-char)
2651 (looking-at verilog-directive-re-1))
2652 (verilog-indent-line))))
2654 (defun electric-verilog-tab ()
2655 "Function called when TAB is pressed in Verilog mode."
2657 ;; If verilog-tab-always-indent, indent the beginning of the line.
2658 (if (or verilog-tab-always-indent
2660 (skip-chars-backward " \t")
2662 (let* ((oldpnt (point))
2666 (skip-chars-forward " \t")
2667 (verilog-indent-line)
2668 (back-to-indentation)
2670 (if (< (point) boi-point)
2671 (back-to-indentation)
2672 (cond ((not verilog-tab-to-comment))
2676 (indent-for-comment)
2677 (when (and (eolp) (= oldpnt (point)))
2678 ; kill existing comment
2680 (re-search-forward comment-start-skip oldpnt 'move)
2681 (goto-char (match-beginning 0))
2682 (skip-chars-backward " \t")
2683 (kill-region (point) oldpnt))))))
2684 (progn (insert "\t"))))
2689 ;; Interactive functions
2692 (defun verilog-indent-buffer ()
2693 "Indent-region the entire buffer as Verilog code.
2694 To call this from the command line, see \\[verilog-batch-indent]."
2697 (indent-region (point-min) (point-max) nil))
2699 (defun verilog-insert-block ()
2700 "Insert Verilog begin ... end; block in the code with right indentation."
2702 (verilog-indent-line)
2704 (electric-verilog-terminate-line)
2706 (electric-verilog-terminate-line)
2709 (verilog-indent-line)))
2711 (defun verilog-star-comment ()
2712 "Insert Verilog star comment at point."
2714 (verilog-indent-line)
2722 (defun verilog-insert-1 (fmt max)
2723 "Use format string FMT to insert integers 0 to MAX - 1.
2724 Inserts one integer per line, at the current column. Stops early
2725 if it reaches the end of the buffer."
2726 (let ((col (current-column))
2730 (insert (format fmt n))
2732 ;; Note that this function does not bother to check for lines
2733 ;; shorter than col.
2737 (move-to-column col))))))
2739 (defun verilog-insert-indices (max)
2740 "Insert a set of indices into a rectangle.
2741 The upper left corner is defined by point. Indices begin with 0
2742 and extend to the MAX - 1. If no prefix arg is given, the user
2743 is prompted for a value. The indices are surrounded by square
2744 brackets \[]. For example, the following code with the point
2745 located after the first 'a' gives:
2751 a = b ==> insert-indices ==> a[ 4] = b
2757 (interactive "NMAX: ")
2758 (verilog-insert-1 "[%3d]" max))
2760 (defun verilog-generate-numbers (max)
2761 "Insert a set of generated numbers into a rectangle.
2762 The upper left corner is defined by point. The numbers are padded to three
2763 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
2764 is supplied, then the user is prompted for the MAX number. Consider the
2765 following code fragment:
2771 buf buf ==> generate-numbers ==> buf buf004
2777 (interactive "NMAX: ")
2778 (verilog-insert-1 "%3.3d" max))
2780 (defun verilog-mark-defun ()
2781 "Mark the current Verilog function (or procedure).
2782 This puts the mark at the end, and point at the beginning."
2784 (if (featurep 'xemacs)
2787 (verilog-end-of-defun)
2789 (verilog-beg-of-defun)
2790 (if (fboundp 'zmacs-activate-region)
2791 (zmacs-activate-region)))
2794 (defun verilog-comment-region (start end)
2795 ; checkdoc-params: (start end)
2796 "Put the region into a Verilog comment.
2797 The comments that are in this area are \"deformed\":
2798 `*)' becomes `!(*' and `}' becomes `!{'.
2799 These deformed comments are returned to normal if you use
2800 \\[verilog-uncomment-region] to undo the commenting.
2802 The commented area starts with `verilog-exclude-str-start', and ends with
2803 `verilog-exclude-str-end'. But if you change these variables,
2804 \\[verilog-uncomment-region] won't recognize the comments."
2807 ;; Insert start and endcomments
2809 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
2810 (not (save-excursion (skip-chars-backward " \t") (bolp))))
2812 (beginning-of-line))
2813 (insert verilog-exclude-str-end)
2818 (insert verilog-exclude-str-start)
2820 ;; Replace end-comments within commented area
2823 (while (re-search-backward "\\*/" start t)
2824 (replace-match "*-/" t t)))
2826 (let ((s+1 (1+ start)))
2827 (while (re-search-backward "/\\*" s+1 t)
2828 (replace-match "/-*" t t))))))
2830 (defun verilog-uncomment-region ()
2831 "Uncomment a commented area; change deformed comments back to normal.
2832 This command does nothing if the pointer is not in a commented
2833 area. See also `verilog-comment-region'."
2836 (let ((start (point))
2838 ;; Find the boundaries of the comment
2840 (setq start (progn (search-backward verilog-exclude-str-start nil t)
2842 (setq end (progn (search-forward verilog-exclude-str-end nil t)
2844 ;; Check if we're really inside a comment
2845 (if (or (equal start (point)) (<= end (point)))
2846 (message "Not standing within commented area.")
2848 ;; Remove endcomment
2851 (let ((pos (point)))
2853 (delete-region pos (1+ (point))))
2854 ;; Change comments back to normal
2856 (while (re-search-backward "\\*-/" start t)
2857 (replace-match "*/" t t)))
2859 (while (re-search-backward "/-\\*" start t)
2860 (replace-match "/*" t t)))
2861 ;; Remove start comment
2864 (let ((pos (point)))
2866 (delete-region pos (1+ (point)))))))))
2868 (defun verilog-beg-of-defun ()
2869 "Move backward to the beginning of the current function or procedure."
2871 (verilog-re-search-backward verilog-defun-re nil 'move))
2873 (defun verilog-end-of-defun ()
2874 "Move forward to the end of the current function or procedure."
2876 (verilog-re-search-forward verilog-end-defun-re nil 'move))
2878 (defun verilog-get-beg-of-defun (&optional warn)
2880 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
2883 (error "%s: Can't find module beginning" (verilog-point-text))
2885 (defun verilog-get-end-of-defun (&optional warn)
2887 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
2890 (error "%s: Can't find endmodule" (verilog-point-text))
2893 (defun verilog-label-be (&optional arg)
2894 "Label matching begin ... end, fork ... join and case ... endcase statements.
2895 With ARG, first kill any existing labels."
2900 (verilog-beg-of-defun)
2903 (verilog-end-of-defun)
2905 (goto-char (marker-position b))
2907 (message "Relabeling module..."))
2909 (> (marker-position e) (point))
2910 (verilog-re-search-forward
2912 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
2913 "\\|\\(`endif\\)\\|\\(`else\\)")
2915 (goto-char (match-beginning 0))
2916 (let ((indent-str (verilog-indent-line)))
2917 (verilog-set-auto-endcomments indent-str 't)
2919 (delete-horizontal-space))
2921 (if (= 9 (% cnt 10))
2922 (message "%d..." cnt)))
2927 (message "%d lines auto commented" cnt))))
2929 (defun verilog-beg-of-statement ()
2930 "Move backward to beginning of statement."
2932 ;; Move back token by token until we see the end
2933 ;; of some ealier line.
2935 ;; If the current point does not begin a new
2936 ;; statement, as in the character ahead of us is a ';', or SOF
2937 ;; or the string after us unambiguosly starts a statement,
2938 ;; or the token before us unambiguously ends a statement,
2939 ;; then move back a token and test again.
2942 (= (preceding-char) ?\;)
2947 (looking-at verilog-extended-complete-re)
2948 (not (save-excursion
2949 (verilog-backward-token)
2950 (looking-at verilog-extended-complete-re))))
2951 (looking-at verilog-basic-complete-re)
2953 (verilog-backward-token)
2955 (looking-at verilog-end-block-re)
2956 (looking-at verilog-preprocessor-re)))))
2957 (verilog-backward-syntactic-ws)
2958 (verilog-backward-token))
2959 ;; Now point is where the previous line ended.
2960 (verilog-forward-syntactic-ws))
2962 (defun verilog-beg-of-statement-1 ()
2963 "Move backward to beginning of statement."
2967 (while (and (not (looking-at verilog-complete-reg))
2969 (verilog-backward-token)
2970 (not (looking-at verilog-complete-reg))
2971 (verilog-backward-syntactic-ws)
2974 (not (= (preceding-char) ?\;))))
2976 (verilog-forward-ws&directives)))
2978 (defun verilog-end-of-statement ()
2979 "Move forward to end of current statement."
2982 (or (looking-at verilog-beg-block-re)
2983 ;; Skip to end of statement
2984 (setq pos (catch 'found
2987 (verilog-skip-forward-comment-or-string)
2988 (cond ((looking-at "[ \t]*;")
2989 (skip-chars-forward "^;")
2991 (throw 'found (point)))
2994 (looking-at verilog-beg-block-re))
2995 (goto-char (match-beginning 0))
2997 ((looking-at "[ \t]*)")
2998 (throw 'found (point)))
3000 (throw 'found (point))))))))
3002 ;; Skip a whole block
3005 (verilog-re-search-forward verilog-end-statement-re nil 'move)
3006 (setq nest (if (match-end 1)
3010 (throw 'found (point)))
3012 (throw 'found (verilog-end-of-statement))))))
3015 (defun verilog-in-case-region-p ()
3016 "Return true if in a case region.
3017 More specifically, point @ in the line foo : @ begin"
3021 (progn (verilog-forward-syntactic-ws)
3022 (looking-at "\\<begin\\>"))
3023 (progn (verilog-backward-syntactic-ws)
3024 (= (preceding-char) ?\:)))
3028 (verilog-re-search-backward
3029 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
3030 "\\(\\<endcase\\>\\)\\>")
3034 (setq nest (1+ nest)))
3038 (setq nest (1- nest)))
3040 (throw 'found (= nest 0)))))))
3042 (defun verilog-in-struct-region-p ()
3043 "Return true if in a struct region.
3044 More specifically, in a list after a struct|union keyword."
3047 (let* ((state (verilog-syntax-ppss))
3048 (depth (nth 0 state)))
3050 (progn (backward-up-list depth)
3051 (verilog-beg-of-statement)
3052 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>"))))))
3054 (defun verilog-in-generate-region-p ()
3055 "Return true if in a generate region.
3056 More specifically, after a generate and before an endgenerate."
3058 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3063 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
3065 ((match-end 1) ; generate
3066 (setq nest (1- nest)))
3067 ((match-end 2) ; endgenerate
3068 (setq nest (1+ nest)))))))
3069 (= nest 0) )) ; return nest
3071 (defun verilog-in-fork-region-p ()
3072 "Return true if between a fork and join."
3074 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
3079 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
3081 ((match-end 1) ; fork
3082 (setq nest (1- nest)))
3083 ((match-end 2) ; join
3084 (setq nest (1+ nest)))))))
3085 (= nest 0) )) ; return nest
3087 (defun verilog-backward-case-item (lim)
3088 "Skip backward to nearest enclosing case item.
3089 Limit search to point LIM."
3095 (verilog-re-search-backward verilog-endcomment-reason-re
3098 ;; Try to find the real :
3099 (if (save-excursion (search-backward ":" lim1 t))
3105 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
3109 (setq colon (1+ colon))
3111 (error "%s: unbalanced [" (verilog-point-text))))
3113 (setq colon (1- colon)))
3116 (setq colon (1+ colon)))))
3117 ;; Skip back to beginning of case item
3118 (skip-chars-backward "\t ")
3119 (verilog-skip-backward-comment-or-string)
3124 (verilog-re-search-backward
3125 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
3129 (goto-char (match-end 1))
3130 (verilog-forward-ws&directives)
3131 (if (looking-at "(")
3134 (verilog-forward-ws&directives)))
3137 (goto-char (match-end 0))
3138 (verilog-forward-ws&directives)
3140 (error "Malformed case item"))))
3141 (setq str (buffer-substring b e))
3145 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3146 (setq str (concat (substring str 0 e) "...")))
3155 (defun verilog-kill-existing-comment ()
3156 "Kill auto comment on this line."
3164 (search-forward "//" e t))))
3166 (delete-region (- b 2) e)))))
3168 (defconst verilog-directive-nest-re
3169 (concat "\\(`else\\>\\)\\|"
3170 "\\(`endif\\>\\)\\|"
3172 "\\(`ifdef\\>\\)\\|"
3173 "\\(`ifndef\\>\\)"))
3174 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
3175 "Add ending comment with given INDENT-STR.
3176 With KILL-EXISTING-COMMENT, remove what was there before.
3177 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
3178 Insert `// case expr ' if this line ends a case block.
3179 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
3180 Insert `// NAME ' if this line ends a function, task, module,
3181 primitive or interface named NAME."
3184 (; Comment close preprocessor directives
3186 (looking-at "\\(`endif\\)\\|\\(`else\\)")
3187 (or kill-existing-comment
3188 (not (save-excursion
3190 (search-backward "//" (verilog-get-beg-of-line) t)))))
3193 (else (if (match-end 2) "!" " ")))
3195 (if kill-existing-comment
3196 (verilog-kill-existing-comment))
3197 (delete-horizontal-space)
3200 (while (and (/= nest 0)
3201 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
3203 ((match-end 1) ; `else
3206 ((match-end 2) ; `endif
3207 (setq nest (1+ nest)))
3208 ((match-end 3) ; `if
3209 (setq nest (1- nest)))
3210 ((match-end 4) ; `ifdef
3211 (setq nest (1- nest)))
3212 ((match-end 5) ; `ifndef
3213 (setq nest (1- nest)))))
3220 (skip-chars-forward "^ \t")
3221 (verilog-forward-syntactic-ws)
3224 (skip-chars-forward "a-zA-Z0-9_")
3227 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
3228 (insert (concat " // " else m " " (buffer-substring b e))))
3230 (insert " // unmatched `else or `endif")
3233 (; Comment close case/class/function/task/module and named block
3234 (and (looking-at "\\<end")
3235 (or kill-existing-comment
3236 (not (save-excursion
3238 (search-backward "//" (verilog-get-beg-of-line) t)))))
3239 (let ((type (car indent-str)))
3240 (unless (eq type 'declaration)
3241 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
3242 (if (looking-at verilog-end-block-ordered-re)
3244 (;- This is a case block; search back for the start of this case
3245 (match-end 1) ;; of verilog-end-block-ordered-re
3248 (str "UNMATCHED!!"))
3250 (verilog-leap-to-head)
3252 ((looking-at "\\<randcase\\>")
3253 (setq str "randcase")
3256 (goto-char (match-end 1))
3259 (setq s (match-beginning 1))
3260 (setq f (progn (end-of-line)
3262 (setq str (buffer-substring s f)))
3264 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
3266 (verilog-get-expr))))))
3268 (if kill-existing-comment
3269 (verilog-kill-existing-comment))
3270 (delete-horizontal-space)
3271 (insert (concat " // " str ))
3272 (if err (ding 't))))
3274 (;- This is a begin..end block
3275 (match-end 2) ;; of verilog-end-block-ordered-re
3276 (let ((str " // UNMATCHED !!")
3282 (verilog-leap-to-head)
3283 (setq there (point))
3284 (if (not (match-end 0))
3288 (if kill-existing-comment
3289 (verilog-kill-existing-comment))
3290 (delete-horizontal-space)
3294 (save-excursion (verilog-beg-of-defun) (point)))
3297 (;-- handle named block differently
3298 (looking-at verilog-named-block-re)
3299 (search-forward ":")
3300 (setq there (point))
3301 (setq str (verilog-get-expr))
3303 (setq str (concat " // block: " str )))
3305 ((verilog-in-case-region-p) ;-- handle case item differently
3307 (setq str (verilog-backward-case-item lim))
3308 (setq there (point))
3310 (setq str (concat " // case: " str )))
3312 (;- try to find "reason" for this begin
3316 (verilog-backward-token)
3317 (verilog-beg-of-statement-1)
3321 ((looking-at verilog-endcomment-reason-re)
3322 (setq there (match-end 0))
3324 (buffer-substring (match-beginning 0) (match-end 0)) " "))
3330 (if (and (verilog-continued-line)
3331 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
3333 (goto-char (match-end 0))
3334 (setq there (point))
3337 (buffer-substring (match-beginning 0) (match-end 0)) " "
3338 (verilog-get-expr))))
3344 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3346 (while (verilog-re-search-backward reg nil 'move)
3348 ((match-end 1) ; begin
3349 (setq nest (1- nest)))
3350 ((match-end 2) ; end
3351 (setq nest (1+ nest)))
3355 (goto-char (match-end 0))
3356 (setq there (point))
3358 (setq str (verilog-get-expr))
3359 (setq str (concat " // else: !if" str ))
3360 (throw 'skip 1)))))))))
3366 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)"))
3368 (while (verilog-re-search-backward reg nil 'move)
3370 ((match-end 1) ; begin
3371 (setq nest (1- nest)))
3372 ((match-end 2) ; end
3373 (setq nest (1+ nest)))
3377 (goto-char (match-end 0))
3378 (setq there (point))
3380 (setq str (verilog-get-expr))
3381 (setq str (concat " // else: !if" str ))
3382 (throw 'skip 1)))))))))
3384 (;- task/function/initial et cetera
3387 (goto-char (match-end 0))
3388 (setq there (point))
3390 (setq str (verilog-get-expr))
3391 (setq str (concat " // " cntx str )))
3394 (setq str " // auto-endcomment confused "))))
3397 (verilog-in-case-region-p) ;-- handle case item differently
3399 (setq there (point))
3401 (setq str (verilog-backward-case-item lim))))
3403 (setq str (concat " // case: " str )))
3405 ((verilog-in-fork-region-p)
3407 (setq str " // fork branch" ))
3409 ((looking-at "\\<end\\>")
3412 (verilog-forward-syntactic-ws)
3414 (setq str (verilog-get-expr))
3415 (setq str (concat " // " cntx str )))
3420 (if kill-existing-comment
3421 (verilog-kill-existing-comment))
3422 (delete-horizontal-space)
3424 (> (count-lines here there) verilog-minimum-comment-distance))
3428 (;- this is endclass, which can be nested
3429 (match-end 11) ;; of verilog-end-block-ordered-re
3432 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
3436 (while (verilog-re-search-backward reg nil 'move)
3438 ((match-end 3) ; endclass
3440 (setq string "unmatched endclass")
3443 ((match-end 2) ; endclass
3444 (setq nest (1+ nest)))
3446 ((match-end 1) ; class
3447 (setq nest (1- nest))
3450 (goto-char (match-end 0))
3453 (skip-chars-forward "^ \t")
3454 (verilog-forward-ws&directives)
3457 (skip-chars-forward "a-zA-Z0-9_")
3459 (setq string (buffer-substring b e)))
3463 (insert (concat " // " string ))))
3465 (;- this is end{function,generate,task,module,primitive,table,generate}
3466 ;- which can not be nested.
3468 (let (string reg (width nil))
3470 (if kill-existing-comment
3472 (verilog-kill-existing-comment)))
3473 (delete-horizontal-space)
3476 ((match-end 5) ;; of verilog-end-block-ordered-re
3477 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
3478 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?"))
3479 ((match-end 6) ;; of verilog-end-block-ordered-re
3480 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
3481 ((match-end 7) ;; of verilog-end-block-ordered-re
3482 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
3483 ((match-end 8) ;; of verilog-end-block-ordered-re
3484 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3485 ((match-end 9) ;; of verilog-end-block-ordered-re
3486 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
3487 ((match-end 10) ;; of verilog-end-block-ordered-re
3488 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3489 ((match-end 11) ;; of verilog-end-block-ordered-re
3490 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3491 ((match-end 12) ;; of verilog-end-block-ordered-re
3492 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3493 ((match-end 13) ;; of verilog-end-block-ordered-re
3494 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3495 ((match-end 14) ;; of verilog-end-block-ordered-re
3496 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
3497 ((match-end 15) ;; of verilog-end-block-ordered-re
3498 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
3500 (t (error "Problem in verilog-set-auto-endcomments")))
3503 (verilog-re-search-backward reg nil 'move)
3507 (skip-chars-forward "^ \t")
3508 (verilog-forward-ws&directives)
3509 (if (and width (looking-at width))
3511 (goto-char (match-end 0))
3512 (verilog-forward-ws&directives)))
3515 (skip-chars-forward "a-zA-Z0-9_")
3517 (setq string (buffer-substring b e)))
3520 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
3522 (insert (concat " // " string )))
3525 (defun verilog-get-expr()
3526 "Grab expression at point, e.g, case ( a | b & (c ^d))."
3528 (verilog-forward-syntactic-ws)
3529 (skip-chars-forward " \t")
3535 (verilog-forward-syntactic-ws)
3536 (if (looking-at "(")
3539 (while (and (/= par 0)
3540 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3543 (setq par (1+ par)))
3545 (setq par (1- par)))))))
3549 (while (and (/= par 0)
3550 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
3553 (setq par (1+ par)))
3555 (setq par (1- par)))))
3559 (while (and (/= par 0)
3560 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
3563 (setq par (1+ par)))
3565 (setq par (1- par)))))
3566 (verilog-forward-syntactic-ws)
3567 (skip-chars-forward "^ \t\n\f")
3569 ((looking-at "/[/\\*]")
3572 (skip-chars-forward "^: \t\n\f")
3574 (str (buffer-substring b e)))
3575 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
3576 (setq str (concat (substring str 0 e) "...")))
3579 (defun verilog-expand-vector ()
3580 "Take a signal vector on the current line and expand it to multiple lines.
3581 Useful for creating tri's and other expanded fields."
3583 (verilog-expand-vector-internal "[" "]"))
3585 (defun verilog-expand-vector-internal (bra ket)
3586 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
3589 (let ((signal-string (buffer-substring (point)
3591 (end-of-line) (point)))))
3595 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
3597 "\\(.*\\)$") signal-string)
3598 (let* ((sig-head (match-string 1 signal-string))
3599 (vec-start (string-to-number (match-string 2 signal-string)))
3600 (vec-end (if (= (match-beginning 3) (match-end 3))
3603 (substring signal-string (1+ (match-beginning 3))
3606 (if (= (match-beginning 4) (match-end 4))
3609 (substring signal-string (+ 2 (match-beginning 4))
3611 (sig-tail (match-string 5 signal-string))
3616 (let ((tmp vec-start))
3617 (setq vec-start vec-end
3619 vec-range (- vec-range))))
3620 (if (< vec-end vec-start)
3621 (while (<= vec-end vec-start)
3622 (setq vec (append vec (list vec-start)))
3623 (setq vec-start (- vec-start vec-range)))
3624 (while (<= vec-start vec-end)
3625 (setq vec (append vec (list vec-start)))
3626 (setq vec-start (+ vec-start vec-range))))
3628 ;; Delete current line
3629 (delete-region (point) (progn (forward-line 0) (point)))
3633 (insert (concat sig-head bra
3634 (int-to-string (car vec)) ket sig-tail "\n"))
3635 (setq vec (cdr vec)))
3640 (defun verilog-strip-comments ()
3641 "Strip all comments from the Verilog code."
3643 (goto-char (point-min))
3644 (while (re-search-forward "//" nil t)
3645 (if (verilog-within-string)
3646 (re-search-forward "\"" nil t)
3647 (if (verilog-in-star-comment-p)
3648 (re-search-forward "\*/" nil t)
3649 (let ((bpt (- (point) 2)))
3651 (delete-region bpt (point))))))
3653 (goto-char (point-min))
3654 (while (re-search-forward "/\\*" nil t)
3655 (if (verilog-within-string)
3656 (re-search-forward "\"" nil t)
3657 (let ((bpt (- (point) 2)))
3658 (re-search-forward "\\*/")
3659 (delete-region bpt (point))))))
3661 (defun verilog-one-line ()
3662 "Convert structural Verilog instances to occupy one line."
3664 (goto-char (point-min))
3665 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
3666 (replace-match "\\1 " nil nil)))
3668 (defun verilog-linter-name ()
3669 "Return name of linter, either surelint or verilint."
3670 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3672 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
3674 (cond ((equal compile-word1 "surelint") `surelint)
3675 ((equal compile-word1 "verilint") `verilint)
3676 ((equal lint-word1 "surelint") `surelint)
3677 ((equal lint-word1 "verilint") `verilint)
3678 (t `surelint)))) ;; back compatibility
3680 (defun verilog-lint-off ()
3681 "Convert a Verilog linter warning line into a disable statement.
3683 pci_bfm_null.v, line 46: Unused input: pci_rst_
3684 becomes a comment for the appropriate tool.
3686 The first word of the `compile-command' or `verilog-linter'
3687 variables is used to determine which product is being used.
3689 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
3691 (let ((linter (verilog-linter-name)))
3692 (cond ((equal linter `surelint)
3693 (verilog-surelint-off))
3694 ((equal linter `verilint)
3695 (verilog-verilint-off))
3696 (t (error "Linter name not set")))))
3698 (defvar compilation-last-buffer)
3700 (defun verilog-surelint-off ()
3701 "Convert a SureLint warning line into a disable statement.
3702 Run from Verilog source window; assumes there is a *compile* buffer
3703 with point set appropriately.
3706 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
3708 // surefire lint_line_off UDDONX"
3710 (let ((buff (if (boundp 'next-error-last-buffer)
3711 next-error-last-buffer
3712 compilation-last-buffer)))
3713 (when (buffer-live-p buff)
3714 ;; FIXME with-current-buffer?
3716 (switch-to-buffer buff)
3719 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
3720 (let* ((code (match-string 2))
3721 (file (match-string 3))
3722 (line (match-string 4))
3723 (buffer (get-file-buffer file))
3728 (and (file-exists-p file)
3729 (find-file-noselect file)))
3731 (let* ((pop-up-windows t))
3732 (let ((name (expand-file-name
3734 (format "Find this error in: (default %s) "
3737 (if (file-directory-p name)
3738 (setq name (expand-file-name filename name)))
3740 (and (file-exists-p name)
3741 (find-file-noselect name))))))))
3742 (switch-to-buffer buffer)
3743 (goto-line (string-to-number line))
3747 ((verilog-in-slash-comment-p)
3748 (re-search-backward "//")
3750 ((looking-at "// surefire lint_off_line ")
3751 (goto-char (match-end 0))
3752 (let ((lim (save-excursion (end-of-line) (point))))
3753 (if (re-search-forward code lim 'move)
3755 (insert (concat " " code)))))
3758 ((verilog-in-star-comment-p)
3759 (re-search-backward "/\*")
3760 (insert (format " // surefire lint_off_line %6s" code )))
3762 (insert (format " // surefire lint_off_line %6s" code ))
3765 (defun verilog-verilint-off ()
3766 "Convert a Verilint warning line into a disable statement.
3769 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
3771 //Verilint 240 off // WARNING: Unused input"
3775 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
3776 (replace-match (format
3777 ;; %3s makes numbers 1-999 line up nicely
3778 "\\1//Verilint %3s off // WARNING: \\3"
3781 (verilog-indent-line))))
3783 (defun verilog-auto-save-compile ()
3784 "Update automatics with \\[verilog-auto], save the buffer, and compile."
3786 (verilog-auto) ; Always do it for safety
3788 (compile compile-command))
3796 (defmacro verilog-batch-error-wrapper (&rest body)
3797 "Execute BODY and add error prefix to any errors found.
3798 This lets programs calling batch mode to easily extract error messages."
3799 `(condition-case err
3802 (error "%%Error: %s%s" (error-message-string err)
3803 (if (featurep 'xemacs) "\n" ""))))) ;; XEmacs forgets to add a newline
3805 (defun verilog-batch-execute-func (funref)
3806 "Internal processing of a batch command, running FUNREF on all command arguments."
3807 (verilog-batch-error-wrapper
3808 ;; General globals needed
3809 (setq make-backup-files nil)
3810 (setq-default make-backup-files nil)
3811 (setq enable-local-variables t)
3812 (setq enable-local-eval t)
3813 ;; Make sure any sub-files we read get proper mode
3814 (setq default-major-mode `verilog-mode)
3815 ;; Ditto files already read in
3817 (when (buffer-file-name buf)
3822 ;; Process the files
3823 (mapcar '(lambda (buf)
3824 (when (buffer-file-name buf)
3826 (if (not (file-exists-p (buffer-file-name buf)))
3828 (concat "File not found: " (buffer-file-name buf))))
3829 (message (concat "Processing " (buffer-file-name buf)))
3835 (defun verilog-batch-auto ()
3836 "For use with --batch, perform automatic expansions as a stand-alone tool.
3837 This sets up the appropriate Verilog mode environment, updates automatics
3838 with \\[verilog-auto] on all command-line files, and saves the buffers.
3839 For proper results, multiple filenames need to be passed on the command
3840 line in bottom-up order."
3841 (unless noninteractive
3842 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3843 (verilog-batch-execute-func `verilog-auto))
3845 (defun verilog-batch-delete-auto ()
3846 "For use with --batch, perform automatic deletion as a stand-alone tool.
3847 This sets up the appropriate Verilog mode environment, deletes automatics
3848 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
3849 (unless noninteractive
3850 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3851 (verilog-batch-execute-func `verilog-delete-auto))
3853 (defun verilog-batch-inject-auto ()
3854 "For use with --batch, perform automatic injection as a stand-alone tool.
3855 This sets up the appropriate Verilog mode environment, injects new automatics
3856 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
3857 For proper results, multiple filenames need to be passed on the command
3858 line in bottom-up order."
3859 (unless noninteractive
3860 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
3861 (verilog-batch-execute-func `verilog-inject-auto))
3863 (defun verilog-batch-indent ()
3864 "For use with --batch, reindent an a entire file as a stand-alone tool.
3865 This sets up the appropriate Verilog mode environment, calls
3866 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
3867 (unless noninteractive
3868 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
3869 (verilog-batch-execute-func `verilog-indent-buffer))
3875 (defconst verilog-indent-alist
3876 '((block . (+ ind verilog-indent-level))
3877 (case . (+ ind verilog-case-indent))
3878 (cparenexp . (+ ind verilog-indent-level))
3879 (cexp . (+ ind verilog-cexp-indent))
3880 (defun . verilog-indent-level-module)
3881 (declaration . verilog-indent-level-declaration)
3882 (directive . (verilog-calculate-indent-directive))
3883 (tf . verilog-indent-level)
3884 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
3887 (comment . (verilog-comment-indent))
3891 (defun verilog-continued-line-1 (lim)
3892 "Return true if this is a continued line.
3893 Set point to where line starts. Limit search to point LIM."
3894 (let ((continued 't))
3895 (if (eq 0 (forward-line -1))
3898 (verilog-backward-ws&directives lim)
3900 (setq continued nil)
3901 (setq continued (verilog-backward-token))))
3902 (setq continued nil))
3905 (defun verilog-calculate-indent ()
3906 "Calculate the indent of the current Verilog line.
3907 Examine previous lines. Once a line is found that is definitive as to the
3908 type of the current line, return that lines' indent level and its type.
3909 Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
3911 (let* ((starting_position (point))
3913 (begin (looking-at "[ \t]*begin\\>"))
3914 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
3915 (type (catch 'nesting
3916 ;; Keep working backwards until we can figure out
3917 ;; what type of statement this is.
3918 ;; Basically we need to figure out
3919 ;; 1) if this is a continuation of the previous line;
3920 ;; 2) are we in a block scope (begin..end)
3922 ;; if we are in a comment, done.
3923 (if (verilog-in-star-comment-p)
3924 (throw 'nesting 'comment))
3926 ;; if we have a directive, done.
3927 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
3928 (throw 'nesting 'directive))
3930 ;; unless we are in the newfangled coverpoint or constraint blocks
3931 ;; if we are in a parenthesized list, and the user likes to indent these, return.
3933 verilog-indent-lists
3934 (not (verilog-in-coverage))
3937 (throw 'nesting 'block)))
3939 ;; See if we are continuing a previous line
3941 ;; trap out if we crawl off the top of the buffer
3942 (if (bobp) (throw 'nesting 'cpp))
3944 (if (verilog-continued-line-1 lim)
3947 (not (looking-at verilog-complete-reg))
3948 (verilog-continued-line-1 lim))
3949 (progn (goto-char sp)
3950 (throw 'nesting 'cexp))
3955 (not verilog-indent-begin-after-if)
3956 (looking-at verilog-no-indent-begin-re))
3959 (skip-chars-forward " \t")
3960 (throw 'nesting 'statement))
3962 (throw 'nesting 'cexp))))
3963 ;; not a continued line
3964 (goto-char starting_position))
3966 (if (looking-at "\\<else\\>")
3967 ;; search back for governing if, striding across begin..end pairs
3970 (while (verilog-re-search-backward verilog-ends-re nil 'move)
3972 ((match-end 1) ; else, we're in deep
3973 (setq elsec (1+ elsec)))
3975 (setq elsec (1- elsec))
3977 (if verilog-align-ifelse
3978 (throw 'nesting 'statement)
3979 (progn ;; back up to first word on this line
3981 (verilog-forward-syntactic-ws)
3982 (throw 'nesting 'statement)))))
3984 ; try to leap back to matching outward block by striding across
3985 ; indent level changing tokens then immediately
3986 ; previous line governs indentation.
3987 (let (( reg) (nest 1))
3988 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
3990 ((match-end 3) ; end
3991 ;; Search back for matching begin
3992 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
3993 ((match-end 4) ; endcase
3994 ;; Search back for matching case
3995 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
3996 ((match-end 5) ; endfunction
3997 ;; Search back for matching function
3998 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
3999 ((match-end 6) ; endtask
4000 ;; Search back for matching task
4001 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4002 ((match-end 7) ; endspecify
4003 ;; Search back for matching specify
4004 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4005 ((match-end 8) ; endtable
4006 ;; Search back for matching table
4007 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4008 ((match-end 9) ; endgenerate
4009 ;; Search back for matching generate
4010 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4011 ((match-end 10) ; joins
4012 ;; Search back for matching fork
4013 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
4014 ((match-end 11) ; class
4015 ;; Search back for matching class
4016 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4017 ((match-end 12) ; covergroup
4018 ;; Search back for matching covergroup
4019 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )))
4021 (while (verilog-re-search-backward reg nil 'move)
4023 ((match-end 1) ; begin
4024 (setq nest (1- nest))
4027 ((match-end 2) ; end
4028 (setq nest (1+ nest)))))
4030 (throw 'nesting (verilog-calc-1)))
4034 ;; Return type of block and indent level.
4037 (if (> par 0) ; Unclosed Parenthesis
4038 (list 'cparenexp par)
4041 (list type (verilog-case-indent-level)))
4042 ((eq type 'statement)
4043 (list type (current-column)))
4047 (list type (verilog-current-indent-level))))))))
4049 (defun verilog-wai ()
4050 "Show matching nesting block for debugging."
4053 (let ((nesting (verilog-calc-1)))
4054 (message "You are at nesting %s" nesting))))
4056 (defun verilog-calc-1 ()
4058 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
4060 ((equal (char-after) ?\{)
4061 (if (verilog-at-constraint-p)
4062 (throw 'nesting 'block)))
4063 ((equal (char-after) ?\})
4065 (let ((there (verilog-at-close-constraint-p)))
4066 (if there (goto-char there))))
4068 ((looking-at verilog-beg-block-re-ordered)
4070 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
4071 (let ((here (point)))
4072 (verilog-beg-of-statement)
4073 (if (looking-at verilog-extended-case-re)
4074 (throw 'nesting 'case)
4076 (throw 'nesting 'case))
4078 ((match-end 4) ; *sigh* could be "disable fork"
4079 (let ((here (point)))
4080 (verilog-beg-of-statement)
4081 (if (looking-at verilog-disable-fork-re)
4082 t ; is disable fork, this is a normal statement
4083 (progn ; or is fork, starts a new block
4085 (throw 'nesting 'block)))))
4088 ;; need to consider typedef struct here...
4089 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
4090 ; *sigh* These words have an optional prefix:
4091 ; extern {virtual|protected}? function a();
4092 ; assert property (p_1);
4093 ; typedef class foo;
4094 ; and we don't want to confuse this with
4099 (let ((here (point)))
4101 (verilog-beg-of-statement)
4102 (if (= (point) here)
4103 (throw 'nesting 'block)))))
4104 (t (throw 'nesting 'block))))
4106 ((looking-at verilog-end-block-re)
4107 (verilog-leap-to-head)
4108 (if (verilog-in-case-region-p)
4110 (verilog-leap-to-case-head)
4111 (if (looking-at verilog-case-re)
4112 (throw 'nesting 'case)))))
4114 ((looking-at (if (verilog-in-generate-region-p)
4115 verilog-defun-level-not-generate-re
4116 verilog-defun-level-re))
4117 (throw 'nesting 'defun))
4119 ((looking-at verilog-cpp-level-re)
4120 (throw 'nesting 'cpp))
4123 (throw 'nesting 'cpp))))
4124 (throw 'nesting 'cpp)))
4126 (defun verilog-calculate-indent-directive ()
4127 "Return indentation level for directive.
4128 For speed, the searcher looks at the last directive, not the indent
4129 of the appropriate enclosing block."
4130 (let ((base -1) ;; Indent of the line that determines our indentation
4131 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else)
4132 ;; Start at current location, scan back for another directive
4136 (while (and (< base 0)
4137 (verilog-re-search-backward verilog-directive-re nil t))
4138 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
4139 (setq base (current-indentation))))
4140 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
4141 (setq ind (- ind verilog-indent-level-directive)))
4142 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
4143 (setq ind (+ ind verilog-indent-level-directive)))
4144 ((looking-at verilog-directive-begin)
4145 (setq ind (+ ind verilog-indent-level-directive)))))
4146 ;; Adjust indent to starting indent of critical line
4147 (setq ind (max 0 (+ ind base))))
4151 (skip-chars-forward " \t")
4152 (cond ((or (looking-at verilog-directive-middle)
4153 (looking-at verilog-directive-end))
4154 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
4157 (defun verilog-leap-to-case-head ()
4160 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
4163 (setq nest (1- nest)))
4165 (setq nest (1+ nest)))
4170 (defun verilog-leap-to-head ()
4171 "Move point to the head of this block.
4172 Jump from end to matching begin, from endcase to matching case, and so on."
4177 ((looking-at "\\<end\\>")
4178 ;; 1: Search back for matching begin
4179 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
4180 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
4181 ((looking-at "\\<endcase\\>")
4182 ;; 2: Search back for matching case
4183 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
4184 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
4185 ;; 3: Search back for matching fork
4186 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4187 ((looking-at "\\<endclass\\>")
4188 ;; 4: Search back for matching class
4189 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
4190 ((looking-at "\\<endtable\\>")
4191 ;; 5: Search back for matching table
4192 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
4193 ((looking-at "\\<endspecify\\>")
4194 ;; 6: Search back for matching specify
4195 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
4196 ((looking-at "\\<endfunction\\>")
4197 ;; 7: Search back for matching function
4198 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
4199 ((looking-at "\\<endgenerate\\>")
4200 ;; 8: Search back for matching generate
4201 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
4202 ((looking-at "\\<endtask\\>")
4203 ;; 9: Search back for matching task
4204 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
4205 ((looking-at "\\<endgroup\\>")
4206 ;; 10: Search back for matching covergroup
4207 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
4208 ((looking-at "\\<endproperty\\>")
4209 ;; 11: Search back for matching property
4210 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
4211 ((looking-at "\\<endinterface\\>")
4212 ;; 12: Search back for matching interface
4213 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
4214 ((looking-at "\\<endsequence\\>")
4215 ;; 12: Search back for matching sequence
4216 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
4217 ((looking-at "\\<endclocking\\>")
4218 ;; 12: Search back for matching clocking
4219 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" )))
4223 (while (verilog-re-search-backward reg nil 'move)
4225 ((match-end 1) ; begin
4226 (setq nest (1- nest))
4228 ;; Now previous line describes syntax
4233 ((match-end 2) ; end
4234 (setq nest (1+ nest)))
4236 ;; endcase, jump to case
4238 (setq nest (1+ nest))
4240 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
4242 ;; join, jump to fork
4244 (setq nest (1+ nest))
4246 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
4249 (defun verilog-continued-line ()
4250 "Return true if this is a continued line.
4251 Set point to where line starts."
4252 (let ((continued 't))
4253 (if (eq 0 (forward-line -1))
4256 (verilog-backward-ws&directives)
4258 (setq continued nil)
4259 (while (and continued
4261 (skip-chars-backward " \t")
4263 (setq continued (verilog-backward-token)))))
4264 (setq continued nil))
4267 (defun verilog-backward-token ()
4268 "Step backward token, returning true if we are now at an end of line token."
4270 (verilog-backward-syntactic-ws)
4274 (;-- Anything ending in a ; is complete
4275 (= (preceding-char) ?\;)
4277 (; If a "}" is prefixed by a ";", then this is a complete statement
4278 ; i.e.: constraint foo { a = b; }
4279 (= (preceding-char) ?\})
4282 (verilog-at-close-constraint-p)))
4283 (;-- constraint foo { a = b }
4284 ; is a complete statement. *sigh*
4285 (= (preceding-char) ?\{)
4288 (not (verilog-at-constraint-p))))
4289 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
4290 ; also could be simply '@(foo)'
4292 ; (b, ... which ISN'T complete
4293 ;;;; Do we need this???
4294 (= (preceding-char) ?\))
4297 (backward-up-list 1)
4298 (verilog-backward-syntactic-ws)
4299 (let ((back (point)))
4302 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
4303 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
4307 ((= (preceding-char) ?\@)
4310 (verilog-backward-token)
4311 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
4312 ((= (preceding-char) ?\#)
4316 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
4320 ((looking-at "\\<else\\>")
4322 ((looking-at verilog-behavioral-block-beg-re)
4324 ((looking-at verilog-indent-re)
4329 (verilog-backward-syntactic-ws)
4331 ((= (preceding-char) ?\:)
4333 (verilog-backward-syntactic-ws)
4335 (if (looking-at verilog-nameable-item-re )
4338 ((= (preceding-char) ?\#)
4341 ((= (preceding-char) ?\`)
4349 (defun verilog-backward-syntactic-ws (&optional bound)
4350 "Backward skip over syntactic whitespace for Emacs 19.
4351 Optional BOUND limits search."
4353 (let* ((bound (or bound (point-min))) (here bound) )
4354 (if (< bound (point))
4356 (narrow-to-region bound (point))
4357 (while (/= here (point))
4359 (verilog-skip-backward-comments))))))
4362 (defun verilog-forward-syntactic-ws (&optional bound)
4363 "Forward skip over syntactic whitespace for Emacs 19.
4364 Optional BOUND limits search."
4366 (let* ((bound (or bound (point-max)))
4368 (if (> bound (point))
4370 (narrow-to-region (point) bound)
4371 (while (/= here (point))
4373 (forward-comment (buffer-size))))))))
4375 (defun verilog-backward-ws&directives (&optional bound)
4376 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
4377 Optional BOUND limits search."
4379 (let* ((bound (or bound (point-min)))
4382 (if (< bound (point))
4384 (let ((state (save-excursion (verilog-syntax-ppss))))
4386 ((nth 7 state) ;; in // comment
4387 (verilog-re-search-backward "//" nil 'move)
4388 (skip-chars-backward "/"))
4389 ((nth 4 state) ;; in /* */ comment
4390 (verilog-re-search-backward "/\*" nil 'move))))
4391 (narrow-to-region bound (point))
4392 (while (/= here (point))
4394 (verilog-skip-backward-comments)
4399 ((verilog-within-translate-off)
4400 (verilog-back-to-start-translate-off (point-min)))
4401 ((looking-at verilog-directive-re-1)
4405 (if p (goto-char p))))))))
4407 (defun verilog-forward-ws&directives (&optional bound)
4408 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
4409 Optional BOUND limits search."
4411 (let* ((bound (or bound (point-max)))
4414 (if (> bound (point))
4416 (let ((state (save-excursion (verilog-syntax-ppss))))
4418 ((nth 7 state) ;; in // comment
4419 (verilog-re-search-forward "//" nil 'move))
4420 ((nth 4 state) ;; in /* */ comment
4421 (verilog-re-search-forward "/\*" nil 'move))))
4422 (narrow-to-region (point) bound)
4423 (while (/= here (point))
4426 (forward-comment (buffer-size))
4429 (if (looking-at verilog-directive-re-1)
4432 (beginning-of-line 2))))))))
4434 (defun verilog-in-comment-p ()
4435 "Return true if in a star or // comment."
4436 (let ((state (save-excursion (verilog-syntax-ppss))))
4437 (or (nth 4 state) (nth 7 state))))
4439 (defun verilog-in-star-comment-p ()
4440 "Return true if in a star comment."
4441 (let ((state (save-excursion (verilog-syntax-ppss))))
4443 (nth 4 state) ; t if in a comment of style a // or b /**/
4445 (nth 7 state) ; t if in a comment of style b /**/
4448 (defun verilog-in-slash-comment-p ()
4449 "Return true if in a slash comment."
4450 (let ((state (save-excursion (verilog-syntax-ppss))))
4453 (defun verilog-in-comment-or-string-p ()
4454 "Return true if in a string or comment."
4455 (let ((state (save-excursion (verilog-syntax-ppss))))
4456 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
4458 (defun verilog-in-escaped-name-p ()
4459 "Return true if in an escaped name."
4462 (skip-chars-backward "^ \t\n\f")
4463 (if (equal (char-after (point) ) ?\\ )
4467 (defun verilog-in-paren ()
4468 "Return true if in a parenthetical expression."
4469 (let ((state (save-excursion (verilog-syntax-ppss))))
4470 (> (nth 0 state) 0 )))
4472 (defun verilog-in-coverage ()
4473 "Return true if in a constraint or coverpoint expression."
4476 (if (verilog-in-paren)
4478 (backward-up-list 1)
4479 (verilog-at-constraint-p)
4482 (defun verilog-at-close-constraint-p ()
4483 "If at the } that closes a constraint or covergroup, return true."
4485 (equal (char-after) ?\})
4489 (verilog-backward-ws&directives)
4490 (if (equal (char-before) ?\;)
4494 (defun verilog-at-constraint-p ()
4495 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
4498 (equal (char-after) ?\{)
4500 (progn (backward-char 1)
4501 (verilog-backward-ws&directives)
4502 (equal (char-before) ?\;))))
4504 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
4508 (defun verilog-parenthesis-depth ()
4509 "Return non zero if in parenthetical-expression."
4510 (save-excursion (nth 1 (verilog-syntax-ppss))))
4513 (defun verilog-skip-forward-comment-or-string ()
4514 "Return true if in a string or comment."
4515 (let ((state (save-excursion (verilog-syntax-ppss))))
4517 ((nth 3 state) ;Inside string
4518 (search-forward "\"")
4520 ((nth 7 state) ;Inside // comment
4523 ((nth 4 state) ;Inside any comment (hence /**/)
4524 (search-forward "*/"))
4528 (defun verilog-skip-backward-comment-or-string ()
4529 "Return true if in a string or comment."
4530 (let ((state (save-excursion (verilog-syntax-ppss))))
4532 ((nth 3 state) ;Inside string
4533 (search-backward "\"")
4535 ((nth 7 state) ;Inside // comment
4536 (search-backward "//")
4537 (skip-chars-backward "/")
4539 ((nth 4 state) ;Inside /* */ comment
4540 (search-backward "/*")
4545 (defun verilog-skip-backward-comments ()
4546 "Return true if a comment was skipped."
4550 (let ((state (save-excursion (verilog-syntax-ppss))))
4552 ((nth 7 state) ;Inside // comment
4553 (search-backward "//")
4554 (skip-chars-backward "/")
4555 (skip-chars-backward " \t\n\f")
4557 ((nth 4 state) ;Inside /* */ comment
4558 (search-backward "/*")
4559 (skip-chars-backward " \t\n\f")
4562 (= (char-before) ?\/)
4563 (= (char-before (1- (point))) ?\*))
4564 (goto-char (- (point) 2))
4567 (skip-chars-backward " \t\n\f")
4570 (defun verilog-skip-forward-comment-p ()
4571 "If in comment, move to end and return true."
4574 (setq state (save-excursion (verilog-syntax-ppss)))
4578 ((nth 7 state) ;Inside // comment
4582 ((nth 4 state) ;Inside any comment
4587 (defun verilog-indent-line-relative ()
4588 "Cheap version of indent line.
4589 Only look at a few lines to determine indent level."
4593 (if (looking-at "^[ \t]*$")
4594 (cond ;- A blank line; No need to be too smart.
4596 (setq indent-str (list 'cpp 0)))
4597 ((verilog-continued-line)
4598 (let ((sp1 (point)))
4599 (if (verilog-continued-line)
4603 (list 'statement (verilog-current-indent-level))))
4605 (setq indent-str (list 'block (verilog-current-indent-level)))))
4608 (setq indent-str (verilog-calculate-indent))))
4609 (progn (skip-chars-forward " \t")
4610 (setq indent-str (verilog-calculate-indent))))
4611 (verilog-do-indent indent-str)))
4613 (defun verilog-indent-line ()
4614 "Indent for special part of code."
4615 (verilog-do-indent (verilog-calculate-indent)))
4617 (defun verilog-do-indent (indent-str)
4618 (let ((type (car indent-str))
4619 (ind (car (cdr indent-str))))
4621 (; handle continued exp
4623 (let ((here (point)))
4624 (verilog-backward-syntactic-ws)
4627 (= (preceding-char) ?\,)
4628 (= (preceding-char) ?\])
4630 (verilog-beg-of-statement-1)
4631 (looking-at verilog-declaration-re)))
4636 (verilog-beg-of-statement-1)
4638 (if (looking-at verilog-declaration-re)
4639 (progn ;; we have multiple words
4640 (goto-char (match-end 0))
4641 (skip-chars-forward " \t")
4643 ((and verilog-indent-declaration-macros
4644 (= (following-char) ?\`))
4648 (skip-chars-forward " \t")))
4649 ((= (following-char) ?\[)
4652 (backward-up-list -1)
4653 (skip-chars-forward " \t"))))
4657 (+ (current-column) verilog-cexp-indent))))))
4659 (indent-line-to val)))
4660 ((= (preceding-char) ?\) )
4662 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4663 (indent-line-to val)))
4667 (verilog-beg-of-statement-1)
4668 (if (and (< (point) here)
4669 (verilog-re-search-forward "=[ \\t]*" here 'move))
4670 (setq val (current-column))
4671 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
4673 (indent-line-to val))))))
4675 (; handle inside parenthetical expressions
4676 (eq type 'cparenexp)
4677 (let ((val (save-excursion
4678 (backward-up-list 1)
4680 (skip-chars-forward " \t")
4682 (indent-line-to val)
4683 (if (and (not (verilog-in-struct-region-p))
4684 (looking-at verilog-declaration-re))
4685 (verilog-indent-declaration ind))))
4687 (;-- Handle the ends
4689 (looking-at verilog-end-block-re )
4690 (verilog-at-close-constraint-p))
4691 (let ((val (if (eq type 'statement)
4692 (- ind verilog-indent-level)
4694 (indent-line-to val)))
4696 (;-- Case -- maybe line 'em up
4697 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
4700 ((looking-at "\\<endcase\\>")
4701 (indent-line-to ind))
4703 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4704 (indent-line-to val))))))
4707 (and (eq type 'defun)
4708 (looking-at verilog-zero-indent-re))
4715 (looking-at verilog-declaration-re))
4716 (verilog-indent-declaration ind))
4718 (;-- Everything else
4720 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
4721 (indent-line-to val))))
4723 (if (looking-at "[ \t]+$")
4724 (skip-chars-forward " \t"))
4725 indent-str ; Return indent data
4728 (defun verilog-current-indent-level ()
4729 "Return the indent-level of the current statement."
4733 (setq par-pos (verilog-parenthesis-depth))
4737 (setq par-pos (verilog-parenthesis-depth)))
4738 (skip-chars-forward " \t")
4741 (defun verilog-case-indent-level ()
4742 "Return the indent-level of the current statement.
4743 Do not count named blocks or case-statements."
4745 (skip-chars-forward " \t")
4747 ((looking-at verilog-named-block-re)
4749 ((and (not (looking-at verilog-case-re))
4750 (looking-at "^[^:;]+[ \t]*:"))
4751 (verilog-re-search-forward ":" nil t)
4752 (skip-chars-forward " \t")
4755 (current-column)))))
4757 (defun verilog-indent-comment ()
4758 "Indent current line as comment."
4761 ((verilog-in-star-comment-p)
4763 (re-search-backward "/\\*" nil t)
4764 (1+(current-column))))
4769 (re-search-backward "//" nil t)
4770 (current-column))))))
4771 (indent-line-to stcol)
4774 (defun verilog-more-comment ()
4775 "Make more comment lines like the previous."
4779 ((verilog-in-star-comment-p)
4782 (re-search-backward "/\\*" nil t)
4783 (1+(current-column))))
4788 (re-search-backward "//" nil t)
4789 (current-column))))))
4795 (skip-chars-forward " \t")
4799 (defun verilog-comment-indent (&optional arg)
4800 "Return the column number the line should be indented to.
4801 ARG is ignored, for `comment-indent-function' compatibility."
4803 ((verilog-in-star-comment-p)
4805 (re-search-backward "/\\*" nil t)
4806 (1+(current-column))))
4811 (re-search-backward "//" nil t)
4812 (current-column)))))
4816 (defun verilog-pretty-declarations (&optional quiet)
4817 "Line up declarations around point."
4821 (verilog-beg-of-statement-1)
4822 (looking-at verilog-declaration-re))
4823 (let* ((m1 (make-marker))
4826 ;; Start of declaration range
4829 (verilog-beg-of-statement-1)
4830 (while (looking-at verilog-declaration-re)
4833 (verilog-backward-syntactic-ws)
4835 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
4837 ;; End of declaration range
4841 (verilog-end-of-statement)
4842 (setq e (point)) ;Might be on last line
4843 (verilog-forward-syntactic-ws)
4844 (while (looking-at verilog-declaration-re)
4846 (verilog-end-of-statement)
4848 (verilog-forward-syntactic-ws))
4850 (edpos (set-marker (make-marker) end))
4855 (verilog-do-indent (verilog-calculate-indent))
4856 (verilog-forward-ws&directives)
4860 (if (and (not quiet)
4861 (> (- end start) 100))
4862 (message "Lining up declarations..(please stand by)"))
4863 ;; Get the beginning of line indent first
4864 (while (progn (setq e (marker-position edpos))
4867 ( (save-excursion (skip-chars-backward " \t")
4869 (verilog-forward-ws&directives)
4870 (indent-line-to base-ind)
4871 (verilog-forward-ws&directives)
4872 (verilog-re-search-forward "[ \t\n\f]" e 'move))
4875 (verilog-re-search-forward "[ \t\n\f]" e 'move)))
4878 ;; Now find biggest prefix
4879 (setq ind (verilog-get-lineup-indent start edpos))
4880 ;; Now indent each line.
4882 (while (progn (setq e (marker-position edpos))
4883 (setq r (- e (point)))
4886 (unless quiet (message "%d" r))
4888 ((or (and verilog-indent-declaration-macros
4889 (looking-at verilog-declaration-re-1-macro))
4890 (looking-at verilog-declaration-re-1-no-macro))
4891 (let ((p (match-end 0)))
4893 (if (verilog-re-search-forward "[[#`]" p 'move)
4897 (goto-char (marker-position m1))
4903 ((verilog-continued-line-1 start)
4905 (indent-line-to ind))
4906 (t ; Must be comment or white space
4908 (verilog-forward-ws&directives)
4911 (unless quiet (message ""))))))
4913 (defun verilog-pretty-expr (&optional quiet myre)
4914 "Line up expressions around point, or optional regexp MYRE."
4915 (interactive "sRegular Expression: ((<|:)?=) ")
4917 (if (or (eq myre nil)
4918 (string-equal myre ""))
4919 (setq myre "\\(<\\|:\\)?="))
4920 (setq myre (concat "\\(^[^;#:<=>]*\\)\\(" myre "\\)"))
4921 (let ((rexp(concat "^\\s-*" verilog-complete-reg)))
4923 (if (and (not (looking-at rexp ))
4925 (let* ((here (point))
4931 (verilog-backward-syntactic-ws)
4933 (while (and (not (looking-at rexp ))
4938 (verilog-backward-syntactic-ws)
4940 ) ;Ack, need to grok `define
4946 (setq e (point)) ;Might be on last line
4947 (verilog-forward-syntactic-ws)
4949 (while (and (not (looking-at rexp ))
4953 (verilog-forward-syntactic-ws)
4957 (edpos (set-marker (make-marker) end))
4961 (verilog-do-indent (verilog-calculate-indent))
4962 (if (and (not quiet)
4963 (> (- end start) 100))
4964 (message "Lining up expressions..(please stand by)"))
4966 ;; Set indent to minimum throughout region
4967 (while (< (point) (marker-position edpos))
4969 (verilog-just-one-space myre)
4971 (verilog-forward-syntactic-ws)
4974 ;; Now find biggest prefix
4975 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
4977 ;; Now indent each line.
4979 (while (progn (setq e (marker-position edpos))
4980 (setq r (- e (point)))
4983 (if (not quiet) (message "%d" r))
4986 (goto-char (match-end 1))
4987 (if (not (verilog-parenthesis-depth)) ;; ignore parenthsized exprs
4988 (if (eq (char-after) ?=)
4989 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
4992 ((verilog-continued-line-1 start)
4994 (indent-line-to ind))
4995 (t ; Must be comment or white space
4997 (verilog-forward-ws&directives)
5001 (unless quiet (message ""))
5004 (defun verilog-just-one-space (myre)
5005 "Remove extra spaces around regular expression MYRE."
5007 (if (and (not(looking-at verilog-complete-reg))
5009 (let ((p1 (match-end 1))
5013 (if (looking-at "\\s-") (just-one-space))
5016 (if (looking-at "\\s-") (just-one-space))
5019 (defun verilog-indent-declaration (baseind)
5020 "Indent current lines as declaration.
5021 Line up the variable names based on previous declaration's indentation.
5022 BASEIND is the base indent to offset everything."
5024 (let ((pos (point-marker))
5025 (lim (save-excursion
5026 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
5027 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
5033 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5034 (indent-line-to val)
5036 ;; Use previous declaration (in this module) as template.
5037 (if (or (memq 'all verilog-auto-lineup)
5038 (memq 'declaration verilog-auto-lineup))
5039 (if (verilog-re-search-backward
5040 (or (and verilog-indent-declaration-macros
5041 verilog-declaration-re-1-macro)
5042 verilog-declaration-re-1-no-macro) lim t)
5044 (goto-char (match-end 0))
5045 (skip-chars-forward " \t")
5046 (setq ind (current-column))
5050 (eval (cdr (assoc 'declaration verilog-indent-alist)))))
5051 (indent-line-to val)
5052 (if (and verilog-indent-declaration-macros
5053 (looking-at verilog-declaration-re-2-macro))
5054 (let ((p (match-end 0)))
5056 (if (verilog-re-search-forward "[[#`]" p 'move)
5060 (goto-char (marker-position m1))
5063 (if (/= (current-column) ind)
5067 (if (looking-at verilog-declaration-re-2-no-macro)
5068 (let ((p (match-end 0)))
5070 (if (verilog-re-search-forward "[[`#]" p 'move)
5074 (goto-char (marker-position m1))
5077 (if (/= (current-column) ind)
5080 (indent-to ind))))))))))
5083 (defun verilog-get-lineup-indent (b edpos)
5084 "Return the indent level that will line up several lines within the region.
5085 Region is defined by B and EDPOS."
5089 ;; Get rightmost position
5090 (while (progn (setq e (marker-position edpos))
5092 (if (verilog-re-search-forward
5093 (or (and verilog-indent-declaration-macros
5094 verilog-declaration-re-1-macro)
5095 verilog-declaration-re-1-no-macro) e 'move)
5097 (goto-char (match-end 0))
5098 (verilog-backward-syntactic-ws)
5099 (if (> (current-column) ind)
5100 (setq ind (current-column)))
5101 (goto-char (match-end 0)))))
5104 ;; No lineup-string found
5107 (skip-chars-backward " \t")
5108 (1+ (current-column))))))
5110 (defun verilog-get-lineup-indent-2 (myre b edpos)
5111 "Return the indent level that will line up several lines within the region."
5115 ;; Get rightmost position
5116 (while (progn (setq e (marker-position edpos))
5118 (if (and (verilog-re-search-forward myre e 'move)
5119 (not (verilog-parenthesis-depth))) ;; skip parenthsized exprs
5121 (goto-char (match-beginning 2))
5122 (verilog-backward-syntactic-ws)
5123 (if (> (current-column) ind)
5124 (setq ind (current-column)))
5125 (goto-char (match-end 0)))
5129 ;; No lineup-string found
5132 (skip-chars-backward " \t")
5133 (1+ (current-column))))))
5135 (defun verilog-comment-depth (type val)
5136 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
5144 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
5146 (replace-match " /* -# ## */")
5150 (insert " /* ## ## */"))))
5153 (format "%s %d" type val))))
5159 (defvar verilog-str nil)
5160 (defvar verilog-all nil)
5161 (defvar verilog-pred nil)
5162 (defvar verilog-buffer-to-use nil)
5163 (defvar verilog-flag nil)
5164 (defvar verilog-toggle-completions nil
5165 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
5166 Repeated use of \\[verilog-complete-word] will show you all of them.
5167 Normally, when there is more than one possible completion,
5168 it displays a list of all possible completions.")
5171 (defvar verilog-type-keywords
5173 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
5174 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
5175 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
5176 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
5177 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
5178 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
5180 "*Keywords for types used when completing a word in a declaration or parmlist.
5181 \(Eg. integer, real, reg...)")
5183 (defvar verilog-cpp-keywords
5184 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
5186 "*Keywords to complete when at first word of a line in declarative scope.
5187 \(Eg. initial, always, begin, assign.)
5188 The procedures and variables defined within the Verilog program
5189 will be completed at runtime and should not be added to this list.")
5191 (defvar verilog-defun-keywords
5194 "always" "always_comb" "always_ff" "always_latch" "assign"
5195 "begin" "end" "generate" "endgenerate" "module" "endmodule"
5196 "specify" "endspecify" "function" "endfunction" "initial" "final"
5197 "task" "endtask" "primitive" "endprimitive"
5199 verilog-type-keywords)
5200 "*Keywords to complete when at first word of a line in declarative scope.
5201 \(Eg. initial, always, begin, assign.)
5202 The procedures and variables defined within the Verilog program
5203 will be completed at runtime and should not be added to this list.")
5205 (defvar verilog-block-keywords
5207 "begin" "break" "case" "continue" "else" "end" "endfunction"
5208 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
5209 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
5211 "*Keywords to complete when at first word of a line in behavioral scope.
5212 \(Eg. begin, if, then, else, for, fork.)
5213 The procedures and variables defined within the Verilog program
5214 will be completed at runtime and should not be added to this list.")
5216 (defvar verilog-tf-keywords
5217 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
5218 "*Keywords to complete when at first word of a line in a task or function.
5219 \(Eg. begin, if, then, else, for, fork.)
5220 The procedures and variables defined within the Verilog program
5221 will be completed at runtime and should not be added to this list.")
5223 (defvar verilog-case-keywords
5224 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
5225 "*Keywords to complete when at first word of a line in case scope.
5226 \(Eg. begin, if, then, else, for, fork.)
5227 The procedures and variables defined within the Verilog program
5228 will be completed at runtime and should not be added to this list.")
5230 (defvar verilog-separator-keywords
5231 '("else" "then" "begin")
5232 "*Keywords to complete when NOT standing at the first word of a statement.
5234 Variables and function names defined within the Verilog program
5235 will be completed at runtime and should not be added to this list.")
5237 (defun verilog-string-diff (str1 str2)
5238 "Return index of first letter where STR1 and STR2 differs."
5242 (if (or (> (1+ diff) (length str1))
5243 (> (1+ diff) (length str2)))
5245 (or (equal (aref str1 diff) (aref str2 diff))
5247 (setq diff (1+ diff))))))
5249 ;; Calculate all possible completions for functions if argument is `function',
5250 ;; completions for procedures if argument is `procedure' or both functions and
5251 ;; procedures otherwise.
5253 (defun verilog-func-completion (type)
5254 "Build regular expression for module/task/function names.
5255 TYPE is 'module, 'tf for task or function, or t if unknown."
5256 (if (string= verilog-str "")
5257 (setq verilog-str "[a-zA-Z_]"))
5258 (let ((verilog-str (concat (cond
5259 ((eq type 'module) "\\<\\(module\\)\\s +")
5260 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
5261 (t "\\<\\(task\\|function\\|module\\)\\s +"))
5262 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
5265 (if (not (looking-at verilog-defun-re))
5266 (verilog-re-search-backward verilog-defun-re nil t))
5269 ;; Search through all reachable functions
5270 (goto-char (point-min))
5271 (while (verilog-re-search-forward verilog-str (point-max) t)
5272 (progn (setq match (buffer-substring (match-beginning 2)
5274 (if (or (null verilog-pred)
5275 (funcall verilog-pred match))
5276 (setq verilog-all (cons match verilog-all)))))
5277 (if (match-beginning 0)
5278 (goto-char (match-beginning 0)))))
5280 (defun verilog-get-completion-decl (end)
5281 "Macro for searching through current declaration (var, type or const)
5282 for matches of `str' and adding the occurrence tp `all' through point END."
5283 (let ((re (or (and verilog-indent-declaration-macros
5284 verilog-declaration-re-2-macro)
5285 verilog-declaration-re-2-no-macro))
5288 (while (and (< (point) end)
5289 (verilog-re-search-forward re end t))
5290 ;; Traverse current line
5291 (setq decl-end (save-excursion (verilog-declaration-end)))
5292 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
5293 (not (match-end 1)))
5294 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
5295 (if (string-match (concat "\\<" verilog-str) match)
5296 (if (or (null verilog-pred)
5297 (funcall verilog-pred match))
5298 (setq verilog-all (cons match verilog-all)))))
5302 (defun verilog-type-completion ()
5303 "Calculate all possible completions for types."
5304 (let ((start (point))
5306 ;; Search for all reachable type declarations
5307 (while (or (verilog-beg-of-defun)
5308 (setq goon (not goon)))
5310 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
5313 (verilog-re-search-forward
5314 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
5316 (not (match-end 1)))
5317 ;; Check current type declaration
5318 (verilog-get-completion-decl start))))))
5320 (defun verilog-var-completion ()
5321 "Calculate all possible completions for variables (or constants)."
5322 (let ((start (point)))
5323 ;; Search for all reachable var declarations
5324 (verilog-beg-of-defun)
5326 ;; Check var declarations
5327 (verilog-get-completion-decl start))))
5329 (defun verilog-keyword-completion (keyword-list)
5330 "Give list of all possible completions of keywords in KEYWORD-LIST."
5331 (mapcar '(lambda (s)
5332 (if (string-match (concat "\\<" verilog-str) s)
5333 (if (or (null verilog-pred)
5334 (funcall verilog-pred s))
5335 (setq verilog-all (cons s verilog-all)))))
5339 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
5340 "Function passed to `completing-read', `try-completion' or `all-completions'.
5341 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
5342 must be a function to be called for every match to check if this should
5343 really be a match. If VERILOG-FLAG is t, the function returns a list of
5344 all possible completions. If VERILOG-FLAG is nil it returns a string,
5345 the longest possible completion, or t if VERILOG-STR is an exact match.
5346 If VERILOG-FLAG is 'lambda, the function returns t if VERILOG-STR is an
5347 exact match, nil otherwise."
5349 (let ((verilog-all nil))
5350 ;; Set buffer to use for searching labels. This should be set
5351 ;; within functions which use verilog-completions
5352 (set-buffer verilog-buffer-to-use)
5354 ;; Determine what should be completed
5355 (let ((state (car (verilog-calculate-indent))))
5356 (cond ((eq state 'defun)
5357 (save-excursion (verilog-var-completion))
5358 (verilog-func-completion 'module)
5359 (verilog-keyword-completion verilog-defun-keywords))
5361 ((eq state 'behavioral)
5362 (save-excursion (verilog-var-completion))
5363 (verilog-func-completion 'module)
5364 (verilog-keyword-completion verilog-defun-keywords))
5367 (save-excursion (verilog-var-completion))
5368 (verilog-func-completion 'tf)
5369 (verilog-keyword-completion verilog-block-keywords))
5372 (save-excursion (verilog-var-completion))
5373 (verilog-func-completion 'tf)
5374 (verilog-keyword-completion verilog-case-keywords))
5377 (save-excursion (verilog-var-completion))
5378 (verilog-func-completion 'tf)
5379 (verilog-keyword-completion verilog-tf-keywords))
5382 (save-excursion (verilog-var-completion))
5383 (verilog-keyword-completion verilog-cpp-keywords))
5385 ((eq state 'cparenexp)
5386 (save-excursion (verilog-var-completion)))
5389 (save-excursion (verilog-var-completion))
5390 (verilog-func-completion 'both)
5391 (verilog-keyword-completion verilog-separator-keywords))))
5393 ;; Now we have built a list of all matches. Give response to caller
5394 (verilog-completion-response))))
5396 (defun verilog-completion-response ()
5397 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
5398 ;; This was not called by all-completions
5399 (if (null verilog-all)
5400 ;; Return nil if there was no matching label
5402 ;; Get longest string common in the labels
5403 (let* ((elm (cdr verilog-all))
5404 (match (car verilog-all))
5405 (min (length match))
5407 (if (string= match verilog-str)
5408 ;; Return t if first match was an exact match
5410 (while (not (null elm))
5411 ;; Find longest common string
5412 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
5415 (setq match (substring match 0 min))))
5416 ;; Terminate with match=t if this is an exact match
5417 (if (string= (car elm) verilog-str)
5421 (setq elm (cdr elm)))))
5422 ;; If this is a test just for exact match, return nil ot t
5423 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
5426 ;; If flag is t, this was called by all-completions. Return
5427 ;; list of all possible completions
5431 (defvar verilog-last-word-numb 0)
5432 (defvar verilog-last-word-shown nil)
5433 (defvar verilog-last-completions nil)
5435 (defun verilog-complete-word ()
5436 "Complete word at current point.
5437 \(See also `verilog-toggle-completions', `verilog-type-keywords',
5438 and `verilog-separator-keywords'.)"
5440 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5441 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5442 (verilog-str (buffer-substring b e))
5443 ;; The following variable is used in verilog-completion
5444 (verilog-buffer-to-use (current-buffer))
5445 (allcomp (if (and verilog-toggle-completions
5446 (string= verilog-last-word-shown verilog-str))
5447 verilog-last-completions
5448 (all-completions verilog-str 'verilog-completion)))
5449 (match (if verilog-toggle-completions
5451 verilog-str (mapcar '(lambda (elm)
5452 (cons elm 0)) allcomp)))))
5453 ;; Delete old string
5456 ;; Toggle-completions inserts whole labels
5457 (if verilog-toggle-completions
5459 ;; Update entry number in list
5460 (setq verilog-last-completions allcomp
5461 verilog-last-word-numb
5462 (if (>= verilog-last-word-numb (1- (length allcomp)))
5464 (1+ verilog-last-word-numb)))
5465 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
5466 ;; Display next match or same string if no match was found
5467 (if (not (null allcomp))
5468 (insert "" verilog-last-word-shown)
5469 (insert "" verilog-str)
5470 (message "(No match)")))
5471 ;; The other form of completion does not necessarily do that.
5473 ;; Insert match if found, or the original string if no match
5474 (if (or (null match) (equal match 't))
5475 (progn (insert "" verilog-str)
5476 (message "(No match)"))
5478 ;; Give message about current status of completion
5479 (cond ((equal match 't)
5480 (if (not (null (cdr allcomp)))
5481 (message "(Complete but not unique)")
5482 (message "(Sole completion)")))
5483 ;; Display buffer if the current completion didn't help
5484 ;; on completing the label.
5485 ((and (not (null (cdr allcomp))) (= (length verilog-str)
5487 (with-output-to-temp-buffer "*Completions*"
5488 (display-completion-list allcomp))
5489 ;; Wait for a key press. Then delete *Completion* window
5490 (momentary-string-display "" (point))
5491 (delete-window (get-buffer-window (get-buffer "*Completions*")))
5494 (defun verilog-show-completions ()
5495 "Show all possible completions at current point."
5497 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
5498 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
5499 (verilog-str (buffer-substring b e))
5500 ;; The following variable is used in verilog-completion
5501 (verilog-buffer-to-use (current-buffer))
5502 (allcomp (if (and verilog-toggle-completions
5503 (string= verilog-last-word-shown verilog-str))
5504 verilog-last-completions
5505 (all-completions verilog-str 'verilog-completion))))
5506 ;; Show possible completions in a temporary buffer.
5507 (with-output-to-temp-buffer "*Completions*"
5508 (display-completion-list allcomp))
5509 ;; Wait for a key press. Then delete *Completion* window
5510 (momentary-string-display "" (point))
5511 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
5514 (defun verilog-get-default-symbol ()
5515 "Return symbol around current point as a string."
5517 (buffer-substring (progn
5518 (skip-chars-backward " \t")
5519 (skip-chars-backward "a-zA-Z0-9_")
5522 (skip-chars-forward "a-zA-Z0-9_")
5525 (defun verilog-build-defun-re (str &optional arg)
5526 "Return function/task/module starting with STR as regular expression.
5527 With optional second ARG non-nil, STR is the complete name of the instruction."
5529 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
5530 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
5532 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
5533 "Function passed to `completing-read', `try-completion' or `all-completions'.
5534 Returns a completion on any function name based on VERILOG-STR prefix. If
5535 VERILOG-PRED is non-nil, it must be a function to be called for every match
5536 to check if this should really be a match. If VERILOG-FLAG is t, the
5537 function returns a list of all possible completions. If it is nil it
5538 returns a string, the longest possible completion, or t if VERILOG-STR is
5539 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
5540 VERILOG-STR is an exact match, nil otherwise."
5542 (let ((verilog-all nil)
5545 ;; Set buffer to use for searching labels. This should be set
5546 ;; within functions which use verilog-completions
5547 (set-buffer verilog-buffer-to-use)
5549 (let ((verilog-str verilog-str))
5550 ;; Build regular expression for functions
5551 (if (string= verilog-str "")
5552 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
5553 (setq verilog-str (verilog-build-defun-re verilog-str)))
5554 (goto-char (point-min))
5556 ;; Build a list of all possible completions
5557 (while (verilog-re-search-forward verilog-str nil t)
5558 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
5559 (if (or (null verilog-pred)
5560 (funcall verilog-pred match))
5561 (setq verilog-all (cons match verilog-all)))))
5563 ;; Now we have built a list of all matches. Give response to caller
5564 (verilog-completion-response))))
5566 (defun verilog-goto-defun ()
5567 "Move to specified Verilog module/task/function.
5568 The default is a name found in the buffer around point.
5569 If search fails, other files are checked based on
5570 `verilog-library-flags'."
5572 (let* ((default (verilog-get-default-symbol))
5573 ;; The following variable is used in verilog-comp-function
5574 (verilog-buffer-to-use (current-buffer))
5575 (label (if (not (string= default ""))
5576 ;; Do completion with default
5577 (completing-read (concat "Label: (default " default ") ")
5578 'verilog-comp-defun nil nil "")
5579 ;; There is no default value. Complete without it
5580 (completing-read "Label: "
5581 'verilog-comp-defun nil nil "")))
5583 ;; If there was no response on prompt, use default value
5584 (if (string= label "")
5585 (setq label default))
5586 ;; Goto right place in buffer if label is not an empty string
5587 (or (string= label "")
5590 (goto-char (point-min))
5592 (re-search-forward (verilog-build-defun-re label t) nil t)))
5595 (beginning-of-line))
5597 (verilog-goto-defun-file label))))
5599 ;; Eliminate compile warning
5600 (defvar occur-pos-list)
5602 (defun verilog-showscopes ()
5603 "List all scopes in this module."
5605 (let ((buffer (current-buffer))
5609 (prevpos (point-min))
5610 (final-context-start (make-marker))
5611 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)"))
5612 (with-output-to-temp-buffer "*Occur*"
5614 (message (format "Searching for %s ..." regexp))
5615 ;; Find next match, but give up if prev match was at end of buffer.
5616 (while (and (not (= prevpos (point-max)))
5617 (verilog-re-search-forward regexp nil t))
5618 (goto-char (match-beginning 0))
5621 (setq linenum (+ linenum (count-lines prevpos (point)))))
5622 (setq prevpos (point))
5623 (goto-char (match-end 0))
5624 (let* ((start (save-excursion
5625 (goto-char (match-beginning 0))
5626 (forward-line (if (< nlines 0) nlines (- nlines)))
5628 (end (save-excursion
5629 (goto-char (match-end 0))
5631 (forward-line (1+ nlines))
5634 (tag (format "%3d" linenum))
5635 (empty (make-string (length tag) ?\ ))
5638 (setq tem (make-marker))
5639 (set-marker tem (point))
5640 (set-buffer standard-output)
5641 (setq occur-pos-list (cons tem occur-pos-list))
5642 (or first (zerop nlines)
5643 (insert "--------\n"))
5645 (insert-buffer-substring buffer start end)
5646 (backward-char (- end start))
5647 (setq tem (if (< nlines 0) (- nlines) nlines))
5651 (setq tem (1- tem)))
5652 (let ((this-linenum linenum))
5653 (set-marker final-context-start
5654 (+ (point) (- (match-end 0) (match-beginning 0))))
5655 (while (< (point) final-context-start)
5657 (setq tag (format "%3d" this-linenum)))
5658 (insert tag ?:)))))))
5659 (set-buffer-modified-p nil))))
5662 ;; Highlight helper functions
5663 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
5664 (defun verilog-within-translate-off ()
5665 "Return point if within translate-off region, else nil."
5666 (and (save-excursion
5668 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
5670 (equal "off" (match-string 2))
5673 (defun verilog-start-translate-off (limit)
5674 "Return point before translate-off directive if before LIMIT, else nil."
5675 (when (re-search-forward
5676 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5678 (match-beginning 0)))
5680 (defun verilog-back-to-start-translate-off (limit)
5681 "Return point before translate-off directive if before LIMIT, else nil."
5682 (when (re-search-backward
5683 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
5685 (match-beginning 0)))
5687 (defun verilog-end-translate-off (limit)
5688 "Return point after translate-on directive if before LIMIT, else nil."
5690 (re-search-forward (concat
5691 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
5693 (defun verilog-match-translate-off (limit)
5694 "Match a translate-off block, setting `match-data' and returning t, else nil.
5695 Bound search by LIMIT."
5696 (when (< (point) limit)
5697 (let ((start (or (verilog-within-translate-off)
5698 (verilog-start-translate-off limit)))
5699 (case-fold-search t))
5701 (let ((end (or (verilog-end-translate-off limit) limit)))
5702 (set-match-data (list start end))
5703 (goto-char end))))))
5705 (defun verilog-font-lock-match-item (limit)
5706 "Match, and move over, any declaration item after point.
5707 Bound search by LIMIT. Adapted from
5708 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
5711 (narrow-to-region (point-min) limit)
5713 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
5715 (goto-char (match-end 1))
5716 ;; move to next item
5717 (if (looking-at "\\(\\s-*,\\)")
5718 (goto-char (match-end 1))
5723 ;; Added by Subbu Meiyappan for Header
5725 (defun verilog-header ()
5726 "Insert a standard Verilog file header."
5728 (let ((start (point)))
5730 //-----------------------------------------------------------------------------
5732 // Project : <project>
5733 //-----------------------------------------------------------------------------
5734 // File : <filename>
5735 // Author : <author>
5736 // Created : <credate>
5737 // Last modified : <moddate>
5738 //-----------------------------------------------------------------------------
5741 //-----------------------------------------------------------------------------
5742 // Copyright (c) <copydate> by <company> This model is the confidential and
5743 // proprietary property of <company> and the possession or use of this
5744 // file requires a written license from <company>.
5745 //------------------------------------------------------------------------------
5746 // Modification history :
5748 //-----------------------------------------------------------------------------
5752 (search-forward "<filename>")
5753 (replace-match (buffer-name) t t)
5754 (search-forward "<author>") (replace-match "" t t)
5755 (insert (user-full-name))
5756 (insert " <" (user-login-name) "@" (system-name) ">")
5757 (search-forward "<credate>") (replace-match "" t t)
5758 (verilog-insert-date)
5759 (search-forward "<moddate>") (replace-match "" t t)
5760 (verilog-insert-date)
5761 (search-forward "<copydate>") (replace-match "" t t)
5762 (verilog-insert-year)
5763 (search-forward "<modhist>") (replace-match "" t t)
5764 (verilog-insert-date)
5765 (insert " : created")
5768 (setq string (read-string "title: "))
5769 (search-forward "<title>")
5770 (replace-match string t t)
5771 (setq string (read-string "project: " verilog-project))
5772 (setq verilog-project string)
5773 (search-forward "<project>")
5774 (replace-match string t t)
5775 (setq string (read-string "Company: " verilog-company))
5776 (setq verilog-company string)
5777 (search-forward "<company>")
5778 (replace-match string t t)
5779 (search-forward "<company>")
5780 (replace-match string t t)
5781 (search-forward "<company>")
5782 (replace-match string t t)
5783 (search-backward "<description>")
5784 (replace-match "" t t))))
5786 ;; verilog-header Uses the verilog-insert-date function
5788 (defun verilog-insert-date ()
5789 "Insert date from the system."
5792 (setq timpos (point))
5793 (if verilog-date-scientific-format
5794 (shell-command "date \"+@%Y/%m/%d\"" t)
5795 (shell-command "date \"+@%d.%m.%Y\"" t))
5796 (search-forward "@")
5797 (delete-region timpos (point))
5801 (defun verilog-insert-year ()
5802 "Insert year from the system."
5805 (setq timpos (point))
5806 (shell-command "date \"+@%Y\"" t)
5807 (search-forward "@")
5808 (delete-region timpos (point))
5814 ;; Signal list parsing
5817 ;; Elements of a signal list
5818 (defsubst verilog-sig-name (sig)
5820 (defsubst verilog-sig-bits (sig)
5822 (defsubst verilog-sig-comment (sig)
5824 (defsubst verilog-sig-memory (sig)
5826 (defsubst verilog-sig-enum (sig)
5828 (defsubst verilog-sig-signed (sig)
5830 (defsubst verilog-sig-type (sig)
5832 (defsubst verilog-sig-multidim (sig)
5834 (defsubst verilog-sig-multidim-string (sig)
5835 (if (verilog-sig-multidim sig)
5836 (let ((str "") (args (verilog-sig-multidim sig)))
5838 (setq str (concat str (car args)))
5839 (setq args (cdr args)))
5841 (defsubst verilog-sig-width (sig)
5842 (verilog-make-width-expression (verilog-sig-bits sig)))
5844 (defsubst verilog-alw-get-inputs (sigs)
5846 (defsubst verilog-alw-get-outputs (sigs)
5848 (defsubst verilog-alw-get-uses-delayed (sigs)
5851 (defun verilog-signals-not-in (in-list not-list)
5852 "Return list of signals in IN-LIST that aren't also in NOT-LIST.
5853 Also remove any duplicates in IN-LIST.
5854 Signals must be in standard (base vector) form."
5857 (if (not (or (assoc (car (car in-list)) not-list)
5858 (assoc (car (car in-list)) out-list)))
5859 (setq out-list (cons (car in-list) out-list)))
5860 (setq in-list (cdr in-list)))
5861 (nreverse out-list)))
5862 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5864 (defun verilog-signals-in (in-list other-list)
5865 "Return list of signals in IN-LIST that are also in OTHER-LIST.
5866 Signals must be in standard (base vector) form."
5869 (if (assoc (car (car in-list)) other-list)
5870 (setq out-list (cons (car in-list) out-list)))
5871 (setq in-list (cdr in-list)))
5872 (nreverse out-list)))
5873 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
5875 (defun verilog-signals-memory (in-list)
5876 "Return list of signals in IN-LIST that are memoried (multidimensional)."
5879 (if (nth 3 (car in-list))
5880 (setq out-list (cons (car in-list) out-list)))
5881 (setq in-list (cdr in-list)))
5883 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
5885 (defun verilog-signals-sort-compare (a b)
5886 "Compare signal A and B for sorting."
5887 (string< (car a) (car b)))
5889 (defun verilog-signals-not-params (in-list)
5890 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
5893 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
5894 (setq out-list (cons (car in-list) out-list)))
5895 (setq in-list (cdr in-list)))
5896 (nreverse out-list)))
5898 (defun verilog-signals-combine-bus (in-list)
5899 "Return a list of signals in IN-LIST, with busses combined.
5900 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
5903 sig highbit lowbit ; Temp information about current signal
5904 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
5905 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
5907 ;; Shove signals so duplicated signals will be adjacent
5908 (setq in-list (sort in-list `verilog-signals-sort-compare))
5910 (setq sig (car in-list))
5911 ;; No current signal; form from existing details
5913 (setq sv-name (verilog-sig-name sig)
5916 sv-comment (verilog-sig-comment sig)
5917 sv-memory (verilog-sig-memory sig)
5918 sv-enum (verilog-sig-enum sig)
5919 sv-signed (verilog-sig-signed sig)
5920 sv-type (verilog-sig-type sig)
5921 sv-multidim (verilog-sig-multidim sig)
5924 ;; Extract bus details
5925 (setq bus (verilog-sig-bits sig))
5927 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
5928 (setq highbit (string-to-number (match-string 1 bus))
5929 lowbit (string-to-number
5930 (match-string 2 bus))))
5931 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
5932 (setq highbit (string-to-number (match-string 1 bus))
5934 ;; Combine bits in bus
5936 (setq sv-highbit (max highbit sv-highbit)
5937 sv-lowbit (min lowbit sv-lowbit))
5938 (setq sv-highbit highbit
5941 ;; String, probably something like `preproc:0
5942 (setq sv-busstring bus)))
5943 ;; Peek ahead to next signal
5944 (setq in-list (cdr in-list))
5945 (setq sig (car in-list))
5946 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
5947 ;; Combine with this signal
5948 (when (and sv-busstring
5949 (not (equal sv-busstring (verilog-sig-bits sig))))
5950 (when nil ;; Debugging
5951 (message (concat "Warning, can't merge into single bus "
5953 ", the AUTOs may be wrong")))
5954 (setq buswarn ", Couldn't Merge"))
5955 (if (verilog-sig-comment sig) (setq combo ", ..."))
5956 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
5957 sv-enum (or sv-enum (verilog-sig-enum sig))
5958 sv-signed (or sv-signed (verilog-sig-signed sig))
5959 sv-type (or sv-type (verilog-sig-type sig))
5960 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
5961 ;; Doesn't match next signal, add to queue, zero in prep for next
5962 ;; Note sig may also be nil for the last signal in the list
5969 (concat "[" (int-to-string sv-highbit) ":"
5970 (int-to-string sv-lowbit) "]")))
5971 (concat sv-comment combo buswarn)
5972 sv-memory sv-enum sv-signed sv-type sv-multidim)
5978 (defun verilog-sig-tieoff (sig &optional no-width)
5979 "Return tieoff expression for given SIG, with appropriate width.
5980 Ignore width if optional NO-WIDTH is set."
5981 (let* ((width (if no-width nil (verilog-sig-width sig))))
5983 (if (and verilog-active-low-regexp
5984 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
5988 ((string-match "^[0-9]+$" width)
5989 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
5991 (concat "{" width "{1'b0}}"))))))
5994 ;; Port/Wire/Etc Reading
5997 (defun verilog-read-inst-backward-name ()
5998 "Internal. Move point back to beginning of inst-name."
5999 (verilog-backward-open-paren)
6002 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
6003 (cond ((looking-at ")")
6004 (verilog-backward-open-paren))
6005 (t (setq done t)))))
6006 (while (looking-at "\\]")
6007 (verilog-backward-open-bracket)
6008 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
6009 (skip-chars-backward "a-zA-Z0-9`_$"))
6011 (defun verilog-read-inst-module ()
6012 "Return module_name when point is inside instantiation."
6014 (verilog-read-inst-backward-name)
6015 ;; Skip over instantiation name
6016 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
6017 ;; Check for parameterized instantiations
6018 (when (looking-at ")")
6019 (verilog-backward-open-paren)
6020 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
6021 (skip-chars-backward "a-zA-Z0-9'_$")
6022 (looking-at "[a-zA-Z0-9`_\$]+")
6023 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6024 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6026 (defun verilog-read-inst-name ()
6027 "Return instance_name when point is inside instantiation."
6029 (verilog-read-inst-backward-name)
6030 (looking-at "[a-zA-Z0-9`_\$]+")
6031 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6032 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6034 (defun verilog-read-module-name ()
6035 "Return module name when after its ( or ;."
6037 (re-search-backward "[(;]")
6038 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
6039 (skip-chars-backward "a-zA-Z0-9`_$")
6040 (looking-at "[a-zA-Z0-9`_\$]+")
6041 ;; Important: don't use match string, this must work with Emacs 19 font-lock on
6042 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
6044 (defun verilog-read-auto-params (num-param &optional max-param)
6045 "Return parameter list inside auto.
6046 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
6049 ;; /*AUTOPUNT("parameter", "parameter")*/
6050 (search-backward "(")
6051 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
6052 (setq olist (cons (match-string 1) olist))
6053 (goto-char (match-end 0))))
6054 (or (eq nil num-param)
6055 (<= num-param (length olist))
6056 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
6057 (if (eq max-param nil) (setq max-param num-param))
6058 (or (eq nil max-param)
6059 (>= max-param (length olist))
6060 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
6063 (defun verilog-read-decls ()
6064 "Compute signal declaration information for the current module at point.
6065 Return a array of [outputs inouts inputs wire reg assign const]."
6066 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
6067 (functask 0) (paren 0) (sig-paren 0)
6068 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
6069 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
6071 (verilog-beg-of-defun)
6072 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
6073 (while (< (point) end-mod-point)
6074 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
6077 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6078 (setq enum (match-string 1)))
6079 (search-forward "\n"))
6080 ((looking-at "/\\*")
6082 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6083 (setq enum (match-string 1)))
6084 (or (search-forward "*/")
6085 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6086 ((looking-at "(\\*")
6088 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
6089 (search-forward "*)")
6090 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6091 ((eq ?\" (following-char))
6092 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
6093 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6094 ((eq ?\; (following-char))
6095 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
6097 ((eq ?= (following-char))
6098 (setq rvalue t newsig nil)
6100 ((and (or rvalue sig-paren)
6101 (cond ((and (eq ?, (following-char))
6102 (eq paren sig-paren))
6106 ;; ,'s can occur inside {} & funcs
6107 ((looking-at "[{(]")
6108 (setq paren (1+ paren))
6111 ((looking-at "[})]")
6112 (setq paren (1- paren))
6114 (when (< paren sig-paren)
6115 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
6117 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
6118 (goto-char (match-end 0))
6119 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
6120 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
6121 (vec ;; Multidimensional
6122 (setq multidim (cons vec multidim))
6123 (setq vec (verilog-string-replace-matches
6124 "\\s-+" "" nil nil (match-string 1))))
6126 (setq vec (verilog-string-replace-matches
6127 "\\s-+" "" nil nil (match-string 1))))))
6128 ;; Normal or escaped identifier -- note we remember the \ if escaped
6129 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
6130 (goto-char (match-end 0))
6131 (setq keywd (match-string 1))
6132 (when (string-match "^\\\\" keywd)
6133 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
6134 (cond ((equal keywd "input")
6135 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6136 expect-signal 'sigs-in io t))
6137 ((equal keywd "output")
6138 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6139 expect-signal 'sigs-out io t))
6140 ((equal keywd "inout")
6141 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
6142 expect-signal 'sigs-inout io t))
6143 ((or (equal keywd "wire")
6145 (equal keywd "tri0")
6146 (equal keywd "tri1"))
6147 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6148 expect-signal 'sigs-wire)))
6149 ((or (equal keywd "reg")
6150 (equal keywd "trireg"))
6151 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6152 expect-signal 'sigs-reg)))
6153 ((equal keywd "assign")
6154 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6155 expect-signal 'sigs-assign))
6156 ((or (equal keywd "supply0")
6157 (equal keywd "supply1")
6158 (equal keywd "supply")
6159 (equal keywd "localparam")
6160 (equal keywd "genvar"))
6161 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6162 expect-signal 'sigs-const)))
6163 ((or (equal keywd "parameter"))
6164 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
6165 expect-signal 'sigs-gparam)))
6166 ((equal keywd "signed")
6167 (setq signed "signed"))
6168 ((or (equal keywd "function")
6169 (equal keywd "task"))
6170 (setq functask (1+ functask)))
6171 ((or (equal keywd "endfunction")
6172 (equal keywd "endtask"))
6173 (setq functask (1- functask)))
6174 ((or (equal keywd "`ifdef")
6175 (equal keywd "`ifndef"))
6177 ((verilog-typedef-name-p keywd)
6178 (setq typedefed keywd))
6182 (eq paren sig-paren)
6183 (not (member keywd verilog-keywords)))
6184 ;; Add new signal to expect-signal's variable
6185 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
6186 (set expect-signal (cons newsig
6187 (symbol-value expect-signal))))))
6190 (skip-syntax-forward " "))
6192 (vector (nreverse sigs-out)
6193 (nreverse sigs-inout)
6195 (nreverse sigs-wire)
6197 (nreverse sigs-assign)
6198 (nreverse sigs-const)
6199 (nreverse sigs-gparam)))))
6202 ;; Prevent compile warnings; these are let's, not globals
6203 ;; Do not remove the eval-when-compile
6204 ;; - we want a error when we are debugging this code if they are refed.
6210 (defsubst verilog-modi-get-decls (modi)
6211 (verilog-modi-cache-results modi 'verilog-read-decls))
6213 (defsubst verilog-modi-get-sub-decls (modi)
6214 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
6217 ;; Signal reading for given module
6218 ;; Note these all take modi's - as returned from the
6219 ;; verilog-modi-current function.
6220 (defsubst verilog-modi-get-outputs (modi)
6221 (aref (verilog-modi-get-decls modi) 0))
6222 (defsubst verilog-modi-get-inouts (modi)
6223 (aref (verilog-modi-get-decls modi) 1))
6224 (defsubst verilog-modi-get-inputs (modi)
6225 (aref (verilog-modi-get-decls modi) 2))
6226 (defsubst verilog-modi-get-wires (modi)
6227 (aref (verilog-modi-get-decls modi) 3))
6228 (defsubst verilog-modi-get-regs (modi)
6229 (aref (verilog-modi-get-decls modi) 4))
6230 (defsubst verilog-modi-get-assigns (modi)
6231 (aref (verilog-modi-get-decls modi) 5))
6232 (defsubst verilog-modi-get-consts (modi)
6233 (aref (verilog-modi-get-decls modi) 6))
6234 (defsubst verilog-modi-get-gparams (modi)
6235 (aref (verilog-modi-get-decls modi) 7))
6236 (defsubst verilog-modi-get-sub-outputs (modi)
6237 (aref (verilog-modi-get-sub-decls modi) 0))
6238 (defsubst verilog-modi-get-sub-inouts (modi)
6239 (aref (verilog-modi-get-sub-decls modi) 1))
6240 (defsubst verilog-modi-get-sub-inputs (modi)
6241 (aref (verilog-modi-get-sub-decls modi) 2))
6244 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
6245 "For `verilog-read-sub-decls-line', add a signal."
6248 (setq port (verilog-symbol-detick-denumber port))
6249 (setq sig (verilog-symbol-detick-denumber sig))
6250 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
6251 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
6252 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
6253 (unless (or (not sig)
6254 (equal sig "")) ;; Ignore .foo(1'b1) assignments
6255 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
6256 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
6257 (verilog-sig-signed portdata)
6258 (verilog-sig-type portdata)
6261 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
6262 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
6263 (verilog-sig-signed portdata)
6264 (verilog-sig-type portdata)
6267 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
6268 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
6269 (verilog-sig-signed portdata)
6270 (verilog-sig-type portdata)
6273 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
6276 (defun verilog-read-sub-decls-line (submodi comment)
6277 "For `verilog-read-sub-decls', read lines of port defs until none match anymore.
6278 Return the list of signals found, using submodi to look up each port."
6279 (let (done port sig vec multidim)
6284 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
6285 (setq port (match-string 1))
6286 (goto-char (match-end 0)))
6287 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
6288 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
6289 (goto-char (match-end 0)))
6290 ((looking-at "\\s-*\\.[^(]*(")
6291 (setq port nil) ;; skip this line
6292 (goto-char (match-end 0)))
6294 (setq port nil done t))) ;; Unknown, ignore rest of line
6298 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
6299 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
6301 ; We intentionally ignore (non-escaped) signals with .s in them
6302 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
6303 ((looking-at "\\([^[({).]*\\)\\s-*)")
6304 (setq sig (verilog-string-remove-spaces (match-string 1))
6306 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
6307 (setq sig (verilog-string-remove-spaces (match-string 1))
6308 vec (match-string 2)))
6309 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
6310 (setq sig (verilog-string-remove-spaces (match-string 1))
6312 (let ((parse (match-string 2)))
6313 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
6314 (when vec (setq multidim (cons vec multidim)))
6315 (setq vec (match-string 1 parse))
6316 (setq parse (match-string 2 parse)))))
6317 ((looking-at "{\\(.*\\)}.*\\s-*)")
6318 (let ((mlst (split-string (match-string 1) ","))
6320 (while (setq mstr (pop mlst))
6321 ;;(unless noninteractive (message "sig: %s " mstr))
6323 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
6324 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6326 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
6328 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
6329 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
6330 vec (match-string 2 mstr))
6331 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
6336 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
6340 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
6342 (forward-line 1)))))
6344 (defun verilog-read-sub-decls ()
6345 "Internally parse signals going to modules under this module.
6346 Return a array of [ outputs inouts inputs ] signals for modules that are
6347 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
6348 is a output, then SIG will be included in the list.
6350 This only works on instantiations created with /*AUTOINST*/ converted by
6351 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
6352 component library to determine connectivity of the design.
6354 One work around for this problem is to manually create // Inputs and //
6355 Outputs comments above subcell signals, for example:
6363 (let ((end-mod-point (verilog-get-end-of-defun t))
6364 st-point end-inst-point
6365 ;; below 3 modified by verilog-read-sub-decls-line
6366 sigs-out sigs-inout sigs-in)
6367 (verilog-beg-of-defun)
6368 (while (verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
6370 (goto-char (match-beginning 0))
6371 (unless (verilog-inside-comment-p)
6372 ;; Attempt to snarf a comment
6373 (let* ((submod (verilog-read-inst-module))
6374 (inst (verilog-read-inst-name))
6375 (comment (concat inst " of " submod ".v")) submodi)
6376 (when (setq submodi (verilog-modi-lookup submod t))
6377 ;; This could have used a list created by verilog-auto-inst
6378 ;; However I want it to be runnable even on user's manually added signals
6379 (verilog-backward-open-paren)
6380 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
6382 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
6383 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
6384 (goto-char st-point)
6385 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
6386 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
6387 (goto-char st-point)
6388 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
6389 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
6391 ;; Combine duplicate bits
6392 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
6393 (vector (verilog-signals-combine-bus (nreverse sigs-out))
6394 (verilog-signals-combine-bus (nreverse sigs-inout))
6395 (verilog-signals-combine-bus (nreverse sigs-in))))))
6397 (defun verilog-read-inst-pins ()
6398 "Return an array of [ pins ] for the current instantiation at point.
6399 For example if declare A A (.B(SIG)) then B will be included in the list."
6401 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
6403 (verilog-backward-open-paren)
6404 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
6405 (setq pin (match-string 1))
6406 (unless (verilog-inside-comment-p)
6407 (setq pins (cons (list pin) pins))
6408 (when (looking-at "(")
6412 (defun verilog-read-arg-pins ()
6413 "Return an array of [ pins ] for the current argument declaration at point."
6415 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
6417 (verilog-backward-open-paren)
6418 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
6419 (setq pin (match-string 1))
6420 (unless (verilog-inside-comment-p)
6421 (setq pins (cons (list pin) pins))))
6424 (defun verilog-read-auto-constants (beg end-mod-point)
6425 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
6428 (let (sig-list tpl-end-pt)
6430 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
6431 (if (not (looking-at "\\s *("))
6432 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
6433 (search-forward "(" end-mod-point)
6434 (setq tpl-end-pt (save-excursion
6436 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6439 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
6440 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
6443 (defun verilog-read-auto-lisp (start end)
6444 "Look for and evaluate a AUTO_LISP between START and END."
6447 (while (re-search-forward "\\<AUTO_LISP(" end t)
6449 (let* ((beg-pt (prog1 (point)
6450 (forward-sexp 1))) ;; Closing paren
6452 (eval-region beg-pt end-pt nil)))))
6455 ;; Prevent compile warnings; these are let's, not globals
6456 ;; Do not remove the eval-when-compile
6457 ;; - we want a error when we are debugging this code if they are refed.
6462 (defvar uses-delayed)
6463 (defvar vector-skip-list))
6465 (defun verilog-read-always-signals-recurse
6466 (exit-keywd rvalue ignore-next)
6467 "Recursive routine for parentheses/bracket matching.
6468 EXIT-KEYWD is expression to stop at, nil if top level.
6469 RVALUE is true if at right hand side of equal.
6470 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
6471 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
6472 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
6473 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
6474 (while (not (or (eobp) gotend))
6477 (search-forward "\n"))
6478 ((looking-at "/\\*")
6479 (or (search-forward "*/")
6480 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6481 ((looking-at "(\\*")
6482 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6483 (search-forward "*)")
6484 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
6485 (t (setq keywd (buffer-substring-no-properties
6487 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6490 sig-last-tolk sig-tolk
6492 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
6495 (or (re-search-forward "[^\\]\"" nil t)
6496 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
6497 ;; else at top level loop, keep parsing
6498 ((and end-else-check (equal keywd "else"))
6499 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
6500 ;; no forward movement, want to see else in lower loop
6501 (setq end-else-check nil))
6502 ;; End at top level loop
6503 ((and end-else-check (looking-at "[^ \t\n\f]"))
6504 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
6507 ((and exit-keywd (equal keywd exit-keywd))
6509 (forward-char (length keywd)))
6510 ;; Standard tokens...
6512 (setq ignore-next nil rvalue semi-rvalue)
6513 ;; Final statement at top level loop?
6514 (when (not exit-keywd)
6515 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
6516 (setq end-else-check t))
6519 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
6520 (goto-char (match-end 0))
6522 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
6523 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
6524 (setq ignore-next nil rvalue nil))
6525 ((equal "?" exit-keywd) ;; x?y:z rvalue
6527 (got-sig ;; label: statement
6528 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
6529 ((not rvalue) ;; begin label
6530 (setq ignore-next t rvalue nil)))
6533 (if (eq (char-before) ?< )
6534 (setq uses-delayed 1))
6535 (setq ignore-next nil rvalue t)
6539 (verilog-read-always-signals-recurse ":" rvalue nil))
6542 (verilog-read-always-signals-recurse "]" t nil))
6545 (cond (sig-last-tolk ;; Function call; zap last signal
6546 (setq got-sig nil)))
6547 (cond ((equal last-keywd "for")
6548 (verilog-read-always-signals-recurse ";" nil nil)
6549 (verilog-read-always-signals-recurse ";" t nil)
6550 (verilog-read-always-signals-recurse ")" nil nil))
6551 (t (verilog-read-always-signals-recurse ")" t nil))))
6552 ((equal keywd "begin")
6553 (skip-syntax-forward "w_")
6554 (verilog-read-always-signals-recurse "end" nil nil)
6555 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
6556 (setq ignore-next nil rvalue semi-rvalue)
6557 (if (not exit-keywd) (setq end-else-check t)))
6558 ((or (equal keywd "case")
6559 (equal keywd "casex")
6560 (equal keywd "casez"))
6561 (skip-syntax-forward "w_")
6562 (verilog-read-always-signals-recurse "endcase" t nil)
6563 (setq ignore-next nil rvalue semi-rvalue)
6564 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
6565 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
6566 (cond ((or (equal keywd "`ifdef")
6567 (equal keywd "`ifndef"))
6568 (setq ignore-next t))
6570 (member keywd verilog-keywords)
6571 (string-match "^\\$" keywd)) ;; PLI task
6572 (setq ignore-next nil))
6574 (setq keywd (verilog-symbol-detick-denumber keywd))
6576 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6577 (setq sigs-out (cons got-sig sigs-out)))
6578 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6580 (setq got-rvalue rvalue
6581 got-sig (if (or (not keywd)
6582 (assoc keywd (if got-rvalue sigs-in sigs-out)))
6583 nil (list keywd nil nil))
6585 (skip-chars-forward "a-zA-Z0-9$_.%`"))
6588 ;; End of non-comment token
6589 (setq last-keywd keywd)))
6590 (skip-syntax-forward " "))
6591 ;; Append the final pending signal
6593 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
6594 (setq sigs-out (cons got-sig sigs-out)))
6595 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
6597 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
6600 (defun verilog-read-always-signals ()
6601 "Parse always block at point and return list of (outputs inout inputs)."
6606 uses-delayed) ;; Found signal/rvalue; push if not function
6607 (search-forward ")")
6608 (verilog-read-always-signals-recurse nil nil nil)
6609 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
6610 ;; Return what was found
6611 (list sigs-out nil sigs-in uses-delayed))))
6613 (defun verilog-read-instants ()
6614 "Parse module at point and return list of ( ( file instance ) ... )."
6615 (verilog-beg-of-defun)
6616 (let* ((end-mod-point (verilog-get-end-of-defun t))
6618 (instants-list nil))
6620 (while (< (point) end-mod-point)
6621 ;; Stay at level 0, no comments
6623 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
6624 (or (> (car state) 0) ; in parens
6625 (nth 5 state) ; comment
6629 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
6630 ;;(if (looking-at "^\\(.+\\)$")
6631 (let ((module (match-string 1))
6632 (instant (match-string 2)))
6633 (if (not (member module verilog-keywords))
6634 (setq instants-list (cons (list module instant) instants-list)))))
6639 (defun verilog-read-auto-template (module)
6640 "Look for a auto_template for the instantiation of the given MODULE.
6641 If found returns the signal name connections. Return REGEXP and
6642 list of ( (signal_name connection_name)... )."
6645 (let ((tpl-regexp "\\([0-9]+\\)")
6648 tpl-sig-list tpl-wild-list tpl-end-pt rep)
6650 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
6652 (goto-char (point-min))
6653 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
6654 (goto-char (match-end 0))
6656 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
6657 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
6658 (setq tpl-regexp (match-string 1))
6659 (goto-char (match-end 0)))
6660 (search-forward "(")
6661 ;; Parse lines in the template
6662 (when verilog-auto-inst-template-numbers
6664 (goto-char (point-min))
6665 (while (search-forward "AUTO_TEMPLATE" nil t)
6666 (setq templateno (1+ templateno)))))
6667 (setq tpl-end-pt (save-excursion
6669 (forward-sexp 1) ;; Moves to paren that closes argdecl's
6673 (while (< (point) tpl-end-pt)
6674 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6675 (setq tpl-sig-list (cons (list
6676 (match-string-no-properties 1)
6677 (match-string-no-properties 2)
6680 (goto-char (match-end 0)))
6683 ;; Regexp bug in XEmacs disallows ][ inside [], and wants + last
6684 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
6685 (setq rep (match-string-no-properties 3))
6686 (goto-char (match-end 0))
6690 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
6696 ((looking-at "[ \t\f]+")
6697 (goto-char (match-end 0)))
6699 (setq lineno (1+ lineno))
6700 (goto-char (match-end 0)))
6702 (search-forward "\n"))
6703 ((looking-at "/\\*")
6705 (or (search-forward "*/")
6706 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
6708 (error "%s: AUTO_TEMPLATE parsing error: %s"
6709 (verilog-point-text)
6710 (progn (looking-at ".*$") (match-string 0))))))
6713 (list tpl-sig-list tpl-wild-list)))
6714 ;; If no template found
6715 (t (vector tpl-regexp nil))))))
6716 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
6718 (defun verilog-set-define (defname defvalue &optional buffer enumname)
6719 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
6720 Optionally associate it with the specified enumeration ENUMNAME."
6722 (set-buffer (or buffer (current-buffer)))
6723 (let ((mac (intern (concat "vh-" defname))))
6724 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6725 ;; Need to define to a constant if no value given
6726 (set (make-variable-buffer-local mac)
6727 (if (equal defvalue "") "1" defvalue)))
6729 (let ((enumvar (intern (concat "venum-" enumname))))
6730 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
6731 (make-variable-buffer-local enumvar)
6732 (add-to-list enumvar defname)))))
6734 (defun verilog-read-defines (&optional filename recurse subcall)
6735 "Read `defines and parameters for the current file, or optional FILENAME.
6736 If the filename is provided, `verilog-library-flags' will be used to
6737 resolve it. If optional RECURSE is non-nil, recurse through `includes.
6739 Parameters must be simple assignments to constants, or have their own
6740 \"parameter\" label rather than a list of parameters. Thus:
6742 parameter X = 5, Y = 10; // Ok
6743 parameter X = {1'b1, 2'h2}; // Ok
6744 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
6746 Defines must be simple text substitutions, one on a line, starting
6747 at the beginning of the line. Any ifdefs or multiline comments around the
6750 Defines are stored inside Emacs variables using the name vh-{definename}.
6752 This function is useful for setting vh-* variables. The file variables
6753 feature can be used to set defines that `verilog-mode' can see; put at the
6754 *END* of your file something like:
6757 // vh-macro:\"macro_definition\"
6760 If macros are defined earlier in the same file and you want their values,
6761 you can read them automatically (provided `enable-local-eval' is on):
6764 // eval:(verilog-read-defines)
6765 // eval:(verilog-read-defines \"group_standard_includes.v\")
6768 Note these are only read when the file is first visited, you must use
6769 \\[find-alternate-file] RET to have these take effect after editing them!
6771 If you want to disable the \"Process `eval' or hook local variables\"
6772 warning message, you need to add to your .emacs file:
6774 (setq enable-local-eval t)"
6775 (let ((origbuf (current-buffer)))
6777 (unless subcall (verilog-getopt-flags))
6779 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
6781 (set-buffer (find-file-noselect (car fns)))
6782 (error (concat (verilog-point-text)
6783 ": Can't find verilog-read-defines file: " filename)))))
6785 (goto-char (point-min))
6786 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6787 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
6788 (unless (verilog-inside-comment-p)
6789 (verilog-read-defines inc recurse t)))))
6791 ;; note we don't use verilog-re... it's faster this way, and that
6792 ;; function has problems when comments are at the end of the define
6793 (goto-char (point-min))
6794 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
6795 (let ((defname (match-string-no-properties 1))
6796 (defvalue (match-string-no-properties 2)))
6797 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
6798 (verilog-set-define defname defvalue origbuf)))
6799 ;; Hack: Read parameters
6800 (goto-char (point-min))
6801 (while (re-search-forward
6802 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
6803 (let ((var (match-string-no-properties 4))
6804 (val (match-string-no-properties 5))
6806 ;; The primary way of getting defines is verilog-read-decls
6807 ;; However, that isn't called yet for included files, so we'll add another scheme
6808 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
6809 (setq enumname (match-string-no-properties 1)))
6811 (verilog-set-define var val origbuf enumname))
6812 (forward-comment 999)
6813 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
6814 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
6815 (goto-char (match-end 0))
6816 (forward-comment 999)))))))
6818 (defun verilog-read-includes ()
6819 "Read `includes for the current file.
6820 This will find all of the `includes which are at the beginning of lines,
6821 ignoring any ifdefs or multiline comments around them.
6822 `verilog-read-defines' is then performed on the current and each included
6825 It is often useful put at the *END* of your file something like:
6828 // eval:(verilog-read-defines)
6829 // eval:(verilog-read-includes)
6832 Note includes are only read when the file is first visited, you must use
6833 \\[find-alternate-file] RET to have these take effect after editing them!
6835 It is good to get in the habit of including all needed files in each .v
6836 file that needs it, rather than waiting for compile time. This will aid
6837 this process, Verilint, and readability. To prevent defining the same
6838 variable over and over when many modules are compiled together, put a test
6839 around the inside each include file:
6842 `ifdef _FOO_V // include if not already included
6845 ... contents of file
6847 ;;slow: (verilog-read-defines nil t))
6849 (verilog-getopt-flags)
6850 (goto-char (point-min))
6851 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
6852 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
6853 (verilog-read-defines inc nil t)))))
6855 (defun verilog-read-signals (&optional start end)
6856 "Return a simple list of all possible signals in the file.
6857 Bounded by optional region from START to END. Overly aggressive but fast.
6858 Some macros and such are also found and included. For dinotrace.el."
6859 (let (sigs-all keywd)
6860 (progn;save-excursion
6861 (goto-char (or start (point-min)))
6862 (setq end (or end (point-max)))
6863 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
6867 (search-forward "\n"))
6868 ((looking-at "/\\*")
6869 (search-forward "*/"))
6870 ((looking-at "(\\*")
6871 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
6872 (search-forward "*)")))
6873 ((eq ?\" (following-char))
6874 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
6875 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
6876 (goto-char (match-end 0))
6877 (setq keywd (match-string-no-properties 1))
6878 (or (member keywd verilog-keywords)
6879 (member keywd sigs-all)
6880 (setq sigs-all (cons keywd sigs-all))))
6881 (t (forward-char 1))))
6886 ;; Argument file parsing
6889 (defun verilog-getopt (arglist)
6890 "Parse -f, -v etc arguments in ARGLIST list or string."
6891 (unless (listp arglist) (setq arglist (list arglist)))
6892 (let ((space-args '())
6894 ;; Split on spaces, so users can pass whole command lines
6896 (setq arg (car arglist)
6897 arglist (cdr arglist))
6898 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
6899 (setq space-args (append space-args
6900 (list (match-string-no-properties 1 arg))))
6901 (setq arg (match-string 2 arg))))
6904 (setq arg (car space-args)
6905 space-args (cdr space-args))
6909 (setq next-param arg))
6911 (setq next-param arg))
6913 (setq next-param arg))
6914 ;; +libext+(ext1)+(ext2)...
6915 ((string-match "^\\+libext\\+\\(.*\\)" arg)
6916 (setq arg (match-string 1 arg))
6917 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
6918 (verilog-add-list-unique `verilog-library-extensions
6919 (match-string 1 arg))
6920 (setq arg (match-string 2 arg))))
6922 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
6923 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
6924 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
6925 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
6926 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
6928 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
6929 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
6930 (verilog-add-list-unique `verilog-library-directories
6931 (match-string 1 arg)))
6933 ((equal "+librescan" arg))
6934 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
6935 ;; Second parameters
6936 ((equal next-param "-f")
6937 (setq next-param nil)
6938 (verilog-getopt-file arg))
6939 ((equal next-param "-v")
6940 (setq next-param nil)
6941 (verilog-add-list-unique `verilog-library-files arg))
6942 ((equal next-param "-y")
6943 (setq next-param nil)
6944 (verilog-add-list-unique `verilog-library-directories arg))
6946 ((string-match "^[^-+]" arg)
6947 (verilog-add-list-unique `verilog-library-files arg))
6948 ;; Default - ignore; no warning
6950 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
6952 (defun verilog-getopt-file (filename)
6953 "Read Verilog options from the specified FILENAME."
6955 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
6956 (orig-buffer (current-buffer))
6959 (set-buffer (find-file-noselect (car fns)))
6960 (error (concat (verilog-point-text)
6961 "Can't find verilog-getopt-file -f file: " filename)))
6962 (goto-char (point-min))
6964 (setq line (buffer-substring (point)
6965 (save-excursion (end-of-line) (point))))
6967 (when (string-match "//" line)
6968 (setq line (substring line 0 (match-beginning 0))))
6970 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
6971 (verilog-getopt line))))))
6973 (defun verilog-getopt-flags ()
6974 "Convert `verilog-library-flags' into standard library variables."
6975 ;; If the flags are local, then all the outputs should be local also
6976 (when (local-variable-p `verilog-library-flags (current-buffer))
6977 (mapc 'make-local-variable '(verilog-library-extensions
6978 verilog-library-directories
6979 verilog-library-files
6980 verilog-library-flags)))
6981 ;; Allow user to customize
6982 (run-hooks 'verilog-before-getopt-flags-hook)
6983 ;; Process arguments
6984 (verilog-getopt verilog-library-flags)
6985 ;; Allow user to customize
6986 (run-hooks 'verilog-getopt-flags-hook))
6988 (defun verilog-add-list-unique (varref object)
6989 "Append to VARREF list the given OBJECT,
6990 unless it is already a member of the variable's list."
6991 (unless (member object (symbol-value varref))
6992 (set varref (append (symbol-value varref) (list object))))
6994 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
6998 ;; Module name lookup
7001 (defun verilog-module-inside-filename-p (module filename)
7002 "Return point if MODULE is specified inside FILENAME, else nil.
7003 Allows version control to check out the file if need be."
7004 (and (or (file-exists-p filename)
7005 (and (fboundp 'vc-backend)
7006 (vc-backend filename)))
7009 (set-buffer (find-file-noselect filename))
7010 (goto-char (point-min))
7012 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
7013 (verilog-re-search-forward-quick "\\<module\\>" nil t)
7014 (verilog-re-search-forward-quick "[(;]" nil t))
7015 (if (equal module (verilog-read-module-name))
7019 (defun verilog-is-number (symbol)
7020 "Return true if SYMBOL is number-like."
7021 (or (string-match "^[0-9 \t:]+$" symbol)
7022 (string-match "^[---]*[0-9]+$" symbol)
7023 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)))
7025 (defun verilog-symbol-detick (symbol wing-it)
7026 "Return an expanded SYMBOL name without any defines.
7027 If the variable vh-{symbol} is defined, return that value.
7028 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
7029 (while (and symbol (string-match "^`" symbol))
7030 (setq symbol (substring symbol 1))
7032 (if (boundp (intern (concat "vh-" symbol)))
7033 ;; Emacs has a bug where boundp on a buffer-local
7034 ;; variable in only one buffer returns t in another.
7035 ;; This can confuse, so check for nil.
7036 (let ((val (eval (intern (concat "vh-" symbol)))))
7038 (if wing-it symbol nil)
7040 (if wing-it symbol nil))))
7042 ;;(verilog-symbol-detick "`mod" nil)
7044 (defun verilog-symbol-detick-denumber (symbol)
7045 "Return SYMBOL with defines converted and any numbers dropped to nil."
7046 (when (string-match "^`" symbol)
7047 ;; This only will work if the define is a simple signal, not
7048 ;; something like a[b]. Sorry, it should be substituted into the parser
7050 (verilog-string-replace-matches
7051 "\[[^0-9: \t]+\]" "" nil nil
7052 (or (verilog-symbol-detick symbol nil)
7053 (if verilog-auto-sense-defines-constant
7056 (if (verilog-is-number symbol)
7060 (defun verilog-symbol-detick-text (text)
7061 "Return TEXT without any known defines.
7062 If the variable vh-{symbol} is defined, substitute that value."
7063 (let ((ok t) symbol val)
7064 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
7065 (setq symbol (match-string 1 text))
7068 (boundp (intern (concat "vh-" symbol)))
7069 ;; Emacs has a bug where boundp on a buffer-local
7070 ;; variable in only one buffer returns t in another.
7071 ;; This can confuse, so check for nil.
7072 (setq val (eval (intern (concat "vh-" symbol)))))
7073 (setq text (replace-match val nil nil text)))
7074 (t (setq ok nil)))))
7076 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
7078 (defun verilog-expand-dirnames (&optional dirnames)
7079 "Return a list of existing directories given a list of wildcarded DIRNAMES.
7080 Or, just the existing dirnames themselves if there are no wildcards."
7082 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
7083 (setq dirnames (reverse dirnames)) ; not nreverse
7085 pattern dirfile dirfiles dirname root filename rest)
7087 (setq dirname (substitute-in-file-name (car dirnames))
7088 dirnames (cdr dirnames))
7089 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
7090 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
7093 (setq root (match-string 1 dirname)
7094 filename (match-string 2 dirname)
7095 rest (match-string 3 dirname)
7097 ;; now replace those * and ? with .+ and .
7098 ;; use ^ and /> to get only whole file names
7099 ;;verilog-string-replace-matches
7100 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
7101 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
7103 ;; Unfortunately allows abc/*/rtl to match abc/rtl
7104 ;; because abc/.. shows up in dirfiles. Solutions welcome.
7105 dirfiles (if (file-directory-p root) ; Ignore version control external
7106 (directory-files root t pattern nil)))
7108 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
7109 dirfiles (cdr dirfiles))
7110 (if (file-directory-p dirfile)
7111 (setq dirlist (cons dirfile dirlist)))))
7114 (if (file-directory-p dirname)
7115 (setq dirlist (cons dirname dirlist))))))
7117 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
7119 (defun verilog-library-filenames (filename current &optional check-ext)
7120 "Return a search path to find the given FILENAME name.
7121 Uses the CURRENT filename, `verilog-library-directories' and
7122 `verilog-library-extensions' variables to build the path.
7123 With optional CHECK-EXT also check `verilog-library-extensions'."
7124 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
7127 (let ((ckext (if check-ext verilog-library-extensions `(""))))
7129 (setq fn (expand-file-name
7130 (concat filename (car ckext))
7131 (expand-file-name (car ckdir) (file-name-directory current))))
7132 (if (file-exists-p fn)
7133 (setq outlist (cons fn outlist)))
7134 (setq ckext (cdr ckext))))
7135 (setq ckdir (cdr ckdir)))
7136 (nreverse outlist)))
7138 (defun verilog-module-filenames (module current)
7139 "Return a search path to find the given MODULE name.
7140 Uses the CURRENT filename, `verilog-library-extensions',
7141 `verilog-library-directories' and `verilog-library-files'
7142 variables to build the path."
7143 ;; Return search locations for it
7144 (append (list current) ; first, current buffer
7145 (verilog-library-filenames module current t)
7146 verilog-library-files)) ; finally, any libraries
7149 ;; Module Information
7151 ;; Many of these functions work on "modi" a module information structure
7152 ;; A modi is: [module-name-string file-name begin-point]
7154 (defvar verilog-cache-enabled t
7155 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
7157 (defvar verilog-modi-cache-list nil
7158 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
7159 For speeding up verilog-modi-get-* commands.
7162 (make-variable-buffer-local 'verilog-modi-cache-list)
7164 (defvar verilog-modi-cache-preserve-tick nil
7165 "Modification tick after which the cache is still considered valid.
7166 Use `verilog-preserve-cache' to set it.")
7167 (defvar verilog-modi-cache-preserve-buffer nil
7168 "Modification tick after which the cache is still considered valid.
7169 Use `verilog-preserve-cache' to set it.")
7171 (defun verilog-modi-current ()
7172 "Return the modi structure for the module currently at point."
7174 ;; read current module's name
7176 (verilog-re-search-backward-quick verilog-defun-re nil nil)
7177 (verilog-re-search-forward-quick "(" nil nil)
7178 (setq name (verilog-read-module-name))
7181 (vector name (or (buffer-file-name) (current-buffer)) pt)))
7183 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
7184 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
7185 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
7186 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
7188 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
7189 "Find the file and point at which MODULE is defined.
7190 If ALLOW-CACHE is set, check and remember cache of previous lookups.
7191 Return modi if successful, else print message unless IGNORE-ERROR is true."
7192 (let* ((current (or (buffer-file-name) (current-buffer))))
7193 (cond ((and verilog-modi-lookup-last-modi
7194 verilog-cache-enabled
7196 (equal verilog-modi-lookup-last-mod module)
7197 (equal verilog-modi-lookup-last-current current)
7198 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
7201 (t (let* ((realmod (verilog-symbol-detick module t))
7202 (orig-filenames (verilog-module-filenames realmod current))
7203 (filenames orig-filenames)
7205 (while (and filenames (not pt))
7206 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
7207 (setq filenames (cdr filenames))))
7208 (cond (pt (setq verilog-modi-lookup-last-modi
7209 (vector realmod (car filenames) pt)))
7210 (t (setq verilog-modi-lookup-last-modi nil)
7212 (error (concat (verilog-point-text)
7213 ": Can't locate " module " module definition"
7214 (if (not (equal module realmod))
7215 (concat " (Expanded macro to " realmod ")")
7217 "\n Check the verilog-library-directories variable."
7218 "\n I looked in (if not listed, doesn't exist):\n\t"
7219 (mapconcat 'concat orig-filenames "\n\t"))))))
7220 (setq verilog-modi-lookup-last-mod module
7221 verilog-modi-lookup-last-current current
7222 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
7223 verilog-modi-lookup-last-modi))
7225 (defsubst verilog-modi-name (modi)
7227 (defsubst verilog-modi-file-or-buffer (modi)
7229 (defsubst verilog-modi-point (modi)
7232 (defun verilog-modi-filename (modi)
7233 "Filename of MODI, or name of buffer if it's never been saved."
7234 (if (bufferp (verilog-modi-file-or-buffer modi))
7235 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
7236 (buffer-name (verilog-modi-file-or-buffer modi)))
7237 (verilog-modi-file-or-buffer modi)))
7239 (defun verilog-modi-goto (modi)
7240 "Move point/buffer to specified MODI."
7241 (or modi (error "Passed unfound modi to goto, check earlier"))
7242 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
7243 (verilog-modi-file-or-buffer modi)
7244 (find-file-noselect (verilog-modi-file-or-buffer modi))))
7245 (or (equal major-mode `verilog-mode) ;; Put into Verilog mode to get syntax
7247 (goto-char (verilog-modi-point modi)))
7249 (defun verilog-goto-defun-file (module)
7250 "Move point to the file at which a given MODULE is defined."
7251 (interactive "sGoto File for Module: ")
7252 (let* ((modi (verilog-modi-lookup module nil)))
7254 (verilog-modi-goto modi)
7255 (switch-to-buffer (current-buffer)))))
7257 (defun verilog-modi-cache-results (modi function)
7258 "Run on MODI the given FUNCTION. Locate the module in a file.
7259 Cache the output of function so next call may have faster access."
7260 (let (func-returns fass)
7262 (verilog-modi-goto modi)
7263 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
7264 verilog-modi-cache-list))
7265 ;; Destroy caching when incorrect; Modified or file changed
7266 (not (and verilog-cache-enabled
7267 (or (equal (buffer-modified-tick) (nth 1 fass))
7268 (and verilog-modi-cache-preserve-tick
7269 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
7270 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
7271 (equal (visited-file-modtime) (nth 2 fass)))))
7272 (setq verilog-modi-cache-list nil
7276 (setq func-returns (nth 3 fass)))
7279 ;; Clear then restore any hilighting to make Emacs 19 happy
7280 (let ((fontlocked (when (and (boundp 'font-lock-mode)
7282 (font-lock-mode nil)
7284 (setq func-returns (funcall function))
7285 (when fontlocked (font-lock-mode t)))
7286 ;; Cache for next time
7287 (setq verilog-modi-cache-list
7288 (cons (list (list (verilog-modi-name modi) function)
7289 (buffer-modified-tick)
7290 (visited-file-modtime)
7292 verilog-modi-cache-list)))))
7296 (defun verilog-modi-cache-add (modi function element sig-list)
7297 "Add function return results to the module cache.
7298 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
7299 function now contains the additional SIG-LIST parameters."
7302 (verilog-modi-goto modi)
7303 (if (setq fass (assoc (list (verilog-modi-name modi) function)
7304 verilog-modi-cache-list))
7305 (let ((func-returns (nth 3 fass)))
7306 (aset func-returns element
7307 (append sig-list (aref func-returns element))))))))
7309 (defmacro verilog-preserve-cache (&rest body)
7310 "Execute the BODY forms, allowing cache preservation within BODY.
7311 This means that changes to the buffer will not result in the cache being
7312 flushed. If the changes affect the modsig state, they must call the
7313 modsig-cache-add-* function, else the results of later calls may be
7314 incorrect. Without this, changes are assumed to be adding/removing signals
7315 and invalidating the cache."
7316 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
7317 (verilog-modi-cache-preserve-buffer (current-buffer)))
7321 (defun verilog-signals-matching-enum (in-list enum)
7322 "Return all signals in IN-LIST matching the given ENUM."
7325 (if (equal (verilog-sig-enum (car in-list)) enum)
7326 (setq out-list (cons (car in-list) out-list)))
7327 (setq in-list (cdr in-list)))
7329 (let* ((enumvar (intern (concat "venum-" enum)))
7330 (enumlist (and (boundp enumvar) (eval enumvar))))
7332 (add-to-list 'out-list (list (car enumlist)))
7333 (setq enumlist (cdr enumlist))))
7334 (nreverse out-list)))
7336 (defun verilog-signals-matching-regexp (in-list regexp)
7337 "Return all signals in IN-LIST matching the given REGEXP, if non-nil."
7342 (if (string-match regexp (verilog-sig-name (car in-list)))
7343 (setq out-list (cons (car in-list) out-list)))
7344 (setq in-list (cdr in-list)))
7345 (nreverse out-list))))
7347 (defun verilog-signals-not-matching-regexp (in-list regexp)
7348 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
7353 (if (not (string-match regexp (verilog-sig-name (car in-list))))
7354 (setq out-list (cons (car in-list) out-list)))
7355 (setq in-list (cdr in-list)))
7356 (nreverse out-list))))
7359 (defun verilog-modi-get-signals (modi)
7361 (verilog-modi-get-outputs modi)
7362 (verilog-modi-get-inouts modi)
7363 (verilog-modi-get-inputs modi)
7364 (verilog-modi-get-wires modi)
7365 (verilog-modi-get-regs modi)
7366 (verilog-modi-get-assigns modi)
7367 (verilog-modi-get-consts modi)
7368 (verilog-modi-get-gparams modi)))
7370 (defun verilog-modi-get-ports (modi)
7372 (verilog-modi-get-outputs modi)
7373 (verilog-modi-get-inouts modi)
7374 (verilog-modi-get-inputs modi)))
7376 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
7377 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
7378 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
7379 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
7380 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
7381 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
7382 (defsubst verilog-modi-cache-add-wires (modi sig-list)
7383 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
7384 (defsubst verilog-modi-cache-add-regs (modi sig-list)
7385 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
7387 (defun verilog-signals-from-signame (signame-list)
7388 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
7389 (mapcar (function (lambda (name) (list name nil nil)))
7393 ;; Auto creation utilities
7396 (defun verilog-auto-re-search-do (search-for func)
7397 "Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
7398 (goto-char (point-min))
7399 (while (verilog-re-search-forward search-for nil t)
7402 (defun verilog-auto-search-do (search-for func)
7403 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
7404 (verilog-auto-re-search-do (regexp-quote search-for) func))
7406 (defun verilog-insert-one-definition (sig type indent-pt)
7407 "Print out a definition for SIG of the given TYPE,
7408 with appropriate INDENT-PT indentation."
7409 (indent-to indent-pt)
7411 (when (verilog-sig-signed sig)
7412 (insert " " (verilog-sig-signed sig)))
7413 (when (verilog-sig-multidim sig)
7414 (insert " " (verilog-sig-multidim-string sig)))
7415 (when (verilog-sig-bits sig)
7416 (insert " " (verilog-sig-bits sig)))
7417 (indent-to (max 24 (+ indent-pt 16)))
7418 (unless (= (char-syntax (preceding-char)) ?\ )
7419 (insert " ")) ; Need space between "]name" if indent-to did nothing
7420 (insert (verilog-sig-name sig)))
7422 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
7423 "Print out a definition for a list of SIGS of the given DIRECTION,
7424 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
7425 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
7427 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
7429 (let ((sig (car sigs)))
7430 (verilog-insert-one-definition
7432 ;; Want "type x" or "output type x", not "wire type x"
7433 (cond ((verilog-sig-type sig)
7435 (if (not (equal direction "wire"))
7436 (concat direction " "))
7437 (verilog-sig-type sig)))
7440 (insert (if v2k "," ";"))
7441 (if (or (not (verilog-sig-comment sig))
7442 (equal "" (verilog-sig-comment sig)))
7444 (indent-to (max 48 (+ indent-pt 40)))
7445 (insert (concat "// " (verilog-sig-comment sig) "\n")))
7446 (setq sigs (cdr sigs)))))
7449 (if (not (boundp 'indent-pt))
7450 (defvar indent-pt nil "Local used by insert-indent")))
7452 (defun verilog-insert-indent (&rest stuff)
7453 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
7454 Presumes that any newlines end a list element."
7455 (let ((need-indent t))
7457 (if need-indent (indent-to indent-pt))
7458 (setq need-indent nil)
7459 (insert (car stuff))
7460 (setq need-indent (string-match "\n$" (car stuff))
7461 stuff (cdr stuff)))))
7462 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
7464 (defun verilog-repair-open-comma ()
7465 "If backwards-from-point is other than a open parenthesis insert comma."
7467 (verilog-backward-syntactic-ws)
7468 (when (save-excursion
7470 (and (not (looking-at "[(,]"))
7472 (verilog-re-search-backward "[(`]" nil t)
7476 (defun verilog-repair-close-comma ()
7477 "If point is at a comma followed by a close parenthesis, fix it.
7478 This repairs those mis-inserted by a AUTOARG."
7479 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
7481 (verilog-forward-close-paren)
7483 (verilog-backward-syntactic-ws)
7485 (when (looking-at ",")
7488 (defun verilog-get-list (start end)
7489 "Return the elements of a comma separated list between START and END."
7491 (let ((my-list (list))
7494 (while (< (point) end)
7495 (when (re-search-forward "\\([^,{]+\\)" end t)
7496 (setq my-string (verilog-string-remove-spaces (match-string 1)))
7497 (setq my-list (nconc my-list (list my-string) ))
7498 (goto-char (match-end 0))))
7501 (defun verilog-make-width-expression (range-exp)
7502 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
7504 (cond ((not range-exp)
7507 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
7508 (setq range-exp (match-string 1 range-exp)))
7509 (cond ((not range-exp)
7511 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$"
7514 (1+ (abs (- (string-to-number (match-string 1 range-exp))
7515 (string-to-number (match-string 2 range-exp)))))))
7516 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
7517 (concat "(1+(" (match-string 1 range-exp) ")"
7518 (if (equal "0" (match-string 2 range-exp))
7519 "" ;; Don't bother with -(0)
7520 (concat "-(" (match-string 2 range-exp) ")"))
7523 ;;(verilog-make-width-expression "`A:`B")
7525 (defun verilog-typedef-name-p (variable-name)
7526 "Return true if the VARIABLE-NAME is a type definition."
7527 (when verilog-typedef-regexp
7528 (string-match verilog-typedef-regexp variable-name)))
7534 (defun verilog-delete-autos-lined ()
7535 "Delete autos that occupy multiple lines, between begin and end comments."
7539 (looking-at "\\s-*// Beginning")
7540 (search-forward "// End of automatic" nil t))
7543 (delete-region pt (point))
7546 (defun verilog-forward-close-paren ()
7547 "Find the close parenthesis that match the current point.
7548 Ignore other close parenthesis with matching open parens."
7551 (unless (verilog-re-search-forward-quick "[()]" nil t)
7552 (error "%s: Mismatching ()" (verilog-point-text)))
7553 (cond ((= (preceding-char) ?\( )
7554 (setq parens (1+ parens)))
7555 ((= (preceding-char) ?\) )
7556 (setq parens (1- parens)))))))
7558 (defun verilog-backward-open-paren ()
7559 "Find the open parenthesis that match the current point.
7560 Ignore other open parenthesis with matching close parens."
7563 (unless (verilog-re-search-backward-quick "[()]" nil t)
7564 (error "%s: Mismatching ()" (verilog-point-text)))
7565 (cond ((= (following-char) ?\) )
7566 (setq parens (1+ parens)))
7567 ((= (following-char) ?\( )
7568 (setq parens (1- parens)))))))
7570 (defun verilog-backward-open-bracket ()
7571 "Find the open bracket that match the current point.
7572 Ignore other open bracket with matching close bracket."
7575 (unless (verilog-re-search-backward-quick "[][]" nil t)
7576 (error "%s: Mismatching []" (verilog-point-text)))
7577 (cond ((= (following-char) ?\] )
7578 (setq parens (1+ parens)))
7579 ((= (following-char) ?\[ )
7580 (setq parens (1- parens)))))))
7582 (defun verilog-delete-to-paren ()
7583 "Delete the automatic inst/sense/arg created by autos.
7584 Deletion stops at the matching end parenthesis."
7585 (delete-region (point)
7587 (verilog-backward-open-paren)
7588 (forward-sexp 1) ;; Moves to paren that closes argdecl's
7592 (defun verilog-auto-star-safe ()
7593 "Return if a .* AUTOINST is safe to delete or expand.
7594 It was created by the AUTOS themselves, or by the user."
7595 (and verilog-auto-star-expand
7596 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
7598 (defun verilog-delete-auto-star-all ()
7599 "Delete a .* AUTOINST, if it is safe."
7600 (when (verilog-auto-star-safe)
7601 (verilog-delete-to-paren)))
7603 (defun verilog-delete-auto-star-implicit ()
7604 "Delete all .* implicit connections created by `verilog-auto-star'.
7605 This function will be called automatically at save unless
7606 `verilog-auto-star-save' is set, any non-templated expanded pins will be
7609 (let (paren-pt indent have-close-paren)
7611 (goto-char (point-min))
7612 ;; We need to match these even outside of comments.
7613 ;; For reasonable performance, we don't check if inside comments, sorry.
7614 (while (re-search-forward "// Implicit \\.\\*" nil t)
7615 (setq paren-pt (point))
7617 (setq have-close-paren
7619 (when (search-forward ");" paren-pt t)
7620 (setq indent (current-indentation))
7622 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
7623 (when have-close-paren
7624 ;; Delete extra commentary
7628 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
7629 (delete-region (match-beginning 0) (match-end 0))))
7630 ;; If it is simple, we can put the ); on the same line as the last text
7631 (let ((rtn-pt (point)))
7633 (while (progn (backward-char 1)
7634 (looking-at "[ \t\n\f]")))
7635 (when (looking-at ",")
7636 (delete-region (+ 1 (point)) rtn-pt))))
7640 ;; Still need to kill final comma - always is one as we put one after the .*
7641 (re-search-backward ",")
7642 (delete-char 1))))))
7644 (defun verilog-delete-auto ()
7645 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
7646 Use \\[verilog-auto] to re-insert the updated AUTOs.
7648 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
7649 called before and after this function, respectively."
7652 (if (buffer-file-name)
7653 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
7654 ;; Allow user to customize
7655 (run-hooks 'verilog-before-delete-auto-hook)
7657 ;; Remove those that have multi-line insertions, possibly with parameters
7658 (verilog-auto-re-search-do
7661 (verilog-regexp-words
7662 `("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
7663 "AUTOINOUT" "AUTOINOUTMODULE" "AUTOINPUT" "AUTOOUTPUT"
7665 "AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
7666 "AUTOUNUSED" "AUTOWIRE")))
7667 "\\(\\|([^)]*)\\|(\"[^\"]*\")\\)" ; Optional parens or quoted parameter
7669 'verilog-delete-autos-lined)
7670 ;; Remove those that are in parenthesis
7671 (verilog-auto-re-search-do
7674 (verilog-regexp-words
7675 `("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
7678 'verilog-delete-to-paren)
7679 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
7680 (verilog-auto-re-search-do "\\.\\*"
7681 'verilog-delete-auto-star-all)
7682 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
7683 (goto-char (point-min))
7684 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
7688 (run-hooks 'verilog-delete-auto-hook)))
7694 (defun verilog-inject-auto ()
7695 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
7697 Any always @ blocks with sensitivity lists that match computed lists will
7698 be replaced with /*AS*/ comments.
7700 Any cells will get /*AUTOINST*/ added to the end of the pin list.
7701 Pins with have identical names will be deleted.
7703 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
7704 support adding new ports. You may wish to delete older ports yourself.
7708 module ExampInject (i, o);
7719 Typing \\[verilog-inject-auto] will make this into:
7721 module ExampInject (i, o/*AUTOARG*/
7726 always @ (/*AS*/i or j)
7737 (defun verilog-inject-arg ()
7738 "Inject AUTOARG into new code. See `verilog-inject-auto'."
7739 ;; Presume one module per file.
7741 (goto-char (point-min))
7742 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
7743 (let ((endmodp (save-excursion
7744 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
7746 ;; See if there's already a comment .. inside a comment so not verilog-re-search
7747 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
7748 (verilog-re-search-forward-quick ";" nil t)
7750 (verilog-backward-syntactic-ws)
7751 (backward-char 1) ; Moves to paren that closes argdecl's
7752 (when (looking-at ")")
7753 (insert "/*AUTOARG*/")))))))
7755 (defun verilog-inject-sense ()
7756 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
7758 (goto-char (point-min))
7759 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
7760 (let ((start-pt (point))
7761 (modi (verilog-modi-current))
7766 (backward-char 1) ;; End )
7767 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
7768 (setq pre-sigs (verilog-signals-from-signame
7769 (verilog-read-signals start-pt (point)))
7770 got-sigs (verilog-auto-sense-sigs modi nil))
7771 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
7772 (verilog-signals-not-in got-sigs pre-sigs)))
7773 (delete-region start-pt (point))
7774 (insert "/*AS*/")))))))
7776 (defun verilog-inject-inst ()
7777 "Inject AUTOINST into new code. See `verilog-inject-auto'."
7779 (goto-char (point-min))
7780 ;; It's hard to distinguish modules; we'll instead search for pins.
7781 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
7782 (verilog-backward-open-paren) ;; Inst start
7784 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
7786 (verilog-forward-close-paren)) ;; Parameters done
7789 (let ((indent-pt (+ (current-column)))
7790 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
7791 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
7792 (goto-char end-pt)) ;; Already there, continue search with next instance
7794 ;; Delete identical interconnect
7795 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
7796 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
7797 (delete-region (match-beginning 0) (match-end 0))
7798 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
7799 (while (or (looking-at "[ \t\n\f,]+")
7800 (looking-at "//[^\n]*"))
7801 (delete-region (match-beginning 0) (match-end 0))
7802 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
7803 (verilog-forward-close-paren)
7805 ;; Not verilog-re-search, as we don't want to strip comments
7806 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
7807 (delete-region (match-beginning 0) (match-end 0)))
7809 (indent-to indent-pt)
7810 (insert "/*AUTOINST*/")))))))))
7816 (defun verilog-auto-save-check ()
7817 "On saving see if we need auto update."
7818 (cond ((not verilog-auto-save-policy)) ; disabled
7819 ((not (save-excursion
7821 (let ((case-fold-search nil))
7822 (goto-char (point-min))
7823 (re-search-forward "AUTO" nil t))))))
7824 ((eq verilog-auto-save-policy 'force)
7826 ((not (buffer-modified-p)))
7827 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
7828 ((eq verilog-auto-save-policy 'detect)
7831 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
7833 ;; Don't ask again if didn't update
7834 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))))
7835 (when (not verilog-auto-star-save)
7836 (verilog-delete-auto-star-implicit))
7837 nil) ;; Always return nil -- we don't write the file ourselves
7839 (defun verilog-auto-read-locals ()
7840 "Return file local variable segment at bottom of file."
7842 (goto-char (point-max))
7843 (if (re-search-backward "Local Variables:" nil t)
7844 (buffer-substring-no-properties (point) (point-max))
7847 (defun verilog-auto-reeval-locals (&optional force)
7848 "Read file local variable segment at bottom of file if it has changed.
7849 If FORCE, always reread it."
7850 (make-local-variable 'verilog-auto-last-file-locals)
7851 (let ((curlocal (verilog-auto-read-locals)))
7852 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
7853 (setq verilog-auto-last-file-locals curlocal)
7854 ;; Note this may cause this function to be recursively invoked.
7855 ;; The above when statement will prevent it from recursing forever.
7856 (hack-local-variables)
7863 (defun verilog-auto-arg-ports (sigs message indent-pt)
7864 "Print a list of ports for a AUTOINST.
7865 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
7868 (indent-to indent-pt)
7872 (indent-to indent-pt)
7874 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
7876 (indent-to indent-pt))
7878 (insert (verilog-sig-name (car sigs)) ",")
7879 (setq sigs (cdr sigs)
7882 (defun verilog-auto-arg ()
7883 "Expand AUTOARG statements.
7884 Replace the argument declarations at the beginning of the
7885 module with ones automatically derived from input and output
7886 statements. This can be dangerous if the module is instantiated
7887 using position-based connections, so use only name-based when
7888 instantiating the resulting module. Long lines are split based
7889 on the `fill-column', see \\[set-fill-column].
7892 Concatenation and outputting partial busses is not supported.
7894 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
7898 module ExampArg (/*AUTOARG*/);
7903 Typing \\[verilog-auto] will make this into:
7905 module ExampArg (/*AUTOARG*/
7915 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
7916 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
7917 conservative guess on adding a comma for the first signal, if you have
7918 any ifdefs or complicated expressions before the AUTOARG you will need
7919 to choose the comma yourself.
7921 Avoid declaring ports manually, as it makes code harder to maintain."
7923 (let ((modi (verilog-modi-current))
7924 (skip-pins (aref (verilog-read-arg-pins) 0)))
7925 (verilog-repair-open-comma)
7926 (verilog-auto-arg-ports (verilog-signals-not-in
7927 (verilog-modi-get-outputs modi)
7930 verilog-indent-level-declaration)
7931 (verilog-auto-arg-ports (verilog-signals-not-in
7932 (verilog-modi-get-inouts modi)
7935 verilog-indent-level-declaration)
7936 (verilog-auto-arg-ports (verilog-signals-not-in
7937 (verilog-modi-get-inputs modi)
7940 verilog-indent-level-declaration)
7941 (verilog-repair-close-comma)
7942 (unless (eq (char-before) ?/ )
7944 (indent-to verilog-indent-level-declaration))))
7946 (defun verilog-auto-inst-port-map (port-st)
7949 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
7950 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
7951 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
7952 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
7953 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
7955 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
7956 "Print out a instantiation connection for this PORT-ST.
7957 Insert to INDENT-PT, use template TPL-LIST.
7958 @ are instantiation numbers, replaced with TPL-NUM.
7959 @\"(expression @)\" are evaluated, with @ as a variable.
7960 If FOR-STAR add comment it is a .* expansion."
7961 (let* ((port (verilog-sig-name port-st))
7962 (tpl-ass (or (assoc port (car tpl-list))
7963 (verilog-auto-inst-port-map port-st)))
7964 ;; vl-* are documented for user use
7965 (vl-name (verilog-sig-name port-st))
7966 (vl-width (verilog-sig-width port-st))
7967 (vl-bits (if (or verilog-auto-inst-vector
7968 (not (assoc port vector-skip-list))
7969 (not (equal (verilog-sig-bits port-st)
7970 (verilog-sig-bits (assoc port vector-skip-list)))))
7971 (or (verilog-sig-bits port-st) "")
7973 ;; Default if not found
7974 (tpl-net (if (verilog-sig-multidim port-st)
7975 (concat port "/*" (verilog-sig-multidim-string port-st)
7977 (concat port vl-bits)))
7978 (case-fold-search nil))
7980 (cond (tpl-ass ; Template of exact port name
7981 (setq tpl-net (nth 1 tpl-ass)))
7982 ((nth 1 tpl-list) ; Wildcards in template, search them
7983 (let ((wildcards (nth 1 tpl-list)))
7985 (when (string-match (nth 0 (car wildcards)) port)
7986 (setq tpl-ass (car wildcards) ; so allow @ parsing
7987 tpl-net (replace-match (nth 1 (car wildcards))
7989 (setq wildcards (cdr wildcards))))))
7990 ;; Parse Templated variable
7992 ;; Evaluate @"(lispcode)"
7993 (when (string-match "@\".*[^\\]\"" tpl-net)
7994 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
7997 (substring tpl-net 0 (match-beginning 0))
7999 (let* ((expr (match-string 1 tpl-net))
8002 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
8003 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
8004 (prin1 (eval (car (read-from-string expr)))
8005 (lambda (ch) ())))))
8006 (if (numberp value) (setq value (number-to-string value)))
8008 (substring tpl-net (match-end 0))))))
8009 ;; Replace @ and [] magic variables in final output
8010 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
8011 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net)))
8012 (indent-to indent-pt)
8014 (indent-to verilog-auto-inst-column)
8015 (insert "(" tpl-net "),")
8017 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8018 verilog-auto-inst-column))
8019 (insert " // Templated")
8020 (when verilog-auto-inst-template-numbers
8021 (insert " T" (int-to-string (nth 2 tpl-ass))
8022 " L" (int-to-string (nth 3 tpl-ass)))))
8024 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
8025 verilog-auto-inst-column))
8026 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
8028 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
8029 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
8030 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
8032 (defun verilog-auto-inst-first ()
8033 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
8034 ;; Do we need a trailing comma?
8035 ;; There maybe a ifdef or something similar before us. What a mess. Thus
8036 ;; to avoid trouble we only insert on preceeding ) or *.
8037 ;; Insert first port on new line
8038 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
8040 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
8041 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
8045 (defun verilog-auto-star ()
8046 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
8048 If `verilog-auto-star-expand' is set, .* pins are treated if they were
8049 AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
8050 will also ignore any .* that are not last in your pin list (this prevents
8051 it from deleting pins following the .* when it expands the AUTOINST.)
8053 On writing your file, unless `verilog-auto-star-save' is set, any
8054 non-templated expanded pins will be removed. You may do this at any time
8055 with \\[verilog-delete-auto-star-implicit].
8057 If you are converting a module to use .* for the first time, you may wish
8058 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
8060 See `verilog-auto-inst' for examples, templates, and more information."
8061 (when (verilog-auto-star-safe)
8062 (verilog-auto-inst)))
8064 (defun verilog-auto-inst ()
8065 "Expand AUTOINST statements, as part of \\[verilog-auto].
8066 Replace the pin connections to an instantiation with ones
8067 automatically derived from the module header of the instantiated netlist.
8069 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
8070 and delete them before saving unless `verilog-auto-star-save' is set.
8071 See `verilog-auto-star' for more information.
8074 Module names must be resolvable to filenames by adding a
8075 `verilog-library-extensions', and being found in the same directory, or
8076 by changing the variable `verilog-library-flags' or
8077 `verilog-library-directories'. Macros `modname are translated through the
8078 vh-{name} Emacs variable, if that is not found, it just ignores the `.
8080 In templates you must have one signal per line, ending in a ), or ));,
8081 and have proper () nesting, including a final ); to end the template.
8083 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8085 SystemVerilog multidimensional input/output has only experimental support.
8087 For example, first take the submodule InstModule.v:
8089 module InstModule (o,i)
8092 wire [31:0] o = {32{i}};
8095 This is then used in a upper level module:
8097 module ExampInst (o,i)
8104 Typing \\[verilog-auto] will make this into:
8106 module ExampInst (o,i)
8117 Where the list of inputs and outputs came from the inst module.
8121 Unless you are instantiating a module multiple times, or the module is
8122 something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
8123 It just makes for unmaintainable code. To sanitize signal names, try
8124 vrename from http://www.veripool.com.
8126 When you need to violate this suggestion there are two ways to list
8127 exceptions, placing them before the AUTOINST, or using templates.
8129 Any ports defined before the /*AUTOINST*/ are not included in the list of
8130 automatics. This is similar to making a template as described below, but
8131 is restricted to simple connections just like you normally make. Also note
8132 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
8133 you have the appropriate // Input or // Output comment, and exactly the
8134 same line formatting as AUTOINST itself uses.
8138 .i (my_i_dont_mess_with_it),
8146 For multiple instantiations based upon a single template, create a
8147 commented out template:
8149 /* InstModule AUTO_TEMPLATE (
8154 Templates go ABOVE the instantiation(s). When an instantiation is
8155 expanded `verilog-mode' simply searches up for the closest template.
8156 Thus you can have multiple templates for the same module, just alternate
8157 between the template for an instantiation and the instantiation itself.
8159 The module name must be the same as the name of the module in the
8160 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
8161 words and capitalized. Only signals that must be different for each
8162 instantiation need to be listed.
8164 Inside a template, a [] in a connection name (with nothing else inside
8165 the brackets) will be replaced by the same bus subscript as it is being
8166 connected to, or the [] will be removed if it is a single bit signal.
8167 Generally it is a good idea to do this for all connections in a template,
8168 as then they will work for any width signal, and with AUTOWIRE. See
8169 PTL_BUS becoming PTL_BUSNEW below.
8171 If you have a complicated template, set `verilog-auto-inst-template-numbers'
8172 to see which regexps are matching. Don't leave that mode set after
8173 debugging is completed though, it will result in lots of extra differences
8174 and merge conflicts.
8178 /* InstModule AUTO_TEMPLATE (
8179 .ptl_bus (ptl_busnew[]),
8182 InstModule ms2m (/*AUTOINST*/);
8184 Typing \\[verilog-auto] will make this into:
8186 InstModule ms2m (/*AUTOINST*/
8188 .NotInTemplate (NotInTemplate),
8189 .ptl_bus (ptl_busnew[3:0]), // Templated
8194 It is common to instantiate a cell multiple times, so templates make it
8195 trivial to substitute part of the cell name into the connection name.
8197 /* InstName AUTO_TEMPLATE <optional \"REGEXP\"> (
8199 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
8203 If no regular expression is provided immediately after the AUTO_TEMPLATE
8204 keyword, then the @ character in any connection names will be replaced
8205 with the instantiation number; the first digits found in the cell's
8208 If a regular expression is provided, the @ character will be replaced
8209 with the first \(\) grouping that matches against the cell name. Using a
8210 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
8211 regexp is provided. If you use multiple layers of parenthesis,
8212 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
8213 characters after test and before _, whereas
8214 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
8219 /* InstModule AUTO_TEMPLATE (
8220 .ptl_mapvalidx (ptl_mapvalid[@]),
8221 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
8224 InstModule ms2m (/*AUTOINST*/);
8226 Typing \\[verilog-auto] will make this into:
8228 InstModule ms2m (/*AUTOINST*/
8230 .ptl_mapvalidx (ptl_mapvalid[2]),
8231 .ptl_mapvalidp1x (ptl_mapvalid[3]));
8233 Note the @ character was replaced with the 2 from \"ms2m\".
8235 Alternatively, using a regular expression for @:
8237 /* InstModule AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
8238 .ptl_mapvalidx (@_ptl_mapvalid),
8239 .ptl_mapvalidp1x (ptl_mapvalid_@),
8242 InstModule ms2_FOO (/*AUTOINST*/);
8243 InstModule ms2_BAR (/*AUTOINST*/);
8245 Typing \\[verilog-auto] will make this into:
8247 InstModule ms2_FOO (/*AUTOINST*/
8249 .ptl_mapvalidx (FOO_ptl_mapvalid),
8250 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
8251 InstModule ms2_BAR (/*AUTOINST*/
8253 .ptl_mapvalidx (BAR_ptl_mapvalid),
8254 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
8259 A template entry of the form
8261 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
8263 will apply an Emacs style regular expression search for any port beginning
8264 in pci_req followed by numbers and ending in _l and connecting that to
8265 the pci_req_jtag_[] net, with the bus subscript coming from what matches
8266 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
8268 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
8269 does the same thing. (Note a @ in the connection/replacement text is
8270 completely different -- still use \\1 there!) Thus this is the same as
8273 .pci_req@_l (pci_req_jtag_[\\1]),
8275 Here's another example to remove the _l, useful when naming conventions
8276 specify _ alone to mean active low. Note the use of [] to keep the bus
8279 .\\(.*\\)_l (\\1_[]),
8283 First any regular expression template is expanded.
8285 If the syntax @\"( ... )\" is found in a connection, the expression in
8286 quotes will be evaluated as a Lisp expression, with @ replaced by the
8287 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
8288 4 into the brackets. Quote all double-quotes inside the expression with
8289 a leading backslash (\\\"). There are special variables defined that are
8290 useful in these Lisp functions:
8292 vl-name Name portion of the input/output port.
8293 vl-bits Bus bits portion of the input/output port ('[2:0]').
8294 vl-width Width of the input/output port ('3' for [2:0]).
8295 May be a (...) expression if bits isn't a constant.
8296 vl-dir Direction of the pin input/output/inout.
8297 vl-cell-type Module name/type of the cell ('InstModule').
8298 vl-cell-name Instance name of the cell ('instName').
8300 Normal Lisp variables may be used in expressions. See
8301 `verilog-read-defines' which can set vh-{definename} variables for use
8302 here. Also, any comments of the form:
8304 /*AUTO_LISP(setq foo 1)*/
8306 will evaluate any Lisp expression inside the parenthesis between the
8307 beginning of the buffer and the point of the AUTOINST. This allows
8308 functions to be defined or variables to be changed between instantiations.
8310 Note that when using lisp expressions errors may occur when @ is not a
8311 number; you may need to use the standard Emacs Lisp functions
8312 `number-to-string' and `string-to-number'.
8314 After the evaluation is completed, @ substitution and [] substitution
8319 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
8320 (indent-pt (save-excursion (verilog-backward-open-paren)
8321 (1+ (current-column))))
8322 (verilog-auto-inst-column (max verilog-auto-inst-column
8323 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8324 (modi (verilog-modi-current))
8325 (vector-skip-list (unless verilog-auto-inst-vector
8326 (verilog-modi-get-signals modi)))
8327 submod submodi inst skip-pins tpl-list tpl-num did-first)
8328 ;; Find module name that is instantiated
8329 (setq submod (verilog-read-inst-module)
8330 inst (verilog-read-inst-name)
8333 skip-pins (aref (verilog-read-inst-pins) 0))
8335 ;; Parse any AUTO_LISP() before here
8336 (verilog-read-auto-lisp (point-min) pt)
8338 ;; Lookup position, etc of submodule
8339 ;; Note this may raise an error
8340 (when (setq submodi (verilog-modi-lookup submod t))
8341 ;; If there's a number in the instantiation, it may be a argument to the
8342 ;; automatic variable instantiation program.
8343 (let* ((tpl-info (verilog-read-auto-template submod))
8344 (tpl-regexp (aref tpl-info 0)))
8345 (setq tpl-num (if (string-match tpl-regexp inst)
8346 (match-string 1 inst)
8348 tpl-list (aref tpl-info 1)))
8349 ;; Find submodule's signals and dump
8350 (let ((sig-list (verilog-signals-not-in
8351 (verilog-modi-get-outputs submodi)
8355 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8356 (indent-to indent-pt)
8357 ;; Note these are searched for in verilog-read-sub-decls.
8358 (insert "// Outputs\n")
8359 (mapc (lambda (port)
8360 (verilog-auto-inst-port port indent-pt
8361 tpl-list tpl-num for-star))
8363 (let ((sig-list (verilog-signals-not-in
8364 (verilog-modi-get-inouts submodi)
8368 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8369 (indent-to indent-pt)
8370 (insert "// Inouts\n")
8371 (mapc (lambda (port)
8372 (verilog-auto-inst-port port indent-pt
8373 tpl-list tpl-num for-star))
8375 (let ((sig-list (verilog-signals-not-in
8376 (verilog-modi-get-inputs submodi)
8380 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8381 (indent-to indent-pt)
8382 (insert "// Inputs\n")
8383 (mapc (lambda (port)
8384 (verilog-auto-inst-port port indent-pt
8385 tpl-list tpl-num for-star))
8390 (re-search-backward "," pt t)
8393 (search-forward "\n") ;; Added by inst-port
8394 (delete-backward-char 1)
8395 (if (search-forward ")" nil t) ;; From user, moved up a line
8396 (delete-backward-char 1))
8397 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
8398 (delete-backward-char 1)))))))))
8400 (defun verilog-auto-inst-param ()
8401 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
8402 Replace the parameter connections to an instantiation with ones
8403 automatically derived from the module header of the instantiated netlist.
8405 See \\[verilog-auto-inst] for limitations, and templates to customize the
8408 For example, first take the submodule InstModule.v:
8410 module InstModule (o,i)
8414 This is then used in a upper level module:
8416 module ExampInst (o,i)
8418 InstModule #(/*AUTOINSTPARAM*/)
8419 instName (/*AUTOINST*/);
8422 Typing \\[verilog-auto] will make this into:
8424 module ExampInst (o,i)
8427 InstModule #(/*AUTOINSTPARAM*/
8430 instName (/*AUTOINST*/);
8433 Where the list of parameter connections come from the inst module.
8437 You can customize the parameter connections using AUTO_TEMPLATEs,
8438 just as you would with \\[verilog-auto-inst]."
8442 (indent-pt (save-excursion (verilog-backward-open-paren)
8443 (1+ (current-column))))
8444 (verilog-auto-inst-column (max verilog-auto-inst-column
8445 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
8446 (modi (verilog-modi-current))
8447 (vector-skip-list (unless verilog-auto-inst-vector
8448 (verilog-modi-get-signals modi)))
8449 submod submodi inst skip-pins tpl-list tpl-num did-first)
8450 ;; Find module name that is instantiated
8451 (setq submod (save-excursion
8452 ;; Get to the point where AUTOINST normally is to read the module
8453 (verilog-re-search-forward-quick "[(;]" nil nil)
8454 (verilog-read-inst-module))
8455 inst (save-excursion
8456 ;; Get to the point where AUTOINST normally is to read the module
8457 (verilog-re-search-forward-quick "[(;]" nil nil)
8458 (verilog-read-inst-name))
8461 skip-pins (aref (verilog-read-inst-pins) 0))
8463 ;; Parse any AUTO_LISP() before here
8464 (verilog-read-auto-lisp (point-min) pt)
8466 ;; Lookup position, etc of submodule
8467 ;; Note this may raise an error
8468 (when (setq submodi (verilog-modi-lookup submod t))
8469 ;; If there's a number in the instantiation, it may be a argument to the
8470 ;; automatic variable instantiation program.
8471 (let* ((tpl-info (verilog-read-auto-template submod))
8472 (tpl-regexp (aref tpl-info 0)))
8473 (setq tpl-num (if (string-match tpl-regexp inst)
8474 (match-string 1 inst)
8476 tpl-list (aref tpl-info 1)))
8477 ;; Find submodule's signals and dump
8478 (let ((sig-list (verilog-signals-not-in
8479 (verilog-modi-get-gparams submodi)
8481 (vl-dir "parameter"))
8483 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
8484 (indent-to indent-pt)
8485 ;; Note these are searched for in verilog-read-sub-decls.
8486 (insert "// Parameters\n")
8487 (mapc (lambda (port)
8488 (verilog-auto-inst-port port indent-pt
8489 tpl-list tpl-num nil))
8494 (re-search-backward "," pt t)
8497 (search-forward "\n") ;; Added by inst-port
8498 (delete-backward-char 1)
8499 (if (search-forward ")" nil t) ;; From user, moved up a line
8500 (delete-backward-char 1)))))))))
8502 (defun verilog-auto-reg ()
8503 "Expand AUTOREG statements, as part of \\[verilog-auto].
8504 Make reg statements for any output that isn't already declared,
8505 and isn't a wire output from a block.
8508 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8510 This does NOT work on memories, declare those yourself.
8514 module ExampReg (o,i)
8521 Typing \\[verilog-auto] will make this into:
8523 module ExampReg (o,i)
8527 // Beginning of automatic regs (for this module's undeclared outputs)
8529 // End of automatics
8533 ;; Point must be at insertion point.
8534 (let* ((indent-pt (current-indentation))
8535 (modi (verilog-modi-current))
8536 (sig-list (verilog-signals-not-in
8537 (verilog-modi-get-outputs modi)
8538 (append (verilog-modi-get-wires modi)
8539 (verilog-modi-get-regs modi)
8540 (verilog-modi-get-assigns modi)
8541 (verilog-modi-get-consts modi)
8542 (verilog-modi-get-gparams modi)
8543 (verilog-modi-get-sub-outputs modi)
8544 (verilog-modi-get-sub-inouts modi)))))
8547 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
8548 (verilog-insert-definition sig-list "reg" indent-pt nil)
8549 (verilog-modi-cache-add-regs modi sig-list)
8550 (verilog-insert-indent "// End of automatics\n")))))
8552 (defun verilog-auto-reg-input ()
8553 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
8554 Make reg statements instantiation inputs that aren't already declared.
8555 This is useful for making a top level shell for testing the module that is
8559 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
8561 This does NOT work on memories, declare those yourself.
8563 An example (see `verilog-auto-inst' for what else is going on here):
8565 module ExampRegInput (o,i)
8573 Typing \\[verilog-auto] will make this into:
8575 module ExampRegInput (o,i)
8579 // Beginning of automatic reg inputs (for undeclared ...
8580 reg [31:0] iv; // From inst of inst.v
8581 // End of automatics
8590 ;; Point must be at insertion point.
8591 (let* ((indent-pt (current-indentation))
8592 (modi (verilog-modi-current))
8593 (sig-list (verilog-signals-combine-bus
8594 (verilog-signals-not-in
8595 (append (verilog-modi-get-sub-inputs modi)
8596 (verilog-modi-get-sub-inouts modi))
8597 (verilog-modi-get-signals modi)))))
8600 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
8601 (verilog-insert-definition sig-list "reg" indent-pt nil)
8602 (verilog-modi-cache-add-regs modi sig-list)
8603 (verilog-insert-indent "// End of automatics\n")))))
8605 (defun verilog-auto-wire ()
8606 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
8607 Make wire statements for instantiations outputs that aren't
8611 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
8612 and all busses must have widths, such as those from AUTOINST, or using []
8615 This does NOT work on memories or SystemVerilog .name connections,
8616 declare those yourself.
8618 Verilog mode will add \"Couldn't Merge\" comments to signals it cannot
8619 determine how to bus together. This occurs when you have ports with
8620 non-numeric or non-sequential bus subscripts. If Verilog mode
8621 mis-guessed, you'll have to declare them yourself.
8623 An example (see `verilog-auto-inst' for what else is going on here):
8625 module ExampWire (o,i)
8633 Typing \\[verilog-auto] will make this into:
8635 module ExampWire (o,i)
8639 // Beginning of automatic wires
8640 wire [31:0] ov; // From inst of inst.v
8641 // End of automatics
8651 ;; Point must be at insertion point.
8652 (let* ((indent-pt (current-indentation))
8653 (modi (verilog-modi-current))
8654 (sig-list (verilog-signals-combine-bus
8655 (verilog-signals-not-in
8656 (append (verilog-modi-get-sub-outputs modi)
8657 (verilog-modi-get-sub-inouts modi))
8658 (verilog-modi-get-signals modi)))))
8661 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
8662 (verilog-insert-definition sig-list "wire" indent-pt nil)
8663 (verilog-modi-cache-add-wires modi sig-list)
8664 (verilog-insert-indent "// End of automatics\n")
8665 (when nil ;; Too slow on huge modules, plus makes everyone's module change
8668 (verilog-pretty-declarations quiet)
8670 (verilog-pretty-expr "//"))))))
8672 (defun verilog-auto-output (&optional with-params)
8673 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
8674 Make output statements for any output signal from an /*AUTOINST*/ that
8675 isn't a input to another AUTOINST. This is useful for modules which
8676 only instantiate other modules.
8679 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8681 If placed inside the parenthesis of a module declaration, it creates
8682 Verilog 2001 style, else uses Verilog 1995 style.
8684 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8685 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8687 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8689 Signals matching `verilog-auto-output-ignore-regexp' are not included.
8691 An example (see `verilog-auto-inst' for what else is going on here):
8693 module ExampOutput (ov,i)
8700 Typing \\[verilog-auto] will make this into:
8702 module ExampOutput (ov,i)
8705 // Beginning of automatic outputs (from unused autoinst outputs)
8706 output [31:0] ov; // From inst of inst.v
8707 // End of automatics
8716 You may also provide an optional regular expression, in which case only
8717 signals matching the regular expression will be included. For example the
8718 same expansion will result from only extracting outputs starting with ov:
8720 /*AUTOOUTPUT(\"^ov\")*/"
8722 ;; Point must be at insertion point.
8723 (let* ((indent-pt (current-indentation))
8724 (regexp (and with-params
8725 (nth 0 (verilog-read-auto-params 1))))
8726 (v2k (verilog-in-paren))
8727 (modi (verilog-modi-current))
8728 (sig-list (verilog-signals-not-in
8729 (verilog-modi-get-sub-outputs modi)
8730 (append (verilog-modi-get-outputs modi)
8731 (verilog-modi-get-inouts modi)
8732 (verilog-modi-get-sub-inputs modi)
8733 (verilog-modi-get-sub-inouts modi)))))
8735 (setq sig-list (verilog-signals-matching-regexp
8737 (setq sig-list (verilog-signals-not-matching-regexp
8738 sig-list verilog-auto-output-ignore-regexp))
8740 (when v2k (verilog-repair-open-comma))
8742 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
8743 (verilog-insert-definition sig-list "output" indent-pt v2k)
8744 (verilog-modi-cache-add-outputs modi sig-list)
8745 (verilog-insert-indent "// End of automatics\n"))
8746 (when v2k (verilog-repair-close-comma)))))
8748 (defun verilog-auto-output-every ()
8749 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
8750 Make output statements for any signals that aren't primary inputs or
8751 outputs already. This makes every signal in the design a output. This is
8752 useful to get Synopsys to preserve every signal in the design, since it
8753 won't optimize away the outputs.
8757 module ExampOutputEvery (o,i,tempa,tempb)
8766 Typing \\[verilog-auto] will make this into:
8768 module ExampOutputEvery (o,i,tempa,tempb)
8772 // Beginning of automatic outputs (every signal)
8775 // End of automatics
8781 ;;Point must be at insertion point
8782 (let* ((indent-pt (current-indentation))
8783 (v2k (verilog-in-paren))
8784 (modi (verilog-modi-current))
8785 (sig-list (verilog-signals-combine-bus
8786 (verilog-signals-not-in
8787 (verilog-modi-get-signals modi)
8788 (verilog-modi-get-ports modi)))))
8790 (when v2k (verilog-repair-open-comma))
8792 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
8793 (verilog-insert-definition sig-list "output" indent-pt v2k)
8794 (verilog-modi-cache-add-outputs modi sig-list)
8795 (verilog-insert-indent "// End of automatics\n"))
8796 (when v2k (verilog-repair-close-comma)))))
8798 (defun verilog-auto-input (&optional with-params)
8799 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
8800 Make input statements for any input signal into an /*AUTOINST*/ that
8801 isn't declared elsewhere inside the module. This is useful for modules which
8802 only instantiate other modules.
8805 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8807 If placed inside the parenthesis of a module declaration, it creates
8808 Verilog 2001 style, else uses Verilog 1995 style.
8810 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8811 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8813 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8815 Signals matching `verilog-auto-input-ignore-regexp' are not included.
8817 An example (see `verilog-auto-inst' for what else is going on here):
8819 module ExampInput (ov,i)
8826 Typing \\[verilog-auto] will make this into:
8828 module ExampInput (ov,i)
8831 // Beginning of automatic inputs (from unused autoinst inputs)
8832 input i; // From inst of inst.v
8833 // End of automatics
8842 You may also provide an optional regular expression, in which case only
8843 signals matching the regular expression will be included. For example the
8844 same expansion will result from only extracting inputs starting with i:
8846 /*AUTOINPUT(\"^i\")*/"
8848 (let* ((indent-pt (current-indentation))
8849 (regexp (and with-params
8850 (nth 0 (verilog-read-auto-params 1))))
8851 (v2k (verilog-in-paren))
8852 (modi (verilog-modi-current))
8853 (sig-list (verilog-signals-not-in
8854 (verilog-modi-get-sub-inputs modi)
8855 (append (verilog-modi-get-inputs modi)
8856 (verilog-modi-get-inouts modi)
8857 (verilog-modi-get-wires modi)
8858 (verilog-modi-get-regs modi)
8859 (verilog-modi-get-consts modi)
8860 (verilog-modi-get-gparams modi)
8861 (verilog-modi-get-sub-outputs modi)
8862 (verilog-modi-get-sub-inouts modi)))))
8864 (setq sig-list (verilog-signals-matching-regexp
8866 (setq sig-list (verilog-signals-not-matching-regexp
8867 sig-list verilog-auto-input-ignore-regexp))
8869 (when v2k (verilog-repair-open-comma))
8871 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
8872 (verilog-insert-definition sig-list "input" indent-pt v2k)
8873 (verilog-modi-cache-add-inputs modi sig-list)
8874 (verilog-insert-indent "// End of automatics\n"))
8875 (when v2k (verilog-repair-close-comma)))))
8877 (defun verilog-auto-inout (&optional with-params)
8878 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
8879 Make inout statements for any inout signal in an /*AUTOINST*/ that
8880 isn't declared elsewhere inside the module.
8883 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
8885 If placed inside the parenthesis of a module declaration, it creates
8886 Verilog 2001 style, else uses Verilog 1995 style.
8888 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
8889 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
8891 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
8893 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
8895 An example (see `verilog-auto-inst' for what else is going on here):
8897 module ExampInout (ov,i)
8904 Typing \\[verilog-auto] will make this into:
8906 module ExampInout (ov,i)
8909 // Beginning of automatic inouts (from unused autoinst inouts)
8910 inout [31:0] ov; // From inst of inst.v
8911 // End of automatics
8920 You may also provide an optional regular expression, in which case only
8921 signals matching the regular expression will be included. For example the
8922 same expansion will result from only extracting inouts starting with i:
8924 /*AUTOINOUT(\"^i\")*/"
8926 ;; Point must be at insertion point.
8927 (let* ((indent-pt (current-indentation))
8928 (regexp (and with-params
8929 (nth 0 (verilog-read-auto-params 1))))
8930 (v2k (verilog-in-paren))
8931 (modi (verilog-modi-current))
8932 (sig-list (verilog-signals-not-in
8933 (verilog-modi-get-sub-inouts modi)
8934 (append (verilog-modi-get-outputs modi)
8935 (verilog-modi-get-inouts modi)
8936 (verilog-modi-get-inputs modi)
8937 (verilog-modi-get-sub-inputs modi)
8938 (verilog-modi-get-sub-outputs modi)))))
8940 (setq sig-list (verilog-signals-matching-regexp
8942 (setq sig-list (verilog-signals-not-matching-regexp
8943 sig-list verilog-auto-inout-ignore-regexp))
8945 (when v2k (verilog-repair-open-comma))
8947 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
8948 (verilog-insert-definition sig-list "inout" indent-pt v2k)
8949 (verilog-modi-cache-add-inouts modi sig-list)
8950 (verilog-insert-indent "// End of automatics\n"))
8951 (when v2k (verilog-repair-close-comma)))))
8953 (defun verilog-auto-inout-module ()
8954 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
8955 Take input/output/inout statements from the specified module and insert
8956 into the current module. This is useful for making null templates and
8957 shell modules which need to have identical I/O with another module.
8958 Any I/O which are already defined in this module will not be redefined.
8961 If placed inside the parenthesis of a module declaration, it creates
8962 Verilog 2001 style, else uses Verilog 1995 style.
8964 Concatenation and outputting partial busses is not supported.
8966 Module names must be resolvable to filenames. See `verilog-auto-inst'.
8968 Signals are not inserted in the same order as in the original module,
8969 though they will appear to be in the same order to a AUTOINST
8970 instantiating either module.
8974 module ExampShell (/*AUTOARG*/)
8975 /*AUTOINOUTMODULE(\"ExampMain\")*/
8978 module ExampMain (i,o,io)
8984 Typing \\[verilog-auto] will make this into:
8986 module ExampShell (/*AUTOARG*/i,o,io)
8987 /*AUTOINOUTMODULE(\"ExampMain\")*/
8988 // Beginning of automatic in/out/inouts (from specific module)
8992 // End of automatics
8995 You may also provide an optional regular expression, in which case only
8996 signals matching the regular expression will be included. For example the
8997 same expansion will result from only extracting signals starting with i:
8999 /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/"
9001 (let* ((params (verilog-read-auto-params 1 2))
9002 (submod (nth 0 params))
9003 (regexp (nth 1 params))
9005 ;; Lookup position, etc of co-module
9006 ;; Note this may raise an error
9007 (when (setq submodi (verilog-modi-lookup submod t))
9008 (let* ((indent-pt (current-indentation))
9009 (v2k (verilog-in-paren))
9010 (modi (verilog-modi-current))
9011 (sig-list-i (verilog-signals-not-in
9012 (verilog-modi-get-inputs submodi)
9013 (append (verilog-modi-get-inputs modi))))
9014 (sig-list-o (verilog-signals-not-in
9015 (verilog-modi-get-outputs submodi)
9016 (append (verilog-modi-get-outputs modi))))
9017 (sig-list-io (verilog-signals-not-in
9018 (verilog-modi-get-inouts submodi)
9019 (append (verilog-modi-get-inouts modi)))))
9022 (setq sig-list-i (verilog-signals-matching-regexp
9024 sig-list-o (verilog-signals-matching-regexp
9026 sig-list-io (verilog-signals-matching-regexp
9027 sig-list-io regexp)))
9028 (when v2k (verilog-repair-open-comma))
9029 (when (or sig-list-i sig-list-o sig-list-io)
9030 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
9031 ;; Don't sort them so a upper AUTOINST will match the main module
9032 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
9033 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
9034 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
9035 (verilog-modi-cache-add-inputs modi sig-list-i)
9036 (verilog-modi-cache-add-outputs modi sig-list-o)
9037 (verilog-modi-cache-add-inouts modi sig-list-io)
9038 (verilog-insert-indent "// End of automatics\n"))
9039 (when v2k (verilog-repair-close-comma)))))))
9041 (defun verilog-auto-sense-sigs (modi presense-sigs)
9042 "Return list of signals for current AUTOSENSE block."
9043 (let* ((sigss (verilog-read-always-signals))
9044 (sig-list (verilog-signals-not-params
9045 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
9046 (append (and (not verilog-auto-sense-include-inputs)
9047 (verilog-alw-get-outputs sigss))
9048 (verilog-modi-get-consts modi)
9049 (verilog-modi-get-gparams modi)
9053 (defun verilog-auto-sense ()
9054 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
9055 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
9056 with one automatically derived from all inputs declared in the always
9057 statement. Signals that are generated within the same always block are NOT
9058 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
9059 Long lines are split based on the `fill-column', see \\[set-fill-column].
9062 Verilog does not allow memories (multidimensional arrays) in sensitivity
9063 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
9066 AUTOSENSE cannot always determine if a `define is a constant or a signal
9067 (it could be in a include file for example). If a `define or other signal
9068 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
9069 declaration anywhere in the module (parenthesis are required):
9071 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
9073 Better yet, use a parameter, which will be understood to be constant
9077 If AUTOSENSE makes a mistake, please report it. (First try putting
9078 a begin/end after your always!) As a workaround, if a signal that
9079 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
9080 If a signal should be in the sensitivity list wasn't, placing it before
9081 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
9082 autos are updated (or added if it occurs there already).
9086 always @ (/*AS*/) begin
9087 /* AUTO_CONSTANT (`constant) */
9088 outin = ina | inb | `constant;
9092 Typing \\[verilog-auto] will make this into:
9094 always @ (/*AS*/ina or inb) begin
9095 /* AUTO_CONSTANT (`constant) */
9096 outin = ina | inb | `constant;
9100 Note in Verilog 2001, you can often get the same result from the new @*
9101 operator. (This was added to the language in part due to AUTOSENSE!)
9104 outin = ina | inb | `constant;
9109 (let* ((start-pt (save-excursion
9110 (verilog-re-search-backward "(" nil t)
9112 (indent-pt (save-excursion
9113 (or (and (goto-char start-pt) (1+ (current-column)))
9114 (current-indentation))))
9115 (modi (verilog-modi-current))
9116 (sig-memories (verilog-signals-memory
9118 (verilog-modi-get-regs modi)
9119 (verilog-modi-get-wires modi))))
9120 sig-list not-first presense-sigs)
9121 ;; Read signals in always, eliminate outputs from sense list
9122 (setq presense-sigs (verilog-signals-from-signame
9124 (verilog-read-signals start-pt (point)))))
9125 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
9127 (let ((tlen (length sig-list)))
9128 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
9129 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
9130 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
9131 (save-excursion (goto-char (point))
9132 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9133 (verilog-re-search-backward "\\s-" start-pt t)
9134 (while (looking-at "\\s-`endif")
9135 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
9136 (verilog-re-search-backward "\\s-" start-pt t))
9137 (not (looking-at "\\s-or\\b"))))
9139 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9141 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
9143 (indent-to indent-pt)
9144 (if not-first (insert "or ")))
9145 (not-first (insert " or ")))
9146 (insert (verilog-sig-name (car sig-list)))
9147 (setq sig-list (cdr sig-list)
9150 (defun verilog-auto-reset ()
9151 "Expand AUTORESET statements, as part of \\[verilog-auto].
9152 Replace the /*AUTORESET*/ comment with code to initialize all
9153 registers set elsewhere in the always block.
9156 AUTORESET will not clear memories.
9158 AUTORESET uses <= if there are any <= in the block, else it uses =.
9160 /*AUTORESET*/ presumes that any signals mentioned between the previous
9161 begin/case/if statement and the AUTORESET comment are being reset manually
9162 and should not be automatically reset. This includes omitting any signals
9163 used on the right hand side of assignments.
9165 By default, AUTORESET will include the width of the signal in the autos,
9166 this is a recent change. To control this behavior, see
9167 `verilog-auto-reset-widths'.
9169 AUTORESET ties signals to deasserted, which is presumed to be zero.
9170 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9175 always @(posedge clk or negedge reset_l) begin
9187 Typing \\[verilog-auto] will make this into:
9189 always @(posedge core_clk or negedge reset_l) begin
9193 // Beginning of autoreset for uninitialized flops
9196 // End of automatics
9208 (let* ((indent-pt (current-indentation))
9209 (modi (verilog-modi-current))
9210 (all-list (verilog-modi-get-signals modi))
9211 sigss sig-list prereset-sigs assignment-str)
9212 ;; Read signals in always, eliminate outputs from reset list
9213 (setq prereset-sigs (verilog-signals-from-signame
9215 (verilog-read-signals
9217 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
9221 (verilog-re-search-backward "@" nil t)
9222 (setq sigss (verilog-read-always-signals)))
9223 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
9224 (concat " <= " verilog-assignment-delay)
9226 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
9228 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
9231 (indent-to indent-pt)
9232 (insert "// Beginning of autoreset for uninitialized flops\n");
9233 (indent-to indent-pt)
9235 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
9237 (insert (verilog-sig-name sig)
9239 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
9241 (indent-to indent-pt)
9242 (setq sig-list (cdr sig-list))))
9243 (insert "// End of automatics")))))
9245 (defun verilog-auto-tieoff ()
9246 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
9247 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
9248 signals to deasserted.
9250 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
9251 input/output list as another module, but no internals. Specifically, it
9252 finds all outputs in the module, and if that input is not otherwise declared
9253 as a register or wire, creates a tieoff.
9255 AUTORESET ties signals to deasserted, which is presumed to be zero.
9256 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
9259 An example of making a stub for another module:
9261 module ExampStub (/*AUTOINST*/);
9262 /*AUTOINOUTMODULE(\"Foo\")*/
9264 // verilator lint_off UNUSED
9265 wire _unused_ok = &{1'b0,
9268 // verilator lint_on UNUSED
9271 Typing \\[verilog-auto] will make this into:
9273 module ExampStub (/*AUTOINST*/...);
9274 /*AUTOINOUTMODULE(\"Foo\")*/
9275 // Beginning of autotieoff
9277 // End of automatics
9280 // Beginning of autotieoff
9281 wire [2:0] foo = 3'b0;
9282 // End of automatics
9288 (let* ((indent-pt (current-indentation))
9289 (modi (verilog-modi-current))
9290 (sig-list (verilog-signals-not-in
9291 (verilog-modi-get-outputs modi)
9292 (append (verilog-modi-get-wires modi)
9293 (verilog-modi-get-regs modi)
9294 (verilog-modi-get-assigns modi)
9295 (verilog-modi-get-consts modi)
9296 (verilog-modi-get-gparams modi)
9297 (verilog-modi-get-sub-outputs modi)
9298 (verilog-modi-get-sub-inouts modi)))))
9301 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
9302 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9303 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
9305 (let ((sig (car sig-list)))
9306 (verilog-insert-one-definition sig "wire" indent-pt)
9307 (indent-to (max 48 (+ indent-pt 40)))
9308 (insert "= " (verilog-sig-tieoff sig)
9310 (setq sig-list (cdr sig-list))))
9311 (verilog-insert-indent "// End of automatics\n")))))
9313 (defun verilog-auto-unused ()
9314 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
9315 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
9316 input and inout signals.
9318 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
9319 input/output list as another module, but no internals. Specifically, it
9320 finds all inputs and inouts in the module, and if that input is not otherwise
9321 used, adds it to a comma separated list.
9323 The comma separated list is intended to be used to create a _unused_ok
9324 signal. Using the exact name \"_unused_ok\" for name of the temporary
9325 signal is recommended as it will insure maximum forward compatibility, it
9326 also makes lint warnings easy to understand; ignore any unused warnings
9327 with \"unused\" in the signal name.
9329 To reduce simulation time, the _unused_ok signal should be forced to a
9330 constant to prevent wiggling. The easiest thing to do is use a
9331 reduction-and with 1'b0 as shown.
9333 This way all unused signals are in one place, making it convenient to add
9334 your tool's specific pragmas around the assignment to disable any unused
9337 You can add signals you do not want included in AUTOUNUSED with
9338 `verilog-auto-unused-ignore-regexp'.
9340 An example of making a stub for another module:
9342 module ExampStub (/*AUTOINST*/);
9343 /*AUTOINOUTMODULE(\"Examp\")*/
9345 // verilator lint_off UNUSED
9346 wire _unused_ok = &{1'b0,
9349 // verilator lint_on UNUSED
9352 Typing \\[verilog-auto] will make this into:
9355 // verilator lint_off UNUSED
9356 wire _unused_ok = &{1'b0,
9358 // Beginning of automatics
9362 // End of automatics
9364 // verilator lint_on UNUSED
9369 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
9370 (modi (verilog-modi-current))
9371 (sig-list (verilog-signals-not-in
9372 (append (verilog-modi-get-inputs modi)
9373 (verilog-modi-get-inouts modi))
9374 (append (verilog-modi-get-sub-inputs modi)
9375 (verilog-modi-get-sub-inouts modi)))))
9376 (setq sig-list (verilog-signals-not-matching-regexp
9377 sig-list verilog-auto-unused-ignore-regexp))
9380 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
9381 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
9383 (let ((sig (car sig-list)))
9384 (indent-to indent-pt)
9385 (insert (verilog-sig-name sig) ",\n")
9386 (setq sig-list (cdr sig-list))))
9387 (verilog-insert-indent "// End of automatics\n")))))
9389 (defun verilog-enum-ascii (signm elim-regexp)
9390 "Convert an enum name SIGNM to an ascii string for insertion.
9391 Remove user provided prefix ELIM-REGEXP."
9392 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
9393 (let ((case-fold-search t))
9394 ;; All upper becomes all lower for readability
9395 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
9397 (defun verilog-auto-ascii-enum ()
9398 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
9399 Create a register to contain the ASCII decode of a enumerated signal type.
9400 This will allow trace viewers to show the ASCII name of states.
9402 First, parameters are built into a enumeration using the synopsys enum
9403 comment. The comment must be between the keyword and the symbol.
9404 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
9406 Next, registers which that enum applies to are also tagged with the same
9407 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
9410 Finally, a AUTOASCIIENUM command is used.
9412 The first parameter is the name of the signal to be decoded.
9414 The second parameter is the name to store the ASCII code into. For the
9415 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
9416 a signal that is just for simulation, and the magic characters _ascii
9417 tell viewers like Dinotrace to display in ASCII format.
9419 The final optional parameter is a string which will be removed from the
9424 //== State enumeration
9425 parameter [2:0] // synopsys enum state_info
9429 //== State variables
9430 reg [2:0] /* synopsys enum state_info */
9431 state_r; /* synopsys state_vector state_r */
9432 reg [2:0] /* synopsys enum state_info */
9435 //== ASCII state decoding
9437 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9439 Typing \\[verilog-auto] will make this into:
9441 ... same front matter ...
9443 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
9444 // Beginning of automatic ASCII enum decoding
9445 reg [39:0] state_ascii_r; // Decode of state_r
9446 always @(state_r) begin
9448 SM_IDLE: state_ascii_r = \"idle \";
9449 SM_SEND: state_ascii_r = \"send \";
9450 SM_WAIT1: state_ascii_r = \"wait1\";
9451 default: state_ascii_r = \"%Erro\";
9454 // End of automatics"
9456 (let* ((params (verilog-read-auto-params 2 3))
9457 (undecode-name (nth 0 params))
9458 (ascii-name (nth 1 params))
9459 (elim-regexp (nth 2 params))
9461 (indent-pt (current-indentation))
9462 (modi (verilog-modi-current))
9464 (sig-list-consts (append (verilog-modi-get-consts modi)
9465 (verilog-modi-get-gparams modi)))
9466 (sig-list-all (append (verilog-modi-get-regs modi)
9467 (verilog-modi-get-outputs modi)
9468 (verilog-modi-get-inouts modi)
9469 (verilog-modi-get-inputs modi)
9470 (verilog-modi-get-wires modi)))
9472 (undecode-sig (or (assoc undecode-name sig-list-all)
9473 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
9474 (undecode-enum (or (verilog-sig-enum undecode-sig)
9475 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
9477 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
9478 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
9483 ;; Find number of ascii chars needed
9484 (let ((tmp-sigs enum-sigs))
9486 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
9487 ascii-chars (max ascii-chars (length (verilog-enum-ascii
9488 (verilog-sig-name (car tmp-sigs))
9490 tmp-sigs (cdr tmp-sigs))))
9493 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
9494 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
9495 (concat "Decode of " undecode-name) nil nil))))
9496 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
9497 (verilog-modi-cache-add-regs modi decode-sig-list))
9499 (verilog-insert-indent "always @(" undecode-name ") begin\n")
9500 (setq indent-pt (+ indent-pt verilog-indent-level))
9501 (indent-to indent-pt)
9502 (insert "case ({" undecode-name "})\n")
9503 (setq indent-pt (+ indent-pt verilog-case-indent))
9505 (let ((tmp-sigs enum-sigs)
9506 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
9507 ascii-name ascii-chars))
9508 (errname (substring "%Error" 0 (min 6 ascii-chars))))
9510 (verilog-insert-indent
9511 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
9512 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
9514 (setq tmp-sigs (cdr tmp-sigs)))
9515 (verilog-insert-indent (format chrfmt "default:" errname)))
9517 (setq indent-pt (- indent-pt verilog-case-indent))
9518 (verilog-insert-indent "endcase\n")
9519 (setq indent-pt (- indent-pt verilog-indent-level))
9520 (verilog-insert-indent "end\n"
9521 "// End of automatics\n"))))
9523 (defun verilog-auto-templated-rel ()
9524 "Replace Templated relative line numbers with absolute line numbers.
9525 Internal use only. This hacks around the line numbers in AUTOINST Templates
9526 being different from the final output's line numbering."
9527 (let ((templateno 0) (template-line (list 0)))
9528 ;; Find line number each template is on
9529 (goto-char (point-min))
9530 (while (search-forward "AUTO_TEMPLATE" nil t)
9531 (setq templateno (1+ templateno))
9533 (cons (count-lines (point-min) (point)) template-line)))
9534 (setq template-line (nreverse template-line))
9535 ;; Replace T# L# with absolute line number
9536 (goto-char (point-min))
9537 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
9539 (concat " Templated "
9540 (int-to-string (+ (nth (string-to-number (match-string 1))
9542 (string-to-number (match-string 2)))))
9550 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
9551 "Expand AUTO statements.
9552 Look for any /*AUTO...*/ commands in the code, as used in
9553 instantiations or argument headers. Update the list of signals
9554 following the /*AUTO...*/ command.
9556 Use \\[verilog-delete-auto] to remove the AUTOs.
9558 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
9560 Use \\[verilog-faq] for a pointer to frequently asked questions.
9562 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
9563 called before and after this function, respectively.
9566 module ModuleName (/*AUTOARG*/)
9571 InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
9573 You can also update the AUTOs from the shell using:
9574 emacs --batch <filenames.v> -f verilog-batch-auto
9575 Or fix indentation with:
9576 emacs --batch <filenames.v> -f verilog-batch-indent
9577 Likewise, you can delete or inject AUTOs with:
9578 emacs --batch <filenames.v> -f verilog-batch-delete-auto
9579 emacs --batch <filenames.v> -f verilog-batch-inject-auto
9581 Using \\[describe-function], see also:
9582 `verilog-auto-arg' for AUTOARG module instantiations
9583 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
9584 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
9585 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
9586 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
9587 `verilog-auto-inst' for AUTOINST instantiation pins
9588 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
9589 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
9590 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
9591 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
9592 `verilog-auto-reg' for AUTOREG registers
9593 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
9594 `verilog-auto-reset' for AUTORESET flop resets
9595 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
9596 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
9597 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
9598 `verilog-auto-wire' for AUTOWIRE instantiation wires
9600 `verilog-read-defines' for reading `define values
9601 `verilog-read-includes' for reading `includes
9603 If you have bugs with these autos, try contacting the AUTOAUTHOR
9604 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
9606 (unless noninteractive (message "Updating AUTOs..."))
9607 (if (fboundp 'dinotrace-unannotate-all)
9608 (dinotrace-unannotate-all))
9609 (let ((oldbuf (if (not (buffer-modified-p))
9611 ;; Before version 20, match-string with font-lock returns a
9612 ;; vector that is not equal to the string. IE if on "input"
9613 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
9614 (fontlocked (when (and (boundp 'font-lock-mode)
9616 (font-lock-mode nil)
9620 ;; If we're not in verilog-mode, change syntax table so parsing works right
9621 (unless (eq major-mode `verilog-mode) (verilog-mode))
9622 ;; Allow user to customize
9623 (run-hooks 'verilog-before-auto-hook)
9624 ;; Try to save the user from needing to revert-file to reread file local-variables
9625 (verilog-auto-reeval-locals)
9626 (verilog-read-auto-lisp (point-min) (point-max))
9627 (verilog-getopt-flags)
9628 ;; These two may seem obvious to do always, but on large includes it can be way too slow
9629 (when verilog-auto-read-includes
9630 (verilog-read-includes)
9631 (verilog-read-defines nil nil t))
9632 ;; This particular ordering is important
9633 ;; INST: Lower modules correct, no internal dependencies, FIRST
9634 (verilog-preserve-cache
9635 ;; Clear existing autos else we'll be screwed by existing ones
9636 (verilog-delete-auto)
9637 ;; Injection if appropriate
9639 (verilog-inject-inst)
9640 (verilog-inject-sense)
9641 (verilog-inject-arg))
9643 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
9644 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
9645 (verilog-auto-search-do ".*" 'verilog-auto-star)
9646 ;; Doesn't matter when done, but combine it with a common changer
9647 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
9648 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
9649 ;; Must be done before autoin/out as creates a reg
9650 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
9652 ;; first in/outs from other files
9653 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
9654 ;; next in/outs which need previous sucked inputs first
9655 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
9656 '(lambda () (verilog-auto-output t)))
9657 (verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
9658 (verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
9659 '(lambda () (verilog-auto-input t)))
9660 (verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
9661 (verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
9662 '(lambda () (verilog-auto-inout t)))
9663 (verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
9664 ;; Then tie off those in/outs
9665 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
9666 ;; Wires/regs must be after inputs/outputs
9667 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
9668 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
9669 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
9670 ;; outputevery needs AUTOOUTPUTs done first
9671 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
9672 ;; After we've created all new variables
9673 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
9674 ;; Must be after all inputs outputs are generated
9675 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
9676 ;; Fix line numbers (comments only)
9677 (verilog-auto-templated-rel))
9679 (run-hooks 'verilog-auto-hook)
9681 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
9683 ;; If end result is same as when started, clear modified flag
9684 (cond ((and oldbuf (equal oldbuf (buffer-string)))
9685 (set-buffer-modified-p nil)
9686 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
9687 (t (unless noninteractive (message "Updating AUTOs...done")))))
9690 ;; Restore font-lock
9691 (when fontlocked (font-lock-mode t))))))
9695 ;; Skeleton based code insertion
9697 (defvar verilog-template-map
9698 (let ((map (make-sparse-keymap)))
9699 (define-key map "a" 'verilog-sk-always)
9700 (define-key map "b" 'verilog-sk-begin)
9701 (define-key map "c" 'verilog-sk-case)
9702 (define-key map "f" 'verilog-sk-for)
9703 (define-key map "g" 'verilog-sk-generate)
9704 (define-key map "h" 'verilog-sk-header)
9705 (define-key map "i" 'verilog-sk-initial)
9706 (define-key map "j" 'verilog-sk-fork)
9707 (define-key map "m" 'verilog-sk-module)
9708 (define-key map "p" 'verilog-sk-primitive)
9709 (define-key map "r" 'verilog-sk-repeat)
9710 (define-key map "s" 'verilog-sk-specify)
9711 (define-key map "t" 'verilog-sk-task)
9712 (define-key map "w" 'verilog-sk-while)
9713 (define-key map "x" 'verilog-sk-casex)
9714 (define-key map "z" 'verilog-sk-casez)
9715 (define-key map "?" 'verilog-sk-if)
9716 (define-key map ":" 'verilog-sk-else-if)
9717 (define-key map "/" 'verilog-sk-comment)
9718 (define-key map "A" 'verilog-sk-assign)
9719 (define-key map "F" 'verilog-sk-function)
9720 (define-key map "I" 'verilog-sk-input)
9721 (define-key map "O" 'verilog-sk-output)
9722 (define-key map "S" 'verilog-sk-state-machine)
9723 (define-key map "=" 'verilog-sk-inout)
9724 (define-key map "W" 'verilog-sk-wire)
9725 (define-key map "R" 'verilog-sk-reg)
9726 (define-key map "D" 'verilog-sk-define-signal)
9728 "Keymap used in Verilog mode for smart template operations.")
9732 ;; Place the templates into Verilog Mode. They may be inserted under any key.
9733 ;; C-c C-t will be the default. If you use templates a lot, you
9734 ;; may want to consider moving the binding to another key in your .emacs
9737 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
9738 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
9740 ;;; ---- statement skeletons ------------------------------------------
9742 (define-skeleton verilog-sk-prompt-condition
9743 "Prompt for the loop condition."
9744 "[condition]: " str )
9746 (define-skeleton verilog-sk-prompt-init
9747 "Prompt for the loop init statement."
9748 "[initial statement]: " str )
9750 (define-skeleton verilog-sk-prompt-inc
9751 "Prompt for the loop increment statement."
9752 "[increment statement]: " str )
9754 (define-skeleton verilog-sk-prompt-name
9755 "Prompt for the name of something."
9758 (define-skeleton verilog-sk-prompt-clock
9759 "Prompt for the name of something."
9760 "name and edge of clock(s): " str)
9762 (defvar verilog-sk-reset nil)
9763 (defun verilog-sk-prompt-reset ()
9764 "Prompt for the name of a state machine reset."
9765 (setq verilog-sk-reset (read-string "name of reset: " "rst")))
9768 (define-skeleton verilog-sk-prompt-state-selector
9769 "Prompt for the name of a state machine selector."
9770 "name of selector (eg {a,b,c,d}): " str )
9772 (define-skeleton verilog-sk-prompt-output
9773 "Prompt for the name of something."
9776 (define-skeleton verilog-sk-prompt-msb
9777 "Prompt for least significant bit specification."
9778 "msb:" str & ?: & '(verilog-sk-prompt-lsb) | -1 )
9780 (define-skeleton verilog-sk-prompt-lsb
9781 "Prompt for least significant bit specification."
9784 (defvar verilog-sk-p nil)
9785 (define-skeleton verilog-sk-prompt-width
9786 "Prompt for a width specification."
9789 (setq verilog-sk-p (point))
9790 (verilog-sk-prompt-msb)
9791 (if (> (point) verilog-sk-p) "] " " ")))
9793 (defun verilog-sk-header ()
9794 "Insert a descriptive header at the top of the file."
9797 (goto-char (point-min))
9798 (verilog-sk-header-tmpl)))
9800 (define-skeleton verilog-sk-header-tmpl
9801 "Insert a comment block containing the module title, author, etc."
9803 "// -*- Mode: Verilog -*-"
9804 "\n// Filename : " (buffer-name)
9805 "\n// Description : " str
9806 "\n// Author : " (user-full-name)
9807 "\n// Created On : " (current-time-string)
9808 "\n// Last Modified By: ."
9809 "\n// Last Modified On: ."
9810 "\n// Update Count : 0"
9811 "\n// Status : Unknown, Use with caution!"
9814 (define-skeleton verilog-sk-module
9815 "Insert a module definition."
9817 > "module " '(verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
9819 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
9821 (define-skeleton verilog-sk-primitive
9822 "Insert a task definition."
9824 > "primitive " '(verilog-sk-prompt-name) " ( " '(verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
9826 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
9828 (define-skeleton verilog-sk-task
9829 "Insert a task definition."
9831 > "task " '(verilog-sk-prompt-name) & ?; \n
9835 > (- verilog-indent-level-behavioral) "end" \n
9836 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
9838 (define-skeleton verilog-sk-function
9839 "Insert a function definition."
9841 > "function [" '(verilog-sk-prompt-width) | -1 '(verilog-sk-prompt-name) ?; \n
9845 > (- verilog-indent-level-behavioral) "end" \n
9846 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
9848 (define-skeleton verilog-sk-always
9849 "Insert always block. Uses the minibuffer to prompt
9850 for sensitivity list."
9852 > "always @ ( /*AUTOSENSE*/ ) begin\n"
9854 > (- verilog-indent-level-behavioral) "end" \n >
9857 (define-skeleton verilog-sk-initial
9858 "Insert an initial block."
9862 > (- verilog-indent-level-behavioral) "end" \n > )
9864 (define-skeleton verilog-sk-specify
9865 "Insert specify block. "
9869 > (- verilog-indent-level-behavioral) "endspecify" \n > )
9871 (define-skeleton verilog-sk-generate
9872 "Insert generate block. "
9876 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
9878 (define-skeleton verilog-sk-begin
9879 "Insert begin end block. Uses the minibuffer to prompt for name."
9881 > "begin" '(verilog-sk-prompt-name) \n
9883 > (- verilog-indent-level-behavioral) "end"
9886 (define-skeleton verilog-sk-fork
9887 "Insert a fork join block."
9892 > (- verilog-indent-level-behavioral) "end" \n
9895 > (- verilog-indent-level-behavioral) "end" \n
9896 > (- verilog-indent-level-behavioral) "join" \n
9900 (define-skeleton verilog-sk-case
9901 "Build skeleton case statement, prompting for the selector expression,
9902 and the case items."
9903 "[selector expression]: "
9904 > "case (" str ") " \n
9905 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9906 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9908 (define-skeleton verilog-sk-casex
9909 "Build skeleton casex statement, prompting for the selector expression,
9910 and the case items."
9911 "[selector expression]: "
9912 > "casex (" str ") " \n
9913 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9914 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9916 (define-skeleton verilog-sk-casez
9917 "Build skeleton casez statement, prompting for the selector expression,
9918 and the case items."
9919 "[selector expression]: "
9920 > "casez (" str ") " \n
9921 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
9922 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
9924 (define-skeleton verilog-sk-if
9925 "Insert a skeleton if statement."
9926 > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
9928 > (- verilog-indent-level-behavioral) "end " \n )
9930 (define-skeleton verilog-sk-else-if
9931 "Insert a skeleton else if statement."
9932 > (verilog-indent-line) "else if ("
9933 (progn (setq verilog-sk-p (point)) nil) '(verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
9935 > "end" (progn (electric-verilog-terminate-line) nil))
9937 (define-skeleton verilog-sk-datadef
9938 "Common routine to get data definition."
9940 '(verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
9942 (define-skeleton verilog-sk-input
9943 "Insert an input definition."
9945 > "input [" '(verilog-sk-datadef))
9947 (define-skeleton verilog-sk-output
9948 "Insert an output definition."
9950 > "output [" '(verilog-sk-datadef))
9952 (define-skeleton verilog-sk-inout
9953 "Insert an inout definition."
9955 > "inout [" '(verilog-sk-datadef))
9957 (defvar verilog-sk-signal nil)
9958 (define-skeleton verilog-sk-def-reg
9959 "Insert a reg definition."
9961 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
9963 (defun verilog-sk-define-signal ()
9964 "Insert a definition of signal under point at top of module."
9966 (let* ((sig-re "[a-zA-Z0-9_]*")
9967 (v1 (buffer-substring
9969 (skip-chars-backward sig-re)
9972 (skip-chars-forward sig-re)
9974 (if (not (member v1 verilog-keywords))
9976 (setq verilog-sk-signal v1)
9977 (verilog-beg-of-defun)
9978 (verilog-end-of-statement)
9979 (verilog-forward-syntactic-ws)
9980 (verilog-sk-def-reg)
9981 (message "signal at point is %s" v1))
9982 (message "object at point (%s) is a keyword" v1))))
9984 (define-skeleton verilog-sk-wire
9985 "Insert a wire definition."
9987 > "wire [" '(verilog-sk-datadef))
9989 (define-skeleton verilog-sk-reg
9990 "Insert a reg definition."
9992 > "reg [" '(verilog-sk-datadef))
9994 (define-skeleton verilog-sk-assign
9995 "Insert a skeleton assign statement."
9997 > "assign " '(verilog-sk-prompt-name) " = " _ ";" \n)
9999 (define-skeleton verilog-sk-while
10000 "Insert a skeleton while loop statement."
10002 > "while (" '(verilog-sk-prompt-condition) ") begin" \n
10004 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10006 (define-skeleton verilog-sk-repeat
10007 "Insert a skeleton repeat loop statement."
10009 > "repeat (" '(verilog-sk-prompt-condition) ") begin" \n
10011 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10013 (define-skeleton verilog-sk-for
10014 "Insert a skeleton while loop statement."
10017 '(verilog-sk-prompt-init) "; "
10018 '(verilog-sk-prompt-condition) "; "
10019 '(verilog-sk-prompt-inc)
10022 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
10024 (define-skeleton verilog-sk-comment
10025 "Inserts three comment lines, making a display comment."
10031 (define-skeleton verilog-sk-state-machine
10032 "Insert a state machine definition."
10033 "Name of state variable: "
10034 '(setq input "state")
10035 > "// State registers for " str | -23 \n
10036 '(setq verilog-sk-state str)
10037 > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
10040 > "// State FF for " verilog-sk-state \n
10041 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
10042 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
10043 > verilog-sk-state " = next_" verilog-sk-state ?; \n
10044 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
10046 > "// Next State Logic for " verilog-sk-state \n
10047 > "always @ ( /*AUTOSENSE*/ ) begin\n"
10048 > "case (" '(verilog-sk-prompt-state-selector) ") " \n
10049 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
10050 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
10051 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
10055 ;; Include file loading with mouse/return event
10057 ;; idea & first impl.: M. Rouat (eldo-mode.el)
10058 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
10060 (if (featurep 'xemacs)
10062 (require 'lucid)) ;; what else can we do ??
10064 (defconst verilog-include-file-regexp
10065 "^`include\\s-+\"\\([^\n\"]*\\)\""
10066 "Regexp that matches the include file.")
10068 (defvar verilog-mode-mouse-map
10069 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
10070 (set-keymap-parent map verilog-mode-map)
10071 ;; mouse button bindings
10072 (define-key map "\r" 'verilog-load-file-at-point)
10073 (if (featurep 'xemacs)
10074 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
10075 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
10076 (if (featurep 'xemacs)
10077 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
10078 (define-key map [S-mouse-2] 'mouse-yank-at-click))
10080 "Map containing mouse bindings for `verilog-mode'.")
10083 (defun verilog-colorize-include-files (beg end old-len)
10084 "This function colorizes included files when the mouse passes over them.
10085 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
10090 (setq end-point (verilog-get-end-of-line))
10092 (beginning-of-line) ; scan entire line !
10093 ;; delete overlays existing on this line
10094 (let ((overlays (overlays-in (point) end-point)))
10097 (overlay-get (car overlays) 'detachable)
10098 (overlay-get (car overlays) 'verilog-include-file))
10099 (delete-overlay (car overlays)))
10100 (setq overlays (cdr overlays)))) ; let
10101 ;; make new ones, could reuse deleted one ?
10102 (while (search-forward-regexp verilog-include-file-regexp end-point t)
10104 (goto-char (match-beginning 1))
10105 (setq ov (make-overlay (match-beginning 1) (match-end 1)))
10106 (overlay-put ov 'start-closed 't)
10107 (overlay-put ov 'end-closed 't)
10108 (overlay-put ov 'evaporate 't)
10109 (overlay-put ov 'verilog-include-file 't)
10110 (overlay-put ov 'mouse-face 'highlight)
10111 (overlay-put ov 'local-map verilog-mode-mouse-map)))))))
10114 (defun verilog-colorize-include-files-buffer ()
10115 "Colorize an include file."
10118 (let ((overlays (overlays-in (point-min) (point-max))))
10121 (overlay-get (car overlays) 'detachable)
10122 (overlay-get (car overlays) 'verilog-include-file))
10123 (delete-overlay (car overlays)))
10124 (setq overlays (cdr overlays)))) ; let
10126 (verilog-colorize-include-files (point-min) (point-max) nil))
10128 ;; ffap-at-mouse isn't useful for Verilog mode. It uses library paths.
10129 ;; so define this function to do more or less the same as ffap-at-mouse
10130 ;; but first resolve filename...
10131 (defun verilog-load-file-at-mouse (event)
10132 "Load file under button 2 click's EVENT.
10133 Files are checked based on `verilog-library-directories'."
10135 (save-excursion ;; implement a Verilog specific ffap-at-mouse
10136 (mouse-set-point event)
10137 (beginning-of-line)
10138 (if (looking-at verilog-include-file-regexp)
10139 (if (and (car (verilog-library-filenames
10140 (match-string 1) (buffer-file-name)))
10141 (file-readable-p (car (verilog-library-filenames
10142 (match-string 1) (buffer-file-name)))))
10143 (find-file (car (verilog-library-filenames
10144 (match-string 1) (buffer-file-name))))
10147 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
10148 (match-string 1)))))))
10150 ;; ffap isn't useable for Verilog mode. It uses library paths.
10151 ;; so define this function to do more or less the same as ffap
10152 ;; but first resolve filename...
10153 (defun verilog-load-file-at-point ()
10154 "Load file under point.
10155 Files are checked based on `verilog-library-directories'."
10157 (save-excursion ;; implement a Verilog specific ffap
10158 (beginning-of-line)
10159 (if (looking-at verilog-include-file-regexp)
10161 (car (verilog-library-filenames
10162 (match-string 1) (buffer-file-name)))
10163 (file-readable-p (car (verilog-library-filenames
10164 (match-string 1) (buffer-file-name)))))
10165 (find-file (car (verilog-library-filenames
10166 (match-string 1) (buffer-file-name))))))))
10173 (defun verilog-faq ()
10174 "Tell the user their current version, and where to get the FAQ etc."
10176 (with-output-to-temp-buffer "*verilog-mode help*"
10177 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
10179 (princ "For new releases, see http://www.verilog.com\n")
10181 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
10183 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
10186 (autoload 'reporter-submit-bug-report "reporter")
10187 (defvar reporter-prompt-for-summary-p)
10189 (defun verilog-submit-bug-report ()
10190 "Submit via mail a bug report on verilog-mode.el."
10192 (let ((reporter-prompt-for-summary-p t))
10193 (reporter-submit-bug-report
10195 (concat "verilog-mode v" verilog-mode-version)
10197 verilog-align-ifelse
10198 verilog-auto-endcomments
10200 verilog-auto-indent-on-newline
10201 verilog-auto-inst-vector
10202 verilog-auto-inst-template-numbers
10203 verilog-auto-lineup
10204 verilog-auto-newline
10205 verilog-auto-save-policy
10206 verilog-auto-sense-defines-constant
10207 verilog-auto-sense-include-inputs
10208 verilog-before-auto-hook
10209 verilog-case-indent
10210 verilog-cexp-indent
10213 verilog-highlight-translate-off
10214 verilog-indent-begin-after-if
10215 verilog-indent-declaration-macros
10216 verilog-indent-level
10217 verilog-indent-level-behavioral
10218 verilog-indent-level-declaration
10219 verilog-indent-level-directive
10220 verilog-indent-level-module
10221 verilog-indent-lists
10222 verilog-library-flags
10223 verilog-library-directories
10224 verilog-library-extensions
10225 verilog-library-files
10227 verilog-minimum-comment-distance
10230 verilog-tab-always-indent
10231 verilog-tab-to-comment
10236 I want to report a bug. I've read the `Bugs' section of `Info' on
10237 Emacs, so I know how to make a clear and unambiguous report. To get
10238 to that Info section, I typed
10240 M-x info RET m " invocation-name " RET m bugs RET
10242 Before I go further, I want to say that Verilog mode has changed my life.
10243 I save so much time, my files are colored nicely, my co workers respect
10244 my coding ability... until now. I'd really appreciate anything you
10245 could do to help me out with this minor deficiency in the product.
10247 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
10248 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
10249 You may also want to look at the Verilog-Mode FAQ, see
10250 http://www.veripool.com/verilog-mode-faq.html.
10252 To reproduce the bug, start a fresh Emacs via " invocation-name "
10253 -no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
10254 the code included below.
10256 Given those lines, I expected [[Fill in here]] to happen;
10257 but instead, [[Fill in here]] happens!.
10259 == The code: =="))))
10261 (provide 'verilog-mode)
10263 ;; Local Variables:
10264 ;; checkdoc-permit-comma-termination-flag:t
10265 ;; checkdoc-force-docstrings-flag:nil
10268 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f
10269 ;;; verilog-mode.el ends here