| blob | 3e8a5b3116f71285548a6e216627db368114a2bd |
1 /** @file\r
2 FACP Table\r
3 \r
4 Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
5 reserved. This program and the accompanying materials are\r
6 licensed and made available under the terms and conditions of the BSD License\r
7 which accompanies this distribution. The full text of the license may be found at\r
8 http://opensource.org/licenses/bsd-license.php\r
9 \r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12 \r
13 **/ \r
14 \r
15 #include "Platform.h"\r
16 \r
17 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
18 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
19 sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
20 EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
21 0, // to make sum of entire table == 0\r
22 EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
23 EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
24 EFI_ACPI_OEM_REVISION, // OEM revision number\r
25 EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
26 EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number\r
27 0, // Physical addesss of FACS\r
28 0, // Physical address of DSDT\r
29 INT_MODEL, // System Interrupt Model\r
30 RESERVED, // reserved\r
31 SCI_INT_VECTOR, // System vector of SCI interrupt\r
32 SMI_CMD_IO_PORT, // Port address of SMI command port\r
33 ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
34 ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
35 S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
36 0xE2, // PState control\r
37 PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
38 PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
39 PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
40 PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r
41 PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r
42 PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
43 GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
44 GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
45 PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
46 PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
47 PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
48 PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
49 GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
50 GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
51 GPE1_BASE, // offset in gpe model where gpe1 events start\r
52 0xE3, // _CST support\r
53 P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
54 P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
55 FLUSH_SIZE, // Size of area read to flush caches\r
56 FLUSH_STRIDE, // Stride used in flushing caches\r
57 DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
58 DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
59 DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
60 MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
61 CENTURY, // index to century in RTC CMOS RAM\r
62 0x03, // Boot architecture flag\r
63 0x00, // Boot architecture flag\r
64 RESERVED, // reserved \r
65 FLAG\r
66 };\r
67 \r
68 \r
69 VOID*\r
70 ReferenceAcpiTable (\r
71 VOID\r
72 )\r
73 {\r
74 //\r
75 // Reference the table being generated to prevent the optimizer from removing the \r
76 // data structure from the exeutable\r
77 //\r
78 return (VOID*)&FACP;\r
79 }\r