| blob | 0db6ac58aaaba2d9f95fe4505ddfbccf95127b94 |
1 Only in binutils-2.35.1/gas: ChangeLog.orig
2 Only in binutils-2.35.1/gas: ChangeLog.rej
3 Only in binutils-2.35.1/gas/config: tc-s390.c.rej
4 diff -rup binutils.orig/gas/doc/c-s390.texi binutils-2.35.1/gas/doc/c-s390.texi
5 --- binutils.orig/gas/doc/c-s390.texi 2021-03-25 14:35:40.951633346 +0000
6 +++ binutils-2.35.1/gas/doc/c-s390.texi 2021-03-25 14:39:39.910468584 +0000
7 @@ -313,7 +313,7 @@ field. The notation changes as follows:
8 @cindex instruction formats, s390
9 @cindex s390 instruction formats
11 -The Principles of Operation manuals lists 26 instruction formats where
12 +The Principles of Operation manuals lists 35 instruction formats where
13 some of the formats have multiple variants. For the @samp{.insn}
14 pseudo directive the assembler recognizes some of the formats.
15 Typically, the most general variant of the instruction format is used
16 @@ -545,6 +545,54 @@ with the @samp{.insn} pseudo directive:
17 0 8 12 16 20 32 36 47
18 @end verbatim
20 +@item VRV format: <insn> V1,D2(V2,B2),M3
21 +@verbatim
22 ++--------+----+----+----+-------------+----+------------+
23 +| OpCode | V1 | V2 | B2 | D2 | M3 | Opcode |
24 ++--------+----+----+----+-------------+----+------------+
25 +0 8 12 16 20 32 36 47
26 +@end verbatim
27 +
28 +@item VRI format: <insn> V1,V2,I3,M4,M5
29 +@verbatim
30 ++--------+----+----+-------------+----+----+------------+
31 +| OpCode | V1 | V2 | I3 | M5 | M4 | Opcode |
32 ++--------+----+----+-------------+----+----+------------+
33 +0 8 12 16 28 32 36 47
34 +@end verbatim
35 +
36 +@item VRX format: <insn> V1,D2(R2,B2),M3
37 +@verbatim
38 ++--------+----+----+----+-------------+----+------------+
39 +| OpCode | V1 | R2 | B2 | D2 | M3 | Opcode |
40 ++--------+----+----+----+-------------+----+------------+
41 +0 8 12 16 20 32 36 47
42 +@end verbatim
43 +
44 +@item VRS format: <insn> R1,V3,D2(B2),M4
45 +@verbatim
46 ++--------+----+----+----+-------------+----+------------+
47 +| OpCode | R1 | V3 | B2 | D2 | M4 | Opcode |
48 ++--------+----+----+----+-------------+----+------------+
49 +0 8 12 16 20 32 36 47
50 +@end verbatim
51 +
52 +@item VRR format: <insn> V1,V2,V3,M4,M5,M6
53 +@verbatim
54 ++--------+----+----+----+---+----+----+----+------------+
55 +| OpCode | V1 | V2 | V3 |///| M6 | M5 | M4 | Opcode |
56 ++--------+----+----+----+---+----+----+----+------------+
57 +0 8 12 16 24 28 32 36 47
58 +@end verbatim
59 +
60 +@item VSI format: <insn> V1,D2(B2),I3
61 +@verbatim
62 ++--------+---------+----+-------------+----+------------+
63 +| OpCode | I3 | B2 | D2 | V1 | Opcode |
64 ++--------+---------+----+-------------+----+------------+
65 +0 8 16 20 32 36 47
66 +@end verbatim
67 +
68 @end table
70 For the complete list of all instruction format variants see the
71 Only in binutils-2.35.1/gas/doc: c-s390.texi.orig
72 Only in binutils-2.35.1/gas/doc: c-s390.texi.rej
73 diff -rup binutils.orig/gas/testsuite/gas/s390/esa-g5.d binutils-2.35.1/gas/testsuite/gas/s390/esa-g5.d
74 --- binutils.orig/gas/testsuite/gas/s390/esa-g5.d 2021-03-25 14:35:41.038632922 +0000
75 +++ binutils-2.35.1/gas/testsuite/gas/s390/esa-g5.d 2021-03-25 14:39:56.533387550 +0000
76 @@ -78,10 +78,14 @@ Disassembly of section .text:
77 .*: 07 29 [ ]*bhr %r9
78 .*: 07 f9 [ ]*br %r9
79 .*: a7 95 00 00 [ ]*bras %r9,e2 <foo\+0xe2>
80 -.*: a7 64 00 00 [ ]*jlh e6 <foo\+0xe6>
81 -.*: a7 66 00 00 [ ]*brct %r6,ea <foo\+0xea>
82 -.*: 84 69 00 00 [ ]*brxh %r6,%r9,ee <foo\+0xee>
83 -.*: 85 69 00 00 [ ]*brxle %r6,%r9,f2 <foo\+0xf2>
84 +.*: a7 65 00 00 [ ]*bras %r6,e6 <foo\+0xe6>
85 +.*: a7 64 00 00 [ ]*jlh ea <foo\+0xea>
86 +.*: a7 66 00 00 [ ]*brct %r6,ee <foo\+0xee>
87 +.*: a7 66 00 00 [ ]*brct %r6,f2 <foo\+0xf2>
88 +.*: 84 69 00 00 [ ]*brxh %r6,%r9,f6 <foo\+0xf6>
89 +.*: 84 69 00 00 [ ]*brxh %r6,%r9,fa <foo\+0xfa>
90 +.*: 85 69 00 00 [ ]*brxle %r6,%r9,fe <foo\+0xfe>
91 +.*: 85 69 00 00 [ ]*brxle %r6,%r9,102 <foo\+0x102>
92 .*: b2 5a 00 69 [ ]*bsa %r6,%r9
93 .*: b2 58 00 69 [ ]*bsg %r6,%r9
94 .*: 0b 69 [ ]*bsm %r6,%r9
95 @@ -180,27 +184,49 @@ Disassembly of section .text:
96 .*: b2 21 00 69 [ ]*ipte %r6,%r9
97 .*: b2 29 00 69 [ ]*iske %r6,%r9
98 .*: b2 23 00 69 [ ]*ivsk %r6,%r9
99 -.*: a7 f4 00 00 [ ]*j 278 <foo\+0x278>
100 -.*: a7 84 00 00 [ ]*je 27c <foo\+0x27c>
101 -.*: a7 24 00 00 [ ]*jh 280 <foo\+0x280>
102 -.*: a7 a4 00 00 [ ]*jhe 284 <foo\+0x284>
103 -.*: a7 44 00 00 [ ]*jl 288 <foo\+0x288>
104 -.*: a7 c4 00 00 [ ]*jle 28c <foo\+0x28c>
105 -.*: a7 64 00 00 [ ]*jlh 290 <foo\+0x290>
106 -.*: a7 44 00 00 [ ]*jl 294 <foo\+0x294>
107 -.*: a7 74 00 00 [ ]*jne 298 <foo\+0x298>
108 -.*: a7 d4 00 00 [ ]*jnh 29c <foo\+0x29c>
109 -.*: a7 54 00 00 [ ]*jnhe 2a0 <foo\+0x2a0>
110 -.*: a7 b4 00 00 [ ]*jnl 2a4 <foo\+0x2a4>
111 -.*: a7 34 00 00 [ ]*jnle 2a8 <foo\+0x2a8>
112 -.*: a7 94 00 00 [ ]*jnlh 2ac <foo\+0x2ac>
113 -.*: a7 b4 00 00 [ ]*jnl 2b0 <foo\+0x2b0>
114 -.*: a7 e4 00 00 [ ]*jno 2b4 <foo\+0x2b4>
115 -.*: a7 d4 00 00 [ ]*jnh 2b8 <foo\+0x2b8>
116 -.*: a7 74 00 00 [ ]*jne 2bc <foo\+0x2bc>
117 -.*: a7 14 00 00 [ ]*jo 2c0 <foo\+0x2c0>
118 -.*: a7 24 00 00 [ ]*jh 2c4 <foo\+0x2c4>
119 -.*: a7 84 00 00 [ ]*je 2c8 <foo\+0x2c8>
120 +.*: a7 f4 00 00 [ ]*j 288 <foo\+0x288>
121 +.*: a7 84 00 00 [ ]*je 28c <foo\+0x28c>
122 +.*: a7 24 00 00 [ ]*jh 290 <foo\+0x290>
123 +.*: a7 a4 00 00 [ ]*jhe 294 <foo\+0x294>
124 +.*: a7 44 00 00 [ ]*jl 298 <foo\+0x298>
125 +.*: a7 c4 00 00 [ ]*jle 29c <foo\+0x29c>
126 +.*: a7 64 00 00 [ ]*jlh 2a0 <foo\+0x2a0>
127 +.*: a7 44 00 00 [ ]*jl 2a4 <foo\+0x2a4>
128 +.*: a7 74 00 00 [ ]*jne 2a8 <foo\+0x2a8>
129 +.*: a7 d4 00 00 [ ]*jnh 2ac <foo\+0x2ac>
130 +.*: a7 54 00 00 [ ]*jnhe 2b0 <foo\+0x2b0>
131 +.*: a7 b4 00 00 [ ]*jnl 2b4 <foo\+0x2b4>
132 +.*: a7 34 00 00 [ ]*jnle 2b8 <foo\+0x2b8>
133 +.*: a7 94 00 00 [ ]*jnlh 2bc <foo\+0x2bc>
134 +.*: a7 b4 00 00 [ ]*jnl 2c0 <foo\+0x2c0>
135 +.*: a7 e4 00 00 [ ]*jno 2c4 <foo\+0x2c4>
136 +.*: a7 d4 00 00 [ ]*jnh 2c8 <foo\+0x2c8>
137 +.*: a7 74 00 00 [ ]*jne 2cc <foo\+0x2cc>
138 +.*: a7 14 00 00 [ ]*jo 2d0 <foo\+0x2d0>
139 +.*: a7 24 00 00 [ ]*jh 2d4 <foo\+0x2d4>
140 +.*: a7 84 00 00 [ ]*je 2d8 <foo\+0x2d8>
141 +.*: a7 04 00 00 [ ]*jnop 2dc <foo\+0x2dc>
142 +.*: a7 14 00 00 [ ]*jo 2e0 <foo\+0x2e0>
143 +.*: a7 24 00 00 [ ]*jh 2e4 <foo\+0x2e4>
144 +.*: a7 24 00 00 [ ]*jh 2e8 <foo\+0x2e8>
145 +.*: a7 34 00 00 [ ]*jnle 2ec <foo\+0x2ec>
146 +.*: a7 44 00 00 [ ]*jl 2f0 <foo\+0x2f0>
147 +.*: a7 44 00 00 [ ]*jl 2f4 <foo\+0x2f4>
148 +.*: a7 54 00 00 [ ]*jnhe 2f8 <foo\+0x2f8>
149 +.*: a7 64 00 00 [ ]*jlh 2fc <foo\+0x2fc>
150 +.*: a7 74 00 00 [ ]*jne 300 <foo\+0x300>
151 +.*: a7 74 00 00 [ ]*jne 304 <foo\+0x304>
152 +.*: a7 84 00 00 [ ]*je 308 <foo\+0x308>
153 +.*: a7 84 00 00 [ ]*je 30c <foo\+0x30c>
154 +.*: a7 94 00 00 [ ]*jnlh 310 <foo\+0x310>
155 +.*: a7 a4 00 00 [ ]*jhe 314 <foo\+0x314>
156 +.*: a7 b4 00 00 [ ]*jnl 318 <foo\+0x318>
157 +.*: a7 b4 00 00 [ ]*jnl 31c <foo\+0x31c>
158 +.*: a7 c4 00 00 [ ]*jle 320 <foo\+0x320>
159 +.*: a7 d4 00 00 [ ]*jnh 324 <foo\+0x324>
160 +.*: a7 d4 00 00 [ ]*jnh 328 <foo\+0x328>
161 +.*: a7 e4 00 00 [ ]*jno 32c <foo\+0x32c>
162 +.*: a7 f4 00 00 [ ]*j 330 <foo\+0x330>
163 .*: ed 65 af ff 00 18 [ ]*kdb %f6,4095\(%r5,%r10\)
164 .*: b3 18 00 69 [ ]*kdbr %f6,%f9
165 .*: ed 65 af ff 00 08 [ ]*keb %f6,4095\(%r5,%r10\)
166 @@ -483,4 +509,4 @@ Disassembly of section .text:
167 .*: f8 58 5f ff af ff [ ]*zap 4095\(6,%r5\),4095\(9,%r10\)
168 .*: b2 21 b0 69 [ ]*ipte %r6,%r9,%r11
169 .*: b2 21 bd 69 [ ]*ipte %r6,%r9,%r11,13
170 -.*: 07 07 [ ]*nopr %r7
171 +.*: 07 07 [ ]*nopr %r7
172 diff -rup binutils.orig/gas/testsuite/gas/s390/esa-g5.s binutils-2.35.1/gas/testsuite/gas/s390/esa-g5.s
173 --- binutils.orig/gas/testsuite/gas/s390/esa-g5.s 2021-03-25 14:35:41.038632922 +0000
174 +++ binutils-2.35.1/gas/testsuite/gas/s390/esa-g5.s 2021-03-25 14:39:56.534387545 +0000
175 @@ -72,10 +72,14 @@ foo:
176 bpr %r9
177 br %r9
178 bras %r9,.
179 + jas %r6,.
180 brc 6,.
181 brct 6,.
182 + jct %r6,.
183 brxh %r6,%r9,.
184 + jxh %r6,%r9,.
185 brxle %r6,%r9,.
186 + jxle %r6,%r9,.
187 bsa %r6,%r9
188 bsg %r6,%r9
189 bsm %r6,%r9
190 @@ -195,6 +199,28 @@ foo:
191 jo .
192 jp .
193 jz .
194 + jnop .
195 + bro .
196 + brh .
197 + brp .
198 + brnle .
199 + brl .
200 + brm .
201 + brnhe .
202 + brlh .
203 + brne .
204 + brnz .
205 + bre .
206 + brz .
207 + brnlh .
208 + brhe .
209 + brnl .
210 + brnm .
211 + brle .
212 + brnh .
213 + brnp .
214 + brno .
215 + bru .
216 kdb %f6,4095(%r5,%r10)
217 kdbr %f6,%f9
218 keb %f6,4095(%r5,%r10)
219 diff -rup binutils.orig/gas/testsuite/gas/s390/esa-z900.d binutils-2.35.1/gas/testsuite/gas/s390/esa-z900.d
220 --- binutils.orig/gas/testsuite/gas/s390/esa-z900.d 2021-03-25 14:35:41.038632922 +0000
221 +++ binutils-2.35.1/gas/testsuite/gas/s390/esa-z900.d 2021-03-25 14:39:56.534387545 +0000
222 @@ -6,29 +6,52 @@
223 Disassembly of section .text:
225 .* <foo>:
226 -.*: c0 f4 00 00 00 00 [ ]*jg 0 \<foo\>
227 -.*: c0 14 00 00 00 00 [ ]*jgo 6 \<foo\+0x6>
228 -.*: c0 24 00 00 00 00 [ ]*jgh c \<foo\+0xc>
229 -.*: c0 24 00 00 00 00 [ ]*jgh 12 \<foo\+0x12>
230 -.*: c0 34 00 00 00 00 [ ]*jgnle 18 \<foo\+0x18>
231 -.*: c0 44 00 00 00 00 [ ]*jgl 1e \<foo\+0x1e>
232 -.*: c0 44 00 00 00 00 [ ]*jgl 24 \<foo\+0x24>
233 -.*: c0 54 00 00 00 00 [ ]*jgnhe 2a \<foo\+0x2a>
234 -.*: c0 64 00 00 00 00 [ ]*jglh 30 \<foo\+0x30>
235 -.*: c0 74 00 00 00 00 [ ]*jgne 36 \<foo\+0x36>
236 -.*: c0 74 00 00 00 00 [ ]*jgne 3c \<foo\+0x3c>
237 -.*: c0 84 00 00 00 00 [ ]*jge 42 \<foo\+0x42>
238 -.*: c0 84 00 00 00 00 [ ]*jge 48 \<foo\+0x48>
239 -.*: c0 94 00 00 00 00 [ ]*jgnlh 4e \<foo\+0x4e>
240 -.*: c0 a4 00 00 00 00 [ ]*jghe 54 \<foo\+0x54>
241 -.*: c0 b4 00 00 00 00 [ ]*jgnl 5a \<foo\+0x5a>
242 -.*: c0 b4 00 00 00 00 [ ]*jgnl 60 \<foo\+0x60>
243 -.*: c0 c4 00 00 00 00 [ ]*jgle 66 \<foo\+0x66>
244 -.*: c0 d4 00 00 00 00 [ ]*jgnh 6c \<foo\+0x6c>
245 -.*: c0 d4 00 00 00 00 [ ]*jgnh 72 \<foo\+0x72>
246 -.*: c0 e4 00 00 00 00 [ ]*jgno 78 \<foo\+0x78>
247 -.*: c0 f4 00 00 00 00 [ ]*jg 7e \<foo\+0x7e>
248 -.*: c0 65 00 00 00 00 [ ]*brasl %r6,84 \<foo\+0x84>
249 +.*: c0 f4 00 00 00 00 [ ]*jg 0 <foo>
250 +.*: c0 04 00 00 00 00 [ ]*jgnop 6 <foo\+0x6>
251 +.*: c0 14 00 00 00 00 [ ]*jgo c <foo\+0xc>
252 +.*: c0 24 00 00 00 00 [ ]*jgh 12 <foo\+0x12>
253 +.*: c0 24 00 00 00 00 [ ]*jgh 18 <foo\+0x18>
254 +.*: c0 34 00 00 00 00 [ ]*jgnle 1e <foo\+0x1e>
255 +.*: c0 44 00 00 00 00 [ ]*jgl 24 <foo\+0x24>
256 +.*: c0 44 00 00 00 00 [ ]*jgl 2a <foo\+0x2a>
257 +.*: c0 54 00 00 00 00 [ ]*jgnhe 30 <foo\+0x30>
258 +.*: c0 64 00 00 00 00 [ ]*jglh 36 <foo\+0x36>
259 +.*: c0 74 00 00 00 00 [ ]*jgne 3c <foo\+0x3c>
260 +.*: c0 74 00 00 00 00 [ ]*jgne 42 <foo\+0x42>
261 +.*: c0 84 00 00 00 00 [ ]*jge 48 <foo\+0x48>
262 +.*: c0 84 00 00 00 00 [ ]*jge 4e <foo\+0x4e>
263 +.*: c0 94 00 00 00 00 [ ]*jgnlh 54 <foo\+0x54>
264 +.*: c0 a4 00 00 00 00 [ ]*jghe 5a <foo\+0x5a>
265 +.*: c0 b4 00 00 00 00 [ ]*jgnl 60 <foo\+0x60>
266 +.*: c0 b4 00 00 00 00 [ ]*jgnl 66 <foo\+0x66>
267 +.*: c0 c4 00 00 00 00 [ ]*jgle 6c <foo\+0x6c>
268 +.*: c0 d4 00 00 00 00 [ ]*jgnh 72 <foo\+0x72>
269 +.*: c0 d4 00 00 00 00 [ ]*jgnh 78 <foo\+0x78>
270 +.*: c0 e4 00 00 00 00 [ ]*jgno 7e <foo\+0x7e>
271 +.*: c0 f4 00 00 00 00 [ ]*jg 84 <foo\+0x84>
272 +.*: c0 14 00 00 00 00 [ ]*jgo 8a <foo\+0x8a>
273 +.*: c0 24 00 00 00 00 [ ]*jgh 90 <foo\+0x90>
274 +.*: c0 24 00 00 00 00 [ ]*jgh 96 <foo\+0x96>
275 +.*: c0 34 00 00 00 00 [ ]*jgnle 9c <foo\+0x9c>
276 +.*: c0 44 00 00 00 00 [ ]*jgl a2 <foo\+0xa2>
277 +.*: c0 44 00 00 00 00 [ ]*jgl a8 <foo\+0xa8>
278 +.*: c0 54 00 00 00 00 [ ]*jgnhe ae <foo\+0xae>
279 +.*: c0 64 00 00 00 00 [ ]*jglh b4 <foo\+0xb4>
280 +.*: c0 74 00 00 00 00 [ ]*jgne ba <foo\+0xba>
281 +.*: c0 74 00 00 00 00 [ ]*jgne c0 <foo\+0xc0>
282 +.*: c0 84 00 00 00 00 [ ]*jge c6 <foo\+0xc6>
283 +.*: c0 84 00 00 00 00 [ ]*jge cc <foo\+0xcc>
284 +.*: c0 94 00 00 00 00 [ ]*jgnlh d2 <foo\+0xd2>
285 +.*: c0 a4 00 00 00 00 [ ]*jghe d8 <foo\+0xd8>
286 +.*: c0 b4 00 00 00 00 [ ]*jgnl de <foo\+0xde>
287 +.*: c0 b4 00 00 00 00 [ ]*jgnl e4 <foo\+0xe4>
288 +.*: c0 c4 00 00 00 00 [ ]*jgle ea <foo\+0xea>
289 +.*: c0 d4 00 00 00 00 [ ]*jgnh f0 <foo\+0xf0>
290 +.*: c0 d4 00 00 00 00 [ ]*jgnh f6 <foo\+0xf6>
291 +.*: c0 e4 00 00 00 00 [ ]*jgno fc <foo\+0xfc>
292 +.*: c0 f4 00 00 00 00 [ ]*jg 102 <foo\+0x102>
293 +.*: c0 65 00 00 00 00 [ ]*brasl %r6,108 <foo\+0x108>
294 +.*: c0 65 00 00 00 00 [ ]*brasl %r6,10e <foo\+0x10e>
295 .*: 01 0b [ ]*tam
296 .*: 01 0c [ ]*sam24
297 .*: 01 0d [ ]*sam31
298 @@ -39,7 +62,7 @@ Disassembly of section .text:
299 .*: b9 97 00 69 [ ]*dlr %r6,%r9
300 .*: b9 98 00 69 [ ]*alcr %r6,%r9
301 .*: b9 99 00 69 [ ]*slbr %r6,%r9
302 -.*: c0 60 00 00 00 00 [ ]*larl %r6,ac \<foo\+0xac\>
303 +.*: c0 60 00 00 00 00 [ ]*larl %r6,136 <foo\+0x136>
304 .*: e3 65 af ff 00 1e [ ]*lrv %r6,4095\(%r5,%r10\)
305 .*: e3 65 af ff 00 1f [ ]*lrvh %r6,4095\(%r5,%r10\)
306 .*: e3 65 af ff 00 3e [ ]*strv %r6,4095\(%r5,%r10\)
307 @@ -49,3 +72,4 @@ Disassembly of section .text:
308 .*: e3 65 af ff 00 98 [ ]*alc %r6,4095\(%r5,%r10\)
309 .*: e3 65 af ff 00 99 [ ]*slb %r6,4095\(%r5,%r10\)
310 .*: eb 69 5f ff 00 1d [ ]*rll %r6,%r9,4095\(%r5\)
311 +.*: 07 07 [ ]*nopr %r7
312 diff -rup binutils.orig/gas/testsuite/gas/s390/esa-z900.s binutils-2.35.1/gas/testsuite/gas/s390/esa-z900.s
313 --- binutils.orig/gas/testsuite/gas/s390/esa-z900.s 2021-03-25 14:35:41.037632927 +0000
314 +++ binutils-2.35.1/gas/testsuite/gas/s390/esa-z900.s 2021-03-25 14:39:56.534387545 +0000
315 @@ -1,6 +1,7 @@
316 .text
317 foo:
318 brcl 15,.
319 + jgnop .
320 jgo .
321 jgh .
322 jgp .
323 @@ -22,7 +23,29 @@ foo:
324 jgnp .
325 jgno .
326 jg .
327 + brol .
328 + brhl .
329 + brpl .
330 + brnlel .
331 + brll .
332 + brml .
333 + brnhel .
334 + brlhl .
335 + brnel .
336 + brnzl .
337 + brel .
338 + brzl .
339 + brnlhl .
340 + brhel .
341 + brnll .
342 + brnml .
343 + brlel .
344 + brnhl .
345 + brnpl .
346 + brnol .
347 + brul .
348 brasl %r6,.
349 + jasl %r6,.
350 tam
351 sam24
352 sam31
353 Only in binutils-2.35.1/gas/testsuite/gas/s390: s390.exp.rej
354 Only in binutils-2.35.1/gas/testsuite/gas/s390: zarch-arch14.d
355 Only in binutils-2.35.1/gas/testsuite/gas/s390: zarch-arch14.s
356 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z10.d binutils-2.35.1/gas/testsuite/gas/s390/zarch-z10.d
357 --- binutils.orig/gas/testsuite/gas/s390/zarch-z10.d 2021-03-25 14:35:41.038632922 +0000
358 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-z10.d 2021-03-25 14:39:49.766420543 +0000
359 @@ -362,11 +362,13 @@ Disassembly of section .text:
360 .*: ec 67 d2 dc e6 54 [ ]*rnsbg %r6,%r7,210,220,230
361 .*: ec 67 d2 dc e6 57 [ ]*rxsbg %r6,%r7,210,220,230
362 .*: ec 67 d2 dc e6 56 [ ]*rosbg %r6,%r7,210,220,230
363 -.*: ec 67 d2 dc e6 55 [ ]*risbg %r6,%r7,210,220,230
364 -.*: c4 6f 00 00 00 00 [ ]*strl %r6,7f6 <foo\+0x7f6>
365 -.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,7fc <foo\+0x7fc>
366 -.*: c4 67 00 00 00 00 [ ]*sthrl %r6,802 <foo\+0x802>
367 -.*: c6 60 00 00 00 00 [ ]*exrl %r6,808 <foo\+0x808>
368 +.*: ec 67 d2 14 e6 55 [ ]*risbg %r6,%r7,210,20,230
369 +.*: ec 67 d2 bc e6 55 [ ]*risbgz %r6,%r7,210,60,230
370 +.*: ec 67 d2 94 e6 55 [ ]*risbgz %r6,%r7,210,20,230
371 +.*: c4 6f 00 00 00 00 [ ]*strl %r6,802 <foo\+0x802>
372 +.*: c4 6b 00 00 00 00 [ ]*stgrl %r6,808 <foo\+0x808>
373 +.*: c4 67 00 00 00 00 [ ]*sthrl %r6,80e <foo\+0x80e>
374 +.*: c6 60 00 00 00 00 [ ]*exrl %r6,814 <foo\+0x814>
375 .*: af ee 6d 05 [ ]*mc 3333\(%r6\),238
376 .*: b9 a2 00 60 [ ]*ptf %r6
377 .*: b9 af 00 67 [ ]*pfmf %r6,%r7
378 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z10.s binutils-2.35.1/gas/testsuite/gas/s390/zarch-z10.s
379 --- binutils.orig/gas/testsuite/gas/s390/zarch-z10.s 2021-03-25 14:35:41.038632922 +0000
380 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-z10.s 2021-03-25 14:39:49.766420543 +0000
381 @@ -356,7 +356,9 @@ foo:
382 rnsbg %r6,%r7,210,220,230
383 rxsbg %r6,%r7,210,220,230
384 rosbg %r6,%r7,210,220,230
385 - risbg %r6,%r7,210,220,230
386 + risbg %r6,%r7,210,20,230
387 + risbg %r6,%r7,210,188,230
388 + risbgz %r6,%r7,210,20,230
389 strl %r6,.
390 stgrl %r6,.
391 sthrl %r6,.
392 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z900.d binutils-2.35.1/gas/testsuite/gas/s390/zarch-z900.d
393 --- binutils.orig/gas/testsuite/gas/s390/zarch-z900.d 2021-03-25 14:35:41.037632927 +0000
394 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-z900.d 2021-03-25 14:39:56.534387545 +0000
395 @@ -20,8 +20,11 @@ Disassembly of section .text:
396 .*: e3 95 af ff 00 46 [ ]*bctg %r9,4095\(%r5,%r10\)
397 .*: b9 46 00 96 [ ]*bctgr %r9,%r6
398 .*: a7 97 00 00 [ ]*brctg %r9,40 \<foo\+0x40\>
399 -.*: ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,44 <foo\+0x44>
400 -.*: ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,4a <foo\+0x4a>
401 +.*: a7 67 00 00 [ ]*brctg %r6,44 <foo\+0x44>
402 +.*: ec 96 00 00 00 44 [ ]*brxhg %r9,%r6,48 <foo\+0x48>
403 +.*: ec 69 00 00 00 44 [ ]*brxhg %r6,%r9,4e <foo\+0x4e>
404 +.*: ec 96 00 00 00 45 [ ]*brxlg %r9,%r6,54 <foo\+0x54>
405 +.*: ec 69 00 00 00 45 [ ]*brxlg %r6,%r9,5a <foo\+0x5a>
406 .*: eb 96 5f ff 00 44 [ ]*bxhg %r9,%r6,4095\(%r5\)
407 .*: eb 96 5f ff 00 45 [ ]*bxleg %r9,%r6,4095\(%r5\)
408 .*: b3 a5 00 96 [ ]*cdgbr %f9,%r6
409 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z900.s binutils-2.35.1/gas/testsuite/gas/s390/zarch-z900.s
410 --- binutils.orig/gas/testsuite/gas/s390/zarch-z900.s 2021-03-25 14:35:41.038632922 +0000
411 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-z900.s 2021-03-25 14:39:56.534387545 +0000
412 @@ -14,8 +14,11 @@ foo:
413 bctg %r9,4095(%r5,%r10)
414 bctgr %r9,%r6
415 brctg %r9,.
416 + jctg %r6,.
417 brxhg %r9,%r6,.
418 + jxhg %r6,%r9,.
419 brxlg %r9,%r6,.
420 + jxleg %r6,%r9,.
421 bxhg %r9,%r6,4095(%r5)
422 bxleg %r9,%r6,4095(%r5)
423 cdgbr %f9,%r6
424 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-zEC12.d binutils-2.35.1/gas/testsuite/gas/s390/zarch-zEC12.d
425 --- binutils.orig/gas/testsuite/gas/s390/zarch-zEC12.d 2021-03-25 14:35:41.037632927 +0000
426 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-zEC12.d 2021-03-25 14:39:49.766420543 +0000
427 @@ -47,6 +47,8 @@ Disassembly of section .text:
428 .*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
429 .*: eb 6c 7a 4d fe 2b [ ]*clgtnh %r6,-5555\(%r7\)
430 .*: ec 67 0c 0d 0e 59 [ ]*risbgn %r6,%r7,12,13,14
431 +.*: ec 67 0c bc 0e 59 [ ]*risbgnz %r6,%r7,12,60,14
432 +.*: ec 67 0c 94 0e 59 [ ]*risbgnz %r6,%r7,12,20,14
433 .*: ed 0f 8f a0 6d aa [ ]*cdzt %f6,4000\(16,%r8\),13
434 .*: ed 21 8f a0 4d ab [ ]*cxzt %f4,4000\(34,%r8\),13
435 .*: ed 0f 8f a0 6d a8 [ ]*czdt %f6,4000\(16,%r8\),13
436 @@ -54,16 +56,16 @@ Disassembly of section .text:
437 .*: b2 e8 c0 56 [ ]*ppa %r5,%r6,12
438 .*: b9 8f 60 59 [ ]*crdte %r5,%r6,%r9
439 .*: b9 8f 61 59 [ ]*crdte %r5,%r6,%r9,1
440 -.*: c5 a0 0c 00 00 0c [ ]*bprp 10,12a <bar>,12a <bar>
441 -.*: c5 a0 00 00 00 00 [ ]*bprp 10,118 <foo\+0x118>,118 <foo\+0x118>
442 -[ ]*119: R_390_PLT12DBL bar\+0x1
443 -[ ]*11b: R_390_PLT24DBL bar\+0x3
444 -.*: c7 a0 00 00 00 00 [ ]*bpp 10,11e <foo\+0x11e>,0
445 -[ ]*122: R_390_PLT16DBL bar\+0x4
446 -.*: c7 a0 00 00 00 00 [ ]*bpp 10,124 <foo\+0x124>,0
447 -[ ]*128: R_390_PC16DBL baz\+0x4
448 +.*: c5 a0 0c 00 00 0c [ ]*bprp 10,136 <bar>,136 <bar>
449 +.*: c5 a0 00 00 00 00 [ ]*bprp 10,124 <foo\+0x124>,124 <foo\+0x124>
450 +[ ]*125: R_390_PLT12DBL bar\+0x1
451 +[ ]*127: R_390_PLT24DBL bar\+0x3
452 +.*: c7 a0 00 00 00 00 [ ]*bpp 10,12a <foo\+0x12a>,0
453 +[ ]*12e: R_390_PLT16DBL bar\+0x4
454 +.*: c7 a0 00 00 00 00 [ ]*bpp 10,130 <foo\+0x130>,0
455 +[ ]*134: R_390_PC16DBL baz\+0x4
458 -000000000000012a <bar>:
459 +0000000000000136 <bar>:
461 .*: 07 07 [ ]*nopr %r7
462 diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-zEC12.s binutils-2.35.1/gas/testsuite/gas/s390/zarch-zEC12.s
463 --- binutils.orig/gas/testsuite/gas/s390/zarch-zEC12.s 2021-03-25 14:35:41.038632922 +0000
464 +++ binutils-2.35.1/gas/testsuite/gas/s390/zarch-zEC12.s 2021-03-25 14:39:49.766420543 +0000
465 @@ -44,6 +44,9 @@ foo:
466 clgtnh %r6,-5555(%r7)
468 risbgn %r6,%r7,12,13,14
469 + risbgn %r6,%r7,12,188,14
470 + risbgnz %r6,%r7,12,20,14
471 +
472 cdzt %f6,4000(16,%r8),13
473 cxzt %f4,4000(34,%r8),13
474 czdt %f6,4000(16,%r8),13
475 Only in binutils-2.35.1/include: ChangeLog.orig
476 Only in binutils-2.35.1/include: ChangeLog.rej
477 Only in binutils-2.35.1/include/opcode: s390.h.rej
478 Only in binutils-2.35.1/ld: ChangeLog.orig
479 Only in binutils-2.35.1/ld: ChangeLog.rej
480 diff -rup binutils.orig/ld/testsuite/ld-s390/tlsbin_64.dd binutils-2.35.1/ld/testsuite/ld-s390/tlsbin_64.dd
481 --- binutils.orig/ld/testsuite/ld-s390/tlsbin_64.dd 2021-03-25 14:35:40.826633955 +0000
482 +++ binutils-2.35.1/ld/testsuite/ld-s390/tlsbin_64.dd 2021-03-25 14:39:56.534387545 +0000
483 @@ -87,26 +87,26 @@ Disassembly of section .text:
484 +[0-9a-f]+: 41 22 90 00 la %r2,0\(%r2,%r9\)
485 # GD -> LE with global variable defined in executable
486 +[0-9a-f]+: e3 20 d0 10 00 04 lg %r2,16\(%r13\)
487 - +[0-9a-f]+: c0 04 00 00 00 00 brcl 0,[0-9a-f]+ <fn2\+0xca>
488 + +[0-9a-f]+: c0 04 00 00 00 00 jgnop [0-9a-f]+ <fn2\+0xca>
489 +[0-9a-f]+: 41 22 90 00 la %r2,0\(%r2,%r9\)
490 # GD -> LE with local variable defined in executable
491 +[0-9a-f]+: e3 20 d0 18 00 04 lg %r2,24\(%r13\)
492 - +[0-9a-f]+: c0 04 00 00 00 00 brcl 0,[0-9a-f]+ <fn2\+0xda>
493 + +[0-9a-f]+: c0 04 00 00 00 00 jgnop [0-9a-f]+ <fn2\+0xda>
494 +[0-9a-f]+: 41 22 90 00 la %r2,0\(%r2,%r9\)
495 # GD -> LE with hidden variable defined in executable
496 +[0-9a-f]+: e3 20 d0 20 00 04 lg %r2,32\(%r13\)
497 - +[0-9a-f]+: c0 04 00 00 00 00 brcl 0,[0-9a-f]+ <fn2\+0xea>
498 + +[0-9a-f]+: c0 04 00 00 00 00 jgnop [0-9a-f]+ <fn2\+0xea>
499 +[0-9a-f]+: 41 22 90 00 la %r2,0\(%r2,%r9\)
500 # LD -> LE
501 +[0-9a-f]+: e3 20 d0 28 00 04 lg %r2,40\(%r13\)
502 - +[0-9a-f]+: c0 04 00 00 00 00 brcl 0,[0-9a-f]+ <fn2\+0xfa>
503 + +[0-9a-f]+: c0 04 00 00 00 00 jgnop [0-9a-f]+ <fn2\+0xfa>
504 +[0-9a-f]+: 41 32 90 00 la %r3,0\(%r2,%r9\)
505 +[0-9a-f]+: e3 40 d0 30 00 04 lg %r4,48\(%r13\)
506 +[0-9a-f]+: 41 54 30 00 la %r5,0\(%r4,%r3\)
507 +[0-9a-f]+: e3 40 d0 38 00 04 lg %r4,56\(%r13\)
508 +[0-9a-f]+: 41 54 30 00 la %r5,0\(%r4,%r3\)
509 +[0-9a-f]+: e3 20 d0 40 00 04 lg %r2,64\(%r13\)
510 - +[0-9a-f]+: c0 04 00 00 00 00 brcl 0,[0-9a-f]+ <fn2\+0x11e>
511 + +[0-9a-f]+: c0 04 00 00 00 00 jgnop [0-9a-f]+ <fn2\+0x11e>
512 +[0-9a-f]+: 41 32 90 00 la %r3,0\(%r2,%r9\)
513 +[0-9a-f]+: e3 40 d0 48 00 04 lg %r4,72\(%r13\)
514 +[0-9a-f]+: 41 54 30 00 la %r5,0\(%r4,%r3\)
515 Only in binutils-2.35.1/opcodes: ChangeLog.orig
516 Only in binutils-2.35.1/opcodes: ChangeLog.rej
517 Only in binutils-2.35.1/opcodes: s390-mkopc.c.rej
518 diff -rup binutils.orig/opcodes/s390-opc.c binutils-2.35.1/opcodes/s390-opc.c
519 --- binutils.orig/opcodes/s390-opc.c 2021-03-25 14:35:40.719634477 +0000
520 +++ binutils-2.35.1/opcodes/s390-opc.c 2021-03-25 14:39:49.766420543 +0000
521 @@ -218,32 +218,34 @@ const struct s390_operand s390_operands[
522 { 8, 8, 0 },
523 #define U8_16 68 /* 8 bit unsigned value starting at 16 */
524 { 8, 16, 0 },
525 -#define U8_24 69 /* 8 bit unsigned value starting at 24 */
526 +#define U6_26 69 /* 6 bit unsigned value starting at 26 */
527 + { 6, 26, 0 },
528 +#define U8_24 70 /* 8 bit unsigned value starting at 24 */
529 { 8, 24, 0 },
530 -#define U8_28 70 /* 8 bit unsigned value starting at 28 */
531 +#define U8_28 71 /* 8 bit unsigned value starting at 28 */
532 { 8, 28, 0 },
533 -#define U8_32 71 /* 8 bit unsigned value starting at 32 */
534 +#define U8_32 72 /* 8 bit unsigned value starting at 32 */
535 { 8, 32, 0 },
536 -#define U12_16 72 /* 12 bit unsigned value starting at 16 */
537 +#define U12_16 73 /* 12 bit unsigned value starting at 16 */
538 { 12, 16, 0 },
539 -#define U16_16 73 /* 16 bit unsigned value starting at 16 */
540 +#define U16_16 74 /* 16 bit unsigned value starting at 16 */
541 { 16, 16, 0 },
542 -#define U16_32 74 /* 16 bit unsigned value starting at 32 */
543 +#define U16_32 75 /* 16 bit unsigned value starting at 32 */
544 { 16, 32, 0 },
545 -#define U32_16 75 /* 32 bit unsigned value starting at 16 */
546 +#define U32_16 76 /* 32 bit unsigned value starting at 16 */
547 { 32, 16, 0 },
549 /* PC-relative address operands. */
551 -#define J12_12 76 /* 12 bit PC relative offset at 12 */
552 +#define J12_12 77 /* 12 bit PC relative offset at 12 */
553 { 12, 12, S390_OPERAND_PCREL },
554 -#define J16_16 77 /* 16 bit PC relative offset at 16 */
555 +#define J16_16 78 /* 16 bit PC relative offset at 16 */
556 { 16, 16, S390_OPERAND_PCREL },
557 -#define J16_32 78 /* 16 bit PC relative offset at 32 */
558 +#define J16_32 79 /* 16 bit PC relative offset at 32 */
559 { 16, 32, S390_OPERAND_PCREL },
560 -#define J24_24 79 /* 24 bit PC relative offset at 24 */
561 +#define J24_24 80 /* 24 bit PC relative offset at 24 */
562 { 24, 24, S390_OPERAND_PCREL },
563 -#define J32_16 80 /* 32 bit PC relative offset at 16 */
564 +#define J32_16 81 /* 32 bit PC relative offset at 16 */
565 { 32, 16, S390_OPERAND_PCREL },
567 };
568 @@ -313,6 +315,7 @@ const struct s390_operand s390_operands[
569 #define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */
570 #define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */
571 #define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */
572 +#define INSTR_RIE_RRUUU2 6, { R_8,R_12,U8_16,U6_26,U8_32,0 } /* e.g. rnsbg */
573 #define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */
574 #define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
575 #define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
576 @@ -534,6 +537,7 @@ const struct s390_operand s390_operands[
577 #define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
578 #define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
579 #define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
580 +#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0xc0, 0x00, 0xff }
581 #define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
582 #define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
583 #define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
584 diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.35.1/opcodes/s390-opc.txt
585 --- binutils.orig/opcodes/s390-opc.txt 2021-03-25 14:35:40.728634433 +0000
586 +++ binutils-2.35.1/opcodes/s390-opc.txt 2021-03-25 14:39:56.534387545 +0000
587 @@ -246,10 +246,14 @@ d7 xc SS_L0RDRD "exclusive OR" g5 esa,za
588 f8 zap SS_LLRDRD "zero and add" g5 esa,zarch
589 a70a ahi RI_RI "add halfword immediate" g5 esa,zarch
590 84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch
591 +84 jxh RSI_RRP "branch relative on index high" g5 esa,zarch
592 85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch
593 +85 jxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch
594 a705 bras RI_RP "branch relative and save" g5 esa,zarch
595 +a705 jas RI_RP "branch relative and save" g5 esa,zarch
596 a704 brc RI_UP "branch relative on condition" g5 esa,zarch
597 a706 brct RI_RP "branch relative on count" g5 esa,zarch
598 +a706 jct RI_RP "branch relative on count" g5 esa,zarch
599 b241 cksm RRE_RR "checksum" g5 esa,zarch
600 a70e chi RI_RI "compare halfword immediate" g5 esa,zarch
601 a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch
602 @@ -268,8 +272,11 @@ a701 tml RI_RU "test under mask low" g5
603 4700 nop RX_0RRD "no operation" g5 esa,zarch optparm
604 4700 b*8 RX_0RRD "conditional branch" g5 esa,zarch
605 47f0 b RX_0RRD "unconditional branch" g5 esa,zarch
606 +a704 jnop RI_0P "nop jump" g5 esa,zarch
607 a704 j*8 RI_0P "conditional jump" g5 esa,zarch
608 +a704 br*8 RI_0P "conditional jump" g5 esa,zarch
609 a7f4 j RI_0P "unconditional jump" g5 esa,zarch
610 +a7f4 bru RI_0P "unconditional jump" g5 esa,zarch
611 b34a axbr RRE_FEFE "add extended bfp" g5 esa,zarch
612 b31a adbr RRE_FF "add long bfp" g5 esa,zarch
613 ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch
614 @@ -437,7 +444,9 @@ e3000000001b slgf RXE_RRRD "subtract log
615 e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch
616 e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch
617 ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch
618 +ec0000000044 jxhg RIE_RRP "branch relative on index high 64" z900 zarch
619 ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch
620 +ec0000000045 jxleg RIE_RRP "branch relative on index low or equal 64" z900 zarch
621 eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch
622 eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch
623 eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch
624 @@ -462,10 +471,15 @@ eb0000000080 icmh RSE_RURD "insert chara
625 a702 tmhh RI_RU "test under mask high high" z900 zarch
626 a703 tmhl RI_RU "test under mask high low" z900 zarch
627 c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch
628 +c004 jgnop RIL_0P "nop jump long" z900 esa,zarch
629 c004 jg*8 RIL_0P "conditional jump long" z900 esa,zarch
630 +c004 br*8l RIL_0P "conditional jump long" z900 esa,zarch
631 c0f4 jg RIL_0P "unconditional jump long" z900 esa,zarch
632 +c0f4 brul RIL_0P "unconditional jump long" z900 esa,zarch
633 c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch
634 +c005 jasl RIL_RP "branch relative and save long" z900 esa,zarch
635 a707 brctg RI_RP "branch relative on count 64" z900 zarch
636 +a707 jctg RI_RP "branch relative on count 64" z900 zarch
637 a709 lghi RI_RI "load halfword immediate 64" z900 zarch
638 a70b aghi RI_RI "add halfword immediate 64" z900 zarch
639 a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch
640 @@ -956,6 +970,7 @@ ec0000000054 rnsbg RIE_RRUUU "rotate the
641 ec0000000057 rxsbg RIE_RRUUU "rotate then exclusive or selected bits" z10 zarch
642 ec0000000056 rosbg RIE_RRUUU "rotate then or selected bits" z10 zarch
643 ec0000000055 risbg RIE_RRUUU "rotate then insert selected bits" z10 zarch
644 +ec0000800055 risbgz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits" z10 zarch
645 c40f strl RIL_RP "store relative long (32)" z10 zarch
646 c40b stgrl RIL_RP "store relative long (64)" z10 zarch
647 c407 sthrl RIL_RP "store halfword relative long" z10 zarch
648 @@ -1139,6 +1154,7 @@ eb0000000023 clt$12 RSY_R0RD "compare lo
649 eb000000002b clgt RSY_RURD "compare logical and trap 64 bit reg-mem" zEC12 zarch
650 eb000000002b clgt$12 RSY_R0RD "compare logical and trap 64 bit reg-mem" zEC12 zarch
651 ec0000000059 risbgn RIE_RRUUU "rotate then insert selected bits nocc" zEC12 zarch
652 +ec0000800059 risbgnz RIE_RRUUU2 "rotate then insert selected bits and zero remaining bits nocc" zEC12 zarch
653 ed00000000aa cdzt RSL_LRDFU "convert from zoned long" zEC12 zarch
654 ed00000000ab cxzt RSL_LRDFEU "convert from zoned extended" zEC12 zarch
655 ed00000000a8 czdt RSL_LRDFU "convert to zoned long" zEC12 zarch
656 Only in binutils-2.35.1/opcodes: s390-opc.txt.orig
657 Only in binutils-2.35.1/opcodes: s390-opc.txt.rej