3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.33 2007/06/26 07:47:28 hasso Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
114 #include "opt_polling.h"
116 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/kernel.h>
120 #include <sys/malloc.h>
121 #include <sys/mbuf.h>
122 /* #include <sys/module.h> */
123 #include <sys/rman.h>
124 #include <sys/serialize.h>
125 #include <sys/socket.h>
126 #include <sys/sockio.h>
127 #include <sys/sysctl.h>
130 #include <net/ethernet.h>
132 #include <net/ifq_var.h>
133 #include <net/if_arp.h>
134 #include <net/if_dl.h>
135 #include <net/if_media.h>
136 #include <net/if_types.h>
137 #include <net/vlan/if_vlan_var.h>
139 #include <dev/netif/mii_layer/mii.h>
140 #include <dev/netif/mii_layer/miivar.h>
142 #include <bus/pci/pcidevs.h>
143 #include <bus/pci/pcireg.h>
144 #include <bus/pci/pcivar.h>
146 /* "device miibus" required. See GENERIC if you get errors here. */
147 #include "miibus_if.h"
149 #include <dev/netif/re/if_rereg.h>
150 #include <dev/netif/re/if_revar.h>
152 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
154 #define RE_DISABLE_HWCSUM
158 * Various supported device vendors/types and their names.
160 static const struct re_type re_devs
[] = {
161 { PCI_VENDOR_DLINK
, PCI_PRODUCT_DLINK_DGE528T
, RE_HWREV_8169S
,
162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
163 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8139
, RE_HWREV_8139CPLUS
,
164 "RealTek 8139C+ 10/100BaseTX" },
165 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8101E
, RE_HWREV_8101E
,
166 "RealTek 8101E PCIe 10/100baseTX" },
167 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8168
, RE_HWREV_8168_SPIN1
,
168 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
169 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8168
, RE_HWREV_8168_SPIN2
,
170 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
171 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
, RE_HWREV_8169
,
172 "RealTek 8169 Gigabit Ethernet" },
173 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
, RE_HWREV_8169S
,
174 "RealTek 8169S Single-chip Gigabit Ethernet" },
175 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
, RE_HWREV_8169_8110SB
,
176 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
, RE_HWREV_8169_8110SC
,
178 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
179 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169SC
, RE_HWREV_8169_8110SC
,
180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
181 { PCI_VENDOR_REALTEK
, PCI_PRODUCT_REALTEK_RT8169
, RE_HWREV_8110S
,
182 "RealTek 8110S Single-chip Gigabit Ethernet" },
183 { PCI_VENDOR_COREGA
, PCI_PRODUCT_COREGA_CG_LAPCIGT
, RE_HWREV_8169S
,
184 "Corega CG-LAPCIGT Gigabit Ethernet" },
185 { PCI_VENDOR_LINKSYS
, PCI_PRODUCT_LINKSYS_EG1032
, RE_HWREV_8169S
,
186 "Linksys EG1032 Gigabit Ethernet" },
187 { PCI_VENDOR_USR2
, PCI_PRODUCT_USR2_997902
, RE_HWREV_8169S
,
188 "US Robotics 997902 Gigabit Ethernet" },
192 static const struct re_hwrev re_hwrevs
[] = {
193 { RE_HWREV_8139CPLUS
, RE_8139CPLUS
, RE_F_HASMPC
, "C+" },
194 { RE_HWREV_8168_SPIN1
, RE_8169
, RE_F_PCIE
, "8168" },
195 { RE_HWREV_8168_SPIN2
, RE_8169
, RE_F_PCIE
, "8168" },
196 { RE_HWREV_8169
, RE_8169
, RE_F_HASMPC
, "8169" },
197 { RE_HWREV_8169S
, RE_8169
, RE_F_HASMPC
, "8169S" },
198 { RE_HWREV_8110S
, RE_8169
, RE_F_HASMPC
, "8110S" },
199 { RE_HWREV_8169_8110SB
, RE_8169
, RE_F_HASMPC
, "8169SB" },
200 { RE_HWREV_8169_8110SC
, RE_8169
, 0, "8169SC" },
201 { RE_HWREV_8100E
, RE_8169
, RE_F_HASMPC
, "8100E" },
202 { RE_HWREV_8101E
, RE_8169
, RE_F_PCIE
, "8101E" },
206 static int re_probe(device_t
);
207 static int re_attach(device_t
);
208 static int re_detach(device_t
);
210 static int re_encap(struct re_softc
*, struct mbuf
**, int *, int *);
212 static void re_dma_map_addr(void *, bus_dma_segment_t
*, int, int);
213 static void re_dma_map_desc(void *, bus_dma_segment_t
*, int,
215 static int re_allocmem(device_t
, struct re_softc
*);
216 static int re_newbuf(struct re_softc
*, int, struct mbuf
*);
217 static int re_rx_list_init(struct re_softc
*);
218 static int re_tx_list_init(struct re_softc
*);
219 static void re_rxeof(struct re_softc
*);
220 static void re_txeof(struct re_softc
*);
221 static void re_intr(void *);
222 static void re_tick(void *);
223 static void re_tick_serialized(void *);
224 static void re_start(struct ifnet
*);
225 static int re_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
226 static void re_init(void *);
227 static void re_stop(struct re_softc
*);
228 static void re_watchdog(struct ifnet
*);
229 static int re_suspend(device_t
);
230 static int re_resume(device_t
);
231 static void re_shutdown(device_t
);
232 static int re_ifmedia_upd(struct ifnet
*);
233 static void re_ifmedia_sts(struct ifnet
*, struct ifmediareq
*);
235 static void re_eeprom_putbyte(struct re_softc
*, int);
236 static void re_eeprom_getword(struct re_softc
*, int, u_int16_t
*);
237 static void re_read_eeprom(struct re_softc
*, caddr_t
, int, int);
238 static int re_gmii_readreg(device_t
, int, int);
239 static int re_gmii_writereg(device_t
, int, int, int);
241 static int re_miibus_readreg(device_t
, int, int);
242 static int re_miibus_writereg(device_t
, int, int, int);
243 static void re_miibus_statchg(device_t
);
245 static void re_setmulti(struct re_softc
*);
246 static void re_reset(struct re_softc
*);
249 static int re_diag(struct re_softc
*);
252 #ifdef DEVICE_POLLING
253 static void re_poll(struct ifnet
*ifp
, enum poll_cmd cmd
, int count
);
256 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS
);
258 static device_method_t re_methods
[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe
, re_probe
),
261 DEVMETHOD(device_attach
, re_attach
),
262 DEVMETHOD(device_detach
, re_detach
),
263 DEVMETHOD(device_suspend
, re_suspend
),
264 DEVMETHOD(device_resume
, re_resume
),
265 DEVMETHOD(device_shutdown
, re_shutdown
),
268 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
269 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
272 DEVMETHOD(miibus_readreg
, re_miibus_readreg
),
273 DEVMETHOD(miibus_writereg
, re_miibus_writereg
),
274 DEVMETHOD(miibus_statchg
, re_miibus_statchg
),
279 static driver_t re_driver
= {
282 sizeof(struct re_softc
)
285 static devclass_t re_devclass
;
287 DECLARE_DUMMY_MODULE(if_re
);
288 DRIVER_MODULE(if_re
, pci
, re_driver
, re_devclass
, 0, 0);
289 DRIVER_MODULE(if_re
, cardbus
, re_driver
, re_devclass
, 0, 0);
290 DRIVER_MODULE(miibus
, re
, miibus_driver
, miibus_devclass
, 0, 0);
293 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
296 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
299 * Send a read command and address to the EEPROM, check for ACK.
302 re_eeprom_putbyte(struct re_softc
*sc
, int addr
)
306 d
= addr
| (RE_9346_READ
<< sc
->re_eewidth
);
309 * Feed in each bit and strobe the clock.
311 for (i
= 1 << (sc
->re_eewidth
+ 3); i
; i
>>= 1) {
313 EE_SET(RE_EE_DATAIN
);
315 EE_CLR(RE_EE_DATAIN
);
325 * Read a word of data stored in the EEPROM at address 'addr.'
328 re_eeprom_getword(struct re_softc
*sc
, int addr
, uint16_t *dest
)
334 * Send address of word we want to read.
336 re_eeprom_putbyte(sc
, addr
);
339 * Start reading bits from EEPROM.
341 for (i
= 0x8000; i
!= 0; i
>>= 1) {
344 if (CSR_READ_1(sc
, RE_EECMD
) & RE_EE_DATAOUT
)
354 * Read a sequence of words from the EEPROM.
357 re_read_eeprom(struct re_softc
*sc
, caddr_t dest
, int off
, int cnt
)
360 uint16_t word
= 0, *ptr
;
362 CSR_SETBIT_1(sc
, RE_EECMD
, RE_EEMODE_PROGRAM
);
365 for (i
= 0; i
< cnt
; i
++) {
366 CSR_SETBIT_1(sc
, RE_EECMD
, RE_EE_SEL
);
367 re_eeprom_getword(sc
, off
+ i
, &word
);
368 CSR_CLRBIT_1(sc
, RE_EECMD
, RE_EE_SEL
);
369 ptr
= (uint16_t *)(dest
+ (i
* 2));
373 CSR_CLRBIT_1(sc
, RE_EECMD
, RE_EEMODE_PROGRAM
);
377 re_gmii_readreg(device_t dev
, int phy
, int reg
)
379 struct re_softc
*sc
= device_get_softc(dev
);
386 /* Let the rgephy driver read the GMEDIASTAT register */
388 if (reg
== RE_GMEDIASTAT
)
389 return(CSR_READ_1(sc
, RE_GMEDIASTAT
));
391 CSR_WRITE_4(sc
, RE_PHYAR
, reg
<< 16);
394 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
395 rval
= CSR_READ_4(sc
, RE_PHYAR
);
396 if (rval
& RE_PHYAR_BUSY
)
401 if (i
== RE_TIMEOUT
) {
402 device_printf(dev
, "PHY read failed\n");
406 return(rval
& RE_PHYAR_PHYDATA
);
410 re_gmii_writereg(device_t dev
, int phy
, int reg
, int data
)
412 struct re_softc
*sc
= device_get_softc(dev
);
416 CSR_WRITE_4(sc
, RE_PHYAR
,
417 (reg
<< 16) | (data
& RE_PHYAR_PHYDATA
) | RE_PHYAR_BUSY
);
420 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
421 rval
= CSR_READ_4(sc
, RE_PHYAR
);
422 if ((rval
& RE_PHYAR_BUSY
) == 0)
428 device_printf(dev
, "PHY write failed\n");
434 re_miibus_readreg(device_t dev
, int phy
, int reg
)
436 struct re_softc
*sc
= device_get_softc(dev
);
438 uint16_t re8139_reg
= 0;
440 if (sc
->re_type
== RE_8169
) {
441 rval
= re_gmii_readreg(dev
, phy
, reg
);
445 /* Pretend the internal PHY is only at address 0 */
451 re8139_reg
= RE_BMCR
;
454 re8139_reg
= RE_BMSR
;
457 re8139_reg
= RE_ANAR
;
460 re8139_reg
= RE_ANER
;
463 re8139_reg
= RE_LPAR
;
469 * Allow the rlphy driver to read the media status
470 * register. If we have a link partner which does not
471 * support NWAY, this is the register which will tell
472 * us the results of parallel detection.
475 return(CSR_READ_1(sc
, RE_MEDIASTAT
));
477 device_printf(dev
, "bad phy register\n");
480 rval
= CSR_READ_2(sc
, re8139_reg
);
481 if (sc
->re_type
== RE_8139CPLUS
&& re8139_reg
== RE_BMCR
) {
482 /* 8139C+ has different bit layout. */
483 rval
&= ~(BMCR_LOOP
| BMCR_ISO
);
489 re_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
491 struct re_softc
*sc
= device_get_softc(dev
);
492 u_int16_t re8139_reg
= 0;
494 if (sc
->re_type
== RE_8169
)
495 return(re_gmii_writereg(dev
, phy
, reg
, data
));
497 /* Pretend the internal PHY is only at address 0 */
503 re8139_reg
= RE_BMCR
;
504 if (sc
->re_type
== RE_8139CPLUS
) {
505 /* 8139C+ has different bit layout. */
506 data
&= ~(BMCR_LOOP
| BMCR_ISO
);
510 re8139_reg
= RE_BMSR
;
513 re8139_reg
= RE_ANAR
;
516 re8139_reg
= RE_ANER
;
519 re8139_reg
= RE_LPAR
;
525 device_printf(dev
, "bad phy register\n");
528 CSR_WRITE_2(sc
, re8139_reg
, data
);
533 re_miibus_statchg(device_t dev
)
538 * Program the 64-bit multicast hash filter.
541 re_setmulti(struct re_softc
*sc
)
543 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
545 uint32_t hashes
[2] = { 0, 0 };
546 struct ifmultiaddr
*ifma
;
550 rxfilt
= CSR_READ_4(sc
, RE_RXCFG
);
552 if (ifp
->if_flags
& IFF_ALLMULTI
|| ifp
->if_flags
& IFF_PROMISC
) {
553 rxfilt
|= RE_RXCFG_RX_MULTI
;
554 CSR_WRITE_4(sc
, RE_RXCFG
, rxfilt
);
555 CSR_WRITE_4(sc
, RE_MAR0
, 0xFFFFFFFF);
556 CSR_WRITE_4(sc
, RE_MAR4
, 0xFFFFFFFF);
560 /* first, zot all the existing hash bits */
561 CSR_WRITE_4(sc
, RE_MAR0
, 0);
562 CSR_WRITE_4(sc
, RE_MAR4
, 0);
564 /* now program new ones */
565 LIST_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
566 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
568 h
= ether_crc32_be(LLADDR((struct sockaddr_dl
*)
569 ifma
->ifma_addr
), ETHER_ADDR_LEN
) >> 26;
571 hashes
[0] |= (1 << h
);
573 hashes
[1] |= (1 << (h
- 32));
578 rxfilt
|= RE_RXCFG_RX_MULTI
;
580 rxfilt
&= ~RE_RXCFG_RX_MULTI
;
582 CSR_WRITE_4(sc
, RE_RXCFG
, rxfilt
);
583 CSR_WRITE_4(sc
, RE_MAR0
, hashes
[0]);
584 CSR_WRITE_4(sc
, RE_MAR4
, hashes
[1]);
588 re_reset(struct re_softc
*sc
)
592 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_RESET
);
594 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
596 if ((CSR_READ_1(sc
, RE_COMMAND
) & RE_CMD_RESET
) == 0)
600 if_printf(&sc
->arpcom
.ac_if
, "reset never completed!\n");
602 CSR_WRITE_1(sc
, 0x82, 1);
607 * The following routine is designed to test for a defect on some
608 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
609 * lines connected to the bus, however for a 32-bit only card, they
610 * should be pulled high. The result of this defect is that the
611 * NIC will not work right if you plug it into a 64-bit slot: DMA
612 * operations will be done with 64-bit transfers, which will fail
613 * because the 64-bit data lines aren't connected.
615 * There's no way to work around this (short of talking a soldering
616 * iron to the board), however we can detect it. The method we use
617 * here is to put the NIC into digital loopback mode, set the receiver
618 * to promiscuous mode, and then try to send a frame. We then compare
619 * the frame data we sent to what was received. If the data matches,
620 * then the NIC is working correctly, otherwise we know the user has
621 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
622 * slot. In the latter case, there's no way the NIC can work correctly,
623 * so we print out a message on the console and abort the device attach.
627 re_diag(struct re_softc
*sc
)
629 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
631 struct ether_header
*eh
;
632 struct re_desc
*cur_rx
;
635 int total_len
, i
, error
= 0, phyaddr
;
636 uint8_t dst
[ETHER_ADDR_LEN
] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
637 uint8_t src
[ETHER_ADDR_LEN
] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
639 /* Allocate a single mbuf */
641 MGETHDR(m0
, MB_DONTWAIT
, MT_DATA
);
646 * Initialize the NIC in test mode. This sets the chip up
647 * so that it can send and receive frames, but performs the
648 * following special functions:
649 * - Puts receiver in promiscuous mode
650 * - Enables digital loopback mode
651 * - Leaves interrupts turned off
654 ifp
->if_flags
|= IFF_PROMISC
;
659 if (sc
->re_type
== RE_8169
)
664 re_miibus_writereg(sc
->re_dev
, phyaddr
, MII_BMCR
, BMCR_RESET
);
665 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
666 status
= re_miibus_readreg(sc
->re_dev
, phyaddr
, MII_BMCR
);
667 if (!(status
& BMCR_RESET
))
671 re_miibus_writereg(sc
->re_dev
, phyaddr
, MII_BMCR
, BMCR_LOOP
);
672 CSR_WRITE_2(sc
, RE_ISR
, RE_INTRS_DIAG
);
676 /* Put some data in the mbuf */
678 eh
= mtod(m0
, struct ether_header
*);
679 bcopy (dst
, eh
->ether_dhost
, ETHER_ADDR_LEN
);
680 bcopy (src
, eh
->ether_shost
, ETHER_ADDR_LEN
);
681 eh
->ether_type
= htons(ETHERTYPE_IP
);
682 m0
->m_pkthdr
.len
= m0
->m_len
= ETHER_MIN_LEN
- ETHER_CRC_LEN
;
685 * Queue the packet, start transmission.
686 * Note: ifq_handoff() ultimately calls re_start() for us.
689 CSR_WRITE_2(sc
, RE_ISR
, 0xFFFF);
690 error
= ifq_handoff(ifp
, m0
, NULL
);
697 /* Wait for it to propagate through the chip */
700 for (i
= 0; i
< RE_TIMEOUT
; i
++) {
701 status
= CSR_READ_2(sc
, RE_ISR
);
702 CSR_WRITE_2(sc
, RE_ISR
, status
);
703 if ((status
& (RE_ISR_TIMEOUT_EXPIRED
|RE_ISR_RX_OK
)) ==
704 (RE_ISR_TIMEOUT_EXPIRED
|RE_ISR_RX_OK
))
709 if (i
== RE_TIMEOUT
) {
710 if_printf(ifp
, "diagnostic failed to receive packet "
711 "in loopback mode\n");
717 * The packet should have been dumped into the first
718 * entry in the RX DMA ring. Grab it from there.
721 bus_dmamap_sync(sc
->re_ldata
.re_rx_list_tag
,
722 sc
->re_ldata
.re_rx_list_map
, BUS_DMASYNC_POSTREAD
);
723 bus_dmamap_sync(sc
->re_ldata
.re_mtag
, sc
->re_ldata
.re_rx_dmamap
[0],
724 BUS_DMASYNC_POSTWRITE
);
725 bus_dmamap_unload(sc
->re_ldata
.re_mtag
, sc
->re_ldata
.re_rx_dmamap
[0]);
727 m0
= sc
->re_ldata
.re_rx_mbuf
[0];
728 sc
->re_ldata
.re_rx_mbuf
[0] = NULL
;
729 eh
= mtod(m0
, struct ether_header
*);
731 cur_rx
= &sc
->re_ldata
.re_rx_list
[0];
732 total_len
= RE_RXBYTES(cur_rx
);
733 rxstat
= le32toh(cur_rx
->re_cmdstat
);
735 if (total_len
!= ETHER_MIN_LEN
) {
736 if_printf(ifp
, "diagnostic failed, received short packet\n");
741 /* Test that the received packet data matches what we sent. */
743 if (bcmp(eh
->ether_dhost
, dst
, ETHER_ADDR_LEN
) ||
744 bcmp(eh
->ether_shost
, &src
, ETHER_ADDR_LEN
) ||
745 be16toh(eh
->ether_type
) != ETHERTYPE_IP
) {
746 if_printf(ifp
, "WARNING, DMA FAILURE!\n");
747 if_printf(ifp
, "expected TX data: %6D/%6D/0x%x\n",
748 dst
, ":", src
, ":", ETHERTYPE_IP
);
749 if_printf(ifp
, "received RX data: %6D/%6D/0x%x\n",
750 eh
->ether_dhost
, ":", eh
->ether_shost
, ":",
751 ntohs(eh
->ether_type
));
752 if_printf(ifp
, "You may have a defective 32-bit NIC plugged "
753 "into a 64-bit PCI slot.\n");
754 if_printf(ifp
, "Please re-install the NIC in a 32-bit slot "
755 "for proper operation.\n");
756 if_printf(ifp
, "Read the re(4) man page for more details.\n");
761 /* Turn interface off, release resources */
765 ifp
->if_flags
&= ~IFF_PROMISC
;
775 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
776 * IDs against our list and return a device name if we find a match.
779 re_probe(device_t dev
)
781 const struct re_type
*t
;
785 uint16_t vendor
, product
;
789 vendor
= pci_get_vendor(dev
);
790 product
= pci_get_device(dev
);
793 * Only attach to rev.3 of the Linksys EG1032 adapter.
794 * Rev.2 is supported by sk(4).
796 if (vendor
== PCI_VENDOR_LINKSYS
&&
797 product
== PCI_PRODUCT_LINKSYS_EG1032
&&
798 pci_get_subdevice(dev
) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3
)
801 for (t
= re_devs
; t
->re_name
!= NULL
; t
++) {
802 if (product
== t
->re_did
&& vendor
== t
->re_vid
)
807 * Check if we found a RealTek device.
809 if (t
->re_name
== NULL
)
813 * Temporarily map the I/O space so we can read the chip ID register.
815 sc
= kmalloc(sizeof(*sc
), M_TEMP
, M_WAITOK
| M_ZERO
);
817 sc
->re_res
= bus_alloc_resource_any(dev
, SYS_RES_IOPORT
, &rid
,
819 if (sc
->re_res
== NULL
) {
820 device_printf(dev
, "couldn't map ports/memory\n");
825 sc
->re_btag
= rman_get_bustag(sc
->re_res
);
826 sc
->re_bhandle
= rman_get_bushandle(sc
->re_res
);
828 hwrev
= CSR_READ_4(sc
, RE_TXCFG
) & RE_TXCFG_HWREV
;
829 bus_release_resource(dev
, SYS_RES_IOPORT
, RE_PCI_LOIO
, sc
->re_res
);
833 * and continue matching for the specific chip...
835 for (; t
->re_name
!= NULL
; t
++) {
836 if (product
== t
->re_did
&& vendor
== t
->re_vid
&&
837 t
->re_basetype
== hwrev
) {
838 device_set_desc(dev
, t
->re_name
);
846 * This routine takes the segment list provided as the result of
847 * a bus_dma_map_load() operation and assigns the addresses/lengths
848 * to RealTek DMA descriptors. This can be called either by the RX
849 * code or the TX code. In the RX case, we'll probably wind up mapping
850 * at most one segment. For the TX case, there could be any number of
851 * segments since TX packets may span multiple mbufs. In either case,
852 * if the number of segments is larger than the re_maxsegs limit
853 * specified by the caller, we abort the mapping operation. Sadly,
854 * whoever designed the buffer mapping API did not provide a way to
855 * return an error from here, so we have to fake it a bit.
859 re_dma_map_desc(void *arg
, bus_dma_segment_t
*segs
, int nseg
,
860 bus_size_t mapsize
, int error
)
862 struct re_dmaload_arg
*ctx
;
863 struct re_desc
*d
= NULL
;
872 /* Signal error to caller if there's too many segments */
873 if (nseg
> ctx
->re_maxsegs
) {
879 * Map the segment array into descriptors. Note that we set the
880 * start-of-frame and end-of-frame markers for either TX or RX, but
881 * they really only have meaning in the TX case. (In the RX case,
882 * it's the chip that tells us where packets begin and end.)
883 * We also keep track of the end of the ring and set the
884 * end-of-ring bits as needed, and we set the ownership bits
885 * in all except the very first descriptor. (The caller will
886 * set this descriptor later when it start transmission or
891 d
= &ctx
->re_ring
[idx
];
892 if (le32toh(d
->re_cmdstat
) & RE_RDESC_STAT_OWN
) {
896 cmdstat
= segs
[i
].ds_len
;
897 d
->re_bufaddr_lo
= htole32(RE_ADDR_LO(segs
[i
].ds_addr
));
898 d
->re_bufaddr_hi
= htole32(RE_ADDR_HI(segs
[i
].ds_addr
));
900 cmdstat
|= RE_TDESC_CMD_SOF
;
902 cmdstat
|= RE_TDESC_CMD_OWN
;
903 if (idx
== (RE_RX_DESC_CNT
- 1))
904 cmdstat
|= RE_TDESC_CMD_EOR
;
905 d
->re_cmdstat
= htole32(cmdstat
| ctx
->re_flags
);
912 d
->re_cmdstat
|= htole32(RE_TDESC_CMD_EOF
);
913 ctx
->re_maxsegs
= nseg
;
918 * Map a single buffer address.
922 re_dma_map_addr(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
929 KASSERT(nseg
== 1, ("too many DMA segments, %d should be 1", nseg
));
931 *addr
= segs
->ds_addr
;
935 re_allocmem(device_t dev
, struct re_softc
*sc
)
940 * Allocate map for RX mbufs.
943 error
= bus_dma_tag_create(sc
->re_parent_tag
, ETHER_ALIGN
, 0,
944 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
, NULL
,
945 NULL
, MCLBYTES
* nseg
, nseg
, MCLBYTES
, BUS_DMA_ALLOCNOW
,
946 &sc
->re_ldata
.re_mtag
);
948 device_printf(dev
, "could not allocate dma tag\n");
953 * Allocate map for TX descriptor list.
955 error
= bus_dma_tag_create(sc
->re_parent_tag
, RE_RING_ALIGN
,
956 0, BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
, NULL
,
957 NULL
, RE_TX_LIST_SZ
, 1, RE_TX_LIST_SZ
, BUS_DMA_ALLOCNOW
,
958 &sc
->re_ldata
.re_tx_list_tag
);
960 device_printf(dev
, "could not allocate dma tag\n");
964 /* Allocate DMA'able memory for the TX ring */
966 error
= bus_dmamem_alloc(sc
->re_ldata
.re_tx_list_tag
,
967 (void **)&sc
->re_ldata
.re_tx_list
, BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
968 &sc
->re_ldata
.re_tx_list_map
);
970 device_printf(dev
, "could not allocate TX ring\n");
974 /* Load the map for the TX ring. */
976 error
= bus_dmamap_load(sc
->re_ldata
.re_tx_list_tag
,
977 sc
->re_ldata
.re_tx_list_map
, sc
->re_ldata
.re_tx_list
,
978 RE_TX_LIST_SZ
, re_dma_map_addr
,
979 &sc
->re_ldata
.re_tx_list_addr
, BUS_DMA_NOWAIT
);
981 device_printf(dev
, "could not get addres of TX ring\n");
985 /* Create DMA maps for TX buffers */
987 for (i
= 0; i
< RE_TX_DESC_CNT
; i
++) {
988 error
= bus_dmamap_create(sc
->re_ldata
.re_mtag
, 0,
989 &sc
->re_ldata
.re_tx_dmamap
[i
]);
991 device_printf(dev
, "can't create DMA map for TX\n");
997 * Allocate map for RX descriptor list.
999 error
= bus_dma_tag_create(sc
->re_parent_tag
, RE_RING_ALIGN
,
1000 0, BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
, NULL
,
1001 NULL
, RE_RX_LIST_SZ
, 1, RE_RX_LIST_SZ
, BUS_DMA_ALLOCNOW
,
1002 &sc
->re_ldata
.re_rx_list_tag
);
1004 device_printf(dev
, "could not allocate dma tag\n");
1008 /* Allocate DMA'able memory for the RX ring */
1010 error
= bus_dmamem_alloc(sc
->re_ldata
.re_rx_list_tag
,
1011 (void **)&sc
->re_ldata
.re_rx_list
, BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
1012 &sc
->re_ldata
.re_rx_list_map
);
1014 device_printf(dev
, "could not allocate RX ring\n");
1018 /* Load the map for the RX ring. */
1020 error
= bus_dmamap_load(sc
->re_ldata
.re_rx_list_tag
,
1021 sc
->re_ldata
.re_rx_list_map
, sc
->re_ldata
.re_rx_list
,
1022 RE_RX_LIST_SZ
, re_dma_map_addr
,
1023 &sc
->re_ldata
.re_rx_list_addr
, BUS_DMA_NOWAIT
);
1025 device_printf(dev
, "could not get address of RX ring\n");
1029 /* Create DMA maps for RX buffers */
1031 for (i
= 0; i
< RE_RX_DESC_CNT
; i
++) {
1032 error
= bus_dmamap_create(sc
->re_ldata
.re_mtag
, 0,
1033 &sc
->re_ldata
.re_rx_dmamap
[i
]);
1035 device_printf(dev
, "can't create DMA map for RX\n");
1044 * Attach the interface. Allocate softc structures, do ifmedia
1045 * setup and ethernet/BPF attach.
1048 re_attach(device_t dev
)
1050 struct re_softc
*sc
= device_get_softc(dev
);
1052 const struct re_hwrev
*hw_rev
;
1053 uint8_t eaddr
[ETHER_ADDR_LEN
];
1054 uint16_t as
[ETHER_ADDR_LEN
/ 2];
1055 uint16_t re_did
= 0;
1057 int error
= 0, rid
, i
;
1059 callout_init(&sc
->re_timer
);
1064 RE_ENABLE_TX_MODERATION(sc
);
1066 sysctl_ctx_init(&sc
->re_sysctl_ctx
);
1067 sc
->re_sysctl_tree
= SYSCTL_ADD_NODE(&sc
->re_sysctl_ctx
,
1068 SYSCTL_STATIC_CHILDREN(_hw
),
1070 device_get_nameunit(dev
),
1072 if (sc
->re_sysctl_tree
== NULL
) {
1073 device_printf(dev
, "can't add sysctl node\n");
1077 SYSCTL_ADD_PROC(&sc
->re_sysctl_ctx
,
1078 SYSCTL_CHILDREN(sc
->re_sysctl_tree
),
1079 OID_AUTO
, "tx_moderation",
1080 CTLTYPE_INT
| CTLFLAG_RW
,
1081 sc
, 0, re_sysctl_tx_moderation
, "I",
1082 "Enable/Disable TX moderation");
1084 #ifndef BURN_BRIDGES
1086 * Handle power management nonsense.
1089 if (pci_get_powerstate(dev
) != PCI_POWERSTATE_D0
) {
1090 uint32_t membase
, irq
;
1092 /* Save important PCI config data. */
1093 membase
= pci_read_config(dev
, RE_PCI_LOMEM
, 4);
1094 irq
= pci_read_config(dev
, PCIR_INTLINE
, 4);
1096 /* Reset the power state. */
1097 device_printf(dev
, "chip is in D%d power mode "
1098 "-- setting to D0\n", pci_get_powerstate(dev
));
1100 pci_set_powerstate(dev
, PCI_POWERSTATE_D0
);
1102 /* Restore PCI config data. */
1103 pci_write_config(dev
, RE_PCI_LOMEM
, membase
, 4);
1104 pci_write_config(dev
, PCIR_INTLINE
, irq
, 4);
1108 * Map control/status registers.
1110 pci_enable_busmaster(dev
);
1113 sc
->re_res
= bus_alloc_resource_any(dev
, SYS_RES_IOPORT
, &rid
,
1116 if (sc
->re_res
== NULL
) {
1117 device_printf(dev
, "couldn't map ports\n");
1122 sc
->re_btag
= rman_get_bustag(sc
->re_res
);
1123 sc
->re_bhandle
= rman_get_bushandle(sc
->re_res
);
1125 /* Allocate interrupt */
1127 sc
->re_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
1128 RF_SHAREABLE
| RF_ACTIVE
);
1130 if (sc
->re_irq
== NULL
) {
1131 device_printf(dev
, "couldn't map interrupt\n");
1136 /* Reset the adapter. */
1139 hwrev
= CSR_READ_4(sc
, RE_TXCFG
) & RE_TXCFG_HWREV
;
1140 for (hw_rev
= re_hwrevs
; hw_rev
->re_desc
!= NULL
; hw_rev
++) {
1141 if (hw_rev
->re_rev
== hwrev
) {
1142 sc
->re_type
= hw_rev
->re_type
;
1143 sc
->re_flags
= hw_rev
->re_flags
;
1149 re_read_eeprom(sc
, (caddr_t
)&re_did
, 0, 1);
1150 if (re_did
!= 0x8129)
1154 * Get station address from the EEPROM.
1156 re_read_eeprom(sc
, (caddr_t
)as
, RE_EE_EADDR
, 3);
1157 for (i
= 0; i
< ETHER_ADDR_LEN
/ 2; i
++)
1158 as
[i
] = le16toh(as
[i
]);
1159 bcopy(as
, eaddr
, sizeof(eaddr
));
1161 if (sc
->re_type
== RE_8169
) {
1162 /* Set RX length mask */
1163 sc
->re_rxlenmask
= RE_RDESC_STAT_GFRAGLEN
;
1164 sc
->re_txstart
= RE_GTXSTART
;
1166 /* Set RX length mask */
1167 sc
->re_rxlenmask
= RE_RDESC_STAT_FRAGLEN
;
1168 sc
->re_txstart
= RE_TXSTART
;
1172 * Allocate the parent bus DMA tag appropriate for PCI.
1174 #define RE_NSEG_NEW 32
1175 error
= bus_dma_tag_create(NULL
, /* parent */
1176 1, 0, /* alignment, boundary */
1177 BUS_SPACE_MAXADDR_32BIT
,/* lowaddr */
1178 BUS_SPACE_MAXADDR
, /* highaddr */
1179 NULL
, NULL
, /* filter, filterarg */
1180 MAXBSIZE
, RE_NSEG_NEW
, /* maxsize, nsegments */
1181 BUS_SPACE_MAXSIZE_32BIT
,/* maxsegsize */
1182 BUS_DMA_ALLOCNOW
, /* flags */
1183 &sc
->re_parent_tag
);
1187 error
= re_allocmem(dev
, sc
);
1193 if (mii_phy_probe(dev
, &sc
->re_miibus
,
1194 re_ifmedia_upd
, re_ifmedia_sts
)) {
1195 device_printf(dev
, "MII without any phy!\n");
1200 ifp
= &sc
->arpcom
.ac_if
;
1202 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
1203 ifp
->if_mtu
= ETHERMTU
;
1204 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1205 ifp
->if_ioctl
= re_ioctl
;
1206 ifp
->if_capabilities
= IFCAP_VLAN_MTU
;
1207 ifp
->if_start
= re_start
;
1208 ifp
->if_capabilities
|= IFCAP_HWCSUM
|IFCAP_VLAN_HWTAGGING
;
1209 #ifdef DEVICE_POLLING
1210 ifp
->if_poll
= re_poll
;
1212 ifp
->if_watchdog
= re_watchdog
;
1213 ifp
->if_init
= re_init
;
1214 if (sc
->re_type
== RE_8169
)
1215 ifp
->if_baudrate
= 1000000000;
1217 ifp
->if_baudrate
= 100000000;
1218 ifq_set_maxlen(&ifp
->if_snd
, RE_IFQ_MAXLEN
);
1219 ifq_set_ready(&ifp
->if_snd
);
1221 #ifdef RE_DISABLE_HWCSUM
1222 ifp
->if_capenable
= ifp
->if_capabilities
& ~IFCAP_HWCSUM
;
1223 ifp
->if_hwassist
= 0;
1225 ifp
->if_capenable
= ifp
->if_capabilities
;
1226 ifp
->if_hwassist
= RE_CSUM_FEATURES
;
1227 #endif /* RE_DISABLE_HWCSUM */
1230 * Call MI attach routine.
1232 ether_ifattach(ifp
, eaddr
, NULL
);
1236 * Perform hardware diagnostic on the original RTL8169.
1237 * Some 32-bit cards were incorrectly wired and would
1238 * malfunction if plugged into a 64-bit slot.
1240 if (hwrev
== RE_HWREV_8169
) {
1241 lwkt_serialize_enter(ifp
->if_serializer
);
1242 error
= re_diag(sc
);
1243 lwkt_serialize_exit(ifp
->if_serializer
);
1246 device_printf(dev
, "hardware diagnostic failure\n");
1247 ether_ifdetach(ifp
);
1251 #endif /* RE_DIAG */
1253 /* Hook interrupt last to avoid having to lock softc */
1254 error
= bus_setup_intr(dev
, sc
->re_irq
, INTR_NETSAFE
, re_intr
, sc
,
1255 &sc
->re_intrhand
, ifp
->if_serializer
);
1258 device_printf(dev
, "couldn't set up irq\n");
1259 ether_ifdetach(ifp
);
1271 * Shutdown hardware and free up resources. This can be called any
1272 * time after the mutex has been initialized. It is called in both
1273 * the error case in attach and the normal detach case so it needs
1274 * to be careful about only freeing resources that have actually been
1278 re_detach(device_t dev
)
1280 struct re_softc
*sc
= device_get_softc(dev
);
1281 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1284 /* These should only be active if attach succeeded */
1285 if (device_is_attached(dev
)) {
1286 lwkt_serialize_enter(ifp
->if_serializer
);
1288 bus_teardown_intr(dev
, sc
->re_irq
, sc
->re_intrhand
);
1289 lwkt_serialize_exit(ifp
->if_serializer
);
1291 ether_ifdetach(ifp
);
1294 device_delete_child(dev
, sc
->re_miibus
);
1295 bus_generic_detach(dev
);
1298 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->re_irq
);
1300 bus_release_resource(dev
, SYS_RES_IOPORT
, RE_PCI_LOIO
,
1304 /* Unload and free the RX DMA ring memory and map */
1306 if (sc
->re_ldata
.re_rx_list_tag
) {
1307 bus_dmamap_unload(sc
->re_ldata
.re_rx_list_tag
,
1308 sc
->re_ldata
.re_rx_list_map
);
1309 bus_dmamem_free(sc
->re_ldata
.re_rx_list_tag
,
1310 sc
->re_ldata
.re_rx_list
,
1311 sc
->re_ldata
.re_rx_list_map
);
1312 bus_dma_tag_destroy(sc
->re_ldata
.re_rx_list_tag
);
1315 /* Unload and free the TX DMA ring memory and map */
1317 if (sc
->re_ldata
.re_tx_list_tag
) {
1318 bus_dmamap_unload(sc
->re_ldata
.re_tx_list_tag
,
1319 sc
->re_ldata
.re_tx_list_map
);
1320 bus_dmamem_free(sc
->re_ldata
.re_tx_list_tag
,
1321 sc
->re_ldata
.re_tx_list
,
1322 sc
->re_ldata
.re_tx_list_map
);
1323 bus_dma_tag_destroy(sc
->re_ldata
.re_tx_list_tag
);
1326 /* Destroy all the RX and TX buffer maps */
1328 if (sc
->re_ldata
.re_mtag
) {
1329 for (i
= 0; i
< RE_TX_DESC_CNT
; i
++)
1330 bus_dmamap_destroy(sc
->re_ldata
.re_mtag
,
1331 sc
->re_ldata
.re_tx_dmamap
[i
]);
1332 for (i
= 0; i
< RE_RX_DESC_CNT
; i
++)
1333 bus_dmamap_destroy(sc
->re_ldata
.re_mtag
,
1334 sc
->re_ldata
.re_rx_dmamap
[i
]);
1335 bus_dma_tag_destroy(sc
->re_ldata
.re_mtag
);
1338 /* Unload and free the stats buffer and map */
1340 if (sc
->re_ldata
.re_stag
) {
1341 bus_dmamap_unload(sc
->re_ldata
.re_stag
,
1342 sc
->re_ldata
.re_rx_list_map
);
1343 bus_dmamem_free(sc
->re_ldata
.re_stag
,
1344 sc
->re_ldata
.re_stats
,
1345 sc
->re_ldata
.re_smap
);
1346 bus_dma_tag_destroy(sc
->re_ldata
.re_stag
);
1349 if (sc
->re_parent_tag
)
1350 bus_dma_tag_destroy(sc
->re_parent_tag
);
1356 re_newbuf(struct re_softc
*sc
, int idx
, struct mbuf
*m
)
1358 struct re_dmaload_arg arg
;
1359 struct mbuf
*n
= NULL
;
1363 n
= m_getcl(MB_DONTWAIT
, MT_DATA
, M_PKTHDR
);
1368 m
->m_data
= m
->m_ext
.ext_buf
;
1370 m
->m_len
= m
->m_pkthdr
.len
= MCLBYTES
;
1374 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1375 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1382 arg
.re_ring
= sc
->re_ldata
.re_rx_list
;
1384 error
= bus_dmamap_load_mbuf(sc
->re_ldata
.re_mtag
,
1385 sc
->re_ldata
.re_rx_dmamap
[idx
], m
, re_dma_map_desc
,
1386 &arg
, BUS_DMA_NOWAIT
);
1387 if (error
|| arg
.re_maxsegs
!= 1) {
1393 sc
->re_ldata
.re_rx_list
[idx
].re_cmdstat
|= htole32(RE_RDESC_CMD_OWN
);
1394 sc
->re_ldata
.re_rx_mbuf
[idx
] = m
;
1396 bus_dmamap_sync(sc
->re_ldata
.re_mtag
, sc
->re_ldata
.re_rx_dmamap
[idx
],
1397 BUS_DMASYNC_PREREAD
);
1403 re_tx_list_init(struct re_softc
*sc
)
1405 bzero(sc
->re_ldata
.re_tx_list
, RE_TX_LIST_SZ
);
1406 bzero(&sc
->re_ldata
.re_tx_mbuf
, RE_TX_DESC_CNT
* sizeof(struct mbuf
*));
1408 bus_dmamap_sync(sc
->re_ldata
.re_tx_list_tag
,
1409 sc
->re_ldata
.re_tx_list_map
, BUS_DMASYNC_PREWRITE
);
1410 sc
->re_ldata
.re_tx_prodidx
= 0;
1411 sc
->re_ldata
.re_tx_considx
= 0;
1412 sc
->re_ldata
.re_tx_free
= RE_TX_DESC_CNT
;
1418 re_rx_list_init(struct re_softc
*sc
)
1422 bzero(sc
->re_ldata
.re_rx_list
, RE_RX_LIST_SZ
);
1423 bzero(&sc
->re_ldata
.re_rx_mbuf
, RE_RX_DESC_CNT
* sizeof(struct mbuf
*));
1425 for (i
= 0; i
< RE_RX_DESC_CNT
; i
++) {
1426 error
= re_newbuf(sc
, i
, NULL
);
1431 /* Flush the RX descriptors */
1433 bus_dmamap_sync(sc
->re_ldata
.re_rx_list_tag
,
1434 sc
->re_ldata
.re_rx_list_map
, BUS_DMASYNC_PREWRITE
);
1436 sc
->re_ldata
.re_rx_prodidx
= 0;
1437 sc
->re_head
= sc
->re_tail
= NULL
;
1443 * RX handler for C+ and 8169. For the gigE chips, we support
1444 * the reception of jumbo frames that have been fragmented
1445 * across multiple 2K mbuf cluster buffers.
1448 re_rxeof(struct re_softc
*sc
)
1450 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1452 struct re_desc
*cur_rx
;
1453 uint32_t rxstat
, rxvlan
;
1456 /* Invalidate the descriptor memory */
1458 bus_dmamap_sync(sc
->re_ldata
.re_rx_list_tag
,
1459 sc
->re_ldata
.re_rx_list_map
, BUS_DMASYNC_POSTREAD
);
1461 for (i
= sc
->re_ldata
.re_rx_prodidx
;
1462 RE_OWN(&sc
->re_ldata
.re_rx_list
[i
]) == 0 ; RE_DESC_INC(i
)) {
1463 cur_rx
= &sc
->re_ldata
.re_rx_list
[i
];
1464 m
= sc
->re_ldata
.re_rx_mbuf
[i
];
1465 total_len
= RE_RXBYTES(cur_rx
);
1466 rxstat
= le32toh(cur_rx
->re_cmdstat
);
1467 rxvlan
= le32toh(cur_rx
->re_vlanctl
);
1469 /* Invalidate the RX mbuf and unload its map */
1471 bus_dmamap_sync(sc
->re_ldata
.re_mtag
,
1472 sc
->re_ldata
.re_rx_dmamap
[i
],
1473 BUS_DMASYNC_POSTWRITE
);
1474 bus_dmamap_unload(sc
->re_ldata
.re_mtag
,
1475 sc
->re_ldata
.re_rx_dmamap
[i
]);
1477 if ((rxstat
& RE_RDESC_STAT_EOF
) == 0) {
1478 m
->m_len
= MCLBYTES
- ETHER_ALIGN
;
1479 if (sc
->re_head
== NULL
) {
1480 sc
->re_head
= sc
->re_tail
= m
;
1482 sc
->re_tail
->m_next
= m
;
1485 re_newbuf(sc
, i
, NULL
);
1490 * NOTE: for the 8139C+, the frame length field
1491 * is always 12 bits in size, but for the gigE chips,
1492 * it is 13 bits (since the max RX frame length is 16K).
1493 * Unfortunately, all 32 bits in the status word
1494 * were already used, so to make room for the extra
1495 * length bit, RealTek took out the 'frame alignment
1496 * error' bit and shifted the other status bits
1497 * over one slot. The OWN, EOR, FS and LS bits are
1498 * still in the same places. We have already extracted
1499 * the frame length and checked the OWN bit, so rather
1500 * than using an alternate bit mapping, we shift the
1501 * status bits one space to the right so we can evaluate
1502 * them using the 8169 status as though it was in the
1503 * same format as that of the 8139C+.
1505 if (sc
->re_type
== RE_8169
)
1508 if (rxstat
& RE_RDESC_STAT_RXERRSUM
) {
1511 * If this is part of a multi-fragment packet,
1512 * discard all the pieces.
1514 if (sc
->re_head
!= NULL
) {
1515 m_freem(sc
->re_head
);
1516 sc
->re_head
= sc
->re_tail
= NULL
;
1518 re_newbuf(sc
, i
, m
);
1523 * If allocating a replacement mbuf fails,
1524 * reload the current one.
1527 if (re_newbuf(sc
, i
, NULL
)) {
1529 if (sc
->re_head
!= NULL
) {
1530 m_freem(sc
->re_head
);
1531 sc
->re_head
= sc
->re_tail
= NULL
;
1533 re_newbuf(sc
, i
, m
);
1537 if (sc
->re_head
!= NULL
) {
1538 m
->m_len
= total_len
% (MCLBYTES
- ETHER_ALIGN
);
1540 * Special case: if there's 4 bytes or less
1541 * in this buffer, the mbuf can be discarded:
1542 * the last 4 bytes is the CRC, which we don't
1543 * care about anyway.
1545 if (m
->m_len
<= ETHER_CRC_LEN
) {
1546 sc
->re_tail
->m_len
-=
1547 (ETHER_CRC_LEN
- m
->m_len
);
1550 m
->m_len
-= ETHER_CRC_LEN
;
1551 sc
->re_tail
->m_next
= m
;
1554 sc
->re_head
= sc
->re_tail
= NULL
;
1555 m
->m_pkthdr
.len
= total_len
- ETHER_CRC_LEN
;
1557 m
->m_pkthdr
.len
= m
->m_len
=
1558 (total_len
- ETHER_CRC_LEN
);
1561 m
->m_pkthdr
.rcvif
= ifp
;
1563 /* Do RX checksumming if enabled */
1565 if (ifp
->if_capenable
& IFCAP_RXCSUM
) {
1567 /* Check IP header checksum */
1568 if (rxstat
& RE_RDESC_STAT_PROTOID
)
1569 m
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
;
1570 if ((rxstat
& RE_RDESC_STAT_IPSUMBAD
) == 0)
1571 m
->m_pkthdr
.csum_flags
|= CSUM_IP_VALID
;
1573 /* Check TCP/UDP checksum */
1574 if ((RE_TCPPKT(rxstat
) &&
1575 (rxstat
& RE_RDESC_STAT_TCPSUMBAD
) == 0) ||
1576 (RE_UDPPKT(rxstat
) &&
1577 (rxstat
& RE_RDESC_STAT_UDPSUMBAD
)) == 0) {
1578 m
->m_pkthdr
.csum_flags
|=
1579 CSUM_DATA_VALID
|CSUM_PSEUDO_HDR
;
1580 m
->m_pkthdr
.csum_data
= 0xffff;
1584 if (rxvlan
& RE_RDESC_VLANCTL_TAG
) {
1586 be16toh((rxvlan
& RE_RDESC_VLANCTL_DATA
)));
1588 ifp
->if_input(ifp
, m
);
1592 /* Flush the RX DMA ring */
1594 bus_dmamap_sync(sc
->re_ldata
.re_rx_list_tag
,
1595 sc
->re_ldata
.re_rx_list_map
, BUS_DMASYNC_PREWRITE
);
1597 sc
->re_ldata
.re_rx_prodidx
= i
;
1601 re_txeof(struct re_softc
*sc
)
1603 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1607 /* Invalidate the TX descriptor list */
1609 bus_dmamap_sync(sc
->re_ldata
.re_tx_list_tag
,
1610 sc
->re_ldata
.re_tx_list_map
, BUS_DMASYNC_POSTREAD
);
1612 for (idx
= sc
->re_ldata
.re_tx_considx
;
1613 sc
->re_ldata
.re_tx_free
< RE_TX_DESC_CNT
; RE_DESC_INC(idx
)) {
1614 txstat
= le32toh(sc
->re_ldata
.re_tx_list
[idx
].re_cmdstat
);
1615 if (txstat
& RE_TDESC_CMD_OWN
)
1618 sc
->re_ldata
.re_tx_list
[idx
].re_bufaddr_lo
= 0;
1621 * We only stash mbufs in the last descriptor
1622 * in a fragment chain, which also happens to
1623 * be the only place where the TX status bits
1626 if (txstat
& RE_TDESC_CMD_EOF
) {
1627 m_freem(sc
->re_ldata
.re_tx_mbuf
[idx
]);
1628 sc
->re_ldata
.re_tx_mbuf
[idx
] = NULL
;
1629 bus_dmamap_unload(sc
->re_ldata
.re_mtag
,
1630 sc
->re_ldata
.re_tx_dmamap
[idx
]);
1631 if (txstat
& (RE_TDESC_STAT_EXCESSCOL
|
1632 RE_TDESC_STAT_COLCNT
))
1633 ifp
->if_collisions
++;
1634 if (txstat
& RE_TDESC_STAT_TXERRSUM
)
1639 sc
->re_ldata
.re_tx_free
++;
1642 /* No changes made to the TX ring, so no flush needed */
1643 if (sc
->re_ldata
.re_tx_free
) {
1644 sc
->re_ldata
.re_tx_considx
= idx
;
1645 ifp
->if_flags
&= ~IFF_OACTIVE
;
1650 * Some chips will ignore a second TX request issued while an
1651 * existing transmission is in progress. If the transmitter goes
1652 * idle but there are still packets waiting to be sent, we need
1653 * to restart the channel here to flush them out. This only seems
1654 * to be required with the PCIe devices.
1656 if (sc
->re_ldata
.re_tx_free
< RE_TX_DESC_CNT
)
1657 CSR_WRITE_1(sc
, sc
->re_txstart
, RE_TXSTART_START
);
1660 * If not all descriptors have been released reaped yet,
1661 * reload the timer so that we will eventually get another
1662 * interrupt that will cause us to re-enter this routine.
1663 * This is done in case the transmitter has gone idle.
1665 if (RE_TX_MODERATION_IS_ENABLED(sc
) &&
1666 sc
->re_ldata
.re_tx_free
< RE_TX_DESC_CNT
)
1667 CSR_WRITE_4(sc
, RE_TIMERCNT
, 1);
1673 struct re_softc
*sc
= xsc
;
1675 lwkt_serialize_enter(sc
->arpcom
.ac_if
.if_serializer
);
1676 re_tick_serialized(xsc
);
1677 lwkt_serialize_exit(sc
->arpcom
.ac_if
.if_serializer
);
1681 re_tick_serialized(void *xsc
)
1683 struct re_softc
*sc
= xsc
;
1684 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1685 struct mii_data
*mii
;
1687 mii
= device_get_softc(sc
->re_miibus
);
1690 if (!(mii
->mii_media_status
& IFM_ACTIVE
))
1693 if (mii
->mii_media_status
& IFM_ACTIVE
&&
1694 IFM_SUBTYPE(mii
->mii_media_active
) != IFM_NONE
) {
1696 if (!ifq_is_empty(&ifp
->if_snd
))
1701 callout_reset(&sc
->re_timer
, hz
, re_tick
, sc
);
1704 #ifdef DEVICE_POLLING
1707 re_poll(struct ifnet
*ifp
, enum poll_cmd cmd
, int count
)
1709 struct re_softc
*sc
= ifp
->if_softc
;
1713 /* disable interrupts */
1714 CSR_WRITE_2(sc
, RE_IMR
, 0x0000);
1716 case POLL_DEREGISTER
:
1717 /* enable interrupts */
1718 CSR_WRITE_2(sc
, RE_IMR
, sc
->re_intrs
);
1721 sc
->rxcycles
= count
;
1725 if (!ifq_is_empty(&ifp
->if_snd
))
1726 (*ifp
->if_start
)(ifp
);
1728 if (cmd
== POLL_AND_CHECK_STATUS
) { /* also check status register */
1731 status
= CSR_READ_2(sc
, RE_ISR
);
1732 if (status
== 0xffff)
1735 CSR_WRITE_2(sc
, RE_ISR
, status
);
1738 * XXX check behaviour on receiver stalls.
1741 if (status
& RE_ISR_SYSTEM_ERR
) {
1749 #endif /* DEVICE_POLLING */
1754 struct re_softc
*sc
= arg
;
1755 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1758 if (sc
->suspended
|| (ifp
->if_flags
& IFF_UP
) == 0)
1762 status
= CSR_READ_2(sc
, RE_ISR
);
1763 /* If the card has gone away the read returns 0xffff. */
1764 if (status
== 0xffff)
1767 CSR_WRITE_2(sc
, RE_ISR
, status
);
1769 if ((status
& sc
->re_intrs
) == 0)
1772 if (status
& (RE_ISR_RX_OK
| RE_ISR_RX_ERR
| RE_ISR_FIFO_OFLOW
))
1775 if ((status
& sc
->re_tx_ack
) ||
1776 (status
& RE_ISR_TX_ERR
) ||
1777 (status
& RE_ISR_TX_DESC_UNAVAIL
))
1780 if (status
& RE_ISR_SYSTEM_ERR
) {
1785 if (status
& RE_ISR_LINKCHG
) {
1786 callout_stop(&sc
->re_timer
);
1787 re_tick_serialized(sc
);
1791 if (!ifq_is_empty(&ifp
->if_snd
))
1792 (*ifp
->if_start
)(ifp
);
1796 re_encap(struct re_softc
*sc
, struct mbuf
**m_head
, int *idx
, int *called_defrag
)
1798 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1799 struct mbuf
*m
, *m_new
= NULL
;
1800 struct re_dmaload_arg arg
;
1805 if (sc
->re_ldata
.re_tx_free
<= 4)
1811 * Set up checksum offload. Note: checksum offload bits must
1812 * appear in all descriptors of a multi-descriptor transmit
1813 * attempt. (This is according to testing done with an 8169
1814 * chip. I'm not sure if this is a requirement or a bug.)
1819 if (m
->m_pkthdr
.csum_flags
& CSUM_IP
)
1820 arg
.re_flags
|= RE_TDESC_CMD_IPCSUM
;
1821 if (m
->m_pkthdr
.csum_flags
& CSUM_TCP
)
1822 arg
.re_flags
|= RE_TDESC_CMD_TCPCSUM
;
1823 if (m
->m_pkthdr
.csum_flags
& CSUM_UDP
)
1824 arg
.re_flags
|= RE_TDESC_CMD_UDPCSUM
;
1828 arg
.re_maxsegs
= sc
->re_ldata
.re_tx_free
;
1829 if (arg
.re_maxsegs
> 4)
1830 arg
.re_maxsegs
-= 4;
1831 arg
.re_ring
= sc
->re_ldata
.re_tx_list
;
1833 map
= sc
->re_ldata
.re_tx_dmamap
[*idx
];
1836 * With some of the RealTek chips, using the checksum offload
1837 * support in conjunction with the autopadding feature results
1838 * in the transmission of corrupt frames. For example, if we
1839 * need to send a really small IP fragment that's less than 60
1840 * bytes in size, and IP header checksumming is enabled, the
1841 * resulting ethernet frame that appears on the wire will
1842 * have garbled payload. To work around this, if TX checksum
1843 * offload is enabled, we always manually pad short frames out
1844 * to the minimum ethernet frame size. We do this by pretending
1845 * the mbuf chain has too many fragments so the coalescing code
1846 * below can assemble the packet into a single buffer that's
1847 * padded out to the mininum frame size.
1849 * Note: this appears unnecessary for TCP, and doing it for TCP
1850 * with PCIe adapters seems to result in bad checksums.
1852 if (arg
.re_flags
&& !(arg
.re_flags
& RE_TDESC_CMD_TCPCSUM
) &&
1853 m
->m_pkthdr
.len
< RE_MIN_FRAMELEN
) {
1856 error
= bus_dmamap_load_mbuf(sc
->re_ldata
.re_mtag
, map
,
1857 m
, re_dma_map_desc
, &arg
, BUS_DMA_NOWAIT
);
1860 if (error
&& error
!= EFBIG
) {
1861 if_printf(ifp
, "can't map mbuf (error %d)\n", error
);
1865 /* Too many segments to map, coalesce into a single mbuf */
1867 if (error
|| arg
.re_maxsegs
== 0) {
1868 m_new
= m_defrag_nofree(m
, MB_DONTWAIT
);
1869 if (m_new
== NULL
) {
1877 * Manually pad short frames, and zero the pad space
1878 * to avoid leaking data.
1880 if (m_new
->m_pkthdr
.len
< RE_MIN_FRAMELEN
) {
1881 bzero(mtod(m_new
, char *) + m_new
->m_pkthdr
.len
,
1882 RE_MIN_FRAMELEN
- m_new
->m_pkthdr
.len
);
1883 m_new
->m_pkthdr
.len
+= RE_MIN_FRAMELEN
-
1884 m_new
->m_pkthdr
.len
;
1885 m_new
->m_len
= m_new
->m_pkthdr
.len
;
1891 arg
.re_maxsegs
= sc
->re_ldata
.re_tx_free
;
1892 arg
.re_ring
= sc
->re_ldata
.re_tx_list
;
1894 error
= bus_dmamap_load_mbuf(sc
->re_ldata
.re_mtag
, map
,
1895 m
, re_dma_map_desc
, &arg
, BUS_DMA_NOWAIT
);
1898 if_printf(ifp
, "can't map mbuf (error %d)\n", error
);
1904 * Insure that the map for this transmission
1905 * is placed at the array index of the last descriptor
1908 sc
->re_ldata
.re_tx_dmamap
[*idx
] =
1909 sc
->re_ldata
.re_tx_dmamap
[arg
.re_idx
];
1910 sc
->re_ldata
.re_tx_dmamap
[arg
.re_idx
] = map
;
1912 sc
->re_ldata
.re_tx_mbuf
[arg
.re_idx
] = m
;
1913 sc
->re_ldata
.re_tx_free
-= arg
.re_maxsegs
;
1916 * Set up hardware VLAN tagging. Note: vlan tag info must
1917 * appear in the first descriptor of a multi-descriptor
1918 * transmission attempt.
1921 if ((m
->m_flags
& (M_PROTO1
|M_PKTHDR
)) == (M_PROTO1
|M_PKTHDR
) &&
1922 m
->m_pkthdr
.rcvif
!= NULL
&&
1923 m
->m_pkthdr
.rcvif
->if_type
== IFT_L2VLAN
) {
1925 ifv
= m
->m_pkthdr
.rcvif
->if_softc
;
1927 sc
->re_ldata
.re_tx_list
[*idx
].re_vlanctl
=
1928 htole32(htobe16(ifv
->ifv_tag
) | RE_TDESC_VLANCTL_TAG
);
1931 /* Transfer ownership of packet to the chip. */
1933 sc
->re_ldata
.re_tx_list
[arg
.re_idx
].re_cmdstat
|=
1934 htole32(RE_TDESC_CMD_OWN
);
1935 if (*idx
!= arg
.re_idx
)
1936 sc
->re_ldata
.re_tx_list
[*idx
].re_cmdstat
|=
1937 htole32(RE_TDESC_CMD_OWN
);
1939 RE_DESC_INC(arg
.re_idx
);
1946 * Main transmit routine for C+ and gigE NICs.
1950 re_start(struct ifnet
*ifp
)
1952 struct re_softc
*sc
= ifp
->if_softc
;
1953 struct mbuf
*m_head
;
1954 struct mbuf
*m_head2
;
1955 int called_defrag
, idx
, need_trans
;
1957 if (!sc
->re_link
|| (ifp
->if_flags
& IFF_OACTIVE
))
1960 idx
= sc
->re_ldata
.re_tx_prodidx
;
1963 while (sc
->re_ldata
.re_tx_mbuf
[idx
] == NULL
) {
1964 m_head
= ifq_poll(&ifp
->if_snd
);
1968 if (re_encap(sc
, &m_head2
, &idx
, &called_defrag
)) {
1970 * If we could not encapsulate the defragged packet,
1971 * the returned m_head2 is garbage and we must dequeue
1972 * and throw away the original packet.
1974 if (called_defrag
) {
1975 ifq_dequeue(&ifp
->if_snd
, m_head
);
1978 ifp
->if_flags
|= IFF_OACTIVE
;
1983 * Clean out the packet we encapsulated. If we defragged
1984 * the packet the m_head2 is the one that got encapsulated
1985 * and the original must be thrown away. Otherwise m_head2
1986 * *IS* the original.
1988 ifq_dequeue(&ifp
->if_snd
, m_head
);
1994 * If there's a BPF listener, bounce a copy of this frame
1997 BPF_MTAP(ifp
, m_head2
);
2001 if (RE_TX_MODERATION_IS_ENABLED(sc
) &&
2002 sc
->re_ldata
.re_tx_free
!= RE_TX_DESC_CNT
)
2003 CSR_WRITE_4(sc
, RE_TIMERCNT
, 1);
2007 /* Flush the TX descriptors */
2008 bus_dmamap_sync(sc
->re_ldata
.re_tx_list_tag
,
2009 sc
->re_ldata
.re_tx_list_map
, BUS_DMASYNC_PREWRITE
);
2011 sc
->re_ldata
.re_tx_prodidx
= idx
;
2014 * RealTek put the TX poll request register in a different
2015 * location on the 8169 gigE chip. I don't know why.
2017 CSR_WRITE_1(sc
, sc
->re_txstart
, RE_TXSTART_START
);
2019 if (RE_TX_MODERATION_IS_ENABLED(sc
)) {
2021 * Use the countdown timer for interrupt moderation.
2022 * 'TX done' interrupts are disabled. Instead, we reset the
2023 * countdown timer, which will begin counting until it hits
2024 * the value in the TIMERINT register, and then trigger an
2025 * interrupt. Each time we write to the TIMERCNT register,
2026 * the timer count is reset to 0.
2028 CSR_WRITE_4(sc
, RE_TIMERCNT
, 1);
2032 * Set a timeout in case the chip goes out to lunch.
2040 struct re_softc
*sc
= xsc
;
2041 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2042 struct mii_data
*mii
;
2045 mii
= device_get_softc(sc
->re_miibus
);
2048 * Cancel pending I/O and free all RX/TX buffers.
2053 * Enable C+ RX and TX mode, as well as VLAN stripping and
2054 * RX checksum offload. We must configure the C+ register
2055 * before all others.
2057 CSR_WRITE_2(sc
, RE_CPLUS_CMD
, RE_CPLUSCMD_RXENB
| RE_CPLUSCMD_TXENB
|
2058 RE_CPLUSCMD_PCI_MRW
| RE_CPLUSCMD_VLANSTRIP
|
2059 (ifp
->if_capenable
& IFCAP_RXCSUM
?
2060 RE_CPLUSCMD_RXCSUM_ENB
: 0));
2063 * Init our MAC address. Even though the chipset
2064 * documentation doesn't mention it, we need to enter "Config
2065 * register write enable" mode to modify the ID registers.
2067 CSR_WRITE_1(sc
, RE_EECMD
, RE_EEMODE_WRITECFG
);
2068 CSR_WRITE_4(sc
, RE_IDR0
,
2069 htole32(*(uint32_t *)(&sc
->arpcom
.ac_enaddr
[0])));
2070 CSR_WRITE_2(sc
, RE_IDR4
,
2071 htole16(*(uint16_t *)(&sc
->arpcom
.ac_enaddr
[4])));
2072 CSR_WRITE_1(sc
, RE_EECMD
, RE_EEMODE_OFF
);
2075 * For C+ mode, initialize the RX descriptors and mbufs.
2077 re_rx_list_init(sc
);
2078 re_tx_list_init(sc
);
2081 * Load the addresses of the RX and TX lists into the chip.
2083 CSR_WRITE_4(sc
, RE_RXLIST_ADDR_HI
,
2084 RE_ADDR_HI(sc
->re_ldata
.re_rx_list_addr
));
2085 CSR_WRITE_4(sc
, RE_RXLIST_ADDR_LO
,
2086 RE_ADDR_LO(sc
->re_ldata
.re_rx_list_addr
));
2088 CSR_WRITE_4(sc
, RE_TXLIST_ADDR_HI
,
2089 RE_ADDR_HI(sc
->re_ldata
.re_tx_list_addr
));
2090 CSR_WRITE_4(sc
, RE_TXLIST_ADDR_LO
,
2091 RE_ADDR_LO(sc
->re_ldata
.re_tx_list_addr
));
2094 * Enable transmit and receive.
2096 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_TX_ENB
|RE_CMD_RX_ENB
);
2099 * Set the initial TX and RX configuration.
2101 if (sc
->re_testmode
) {
2102 if (sc
->re_type
== RE_8169
)
2103 CSR_WRITE_4(sc
, RE_TXCFG
,
2104 RE_TXCFG_CONFIG
| RE_LOOPTEST_ON
);
2106 CSR_WRITE_4(sc
, RE_TXCFG
,
2107 RE_TXCFG_CONFIG
| RE_LOOPTEST_ON_CPLUS
);
2109 CSR_WRITE_4(sc
, RE_TXCFG
, RE_TXCFG_CONFIG
);
2111 CSR_WRITE_1(sc
, RE_EARLY_TX_THRESH
, 16);
2113 CSR_WRITE_4(sc
, RE_RXCFG
, RE_RXCFG_CONFIG
);
2115 /* Set the individual bit to receive frames for this host only. */
2116 rxcfg
= CSR_READ_4(sc
, RE_RXCFG
);
2117 rxcfg
|= RE_RXCFG_RX_INDIV
;
2119 /* If we want promiscuous mode, set the allframes bit. */
2120 if (ifp
->if_flags
& IFF_PROMISC
) {
2121 rxcfg
|= RE_RXCFG_RX_ALLPHYS
;
2122 CSR_WRITE_4(sc
, RE_RXCFG
, rxcfg
);
2124 rxcfg
&= ~RE_RXCFG_RX_ALLPHYS
;
2125 CSR_WRITE_4(sc
, RE_RXCFG
, rxcfg
);
2129 * Set capture broadcast bit to capture broadcast frames.
2131 if (ifp
->if_flags
& IFF_BROADCAST
) {
2132 rxcfg
|= RE_RXCFG_RX_BROAD
;
2133 CSR_WRITE_4(sc
, RE_RXCFG
, rxcfg
);
2135 rxcfg
&= ~RE_RXCFG_RX_BROAD
;
2136 CSR_WRITE_4(sc
, RE_RXCFG
, rxcfg
);
2140 * Program the multicast filter, if necessary.
2144 #ifdef DEVICE_POLLING
2146 * Disable interrupts if we are polling.
2148 if (ifp
->if_flags
& IFF_POLLING
)
2149 CSR_WRITE_2(sc
, RE_IMR
, 0);
2150 else /* otherwise ... */
2151 #endif /* DEVICE_POLLING */
2153 * Enable interrupts.
2155 if (sc
->re_testmode
)
2156 CSR_WRITE_2(sc
, RE_IMR
, 0);
2158 CSR_WRITE_2(sc
, RE_IMR
, sc
->re_intrs
);
2159 CSR_WRITE_2(sc
, RE_ISR
, sc
->re_intrs
);
2161 /* Set initial TX threshold */
2162 sc
->re_txthresh
= RE_TX_THRESH_INIT
;
2164 /* Start RX/TX process. */
2165 if (sc
->re_flags
& RE_F_HASMPC
)
2166 CSR_WRITE_4(sc
, RE_MISSEDPKT
, 0);
2168 /* Enable receiver and transmitter. */
2169 CSR_WRITE_1(sc
, RE_COMMAND
, RE_CMD_TX_ENB
|RE_CMD_RX_ENB
);
2172 if (RE_TX_MODERATION_IS_ENABLED(sc
)) {
2174 * Initialize the timer interrupt register so that
2175 * a timer interrupt will be generated once the timer
2176 * reaches a certain number of ticks. The timer is
2177 * reloaded on each transmit. This gives us TX interrupt
2178 * moderation, which dramatically improves TX frame rate.
2180 if (sc
->re_type
== RE_8169
)
2181 CSR_WRITE_4(sc
, RE_TIMERINT_8169
, 0x800);
2183 CSR_WRITE_4(sc
, RE_TIMERINT
, 0x400);
2187 * For 8169 gigE NICs, set the max allowed RX packet
2188 * size so we can receive jumbo frames.
2190 if (sc
->re_type
== RE_8169
)
2191 CSR_WRITE_2(sc
, RE_MAXRXPKTLEN
, 16383);
2193 if (sc
->re_testmode
) {
2199 CSR_WRITE_1(sc
, RE_CFG1
, RE_CFG1_DRVLOAD
|RE_CFG1_FULLDUPLEX
);
2201 ifp
->if_flags
|= IFF_RUNNING
;
2202 ifp
->if_flags
&= ~IFF_OACTIVE
;
2205 callout_reset(&sc
->re_timer
, hz
, re_tick
, sc
);
2209 * Set media options.
2212 re_ifmedia_upd(struct ifnet
*ifp
)
2214 struct re_softc
*sc
= ifp
->if_softc
;
2215 struct mii_data
*mii
;
2217 mii
= device_get_softc(sc
->re_miibus
);
2224 * Report current media status.
2227 re_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
2229 struct re_softc
*sc
= ifp
->if_softc
;
2230 struct mii_data
*mii
;
2232 mii
= device_get_softc(sc
->re_miibus
);
2235 ifmr
->ifm_active
= mii
->mii_media_active
;
2236 ifmr
->ifm_status
= mii
->mii_media_status
;
2240 re_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
2242 struct re_softc
*sc
= ifp
->if_softc
;
2243 struct ifreq
*ifr
= (struct ifreq
*) data
;
2244 struct mii_data
*mii
;
2249 if (ifr
->ifr_mtu
> RE_JUMBO_MTU
)
2251 ifp
->if_mtu
= ifr
->ifr_mtu
;
2254 if (ifp
->if_flags
& IFF_UP
)
2256 else if (ifp
->if_flags
& IFF_RUNNING
)
2266 mii
= device_get_softc(sc
->re_miibus
);
2267 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
2270 ifp
->if_capenable
&= ~(IFCAP_HWCSUM
);
2271 ifp
->if_capenable
|=
2272 ifr
->ifr_reqcap
& (IFCAP_HWCSUM
);
2273 if (ifp
->if_capenable
& IFCAP_TXCSUM
)
2274 ifp
->if_hwassist
= RE_CSUM_FEATURES
;
2276 ifp
->if_hwassist
= 0;
2277 if (ifp
->if_flags
& IFF_RUNNING
)
2281 error
= ether_ioctl(ifp
, command
, data
);
2288 re_watchdog(struct ifnet
*ifp
)
2290 struct re_softc
*sc
= ifp
->if_softc
;
2292 if_printf(ifp
, "watchdog timeout\n");
2301 if (!ifq_is_empty(&ifp
->if_snd
))
2306 * Stop the adapter and free any mbufs allocated to the
2310 re_stop(struct re_softc
*sc
)
2312 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2316 callout_stop(&sc
->re_timer
);
2318 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
2320 CSR_WRITE_1(sc
, RE_COMMAND
, 0x00);
2321 CSR_WRITE_2(sc
, RE_IMR
, 0x0000);
2322 CSR_WRITE_2(sc
, RE_ISR
, 0xFFFF);
2324 if (sc
->re_head
!= NULL
) {
2325 m_freem(sc
->re_head
);
2326 sc
->re_head
= sc
->re_tail
= NULL
;
2329 /* Free the TX list buffers. */
2330 for (i
= 0; i
< RE_TX_DESC_CNT
; i
++) {
2331 if (sc
->re_ldata
.re_tx_mbuf
[i
] != NULL
) {
2332 bus_dmamap_unload(sc
->re_ldata
.re_mtag
,
2333 sc
->re_ldata
.re_tx_dmamap
[i
]);
2334 m_freem(sc
->re_ldata
.re_tx_mbuf
[i
]);
2335 sc
->re_ldata
.re_tx_mbuf
[i
] = NULL
;
2339 /* Free the RX list buffers. */
2340 for (i
= 0; i
< RE_RX_DESC_CNT
; i
++) {
2341 if (sc
->re_ldata
.re_rx_mbuf
[i
] != NULL
) {
2342 bus_dmamap_unload(sc
->re_ldata
.re_mtag
,
2343 sc
->re_ldata
.re_rx_dmamap
[i
]);
2344 m_freem(sc
->re_ldata
.re_rx_mbuf
[i
]);
2345 sc
->re_ldata
.re_rx_mbuf
[i
] = NULL
;
2351 * Device suspend routine. Stop the interface and save some PCI
2352 * settings in case the BIOS doesn't restore them properly on
2356 re_suspend(device_t dev
)
2358 #ifndef BURN_BRIDGES
2361 struct re_softc
*sc
= device_get_softc(dev
);
2365 #ifndef BURN_BRIDGES
2366 for (i
= 0; i
< 5; i
++)
2367 sc
->saved_maps
[i
] = pci_read_config(dev
, PCIR_MAPS
+ i
* 4, 4);
2368 sc
->saved_biosaddr
= pci_read_config(dev
, PCIR_BIOS
, 4);
2369 sc
->saved_intline
= pci_read_config(dev
, PCIR_INTLINE
, 1);
2370 sc
->saved_cachelnsz
= pci_read_config(dev
, PCIR_CACHELNSZ
, 1);
2371 sc
->saved_lattimer
= pci_read_config(dev
, PCIR_LATTIMER
, 1);
2380 * Device resume routine. Restore some PCI settings in case the BIOS
2381 * doesn't, re-enable busmastering, and restart the interface if
2385 re_resume(device_t dev
)
2387 struct re_softc
*sc
= device_get_softc(dev
);
2388 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2389 #ifndef BURN_BRIDGES
2393 #ifndef BURN_BRIDGES
2394 /* better way to do this? */
2395 for (i
= 0; i
< 5; i
++)
2396 pci_write_config(dev
, PCIR_MAPS
+ i
* 4, sc
->saved_maps
[i
], 4);
2397 pci_write_config(dev
, PCIR_BIOS
, sc
->saved_biosaddr
, 4);
2398 pci_write_config(dev
, PCIR_INTLINE
, sc
->saved_intline
, 1);
2399 pci_write_config(dev
, PCIR_CACHELNSZ
, sc
->saved_cachelnsz
, 1);
2400 pci_write_config(dev
, PCIR_LATTIMER
, sc
->saved_lattimer
, 1);
2402 /* reenable busmastering */
2403 pci_enable_busmaster(dev
);
2404 pci_enable_io(dev
, SYS_RES_IOPORT
);
2407 /* reinitialize interface if necessary */
2408 if (ifp
->if_flags
& IFF_UP
)
2417 * Stop all chip I/O so that the kernel's probe routines don't
2418 * get confused by errant DMAs when rebooting.
2421 re_shutdown(device_t dev
)
2423 struct re_softc
*sc
= device_get_softc(dev
);
2424 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2426 lwkt_serialize_enter(ifp
->if_serializer
);
2428 lwkt_serialize_exit(ifp
->if_serializer
);
2432 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS
)
2434 struct re_softc
*sc
= arg1
;
2435 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2436 int error
= 0, mod
, mod_old
;
2438 lwkt_serialize_enter(ifp
->if_serializer
);
2440 mod_old
= mod
= RE_TX_MODERATION_IS_ENABLED(sc
);
2442 error
= sysctl_handle_int(oidp
, &mod
, 0, req
);
2443 if (error
|| req
->newptr
== NULL
|| mod
== mod_old
)
2445 if (mod
!= 0 && mod
!= 1) {
2451 RE_ENABLE_TX_MODERATION(sc
);
2453 RE_DISABLE_TX_MODERATION(sc
);
2455 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_UP
)) == (IFF_RUNNING
| IFF_UP
))
2458 lwkt_serialize_exit(ifp
->if_serializer
);