1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.17 2007/05/07 04:54:32 sephe Exp $
39 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
40 * 1000mbps; all we need to negotiate here is full or half duplex.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
49 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_arp.h>
58 #include "brgphyreg.h"
59 #include <dev/netif/bge/if_bgereg.h>
61 #include "miibus_if.h"
63 static int brgphy_probe(device_t
);
64 static int brgphy_attach(device_t
);
66 static const struct mii_phydesc brgphys
[] = {
67 MII_PHYDESC(xxBROADCOM
, BCM5400
),
68 MII_PHYDESC(xxBROADCOM
, BCM5401
),
69 MII_PHYDESC(xxBROADCOM
, BCM5411
),
70 MII_PHYDESC(xxBROADCOM
, BCM5421
),
71 MII_PHYDESC(xxBROADCOM
, BCM54K2
),
72 MII_PHYDESC(xxBROADCOM
, BCM5462
),
74 MII_PHYDESC(xxBROADCOM
, BCM5701
),
75 MII_PHYDESC(xxBROADCOM
, BCM5703
),
76 MII_PHYDESC(xxBROADCOM
, BCM5704
),
77 MII_PHYDESC(xxBROADCOM
, BCM5705
),
79 MII_PHYDESC(xxBROADCOM
, BCM5714
),
80 MII_PHYDESC(xxBROADCOM
, BCM5750
),
81 MII_PHYDESC(xxBROADCOM
, BCM5752
),
82 MII_PHYDESC(xxBROADCOM2
,BCM5755
),
83 MII_PHYDESC(xxBROADCOM
, BCM5780
),
84 MII_PHYDESC(xxBROADCOM2
,BCM5787
),
86 MII_PHYDESC(xxBROADCOM
, BCM5706C
),
87 MII_PHYDESC(xxBROADCOM
, BCM5708C
),
92 static device_method_t brgphy_methods
[] = {
93 /* device interface */
94 DEVMETHOD(device_probe
, brgphy_probe
),
95 DEVMETHOD(device_attach
, brgphy_attach
),
96 DEVMETHOD(device_detach
, ukphy_detach
),
97 DEVMETHOD(device_shutdown
, bus_generic_shutdown
),
101 static devclass_t brgphy_devclass
;
103 static driver_t brgphy_driver
= {
106 sizeof(struct mii_softc
)
109 DRIVER_MODULE(brgphy
, miibus
, brgphy_driver
, brgphy_devclass
, 0, 0);
111 static int brgphy_service(struct mii_softc
*, struct mii_data
*, int);
112 static void brgphy_status(struct mii_softc
*);
113 static void brgphy_mii_phy_auto(struct mii_softc
*);
114 static void brgphy_reset(struct mii_softc
*);
115 static void brgphy_loop(struct mii_softc
*);
117 static void brgphy_bcm5401_dspcode(struct mii_softc
*);
118 static void brgphy_bcm5411_dspcode(struct mii_softc
*);
119 static void brgphy_bcm5421_dspcode(struct mii_softc
*);
120 static void brgphy_bcm54k2_dspcode(struct mii_softc
*);
122 static void brgphy_adc_bug(struct mii_softc
*);
123 static void brgphy_5704_a0_bug(struct mii_softc
*);
124 static void brgphy_ber_bug(struct mii_softc
*);
125 static void brgphy_crc_bug(struct mii_softc
*);
127 static void brgphy_jumbo_settings(struct mii_softc
*, u_long
);
128 static void brgphy_eth_wirespeed(struct mii_softc
*);
131 brgphy_probe(device_t dev
)
133 struct mii_attach_args
*ma
= device_get_ivars(dev
);
134 const struct mii_phydesc
*mpd
;
136 mpd
= mii_phy_match(ma
, brgphys
);
138 device_set_desc(dev
, mpd
->mpd_name
);
145 brgphy_attach(device_t dev
)
147 struct mii_softc
*sc
;
148 struct mii_attach_args
*ma
;
149 struct mii_data
*mii
;
151 sc
= device_get_softc(dev
);
152 ma
= device_get_ivars(dev
);
153 mii_softc_init(sc
, ma
);
154 sc
->mii_dev
= device_get_parent(dev
);
155 mii
= device_get_softc(sc
->mii_dev
);
156 LIST_INSERT_HEAD(&mii
->mii_phys
, sc
, mii_list
);
158 sc
->mii_inst
= mii
->mii_instance
;
159 sc
->mii_service
= brgphy_service
;
160 sc
->mii_reset
= brgphy_reset
;
163 sc
->mii_flags
|= MIIF_NOISOLATE
;
168 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
170 ADD(IFM_MAKEWORD(IFM_ETHER
, IFM_NONE
, 0, sc
->mii_inst
),
173 ADD(IFM_MAKEWORD(IFM_ETHER
, IFM_100_TX
, IFM_LOOP
, sc
->mii_inst
),
179 sc
->mii_capabilities
= PHY_READ(sc
, MII_BMSR
) & ma
->mii_capmask
;
180 if (sc
->mii_capabilities
& BMSR_EXTSTAT
)
181 sc
->mii_extcapabilities
= PHY_READ(sc
, MII_EXTSR
);
183 device_printf(dev
, " ");
184 if ((sc
->mii_capabilities
& BMSR_MEDIAMASK
) ||
185 (sc
->mii_extcapabilities
& EXTSR_MEDIAMASK
))
186 mii_phy_add_media(sc
);
188 kprintf("no media present");
191 MIIBUS_MEDIAINIT(sc
->mii_dev
);
196 brgphy_service(struct mii_softc
*sc
, struct mii_data
*mii
, int cmd
)
198 struct ifmedia_entry
*ife
= mii
->mii_media
.ifm_cur
;
204 * If we're not polling our PHY instance, just return.
206 if (IFM_INST(ife
->ifm_media
) != sc
->mii_inst
)
212 * If the media indicates a different PHY instance,
215 if (IFM_INST(ife
->ifm_media
) != sc
->mii_inst
) {
216 reg
= PHY_READ(sc
, MII_BMCR
);
217 PHY_WRITE(sc
, MII_BMCR
, reg
| BMCR_ISO
);
222 * If the interface is not up, don't do anything.
224 if ((mii
->mii_ifp
->if_flags
& IFF_UP
) == 0)
227 brgphy_reset(sc
); /* XXX hardware bug work-around */
229 switch (IFM_SUBTYPE(ife
->ifm_media
)) {
233 * If we're already in auto mode, just return.
235 if (PHY_READ(sc
, BRGPHY_MII_BMCR
) & BRGPHY_BMCR_AUTOEN
)
238 brgphy_mii_phy_auto(sc
);
241 speed
= BRGPHY_S1000
;
250 if ((ife
->ifm_media
& IFM_GMASK
) == IFM_FDX
) {
251 speed
|= BRGPHY_BMCR_FDX
;
252 gig
= BRGPHY_1000CTL_AFD
;
254 gig
= BRGPHY_1000CTL_AHD
;
257 PHY_WRITE(sc
, BRGPHY_MII_1000CTL
, 0);
258 PHY_WRITE(sc
, BRGPHY_MII_BMCR
, speed
);
259 PHY_WRITE(sc
, BRGPHY_MII_ANAR
, BRGPHY_SEL_TYPE
);
261 if (IFM_SUBTYPE(ife
->ifm_media
) != IFM_1000_T
)
264 PHY_WRITE(sc
, BRGPHY_MII_1000CTL
, gig
);
265 PHY_WRITE(sc
, BRGPHY_MII_BMCR
,
266 speed
|BRGPHY_BMCR_AUTOEN
|BRGPHY_BMCR_STARTNEG
);
268 if (sc
->mii_model
!= MII_MODEL_xxBROADCOM_BCM5701
)
272 * When settning the link manually, one side must
273 * be the master and the other the slave. However
274 * ifmedia doesn't give us a good way to specify
275 * this, so we fake it by using one of the LINK
276 * flags. If LINK0 is set, we program the PHY to
277 * be a master, otherwise it's a slave.
279 if ((mii
->mii_ifp
->if_flags
& IFF_LINK0
)) {
280 PHY_WRITE(sc
, BRGPHY_MII_1000CTL
,
281 gig
|BRGPHY_1000CTL_MSE
|BRGPHY_1000CTL_MSC
);
283 PHY_WRITE(sc
, BRGPHY_MII_1000CTL
,
284 gig
|BRGPHY_1000CTL_MSE
);
289 PHY_WRITE(sc
, MII_BMCR
, BMCR_ISO
|BMCR_PDOWN
);
300 * If we're not currently selected, just return.
302 if (IFM_INST(ife
->ifm_media
) != sc
->mii_inst
)
306 * Is the interface even up?
308 if ((mii
->mii_ifp
->if_flags
& IFF_UP
) == 0)
312 * Only used for autonegotiation.
314 if (IFM_SUBTYPE(ife
->ifm_media
) != IFM_AUTO
)
318 * Check to see if we have link. If we do, we don't
319 * need to restart the autonegotiation process. Read
320 * the BMSR twice in case it's latched.
322 reg
= PHY_READ(sc
, BRGPHY_MII_AUXSTS
);
323 if (reg
& BRGPHY_AUXSTS_LINK
)
327 * Only retry autonegotiation every 5 seconds.
329 if (++sc
->mii_ticks
<= sc
->mii_anegticks
)
333 brgphy_mii_phy_auto(sc
);
337 /* Update the media status. */
341 * Callback if something changed. Note that we need to poke
342 * the DSP on the Broadcom PHYs if the media changes.
344 if (sc
->mii_media_active
!= mii
->mii_media_active
||
345 sc
->mii_media_status
!= mii
->mii_media_status
||
346 cmd
== MII_MEDIACHG
) {
347 switch (sc
->mii_model
) {
348 case MII_MODEL_xxBROADCOM_BCM5400
:
349 brgphy_bcm5401_dspcode(sc
);
351 case MII_MODEL_xxBROADCOM_BCM5401
:
352 if (sc
->mii_rev
== 1 || sc
->mii_rev
== 3)
353 brgphy_bcm5401_dspcode(sc
);
355 case MII_MODEL_xxBROADCOM_BCM5411
:
356 brgphy_bcm5411_dspcode(sc
);
360 mii_phy_update(sc
, cmd
);
365 brgphy_status(struct mii_softc
*sc
)
367 struct mii_data
*mii
= sc
->mii_pdata
;
370 mii
->mii_media_status
= IFM_AVALID
;
371 mii
->mii_media_active
= IFM_ETHER
;
373 aux
= PHY_READ(sc
, BRGPHY_MII_AUXSTS
);
374 if (aux
& BRGPHY_AUXSTS_LINK
)
375 mii
->mii_media_status
|= IFM_ACTIVE
;
377 bmcr
= PHY_READ(sc
, BRGPHY_MII_BMCR
);
378 if (bmcr
& BRGPHY_BMCR_LOOP
)
379 mii
->mii_media_active
|= IFM_LOOP
;
381 if (bmcr
& BRGPHY_BMCR_AUTOEN
) {
382 if ((PHY_READ(sc
, BRGPHY_MII_BMSR
) & BRGPHY_BMSR_ACOMP
) == 0) {
383 /* Erg, still trying, I guess... */
384 mii
->mii_media_active
|= IFM_NONE
;
388 switch (aux
& BRGPHY_AUXSTS_AN_RES
) {
389 case BRGPHY_RES_1000FD
:
390 mii
->mii_media_active
|= IFM_1000_T
| IFM_FDX
;
392 case BRGPHY_RES_1000HD
:
393 mii
->mii_media_active
|= IFM_1000_T
| IFM_HDX
;
395 case BRGPHY_RES_100FD
:
396 mii
->mii_media_active
|= IFM_100_TX
| IFM_FDX
;
398 case BRGPHY_RES_100T4
:
399 mii
->mii_media_active
|= IFM_100_T4
;
401 case BRGPHY_RES_100HD
:
402 mii
->mii_media_active
|= IFM_100_TX
| IFM_HDX
;
404 case BRGPHY_RES_10FD
:
405 mii
->mii_media_active
|= IFM_10_T
| IFM_FDX
;
407 case BRGPHY_RES_10HD
:
408 mii
->mii_media_active
|= IFM_10_T
| IFM_HDX
;
411 mii
->mii_media_active
|= IFM_NONE
;
415 mii
->mii_media_active
= mii
->mii_media
.ifm_cur
->ifm_media
;
421 brgphy_mii_phy_auto(struct mii_softc
*sc
)
427 ktcr
= BRGPHY_1000CTL_AFD
|BRGPHY_1000CTL_AHD
;
428 if (sc
->mii_model
== MII_MODEL_xxBROADCOM_BCM5701
)
429 ktcr
|= BRGPHY_1000CTL_MSE
|BRGPHY_1000CTL_MSC
;
430 PHY_WRITE(sc
, BRGPHY_MII_1000CTL
, ktcr
);
431 ktcr
= PHY_READ(sc
, BRGPHY_MII_1000CTL
);
433 PHY_WRITE(sc
, BRGPHY_MII_ANAR
,
434 BMSR_MEDIA_TO_ANAR(sc
->mii_capabilities
) | ANAR_CSMA
);
436 PHY_WRITE(sc
, BRGPHY_MII_BMCR
,
437 BRGPHY_BMCR_AUTOEN
| BRGPHY_BMCR_STARTNEG
);
438 PHY_WRITE(sc
, BRGPHY_MII_IMR
, 0xFF00);
442 brgphy_loop(struct mii_softc
*sc
)
447 PHY_WRITE(sc
, BRGPHY_MII_BMCR
, BRGPHY_BMCR_LOOP
);
448 for (i
= 0; i
< 15000; i
++) {
449 bmsr
= PHY_READ(sc
, BRGPHY_MII_BMSR
);
450 if (!(bmsr
& BRGPHY_BMSR_LINK
))
457 brgphy_reset(struct mii_softc
*sc
)
463 switch (sc
->mii_model
) {
464 case MII_MODEL_xxBROADCOM_BCM5400
:
465 brgphy_bcm5401_dspcode(sc
);
467 case MII_MODEL_xxBROADCOM_BCM5401
:
468 if (sc
->mii_rev
== 1 || sc
->mii_rev
== 3)
469 brgphy_bcm5401_dspcode(sc
);
471 case MII_MODEL_xxBROADCOM_BCM5411
:
472 brgphy_bcm5411_dspcode(sc
);
474 case MII_MODEL_xxBROADCOM_BCM5421
:
475 brgphy_bcm5421_dspcode(sc
);
477 case MII_MODEL_xxBROADCOM_BCM54K2
:
478 brgphy_bcm54k2_dspcode(sc
);
482 ifp
= sc
->mii_pdata
->mii_ifp
;
483 if (strncmp(ifp
->if_xname
, "bge", 3) == 0) {
484 struct bge_softc
*bge_sc
= ifp
->if_softc
;
486 if (bge_sc
->bge_flags
& BGE_FLAG_ADC_BUG
)
488 if (bge_sc
->bge_flags
& BGE_FLAG_5704_A0_BUG
)
489 brgphy_5704_a0_bug(sc
);
490 if (bge_sc
->bge_flags
& BGE_FLAG_BER_BUG
) {
492 } else if (bge_sc
->bge_flags
& BGE_FLAG_JITTER_BUG
) {
493 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x0c00);
494 PHY_WRITE(sc
, BRGPHY_MII_DSP_ADDR_REG
, 0x000a);
496 if (bge_sc
->bge_flags
& BGE_FLAG_ADJUST_TRIM
) {
497 PHY_WRITE(sc
, BRGPHY_MII_DSP_RW_PORT
, 0x110b);
498 PHY_WRITE(sc
, BRGPHY_TEST1
,
499 BRGPHY_TEST1_TRIM_EN
| 0x4);
501 PHY_WRITE(sc
, BRGPHY_MII_DSP_RW_PORT
, 0x010b);
504 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x0400);
506 if (bge_sc
->bge_flags
& BGE_FLAG_CRC_BUG
)
509 /* Set Jumbo frame settings in the PHY. */
510 brgphy_jumbo_settings(sc
, ifp
->if_mtu
);
512 /* Enable Ethernet@Wirespeed */
513 if (bge_sc
->bge_flags
& BGE_FLAG_ETH_WIRESPEED
)
514 brgphy_eth_wirespeed(sc
);
516 /* Enable Link LED on Dell boxes */
517 if (bge_sc
->bge_flags
& BGE_FLAG_NO_3LED
) {
518 PHY_WRITE(sc
, BRGPHY_MII_PHY_EXTCTL
,
519 PHY_READ(sc
, BRGPHY_MII_PHY_EXTCTL
)
520 & ~BRGPHY_PHY_EXTCTL_3_LED
);
525 /* Turn off tap power management on 5401. */
527 brgphy_bcm5401_dspcode(struct mii_softc
*sc
)
529 static const struct {
533 { BRGPHY_MII_AUXCTL
, 0x0c20 },
534 { BRGPHY_MII_DSP_ADDR_REG
, 0x0012 },
535 { BRGPHY_MII_DSP_RW_PORT
, 0x1804 },
536 { BRGPHY_MII_DSP_ADDR_REG
, 0x0013 },
537 { BRGPHY_MII_DSP_RW_PORT
, 0x1204 },
538 { BRGPHY_MII_DSP_ADDR_REG
, 0x8006 },
539 { BRGPHY_MII_DSP_RW_PORT
, 0x0132 },
540 { BRGPHY_MII_DSP_ADDR_REG
, 0x8006 },
541 { BRGPHY_MII_DSP_RW_PORT
, 0x0232 },
542 { BRGPHY_MII_DSP_ADDR_REG
, 0x201f },
543 { BRGPHY_MII_DSP_RW_PORT
, 0x0a20 },
548 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
549 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
553 /* Setting some undocumented voltage */
555 brgphy_bcm5411_dspcode(struct mii_softc
*sc
)
557 static const struct {
568 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
569 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
573 brgphy_bcm5421_dspcode(struct mii_softc
*sc
)
577 /* Set Class A mode */
578 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x1007);
579 data
= PHY_READ(sc
, BRGPHY_MII_AUXCTL
);
580 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, data
| 0x0400);
582 /* Set FFE gamma override to -0.125 */
583 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x0007);
584 data
= PHY_READ(sc
, BRGPHY_MII_AUXCTL
);
585 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, data
| 0x0800);
586 PHY_WRITE(sc
, BRGPHY_MII_DSP_ADDR_REG
, 0x000a);
587 data
= PHY_READ(sc
, BRGPHY_MII_DSP_RW_PORT
);
588 PHY_WRITE(sc
, BRGPHY_MII_DSP_RW_PORT
, data
| 0x0200);
592 brgphy_bcm54k2_dspcode(struct mii_softc
*sc
)
594 static const struct {
604 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
605 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
609 brgphy_adc_bug(struct mii_softc
*sc
)
611 static const struct {
615 { BRGPHY_MII_AUXCTL
, 0x0c00 },
616 { BRGPHY_MII_DSP_ADDR_REG
, 0x201f },
617 { BRGPHY_MII_DSP_RW_PORT
, 0x2aaa },
618 { BRGPHY_MII_DSP_ADDR_REG
, 0x000a },
619 { BRGPHY_MII_DSP_RW_PORT
, 0x0323 },
620 { BRGPHY_MII_AUXCTL
, 0x0400 },
625 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
626 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
630 brgphy_5704_a0_bug(struct mii_softc
*sc
)
632 static const struct {
642 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
643 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
647 brgphy_ber_bug(struct mii_softc
*sc
)
649 static const struct {
653 { BRGPHY_MII_AUXCTL
, 0x0c00 },
654 { BRGPHY_MII_DSP_ADDR_REG
, 0x000a },
655 { BRGPHY_MII_DSP_RW_PORT
, 0x310b },
656 { BRGPHY_MII_DSP_ADDR_REG
, 0x201f },
657 { BRGPHY_MII_DSP_RW_PORT
, 0x9506 },
658 { BRGPHY_MII_DSP_ADDR_REG
, 0x401f },
659 { BRGPHY_MII_DSP_RW_PORT
, 0x14e2 },
660 { BRGPHY_MII_AUXCTL
, 0x0400 },
665 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
666 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
670 brgphy_crc_bug(struct mii_softc
*sc
)
672 static const struct {
676 { BRGPHY_MII_DSP_ADDR_REG
, 0x0a75 },
684 for (i
= 0; dspcode
[i
].reg
!= 0; i
++)
685 PHY_WRITE(sc
, dspcode
[i
].reg
, dspcode
[i
].val
);
689 brgphy_jumbo_settings(struct mii_softc
*sc
, u_long mtu
)
693 /* Set or clear jumbo frame settings in the PHY. */
694 if (mtu
> ETHER_MAX_LEN
) {
695 if (sc
->mii_model
== MII_MODEL_xxBROADCOM_BCM5401
) {
696 /* BCM5401 PHY cannot read-modify-write. */
697 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x4c20);
699 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x7);
700 val
= PHY_READ(sc
, BRGPHY_MII_AUXCTL
);
701 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
,
702 val
| BRGPHY_AUXCTL_LONG_PKT
);
705 val
= PHY_READ(sc
, BRGPHY_MII_PHY_EXTCTL
);
706 PHY_WRITE(sc
, BRGPHY_MII_PHY_EXTCTL
,
707 val
| BRGPHY_PHY_EXTCTL_HIGH_LA
);
709 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x7);
710 val
= PHY_READ(sc
, BRGPHY_MII_AUXCTL
);
711 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
,
712 val
& ~(BRGPHY_AUXCTL_LONG_PKT
| 0x7));
714 val
= PHY_READ(sc
, BRGPHY_MII_PHY_EXTCTL
);
715 PHY_WRITE(sc
, BRGPHY_MII_PHY_EXTCTL
,
716 val
& ~BRGPHY_PHY_EXTCTL_HIGH_LA
);
721 brgphy_eth_wirespeed(struct mii_softc
*sc
)
725 /* Enable Ethernet@Wirespeed */
726 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, 0x7007);
727 val
= PHY_READ(sc
, BRGPHY_MII_AUXCTL
);
728 PHY_WRITE(sc
, BRGPHY_MII_AUXCTL
, (val
| (1 << 15) | (1 << 4)));