sys/dev/raid/twa/twa_reg.h

   1 /*-
   2  * Copyright (c) 2003-04 3ware, Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  *      $FreeBSD$
  27  * $DragonFly: src/sys/dev/raid/twa/twa_reg.h,v 1.2 2006/12/23 00:26:24 swildner Exp $
  28  */
  29
  30 /*
  31  * 3ware driver for 9000 series storage controllers.
  32  *
  33  * Author: Vinod Kashyap
  34  */
  35
  36 /*
  37  * The following macro has no business being in twa_reg.h.  It should probably
  38  * be defined in twa_includes.h, before the #include twa_reg.h....  But that
  39  * causes the API to run into build errors.  Will leave it here for now...
  40  */
  41 #define TWA_64BIT_ADDRESSES     ((sizeof(bus_addr_t) == 8) ? 1 : 0)
  42
  43 /* Register offsets from base address. */
  44 #define TWA_CONTROL_REGISTER_OFFSET             0x0
  45 #define TWA_STATUS_REGISTER_OFFSET              0x4
  46 #define TWA_COMMAND_QUEUE_OFFSET                0x8
  47 #define TWA_RESPONSE_QUEUE_OFFSET               0xC
  48 #define TWA_COMMAND_QUEUE_OFFSET_LOW            0x20
  49 #define TWA_COMMAND_QUEUE_OFFSET_HIGH           0x24
  50
  51 /* Functions to read from, and write to registers */
  52 #define TWA_WRITE_CONTROL_REGISTER(sc, val)     \
  53         TWA_WRITE_REGISTER(sc, TWA_CONTROL_REGISTER_OFFSET, val)
  54 #define TWA_READ_STATUS_REGISTER(sc)            \
  55         TWA_READ_REGISTER(sc, TWA_STATUS_REGISTER_OFFSET)
  56 #define TWA_WRITE_COMMAND_QUEUE(sc, val)                                \
  57         do {                                                            \
  58                 if (TWA_64BIT_ADDRESSES) {                              \
  59                         /* First write the low 4 bytes, then the high 4. */  \
  60                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \
  61                                                 (u_int32_t)(val));      \
  62                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
  63                                         (u_int32_t)(((u_int64_t)val)>>32));  \
  64                 } else                                                  \
  65                         TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\
  66                                                 (u_int32_t)(val)); \
  67         } while (0)
  68 #define TWA_READ_RESPONSE_QUEUE(sc)             \
  69         (union twa_response_queue)TWA_READ_REGISTER(sc, TWA_RESPONSE_QUEUE_OFFSET)
  70
  71 /* Control register bit definitions. */
  72 #define TWA_CONTROL_CLEAR_SBUF_WRITE_ERROR      0x00000008
  73 #define TWA_CONTROL_ISSUE_HOST_INTERRUPT        0x00000020
  74 #define TWA_CONTROL_DISABLE_INTERRUPTS          0x00000040
  75 #define TWA_CONTROL_ENABLE_INTERRUPTS           0x00000080
  76 #define TWA_CONTROL_ISSUE_SOFT_RESET            0x00000100
  77 #define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT   0x00004000
  78 #define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT    0x00008000
  79 #define TWA_CONTROL_MASK_RESPONSE_INTERRUPT     0x00010000
  80 #define TWA_CONTROL_MASK_COMMAND_INTERRUPT      0x00020000
  81 #define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT   0x00040000
  82 #define TWA_CONTROL_CLEAR_HOST_INTERRUPT        0x00080000
  83 #define TWA_CONTROL_CLEAR_PCI_ABORT             0x00100000
  84 #define TWA_CONTROL_CLEAR_QUEUE_ERROR           0x00400000
  85 #define TWA_CONTROL_CLEAR_PARITY_ERROR          0x00800000
  86
  87
  88 #define TWA_SOFT_RESET(sc)                                              \
  89                 TWA_WRITE_CONTROL_REGISTER(sc,                          \
  90                         TWA_CONTROL_ISSUE_SOFT_RESET |                  \
  91                         TWA_CONTROL_CLEAR_HOST_INTERRUPT |              \
  92                         TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT |         \
  93                         TWA_CONTROL_MASK_COMMAND_INTERRUPT |            \
  94                         TWA_CONTROL_MASK_RESPONSE_INTERRUPT |           \
  95                         TWA_CONTROL_DISABLE_INTERRUPTS)
  96
  97 /* Status register bit definitions. */
  98 #define TWA_STATUS_ROM_BIOS_IN_SBUF             0x00000002
  99 #define TWA_STATUS_SBUF_WRITE_ERROR             0x00000008
 100 #define TWA_STATUS_COMMAND_QUEUE_EMPTY          0x00001000
 101 #define TWA_STATUS_MICROCONTROLLER_READY        0x00002000
 102 #define TWA_STATUS_RESPONSE_QUEUE_EMPTY         0x00004000
 103 #define TWA_STATUS_COMMAND_QUEUE_FULL           0x00008000
 104 #define TWA_STATUS_RESPONSE_INTERRUPT           0x00010000
 105 #define TWA_STATUS_COMMAND_INTERRUPT            0x00020000
 106 #define TWA_STATUS_ATTENTION_INTERRUPT          0x00040000
 107 #define TWA_STATUS_HOST_INTERRUPT               0x00080000
 108 #define TWA_STATUS_PCI_ABORT_INTERRUPT          0x00100000
 109 #define TWA_STATUS_MICROCONTROLLER_ERROR        0x00200000
 110 #define TWA_STATUS_QUEUE_ERROR_INTERRUPT        0x00400000
 111 #define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT   0x00800000
 112 #define TWA_STATUS_MINOR_VERSION_MASK           0x0F000000
 113 #define TWA_STATUS_MAJOR_VERSION_MASK           0xF0000000
 114
 115 #define TWA_STATUS_EXPECTED_BITS                0x00002000
 116 #define TWA_STATUS_UNEXPECTED_BITS              0x00F00000
 117
 118 /* For use with the %b kprintf format. */
 119 #define TWA_STATUS_BITS_DESCRIPTION \
 120         "\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n"
 121
 122 /* Detect inconsistencies in the status register. */
 123 #define TWA_STATUS_ERRORS(x)                    \
 124         ((x & TWA_STATUS_UNEXPECTED_BITS) &&    \
 125          (x & TWA_STATUS_MICROCONTROLLER_READY))
 126
 127 /* PCI related defines. */
 128 #define TWA_IO_CONFIG_REG               0x10
 129 #define TWA_DEVICE_NAME                 "3ware 9000 series Storage Controller"
 130 #define TWA_VENDOR_ID                   0x13C1
 131 #define TWA_DEVICE_ID_9K                0x1002
 132
 133 #define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR       0xc100
 134 #define TWA_PCI_CONFIG_CLEAR_PCI_ABORT          0x2000
 135
 136 /* Command packet opcodes. */
 137 #define TWA_OP_NOP                      0x00
 138 #define TWA_OP_INIT_CONNECTION          0x01
 139 #define TWA_OP_READ                     0x02
 140 #define TWA_OP_WRITE                    0x03
 141 #define TWA_OP_READVERIFY               0x04
 142 #define TWA_OP_VERIFY                   0x05
 143 #define TWA_OP_ZEROUNIT                 0x08
 144 #define TWA_OP_REPLACEUNIT              0x09
 145 #define TWA_OP_HOTSWAP                  0x0A
 146 #define TWA_OP_SELFTESTS                0x0B
 147 #define TWA_OP_SYNC_PARAM               0x0C
 148 #define TWA_OP_REORDER_UNITS            0x0D
 149
 150 #define TWA_OP_EXECUTE_SCSI_COMMAND     0x10
 151 #define TWA_OP_ATA_PASSTHROUGH          0x11
 152 #define TWA_OP_GET_PARAM                0x12
 153 #define TWA_OP_SET_PARAM                0x13
 154 #define TWA_OP_CREATEUNIT               0x14
 155 #define TWA_OP_DELETEUNIT               0x15
 156 #define TWA_OP_DOWNLOAD_FIRMWARE        0x16
 157 #define TWA_OP_REBUILDUNIT              0x17
 158 #define TWA_OP_POWER_MANAGEMENT         0x18
 159
 160 #define TWA_OP_REMOTE_PRINT             0x1B
 161 #define TWA_OP_RESET_FIRMWARE           0x1C
 162 #define TWA_OP_DEBUG                    0x1D
 163
 164 #define TWA_OP_DIAGNOSTICS              0x1F
 165
 166 /* Misc defines. */
 167 #define TWA_ALIGNMENT                   0x4
 168 #define TWA_MAX_UNITS                   16
 169 #define TWA_INIT_MESSAGE_CREDITS        0x100
 170 #define TWA_SHUTDOWN_MESSAGE_CREDITS    0x001
 171 #define TWA_64BIT_SG_ADDRESSES          0x00000001
 172 #define TWA_EXTENDED_INIT_CONNECT       0x00000002
 173 #define TWA_BASE_MODE                   1
 174 #define TWA_BASE_FW_SRL                 0x17
 175 #define TWA_BASE_FW_BRANCH              0
 176 #define TWA_BASE_FW_BUILD               1
 177 #define TWA_CURRENT_FW_SRL              0x18
 178 #define TWA_CURRENT_FW_BRANCH           1
 179 #define TWA_CURRENT_FW_BUILD            9
 180 #define TWA_9000_ARCH_ID                0x5     /* 9000 series controllers */
 181 #define TWA_CTLR_FW_SAME_OR_NEWER       0x00000001
 182 #define TWA_CTLR_FW_COMPATIBLE          0x00000002
 183 #define TWA_BUNDLED_FW_SAFE_TO_FLASH    0x00000004
 184 #define TWA_CTLR_FW_RECOMMENDS_FLASH    0x00000008
 185 #define NUM_FW_IMAGE_CHUNKS             5
 186 #define TWA_MAX_IO_SIZE                 0x20000 /* 128K */
 187 #define TWA_MAX_SG_ELEMENTS             (TWA_64BIT_ADDRESSES ? 70 : 105)
 188 #define TWA_MAX_ATA_SG_ELEMENTS         60
 189 #define TWA_Q_LENGTH                    TWA_INIT_MESSAGE_CREDITS
 190 #define TWA_MAX_RESET_TRIES             3
 191 #define TWA_SECTOR_SIZE                 0x200   /* generic I/O bufffer */
 192 #define TWA_SENSE_DATA_LENGTH           18
 193
 194 #define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED    0x010a
 195 #define TWA_ERROR_UNIT_OFFLINE                  0x0128
 196 #define TWA_ERROR_MORE_DATA                     0x0231
 197
 198 #pragma pack(1)
 199 /* Scatter/Gather list entry. */
 200 struct twa_sg {
 201         bus_addr_t      address;
 202         bus_size_t      length;
 203 } __attribute__ ((packed));
 204
 205
 206 /* 7000 structures. */
 207 struct twa_command_init_connect {
 208         u_int8_t        opcode:5;       /* TWA_OP_INITCONNECTION */
 209         u_int8_t        res1:3;
 210         u_int8_t        size;
 211         u_int8_t        request_id;
 212         u_int8_t        res2;
 213         u_int8_t        status;
 214         u_int8_t        flags;
 215         u_int16_t       message_credits;
 216         u_int32_t       features;
 217         u_int16_t       fw_srl;
 218         u_int16_t       fw_arch_id;
 219         u_int16_t       fw_branch;
 220         u_int16_t       fw_build;
 221         u_int32_t       result;
 222 } __attribute__ ((packed));
 223
 224
 225 struct twa_command_download_firmware {
 226         u_int8_t        opcode:5;       /* TWA_DOWNLOAD_FIRMWARE */
 227         u_int8_t        sgl_offset:3;
 228         u_int8_t        size;
 229         u_int8_t        request_id;
 230         u_int8_t        unit;
 231         u_int8_t        status;
 232         u_int8_t        flags;
 233         u_int16_t       param;
 234         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
 235 } __attribute__ ((packed));
 236
 237
 238 struct twa_command_reset_firmware {
 239         u_int8_t        opcode:5;       /* TWA_OP_RESET_FIRMWARE */
 240         u_int8_t        res1:3;
 241         u_int8_t        size;
 242         u_int8_t        request_id;
 243         u_int8_t        unit;
 244         u_int8_t        status;
 245         u_int8_t        flags;
 246         u_int8_t        res2;
 247         u_int8_t        param;
 248 } __attribute__ ((packed));
 249
 250
 251 struct twa_command_io {
 252         u_int8_t        opcode:5;       /* TWA_OP_READ/TWA_OP_WRITE */
 253         u_int8_t        sgl_offset:3;
 254         u_int8_t        size;
 255         u_int8_t        request_id;
 256         u_int8_t        unit:4;
 257         u_int8_t        host_id:4;
 258         u_int8_t        status;
 259         u_int8_t        flags;
 260         u_int16_t       block_count;
 261         u_int32_t       lba;
 262         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
 263 } __attribute__ ((packed));
 264
 265
 266 struct twa_command_hotswap {
 267         u_int8_t        opcode:5;       /* TWA_OP_HOTSWAP */
 268         u_int8_t        res1:3;
 269         u_int8_t        size;
 270         u_int8_t        request_id;
 271         u_int8_t        unit:4;
 272         u_int8_t        host_id:4;
 273         u_int8_t        status;
 274         u_int8_t        flags;
 275         u_int8_t        action;
 276 #define TWA_OP_HOTSWAP_REMOVE           0x00    /* remove assumed-degraded unit */
 277 #define TWA_OP_HOTSWAP_ADD_CBOD         0x01    /* add CBOD to empty port */
 278 #define TWA_OP_HOTSWAP_ADD_SPARE        0x02    /* add spare to empty port */
 279         u_int8_t        aport;
 280 } __attribute__ ((packed));
 281
 282
 283 struct twa_command_param {
 284         u_int8_t        opcode:5;       /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */
 285         u_int8_t        sgl_offset:3;
 286         u_int8_t        size;
 287         u_int8_t        request_id;
 288         u_int8_t        unit:4;
 289         u_int8_t        host_id:4;
 290         u_int8_t        status;
 291         u_int8_t        flags;
 292         u_int16_t       param_count;
 293         struct twa_sg   sgl[TWA_MAX_SG_ELEMENTS];
 294 } __attribute__ ((packed));
 295
 296
 297 struct twa_command_rebuildunit {
 298         u_int8_t        opcode:5;       /* TWA_OP_REBUILDUNIT */
 299         u_int8_t        res1:3;
 300         u_int8_t        size;
 301         u_int8_t        request_id;
 302         u_int8_t        src_unit:4;
 303         u_int8_t        host_id:4;
 304         u_int8_t        status;
 305         u_int8_t        flags;
 306         u_int8_t        action:7;
 307 #define TWA_OP_REBUILDUNIT_NOP          0
 308 #define TWA_OP_REBUILDUNIT_STOP         2       /* stop all rebuilds */
 309 #define TWA_OP_REBUILDUNIT_START        4       /* start rebuild with lowest unit */
 310 #define TWA_OP_REBUILDUNIT_STARTUNIT    5       /* rebuild src_unit (not supported) */
 311         u_int8_t        cs:1;                   /* request state change on src_unit */
 312         u_int8_t        logical_subunit;        /* for RAID10 rebuild of logical subunit */
 313 } __attribute__ ((packed));
 314
 315
 316 struct twa_command_ata {
 317         u_int8_t        opcode:5;       /* TWA_OP_ATA_PASSTHROUGH */
 318         u_int8_t        sgl_offset:3;
 319         u_int8_t        size;
 320         u_int8_t        request_id;
 321         u_int8_t        unit:4;
 322         u_int8_t        host_id:4;
 323         u_int8_t        status;
 324         u_int8_t        flags;
 325         u_int16_t       param;
 326         u_int16_t       features;
 327         u_int16_t       sector_count;
 328         u_int16_t       sector_num;
 329         u_int16_t       cylinder_lo;
 330         u_int16_t       cylinder_hi;
 331         u_int8_t        drive_head;
 332         u_int8_t        command;
 333         struct twa_sg   sgl[TWA_MAX_ATA_SG_ELEMENTS];
 334 } __attribute__ ((packed));
 335
 336
 337 struct twa_command_generic {
 338         u_int8_t        opcode:5;
 339         u_int8_t        sgl_offset:3;
 340         u_int8_t        size;
 341         u_int8_t        request_id;
 342         u_int8_t        unit:4;
 343         u_int8_t        host_id:4;
 344         u_int8_t        status;
 345         u_int8_t        flags;
 346 #define TWA_FLAGS_SUCCESS       0x00
 347 #define TWA_FLAGS_INFORMATIONAL 0x01
 348 #define TWA_FLAGS_WARNING       0x02
 349 #define TWA_FLAGS_FATAL         0x03
 350 #define TWA_FLAGS_PERCENTAGE    (1<<8)  /* bits 0-6 indicate completion percentage */
 351         u_int16_t       count;          /* block count, parameter count, message credits */
 352 } __attribute__ ((packed));
 353
 354
 355 /* Command packet - must be TWA_ALIGNMENT aligned. */
 356 union twa_command_7k {
 357         struct twa_command_init_connect         init_connect;
 358         struct twa_command_download_firmware    download_fw;
 359         struct twa_command_reset_firmware       reset_fw;
 360         struct twa_command_io                   io;
 361         struct twa_command_hotswap              hotswap;
 362         struct twa_command_param                param;
 363         struct twa_command_rebuildunit          rebuildunit;
 364         struct twa_command_ata                  ata;
 365         struct twa_command_generic              generic;
 366 } __attribute__ ((packed));
 367
 368
 369 /* 9000 structures. */
 370
 371 /* Command Packet. */
 372 struct twa_command_9k {
 373         struct {
 374                 u_int8_t        opcode:5;
 375                 u_int8_t        reserved:3;
 376         } command;
 377         u_int8_t        unit;
 378         u_int16_t       request_id;
 379         u_int8_t        status;
 380         u_int8_t        sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */
 381         u_int16_t       sgl_entries;
 382         u_int8_t        cdb[16];
 383         struct twa_sg   sg_list[TWA_MAX_SG_ELEMENTS];
 384         u_int8_t        padding[32];
 385 } __attribute__ ((packed));
 386
 387
 388 /* Command packet header. */
 389 struct twa_command_header {
 390         u_int8_t        sense_data[TWA_SENSE_DATA_LENGTH];
 391         struct {
 392                 int8_t          reserved[4];
 393                 u_int16_t       error;
 394                 u_int8_t        padding;
 395                 struct {
 396                         u_int8_t        severity:3;
 397                         u_int8_t        reserved:5;
 398                 } substatus_block;
 399         } status_block;
 400         u_int8_t        err_specific_desc[98];
 401         struct {
 402                 u_int8_t        size_header;
 403                 u_int16_t       reserved;
 404                 u_int8_t        size_sense;
 405         } header_desc;
 406 } __attribute__ ((packed));
 407
 408
 409 /* Full command packet. */
 410 struct twa_command_packet {
 411         struct twa_command_header       cmd_hdr;
 412         union {
 413                 union twa_command_7k    cmd_pkt_7k;
 414                 struct twa_command_9k   cmd_pkt_9k;
 415         } command;
 416 } __attribute__ ((packed));
 417
 418
 419 /* Response queue entry. */
 420 union twa_response_queue {
 421         struct {
 422                 u_int32_t       undefined_1:4;
 423                 u_int32_t       response_id:8;
 424                 u_int32_t       undefined_2:20;
 425         } u;
 426         u_int32_t       value;
 427 } __attribute__ ((packed));
 428
 429
 430 #define TWA_AEN_QUEUE_EMPTY             0x00
 431 #define TWA_AEN_SOFT_RESET              0x01
 432 #define TWA_AEN_SYNC_TIME_WITH_HOST     0x31
 433 #define TWA_AEN_SEVERITY_ERROR          0x1
 434 #define TWA_AEN_SEVERITY_WARNING        0x1
 435 #define TWA_AEN_SEVERITY_INFO           0x1
 436 #define TWA_AEN_SEVERITY_DEBUG          0x4
 437
 438 #define TWA_PARAM_VERSION_TABLE         0x0402
 439 #define TWA_PARAM_VERSION_MONITOR       2       /* monitor version [16] */
 440 #define TWA_PARAM_VERSION_FW            3       /* firmware version [16] */
 441 #define TWA_PARAM_VERSION_BIOS          4       /* BIOSs version [16] */
 442 #define TWA_PARAM_VERSION_PCBA          5       /* PCB version [8] */
 443 #define TWA_PARAM_VERSION_ATA           6       /* A-chip version [8] */
 444 #define TWA_PARAM_VERSION_PCI           7       /* P-chip version [8] */
 445
 446 #define TWA_PARAM_CONTROLLER_TABLE      0x0403
 447 #define TWA_PARAM_CONTROLLER_PORT_COUNT 3       /* number of ports [1] */
 448
 449 #define TWA_PARAM_TIME_TABLE            0x40A
 450 #define TWA_PARAM_TIME_SchedulerTime    0x3
 451
 452 #define TWA_9K_PARAM_DESCRIPTOR         0x8000
 453
 454
 455 struct twa_param_9k {
 456         u_int16_t       table_id;
 457         u_int8_t        parameter_id;
 458         u_int8_t        reserved;
 459         u_int16_t       parameter_size_bytes;
 460         u_int16_t       parameter_actual_size_bytes;
 461         u_int8_t        data[1];
 462 } __attribute__ ((packed));
 463 #pragma pack()
 464