sys/dev/raid/amr/amrreg.h

   1 /*-
   2  * Copyright (c) 1999,2000 Michael Smith
   3  * Copyright (c) 2000 BSDi
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * Copyright (c) 2002 Eric Moore
  28  * Copyright (c) 2002 LSI Logic Corporation
  29  * All rights reserved.
  30  *
  31  * Redistribution and use in source and binary forms, with or without
  32  * modification, are permitted provided that the following conditions
  33  * are met:
  34  * 1. Redistributions of source code must retain the above copyright
  35  *    notice, this list of conditions and the following disclaimer.
  36  * 2. Redistributions in binary form must reproduce the above copyright
  37  *    notice, this list of conditions and the following disclaimer in the
  38  *    documentation and/or other materials provided with the distribution.
  39  * 3. The party using or redistributing the source code and binary forms
  40  *    agrees to the disclaimer below and the terms and conditions set forth
  41  *    herein.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  47  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53  * SUCH DAMAGE.
  54  *
  55  *      $FreeBSD: src/sys/dev/amr/amrreg.h,v 1.1.2.4 2002/11/11 13:19:10 emoore Exp $
  56  *      $DragonFly: src/sys/dev/raid/amr/amrreg.h,v 1.2 2003/06/17 06:28:22 dillon Exp $
  57  */
  58
  59 /********************************************************************************
  60  ********************************************************************************
  61                                                                 Driver parameters
  62  ********************************************************************************
  63  ********************************************************************************/
  64
  65 /*
  66  * We could actually use all 17 segments, but using only 16 means that
  67  * each scatter/gather map is 128 bytes in size, and thus we don't have to worry about
  68  * maps crossing page boundaries.
  69  *
  70  * The AMI documentation says that the limit is 26.  Unfortunately, there's no way to
  71  * cleanly fit more than 16 entries in without a page boundary.  But is this a concern,
  72  * since we allocate the s/g maps contiguously anyway?
  73  */
  74 /*
  75  * emoore - Oct 21, 2002
  76  * firmware doesn't have sglist boundary restrictions.
  77  * The sgelem can be set to 26
  78  */
  79 #define AMR_NSEG                26
  80
  81 #define AMR_MAXCMD              255             /* ident = 0 not allowed */
  82 #define AMR_LIMITCMD            120             /* maximum count of outstanding commands */
  83 #define AMR_MAXLD               40
  84
  85 #define AMR_MAX_CHANNELS        4
  86 #define AMR_MAX_TARGETS         15
  87 #define AMR_MAX_LUNS            7
  88 #define AMR_MAX_SCSI_CMDS       (15 * AMR_MAX_CHANNELS) /* one for every target? */
  89
  90 #define AMR_MAX_CDB_LEN         0x0a
  91 #define AMR_MAX_EXTCDB_LEN      0x10
  92 #define AMR_MAX_REQ_SENSE_LEN   0x20
  93
  94 #define AMR_BLKSIZE             512             /* constant for all controllers */
  95
  96 /*
  97  * Perform at-startup board initialisation.
  98  * At this point in time, this code doesn't work correctly, so leave it disabled.
  99  */
 100 /*#define AMR_BOARD_INIT*/
 101
 102 /********************************************************************************
 103  ********************************************************************************
 104                                                           Interface Magic Numbers
 105  ********************************************************************************
 106  ********************************************************************************/
 107
 108 /*
 109  * Mailbox commands
 110  */
 111 #define AMR_CMD_LREAD           0x01
 112 #define AMR_CMD_LWRITE          0x02
 113 #define AMR_CMD_PASS            0x03
 114 #define AMR_CMD_EXT_ENQUIRY     0x04
 115 #define AMR_CMD_ENQUIRY         0x05
 116 #define AMR_CMD_FLUSH           0x0a
 117 #define AMR_CMD_EXT_ENQUIRY2    0x0c
 118 #define AMR_CONFIG_PRODINFO     0x0e
 119 #define AMR_CMD_GET_MACHINEID   0x36
 120 #define AMR_CMD_GET_INITIATOR   0x7d    /* returns one byte */
 121 #define AMR_CMD_CONFIG          0xa1
 122 #define AMR_CONFIG_PRODUCT_INFO         0x0e
 123 #define AMR_CONFIG_ENQ3                 0x0f
 124 #define AMR_CONFIG_ENQ3_SOLICITED_NOTIFY        0x01
 125 #define AMR_CONFIG_ENQ3_SOLICITED_FULL          0x02
 126 #define AMR_CONFIG_ENQ3_UNSOLICITED             0x03
 127 #define AMR_CMD_EXTPASS         0xe3
 128
 129 /*
 130  * Command results
 131  */
 132 #define AMR_STATUS_SUCCESS      0x00
 133 #define AMR_STATUS_ABORTED      0x02
 134 #define AMR_STATUS_FAILED       0x80
 135
 136 /*
 137  * Physical/logical drive states
 138  */
 139 #define AMR_DRV_CURSTATE(x)     ((x) & 0x0f)
 140 #define AMR_DRV_PREVSTATE(x)    (((x) >> 4) & 0x0f)
 141 #define AMR_DRV_OFFLINE         0x00
 142 #define AMR_DRV_DEGRADED        0x01
 143 #define AMR_DRV_OPTIMAL         0x02
 144 #define AMR_DRV_ONLINE          0x03
 145 #define AMR_DRV_FAILED          0x04
 146 #define AMR_DRV_REBUILD         0x05
 147 #define AMR_DRV_HOTSPARE        0x06
 148
 149 /*
 150  * Logical drive properties
 151  */
 152 #define AMR_DRV_RAID_MASK       0x0f    /* RAID level 0, 1, 3, 5, etc. */
 153 #define AMR_DRV_WRITEBACK       0x10    /* write-back enabled */
 154 #define AMR_DRV_READHEAD        0x20    /* readhead policy enabled */
 155 #define AMR_DRV_ADAPTIVE        0x40    /* adaptive I/O policy enabled */
 156
 157 /*
 158  * Battery status
 159  */
 160 #define AMR_BATT_MODULE_MISSING         0x01
 161 #define AMR_BATT_LOW_VOLTAGE            0x02
 162 #define AMR_BATT_TEMP_HIGH              0x04
 163 #define AMR_BATT_PACK_MISSING           0x08
 164 #define AMR_BATT_CHARGE_MASK            0x30
 165 #define AMR_BATT_CHARGE_DONE            0x00
 166 #define AMR_BATT_CHARGE_INPROG          0x10
 167 #define AMR_BATT_CHARGE_FAIL            0x20
 168 #define AMR_BATT_CYCLES_EXCEEDED        0x40
 169
 170
 171 /********************************************************************************
 172  ********************************************************************************
 173                                                            8LD Firmware Interface
 174  ********************************************************************************
 175  ********************************************************************************/
 176
 177 /*
 178  * Array constraints
 179  */
 180 #define AMR_8LD_MAXDRIVES       8
 181 #define AMR_8LD_MAXCHAN         5
 182 #define AMR_8LD_MAXTARG         15
 183 #define AMR_8LD_MAXPHYSDRIVES   (AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
 184
 185 /*
 186  * Adapter Info structure
 187  */
 188 struct amr_adapter_info
 189 {
 190     u_int8_t    aa_maxio;
 191     u_int8_t    aa_rebuild_rate;
 192     u_int8_t    aa_maxtargchan;
 193     u_int8_t    aa_channels;
 194     u_int8_t    aa_firmware[4];
 195     u_int16_t   aa_flashage;
 196     u_int8_t    aa_chipsetvalue;
 197     u_int8_t    aa_memorysize;
 198     u_int8_t    aa_cacheflush;
 199     u_int8_t    aa_bios[4];
 200     u_int8_t    aa_boardtype;
 201     u_int8_t    aa_scsisensealert;
 202     u_int8_t    aa_writeconfigcount;
 203     u_int8_t    aa_driveinsertioncount;
 204     u_int8_t    aa_inserteddrive;
 205     u_int8_t    aa_batterystatus;
 206     u_int8_t    res1;
 207 } __packed;
 208
 209 /*
 210  * Logical Drive info structure
 211  */
 212 struct amr_logdrive_info
 213 {
 214     u_int8_t    al_numdrives;
 215     u_int8_t    res1[3];
 216     u_int32_t   al_size[AMR_8LD_MAXDRIVES];
 217     u_int8_t    al_properties[AMR_8LD_MAXDRIVES];
 218     u_int8_t    al_state[AMR_8LD_MAXDRIVES];
 219 } __packed;
 220
 221 /*
 222  * Physical Drive info structure
 223  */
 224 struct amr_physdrive_info
 225 {
 226     u_int8_t    ap_state[AMR_8LD_MAXPHYSDRIVES];        /* low nibble current state, high nibble previous state */
 227     u_int8_t    ap_predictivefailure;
 228 } __packed;
 229
 230 /*
 231  * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and
 232  * AMR_CMD_EXT_ENQUIRY2.
 233  *                                                              ENQUIRY EXT_ENQUIRY EXT_ENQUIRY2
 234  */
 235 struct amr_enquiry
 236 {
 237     struct amr_adapter_info     ae_adapter;                     /* X      X             X */
 238     struct amr_logdrive_info    ae_ldrv;                        /* X      X             X */
 239     struct amr_physdrive_info   ae_pdrv;                        /* X      X             X */
 240     u_int8_t                    ae_formatting[AMR_8LD_MAXDRIVES];/*       X             X */
 241     u_int8_t                    res1[AMR_8LD_MAXDRIVES];        /*        X             X */
 242     u_int32_t                   ae_extlen;                      /*                      X */
 243     u_int16_t                   ae_subsystem;                   /*                      X */
 244     u_int16_t                   ae_subvendor;                   /*                      X */
 245     u_int32_t                   ae_signature;                   /*                      X */
 246 #define AMR_SIG_431     0xfffe0001
 247 #define AMR_SIG_438     0xfffd0002
 248 #define AMR_SIG_762     0xfffc0003
 249 #define AMR_SIG_T5      0xfffb0004
 250 #define AMR_SIG_466     0xfffa0005
 251 #define AMR_SIG_467     0xfff90006
 252 #define AMR_SIG_T7      0xfff80007
 253 #define AMR_SIG_490     0xfff70008
 254     u_int8_t                    res2[844];                      /*                      X */
 255 } __packed;
 256
 257
 258 /********************************************************************************
 259  ********************************************************************************
 260                                                           40LD Firmware Interface
 261  ********************************************************************************
 262  ********************************************************************************/
 263
 264 /*
 265  * Array constraints
 266  */
 267 #define AMR_40LD_MAXDRIVES      40
 268 #define AMR_40LD_MAXCHAN        16
 269 #define AMR_40LD_MAXTARG        16
 270 #define AMR_40LD_MAXPHYSDRIVES  256
 271
 272 /*
 273  * Product Info structure
 274  */
 275 struct amr_prodinfo
 276 {
 277     u_int32_t   ap_size;                /* current size in bytes (not including resvd) */
 278     u_int32_t   ap_configsig;           /* default is 0x00282008, indicating 0x28 maximum
 279                                          * logical drives, 0x20 maximum stripes and 0x08
 280                                          * maximum spans */
 281     u_int8_t    ap_firmware[16];        /* printable identifiers */
 282     u_int8_t    ap_bios[16];
 283     u_int8_t    ap_product[80];
 284     u_int8_t    ap_maxio;               /* maximum number of concurrent commands supported */
 285     u_int8_t    ap_nschan;              /* number of SCSI channels present */
 286     u_int8_t    ap_fcloops;             /* number of fibre loops present */
 287     u_int8_t    ap_memtype;             /* memory type */
 288     u_int32_t   ap_signature;
 289     u_int16_t   ap_memsize;             /* onboard memory in MB */
 290     u_int16_t   ap_subsystem;           /* subsystem identifier */
 291     u_int16_t   ap_subvendor;           /* subsystem vendor ID */
 292     u_int8_t    ap_numnotifyctr;        /* number of notify counters */
 293 } __packed;
 294
 295 /*
 296  * Notify structure
 297  */
 298 struct amr_notify
 299 {
 300     u_int32_t   an_globalcounter;       /* change counter */
 301
 302     u_int8_t    an_paramcounter;        /* parameter change counter */
 303     u_int8_t    an_paramid;
 304 #define AMR_PARAM_REBUILD_RATE          0x01    /* value = new rebuild rate */
 305 #define AMR_PARAM_FLUSH_INTERVAL        0x02    /* value = new flush interval */
 306 #define AMR_PARAM_SENSE_ALERT           0x03    /* value = last physical drive with check condition set */
 307 #define AMR_PARAM_DRIVE_INSERTED        0x04    /* value = last physical drive inserted */
 308 #define AMR_PARAM_BATTERY_STATUS        0x05    /* value = battery status */
 309     u_int16_t   an_paramval;
 310
 311     u_int8_t    an_writeconfigcounter;  /* write config occurred */
 312     u_int8_t    res1[3];
 313
 314     u_int8_t    an_ldrvopcounter;       /* logical drive operation started/completed */
 315     u_int8_t    an_ldrvopid;
 316     u_int8_t    an_ldrvopcmd;
 317 #define AMR_LDRVOP_CHECK        0x01
 318 #define AMR_LDRVOP_INIT         0x02
 319 #define AMR_LDRVOP_REBUILD      0x03
 320     u_int8_t    an_ldrvopstatus;
 321 #define AMR_LDRVOP_SUCCESS      0x00
 322 #define AMR_LDRVOP_FAILED       0x01
 323 #define AMR_LDRVOP_ABORTED      0x02
 324 #define AMR_LDRVOP_CORRECTED    0x03
 325 #define AMR_LDRVOP_STARTED      0x04
 326
 327     u_int8_t    an_ldrvstatecounter;    /* logical drive state change occurred */
 328     u_int8_t    an_ldrvstateid;
 329     u_int8_t    an_ldrvstatenew;
 330     u_int8_t    an_ldrvstateold;
 331
 332     u_int8_t    an_pdrvstatecounter;    /* physical drive state change occurred */
 333     u_int8_t    an_pdrvstateid;
 334     u_int8_t    an_pdrvstatenew;
 335     u_int8_t    an_pdrvstateold;
 336
 337     u_int8_t    an_pdrvfmtcounter;
 338     u_int8_t    an_pdrvfmtid;
 339     u_int8_t    an_pdrvfmtval;
 340 #define AMR_FORMAT_START        0x01
 341 #define AMR_FORMAT_COMPLETE     0x02
 342     u_int8_t    res2;
 343
 344     u_int8_t    an_targxfercounter;     /* scsi xfer rate change */
 345     u_int8_t    an_targxferid;
 346     u_int8_t    an_targxferval;
 347     u_int8_t    res3;
 348
 349     u_int8_t    an_fcloopidcounter;     /* FC/AL loop ID changed */
 350     u_int8_t    an_fcloopidpdrvid;
 351     u_int8_t    an_fcloopid0;
 352     u_int8_t    an_fcloopid1;
 353
 354     u_int8_t    an_fcloopstatecounter;  /* FC/AL loop status changed */
 355     u_int8_t    an_fcloopstate0;
 356     u_int8_t    an_fcloopstate1;
 357     u_int8_t    res4;
 358 } __packed;
 359
 360 /*
 361  * Enquiry3 structure
 362  */
 363 struct amr_enquiry3
 364 {
 365     u_int32_t   ae_datasize;            /* valid data size in this structure */
 366     union {                             /* event notify structure */
 367         struct amr_notify       n;
 368         u_int8_t                pad[0x80];
 369     }           ae_notify;
 370     u_int8_t    ae_rebuildrate;         /* current rebuild rate in % */
 371     u_int8_t    ae_cacheflush;          /* flush interval in seconds */
 372     u_int8_t    ae_sensealert;
 373     u_int8_t    ae_driveinsertcount;    /* count of inserted drives */
 374     u_int8_t    ae_batterystatus;
 375     u_int8_t    ae_numldrives;
 376     u_int8_t    ae_reconstate[AMR_40LD_MAXDRIVES / 8];  /* reconstruction state */
 377     u_int16_t   ae_opstatus[AMR_40LD_MAXDRIVES / 8];    /* operation status per drive */
 378     u_int32_t   ae_drivesize[AMR_40LD_MAXDRIVES];       /* logical drive size */
 379     u_int8_t    ae_driveprop[AMR_40LD_MAXDRIVES];       /* logical drive properties */
 380     u_int8_t    ae_drivestate[AMR_40LD_MAXDRIVES];      /* physical drive state */
 381     u_int16_t   ae_driveformat[AMR_40LD_MAXPHYSDRIVES];
 382     u_int8_t    ae_targxfer[80];                        /* physical drive transfer rates */
 383
 384     u_int8_t    res1[263];              /* pad to 1024 bytes */
 385 } __packed;
 386
 387
 388 /********************************************************************************
 389  ********************************************************************************
 390                                                    Mailbox and Command Structures
 391  ********************************************************************************
 392  ********************************************************************************/
 393
 394 #define AMR_MBOX_CMDSIZE        0x10    /* portion worth copying for controller */
 395
 396 struct amr_mailbox
 397 {
 398     u_int8_t    mb_command;
 399     u_int8_t    mb_ident;
 400     u_int16_t   mb_blkcount;
 401     u_int32_t   mb_lba;
 402     u_int32_t   mb_physaddr;
 403     u_int8_t    mb_drive;
 404     u_int8_t    mb_nsgelem;
 405     u_int8_t    res1;
 406     u_int8_t    mb_busy;
 407     u_int8_t    mb_nstatus;
 408     u_int8_t    mb_status;
 409     u_int8_t    mb_completed[46];
 410     u_int8_t    mb_poll;
 411     u_int8_t    mb_ack;
 412     u_int8_t    res2[16];
 413 } __packed;
 414
 415 struct amr_mailbox64
 416 {
 417     u_int32_t           mb64_segment;   /* for 64-bit controllers */
 418     struct amr_mailbox  mb;
 419 } __packed;
 420
 421 struct amr_mailbox_ioctl
 422 {
 423     u_int8_t    mb_command;
 424     u_int8_t    mb_ident;
 425     u_int8_t    mb_channel;
 426     u_int8_t    mb_param;
 427     u_int8_t    mb_pad[4];
 428     u_int32_t   mb_physaddr;
 429     u_int8_t    mb_drive;
 430     u_int8_t    mb_nsgelem;
 431     u_int8_t    res1;
 432     u_int8_t    mb_busy;
 433     u_int8_t    mb_nstatus;
 434     u_int8_t    mb_completed[46];
 435     u_int8_t    mb_poll;
 436     u_int8_t    mb_ack;
 437     u_int8_t    res4[16];
 438 } __packed;
 439
 440 struct amr_sgentry
 441 {
 442     u_int32_t   sg_addr;
 443     u_int32_t   sg_count;
 444 } __packed;
 445
 446 struct amr_passthrough
 447 {
 448     u_int8_t    ap_timeout:3;
 449     u_int8_t    ap_ars:1;
 450     u_int8_t    ap_dummy:3;
 451     u_int8_t    ap_islogical:1;
 452     u_int8_t    ap_logical_drive_no;
 453     u_int8_t    ap_channel;
 454     u_int8_t    ap_scsi_id;
 455     u_int8_t    ap_queue_tag;
 456     u_int8_t    ap_queue_action;
 457     u_int8_t    ap_cdb[AMR_MAX_CDB_LEN];
 458     u_int8_t    ap_cdb_length;
 459     u_int8_t    ap_request_sense_length;
 460     u_int8_t    ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
 461     u_int8_t    ap_no_sg_elements;
 462     u_int8_t    ap_scsi_status;
 463     u_int32_t   ap_data_transfer_address;
 464     u_int32_t   ap_data_transfer_length;
 465 } __packed;
 466
 467 struct amr_ext_passthrough
 468 {
 469     u_int8_t    ap_timeout:3;
 470     u_int8_t    ap_ars:1;
 471     u_int8_t    ap_rsvd1:1;
 472     u_int8_t    ap_cd_rom:1;
 473     u_int8_t    ap_rsvd2:1;
 474     u_int8_t    ap_islogical:1;
 475     u_int8_t    ap_logical_drive_no;
 476     u_int8_t    ap_channel;
 477     u_int8_t    ap_scsi_id;
 478     u_int8_t    ap_queue_tag;
 479     u_int8_t    ap_queue_action;
 480     u_int8_t    ap_cdb_length;
 481     u_int8_t    ap_rsvd3;
 482     u_int8_t    ap_cdb[AMR_MAX_EXTCDB_LEN];
 483     u_int8_t    ap_no_sg_elements;
 484     u_int8_t    ap_scsi_status;
 485     u_int8_t    ap_request_sense_length;
 486     u_int8_t    ap_request_sense_area[AMR_MAX_REQ_SENSE_LEN];
 487     u_int8_t    ap_rsvd4;
 488     u_int32_t   ap_data_transfer_address;
 489     u_int32_t   ap_data_transfer_length;
 490 } __packed;
 491
 492 #ifdef _KERNEL
 493 /********************************************************************************
 494  ********************************************************************************
 495                                                "Quartz" i960 PCI bridge interface
 496  ********************************************************************************
 497  ********************************************************************************/
 498
 499 #define AMR_CFG_SIG             0xa0            /* PCI config register for signature */
 500 #define AMR_SIGNATURE_1         0xCCCC          /* i960 signature (older adapters) */
 501 #define AMR_SIGNATURE_2         0x3344          /* i960 signature (newer adapters) */
 502
 503 /*
 504  * Doorbell registers
 505  */
 506 #define AMR_QIDB                0x20
 507 #define AMR_QODB                0x2c
 508 #define AMR_QIDB_SUBMIT         0x00000001      /* mailbox ready for work */
 509 #define AMR_QIDB_ACK            0x00000002      /* mailbox done */
 510 #define AMR_QODB_READY          0x10001234      /* work ready to be processed */
 511
 512 /*
 513  * Initialisation status
 514  */
 515 #define AMR_QINIT_SCAN          0x01    /* init scanning drives */
 516 #define AMR_QINIT_SCANINIT      0x02    /* init scanning initialising */
 517 #define AMR_QINIT_FIRMWARE      0x03    /* init firmware initing */
 518 #define AMR_QINIT_INPROG        0xdc    /* init in progress */
 519 #define AMR_QINIT_SPINUP        0x2c    /* init spinning drives */
 520 #define AMR_QINIT_NOMEM         0xac    /* insufficient memory */
 521 #define AMR_QINIT_CACHEFLUSH    0xbc    /* init flushing cache */
 522 #define AMR_QINIT_DONE          0x9c    /* init successfully done */
 523
 524 /*
 525  * I/O primitives
 526  */
 527 #define AMR_QPUT_IDB(sc, val)   bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QIDB, val)
 528 #define AMR_QGET_IDB(sc)        bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QIDB)
 529 #define AMR_QPUT_ODB(sc, val)   bus_space_write_4(sc->amr_btag, sc->amr_bhandle, AMR_QODB, val)
 530 #define AMR_QGET_ODB(sc)        bus_space_read_4 (sc->amr_btag, sc->amr_bhandle, AMR_QODB)
 531
 532 #ifdef AMR_BOARD_INIT
 533 #define AMR_QRESET(sc)                                                                                  \
 534         do {                                                                                            \
 535             pci_write_config((sc)->amr_dev, 0x40, pci_read_config((sc)->amr_dev, 0x40, 1) | 0x20, 1);   \
 536             pci_write_config((sc)->amr_dev, 0x64, 0x1122, 1);                                           \
 537         } while (0)
 538 #define AMR_QGET_INITSTATUS(sc) pci_read_config((sc)->amr_dev, 0x9c, 1)
 539 #define AMR_QGET_INITCHAN(sc)   pci_read_config((sc)->amr_dev, 0x9f, 1)
 540 #define AMR_QGET_INITTARG(sc)   pci_read_config((sc)->amr_dev, 0x9e, 1)
 541 #endif
 542
 543 /********************************************************************************
 544  ********************************************************************************
 545                                        "Standard" old-style ASIC bridge interface
 546  ********************************************************************************
 547  ********************************************************************************/
 548
 549 /*
 550  * I/O registers
 551  */
 552 #define AMR_SCMD                0x10    /* command/ack register (write) */
 553 #define AMR_SMBOX_BUSY          0x10    /* mailbox status (read) */
 554 #define AMR_STOGGLE             0x11    /* interrupt enable bit here */
 555 #define AMR_SMBOX_0             0x14    /* mailbox physical address low byte */
 556 #define AMR_SMBOX_1             0x15
 557 #define AMR_SMBOX_2             0x16
 558 #define AMR_SMBOX_3             0x17    /*                          high byte */
 559 #define AMR_SMBOX_ENABLE        0x18    /* atomic mailbox address enable */
 560 #define AMR_SINTR               0x1a    /* interrupt status */
 561
 562 /*
 563  * I/O magic numbers
 564  */
 565 #define AMR_SCMD_POST           0x10    /* -> SCMD to initiate action on mailbox */
 566 #define AMR_SCMD_ACKINTR        0x08    /* -> SCMD to ack mailbox retrieved */
 567 #define AMR_STOGL_IENABLE       0xc0    /* in STOGGLE */
 568 #define AMR_SINTR_VALID         0x40    /* in SINTR */
 569 #define AMR_SMBOX_BUSYFLAG      0x10    /* in SMBOX_BUSY */
 570 #define AMR_SMBOX_ADDR          0x00    /* -> SMBOX_ENABLE */
 571
 572 /*
 573  * Initialisation status
 574  */
 575 #define AMR_SINIT_ABEND         0xee    /* init abnormal terminated */
 576 #define AMR_SINIT_NOMEM         0xca    /* insufficient memory */
 577 #define AMR_SINIT_CACHEFLUSH    0xbb    /* firmware flushing cache */
 578 #define AMR_SINIT_INPROG        0x11    /* init in progress */
 579 #define AMR_SINIT_SPINUP        0x22    /* firmware spinning drives */
 580 #define AMR_SINIT_DONE          0x99    /* init successfully done */
 581
 582 /*
 583  * I/O primitives
 584  */
 585 #define AMR_SPUT_ISTAT(sc, val) bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SINTR, val)
 586 #define AMR_SGET_ISTAT(sc)      bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SINTR)
 587 #define AMR_SACK_INTERRUPT(sc)  bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_ACKINTR)
 588 #define AMR_SPOST_COMMAND(sc)   bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_SCMD, AMR_SCMD_POST)
 589 #define AMR_SGET_MBSTAT(sc)     bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_BUSY)
 590 #define AMR_SENABLE_INTR(sc)                                                                                    \
 591         bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE,                                           \
 592                           bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) | AMR_STOGL_IENABLE)
 593 #define AMR_SDISABLE_INTR(sc)                                                                                   \
 594         bus_space_write_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE,                                           \
 595                           bus_space_read_1(sc->amr_btag, sc->amr_bhandle, AMR_STOGGLE) & ~AMR_STOGL_IENABLE)
 596 #define AMR_SBYTE_SET(sc, reg, val)     bus_space_write_1(sc->amr_btag, sc->amr_bhandle, reg, val)
 597
 598 #ifdef AMR_BOARD_INIT
 599 #define AMR_SRESET(sc)          bus_space_write_1(sc->amr_btag, sc->amr_bhandle, 0, 0x80)
 600 #define AMR_SGET_INITSTATUS(sc) bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE)
 601 #define AMR_SGET_FAILDRIVE(sc)  bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 1)
 602 #define AMR_SGET_INITCHAN(sc)   bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 2)
 603 #define AMR_SGET_INITTARG(sc)   bus_space_read_1 (sc->amr_btag, sc->amr_bhandle, AMR_SMBOX_ENABLE + 3)
 604 #endif
 605
 606 #endif /* _KERNEL */