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Add sysctl/tunable for TX/RX interrupt coalescing variables. Default
[dragonfly/vkernel-mp.git] / sys / dev / netif / bge / if_bge.c
blob0c9bd6a6d9654ac7b0882e3323224f4165999779
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.81 2007/06/19 14:59:41 sephe Exp $
35 *
36 */
37
38 /*
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 *
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
43 */
44
45 /*
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
56 * into the driver.
57 *
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
60 *
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
64 *
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
67 *
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
72 * ring.
73 */
74
75 #include "opt_polling.h"
76 #include <sys/param.h>
77 #include <sys/bus.h>
78 #include <sys/endian.h>
79 #include <sys/kernel.h>
80 #include <sys/mbuf.h>
81 #include <sys/malloc.h>
82 #include <sys/queue.h>
83 #include <sys/rman.h>
84 #include <sys/serialize.h>
85 #include <sys/socket.h>
86 #include <sys/sockio.h>
87 #include <sys/sysctl.h>
88
89 #include <net/bpf.h>
90 #include <net/ethernet.h>
91 #include <net/if.h>
92 #include <net/if_arp.h>
93 #include <net/if_dl.h>
94 #include <net/if_media.h>
95 #include <net/if_types.h>
96 #include <net/ifq_var.h>
97 #include <net/vlan/if_vlan_var.h>
98
99 #include <dev/netif/mii_layer/mii.h>
100 #include <dev/netif/mii_layer/miivar.h>
101 #include <dev/netif/mii_layer/brgphyreg.h>
102
103 #include <bus/pci/pcidevs.h>
104 #include <bus/pci/pcireg.h>
105 #include <bus/pci/pcivar.h>
106
107 #include <dev/netif/bge/if_bgereg.h>
108
109 /* "device miibus" required. See GENERIC if you get errors here. */
110 #include "miibus_if.h"
111
112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
113 #define BGE_MIN_FRAME 60
114
115 /*
116 * Various supported device vendors/types and their names. Note: the
117 * spec seems to indicate that the hardware still has Alteon's vendor
118 * ID burned into it, though it will always be overriden by the vendor
119 * ID in the EEPROM. Just to be safe, we cover all possibilities.
120 */
121 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
122
123 static struct bge_type bge_devs[] = {
124 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
125 "3COM 3C996 Gigabit Ethernet" },
126
127 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
128 "Alteon BCM5700 Gigabit Ethernet" },
129 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
130 "Alteon BCM5701 Gigabit Ethernet" },
131
132 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
133 "Altima AC1000 Gigabit Ethernet" },
134 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
135 "Altima AC1002 Gigabit Ethernet" },
136 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
137 "Altima AC9100 Gigabit Ethernet" },
138
139 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
140 "Apple BCM5701 Gigabit Ethernet" },
141
142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
143 "Broadcom BCM5700 Gigabit Ethernet" },
144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
145 "Broadcom BCM5701 Gigabit Ethernet" },
146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
147 "Broadcom BCM5702 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
149 "Broadcom BCM5702X Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
151 "Broadcom BCM5702 Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
153 "Broadcom BCM5703 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
155 "Broadcom BCM5703X Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
157 "Broadcom BCM5703 Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
159 "Broadcom BCM5704C Dual Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
161 "Broadcom BCM5704S Dual Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
163 "Broadcom BCM5704S Dual Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
165 "Broadcom BCM5705 Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
167 "Broadcom BCM5705F Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
169 "Broadcom BCM5705K Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
171 "Broadcom BCM5705M Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
173 "Broadcom BCM5705M Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
175 "Broadcom BCM5714C Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
177 "Broadcom BCM5714S Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
179 "Broadcom BCM5715 Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
181 "Broadcom BCM5715S Gigabit Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
183 "Broadcom BCM5720 Gigabit Ethernet" },
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
185 "Broadcom BCM5721 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
187 "Broadcom BCM5722 Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
189 "Broadcom BCM5750 Gigabit Ethernet" },
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
191 "Broadcom BCM5750M Gigabit Ethernet" },
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
193 "Broadcom BCM5751 Gigabit Ethernet" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
195 "Broadcom BCM5751F Gigabit Ethernet" },
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
197 "Broadcom BCM5751M Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
199 "Broadcom BCM5752 Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
201 "Broadcom BCM5752M Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
203 "Broadcom BCM5753 Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
205 "Broadcom BCM5753F Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
207 "Broadcom BCM5753M Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
209 "Broadcom BCM5754 Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
211 "Broadcom BCM5754M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
213 "Broadcom BCM5755 Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
215 "Broadcom BCM5755M Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
217 "Broadcom BCM5756 Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
219 "Broadcom BCM5780 Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
221 "Broadcom BCM5780S Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
223 "Broadcom BCM5781 Gigabit Ethernet" },
224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
225 "Broadcom BCM5782 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
227 "Broadcom BCM5786 Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
229 "Broadcom BCM5787 Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
231 "Broadcom BCM5787F Gigabit Ethernet" },
232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
233 "Broadcom BCM5787M Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
235 "Broadcom BCM5788 Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
237 "Broadcom BCM5789 Gigabit Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
239 "Broadcom BCM5901 Fast Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
241 "Broadcom BCM5901A2 Fast Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
243 "Broadcom BCM5903M Fast Ethernet" },
244
245 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
246 "SysKonnect Gigabit Ethernet" },
247
248 { 0, 0, NULL }
249 };
250
251 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
252 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
253 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
254 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
255 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
256
257 static int bge_probe(device_t);
258 static int bge_attach(device_t);
259 static int bge_detach(device_t);
260 static void bge_txeof(struct bge_softc *);
261 static void bge_rxeof(struct bge_softc *);
262
263 static void bge_tick(void *);
264 static void bge_stats_update(struct bge_softc *);
265 static void bge_stats_update_regs(struct bge_softc *);
266 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
267
268 #ifdef DEVICE_POLLING
269 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
270 #endif
271 static void bge_intr(void *);
272 static void bge_start(struct ifnet *);
273 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
274 static void bge_init(void *);
275 static void bge_stop(struct bge_softc *);
276 static void bge_watchdog(struct ifnet *);
277 static void bge_shutdown(device_t);
278 static int bge_suspend(device_t);
279 static int bge_resume(device_t);
280 static int bge_ifmedia_upd(struct ifnet *);
281 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
282
283 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
284 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
285
286 static void bge_setmulti(struct bge_softc *);
287 static void bge_setpromisc(struct bge_softc *);
288
289 static int bge_alloc_jumbo_mem(struct bge_softc *);
290 static void bge_free_jumbo_mem(struct bge_softc *);
291 static struct bge_jslot
292 *bge_jalloc(struct bge_softc *);
293 static void bge_jfree(void *);
294 static void bge_jref(void *);
295 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
296 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
297 static int bge_init_rx_ring_std(struct bge_softc *);
298 static void bge_free_rx_ring_std(struct bge_softc *);
299 static int bge_init_rx_ring_jumbo(struct bge_softc *);
300 static void bge_free_rx_ring_jumbo(struct bge_softc *);
301 static void bge_free_tx_ring(struct bge_softc *);
302 static int bge_init_tx_ring(struct bge_softc *);
303
304 static int bge_chipinit(struct bge_softc *);
305 static int bge_blockinit(struct bge_softc *);
306
307 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
308 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
309 #ifdef notdef
310 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
311 #endif
312 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
313 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
314
315 static int bge_miibus_readreg(device_t, int, int);
316 static int bge_miibus_writereg(device_t, int, int, int);
317 static void bge_miibus_statchg(device_t);
318 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
319 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
320 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
321
322 static void bge_reset(struct bge_softc *);
323
324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
325 static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
326 bus_size_t, int);
327 static int bge_dma_alloc(struct bge_softc *);
328 static void bge_dma_free(struct bge_softc *);
329 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
330 bus_dma_tag_t *, bus_dmamap_t *,
331 void **, bus_addr_t *);
332 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
333
334 static void bge_coal_change(struct bge_softc *);
335 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
336 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
337 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
338 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
339 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
340
341 /*
342 * Set following tunable to 1 for some IBM blade servers with the DNLK
343 * switch module. Auto negotiation is broken for those configurations.
344 */
345 static int bge_fake_autoneg = 0;
346 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
347
348 /* Interrupt moderation control variables. */
349 static int bge_rx_coal_ticks = 150; /* usec */
350 static int bge_tx_coal_ticks = 1000000; /* usec */
351 static int bge_rx_max_coal_bds = 16;
352 static int bge_tx_max_coal_bds = 32;
353
354 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
355 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
356 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
357 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
358
359 static device_method_t bge_methods[] = {
360 /* Device interface */
361 DEVMETHOD(device_probe, bge_probe),
362 DEVMETHOD(device_attach, bge_attach),
363 DEVMETHOD(device_detach, bge_detach),
364 DEVMETHOD(device_shutdown, bge_shutdown),
365 DEVMETHOD(device_suspend, bge_suspend),
366 DEVMETHOD(device_resume, bge_resume),
367
368 /* bus interface */
369 DEVMETHOD(bus_print_child, bus_generic_print_child),
370 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
371
372 /* MII interface */
373 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
374 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
375 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
376
377 { 0, 0 }
378 };
379
380 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
381 static devclass_t bge_devclass;
382
383 DECLARE_DUMMY_MODULE(if_bge);
384 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
385 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
386
387 static uint32_t
388 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
389 {
390 device_t dev = sc->bge_dev;
391 uint32_t val;
392
393 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
394 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
395 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
396 return (val);
397 }
398
399 static void
400 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
401 {
402 device_t dev = sc->bge_dev;
403
404 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
405 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
406 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
407 }
408
409 #ifdef notdef
410 static uint32_t
411 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
412 {
413 device_t dev = sc->bge_dev;
414
415 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
416 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
417 }
418 #endif
419
420 static void
421 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
422 {
423 device_t dev = sc->bge_dev;
424
425 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
426 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
427 }
428
429 static void
430 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
431 {
432 CSR_WRITE_4(sc, off, val);
433 }
434
435 /*
436 * Read a byte of data stored in the EEPROM at address 'addr.' The
437 * BCM570x supports both the traditional bitbang interface and an
438 * auto access interface for reading the EEPROM. We use the auto
439 * access method.
440 */
441 static uint8_t
442 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
443 {
444 int i;
445 uint32_t byte = 0;
446
447 /*
448 * Enable use of auto EEPROM access so we can avoid
449 * having to use the bitbang method.
450 */
451 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
452
453 /* Reset the EEPROM, load the clock period. */
454 CSR_WRITE_4(sc, BGE_EE_ADDR,
455 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
456 DELAY(20);
457
458 /* Issue the read EEPROM command. */
459 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
460
461 /* Wait for completion */
462 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
463 DELAY(10);
464 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
465 break;
466 }
467
468 if (i == BGE_TIMEOUT) {
469 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
470 return(1);
471 }
472
473 /* Get result. */
474 byte = CSR_READ_4(sc, BGE_EE_DATA);
475
476 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
477
478 return(0);
479 }
480
481 /*
482 * Read a sequence of bytes from the EEPROM.
483 */
484 static int
485 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
486 {
487 size_t i;
488 int err;
489 uint8_t byte;
490
491 for (byte = 0, err = 0, i = 0; i < len; i++) {
492 err = bge_eeprom_getbyte(sc, off + i, &byte);
493 if (err)
494 break;
495 *(dest + i) = byte;
496 }
497
498 return(err ? 1 : 0);
499 }
500
501 static int
502 bge_miibus_readreg(device_t dev, int phy, int reg)
503 {
504 struct bge_softc *sc;
505 struct ifnet *ifp;
506 uint32_t val, autopoll;
507 int i;
508
509 sc = device_get_softc(dev);
510 ifp = &sc->arpcom.ac_if;
511
512 /*
513 * Broadcom's own driver always assumes the internal
514 * PHY is at GMII address 1. On some chips, the PHY responds
515 * to accesses at all addresses, which could cause us to
516 * bogusly attach the PHY 32 times at probe type. Always
517 * restricting the lookup to address 1 is simpler than
518 * trying to figure out which chips revisions should be
519 * special-cased.
520 */
521 if (phy != 1)
522 return(0);
523
524 /* Reading with autopolling on may trigger PCI errors */
525 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
526 if (autopoll & BGE_MIMODE_AUTOPOLL) {
527 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
528 DELAY(40);
529 }
530
531 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
532 BGE_MIPHY(phy)|BGE_MIREG(reg));
533
534 for (i = 0; i < BGE_TIMEOUT; i++) {
535 val = CSR_READ_4(sc, BGE_MI_COMM);
536 if (!(val & BGE_MICOMM_BUSY))
537 break;
538 }
539
540 if (i == BGE_TIMEOUT) {
541 if_printf(ifp, "PHY read timed out\n");
542 val = 0;
543 goto done;
544 }
545
546 val = CSR_READ_4(sc, BGE_MI_COMM);
547
548 done:
549 if (autopoll & BGE_MIMODE_AUTOPOLL) {
550 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
551 DELAY(40);
552 }
553
554 if (val & BGE_MICOMM_READFAIL)
555 return(0);
556
557 return(val & 0xFFFF);
558 }
559
560 static int
561 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
562 {
563 struct bge_softc *sc;
564 uint32_t autopoll;
565 int i;
566
567 sc = device_get_softc(dev);
568
569 /* Reading with autopolling on may trigger PCI errors */
570 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
571 if (autopoll & BGE_MIMODE_AUTOPOLL) {
572 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
573 DELAY(40);
574 }
575
576 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
577 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
578
579 for (i = 0; i < BGE_TIMEOUT; i++) {
580 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
581 break;
582 }
583
584 if (autopoll & BGE_MIMODE_AUTOPOLL) {
585 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
586 DELAY(40);
587 }
588
589 if (i == BGE_TIMEOUT) {
590 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
591 return(0);
592 }
593
594 return(0);
595 }
596
597 static void
598 bge_miibus_statchg(device_t dev)
599 {
600 struct bge_softc *sc;
601 struct mii_data *mii;
602
603 sc = device_get_softc(dev);
604 mii = device_get_softc(sc->bge_miibus);
605
606 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
607 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
608 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
609 } else {
610 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
611 }
612
613 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
614 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
615 } else {
616 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
617 }
618 }
619
620 /*
621 * Memory management for jumbo frames.
622 */
623 static int
624 bge_alloc_jumbo_mem(struct bge_softc *sc)
625 {
626 struct ifnet *ifp = &sc->arpcom.ac_if;
627 struct bge_jslot *entry;
628 uint8_t *ptr;
629 bus_addr_t paddr;
630 int i, error;
631
632 /*
633 * Create tag for jumbo mbufs.
634 * This is really a bit of a kludge. We allocate a special
635 * jumbo buffer pool which (thanks to the way our DMA
636 * memory allocation works) will consist of contiguous
637 * pages. This means that even though a jumbo buffer might
638 * be larger than a page size, we don't really need to
639 * map it into more than one DMA segment. However, the
640 * default mbuf tag will result in multi-segment mappings,
641 * so we have to create a special jumbo mbuf tag that
642 * lets us get away with mapping the jumbo buffers as
643 * a single segment. I think eventually the driver should
644 * be changed so that it uses ordinary mbufs and cluster
645 * buffers, i.e. jumbo frames can span multiple DMA
646 * descriptors. But that's a project for another day.
647 */
648
649 /*
650 * Create DMA stuffs for jumbo RX ring.
651 */
652 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
653 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
654 &sc->bge_cdata.bge_rx_jumbo_ring_map,
655 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
656 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
657 if (error) {
658 if_printf(ifp, "could not create jumbo RX ring\n");
659 return error;
660 }
661
662 /*
663 * Create DMA stuffs for jumbo buffer block.
664 */
665 error = bge_dma_block_alloc(sc, BGE_JMEM,
666 &sc->bge_cdata.bge_jumbo_tag,
667 &sc->bge_cdata.bge_jumbo_map,
668 (void **)&sc->bge_ldata.bge_jumbo_buf,
669 &paddr);
670 if (error) {
671 if_printf(ifp, "could not create jumbo buffer\n");
672 return error;
673 }
674
675 SLIST_INIT(&sc->bge_jfree_listhead);
676
677 /*
678 * Now divide it up into 9K pieces and save the addresses
679 * in an array. Note that we play an evil trick here by using
680 * the first few bytes in the buffer to hold the the address
681 * of the softc structure for this interface. This is because
682 * bge_jfree() needs it, but it is called by the mbuf management
683 * code which will not pass it to us explicitly.
684 */
685 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
686 entry = &sc->bge_cdata.bge_jslots[i];
687 entry->bge_sc = sc;
688 entry->bge_buf = ptr;
689 entry->bge_paddr = paddr;
690 entry->bge_inuse = 0;
691 entry->bge_slot = i;
692 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
693
694 ptr += BGE_JLEN;
695 paddr += BGE_JLEN;
696 }
697 return 0;
698 }
699
700 static void
701 bge_free_jumbo_mem(struct bge_softc *sc)
702 {
703 /* Destroy jumbo RX ring. */
704 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
705 sc->bge_cdata.bge_rx_jumbo_ring_map,
706 sc->bge_ldata.bge_rx_jumbo_ring);
707
708 /* Destroy jumbo buffer block. */
709 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
710 sc->bge_cdata.bge_jumbo_map,
711 sc->bge_ldata.bge_jumbo_buf);
712 }
713
714 /*
715 * Allocate a jumbo buffer.
716 */
717 static struct bge_jslot *
718 bge_jalloc(struct bge_softc *sc)
719 {
720 struct bge_jslot *entry;
721
722 lwkt_serialize_enter(&sc->bge_jslot_serializer);
723 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
724 if (entry) {
725 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
726 entry->bge_inuse = 1;
727 } else {
728 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
729 }
730 lwkt_serialize_exit(&sc->bge_jslot_serializer);
731 return(entry);
732 }
733
734 /*
735 * Adjust usage count on a jumbo buffer.
736 */
737 static void
738 bge_jref(void *arg)
739 {
740 struct bge_jslot *entry = (struct bge_jslot *)arg;
741 struct bge_softc *sc = entry->bge_sc;
742
743 if (sc == NULL)
744 panic("bge_jref: can't find softc pointer!");
745
746 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
747 panic("bge_jref: asked to reference buffer "
748 "that we don't manage!");
749 } else if (entry->bge_inuse == 0) {
750 panic("bge_jref: buffer already free!");
751 } else {
752 atomic_add_int(&entry->bge_inuse, 1);
753 }
754 }
755
756 /*
757 * Release a jumbo buffer.
758 */
759 static void
760 bge_jfree(void *arg)
761 {
762 struct bge_jslot *entry = (struct bge_jslot *)arg;
763 struct bge_softc *sc = entry->bge_sc;
764
765 if (sc == NULL)
766 panic("bge_jfree: can't find softc pointer!");
767
768 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
769 panic("bge_jfree: asked to free buffer that we don't manage!");
770 } else if (entry->bge_inuse == 0) {
771 panic("bge_jfree: buffer already free!");
772 } else {
773 /*
774 * Possible MP race to 0, use the serializer. The atomic insn
775 * is still needed for races against bge_jref().
776 */
777 lwkt_serialize_enter(&sc->bge_jslot_serializer);
778 atomic_subtract_int(&entry->bge_inuse, 1);
779 if (entry->bge_inuse == 0) {
780 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
781 entry, jslot_link);
782 }
783 lwkt_serialize_exit(&sc->bge_jslot_serializer);
784 }
785 }
786
787
788 /*
789 * Intialize a standard receive ring descriptor.
790 */
791 static int
792 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
793 {
794 struct mbuf *m_new = NULL;
795 struct bge_dmamap_arg ctx;
796 bus_dma_segment_t seg;
797 struct bge_rx_bd *r;
798 int error;
799
800 if (m == NULL) {
801 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
802 if (m_new == NULL)
803 return ENOBUFS;
804 } else {
805 m_new = m;
806 m_new->m_data = m_new->m_ext.ext_buf;
807 }
808 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
809
810 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
811 m_adj(m_new, ETHER_ALIGN);
812
813 ctx.bge_maxsegs = 1;
814 ctx.bge_segs = &seg;
815 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
816 sc->bge_cdata.bge_rx_std_dmamap[i],
817 m_new, bge_dma_map_mbuf, &ctx,
818 BUS_DMA_NOWAIT);
819 if (error || ctx.bge_maxsegs == 0) {
820 if (m == NULL)
821 m_freem(m_new);
822 return ENOMEM;
823 }
824
825 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
826
827 r = &sc->bge_ldata.bge_rx_std_ring[i];
828 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
829 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
830 r->bge_flags = BGE_RXBDFLAG_END;
831 r->bge_len = m_new->m_len;
832 r->bge_idx = i;
833
834 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
835 sc->bge_cdata.bge_rx_std_dmamap[i],
836 BUS_DMASYNC_PREREAD);
837 return 0;
838 }
839
840 /*
841 * Initialize a jumbo receive ring descriptor. This allocates
842 * a jumbo buffer from the pool managed internally by the driver.
843 */
844 static int
845 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
846 {
847 struct mbuf *m_new = NULL;
848 struct bge_jslot *buf;
849 struct bge_rx_bd *r;
850 bus_addr_t paddr;
851
852 if (m == NULL) {
853 /* Allocate the mbuf. */
854 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
855 if (m_new == NULL)
856 return(ENOBUFS);
857
858 /* Allocate the jumbo buffer */
859 buf = bge_jalloc(sc);
860 if (buf == NULL) {
861 m_freem(m_new);
862 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
863 "-- packet dropped!\n");
864 return ENOBUFS;
865 }
866
867 /* Attach the buffer to the mbuf. */
868 m_new->m_ext.ext_arg = buf;
869 m_new->m_ext.ext_buf = buf->bge_buf;
870 m_new->m_ext.ext_free = bge_jfree;
871 m_new->m_ext.ext_ref = bge_jref;
872 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
873
874 m_new->m_flags |= M_EXT;
875 } else {
876 KKASSERT(m->m_flags & M_EXT);
877 m_new = m;
878 buf = m_new->m_ext.ext_arg;
879 }
880 m_new->m_data = m_new->m_ext.ext_buf;
881 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
882
883 paddr = buf->bge_paddr;
884 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
885 m_adj(m_new, ETHER_ALIGN);
886 paddr += ETHER_ALIGN;
887 }
888
889 /* Set up the descriptor. */
890 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
891
892 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
893 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
894 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
895 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
896 r->bge_len = m_new->m_len;
897 r->bge_idx = i;
898
899 return 0;
900 }
901
902 /*
903 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
904 * that's 1MB or memory, which is a lot. For now, we fill only the first
905 * 256 ring entries and hope that our CPU is fast enough to keep up with
906 * the NIC.
907 */
908 static int
909 bge_init_rx_ring_std(struct bge_softc *sc)
910 {
911 int i;
912
913 for (i = 0; i < BGE_SSLOTS; i++) {
914 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
915 return(ENOBUFS);
916 };
917
918 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
919 sc->bge_cdata.bge_rx_std_ring_map,
920 BUS_DMASYNC_PREWRITE);
921
922 sc->bge_std = i - 1;
923 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
924
925 return(0);
926 }
927
928 static void
929 bge_free_rx_ring_std(struct bge_softc *sc)
930 {
931 int i;
932
933 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
934 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
935 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
936 sc->bge_cdata.bge_rx_std_dmamap[i]);
937 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
938 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
939 }
940 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
941 sizeof(struct bge_rx_bd));
942 }
943 }
944
945 static int
946 bge_init_rx_ring_jumbo(struct bge_softc *sc)
947 {
948 int i;
949 struct bge_rcb *rcb;
950
951 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
952 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
953 return(ENOBUFS);
954 };
955
956 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
957 sc->bge_cdata.bge_rx_jumbo_ring_map,
958 BUS_DMASYNC_PREWRITE);
959
960 sc->bge_jumbo = i - 1;
961
962 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
963 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
964 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
965
966 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
967
968 return(0);
969 }
970
971 static void
972 bge_free_rx_ring_jumbo(struct bge_softc *sc)
973 {
974 int i;
975
976 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
977 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
978 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
979 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
980 }
981 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
982 sizeof(struct bge_rx_bd));
983 }
984 }
985
986 static void
987 bge_free_tx_ring(struct bge_softc *sc)
988 {
989 int i;
990
991 for (i = 0; i < BGE_TX_RING_CNT; i++) {
992 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
993 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
994 sc->bge_cdata.bge_tx_dmamap[i]);
995 m_freem(sc->bge_cdata.bge_tx_chain[i]);
996 sc->bge_cdata.bge_tx_chain[i] = NULL;
997 }
998 bzero(&sc->bge_ldata.bge_tx_ring[i],
999 sizeof(struct bge_tx_bd));
1000 }
1001 }
1002
1003 static int
1004 bge_init_tx_ring(struct bge_softc *sc)
1005 {
1006 sc->bge_txcnt = 0;
1007 sc->bge_tx_saved_considx = 0;
1008 sc->bge_tx_prodidx = 0;
1009
1010 /* Initialize transmit producer index for host-memory send ring. */
1011 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1012
1013 /* 5700 b2 errata */
1014 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1015 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1016
1017 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1018 /* 5700 b2 errata */
1019 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1020 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1021
1022 return(0);
1023 }
1024
1025 static void
1026 bge_setmulti(struct bge_softc *sc)
1027 {
1028 struct ifnet *ifp;
1029 struct ifmultiaddr *ifma;
1030 uint32_t hashes[4] = { 0, 0, 0, 0 };
1031 int h, i;
1032
1033 ifp = &sc->arpcom.ac_if;
1034
1035 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1036 for (i = 0; i < 4; i++)
1037 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1038 return;
1039 }
1040
1041 /* First, zot all the existing filters. */
1042 for (i = 0; i < 4; i++)
1043 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1044
1045 /* Now program new ones. */
1046 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1047 if (ifma->ifma_addr->sa_family != AF_LINK)
1048 continue;
1049 h = ether_crc32_le(
1050 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1051 ETHER_ADDR_LEN) & 0x7f;
1052 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1053 }
1054
1055 for (i = 0; i < 4; i++)
1056 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1057 }
1058
1059 /*
1060 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1061 * self-test results.
1062 */
1063 static int
1064 bge_chipinit(struct bge_softc *sc)
1065 {
1066 int i;
1067 uint32_t dma_rw_ctl;
1068
1069 /* Set endian type before we access any non-PCI registers. */
1070 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1071
1072 /*
1073 * Check the 'ROM failed' bit on the RX CPU to see if
1074 * self-tests passed.
1075 */
1076 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1077 if_printf(&sc->arpcom.ac_if,
1078 "RX CPU self-diagnostics failed!\n");
1079 return(ENODEV);
1080 }
1081
1082 /* Clear the MAC control register */
1083 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1084
1085 /*
1086 * Clear the MAC statistics block in the NIC's
1087 * internal memory.
1088 */
1089 for (i = BGE_STATS_BLOCK;
1090 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1091 BGE_MEMWIN_WRITE(sc, i, 0);
1092
1093 for (i = BGE_STATUS_BLOCK;
1094 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1095 BGE_MEMWIN_WRITE(sc, i, 0);
1096
1097 /* Set up the PCI DMA control register. */
1098 if (sc->bge_flags & BGE_FLAG_PCIE) {
1099 /* PCI Express */
1100 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1101 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1102 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1103 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1104 /* PCI-X bus */
1105 if (BGE_IS_5714_FAMILY(sc)) {
1106 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1107 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1108 /* XXX magic values, Broadcom-supplied Linux driver */
1109 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1110 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1111 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1112 } else {
1113 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1114 }
1115 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1116 /*
1117 * The 5704 uses a different encoding of read/write
1118 * watermarks.
1119 */
1120 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1121 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1122 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1123 } else {
1124 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1125 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1126 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1127 (0x0F);
1128 }
1129
1130 /*
1131 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1132 * for hardware bugs.
1133 */
1134 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1135 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1136 uint32_t tmp;
1137
1138 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1139 if (tmp == 0x6 || tmp == 0x7)
1140 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1141 }
1142 } else {
1143 /* Conventional PCI bus */
1144 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1145 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1146 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1147 (0x0F);
1148 }
1149
1150 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1151 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1152 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1153 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1154 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1155
1156 /*
1157 * Set up general mode register.
1158 */
1159 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1160 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1161 BGE_MODECTL_TX_NO_PHDR_CSUM);
1162
1163 /*
1164 * Disable memory write invalidate. Apparently it is not supported
1165 * properly by these devices.
1166 */
1167 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1168
1169 /* Set the timer prescaler (always 66Mhz) */
1170 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1171
1172 return(0);
1173 }
1174
1175 static int
1176 bge_blockinit(struct bge_softc *sc)
1177 {
1178 struct bge_rcb *rcb;
1179 bus_size_t vrcb;
1180 bge_hostaddr taddr;
1181 uint32_t val;
1182 int i;
1183
1184 /*
1185 * Initialize the memory window pointer register so that
1186 * we can access the first 32K of internal NIC RAM. This will
1187 * allow us to set up the TX send ring RCBs and the RX return
1188 * ring RCBs, plus other things which live in NIC memory.
1189 */
1190 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1191
1192 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1193
1194 if (!BGE_IS_5705_PLUS(sc)) {
1195 /* Configure mbuf memory pool */
1196 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1197 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1198 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1199 else
1200 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1201
1202 /* Configure DMA resource pool */
1203 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1204 BGE_DMA_DESCRIPTORS);
1205 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1206 }
1207
1208 /* Configure mbuf pool watermarks */
1209 if (BGE_IS_5705_PLUS(sc)) {
1210 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1211 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1212 } else {
1213 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1214 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1215 }
1216 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1217
1218 /* Configure DMA resource watermarks */
1219 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1220 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1221
1222 /* Enable buffer manager */
1223 if (!BGE_IS_5705_PLUS(sc)) {
1224 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1225 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1226
1227 /* Poll for buffer manager start indication */
1228 for (i = 0; i < BGE_TIMEOUT; i++) {
1229 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1230 break;
1231 DELAY(10);
1232 }
1233
1234 if (i == BGE_TIMEOUT) {
1235 if_printf(&sc->arpcom.ac_if,
1236 "buffer manager failed to start\n");
1237 return(ENXIO);
1238 }
1239 }
1240
1241 /* Enable flow-through queues */
1242 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1243 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1244
1245 /* Wait until queue initialization is complete */
1246 for (i = 0; i < BGE_TIMEOUT; i++) {
1247 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1248 break;
1249 DELAY(10);
1250 }
1251
1252 if (i == BGE_TIMEOUT) {
1253 if_printf(&sc->arpcom.ac_if,
1254 "flow-through queue init failed\n");
1255 return(ENXIO);
1256 }
1257
1258 /* Initialize the standard RX ring control block */
1259 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1260 rcb->bge_hostaddr.bge_addr_lo =
1261 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1262 rcb->bge_hostaddr.bge_addr_hi =
1263 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1264 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1265 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1266 if (BGE_IS_5705_PLUS(sc))
1267 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1268 else
1269 rcb->bge_maxlen_flags =
1270 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1271 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1272 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1273 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1274 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1275 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1276
1277 /*
1278 * Initialize the jumbo RX ring control block
1279 * We set the 'ring disabled' bit in the flags
1280 * field until we're actually ready to start
1281 * using this ring (i.e. once we set the MTU
1282 * high enough to require it).
1283 */
1284 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1285 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1286
1287 rcb->bge_hostaddr.bge_addr_lo =
1288 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1289 rcb->bge_hostaddr.bge_addr_hi =
1290 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1291 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1292 sc->bge_cdata.bge_rx_jumbo_ring_map,
1293 BUS_DMASYNC_PREREAD);
1294 rcb->bge_maxlen_flags =
1295 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1296 BGE_RCB_FLAG_RING_DISABLED);
1297 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1298 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1299 rcb->bge_hostaddr.bge_addr_hi);
1300 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1301 rcb->bge_hostaddr.bge_addr_lo);
1302 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1303 rcb->bge_maxlen_flags);
1304 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1305
1306 /* Set up dummy disabled mini ring RCB */
1307 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1308 rcb->bge_maxlen_flags =
1309 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1310 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1311 rcb->bge_maxlen_flags);
1312 }
1313
1314 /*
1315 * Set the BD ring replentish thresholds. The recommended
1316 * values are 1/8th the number of descriptors allocated to
1317 * each ring.
1318 */
1319 if (BGE_IS_5705_PLUS(sc))
1320 val = 8;
1321 else
1322 val = BGE_STD_RX_RING_CNT / 8;
1323 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1324 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1325
1326 /*
1327 * Disable all unused send rings by setting the 'ring disabled'
1328 * bit in the flags field of all the TX send ring control blocks.
1329 * These are located in NIC memory.
1330 */
1331 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1332 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1333 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1334 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1335 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1336 vrcb += sizeof(struct bge_rcb);
1337 }
1338
1339 /* Configure TX RCB 0 (we use only the first ring) */
1340 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1341 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1342 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1343 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1344 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1345 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1346 if (!BGE_IS_5705_PLUS(sc)) {
1347 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1348 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1349 }
1350
1351 /* Disable all unused RX return rings */
1352 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1353 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1354 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1355 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1356 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1357 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1358 BGE_RCB_FLAG_RING_DISABLED));
1359 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1360 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1361 (i * (sizeof(uint64_t))), 0);
1362 vrcb += sizeof(struct bge_rcb);
1363 }
1364
1365 /* Initialize RX ring indexes */
1366 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1367 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1368 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1369
1370 /*
1371 * Set up RX return ring 0
1372 * Note that the NIC address for RX return rings is 0x00000000.
1373 * The return rings live entirely within the host, so the
1374 * nicaddr field in the RCB isn't used.
1375 */
1376 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1377 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1378 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1379 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1380 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1381 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1382 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1383
1384 /* Set random backoff seed for TX */
1385 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1386 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1387 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1388 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1389 BGE_TX_BACKOFF_SEED_MASK);
1390
1391 /* Set inter-packet gap */
1392 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1393
1394 /*
1395 * Specify which ring to use for packets that don't match
1396 * any RX rules.
1397 */
1398 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1399
1400 /*
1401 * Configure number of RX lists. One interrupt distribution
1402 * list, sixteen active lists, one bad frames class.
1403 */
1404 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1405
1406 /* Inialize RX list placement stats mask. */
1407 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1408 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1409
1410 /* Disable host coalescing until we get it set up */
1411 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1412
1413 /* Poll to make sure it's shut down. */
1414 for (i = 0; i < BGE_TIMEOUT; i++) {
1415 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1416 break;
1417 DELAY(10);
1418 }
1419
1420 if (i == BGE_TIMEOUT) {
1421 if_printf(&sc->arpcom.ac_if,
1422 "host coalescing engine failed to idle\n");
1423 return(ENXIO);
1424 }
1425
1426 /* Set up host coalescing defaults */
1427 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1428 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1429 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1430 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1431 if (!BGE_IS_5705_PLUS(sc)) {
1432 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1433 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1434 }
1435 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1436 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1437
1438 /* Set up address of statistics block */
1439 if (!BGE_IS_5705_PLUS(sc)) {
1440 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1441 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1442 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1443 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1444
1445 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1446 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1447 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1448 }
1449
1450 /* Set up address of status block */
1451 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1452 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1453 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1454 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1455 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1456 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1457
1458 /* Turn on host coalescing state machine */
1459 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1460
1461 /* Turn on RX BD completion state machine and enable attentions */
1462 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1463 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1464
1465 /* Turn on RX list placement state machine */
1466 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1467
1468 /* Turn on RX list selector state machine. */
1469 if (!BGE_IS_5705_PLUS(sc))
1470 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1471
1472 /* Turn on DMA, clear stats */
1473 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1474 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1475 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1476 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1477 ((sc->bge_flags & BGE_FLAG_TBI) ?
1478 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1479
1480 /* Set misc. local control, enable interrupts on attentions */
1481 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1482
1483 #ifdef notdef
1484 /* Assert GPIO pins for PHY reset */
1485 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1486 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1487 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1488 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1489 #endif
1490
1491 /* Turn on DMA completion state machine */
1492 if (!BGE_IS_5705_PLUS(sc))
1493 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1494
1495 /* Turn on write DMA state machine */
1496 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1497 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1498 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1499 val |= (1 << 29); /* Enable host coalescing bug fix. */
1500 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1501
1502 /* Turn on read DMA state machine */
1503 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1504 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1505
1506 /* Turn on RX data completion state machine */
1507 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1508
1509 /* Turn on RX BD initiator state machine */
1510 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1511
1512 /* Turn on RX data and RX BD initiator state machine */
1513 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1514
1515 /* Turn on Mbuf cluster free state machine */
1516 if (!BGE_IS_5705_PLUS(sc))
1517 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1518
1519 /* Turn on send BD completion state machine */
1520 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1521
1522 /* Turn on send data completion state machine */
1523 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1524
1525 /* Turn on send data initiator state machine */
1526 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1527
1528 /* Turn on send BD initiator state machine */
1529 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1530
1531 /* Turn on send BD selector state machine */
1532 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1533
1534 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1535 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1536 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1537
1538 /* ack/clear link change events */
1539 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1540 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1541 BGE_MACSTAT_LINK_CHANGED);
1542 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1543
1544 /* Enable PHY auto polling (for MII/GMII only) */
1545 if (sc->bge_flags & BGE_FLAG_TBI) {
1546 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1547 } else {
1548 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1549 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1550 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1551 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1552 BGE_EVTENB_MI_INTERRUPT);
1553 }
1554 }
1555
1556 /*
1557 * Clear any pending link state attention.
1558 * Otherwise some link state change events may be lost until attention
1559 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1560 * It's not necessary on newer BCM chips - perhaps enabling link
1561 * state change attentions implies clearing pending attention.
1562 */
1563 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1564 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1565 BGE_MACSTAT_LINK_CHANGED);
1566
1567 /* Enable link state change attentions. */
1568 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1569
1570 return(0);
1571 }
1572
1573 /*
1574 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1575 * against our list and return its name if we find a match. Note
1576 * that since the Broadcom controller contains VPD support, we
1577 * can get the device name string from the controller itself instead
1578 * of the compiled-in string. This is a little slow, but it guarantees
1579 * we'll always announce the right product name.
1580 */
1581 static int
1582 bge_probe(device_t dev)
1583 {
1584 struct bge_softc *sc;
1585 struct bge_type *t;
1586 char *descbuf;
1587 uint16_t product, vendor;
1588
1589 product = pci_get_device(dev);
1590 vendor = pci_get_vendor(dev);
1591
1592 for (t = bge_devs; t->bge_name != NULL; t++) {
1593 if (vendor == t->bge_vid && product == t->bge_did)
1594 break;
1595 }
1596
1597 if (t->bge_name == NULL)
1598 return(ENXIO);
1599
1600 sc = device_get_softc(dev);
1601 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1602 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1603 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1604 device_set_desc_copy(dev, descbuf);
1605 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1606 sc->bge_flags |= BGE_FLAG_NO_3LED;
1607 kfree(descbuf, M_TEMP);
1608 return(0);
1609 }
1610
1611 static int
1612 bge_attach(device_t dev)
1613 {
1614 struct ifnet *ifp;
1615 struct bge_softc *sc;
1616 uint32_t hwcfg = 0;
1617 uint32_t mac_addr = 0;
1618 int error = 0, rid;
1619 uint8_t ether_addr[ETHER_ADDR_LEN];
1620
1621 sc = device_get_softc(dev);
1622 sc->bge_dev = dev;
1623 callout_init(&sc->bge_stat_timer);
1624 lwkt_serialize_init(&sc->bge_jslot_serializer);
1625
1626 /*
1627 * Map control/status registers.
1628 */
1629 pci_enable_busmaster(dev);
1630
1631 rid = BGE_PCI_BAR0;
1632 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1633 RF_ACTIVE);
1634
1635 if (sc->bge_res == NULL) {
1636 device_printf(dev, "couldn't map memory\n");
1637 return ENXIO;
1638 }
1639
1640 sc->bge_btag = rman_get_bustag(sc->bge_res);
1641 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1642
1643 /* Save ASIC rev. */
1644 sc->bge_chipid =
1645 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1646 BGE_PCIMISCCTL_ASICREV;
1647 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1648 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1649
1650 /* Save chipset family. */
1651 switch (sc->bge_asicrev) {
1652 case BGE_ASICREV_BCM5700:
1653 case BGE_ASICREV_BCM5701:
1654 case BGE_ASICREV_BCM5703:
1655 case BGE_ASICREV_BCM5704:
1656 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1657 break;
1658
1659 case BGE_ASICREV_BCM5714_A0:
1660 case BGE_ASICREV_BCM5780:
1661 case BGE_ASICREV_BCM5714:
1662 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1663 /* Fall through */
1664
1665 case BGE_ASICREV_BCM5750:
1666 case BGE_ASICREV_BCM5752:
1667 case BGE_ASICREV_BCM5755:
1668 case BGE_ASICREV_BCM5787:
1669 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1670 /* Fall through */
1671
1672 case BGE_ASICREV_BCM5705:
1673 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1674 break;
1675 }
1676
1677 /*
1678 * Set various quirk flags.
1679 */
1680
1681 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1682 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1683 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1684 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1685 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1686 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1687 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1688
1689 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1690 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1691 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1692
1693 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1694 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1695 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1696
1697 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1698 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1699
1700 if (BGE_IS_5705_PLUS(sc)) {
1701 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1702 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1703 uint32_t product = pci_get_device(dev);
1704
1705 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1706 product != PCI_PRODUCT_BROADCOM_BCM5756)
1707 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1708 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1709 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1710 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1711 sc->bge_flags |= BGE_FLAG_BER_BUG;
1712 }
1713 }
1714
1715 /* Allocate interrupt */
1716 rid = 0;
1717
1718 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1719 RF_SHAREABLE | RF_ACTIVE);
1720
1721 if (sc->bge_irq == NULL) {
1722 device_printf(dev, "couldn't map interrupt\n");
1723 error = ENXIO;
1724 goto fail;
1725 }
1726
1727 /*
1728 * Check if this is a PCI-X or PCI Express device.
1729 */
1730 if (BGE_IS_5705_PLUS(sc)) {
1731 uint32_t reg;
1732
1733 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1734 if ((reg & 0xff) == BGE_PCIE_CAPID)
1735 sc->bge_flags |= BGE_FLAG_PCIE;
1736 } else {
1737 /*
1738 * Check if the device is in PCI-X Mode.
1739 * (This bit is not valid on PCI Express controllers.)
1740 */
1741 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1742 BGE_PCISTATE_PCI_BUSMODE) == 0)
1743 sc->bge_flags |= BGE_FLAG_PCIX;
1744 }
1745
1746 ifp = &sc->arpcom.ac_if;
1747 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1748
1749 /* Try to reset the chip. */
1750 bge_reset(sc);
1751
1752 if (bge_chipinit(sc)) {
1753 device_printf(dev, "chip initialization failed\n");
1754 error = ENXIO;
1755 goto fail;
1756 }
1757
1758 /*
1759 * Get station address from the EEPROM.
1760 */
1761 mac_addr = bge_readmem_ind(sc, 0x0c14);
1762 if ((mac_addr >> 16) == 0x484b) {
1763 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1764 ether_addr[1] = (uint8_t)mac_addr;
1765 mac_addr = bge_readmem_ind(sc, 0x0c18);
1766 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1767 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1768 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1769 ether_addr[5] = (uint8_t)mac_addr;
1770 } else if (bge_read_eeprom(sc, ether_addr,
1771 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1772 device_printf(dev, "failed to read station address\n");
1773 error = ENXIO;
1774 goto fail;
1775 }
1776
1777 /* 5705/5750 limits RX return ring to 512 entries. */
1778 if (BGE_IS_5705_PLUS(sc))
1779 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1780 else
1781 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1782
1783 error = bge_dma_alloc(sc);
1784 if (error)
1785 goto fail;
1786
1787 /* Set default tuneable values. */
1788 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1789 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1790 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1791 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1792 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1793
1794 /* Set up ifnet structure */
1795 ifp->if_softc = sc;
1796 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1797 ifp->if_ioctl = bge_ioctl;
1798 ifp->if_start = bge_start;
1799 #ifdef DEVICE_POLLING
1800 ifp->if_poll = bge_poll;
1801 #endif
1802 ifp->if_watchdog = bge_watchdog;
1803 ifp->if_init = bge_init;
1804 ifp->if_mtu = ETHERMTU;
1805 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1806 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1807 ifq_set_ready(&ifp->if_snd);
1808
1809 /*
1810 * 5700 B0 chips do not support checksumming correctly due
1811 * to hardware bugs.
1812 */
1813 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1814 ifp->if_capabilities |= IFCAP_HWCSUM;
1815 ifp->if_hwassist = BGE_CSUM_FEATURES;
1816 }
1817 ifp->if_capenable = ifp->if_capabilities;
1818
1819 /*
1820 * Figure out what sort of media we have by checking the
1821 * hardware config word in the first 32k of NIC internal memory,
1822 * or fall back to examining the EEPROM if necessary.
1823 * Note: on some BCM5700 cards, this value appears to be unset.
1824 * If that's the case, we have to rely on identifying the NIC
1825 * by its PCI subsystem ID, as we do below for the SysKonnect
1826 * SK-9D41.
1827 */
1828 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1829 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1830 else {
1831 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1832 sizeof(hwcfg))) {
1833 device_printf(dev, "failed to read EEPROM\n");
1834 error = ENXIO;
1835 goto fail;
1836 }
1837 hwcfg = ntohl(hwcfg);
1838 }
1839
1840 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1841 sc->bge_flags |= BGE_FLAG_TBI;
1842
1843 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1844 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1845 sc->bge_flags |= BGE_FLAG_TBI;
1846
1847 if (sc->bge_flags & BGE_FLAG_TBI) {
1848 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1849 bge_ifmedia_upd, bge_ifmedia_sts);
1850 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1851 ifmedia_add(&sc->bge_ifmedia,
1852 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1853 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1854 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1855 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1856 } else {
1857 /*
1858 * Do transceiver setup.
1859 */
1860 if (mii_phy_probe(dev, &sc->bge_miibus,
1861 bge_ifmedia_upd, bge_ifmedia_sts)) {
1862 device_printf(dev, "MII without any PHY!\n");
1863 error = ENXIO;
1864 goto fail;
1865 }
1866 }
1867
1868 /*
1869 * When using the BCM5701 in PCI-X mode, data corruption has
1870 * been observed in the first few bytes of some received packets.
1871 * Aligning the packet buffer in memory eliminates the corruption.
1872 * Unfortunately, this misaligns the packet payloads. On platforms
1873 * which do not support unaligned accesses, we will realign the
1874 * payloads by copying the received packets.
1875 */
1876 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1877 (sc->bge_flags & BGE_FLAG_PCIX))
1878 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1879
1880 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1881 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1882 sc->bge_link_upd = bge_bcm5700_link_upd;
1883 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1884 } else if (sc->bge_flags & BGE_FLAG_TBI) {
1885 sc->bge_link_upd = bge_tbi_link_upd;
1886 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1887 } else {
1888 sc->bge_link_upd = bge_copper_link_upd;
1889 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1890 }
1891
1892 /*
1893 * Create sysctl nodes.
1894 */
1895 sysctl_ctx_init(&sc->bge_sysctl_ctx);
1896 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1897 SYSCTL_STATIC_CHILDREN(_hw),
1898 OID_AUTO,
1899 device_get_nameunit(dev),
1900 CTLFLAG_RD, 0, "");
1901 if (sc->bge_sysctl_tree == NULL) {
1902 device_printf(dev, "can't add sysctl node\n");
1903 error = ENXIO;
1904 goto fail;
1905 }
1906
1907 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1908 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1909 OID_AUTO, "rx_coal_ticks",
1910 CTLTYPE_INT | CTLFLAG_RW,
1911 sc, 0, bge_sysctl_rx_coal_ticks, "I",
1912 "Receive coalescing ticks (usec).");
1913 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1914 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1915 OID_AUTO, "tx_coal_ticks",
1916 CTLTYPE_INT | CTLFLAG_RW,
1917 sc, 0, bge_sysctl_tx_coal_ticks, "I",
1918 "Transmit coalescing ticks (usec).");
1919 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1920 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1921 OID_AUTO, "rx_max_coal_bds",
1922 CTLTYPE_INT | CTLFLAG_RW,
1923 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1924 "Receive max coalesced BD count.");
1925 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1926 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1927 OID_AUTO, "tx_max_coal_bds",
1928 CTLTYPE_INT | CTLFLAG_RW,
1929 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1930 "Transmit max coalesced BD count.");
1931
1932 /*
1933 * Call MI attach routine.
1934 */
1935 ether_ifattach(ifp, ether_addr, NULL);
1936
1937 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1938 bge_intr, sc, &sc->bge_intrhand,
1939 ifp->if_serializer);
1940 if (error) {
1941 ether_ifdetach(ifp);
1942 device_printf(dev, "couldn't set up irq\n");
1943 goto fail;
1944 }
1945 return(0);
1946 fail:
1947 bge_detach(dev);
1948 return(error);
1949 }
1950
1951 static int
1952 bge_detach(device_t dev)
1953 {
1954 struct bge_softc *sc = device_get_softc(dev);
1955
1956 if (device_is_attached(dev)) {
1957 struct ifnet *ifp = &sc->arpcom.ac_if;
1958
1959 lwkt_serialize_enter(ifp->if_serializer);
1960 bge_stop(sc);
1961 bge_reset(sc);
1962 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1963 lwkt_serialize_exit(ifp->if_serializer);
1964
1965 ether_ifdetach(ifp);
1966 }
1967
1968 if (sc->bge_flags & BGE_FLAG_TBI)
1969 ifmedia_removeall(&sc->bge_ifmedia);
1970 if (sc->bge_miibus)
1971 device_delete_child(dev, sc->bge_miibus);
1972 bus_generic_detach(dev);
1973
1974 if (sc->bge_irq != NULL)
1975 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1976
1977 if (sc->bge_res != NULL)
1978 bus_release_resource(dev, SYS_RES_MEMORY,
1979 BGE_PCI_BAR0, sc->bge_res);
1980
1981 if (sc->bge_sysctl_tree != NULL)
1982 sysctl_ctx_free(&sc->bge_sysctl_ctx);
1983
1984 bge_dma_free(sc);
1985
1986 return 0;
1987 }
1988
1989 static void
1990 bge_reset(struct bge_softc *sc)
1991 {
1992 device_t dev;
1993 uint32_t cachesize, command, pcistate, reset;
1994 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
1995 int i, val = 0;
1996
1997 dev = sc->bge_dev;
1998
1999 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2000 if (sc->bge_flags & BGE_FLAG_PCIE)
2001 write_op = bge_writemem_direct;
2002 else
2003 write_op = bge_writemem_ind;
2004 } else {
2005 write_op = bge_writereg_ind;
2006 }
2007
2008 /* Save some important PCI state. */
2009 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2010 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2011 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2012
2013 pci_write_config(dev, BGE_PCI_MISC_CTL,
2014 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2015 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2016
2017 /* Disable fastboot on controllers that support it. */
2018 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2019 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2020 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2021 if (bootverbose)
2022 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2023 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2024 }
2025
2026 /*
2027 * Write the magic number to SRAM at offset 0xB50.
2028 * When firmware finishes its initialization it will
2029 * write ~BGE_MAGIC_NUMBER to the same location.
2030 */
2031 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2032
2033 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2034
2035 /* XXX: Broadcom Linux driver. */
2036 if (sc->bge_flags & BGE_FLAG_PCIE) {
2037 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2038 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2039 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2040 /* Prevent PCIE link training during global reset */
2041 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2042 reset |= (1<<29);
2043 }
2044 }
2045
2046 /*
2047 * Set GPHY Power Down Override to leave GPHY
2048 * powered up in D0 uninitialized.
2049 */
2050 if (BGE_IS_5705_PLUS(sc))
2051 reset |= 0x04000000;
2052
2053 /* Issue global reset */
2054 write_op(sc, BGE_MISC_CFG, reset);
2055
2056 DELAY(1000);
2057
2058 /* XXX: Broadcom Linux driver. */
2059 if (sc->bge_flags & BGE_FLAG_PCIE) {
2060 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2061 uint32_t v;
2062
2063 DELAY(500000); /* wait for link training to complete */
2064 v = pci_read_config(dev, 0xc4, 4);
2065 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2066 }
2067 /*
2068 * Set PCIE max payload size to 128 bytes and
2069 * clear error status.
2070 */
2071 pci_write_config(dev, 0xd8, 0xf5000, 4);
2072 }
2073
2074 /* Reset some of the PCI state that got zapped by reset */
2075 pci_write_config(dev, BGE_PCI_MISC_CTL,
2076 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2077 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2078 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2079 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2080 write_op(sc, BGE_MISC_CFG, (65 << 1));
2081
2082 /* Enable memory arbiter. */
2083 if (BGE_IS_5714_FAMILY(sc)) {
2084 uint32_t val;
2085
2086 val = CSR_READ_4(sc, BGE_MARB_MODE);
2087 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2088 } else {
2089 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2090 }
2091
2092 /*
2093 * Poll until we see the 1's complement of the magic number.
2094 * This indicates that the firmware initialization
2095 * is complete.
2096 */
2097 for (i = 0; i < BGE_TIMEOUT; i++) {
2098 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2099 if (val == ~BGE_MAGIC_NUMBER)
2100 break;
2101 DELAY(10);
2102 }
2103
2104 if (i == BGE_TIMEOUT) {
2105 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2106 "found 0x%08x\n", val);
2107 return;
2108 }
2109
2110 /*
2111 * XXX Wait for the value of the PCISTATE register to
2112 * return to its original pre-reset state. This is a
2113 * fairly good indicator of reset completion. If we don't
2114 * wait for the reset to fully complete, trying to read
2115 * from the device's non-PCI registers may yield garbage
2116 * results.
2117 */
2118 for (i = 0; i < BGE_TIMEOUT; i++) {
2119 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2120 break;
2121 DELAY(10);
2122 }
2123
2124 if (sc->bge_flags & BGE_FLAG_PCIE) {
2125 reset = bge_readmem_ind(sc, 0x7c00);
2126 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2127 }
2128
2129 /* Fix up byte swapping */
2130 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2131 BGE_MODECTL_BYTESWAP_DATA);
2132
2133 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2134
2135 /*
2136 * The 5704 in TBI mode apparently needs some special
2137 * adjustment to insure the SERDES drive level is set
2138 * to 1.2V.
2139 */
2140 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2141 (sc->bge_flags & BGE_FLAG_TBI)) {
2142 uint32_t serdescfg;
2143
2144 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2145 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2146 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2147 }
2148
2149 /* XXX: Broadcom Linux driver. */
2150 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2151 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2152 uint32_t v;
2153
2154 v = CSR_READ_4(sc, 0x7c00);
2155 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2156 }
2157
2158 DELAY(10000);
2159 }
2160
2161 /*
2162 * Frame reception handling. This is called if there's a frame
2163 * on the receive return list.
2164 *
2165 * Note: we have to be able to handle two possibilities here:
2166 * 1) the frame is from the jumbo recieve ring
2167 * 2) the frame is from the standard receive ring
2168 */
2169
2170 static void
2171 bge_rxeof(struct bge_softc *sc)
2172 {
2173 struct ifnet *ifp;
2174 int stdcnt = 0, jumbocnt = 0;
2175
2176 if (sc->bge_rx_saved_considx ==
2177 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2178 return;
2179
2180 ifp = &sc->arpcom.ac_if;
2181
2182 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2183 sc->bge_cdata.bge_rx_return_ring_map,
2184 BUS_DMASYNC_POSTREAD);
2185 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2186 sc->bge_cdata.bge_rx_std_ring_map,
2187 BUS_DMASYNC_POSTREAD);
2188 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2189 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2190 sc->bge_cdata.bge_rx_jumbo_ring_map,
2191 BUS_DMASYNC_POSTREAD);
2192 }
2193
2194 while (sc->bge_rx_saved_considx !=
2195 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2196 struct bge_rx_bd *cur_rx;
2197 uint32_t rxidx;
2198 struct mbuf *m = NULL;
2199 uint16_t vlan_tag = 0;
2200 int have_tag = 0;
2201
2202 cur_rx =
2203 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2204
2205 rxidx = cur_rx->bge_idx;
2206 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2207
2208 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2209 have_tag = 1;
2210 vlan_tag = cur_rx->bge_vlan_tag;
2211 }
2212
2213 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2214 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2215 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2216 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2217 jumbocnt++;
2218 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2219 ifp->if_ierrors++;
2220 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2221 continue;
2222 }
2223 if (bge_newbuf_jumbo(sc,
2224 sc->bge_jumbo, NULL) == ENOBUFS) {
2225 ifp->if_ierrors++;
2226 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2227 continue;
2228 }
2229 } else {
2230 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2231 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2232 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2233 BUS_DMASYNC_POSTREAD);
2234 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2235 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2236 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2237 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2238 stdcnt++;
2239 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2240 ifp->if_ierrors++;
2241 bge_newbuf_std(sc, sc->bge_std, m);
2242 continue;
2243 }
2244 if (bge_newbuf_std(sc, sc->bge_std,
2245 NULL) == ENOBUFS) {
2246 ifp->if_ierrors++;
2247 bge_newbuf_std(sc, sc->bge_std, m);
2248 continue;
2249 }
2250 }
2251
2252 ifp->if_ipackets++;
2253 #ifndef __i386__
2254 /*
2255 * The i386 allows unaligned accesses, but for other
2256 * platforms we must make sure the payload is aligned.
2257 */
2258 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2259 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2260 cur_rx->bge_len);
2261 m->m_data += ETHER_ALIGN;
2262 }
2263 #endif
2264 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2265 m->m_pkthdr.rcvif = ifp;
2266
2267 if (ifp->if_capenable & IFCAP_RXCSUM) {
2268 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2269 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2270 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2271 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2272 }
2273 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2274 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2275 m->m_pkthdr.csum_data =
2276 cur_rx->bge_tcp_udp_csum;
2277 m->m_pkthdr.csum_flags |=
2278 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2279 }
2280 }
2281
2282 /*
2283 * If we received a packet with a vlan tag, pass it
2284 * to vlan_input() instead of ether_input().
2285 */
2286 if (have_tag) {
2287 VLAN_INPUT_TAG(m, vlan_tag);
2288 have_tag = vlan_tag = 0;
2289 } else {
2290 ifp->if_input(ifp, m);
2291 }
2292 }
2293
2294 if (stdcnt > 0) {
2295 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2296 sc->bge_cdata.bge_rx_std_ring_map,
2297 BUS_DMASYNC_PREWRITE);
2298 }
2299
2300 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2301 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2302 sc->bge_cdata.bge_rx_jumbo_ring_map,
2303 BUS_DMASYNC_PREWRITE);
2304 }
2305
2306 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2307 if (stdcnt)
2308 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2309 if (jumbocnt)
2310 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2311 }
2312
2313 static void
2314 bge_txeof(struct bge_softc *sc)
2315 {
2316 struct bge_tx_bd *cur_tx = NULL;
2317 struct ifnet *ifp;
2318
2319 if (sc->bge_tx_saved_considx ==
2320 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2321 return;
2322
2323 ifp = &sc->arpcom.ac_if;
2324
2325 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2326 sc->bge_cdata.bge_tx_ring_map,
2327 BUS_DMASYNC_POSTREAD);
2328
2329 /*
2330 * Go through our tx ring and free mbufs for those
2331 * frames that have been sent.
2332 */
2333 while (sc->bge_tx_saved_considx !=
2334 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2335 uint32_t idx = 0;
2336
2337 idx = sc->bge_tx_saved_considx;
2338 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2339 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2340 ifp->if_opackets++;
2341 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2342 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2343 sc->bge_cdata.bge_tx_dmamap[idx],
2344 BUS_DMASYNC_POSTWRITE);
2345 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2346 sc->bge_cdata.bge_tx_dmamap[idx]);
2347 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2348 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2349 }
2350 sc->bge_txcnt--;
2351 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2352 }
2353
2354 if (cur_tx != NULL &&
2355 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2356 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2357 ifp->if_flags &= ~IFF_OACTIVE;
2358
2359 if (sc->bge_txcnt == 0)
2360 ifp->if_timer = 0;
2361
2362 if (!ifq_is_empty(&ifp->if_snd))
2363 ifp->if_start(ifp);
2364 }
2365
2366 #ifdef DEVICE_POLLING
2367
2368 static void
2369 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2370 {
2371 struct bge_softc *sc = ifp->if_softc;
2372 uint32_t status;
2373
2374 switch(cmd) {
2375 case POLL_REGISTER:
2376 /*
2377 * Mask the interrupt when we start polling
2378 */
2379 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2380 break;
2381 case POLL_DEREGISTER:
2382 /*
2383 * Unmask the interrupt when we stop polling.
2384 */
2385 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2386 break;
2387 case POLL_AND_CHECK_STATUS:
2388 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2389 sc->bge_cdata.bge_status_map,
2390 BUS_DMASYNC_POSTREAD);
2391
2392 /*
2393 * Process link state changes.
2394 */
2395 status = CSR_READ_4(sc, BGE_MAC_STS);
2396 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2397 sc->bge_link_evt = 0;
2398 sc->bge_link_upd(sc, status);
2399 }
2400 /* fall through */
2401 case POLL_ONLY:
2402 if (ifp->if_flags & IFF_RUNNING) {
2403 bge_rxeof(sc);
2404 bge_txeof(sc);
2405 }
2406 break;
2407 }
2408 }
2409
2410 #endif
2411
2412 static void
2413 bge_intr(void *xsc)
2414 {
2415 struct bge_softc *sc = xsc;
2416 struct ifnet *ifp = &sc->arpcom.ac_if;
2417 uint32_t status;
2418
2419 /*
2420 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2421 * disable interrupts by writing nonzero like we used to, since with
2422 * our current organization this just gives complications and
2423 * pessimizations for re-enabling interrupts. We used to have races
2424 * instead of the necessary complications. Disabling interrupts
2425 * would just reduce the chance of a status update while we are
2426 * running (by switching to the interrupt-mode coalescence
2427 * parameters), but this chance is already very low so it is more
2428 * efficient to get another interrupt than prevent it.
2429 *
2430 * We do the ack first to ensure another interrupt if there is a
2431 * status update after the ack. We don't check for the status
2432 * changing later because it is more efficient to get another
2433 * interrupt than prevent it, not quite as above (not checking is
2434 * a smaller optimization than not toggling the interrupt enable,
2435 * since checking doesn't involve PCI accesses and toggling require
2436 * the status check). So toggling would probably be a pessimization
2437 * even with MSI. It would only be needed for using a task queue.
2438 */
2439 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2440
2441 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2442 sc->bge_cdata.bge_status_map,
2443 BUS_DMASYNC_POSTREAD);
2444
2445 /*
2446 * Process link state changes.
2447 */
2448 status = CSR_READ_4(sc, BGE_MAC_STS);
2449 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2450 sc->bge_link_evt = 0;
2451 sc->bge_link_upd(sc, status);
2452 }
2453
2454 if (ifp->if_flags & IFF_RUNNING) {
2455 /* Check RX return ring producer/consumer */
2456 bge_rxeof(sc);
2457
2458 /* Check TX ring producer/consumer */
2459 bge_txeof(sc);
2460 }
2461
2462 if (sc->bge_coal_chg)
2463 bge_coal_change(sc);
2464 }
2465
2466 static void
2467 bge_tick(void *xsc)
2468 {
2469 struct bge_softc *sc = xsc;
2470 struct ifnet *ifp = &sc->arpcom.ac_if;
2471
2472 lwkt_serialize_enter(ifp->if_serializer);
2473
2474 if (BGE_IS_5705_PLUS(sc))
2475 bge_stats_update_regs(sc);
2476 else
2477 bge_stats_update(sc);
2478
2479 if (sc->bge_flags & BGE_FLAG_TBI) {
2480 /*
2481 * Since in TBI mode auto-polling can't be used we should poll
2482 * link status manually. Here we register pending link event
2483 * and trigger interrupt.
2484 */
2485 sc->bge_link_evt++;
2486 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2487 } else if (!sc->bge_link) {
2488 mii_tick(device_get_softc(sc->bge_miibus));
2489 }
2490
2491 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2492
2493 lwkt_serialize_exit(ifp->if_serializer);
2494 }
2495
2496 static void
2497 bge_stats_update_regs(struct bge_softc *sc)
2498 {
2499 struct ifnet *ifp = &sc->arpcom.ac_if;
2500 struct bge_mac_stats_regs stats;
2501 uint32_t *s;
2502 int i;
2503
2504 s = (uint32_t *)&stats;
2505 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2506 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2507 s++;
2508 }
2509
2510 ifp->if_collisions +=
2511 (stats.dot3StatsSingleCollisionFrames +
2512 stats.dot3StatsMultipleCollisionFrames +
2513 stats.dot3StatsExcessiveCollisions +
2514 stats.dot3StatsLateCollisions) -
2515 ifp->if_collisions;
2516 }
2517
2518 static void
2519 bge_stats_update(struct bge_softc *sc)
2520 {
2521 struct ifnet *ifp = &sc->arpcom.ac_if;
2522 bus_size_t stats;
2523
2524 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2525
2526 #define READ_STAT(sc, stats, stat) \
2527 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2528
2529 ifp->if_collisions +=
2530 (READ_STAT(sc, stats,
2531 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2532 READ_STAT(sc, stats,
2533 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2534 READ_STAT(sc, stats,
2535 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2536 READ_STAT(sc, stats,
2537 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2538 ifp->if_collisions;
2539
2540 #undef READ_STAT
2541
2542 #ifdef notdef
2543 ifp->if_collisions +=
2544 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2545 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2546 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2547 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2548 ifp->if_collisions;
2549 #endif
2550 }
2551
2552 /*
2553 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2554 * pointers to descriptors.
2555 */
2556 static int
2557 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2558 {
2559 struct bge_tx_bd *d = NULL;
2560 uint16_t csum_flags = 0;
2561 struct ifvlan *ifv = NULL;
2562 struct bge_dmamap_arg ctx;
2563 bus_dma_segment_t segs[BGE_NSEG_NEW];
2564 bus_dmamap_t map;
2565 int error, maxsegs, idx, i;
2566
2567 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2568 m_head->m_pkthdr.rcvif != NULL &&
2569 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2570 ifv = m_head->m_pkthdr.rcvif->if_softc;
2571
2572 if (m_head->m_pkthdr.csum_flags) {
2573 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2574 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2575 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2576 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2577 if (m_head->m_flags & M_LASTFRAG)
2578 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2579 else if (m_head->m_flags & M_FRAG)
2580 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2581 }
2582
2583 idx = *txidx;
2584 map = sc->bge_cdata.bge_tx_dmamap[idx];
2585
2586 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2587 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2588 ("not enough segments %d\n", maxsegs));
2589
2590 if (maxsegs > BGE_NSEG_NEW)
2591 maxsegs = BGE_NSEG_NEW;
2592
2593 /*
2594 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2595 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2596 * but when such padded frames employ the bge IP/TCP checksum
2597 * offload, the hardware checksum assist gives incorrect results
2598 * (possibly from incorporating its own padding into the UDP/TCP
2599 * checksum; who knows). If we pad such runts with zeros, the
2600 * onboard checksum comes out correct. We do this by pretending
2601 * the mbuf chain has too many fragments so the coalescing code
2602 * below can assemble the packet into a single buffer that's
2603 * padded out to the mininum frame size.
2604 */
2605 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2606 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2607 error = EFBIG;
2608 } else {
2609 ctx.bge_segs = segs;
2610 ctx.bge_maxsegs = maxsegs;
2611 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2612 m_head, bge_dma_map_mbuf, &ctx,
2613 BUS_DMA_NOWAIT);
2614 }
2615 if (error == EFBIG || ctx.bge_maxsegs == 0) {
2616 struct mbuf *m_new;
2617
2618 m_new = m_defrag(m_head, MB_DONTWAIT);
2619 if (m_new == NULL) {
2620 if_printf(&sc->arpcom.ac_if,
2621 "could not defrag TX mbuf\n");
2622 error = ENOBUFS;
2623 goto back;
2624 } else {
2625 m_head = m_new;
2626 }
2627
2628 /*
2629 * Manually pad short frames, and zero the pad space
2630 * to avoid leaking data.
2631 */
2632 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2633 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2634 int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2635
2636 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2637 pad_len);
2638 m_head->m_pkthdr.len += pad_len;
2639 m_head->m_len = m_head->m_pkthdr.len;
2640 }
2641
2642 ctx.bge_segs = segs;
2643 ctx.bge_maxsegs = maxsegs;
2644 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2645 m_head, bge_dma_map_mbuf, &ctx,
2646 BUS_DMA_NOWAIT);
2647 if (error || ctx.bge_maxsegs == 0) {
2648 if_printf(&sc->arpcom.ac_if,
2649 "could not defrag TX mbuf\n");
2650 if (error == 0)
2651 error = EFBIG;
2652 goto back;
2653 }
2654 } else if (error) {
2655 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2656 goto back;
2657 }
2658
2659 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2660
2661 for (i = 0; ; i++) {
2662 d = &sc->bge_ldata.bge_tx_ring[idx];
2663
2664 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2665 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2666 d->bge_len = segs[i].ds_len;
2667 d->bge_flags = csum_flags;
2668
2669 if (i == ctx.bge_maxsegs - 1)
2670 break;
2671 BGE_INC(idx, BGE_TX_RING_CNT);
2672 }
2673 /* Mark the last segment as end of packet... */
2674 d->bge_flags |= BGE_TXBDFLAG_END;
2675
2676 /* Set vlan tag to the first segment of the packet. */
2677 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2678 if (ifv != NULL) {
2679 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2680 d->bge_vlan_tag = ifv->ifv_tag;
2681 } else {
2682 d->bge_vlan_tag = 0;
2683 }
2684
2685 /*
2686 * Insure that the map for this transmission is placed at
2687 * the array index of the last descriptor in this chain.
2688 */
2689 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2690 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2691 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2692 sc->bge_txcnt += ctx.bge_maxsegs;
2693
2694 BGE_INC(idx, BGE_TX_RING_CNT);
2695 *txidx = idx;
2696 back:
2697 if (error)
2698 m_freem(m_head);
2699 return error;
2700 }
2701
2702 /*
2703 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2704 * to the mbuf data regions directly in the transmit descriptors.
2705 */
2706 static void
2707 bge_start(struct ifnet *ifp)
2708 {
2709 struct bge_softc *sc = ifp->if_softc;
2710 struct mbuf *m_head = NULL;
2711 uint32_t prodidx;
2712 int need_trans;
2713
2714 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING ||
2715 !sc->bge_link)
2716 return;
2717
2718 prodidx = sc->bge_tx_prodidx;
2719
2720 need_trans = 0;
2721 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2722 m_head = ifq_poll(&ifp->if_snd);
2723 if (m_head == NULL)
2724 break;
2725
2726 /*
2727 * XXX
2728 * The code inside the if() block is never reached since we
2729 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2730 * requests to checksum TCP/UDP in a fragmented packet.
2731 *
2732 * XXX
2733 * safety overkill. If this is a fragmented packet chain
2734 * with delayed TCP/UDP checksums, then only encapsulate
2735 * it if we have enough descriptors to handle the entire
2736 * chain at once.
2737 * (paranoia -- may not actually be needed)
2738 */
2739 if (m_head->m_flags & M_FIRSTFRAG &&
2740 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2741 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2742 m_head->m_pkthdr.csum_data + 16) {
2743 ifp->if_flags |= IFF_OACTIVE;
2744 break;
2745 }
2746 }
2747
2748 /*
2749 * Sanity check: avoid coming within BGE_NSEG_RSVD
2750 * descriptors of the end of the ring. Also make
2751 * sure there are BGE_NSEG_SPARE descriptors for
2752 * jumbo buffers' defragmentation.
2753 */
2754 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2755 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2756 ifp->if_flags |= IFF_OACTIVE;
2757 break;
2758 }
2759
2760 /*
2761 * Dequeue the packet before encapsulation, since
2762 * bge_encap() may free the packet if error happens.
2763 */
2764 ifq_dequeue(&ifp->if_snd, m_head);
2765
2766 /*
2767 * Pack the data into the transmit ring. If we
2768 * don't have room, set the OACTIVE flag and wait
2769 * for the NIC to drain the ring.
2770 */
2771 if (bge_encap(sc, m_head, &prodidx)) {
2772 ifp->if_flags |= IFF_OACTIVE;
2773 break;
2774 }
2775 need_trans = 1;
2776
2777 BPF_MTAP(ifp, m_head);
2778 }
2779
2780 if (!need_trans)
2781 return;
2782
2783 /* Transmit */
2784 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2785 /* 5700 b2 errata */
2786 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2787 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2788
2789 sc->bge_tx_prodidx = prodidx;
2790
2791 /*
2792 * Set a timeout in case the chip goes out to lunch.
2793 */
2794 ifp->if_timer = 5;
2795 }
2796
2797 static void
2798 bge_init(void *xsc)
2799 {
2800 struct bge_softc *sc = xsc;
2801 struct ifnet *ifp = &sc->arpcom.ac_if;
2802 uint16_t *m;
2803
2804 ASSERT_SERIALIZED(ifp->if_serializer);
2805
2806 if (ifp->if_flags & IFF_RUNNING)
2807 return;
2808
2809 /* Cancel pending I/O and flush buffers. */
2810 bge_stop(sc);
2811 bge_reset(sc);
2812 bge_chipinit(sc);
2813
2814 /*
2815 * Init the various state machines, ring
2816 * control blocks and firmware.
2817 */
2818 if (bge_blockinit(sc)) {
2819 if_printf(ifp, "initialization failure\n");
2820 return;
2821 }
2822
2823 /* Specify MTU. */
2824 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2825 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2826
2827 /* Load our MAC address. */
2828 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2829 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2830 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2831
2832 /* Enable or disable promiscuous mode as needed. */
2833 bge_setpromisc(sc);
2834
2835 /* Program multicast filter. */
2836 bge_setmulti(sc);
2837
2838 /* Init RX ring. */
2839 bge_init_rx_ring_std(sc);
2840
2841 /*
2842 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2843 * memory to insure that the chip has in fact read the first
2844 * entry of the ring.
2845 */
2846 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2847 uint32_t v, i;
2848 for (i = 0; i < 10; i++) {
2849 DELAY(20);
2850 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2851 if (v == (MCLBYTES - ETHER_ALIGN))
2852 break;
2853 }
2854 if (i == 10)
2855 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2856 }
2857
2858 /* Init jumbo RX ring. */
2859 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2860 bge_init_rx_ring_jumbo(sc);
2861
2862 /* Init our RX return ring index */
2863 sc->bge_rx_saved_considx = 0;
2864
2865 /* Init TX ring. */
2866 bge_init_tx_ring(sc);
2867
2868 /* Turn on transmitter */
2869 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2870
2871 /* Turn on receiver */
2872 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2873
2874 /* Tell firmware we're alive. */
2875 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2876
2877 /* Enable host interrupts. */
2878 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2879 #ifdef DEVICE_POLLING
2880 if ((ifp->if_flags & IFF_POLLING) == 0)
2881 #endif
2882 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2883 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2884
2885 bge_ifmedia_upd(ifp);
2886
2887 ifp->if_flags |= IFF_RUNNING;
2888 ifp->if_flags &= ~IFF_OACTIVE;
2889
2890 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2891 }
2892
2893 /*
2894 * Set media options.
2895 */
2896 static int
2897 bge_ifmedia_upd(struct ifnet *ifp)
2898 {
2899 struct bge_softc *sc = ifp->if_softc;
2900
2901 /* If this is a 1000baseX NIC, enable the TBI port. */
2902 if (sc->bge_flags & BGE_FLAG_TBI) {
2903 struct ifmedia *ifm = &sc->bge_ifmedia;
2904
2905 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2906 return(EINVAL);
2907
2908 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2909 case IFM_AUTO:
2910 /*
2911 * The BCM5704 ASIC appears to have a special
2912 * mechanism for programming the autoneg
2913 * advertisement registers in TBI mode.
2914 */
2915 if (!bge_fake_autoneg &&
2916 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2917 uint32_t sgdig;
2918
2919 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2920 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2921 sgdig |= BGE_SGDIGCFG_AUTO |
2922 BGE_SGDIGCFG_PAUSE_CAP |
2923 BGE_SGDIGCFG_ASYM_PAUSE;
2924 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2925 sgdig | BGE_SGDIGCFG_SEND);
2926 DELAY(5);
2927 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2928 }
2929 break;
2930 case IFM_1000_SX:
2931 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2932 BGE_CLRBIT(sc, BGE_MAC_MODE,
2933 BGE_MACMODE_HALF_DUPLEX);
2934 } else {
2935 BGE_SETBIT(sc, BGE_MAC_MODE,
2936 BGE_MACMODE_HALF_DUPLEX);
2937 }
2938 break;
2939 default:
2940 return(EINVAL);
2941 }
2942 } else {
2943 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2944
2945 sc->bge_link_evt++;
2946 sc->bge_link = 0;
2947 if (mii->mii_instance) {
2948 struct mii_softc *miisc;
2949
2950 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2951 mii_phy_reset(miisc);
2952 }
2953 mii_mediachg(mii);
2954 }
2955 return(0);
2956 }
2957
2958 /*
2959 * Report current media status.
2960 */
2961 static void
2962 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2963 {
2964 struct bge_softc *sc = ifp->if_softc;
2965
2966 if (sc->bge_flags & BGE_FLAG_TBI) {
2967 ifmr->ifm_status = IFM_AVALID;
2968 ifmr->ifm_active = IFM_ETHER;
2969 if (CSR_READ_4(sc, BGE_MAC_STS) &
2970 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2971 ifmr->ifm_status |= IFM_ACTIVE;
2972 } else {
2973 ifmr->ifm_active |= IFM_NONE;
2974 return;
2975 }
2976
2977 ifmr->ifm_active |= IFM_1000_SX;
2978 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2979 ifmr->ifm_active |= IFM_HDX;
2980 else
2981 ifmr->ifm_active |= IFM_FDX;
2982 } else {
2983 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2984
2985 mii_pollstat(mii);
2986 ifmr->ifm_active = mii->mii_media_active;
2987 ifmr->ifm_status = mii->mii_media_status;
2988 }
2989 }
2990
2991 static int
2992 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2993 {
2994 struct bge_softc *sc = ifp->if_softc;
2995 struct ifreq *ifr = (struct ifreq *)data;
2996 int mask, error = 0;
2997
2998 ASSERT_SERIALIZED(ifp->if_serializer);
2999
3000 switch (command) {
3001 case SIOCSIFMTU:
3002 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3003 (BGE_IS_JUMBO_CAPABLE(sc) &&
3004 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3005 error = EINVAL;
3006 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3007 ifp->if_mtu = ifr->ifr_mtu;
3008 ifp->if_flags &= ~IFF_RUNNING;
3009 bge_init(sc);
3010 }
3011 break;
3012 case SIOCSIFFLAGS:
3013 if (ifp->if_flags & IFF_UP) {
3014 if (ifp->if_flags & IFF_RUNNING) {
3015 mask = ifp->if_flags ^ sc->bge_if_flags;
3016
3017 /*
3018 * If only the state of the PROMISC flag
3019 * changed, then just use the 'set promisc
3020 * mode' command instead of reinitializing
3021 * the entire NIC. Doing a full re-init
3022 * means reloading the firmware and waiting
3023 * for it to start up, which may take a
3024 * second or two. Similarly for ALLMULTI.
3025 */
3026 if (mask & IFF_PROMISC)
3027 bge_setpromisc(sc);
3028 if (mask & IFF_ALLMULTI)
3029 bge_setmulti(sc);
3030 } else {
3031 bge_init(sc);
3032 }
3033 } else {
3034 if (ifp->if_flags & IFF_RUNNING)
3035 bge_stop(sc);
3036 }
3037 sc->bge_if_flags = ifp->if_flags;
3038 break;
3039 case SIOCADDMULTI:
3040 case SIOCDELMULTI:
3041 if (ifp->if_flags & IFF_RUNNING)
3042 bge_setmulti(sc);
3043 break;
3044 case SIOCSIFMEDIA:
3045 case SIOCGIFMEDIA:
3046 if (sc->bge_flags & BGE_FLAG_TBI) {
3047 error = ifmedia_ioctl(ifp, ifr,
3048 &sc->bge_ifmedia, command);
3049 } else {
3050 struct mii_data *mii;
3051
3052 mii = device_get_softc(sc->bge_miibus);
3053 error = ifmedia_ioctl(ifp, ifr,
3054 &mii->mii_media, command);
3055 }
3056 break;
3057 case SIOCSIFCAP:
3058 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3059 if (mask & IFCAP_HWCSUM) {
3060 ifp->if_capenable ^= IFCAP_HWCSUM;
3061 if (IFCAP_HWCSUM & ifp->if_capenable)
3062 ifp->if_hwassist = BGE_CSUM_FEATURES;
3063 else
3064 ifp->if_hwassist = 0;
3065 }
3066 break;
3067 default:
3068 error = ether_ioctl(ifp, command, data);
3069 break;
3070 }
3071 return error;
3072 }
3073
3074 static void
3075 bge_watchdog(struct ifnet *ifp)
3076 {
3077 struct bge_softc *sc = ifp->if_softc;
3078
3079 if_printf(ifp, "watchdog timeout -- resetting\n");
3080
3081 ifp->if_flags &= ~IFF_RUNNING;
3082 bge_init(sc);
3083
3084 ifp->if_oerrors++;
3085
3086 if (!ifq_is_empty(&ifp->if_snd))
3087 ifp->if_start(ifp);
3088 }
3089
3090 /*
3091 * Stop the adapter and free any mbufs allocated to the
3092 * RX and TX lists.
3093 */
3094 static void
3095 bge_stop(struct bge_softc *sc)
3096 {
3097 struct ifnet *ifp = &sc->arpcom.ac_if;
3098 struct ifmedia_entry *ifm;
3099 struct mii_data *mii = NULL;
3100 int mtmp, itmp;
3101
3102 ASSERT_SERIALIZED(ifp->if_serializer);
3103
3104 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3105 mii = device_get_softc(sc->bge_miibus);
3106
3107 callout_stop(&sc->bge_stat_timer);
3108
3109 /*
3110 * Disable all of the receiver blocks
3111 */
3112 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3113 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3114 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3115 if (!BGE_IS_5705_PLUS(sc))
3116 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3117 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3118 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3119 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3120
3121 /*
3122 * Disable all of the transmit blocks
3123 */
3124 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3125 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3126 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3127 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3128 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3129 if (!BGE_IS_5705_PLUS(sc))
3130 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3131 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3132
3133 /*
3134 * Shut down all of the memory managers and related
3135 * state machines.
3136 */
3137 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3138 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3139 if (!BGE_IS_5705_PLUS(sc))
3140 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3141 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3142 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3143 if (!BGE_IS_5705_PLUS(sc)) {
3144 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3145 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3146 }
3147
3148 /* Disable host interrupts. */
3149 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3150 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3151
3152 /*
3153 * Tell firmware we're shutting down.
3154 */
3155 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3156
3157 /* Free the RX lists. */
3158 bge_free_rx_ring_std(sc);
3159
3160 /* Free jumbo RX list. */
3161 if (BGE_IS_JUMBO_CAPABLE(sc))
3162 bge_free_rx_ring_jumbo(sc);
3163
3164 /* Free TX buffers. */
3165 bge_free_tx_ring(sc);
3166
3167 /*
3168 * Isolate/power down the PHY, but leave the media selection
3169 * unchanged so that things will be put back to normal when
3170 * we bring the interface back up.
3171 */
3172 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3173 itmp = ifp->if_flags;
3174 ifp->if_flags |= IFF_UP;
3175 ifm = mii->mii_media.ifm_cur;
3176 mtmp = ifm->ifm_media;
3177 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3178 mii_mediachg(mii);
3179 ifm->ifm_media = mtmp;
3180 ifp->if_flags = itmp;
3181 }
3182
3183 sc->bge_link = 0;
3184 sc->bge_coal_chg = 0;
3185
3186 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3187
3188 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3189 ifp->if_timer = 0;
3190 }
3191
3192 /*
3193 * Stop all chip I/O so that the kernel's probe routines don't
3194 * get confused by errant DMAs when rebooting.
3195 */
3196 static void
3197 bge_shutdown(device_t dev)
3198 {
3199 struct bge_softc *sc = device_get_softc(dev);
3200 struct ifnet *ifp = &sc->arpcom.ac_if;
3201
3202 lwkt_serialize_enter(ifp->if_serializer);
3203 bge_stop(sc);
3204 bge_reset(sc);
3205 lwkt_serialize_exit(ifp->if_serializer);
3206 }
3207
3208 static int
3209 bge_suspend(device_t dev)
3210 {
3211 struct bge_softc *sc = device_get_softc(dev);
3212 struct ifnet *ifp = &sc->arpcom.ac_if;
3213
3214 lwkt_serialize_enter(ifp->if_serializer);
3215 bge_stop(sc);
3216 lwkt_serialize_exit(ifp->if_serializer);
3217
3218 return 0;
3219 }
3220
3221 static int
3222 bge_resume(device_t dev)
3223 {
3224 struct bge_softc *sc = device_get_softc(dev);
3225 struct ifnet *ifp = &sc->arpcom.ac_if;
3226
3227 lwkt_serialize_enter(ifp->if_serializer);
3228
3229 if (ifp->if_flags & IFF_UP) {
3230 bge_init(sc);
3231
3232 if (!ifq_is_empty(&ifp->if_snd))
3233 ifp->if_start(ifp);
3234 }
3235
3236 lwkt_serialize_exit(ifp->if_serializer);
3237
3238 return 0;
3239 }
3240
3241 static void
3242 bge_setpromisc(struct bge_softc *sc)
3243 {
3244 struct ifnet *ifp = &sc->arpcom.ac_if;
3245
3246 if (ifp->if_flags & IFF_PROMISC)
3247 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3248 else
3249 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3250 }
3251
3252 static void
3253 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3254 {
3255 struct bge_dmamap_arg *ctx = arg;
3256
3257 if (error)
3258 return;
3259
3260 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3261 ("only one segment is allowed\n"));
3262
3263 ctx->bge_segs[0] = *segs;
3264 }
3265
3266 static void
3267 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3268 bus_size_t mapsz __unused, int error)
3269 {
3270 struct bge_dmamap_arg *ctx = arg;
3271 int i;
3272
3273 if (error)
3274 return;
3275
3276 if (nsegs > ctx->bge_maxsegs) {
3277 ctx->bge_maxsegs = 0;
3278 return;
3279 }
3280
3281 ctx->bge_maxsegs = nsegs;
3282 for (i = 0; i < nsegs; ++i)
3283 ctx->bge_segs[i] = segs[i];
3284 }
3285
3286 static void
3287 bge_dma_free(struct bge_softc *sc)
3288 {
3289 int i;
3290
3291 /* Destroy RX/TX mbuf DMA stuffs. */
3292 if (sc->bge_cdata.bge_mtag != NULL) {
3293 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3294 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3295 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3296 sc->bge_cdata.bge_rx_std_dmamap[i]);
3297 }
3298 }
3299
3300 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3301 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3302 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3303 sc->bge_cdata.bge_tx_dmamap[i]);
3304 }
3305 }
3306 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3307 }
3308
3309 /* Destroy standard RX ring */
3310 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3311 sc->bge_cdata.bge_rx_std_ring_map,
3312 sc->bge_ldata.bge_rx_std_ring);
3313
3314 if (BGE_IS_JUMBO_CAPABLE(sc))
3315 bge_free_jumbo_mem(sc);
3316
3317 /* Destroy RX return ring */
3318 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3319 sc->bge_cdata.bge_rx_return_ring_map,
3320 sc->bge_ldata.bge_rx_return_ring);
3321
3322 /* Destroy TX ring */
3323 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3324 sc->bge_cdata.bge_tx_ring_map,
3325 sc->bge_ldata.bge_tx_ring);
3326
3327 /* Destroy status block */
3328 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3329 sc->bge_cdata.bge_status_map,
3330 sc->bge_ldata.bge_status_block);
3331
3332 /* Destroy statistics block */
3333 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3334 sc->bge_cdata.bge_stats_map,
3335 sc->bge_ldata.bge_stats);
3336
3337 /* Destroy the parent tag */
3338 if (sc->bge_cdata.bge_parent_tag != NULL)
3339 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3340 }
3341
3342 static int
3343 bge_dma_alloc(struct bge_softc *sc)
3344 {
3345 struct ifnet *ifp = &sc->arpcom.ac_if;
3346 int nseg, i, error;
3347
3348 /*
3349 * Allocate the parent bus DMA tag appropriate for PCI.
3350 */
3351 error = bus_dma_tag_create(NULL, 1, 0,
3352 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3353 NULL, NULL,
3354 MAXBSIZE, BGE_NSEG_NEW,
3355 BUS_SPACE_MAXSIZE_32BIT,
3356 0, &sc->bge_cdata.bge_parent_tag);
3357 if (error) {
3358 if_printf(ifp, "could not allocate parent dma tag\n");
3359 return error;
3360 }
3361
3362 /*
3363 * Create DMA tag for mbufs.
3364 */
3365 nseg = BGE_NSEG_NEW;
3366 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3367 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3368 NULL, NULL,
3369 MCLBYTES * nseg, nseg, MCLBYTES,
3370 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3371 if (error) {
3372 if_printf(ifp, "could not allocate mbuf dma tag\n");
3373 return error;
3374 }
3375
3376 /*
3377 * Create DMA maps for TX/RX mbufs.
3378 */
3379 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3380 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3381 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3382 if (error) {
3383 int j;
3384
3385 for (j = 0; j < i; ++j) {
3386 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3387 sc->bge_cdata.bge_rx_std_dmamap[j]);
3388 }
3389 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3390 sc->bge_cdata.bge_mtag = NULL;
3391
3392 if_printf(ifp, "could not create DMA map for RX\n");
3393 return error;
3394 }
3395 }
3396
3397 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3398 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3399 &sc->bge_cdata.bge_tx_dmamap[i]);
3400 if (error) {
3401 int j;
3402
3403 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3404 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3405 sc->bge_cdata.bge_rx_std_dmamap[j]);
3406 }
3407 for (j = 0; j < i; ++j) {
3408 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3409 sc->bge_cdata.bge_tx_dmamap[j]);
3410 }
3411 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3412 sc->bge_cdata.bge_mtag = NULL;
3413
3414 if_printf(ifp, "could not create DMA map for TX\n");
3415 return error;
3416 }
3417 }
3418
3419 /*
3420 * Create DMA stuffs for standard RX ring.
3421 */
3422 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3423 &sc->bge_cdata.bge_rx_std_ring_tag,
3424 &sc->bge_cdata.bge_rx_std_ring_map,
3425 (void **)&sc->bge_ldata.bge_rx_std_ring,
3426 &sc->bge_ldata.bge_rx_std_ring_paddr);
3427 if (error) {
3428 if_printf(ifp, "could not create std RX ring\n");
3429 return error;
3430 }
3431
3432 /*
3433 * Create jumbo buffer pool.
3434 */
3435 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3436 error = bge_alloc_jumbo_mem(sc);
3437 if (error) {
3438 if_printf(ifp, "could not create jumbo buffer pool\n");
3439 return error;
3440 }
3441 }
3442
3443 /*
3444 * Create DMA stuffs for RX return ring.
3445 */
3446 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3447 &sc->bge_cdata.bge_rx_return_ring_tag,
3448 &sc->bge_cdata.bge_rx_return_ring_map,
3449 (void **)&sc->bge_ldata.bge_rx_return_ring,
3450 &sc->bge_ldata.bge_rx_return_ring_paddr);
3451 if (error) {
3452 if_printf(ifp, "could not create RX ret ring\n");
3453 return error;
3454 }
3455
3456 /*
3457 * Create DMA stuffs for TX ring.
3458 */
3459 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3460 &sc->bge_cdata.bge_tx_ring_tag,
3461 &sc->bge_cdata.bge_tx_ring_map,
3462 (void **)&sc->bge_ldata.bge_tx_ring,
3463 &sc->bge_ldata.bge_tx_ring_paddr);
3464 if (error) {
3465 if_printf(ifp, "could not create TX ring\n");
3466 return error;
3467 }
3468
3469 /*
3470 * Create DMA stuffs for status block.
3471 */
3472 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3473 &sc->bge_cdata.bge_status_tag,
3474 &sc->bge_cdata.bge_status_map,
3475 (void **)&sc->bge_ldata.bge_status_block,
3476 &sc->bge_ldata.bge_status_block_paddr);
3477 if (error) {
3478 if_printf(ifp, "could not create status block\n");
3479 return error;
3480 }
3481
3482 /*
3483 * Create DMA stuffs for statistics block.
3484 */
3485 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3486 &sc->bge_cdata.bge_stats_tag,
3487 &sc->bge_cdata.bge_stats_map,
3488 (void **)&sc->bge_ldata.bge_stats,
3489 &sc->bge_ldata.bge_stats_paddr);
3490 if (error) {
3491 if_printf(ifp, "could not create stats block\n");
3492 return error;
3493 }
3494 return 0;
3495 }
3496
3497 static int
3498 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3499 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3500 {
3501 struct ifnet *ifp = &sc->arpcom.ac_if;
3502 struct bge_dmamap_arg ctx;
3503 bus_dma_segment_t seg;
3504 int error;
3505
3506 /*
3507 * Create DMA tag
3508 */
3509 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3510 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3511 NULL, NULL, size, 1, size, 0, tag);
3512 if (error) {
3513 if_printf(ifp, "could not allocate dma tag\n");
3514 return error;
3515 }
3516
3517 /*
3518 * Allocate DMA'able memory
3519 */
3520 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3521 map);
3522 if (error) {
3523 if_printf(ifp, "could not allocate dma memory\n");
3524 bus_dma_tag_destroy(*tag);
3525 *tag = NULL;
3526 return error;
3527 }
3528
3529 /*
3530 * Load the DMA'able memory
3531 */
3532 ctx.bge_maxsegs = 1;
3533 ctx.bge_segs = &seg;
3534 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3535 BUS_DMA_WAITOK);
3536 if (error) {
3537 if_printf(ifp, "could not load dma memory\n");
3538 bus_dmamem_free(*tag, *addr, *map);
3539 bus_dma_tag_destroy(*tag);
3540 *tag = NULL;
3541 return error;
3542 }
3543 *paddr = ctx.bge_segs[0].ds_addr;
3544
3545 return 0;
3546 }
3547
3548 static void
3549 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3550 {
3551 if (tag != NULL) {
3552 bus_dmamap_unload(tag, map);
3553 bus_dmamem_free(tag, addr, map);
3554 bus_dma_tag_destroy(tag);
3555 }
3556 }
3557
3558 /*
3559 * Grrr. The link status word in the status block does
3560 * not work correctly on the BCM5700 rev AX and BX chips,
3561 * according to all available information. Hence, we have
3562 * to enable MII interrupts in order to properly obtain
3563 * async link changes. Unfortunately, this also means that
3564 * we have to read the MAC status register to detect link
3565 * changes, thereby adding an additional register access to
3566 * the interrupt handler.
3567 *
3568 * XXX: perhaps link state detection procedure used for
3569 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3570 */
3571 static void
3572 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3573 {
3574 struct ifnet *ifp = &sc->arpcom.ac_if;
3575 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3576
3577 mii_pollstat(mii);
3578
3579 if (!sc->bge_link &&
3580 (mii->mii_media_status & IFM_ACTIVE) &&
3581 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3582 sc->bge_link++;
3583 if (bootverbose)
3584 if_printf(ifp, "link UP\n");
3585 } else if (sc->bge_link &&
3586 (!(mii->mii_media_status & IFM_ACTIVE) ||
3587 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3588 sc->bge_link = 0;
3589 if (bootverbose)
3590 if_printf(ifp, "link DOWN\n");
3591 }
3592
3593 /* Clear the interrupt. */
3594 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3595 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3596 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3597 }
3598
3599 static void
3600 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3601 {
3602 struct ifnet *ifp = &sc->arpcom.ac_if;
3603
3604 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3605
3606 /*
3607 * Sometimes PCS encoding errors are detected in
3608 * TBI mode (on fiber NICs), and for some reason
3609 * the chip will signal them as link changes.
3610 * If we get a link change event, but the 'PCS
3611 * encoding error' bit in the MAC status register
3612 * is set, don't bother doing a link check.
3613 * This avoids spurious "gigabit link up" messages
3614 * that sometimes appear on fiber NICs during
3615 * periods of heavy traffic.
3616 */
3617 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3618 if (!sc->bge_link) {
3619 sc->bge_link++;
3620 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3621 BGE_CLRBIT(sc, BGE_MAC_MODE,
3622 BGE_MACMODE_TBI_SEND_CFGS);
3623 }
3624 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3625
3626 if (bootverbose)
3627 if_printf(ifp, "link UP\n");
3628
3629 ifp->if_link_state = LINK_STATE_UP;
3630 if_link_state_change(ifp);
3631 }
3632 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3633 if (sc->bge_link) {
3634 sc->bge_link = 0;
3635
3636 if (bootverbose)
3637 if_printf(ifp, "link DOWN\n");
3638
3639 ifp->if_link_state = LINK_STATE_DOWN;
3640 if_link_state_change(ifp);
3641 }
3642 }
3643
3644 #undef PCS_ENCODE_ERR
3645
3646 /* Clear the attention. */
3647 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3648 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3649 BGE_MACSTAT_LINK_CHANGED);
3650 }
3651
3652 static void
3653 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3654 {
3655 /*
3656 * Check that the AUTOPOLL bit is set before
3657 * processing the event as a real link change.
3658 * Turning AUTOPOLL on and off in the MII read/write
3659 * functions will often trigger a link status
3660 * interrupt for no reason.
3661 */
3662 if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3663 struct ifnet *ifp = &sc->arpcom.ac_if;
3664 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3665
3666 mii_pollstat(mii);
3667
3668 if (!sc->bge_link &&
3669 (mii->mii_media_status & IFM_ACTIVE) &&
3670 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3671 sc->bge_link++;
3672 if (bootverbose)
3673 if_printf(ifp, "link UP\n");
3674 } else if (sc->bge_link &&
3675 (!(mii->mii_media_status & IFM_ACTIVE) ||
3676 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3677 sc->bge_link = 0;
3678 if (bootverbose)
3679 if_printf(ifp, "link DOWN\n");
3680 }
3681 }
3682
3683 /* Clear the attention. */
3684 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3685 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3686 BGE_MACSTAT_LINK_CHANGED);
3687 }
3688
3689 static int
3690 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3691 {
3692 struct bge_softc *sc = arg1;
3693
3694 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3695 &sc->bge_rx_coal_ticks,
3696 BGE_RX_COAL_TICKS_CHG);
3697 }
3698
3699 static int
3700 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3701 {
3702 struct bge_softc *sc = arg1;
3703
3704 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3705 &sc->bge_tx_coal_ticks,
3706 BGE_TX_COAL_TICKS_CHG);
3707 }
3708
3709 static int
3710 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3711 {
3712 struct bge_softc *sc = arg1;
3713
3714 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3715 &sc->bge_rx_max_coal_bds,
3716 BGE_RX_MAX_COAL_BDS_CHG);
3717 }
3718
3719 static int
3720 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3721 {
3722 struct bge_softc *sc = arg1;
3723
3724 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3725 &sc->bge_tx_max_coal_bds,
3726 BGE_TX_MAX_COAL_BDS_CHG);
3727 }
3728
3729 static int
3730 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3731 uint32_t coal_chg_mask)
3732 {
3733 struct bge_softc *sc = arg1;
3734 struct ifnet *ifp = &sc->arpcom.ac_if;
3735 int error = 0, v;
3736
3737 lwkt_serialize_enter(ifp->if_serializer);
3738
3739 v = *coal;
3740 error = sysctl_handle_int(oidp, &v, 0, req);
3741 if (!error && req->newptr != NULL) {
3742 if (v < 0) {
3743 error = EINVAL;
3744 } else {
3745 *coal = v;
3746 sc->bge_coal_chg |= coal_chg_mask;
3747 }
3748 }
3749
3750 lwkt_serialize_exit(ifp->if_serializer);
3751 return error;
3752 }
3753
3754 static void
3755 bge_coal_change(struct bge_softc *sc)
3756 {
3757 struct ifnet *ifp = &sc->arpcom.ac_if;
3758 uint32_t val;
3759
3760 ASSERT_SERIALIZED(ifp->if_serializer);
3761
3762 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3763 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3764 sc->bge_rx_coal_ticks);
3765 DELAY(10);
3766 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3767
3768 if (bootverbose) {
3769 if_printf(ifp, "rx_coal_ticks -> %u\n",
3770 sc->bge_rx_coal_ticks);
3771 }
3772 }
3773
3774 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3775 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3776 sc->bge_tx_coal_ticks);
3777 DELAY(10);
3778 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3779
3780 if (bootverbose) {
3781 if_printf(ifp, "tx_coal_ticks -> %u\n",
3782 sc->bge_tx_coal_ticks);
3783 }
3784 }
3785
3786 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3787 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3788 sc->bge_rx_max_coal_bds);
3789 DELAY(10);
3790 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3791
3792 if (bootverbose) {
3793 if_printf(ifp, "rx_max_coal_bds -> %u\n",
3794 sc->bge_rx_max_coal_bds);
3795 }
3796 }
3797
3798 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3799 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3800 sc->bge_tx_max_coal_bds);
3801 DELAY(10);
3802 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3803
3804 if (bootverbose) {
3805 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3806 sc->bge_tx_max_coal_bds);
3807 }
3808 }
3809
3810 sc->bge_coal_chg = 0;
3811 }
DragonFly vkernel multiprocessor port