3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/dev/vge/if_vge.c,v 1.24 2006/02/14 12:44:56 glebius Exp $
33 * $DragonFly: src/sys/dev/netif/vge/if_vge.c,v 1.4 2007/03/24 08:42:42 sephe Exp $
37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
46 * combines a tri-speed ethernet MAC and PHY, with the following
49 * o Jumbo frame support up to 16K
50 * o Transmit and receive flow control
51 * o IPv4 checksum offload
52 * o VLAN tag insertion and stripping
54 * o 64-bit multicast hash table filter
55 * o 64 entry CAM filter
56 * o 16K RX FIFO and 48K TX FIFO memory
57 * o Interrupt moderation
59 * The VT6122 supports up to four transmit DMA queues. The descriptors
60 * in the transmit ring can address up to 7 data fragments; frames which
61 * span more than 7 data buffers must be coalesced, but in general the
62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
63 * long. The receive descriptors address only a single buffer.
65 * There are two peculiar design issues with the VT6122. One is that
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
68 * systems, but on architectures that generate unaligned access traps, we
69 * have to do some copying.
71 * The other issue has to do with the way 64-bit addresses are handled.
72 * The DMA descriptors only allow you to specify 48 bits of addressing
73 * information. The remaining 16 bits are specified using one of the
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
76 * memory, you must have to make sure your network data buffers reside
77 * in the same 48-bit 'segment.'
79 * Special thanks to Ryan Fu at VIA Networking for providing documentation
80 * and sample NICs for testing.
83 #include "opt_polling.h"
85 #include <sys/param.h>
86 #include <sys/endian.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/serialize.h>
100 #include <net/if_arp.h>
101 #include <net/ethernet.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104 #include <net/ifq_var.h>
105 #include <net/if_types.h>
106 #include <net/vlan/if_vlan_var.h>
110 #include <dev/netif/mii_layer/mii.h>
111 #include <dev/netif/mii_layer/miivar.h>
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
115 #include <bus/pci/pcidevs.h>
117 #include "miibus_if.h"
119 #include <dev/netif/vge/if_vgereg.h>
120 #include <dev/netif/vge/if_vgevar.h>
122 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
125 * Various supported device vendors/types and their names.
127 static const struct vge_type vge_devs
[] = {
128 { PCI_VENDOR_VIATECH
, PCI_PRODUCT_VIATECH_VT612X
,
129 "VIA Networking Gigabit Ethernet" },
133 static int vge_probe (device_t
);
134 static int vge_attach (device_t
);
135 static int vge_detach (device_t
);
137 static int vge_encap (struct vge_softc
*, struct mbuf
*, int);
139 static void vge_dma_map_addr (void *, bus_dma_segment_t
*, int, int);
140 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t
*, int,
142 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t
*, int,
144 static int vge_dma_alloc (device_t
);
145 static void vge_dma_free (struct vge_softc
*);
146 static int vge_newbuf (struct vge_softc
*, int, struct mbuf
*);
147 static int vge_rx_list_init (struct vge_softc
*);
148 static int vge_tx_list_init (struct vge_softc
*);
150 static __inline
void vge_fixup_rx
153 static void vge_rxeof (struct vge_softc
*, int);
154 static void vge_txeof (struct vge_softc
*);
155 static void vge_intr (void *);
156 static void vge_tick (struct vge_softc
*);
157 static void vge_start (struct ifnet
*);
158 static int vge_ioctl (struct ifnet
*, u_long
, caddr_t
,
160 static void vge_init (void *);
161 static void vge_stop (struct vge_softc
*);
162 static void vge_watchdog (struct ifnet
*);
163 static int vge_suspend (device_t
);
164 static int vge_resume (device_t
);
165 static void vge_shutdown (device_t
);
166 static int vge_ifmedia_upd (struct ifnet
*);
167 static void vge_ifmedia_sts (struct ifnet
*, struct ifmediareq
*);
170 static void vge_eeprom_getword (struct vge_softc
*, int, u_int16_t
*);
172 static void vge_read_eeprom (struct vge_softc
*, uint8_t *, int, int, int);
174 static void vge_miipoll_start (struct vge_softc
*);
175 static void vge_miipoll_stop (struct vge_softc
*);
176 static int vge_miibus_readreg (device_t
, int, int);
177 static int vge_miibus_writereg (device_t
, int, int, int);
178 static void vge_miibus_statchg (device_t
);
180 static void vge_cam_clear (struct vge_softc
*);
181 static int vge_cam_set (struct vge_softc
*, uint8_t *);
182 static void vge_setmulti (struct vge_softc
*);
183 static void vge_reset (struct vge_softc
*);
185 #ifdef DEVICE_POLLING
186 static void vge_poll(struct ifnet
*, enum poll_cmd
, int);
187 static void vge_disable_intr(struct vge_softc
*);
189 static void vge_enable_intr(struct vge_softc
*, uint32_t);
191 #define VGE_PCI_LOIO 0x10
192 #define VGE_PCI_LOMEM 0x14
194 static device_method_t vge_methods
[] = {
195 /* Device interface */
196 DEVMETHOD(device_probe
, vge_probe
),
197 DEVMETHOD(device_attach
, vge_attach
),
198 DEVMETHOD(device_detach
, vge_detach
),
199 DEVMETHOD(device_suspend
, vge_suspend
),
200 DEVMETHOD(device_resume
, vge_resume
),
201 DEVMETHOD(device_shutdown
, vge_shutdown
),
204 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
205 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
208 DEVMETHOD(miibus_readreg
, vge_miibus_readreg
),
209 DEVMETHOD(miibus_writereg
, vge_miibus_writereg
),
210 DEVMETHOD(miibus_statchg
, vge_miibus_statchg
),
215 static driver_t vge_driver
= {
218 sizeof(struct vge_softc
)
221 static devclass_t vge_devclass
;
223 DECLARE_DUMMY_MODULE(if_vge
);
224 MODULE_DEPEND(if_vge
, miibus
, 1, 1, 1);
225 DRIVER_MODULE(if_vge
, pci
, vge_driver
, vge_devclass
, 0, 0);
226 DRIVER_MODULE(if_vge
, cardbus
, vge_driver
, vge_devclass
, 0, 0);
227 DRIVER_MODULE(miibus
, vge
, miibus_driver
, miibus_devclass
, 0, 0);
231 * Read a word of data stored in the EEPROM at address 'addr.'
234 vge_eeprom_getword(struct vge_softc
*sc
, int addr
, uint16_t dest
)
240 * Enter EEPROM embedded programming mode. In order to
241 * access the EEPROM at all, we first have to set the
242 * EELOAD bit in the CHIPCFG2 register.
244 CSR_SETBIT_1(sc
, VGE_CHIPCFG2
, VGE_CHIPCFG2_EELOAD
);
245 CSR_SETBIT_1(sc
, VGE_EECSR
, VGE_EECSR_EMBP
/*|VGE_EECSR_ECS*/);
247 /* Select the address of the word we want to read */
248 CSR_WRITE_1(sc
, VGE_EEADDR
, addr
);
250 /* Issue read command */
251 CSR_SETBIT_1(sc
, VGE_EECMD
, VGE_EECMD_ERD
);
253 /* Wait for the done bit to be set. */
254 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
255 if (CSR_READ_1(sc
, VGE_EECMD
) & VGE_EECMD_EDONE
)
258 if (i
== VGE_TIMEOUT
) {
259 device_printf(sc
->vge_dev
, "EEPROM read timed out\n");
264 /* Read the result */
265 word
= CSR_READ_2(sc
, VGE_EERDDAT
);
267 /* Turn off EEPROM access mode. */
268 CSR_CLRBIT_1(sc
, VGE_EECSR
, VGE_EECSR_EMBP
/*|VGE_EECSR_ECS*/);
269 CSR_CLRBIT_1(sc
, VGE_CHIPCFG2
, VGE_CHIPCFG2_EELOAD
);
276 * Read a sequence of words from the EEPROM.
279 vge_read_eeprom(struct vge_softc
*sc
, uint8_t *dest
, int off
, int cnt
, int swap
)
283 uint16_t word
= 0, *ptr
;
285 for (i
= 0; i
< cnt
; i
++) {
286 vge_eeprom_getword(sc
, off
+ i
, &word
);
287 ptr
= (uint16_t *)(dest
+ (i
* 2));
294 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
295 dest
[i
] = CSR_READ_1(sc
, VGE_PAR0
+ i
);
300 vge_miipoll_stop(struct vge_softc
*sc
)
304 CSR_WRITE_1(sc
, VGE_MIICMD
, 0);
306 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
308 if (CSR_READ_1(sc
, VGE_MIISTS
) & VGE_MIISTS_IIDL
)
311 if (i
== VGE_TIMEOUT
)
312 if_printf(&sc
->arpcom
.ac_if
, "failed to idle MII autopoll\n");
316 vge_miipoll_start(struct vge_softc
*sc
)
320 /* First, make sure we're idle. */
321 CSR_WRITE_1(sc
, VGE_MIICMD
, 0);
322 CSR_WRITE_1(sc
, VGE_MIIADDR
, VGE_MIIADDR_SWMPL
);
324 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
326 if (CSR_READ_1(sc
, VGE_MIISTS
) & VGE_MIISTS_IIDL
)
329 if (i
== VGE_TIMEOUT
) {
330 if_printf(&sc
->arpcom
.ac_if
, "failed to idle MII autopoll\n");
334 /* Now enable auto poll mode. */
335 CSR_WRITE_1(sc
, VGE_MIICMD
, VGE_MIICMD_MAUTO
);
337 /* And make sure it started. */
338 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
340 if ((CSR_READ_1(sc
, VGE_MIISTS
) & VGE_MIISTS_IIDL
) == 0)
343 if (i
== VGE_TIMEOUT
)
344 if_printf(&sc
->arpcom
.ac_if
, "failed to start MII autopoll\n");
348 vge_miibus_readreg(device_t dev
, int phy
, int reg
)
350 struct vge_softc
*sc
;
354 sc
= device_get_softc(dev
);
356 if (phy
!= (CSR_READ_1(sc
, VGE_MIICFG
) & 0x1F))
359 vge_miipoll_stop(sc
);
361 /* Specify the register we want to read. */
362 CSR_WRITE_1(sc
, VGE_MIIADDR
, reg
);
364 /* Issue read command. */
365 CSR_SETBIT_1(sc
, VGE_MIICMD
, VGE_MIICMD_RCMD
);
367 /* Wait for the read command bit to self-clear. */
368 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
370 if ((CSR_READ_1(sc
, VGE_MIICMD
) & VGE_MIICMD_RCMD
) == 0)
373 if (i
== VGE_TIMEOUT
)
374 if_printf(&sc
->arpcom
.ac_if
, "MII read timed out\n");
376 rval
= CSR_READ_2(sc
, VGE_MIIDATA
);
378 vge_miipoll_start(sc
);
384 vge_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
386 struct vge_softc
*sc
;
389 sc
= device_get_softc(dev
);
391 if (phy
!= (CSR_READ_1(sc
, VGE_MIICFG
) & 0x1F))
394 vge_miipoll_stop(sc
);
396 /* Specify the register we want to write. */
397 CSR_WRITE_1(sc
, VGE_MIIADDR
, reg
);
399 /* Specify the data we want to write. */
400 CSR_WRITE_2(sc
, VGE_MIIDATA
, data
);
402 /* Issue write command. */
403 CSR_SETBIT_1(sc
, VGE_MIICMD
, VGE_MIICMD_WCMD
);
405 /* Wait for the write command bit to self-clear. */
406 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
408 if ((CSR_READ_1(sc
, VGE_MIICMD
) & VGE_MIICMD_WCMD
) == 0)
411 if (i
== VGE_TIMEOUT
) {
412 if_printf(&sc
->arpcom
.ac_if
, "MII write timed out\n");
416 vge_miipoll_start(sc
);
422 vge_cam_clear(struct vge_softc
*sc
)
427 * Turn off all the mask bits. This tells the chip
428 * that none of the entries in the CAM filter are valid.
429 * desired entries will be enabled as we fill the filter in.
431 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
432 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_CAMMASK
);
433 CSR_WRITE_1(sc
, VGE_CAMADDR
, VGE_CAMADDR_ENABLE
);
434 for (i
= 0; i
< 8; i
++)
435 CSR_WRITE_1(sc
, VGE_CAM0
+ i
, 0);
437 /* Clear the VLAN filter too. */
438 CSR_WRITE_1(sc
, VGE_CAMADDR
, VGE_CAMADDR_ENABLE
|VGE_CAMADDR_AVSEL
|0);
439 for (i
= 0; i
< 8; i
++)
440 CSR_WRITE_1(sc
, VGE_CAM0
+ i
, 0);
442 CSR_WRITE_1(sc
, VGE_CAMADDR
, 0);
443 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
444 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_MAR
);
450 vge_cam_set(struct vge_softc
*sc
, uint8_t *addr
)
454 if (sc
->vge_camidx
== VGE_CAM_MAXADDRS
)
457 /* Select the CAM data page. */
458 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
459 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_CAMDATA
);
461 /* Set the filter entry we want to update and enable writing. */
462 CSR_WRITE_1(sc
, VGE_CAMADDR
, VGE_CAMADDR_ENABLE
|sc
->vge_camidx
);
464 /* Write the address to the CAM registers */
465 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
466 CSR_WRITE_1(sc
, VGE_CAM0
+ i
, addr
[i
]);
468 /* Issue a write command. */
469 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_WRITE
);
471 /* Wake for it to clear. */
472 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
474 if ((CSR_READ_1(sc
, VGE_CAMCTL
) & VGE_CAMCTL_WRITE
) == 0)
477 if (i
== VGE_TIMEOUT
) {
478 if_printf(&sc
->arpcom
.ac_if
, "setting CAM filter failed\n");
483 /* Select the CAM mask page. */
484 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
485 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_CAMMASK
);
487 /* Set the mask bit that enables this filter. */
488 CSR_SETBIT_1(sc
, VGE_CAM0
+ (sc
->vge_camidx
/8),
489 1<<(sc
->vge_camidx
& 7));
494 /* Turn off access to CAM. */
495 CSR_WRITE_1(sc
, VGE_CAMADDR
, 0);
496 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
497 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_MAR
);
503 * Program the multicast filter. We use the 64-entry CAM filter
504 * for perfect filtering. If there's more than 64 multicast addresses,
505 * we use the hash filter insted.
508 vge_setmulti(struct vge_softc
*sc
)
510 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
512 struct ifmultiaddr
*ifma
;
513 uint32_t h
, hashes
[2] = { 0, 0 };
515 /* First, zot all the multicast entries. */
517 CSR_WRITE_4(sc
, VGE_MAR0
, 0);
518 CSR_WRITE_4(sc
, VGE_MAR1
, 0);
521 * If the user wants allmulti or promisc mode, enable reception
522 * of all multicast frames.
524 if (ifp
->if_flags
& IFF_ALLMULTI
|| ifp
->if_flags
& IFF_PROMISC
) {
525 CSR_WRITE_4(sc
, VGE_MAR0
, 0xFFFFFFFF);
526 CSR_WRITE_4(sc
, VGE_MAR1
, 0xFFFFFFFF);
530 /* Now program new ones */
531 LIST_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
532 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
534 error
= vge_cam_set(sc
,
535 LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
));
540 /* If there were too many addresses, use the hash filter. */
544 LIST_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
545 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
547 h
= ether_crc32_be(LLADDR((struct sockaddr_dl
*)
548 ifma
->ifma_addr
), ETHER_ADDR_LEN
) >> 26;
550 hashes
[0] |= (1 << h
);
552 hashes
[1] |= (1 << (h
- 32));
555 CSR_WRITE_4(sc
, VGE_MAR0
, hashes
[0]);
556 CSR_WRITE_4(sc
, VGE_MAR1
, hashes
[1]);
561 vge_reset(struct vge_softc
*sc
)
565 CSR_WRITE_1(sc
, VGE_CRS1
, VGE_CR1_SOFTRESET
);
567 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
569 if ((CSR_READ_1(sc
, VGE_CRS1
) & VGE_CR1_SOFTRESET
) == 0)
573 if (i
== VGE_TIMEOUT
) {
574 if_printf(&sc
->arpcom
.ac_if
, "soft reset timed out");
575 CSR_WRITE_1(sc
, VGE_CRS3
, VGE_CR3_STOP_FORCE
);
581 CSR_SETBIT_1(sc
, VGE_EECSR
, VGE_EECSR_RELOAD
);
583 for (i
= 0; i
< VGE_TIMEOUT
; i
++) {
585 if ((CSR_READ_1(sc
, VGE_EECSR
) & VGE_EECSR_RELOAD
) == 0)
588 if (i
== VGE_TIMEOUT
) {
589 if_printf(&sc
->arpcom
.ac_if
, "EEPROM reload timed out\n");
593 CSR_CLRBIT_1(sc
, VGE_CHIPCFG0
, VGE_CHIPCFG0_PACPI
);
597 * Probe for a VIA gigabit chip. Check the PCI vendor and device
598 * IDs against our list and return a device name if we find a match.
601 vge_probe(device_t dev
)
603 const struct vge_type
*t
;
606 did
= pci_get_device(dev
);
607 vid
= pci_get_vendor(dev
);
608 for (t
= vge_devs
; t
->vge_name
!= NULL
; ++t
) {
609 if (vid
== t
->vge_vid
&& did
== t
->vge_did
) {
610 device_set_desc(dev
, t
->vge_name
);
618 vge_dma_map_rx_desc(void *arg
, bus_dma_segment_t
*segs
, int nseg
,
619 bus_size_t mapsize
, int error
)
622 struct vge_dmaload_arg
*ctx
;
623 struct vge_rx_desc
*d
= NULL
;
630 /* Signal error to caller if there's too many segments */
631 if (nseg
> ctx
->vge_maxsegs
) {
632 ctx
->vge_maxsegs
= 0;
637 * Map the segment array into descriptors.
639 d
= &ctx
->sc
->vge_ldata
.vge_rx_list
[ctx
->vge_idx
];
641 /* If this descriptor is still owned by the chip, bail. */
642 if (le32toh(d
->vge_sts
) & VGE_RDSTS_OWN
) {
643 if_printf(&ctx
->sc
->arpcom
.ac_if
,
644 "tried to map busy descriptor\n");
645 ctx
->vge_maxsegs
= 0;
649 d
->vge_buflen
= htole16(VGE_BUFLEN(segs
[0].ds_len
) | VGE_RXDESC_I
);
650 d
->vge_addrlo
= htole32(VGE_ADDR_LO(segs
[0].ds_addr
));
651 d
->vge_addrhi
= htole16(VGE_ADDR_HI(segs
[0].ds_addr
) & 0xFFFF);
655 ctx
->vge_maxsegs
= 1;
659 vge_dma_map_tx_desc(void *arg
, bus_dma_segment_t
*segs
, int nseg
,
660 bus_size_t mapsize
, int error
)
662 struct vge_dmaload_arg
*ctx
;
663 struct vge_tx_desc
*d
= NULL
;
664 struct vge_tx_frag
*f
;
672 /* Signal error to caller if there's too many segments */
673 if (nseg
> ctx
->vge_maxsegs
) {
674 ctx
->vge_maxsegs
= 0;
678 /* Map the segment array into descriptors. */
679 d
= &ctx
->sc
->vge_ldata
.vge_tx_list
[ctx
->vge_idx
];
681 /* If this descriptor is still owned by the chip, bail. */
682 if (le32toh(d
->vge_sts
) & VGE_TDSTS_OWN
) {
683 ctx
->vge_maxsegs
= 0;
687 for (i
= 0; i
< nseg
; i
++) {
689 f
->vge_buflen
= htole16(VGE_BUFLEN(segs
[i
].ds_len
));
690 f
->vge_addrlo
= htole32(VGE_ADDR_LO(segs
[i
].ds_addr
));
691 f
->vge_addrhi
= htole16(VGE_ADDR_HI(segs
[i
].ds_addr
) & 0xFFFF);
694 /* Argh. This chip does not autopad short frames */
695 if (ctx
->vge_m0
->m_pkthdr
.len
< VGE_MIN_FRAMELEN
) {
697 f
->vge_buflen
= htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN
-
698 ctx
->vge_m0
->m_pkthdr
.len
));
699 f
->vge_addrlo
= htole32(VGE_ADDR_LO(segs
[0].ds_addr
));
700 f
->vge_addrhi
= htole16(VGE_ADDR_HI(segs
[0].ds_addr
) & 0xFFFF);
701 ctx
->vge_m0
->m_pkthdr
.len
= VGE_MIN_FRAMELEN
;
706 * When telling the chip how many segments there are, we
707 * must use nsegs + 1 instead of just nsegs. Darned if I
712 d
->vge_sts
= ctx
->vge_m0
->m_pkthdr
.len
<< 16;
713 d
->vge_ctl
= ctx
->vge_flags
|(i
<< 28)|VGE_TD_LS_NORM
;
715 if (ctx
->vge_m0
->m_pkthdr
.len
> ETHERMTU
+ ETHER_HDR_LEN
)
716 d
->vge_ctl
|= VGE_TDCTL_JUMBO
;
718 ctx
->vge_maxsegs
= nseg
;
722 * Map a single buffer address.
726 vge_dma_map_addr(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
731 KASSERT(nseg
== 1, ("too many DMA segments, %d should be 1", nseg
));
732 *((bus_addr_t
*)arg
) = segs
->ds_addr
;
736 vge_dma_alloc(device_t dev
)
738 struct vge_softc
*sc
= device_get_softc(dev
);
739 int error
, nseg
, i
, tx_pos
= 0, rx_pos
= 0;
742 * Allocate the parent bus DMA tag appropriate for PCI.
744 #define VGE_NSEG_NEW 32
745 error
= bus_dma_tag_create(NULL
, /* parent */
746 1, 0, /* alignment, boundary */
747 BUS_SPACE_MAXADDR_32BIT
,/* lowaddr */
748 BUS_SPACE_MAXADDR
, /* highaddr */
749 NULL
, NULL
, /* filter, filterarg */
750 MAXBSIZE
, VGE_NSEG_NEW
, /* maxsize, nsegments */
751 BUS_SPACE_MAXSIZE_32BIT
,/* maxsegsize */
752 BUS_DMA_ALLOCNOW
, /* flags */
753 &sc
->vge_parent_tag
);
755 device_printf(dev
, "can't create parent dma tag\n");
760 * Allocate map for RX mbufs.
763 error
= bus_dma_tag_create(sc
->vge_parent_tag
, ETHER_ALIGN
, 0,
764 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
,
766 MCLBYTES
* nseg
, nseg
, MCLBYTES
,
767 BUS_DMA_ALLOCNOW
, &sc
->vge_ldata
.vge_mtag
);
769 device_printf(dev
, "could not allocate mbuf dma tag\n");
774 * Allocate map for TX descriptor list.
776 error
= bus_dma_tag_create(sc
->vge_parent_tag
, VGE_RING_ALIGN
, 0,
777 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
,
779 VGE_TX_LIST_SZ
, 1, VGE_TX_LIST_SZ
,
781 &sc
->vge_ldata
.vge_tx_list_tag
);
783 device_printf(dev
, "could not allocate tx list dma tag\n");
787 /* Allocate DMA'able memory for the TX ring */
788 error
= bus_dmamem_alloc(sc
->vge_ldata
.vge_tx_list_tag
,
789 (void **)&sc
->vge_ldata
.vge_tx_list
,
790 BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
791 &sc
->vge_ldata
.vge_tx_list_map
);
793 device_printf(dev
, "could not allocate tx list dma memory\n");
797 /* Load the map for the TX ring. */
798 error
= bus_dmamap_load(sc
->vge_ldata
.vge_tx_list_tag
,
799 sc
->vge_ldata
.vge_tx_list_map
,
800 sc
->vge_ldata
.vge_tx_list
, VGE_TX_LIST_SZ
,
802 &sc
->vge_ldata
.vge_tx_list_addr
,
805 device_printf(dev
, "could not load tx list\n");
806 bus_dmamem_free(sc
->vge_ldata
.vge_tx_list_tag
,
807 sc
->vge_ldata
.vge_tx_list
,
808 sc
->vge_ldata
.vge_tx_list_map
);
809 sc
->vge_ldata
.vge_tx_list
= NULL
;
813 /* Create DMA maps for TX buffers */
814 for (i
= 0; i
< VGE_TX_DESC_CNT
; i
++) {
815 error
= bus_dmamap_create(sc
->vge_ldata
.vge_mtag
, 0,
816 &sc
->vge_ldata
.vge_tx_dmamap
[i
]);
818 device_printf(dev
, "can't create DMA map for TX\n");
823 tx_pos
= VGE_TX_DESC_CNT
;
826 * Allocate map for RX descriptor list.
828 error
= bus_dma_tag_create(sc
->vge_parent_tag
, VGE_RING_ALIGN
, 0,
829 BUS_SPACE_MAXADDR_32BIT
, BUS_SPACE_MAXADDR
,
831 VGE_TX_LIST_SZ
, 1, VGE_TX_LIST_SZ
,
833 &sc
->vge_ldata
.vge_rx_list_tag
);
835 device_printf(dev
, "could not allocate rx list dma tag\n");
839 /* Allocate DMA'able memory for the RX ring */
840 error
= bus_dmamem_alloc(sc
->vge_ldata
.vge_rx_list_tag
,
841 (void **)&sc
->vge_ldata
.vge_rx_list
,
842 BUS_DMA_WAITOK
| BUS_DMA_ZERO
,
843 &sc
->vge_ldata
.vge_rx_list_map
);
845 device_printf(dev
, "could not allocate rx list dma memory\n");
849 /* Load the map for the RX ring. */
850 error
= bus_dmamap_load(sc
->vge_ldata
.vge_rx_list_tag
,
851 sc
->vge_ldata
.vge_rx_list_map
,
852 sc
->vge_ldata
.vge_rx_list
, VGE_TX_LIST_SZ
,
854 &sc
->vge_ldata
.vge_rx_list_addr
,
857 device_printf(dev
, "could not load rx list\n");
858 bus_dmamem_free(sc
->vge_ldata
.vge_rx_list_tag
,
859 sc
->vge_ldata
.vge_rx_list
,
860 sc
->vge_ldata
.vge_rx_list_map
);
861 sc
->vge_ldata
.vge_rx_list
= NULL
;
865 /* Create DMA maps for RX buffers */
866 for (i
= 0; i
< VGE_RX_DESC_CNT
; i
++) {
867 error
= bus_dmamap_create(sc
->vge_ldata
.vge_mtag
, 0,
868 &sc
->vge_ldata
.vge_rx_dmamap
[i
]);
870 device_printf(dev
, "can't create DMA map for RX\n");
878 for (i
= 0; i
< tx_pos
; ++i
) {
879 error
= bus_dmamap_destroy(sc
->vge_ldata
.vge_mtag
,
880 sc
->vge_ldata
.vge_tx_dmamap
[i
]);
882 for (i
= 0; i
< rx_pos
; ++i
) {
883 error
= bus_dmamap_destroy(sc
->vge_ldata
.vge_mtag
,
884 sc
->vge_ldata
.vge_rx_dmamap
[i
]);
886 bus_dma_tag_destroy(sc
->vge_ldata
.vge_mtag
);
887 sc
->vge_ldata
.vge_mtag
= NULL
;
893 vge_dma_free(struct vge_softc
*sc
)
895 /* Unload and free the RX DMA ring memory and map */
896 if (sc
->vge_ldata
.vge_rx_list_tag
) {
897 bus_dmamap_unload(sc
->vge_ldata
.vge_rx_list_tag
,
898 sc
->vge_ldata
.vge_rx_list_map
);
899 bus_dmamem_free(sc
->vge_ldata
.vge_rx_list_tag
,
900 sc
->vge_ldata
.vge_rx_list
,
901 sc
->vge_ldata
.vge_rx_list_map
);
904 if (sc
->vge_ldata
.vge_rx_list_tag
)
905 bus_dma_tag_destroy(sc
->vge_ldata
.vge_rx_list_tag
);
907 /* Unload and free the TX DMA ring memory and map */
908 if (sc
->vge_ldata
.vge_tx_list_tag
) {
909 bus_dmamap_unload(sc
->vge_ldata
.vge_tx_list_tag
,
910 sc
->vge_ldata
.vge_tx_list_map
);
911 bus_dmamem_free(sc
->vge_ldata
.vge_tx_list_tag
,
912 sc
->vge_ldata
.vge_tx_list
,
913 sc
->vge_ldata
.vge_tx_list_map
);
916 if (sc
->vge_ldata
.vge_tx_list_tag
)
917 bus_dma_tag_destroy(sc
->vge_ldata
.vge_tx_list_tag
);
919 /* Destroy all the RX and TX buffer maps */
920 if (sc
->vge_ldata
.vge_mtag
) {
923 for (i
= 0; i
< VGE_TX_DESC_CNT
; i
++) {
924 bus_dmamap_destroy(sc
->vge_ldata
.vge_mtag
,
925 sc
->vge_ldata
.vge_tx_dmamap
[i
]);
927 for (i
= 0; i
< VGE_RX_DESC_CNT
; i
++) {
928 bus_dmamap_destroy(sc
->vge_ldata
.vge_mtag
,
929 sc
->vge_ldata
.vge_rx_dmamap
[i
]);
931 bus_dma_tag_destroy(sc
->vge_ldata
.vge_mtag
);
934 if (sc
->vge_parent_tag
)
935 bus_dma_tag_destroy(sc
->vge_parent_tag
);
939 * Attach the interface. Allocate softc structures, do ifmedia
940 * setup and ethernet/BPF attach.
943 vge_attach(device_t dev
)
945 uint8_t eaddr
[ETHER_ADDR_LEN
];
946 struct vge_softc
*sc
;
950 sc
= device_get_softc(dev
);
951 ifp
= &sc
->arpcom
.ac_if
;
953 /* Initialize if_xname early, so if_printf() can be used */
954 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
957 * Map control/status registers.
959 pci_enable_busmaster(dev
);
961 sc
->vge_res_rid
= VGE_PCI_LOMEM
;
962 sc
->vge_res
= bus_alloc_resource_any(dev
, SYS_RES_MEMORY
,
963 &sc
->vge_res_rid
, RF_ACTIVE
);
964 if (sc
->vge_res
== NULL
) {
965 device_printf(dev
, "couldn't map ports/memory\n");
969 sc
->vge_btag
= rman_get_bustag(sc
->vge_res
);
970 sc
->vge_bhandle
= rman_get_bushandle(sc
->vge_res
);
972 /* Allocate interrupt */
974 sc
->vge_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &sc
->vge_irq_rid
,
975 RF_SHAREABLE
| RF_ACTIVE
);
976 if (sc
->vge_irq
== NULL
) {
977 device_printf(dev
, "couldn't map interrupt\n");
982 /* Reset the adapter. */
986 * Get station address from the EEPROM.
988 vge_read_eeprom(sc
, eaddr
, VGE_EE_EADDR
, 3, 0);
990 /* Allocate DMA related stuffs */
991 error
= vge_dma_alloc(dev
);
996 error
= mii_phy_probe(dev
, &sc
->vge_miibus
, vge_ifmedia_upd
,
999 device_printf(dev
, "MII without any phy!\n");
1004 ifp
->if_mtu
= ETHERMTU
;
1005 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1006 ifp
->if_init
= vge_init
;
1007 ifp
->if_start
= vge_start
;
1008 ifp
->if_watchdog
= vge_watchdog
;
1009 ifp
->if_ioctl
= vge_ioctl
;
1010 #ifdef DEVICE_POLLING
1011 ifp
->if_poll
= vge_poll
;
1013 ifp
->if_hwassist
= VGE_CSUM_FEATURES
;
1014 ifp
->if_capabilities
= IFCAP_VLAN_MTU
|
1016 IFCAP_VLAN_HWTAGGING
;
1017 ifp
->if_capenable
= ifp
->if_capabilities
;
1018 ifq_set_maxlen(&ifp
->if_snd
, VGE_IFQ_MAXLEN
);
1019 ifq_set_ready(&ifp
->if_snd
);
1022 * Call MI attach routine.
1024 ether_ifattach(ifp
, eaddr
, NULL
);
1026 /* Hook interrupt last to avoid having to lock softc */
1027 error
= bus_setup_intr(dev
, sc
->vge_irq
, INTR_MPSAFE
, vge_intr
, sc
,
1028 &sc
->vge_intrhand
, ifp
->if_serializer
);
1030 device_printf(dev
, "couldn't set up irq\n");
1031 ether_ifdetach(ifp
);
1042 * Shutdown hardware and free up resources. This can be called any
1043 * time after the mutex has been initialized. It is called in both
1044 * the error case in attach and the normal detach case so it needs
1045 * to be careful about only freeing resources that have actually been
1049 vge_detach(device_t dev
)
1051 struct vge_softc
*sc
= device_get_softc(dev
);
1052 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1054 /* These should only be active if attach succeeded */
1055 if (device_is_attached(dev
)) {
1056 lwkt_serialize_enter(ifp
->if_serializer
);
1059 bus_teardown_intr(dev
, sc
->vge_irq
, sc
->vge_intrhand
);
1061 * Force off the IFF_UP flag here, in case someone
1062 * still had a BPF descriptor attached to this
1063 * interface. If they do, ether_ifattach() will cause
1064 * the BPF code to try and clear the promisc mode
1065 * flag, which will bubble down to vge_ioctl(),
1066 * which will try to call vge_init() again. This will
1067 * turn the NIC back on and restart the MII ticker,
1068 * which will panic the system when the kernel tries
1069 * to invoke the vge_tick() function that isn't there
1072 ifp
->if_flags
&= ~IFF_UP
;
1074 lwkt_serialize_exit(ifp
->if_serializer
);
1076 ether_ifdetach(ifp
);
1080 device_delete_child(dev
, sc
->vge_miibus
);
1081 bus_generic_detach(dev
);
1084 bus_release_resource(dev
, SYS_RES_IRQ
, sc
->vge_irq_rid
,
1089 bus_release_resource(dev
, SYS_RES_MEMORY
, sc
->vge_res_rid
,
1098 vge_newbuf(struct vge_softc
*sc
, int idx
, struct mbuf
*m
)
1100 struct vge_dmaload_arg arg
;
1101 struct mbuf
*n
= NULL
;
1105 n
= m_getcl(MB_DONTWAIT
, MT_DATA
, M_PKTHDR
);
1110 m
->m_data
= m
->m_ext
.ext_buf
;
1116 * This is part of an evil trick to deal with non-x86 platforms.
1117 * The VIA chip requires RX buffers to be aligned on 32-bit
1118 * boundaries, but that will hose non-x86 machines. To get around
1119 * this, we leave some empty space at the start of each buffer
1120 * and for non-x86 hosts, we copy the buffer back two bytes
1121 * to achieve word alignment. This is slightly more efficient
1122 * than allocating a new buffer, copying the contents, and
1123 * discarding the old buffer.
1125 m
->m_len
= m
->m_pkthdr
.len
= MCLBYTES
- VGE_ETHER_ALIGN
;
1126 m_adj(m
, VGE_ETHER_ALIGN
);
1128 m
->m_len
= m
->m_pkthdr
.len
= MCLBYTES
;
1133 arg
.vge_maxsegs
= 1;
1136 error
= bus_dmamap_load_mbuf(sc
->vge_ldata
.vge_mtag
,
1137 sc
->vge_ldata
.vge_rx_dmamap
[idx
], m
,
1138 vge_dma_map_rx_desc
, &arg
, BUS_DMA_NOWAIT
);
1139 if (error
|| arg
.vge_maxsegs
!= 1) {
1146 * Note: the manual fails to document the fact that for
1147 * proper opration, the driver needs to replentish the RX
1148 * DMA ring 4 descriptors at a time (rather than one at a
1149 * time, like most chips). We can allocate the new buffers
1150 * but we should not set the OWN bits until we're ready
1151 * to hand back 4 of them in one shot.
1154 #define VGE_RXCHUNK 4
1155 sc
->vge_rx_consumed
++;
1156 if (sc
->vge_rx_consumed
== VGE_RXCHUNK
) {
1157 for (i
= idx
; i
!= idx
- sc
->vge_rx_consumed
; i
--) {
1158 sc
->vge_ldata
.vge_rx_list
[i
].vge_sts
|=
1159 htole32(VGE_RDSTS_OWN
);
1161 sc
->vge_rx_consumed
= 0;
1164 sc
->vge_ldata
.vge_rx_mbuf
[idx
] = m
;
1166 bus_dmamap_sync(sc
->vge_ldata
.vge_mtag
,
1167 sc
->vge_ldata
.vge_rx_dmamap
[idx
], BUS_DMASYNC_PREREAD
);
1173 vge_tx_list_init(struct vge_softc
*sc
)
1175 bzero ((char *)sc
->vge_ldata
.vge_tx_list
, VGE_TX_LIST_SZ
);
1176 bzero ((char *)&sc
->vge_ldata
.vge_tx_mbuf
,
1177 (VGE_TX_DESC_CNT
* sizeof(struct mbuf
*)));
1179 bus_dmamap_sync(sc
->vge_ldata
.vge_tx_list_tag
,
1180 sc
->vge_ldata
.vge_tx_list_map
, BUS_DMASYNC_PREWRITE
);
1181 sc
->vge_ldata
.vge_tx_prodidx
= 0;
1182 sc
->vge_ldata
.vge_tx_considx
= 0;
1183 sc
->vge_ldata
.vge_tx_free
= VGE_TX_DESC_CNT
;
1189 vge_rx_list_init(struct vge_softc
*sc
)
1193 bzero(sc
->vge_ldata
.vge_rx_list
, VGE_RX_LIST_SZ
);
1194 bzero(&sc
->vge_ldata
.vge_rx_mbuf
,
1195 VGE_RX_DESC_CNT
* sizeof(struct mbuf
*));
1197 sc
->vge_rx_consumed
= 0;
1199 for (i
= 0; i
< VGE_RX_DESC_CNT
; i
++) {
1200 if (vge_newbuf(sc
, i
, NULL
) == ENOBUFS
)
1204 /* Flush the RX descriptors */
1205 bus_dmamap_sync(sc
->vge_ldata
.vge_rx_list_tag
,
1206 sc
->vge_ldata
.vge_rx_list_map
,
1207 BUS_DMASYNC_PREWRITE
);
1209 sc
->vge_ldata
.vge_rx_prodidx
= 0;
1210 sc
->vge_rx_consumed
= 0;
1211 sc
->vge_head
= sc
->vge_tail
= NULL
;
1216 static __inline
void
1217 vge_fixup_rx(struct mbuf
*m
)
1219 uint16_t *src
, *dst
;
1222 src
= mtod(m
, uint16_t *);
1225 for (i
= 0; i
< (m
->m_len
/ sizeof(uint16_t) + 1); i
++)
1228 m
->m_data
-= ETHER_ALIGN
;
1233 * RX handler. We support the reception of jumbo frames that have
1234 * been fragmented across multiple 2K mbuf cluster buffers.
1237 vge_rxeof(struct vge_softc
*sc
, int count
)
1239 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1241 int i
, total_len
, lim
= 0;
1242 struct vge_rx_desc
*cur_rx
;
1243 uint32_t rxstat
, rxctl
;
1245 ASSERT_SERIALIZED(ifp
->if_serializer
);
1247 i
= sc
->vge_ldata
.vge_rx_prodidx
;
1249 /* Invalidate the descriptor memory */
1251 bus_dmamap_sync(sc
->vge_ldata
.vge_rx_list_tag
,
1252 sc
->vge_ldata
.vge_rx_list_map
, BUS_DMASYNC_POSTREAD
);
1254 while (!VGE_OWN(&sc
->vge_ldata
.vge_rx_list
[i
])) {
1255 #ifdef DEVICE_POLLING
1256 if (count
>= 0 && count
-- == 0)
1260 cur_rx
= &sc
->vge_ldata
.vge_rx_list
[i
];
1261 m
= sc
->vge_ldata
.vge_rx_mbuf
[i
];
1262 total_len
= VGE_RXBYTES(cur_rx
);
1263 rxstat
= le32toh(cur_rx
->vge_sts
);
1264 rxctl
= le32toh(cur_rx
->vge_ctl
);
1266 /* Invalidate the RX mbuf and unload its map */
1267 bus_dmamap_sync(sc
->vge_ldata
.vge_mtag
,
1268 sc
->vge_ldata
.vge_rx_dmamap
[i
],
1269 BUS_DMASYNC_POSTWRITE
);
1270 bus_dmamap_unload(sc
->vge_ldata
.vge_mtag
,
1271 sc
->vge_ldata
.vge_rx_dmamap
[i
]);
1274 * If the 'start of frame' bit is set, this indicates
1275 * either the first fragment in a multi-fragment receive,
1276 * or an intermediate fragment. Either way, we want to
1277 * accumulate the buffers.
1279 if (rxstat
& VGE_RXPKT_SOF
) {
1280 m
->m_len
= MCLBYTES
- VGE_ETHER_ALIGN
;
1281 if (sc
->vge_head
== NULL
) {
1282 sc
->vge_head
= sc
->vge_tail
= m
;
1284 m
->m_flags
&= ~M_PKTHDR
;
1285 sc
->vge_tail
->m_next
= m
;
1288 vge_newbuf(sc
, i
, NULL
);
1294 * Bad/error frames will have the RXOK bit cleared.
1295 * However, there's one error case we want to allow:
1296 * if a VLAN tagged frame arrives and the chip can't
1297 * match it against the CAM filter, it considers this
1298 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1299 * We don't want to drop the frame though: our VLAN
1300 * filtering is done in software.
1302 if (!(rxstat
& VGE_RDSTS_RXOK
) && !(rxstat
& VGE_RDSTS_VIDM
) &&
1303 !(rxstat
& VGE_RDSTS_CSUMERR
)) {
1306 * If this is part of a multi-fragment packet,
1307 * discard all the pieces.
1309 if (sc
->vge_head
!= NULL
) {
1310 m_freem(sc
->vge_head
);
1311 sc
->vge_head
= sc
->vge_tail
= NULL
;
1313 vge_newbuf(sc
, i
, m
);
1319 * If allocating a replacement mbuf fails,
1320 * reload the current one.
1322 if (vge_newbuf(sc
, i
, NULL
)) {
1324 if (sc
->vge_head
!= NULL
) {
1325 m_freem(sc
->vge_head
);
1326 sc
->vge_head
= sc
->vge_tail
= NULL
;
1328 vge_newbuf(sc
, i
, m
);
1335 if (sc
->vge_head
!= NULL
) {
1336 m
->m_len
= total_len
% (MCLBYTES
- VGE_ETHER_ALIGN
);
1338 * Special case: if there's 4 bytes or less
1339 * in this buffer, the mbuf can be discarded:
1340 * the last 4 bytes is the CRC, which we don't
1341 * care about anyway.
1343 if (m
->m_len
<= ETHER_CRC_LEN
) {
1344 sc
->vge_tail
->m_len
-=
1345 (ETHER_CRC_LEN
- m
->m_len
);
1348 m
->m_len
-= ETHER_CRC_LEN
;
1349 m
->m_flags
&= ~M_PKTHDR
;
1350 sc
->vge_tail
->m_next
= m
;
1353 sc
->vge_head
= sc
->vge_tail
= NULL
;
1354 m
->m_pkthdr
.len
= total_len
- ETHER_CRC_LEN
;
1356 m
->m_pkthdr
.len
= m
->m_len
=
1357 (total_len
- ETHER_CRC_LEN
);
1364 m
->m_pkthdr
.rcvif
= ifp
;
1366 /* Do RX checksumming if enabled */
1367 if (ifp
->if_capenable
& IFCAP_RXCSUM
) {
1368 /* Check IP header checksum */
1369 if (rxctl
& VGE_RDCTL_IPPKT
)
1370 m
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
;
1371 if (rxctl
& VGE_RDCTL_IPCSUMOK
)
1372 m
->m_pkthdr
.csum_flags
|= CSUM_IP_VALID
;
1374 /* Check TCP/UDP checksum */
1375 if (rxctl
& (VGE_RDCTL_TCPPKT
|VGE_RDCTL_UDPPKT
) &&
1376 rxctl
& VGE_RDCTL_PROTOCSUMOK
) {
1377 m
->m_pkthdr
.csum_flags
|=
1378 CSUM_DATA_VALID
|CSUM_PSEUDO_HDR
;
1379 m
->m_pkthdr
.csum_data
= 0xffff;
1383 if (rxstat
& VGE_RDSTS_VTAG
)
1384 VLAN_INPUT_TAG(m
, ntohs((rxctl
& VGE_RDCTL_VLANID
)));
1386 ifp
->if_input(ifp
, m
);
1389 if (lim
== VGE_RX_DESC_CNT
)
1393 /* Flush the RX DMA ring */
1394 bus_dmamap_sync(sc
->vge_ldata
.vge_rx_list_tag
,
1395 sc
->vge_ldata
.vge_rx_list_map
,
1396 BUS_DMASYNC_PREWRITE
);
1398 sc
->vge_ldata
.vge_rx_prodidx
= i
;
1399 CSR_WRITE_2(sc
, VGE_RXDESC_RESIDUECNT
, lim
);
1403 vge_txeof(struct vge_softc
*sc
)
1405 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1409 idx
= sc
->vge_ldata
.vge_tx_considx
;
1411 /* Invalidate the TX descriptor list */
1413 bus_dmamap_sync(sc
->vge_ldata
.vge_tx_list_tag
,
1414 sc
->vge_ldata
.vge_tx_list_map
, BUS_DMASYNC_POSTREAD
);
1416 while (idx
!= sc
->vge_ldata
.vge_tx_prodidx
) {
1418 txstat
= le32toh(sc
->vge_ldata
.vge_tx_list
[idx
].vge_sts
);
1419 if (txstat
& VGE_TDSTS_OWN
)
1422 m_freem(sc
->vge_ldata
.vge_tx_mbuf
[idx
]);
1423 sc
->vge_ldata
.vge_tx_mbuf
[idx
] = NULL
;
1424 bus_dmamap_unload(sc
->vge_ldata
.vge_mtag
,
1425 sc
->vge_ldata
.vge_tx_dmamap
[idx
]);
1426 if (txstat
& (VGE_TDSTS_EXCESSCOLL
|VGE_TDSTS_COLL
))
1427 ifp
->if_collisions
++;
1428 if (txstat
& VGE_TDSTS_TXERR
)
1433 sc
->vge_ldata
.vge_tx_free
++;
1434 VGE_TX_DESC_INC(idx
);
1437 /* No changes made to the TX ring, so no flush needed */
1438 if (idx
!= sc
->vge_ldata
.vge_tx_considx
) {
1439 sc
->vge_ldata
.vge_tx_considx
= idx
;
1440 ifp
->if_flags
&= ~IFF_OACTIVE
;
1445 * If not all descriptors have been released reaped yet,
1446 * reload the timer so that we will eventually get another
1447 * interrupt that will cause us to re-enter this routine.
1448 * This is done in case the transmitter has gone idle.
1450 if (sc
->vge_ldata
.vge_tx_free
!= VGE_TX_DESC_CNT
)
1451 CSR_WRITE_1(sc
, VGE_CRS1
, VGE_CR1_TIMER0_ENABLE
);
1455 vge_tick(struct vge_softc
*sc
)
1457 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1458 struct mii_data
*mii
;
1460 mii
= device_get_softc(sc
->vge_miibus
);
1464 if (!(mii
->mii_media_status
& IFM_ACTIVE
))
1467 if (mii
->mii_media_status
& IFM_ACTIVE
&&
1468 IFM_SUBTYPE(mii
->mii_media_active
) != IFM_NONE
) {
1470 if (!ifq_is_empty(&ifp
->if_snd
))
1476 #ifdef DEVICE_POLLING
1478 vge_poll(struct ifnet
*ifp
, enum poll_cmd cmd
, int count
)
1480 struct vge_softc
*sc
= ifp
->if_softc
;
1482 sc
->rxcycles
= count
;
1486 vge_disable_intr(sc
);
1488 case POLL_DEREGISTER
:
1489 vge_enable_intr(sc
, 0xffffffff);
1492 case POLL_AND_CHECK_STATUS
:
1493 vge_rxeof(sc
, count
);
1496 if (!ifq_is_empty(&ifp
->if_snd
))
1499 /* XXX copy & paste from vge_intr */
1500 if (cmd
== POLL_AND_CHECK_STATUS
) {
1501 uint32_t status
= 0;
1503 status
= CSR_READ_4(sc
, VGE_ISR
);
1504 if (status
== 0xffffffff)
1508 CSR_WRITE_4(sc
, VGE_ISR
, status
);
1510 if (status
& (VGE_ISR_TXDMA_STALL
|
1511 VGE_ISR_RXDMA_STALL
))
1514 if (status
& (VGE_ISR_RXOFLOW
| VGE_ISR_RXNODESC
)) {
1516 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_RUN
);
1517 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_WAK
);
1524 #endif /* DEVICE_POLLING */
1529 struct vge_softc
*sc
= arg
;
1530 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1533 if (sc
->suspended
|| !(ifp
->if_flags
& IFF_UP
))
1536 /* Disable interrupts */
1537 CSR_WRITE_1(sc
, VGE_CRC3
, VGE_CR3_INT_GMSK
);
1540 status
= CSR_READ_4(sc
, VGE_ISR
);
1541 /* If the card has gone away the read returns 0xffff. */
1542 if (status
== 0xFFFFFFFF)
1546 CSR_WRITE_4(sc
, VGE_ISR
, status
);
1548 if ((status
& VGE_INTRS
) == 0)
1551 if (status
& (VGE_ISR_RXOK
|VGE_ISR_RXOK_HIPRIO
))
1554 if (status
& (VGE_ISR_RXOFLOW
|VGE_ISR_RXNODESC
)) {
1557 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_RUN
);
1558 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_WAK
);
1561 if (status
& (VGE_ISR_TXOK0
|VGE_ISR_TIMER0
))
1564 if (status
& (VGE_ISR_TXDMA_STALL
|VGE_ISR_RXDMA_STALL
))
1567 if (status
& VGE_ISR_LINKSTS
)
1571 /* Re-enable interrupts */
1572 CSR_WRITE_1(sc
, VGE_CRS3
, VGE_CR3_INT_GMSK
);
1574 if (!ifq_is_empty(&ifp
->if_snd
))
1579 vge_encap(struct vge_softc
*sc
, struct mbuf
*m_head
, int idx
)
1581 struct vge_dmaload_arg arg
;
1587 if (m_head
->m_pkthdr
.csum_flags
& CSUM_IP
)
1588 arg
.vge_flags
|= VGE_TDCTL_IPCSUM
;
1589 if (m_head
->m_pkthdr
.csum_flags
& CSUM_TCP
)
1590 arg
.vge_flags
|= VGE_TDCTL_TCPCSUM
;
1591 if (m_head
->m_pkthdr
.csum_flags
& CSUM_UDP
)
1592 arg
.vge_flags
|= VGE_TDCTL_UDPCSUM
;
1596 arg
.vge_m0
= m_head
;
1597 arg
.vge_maxsegs
= VGE_TX_FRAGS
;
1599 map
= sc
->vge_ldata
.vge_tx_dmamap
[idx
];
1600 error
= bus_dmamap_load_mbuf(sc
->vge_ldata
.vge_mtag
, map
, m_head
,
1601 vge_dma_map_tx_desc
, &arg
, BUS_DMA_NOWAIT
);
1602 if (error
&& error
!= EFBIG
) {
1603 if_printf(&sc
->arpcom
.ac_if
, "can't map mbuf (error %d)\n",
1608 /* Too many segments to map, coalesce into a single mbuf */
1609 if (error
|| arg
.vge_maxsegs
== 0) {
1612 m_new
= m_defrag(m_head
, MB_DONTWAIT
);
1613 if (m_new
== NULL
) {
1621 arg
.vge_m0
= m_head
;
1623 arg
.vge_maxsegs
= 1;
1625 error
= bus_dmamap_load_mbuf(sc
->vge_ldata
.vge_mtag
, map
,
1626 m_head
, vge_dma_map_tx_desc
, &arg
,
1629 if_printf(&sc
->arpcom
.ac_if
,
1630 "can't map mbuf (error %d)\n", error
);
1635 sc
->vge_ldata
.vge_tx_mbuf
[idx
] = m_head
;
1636 sc
->vge_ldata
.vge_tx_free
--;
1639 * Set up hardware VLAN tagging.
1641 if ((m_head
->m_flags
& (M_PROTO1
|M_PKTHDR
)) == (M_PROTO1
|M_PKTHDR
) &&
1642 m_head
->m_pkthdr
.rcvif
!= NULL
&&
1643 m_head
->m_pkthdr
.rcvif
->if_type
== IFT_L2VLAN
) {
1644 struct ifvlan
*ifv
= m_head
->m_pkthdr
.rcvif
->if_softc
;
1647 sc
->vge_ldata
.vge_tx_list
[idx
].vge_ctl
|=
1648 htole32(htons(ifv
->ifv_tag
) | VGE_TDCTL_VTAG
);
1652 sc
->vge_ldata
.vge_tx_list
[idx
].vge_sts
|= htole32(VGE_TDSTS_OWN
);
1661 * Main transmit routine.
1665 vge_start(struct ifnet
*ifp
)
1667 struct vge_softc
*sc
= ifp
->if_softc
;
1668 struct mbuf
*m_head
= NULL
;
1671 ASSERT_SERIALIZED(ifp
->if_serializer
);
1673 if (!sc
->vge_link
|| (ifp
->if_flags
& IFF_OACTIVE
))
1676 if (ifq_is_empty(&ifp
->if_snd
))
1679 idx
= sc
->vge_ldata
.vge_tx_prodidx
;
1683 pidx
= VGE_TX_DESC_CNT
- 1;
1685 while (sc
->vge_ldata
.vge_tx_mbuf
[idx
] == NULL
) {
1686 m_head
= ifq_poll(&ifp
->if_snd
);
1690 if (sc
->vge_ldata
.vge_tx_free
<= 2) {
1691 ifp
->if_flags
|= IFF_OACTIVE
;
1695 m_head
= ifq_dequeue(&ifp
->if_snd
, m_head
);
1697 if (vge_encap(sc
, m_head
, idx
)) {
1698 /* If vge_encap() failed, it will free m_head for us */
1699 ifp
->if_flags
|= IFF_OACTIVE
;
1703 sc
->vge_ldata
.vge_tx_list
[pidx
].vge_frag
[0].vge_buflen
|=
1704 htole16(VGE_TXDESC_Q
);
1707 VGE_TX_DESC_INC(idx
);
1710 * If there's a BPF listener, bounce a copy of this frame
1713 BPF_MTAP(ifp
, m_head
);
1716 if (idx
== sc
->vge_ldata
.vge_tx_prodidx
)
1719 /* Flush the TX descriptors */
1720 bus_dmamap_sync(sc
->vge_ldata
.vge_tx_list_tag
,
1721 sc
->vge_ldata
.vge_tx_list_map
,
1722 BUS_DMASYNC_PREWRITE
);
1724 /* Issue a transmit command. */
1725 CSR_WRITE_2(sc
, VGE_TXQCSRS
, VGE_TXQCSR_WAK0
);
1727 sc
->vge_ldata
.vge_tx_prodidx
= idx
;
1730 * Use the countdown timer for interrupt moderation.
1731 * 'TX done' interrupts are disabled. Instead, we reset the
1732 * countdown timer, which will begin counting until it hits
1733 * the value in the SSTIMER register, and then trigger an
1734 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1735 * the timer count is reloaded. Only when the transmitter
1736 * is idle will the timer hit 0 and an interrupt fire.
1738 CSR_WRITE_1(sc
, VGE_CRS1
, VGE_CR1_TIMER0_ENABLE
);
1741 * Set a timeout in case the chip goes out to lunch.
1749 struct vge_softc
*sc
= xsc
;
1750 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1751 struct mii_data
*mii
;
1754 ASSERT_SERIALIZED(ifp
->if_serializer
);
1756 mii
= device_get_softc(sc
->vge_miibus
);
1759 * Cancel pending I/O and free all RX/TX buffers.
1765 * Initialize the RX and TX descriptors and mbufs.
1767 vge_rx_list_init(sc
);
1768 vge_tx_list_init(sc
);
1770 /* Set our station address */
1771 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
1772 CSR_WRITE_1(sc
, VGE_PAR0
+ i
, IF_LLADDR(ifp
)[i
]);
1775 * Set receive FIFO threshold. Also allow transmission and
1776 * reception of VLAN tagged frames.
1778 CSR_CLRBIT_1(sc
, VGE_RXCFG
, VGE_RXCFG_FIFO_THR
|VGE_RXCFG_VTAGOPT
);
1779 CSR_SETBIT_1(sc
, VGE_RXCFG
, VGE_RXFIFOTHR_128BYTES
|VGE_VTAG_OPT2
);
1781 /* Set DMA burst length */
1782 CSR_CLRBIT_1(sc
, VGE_DMACFG0
, VGE_DMACFG0_BURSTLEN
);
1783 CSR_SETBIT_1(sc
, VGE_DMACFG0
, VGE_DMABURST_128
);
1785 CSR_SETBIT_1(sc
, VGE_TXCFG
, VGE_TXCFG_ARB_PRIO
|VGE_TXCFG_NONBLK
);
1787 /* Set collision backoff algorithm */
1788 CSR_CLRBIT_1(sc
, VGE_CHIPCFG1
, VGE_CHIPCFG1_CRANDOM
|
1789 VGE_CHIPCFG1_CAP
|VGE_CHIPCFG1_MBA
|VGE_CHIPCFG1_BAKOPT
);
1790 CSR_SETBIT_1(sc
, VGE_CHIPCFG1
, VGE_CHIPCFG1_OFSET
);
1792 /* Disable LPSEL field in priority resolution */
1793 CSR_SETBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_LPSEL_DIS
);
1796 * Load the addresses of the DMA queues into the chip.
1797 * Note that we only use one transmit queue.
1799 CSR_WRITE_4(sc
, VGE_TXDESC_ADDR_LO0
,
1800 VGE_ADDR_LO(sc
->vge_ldata
.vge_tx_list_addr
));
1801 CSR_WRITE_2(sc
, VGE_TXDESCNUM
, VGE_TX_DESC_CNT
- 1);
1803 CSR_WRITE_4(sc
, VGE_RXDESC_ADDR_LO
,
1804 VGE_ADDR_LO(sc
->vge_ldata
.vge_rx_list_addr
));
1805 CSR_WRITE_2(sc
, VGE_RXDESCNUM
, VGE_RX_DESC_CNT
- 1);
1806 CSR_WRITE_2(sc
, VGE_RXDESC_RESIDUECNT
, VGE_RX_DESC_CNT
);
1808 /* Enable and wake up the RX descriptor queue */
1809 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_RUN
);
1810 CSR_WRITE_1(sc
, VGE_RXQCSRS
, VGE_RXQCSR_WAK
);
1812 /* Enable the TX descriptor queue */
1813 CSR_WRITE_2(sc
, VGE_TXQCSRS
, VGE_TXQCSR_RUN0
);
1815 /* Set up the receive filter -- allow large frames for VLANs. */
1816 CSR_WRITE_1(sc
, VGE_RXCTL
, VGE_RXCTL_RX_UCAST
|VGE_RXCTL_RX_GIANT
);
1818 /* If we want promiscuous mode, set the allframes bit. */
1819 if (ifp
->if_flags
& IFF_PROMISC
)
1820 CSR_SETBIT_1(sc
, VGE_RXCTL
, VGE_RXCTL_RX_PROMISC
);
1822 /* Set capture broadcast bit to capture broadcast frames. */
1823 if (ifp
->if_flags
& IFF_BROADCAST
)
1824 CSR_SETBIT_1(sc
, VGE_RXCTL
, VGE_RXCTL_RX_BCAST
);
1826 /* Set multicast bit to capture multicast frames. */
1827 if (ifp
->if_flags
& IFF_MULTICAST
)
1828 CSR_SETBIT_1(sc
, VGE_RXCTL
, VGE_RXCTL_RX_MCAST
);
1830 /* Init the cam filter. */
1833 /* Init the multicast filter. */
1836 /* Enable flow control */
1838 CSR_WRITE_1(sc
, VGE_CRS2
, 0x8B);
1840 /* Enable jumbo frame reception (if desired) */
1842 /* Start the MAC. */
1843 CSR_WRITE_1(sc
, VGE_CRC0
, VGE_CR0_STOP
);
1844 CSR_WRITE_1(sc
, VGE_CRS1
, VGE_CR1_NOPOLL
);
1845 CSR_WRITE_1(sc
, VGE_CRS0
,
1846 VGE_CR0_TX_ENABLE
|VGE_CR0_RX_ENABLE
|VGE_CR0_START
);
1849 * Configure one-shot timer for microsecond
1850 * resulution and load it for 500 usecs.
1852 CSR_SETBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_TIMER0_RES
);
1853 CSR_WRITE_2(sc
, VGE_SSTIMER
, 400);
1856 * Configure interrupt moderation for receive. Enable
1857 * the holdoff counter and load it, and set the RX
1858 * suppression count to the number of descriptors we
1859 * want to allow before triggering an interrupt.
1860 * The holdoff timer is in units of 20 usecs.
1864 CSR_WRITE_1(sc
, VGE_INTCTL1
, VGE_INTCTL_TXINTSUP_DISABLE
);
1865 /* Select the interrupt holdoff timer page. */
1866 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
1867 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_INTHLDOFF
);
1868 CSR_WRITE_1(sc
, VGE_INTHOLDOFF
, 10); /* ~200 usecs */
1870 /* Enable use of the holdoff timer. */
1871 CSR_WRITE_1(sc
, VGE_CRS3
, VGE_CR3_INT_HOLDOFF
);
1872 CSR_WRITE_1(sc
, VGE_INTCTL1
, VGE_INTCTL_SC_RELOAD
);
1874 /* Select the RX suppression threshold page. */
1875 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
1876 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_RXSUPPTHR
);
1877 CSR_WRITE_1(sc
, VGE_RXSUPPTHR
, 64); /* interrupt after 64 packets */
1879 /* Restore the page select bits. */
1880 CSR_CLRBIT_1(sc
, VGE_CAMCTL
, VGE_CAMCTL_PAGESEL
);
1881 CSR_SETBIT_1(sc
, VGE_CAMCTL
, VGE_PAGESEL_MAR
);
1884 #ifdef DEVICE_POLLING
1885 /* Disable intr if polling(4) is enabled */
1886 if (ifp
->if_flags
& IFF_POLLING
)
1887 vge_disable_intr(sc
);
1890 vge_enable_intr(sc
, 0);
1894 ifp
->if_flags
|= IFF_RUNNING
;
1895 ifp
->if_flags
&= ~IFF_OACTIVE
;
1897 sc
->vge_if_flags
= 0;
1902 * Set media options.
1905 vge_ifmedia_upd(struct ifnet
*ifp
)
1907 struct vge_softc
*sc
= ifp
->if_softc
;
1908 struct mii_data
*mii
= device_get_softc(sc
->vge_miibus
);
1916 * Report current media status.
1919 vge_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
1921 struct vge_softc
*sc
= ifp
->if_softc
;
1922 struct mii_data
*mii
= device_get_softc(sc
->vge_miibus
);
1925 ifmr
->ifm_active
= mii
->mii_media_active
;
1926 ifmr
->ifm_status
= mii
->mii_media_status
;
1930 vge_miibus_statchg(device_t dev
)
1932 struct vge_softc
*sc
;
1933 struct mii_data
*mii
;
1934 struct ifmedia_entry
*ife
;
1936 sc
= device_get_softc(dev
);
1937 mii
= device_get_softc(sc
->vge_miibus
);
1938 ife
= mii
->mii_media
.ifm_cur
;
1941 * If the user manually selects a media mode, we need to turn
1942 * on the forced MAC mode bit in the DIAGCTL register. If the
1943 * user happens to choose a full duplex mode, we also need to
1944 * set the 'force full duplex' bit. This applies only to
1945 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
1946 * mode is disabled, and in 1000baseT mode, full duplex is
1947 * always implied, so we turn on the forced mode bit but leave
1948 * the FDX bit cleared.
1951 switch (IFM_SUBTYPE(ife
->ifm_media
)) {
1953 CSR_CLRBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_MACFORCE
);
1954 CSR_CLRBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_FDXFORCE
);
1957 CSR_SETBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_MACFORCE
);
1958 CSR_CLRBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_FDXFORCE
);
1962 CSR_SETBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_MACFORCE
);
1963 if ((ife
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
1964 CSR_SETBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_FDXFORCE
);
1966 CSR_CLRBIT_1(sc
, VGE_DIAGCTL
, VGE_DIAGCTL_FDXFORCE
);
1969 device_printf(dev
, "unknown media type: %x\n",
1970 IFM_SUBTYPE(ife
->ifm_media
));
1976 vge_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
1978 struct vge_softc
*sc
= ifp
->if_softc
;
1979 struct ifreq
*ifr
= (struct ifreq
*)data
;
1980 struct mii_data
*mii
;
1985 if (ifr
->ifr_mtu
> VGE_JUMBO_MTU
)
1987 ifp
->if_mtu
= ifr
->ifr_mtu
;
1990 if (ifp
->if_flags
& IFF_UP
) {
1991 if ((ifp
->if_flags
& IFF_RUNNING
) &&
1992 (ifp
->if_flags
& IFF_PROMISC
) &&
1993 !(sc
->vge_if_flags
& IFF_PROMISC
)) {
1994 CSR_SETBIT_1(sc
, VGE_RXCTL
,
1995 VGE_RXCTL_RX_PROMISC
);
1997 } else if ((ifp
->if_flags
& IFF_RUNNING
) &&
1998 !(ifp
->if_flags
& IFF_PROMISC
) &&
1999 (sc
->vge_if_flags
& IFF_PROMISC
)) {
2000 CSR_CLRBIT_1(sc
, VGE_RXCTL
,
2001 VGE_RXCTL_RX_PROMISC
);
2007 if (ifp
->if_flags
& IFF_RUNNING
)
2010 sc
->vge_if_flags
= ifp
->if_flags
;
2018 mii
= device_get_softc(sc
->vge_miibus
);
2019 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
2023 uint32_t mask
= ifr
->ifr_reqcap
^ ifp
->if_capenable
;
2025 if (mask
& IFCAP_HWCSUM
) {
2026 ifp
->if_capenable
|= ifr
->ifr_reqcap
& (IFCAP_HWCSUM
);
2027 if (ifp
->if_capenable
& IFCAP_TXCSUM
)
2028 ifp
->if_hwassist
= VGE_CSUM_FEATURES
;
2030 ifp
->if_hwassist
= 0;
2031 if (ifp
->if_flags
& IFF_RUNNING
)
2037 error
= ether_ioctl(ifp
, command
, data
);
2044 vge_watchdog(struct ifnet
*ifp
)
2046 struct vge_softc
*sc
= ifp
->if_softc
;
2048 if_printf(ifp
, "watchdog timeout\n");
2058 * Stop the adapter and free any mbufs allocated to the
2062 vge_stop(struct vge_softc
*sc
)
2064 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2067 ASSERT_SERIALIZED(ifp
->if_serializer
);
2071 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
2073 CSR_WRITE_1(sc
, VGE_CRC3
, VGE_CR3_INT_GMSK
);
2074 CSR_WRITE_1(sc
, VGE_CRS0
, VGE_CR0_STOP
);
2075 CSR_WRITE_4(sc
, VGE_ISR
, 0xFFFFFFFF);
2076 CSR_WRITE_2(sc
, VGE_TXQCSRC
, 0xFFFF);
2077 CSR_WRITE_1(sc
, VGE_RXQCSRC
, 0xFF);
2078 CSR_WRITE_4(sc
, VGE_RXDESC_ADDR_LO
, 0);
2080 if (sc
->vge_head
!= NULL
) {
2081 m_freem(sc
->vge_head
);
2082 sc
->vge_head
= sc
->vge_tail
= NULL
;
2085 /* Free the TX list buffers. */
2086 for (i
= 0; i
< VGE_TX_DESC_CNT
; i
++) {
2087 if (sc
->vge_ldata
.vge_tx_mbuf
[i
] != NULL
) {
2088 bus_dmamap_unload(sc
->vge_ldata
.vge_mtag
,
2089 sc
->vge_ldata
.vge_tx_dmamap
[i
]);
2090 m_freem(sc
->vge_ldata
.vge_tx_mbuf
[i
]);
2091 sc
->vge_ldata
.vge_tx_mbuf
[i
] = NULL
;
2095 /* Free the RX list buffers. */
2096 for (i
= 0; i
< VGE_RX_DESC_CNT
; i
++) {
2097 if (sc
->vge_ldata
.vge_rx_mbuf
[i
] != NULL
) {
2098 bus_dmamap_unload(sc
->vge_ldata
.vge_mtag
,
2099 sc
->vge_ldata
.vge_rx_dmamap
[i
]);
2100 m_freem(sc
->vge_ldata
.vge_rx_mbuf
[i
]);
2101 sc
->vge_ldata
.vge_rx_mbuf
[i
] = NULL
;
2107 * Device suspend routine. Stop the interface and save some PCI
2108 * settings in case the BIOS doesn't restore them properly on
2112 vge_suspend(device_t dev
)
2114 struct vge_softc
*sc
= device_get_softc(dev
);
2115 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2117 lwkt_serialize_enter(ifp
->if_serializer
);
2120 lwkt_serialize_exit(ifp
->if_serializer
);
2126 * Device resume routine. Restore some PCI settings in case the BIOS
2127 * doesn't, re-enable busmastering, and restart the interface if
2131 vge_resume(device_t dev
)
2133 struct vge_softc
*sc
= device_get_softc(dev
);
2134 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2136 /* reenable busmastering */
2137 pci_enable_busmaster(dev
);
2138 pci_enable_io(dev
, SYS_RES_MEMORY
);
2140 lwkt_serialize_enter(ifp
->if_serializer
);
2141 /* reinitialize interface if necessary */
2142 if (ifp
->if_flags
& IFF_UP
)
2146 lwkt_serialize_exit(ifp
->if_serializer
);
2152 * Stop all chip I/O so that the kernel's probe routines don't
2153 * get confused by errant DMAs when rebooting.
2156 vge_shutdown(device_t dev
)
2158 struct vge_softc
*sc
= device_get_softc(dev
);
2159 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2161 lwkt_serialize_enter(ifp
->if_serializer
);
2163 lwkt_serialize_exit(ifp
->if_serializer
);
2167 vge_enable_intr(struct vge_softc
*sc
, uint32_t isr
)
2169 CSR_WRITE_4(sc
, VGE_IMR
, VGE_INTRS
);
2170 CSR_WRITE_4(sc
, VGE_ISR
, isr
);
2171 CSR_WRITE_1(sc
, VGE_CRS3
, VGE_CR3_INT_GMSK
);
2174 #ifdef DEVICE_POLLING
2176 vge_disable_intr(struct vge_softc
*sc
)
2178 CSR_WRITE_4(sc
, VGE_IMR
, 0);
2179 CSR_WRITE_1(sc
, VGE_CRC3
, VGE_CR3_INT_GMSK
);