2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.46 2007/04/03 14:20:52 sephe Exp $
37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
38 * Manuals, sample driver and firmware source kits are available
39 * from http://www.alteon.com/support/openkits.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
51 * filtering and jumbo (9014 byte) frames. The hardware is largely
52 * controlled by firmware, which must be loaded into the NIC during
55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
56 * revision, which supports new features such as extended commands,
57 * extended jumbo receive ring desciptors and a mini receive ring.
59 * Alteon Networks is to be commended for releasing such a vast amount
60 * of development material for the Tigon NIC without requiring an NDA
61 * (although they really should have done it a long time ago). With
62 * any luck, the other vendors will finally wise up and follow Alteon's
65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
66 * this driver by #including it as a C header file. This bloats the
67 * driver somewhat, but it's the easiest method considering that the
68 * driver code and firmware code need to be kept in sync. The source
69 * for the firmware is not provided with the FreeBSD distribution since
70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
72 * The following people deserve special thanks:
73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
75 * - Raymond Lee of Netgear, for providing a pair of Netgear
76 * GA620 Tigon 2 boards for testing
77 * - Ulf Zimmermann, for bringing the GA260 to my attention and
78 * convincing me to write this driver.
79 * - Andrew Gallatin for providing FreeBSD/Alpha support.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
89 #include <sys/queue.h>
90 #include <sys/serialize.h>
93 #include <sys/thread2.h>
96 #include <net/ifq_var.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
102 #include <net/vlan/if_vlan_var.h>
106 #include <netinet/in_systm.h>
107 #include <netinet/in.h>
108 #include <netinet/ip.h>
110 #include <vm/vm.h> /* for vtophys */
111 #include <vm/pmap.h> /* for vtophys */
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
116 #include "if_tireg.h"
121 * Temporarily disable the checksum offload support for now.
122 * Tests with ftp.freesoftware.com show that after about 12 hours,
123 * the firmware will begin calculating completely bogus TX checksums
124 * and refuse to stop until the interface is reset. Unfortunately,
125 * there isn't enough time to fully debug this before the 4.1
126 * release, so this will need to stay off for now.
129 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
131 #define TI_CSUM_FEATURES 0
135 * Various supported device vendors/types and their names.
138 static struct ti_type ti_devs
[] = {
139 { ALT_VENDORID
, ALT_DEVICEID_ACENIC
,
140 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
141 { ALT_VENDORID
, ALT_DEVICEID_ACENIC_COPPER
,
142 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
143 { TC_VENDORID
, TC_DEVICEID_3C985
,
144 "3Com 3c985-SX Gigabit Ethernet" },
145 { NG_VENDORID
, NG_DEVICEID_GA620
,
146 "Netgear GA620 1000baseSX Gigabit Ethernet" },
147 { NG_VENDORID
, NG_DEVICEID_GA620T
,
148 "Netgear GA620 1000baseT Gigabit Ethernet" },
149 { SGI_VENDORID
, SGI_DEVICEID_TIGON
,
150 "Silicon Graphics Gigabit Ethernet" },
151 { DEC_VENDORID
, DEC_DEVICEID_FARALLON_PN9000SX
,
152 "Farallon PN9000SX Gigabit Ethernet" },
156 static int ti_probe(device_t
);
157 static int ti_attach(device_t
);
158 static int ti_detach(device_t
);
159 static void ti_txeof(struct ti_softc
*);
160 static void ti_rxeof(struct ti_softc
*);
162 static void ti_stats_update(struct ti_softc
*);
163 static int ti_encap(struct ti_softc
*, struct mbuf
*, uint32_t *);
165 static void ti_intr(void *);
166 static void ti_start(struct ifnet
*);
167 static int ti_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
168 static void ti_init(void *);
169 static void ti_init2(struct ti_softc
*);
170 static void ti_stop(struct ti_softc
*);
171 static void ti_watchdog(struct ifnet
*);
172 static void ti_shutdown(device_t
);
173 static int ti_ifmedia_upd(struct ifnet
*);
174 static void ti_ifmedia_sts(struct ifnet
*, struct ifmediareq
*);
176 static uint32_t ti_eeprom_putbyte(struct ti_softc
*, int);
177 static uint8_t ti_eeprom_getbyte(struct ti_softc
*, int, uint8_t *);
178 static int ti_read_eeprom(struct ti_softc
*, caddr_t
, int, int);
180 static void ti_add_mcast(struct ti_softc
*, struct ether_addr
*);
181 static void ti_del_mcast(struct ti_softc
*, struct ether_addr
*);
182 static void ti_setmulti(struct ti_softc
*);
184 static void ti_mem(struct ti_softc
*, uint32_t, uint32_t, caddr_t
);
185 static void ti_loadfw(struct ti_softc
*);
186 static void ti_cmd(struct ti_softc
*, struct ti_cmd_desc
*);
187 static void ti_cmd_ext(struct ti_softc
*, struct ti_cmd_desc
*,
189 static void ti_handle_events(struct ti_softc
*);
190 static int ti_alloc_jumbo_mem(struct ti_softc
*);
191 static struct ti_jslot
*
192 ti_jalloc(struct ti_softc
*);
193 static void ti_jfree(void *);
194 static void ti_jref(void *);
195 static int ti_newbuf_std(struct ti_softc
*, int, struct mbuf
*);
196 static int ti_newbuf_mini(struct ti_softc
*, int, struct mbuf
*);
197 static int ti_newbuf_jumbo(struct ti_softc
*, int, struct mbuf
*);
198 static int ti_init_rx_ring_std(struct ti_softc
*);
199 static void ti_free_rx_ring_std(struct ti_softc
*);
200 static int ti_init_rx_ring_jumbo(struct ti_softc
*);
201 static void ti_free_rx_ring_jumbo(struct ti_softc
*);
202 static int ti_init_rx_ring_mini(struct ti_softc
*);
203 static void ti_free_rx_ring_mini(struct ti_softc
*);
204 static void ti_free_tx_ring(struct ti_softc
*);
205 static int ti_init_tx_ring(struct ti_softc
*);
207 static int ti_64bitslot_war(struct ti_softc
*);
208 static int ti_chipinit(struct ti_softc
*);
209 static int ti_gibinit(struct ti_softc
*);
211 static device_method_t ti_methods
[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe
, ti_probe
),
214 DEVMETHOD(device_attach
, ti_attach
),
215 DEVMETHOD(device_detach
, ti_detach
),
216 DEVMETHOD(device_shutdown
, ti_shutdown
),
221 static DEFINE_CLASS_0(ti
, ti_driver
, ti_methods
, sizeof(struct ti_softc
));
222 static devclass_t ti_devclass
;
224 DECLARE_DUMMY_MODULE(if_ti
);
225 DRIVER_MODULE(if_ti
, pci
, ti_driver
, ti_devclass
, 0, 0);
228 * Send an instruction or address to the EEPROM, check for ACK.
231 ti_eeprom_putbyte(struct ti_softc
*sc
, int byte
)
236 * Make sure we're in TX mode.
238 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_TXEN
);
241 * Feed in each bit and stobe the clock.
243 for (i
= 0x80; i
; i
>>= 1) {
245 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_DOUT
);
247 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_DOUT
);
249 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
251 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
257 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_TXEN
);
262 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
263 ack
= CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
) & TI_MLC_EE_DIN
;
264 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
270 * Read a byte of data stored in the EEPROM at address 'addr.'
271 * We have to send two address bytes since the EEPROM can hold
272 * more than 256 bytes of data.
275 ti_eeprom_getbyte(struct ti_softc
*sc
, int addr
, uint8_t *dest
)
277 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
284 * Send write control code to EEPROM.
286 if (ti_eeprom_putbyte(sc
, EEPROM_CTL_WRITE
)) {
287 if_printf(ifp
, "failed to send write command, status: %x\n",
288 CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
));
293 * Send first byte of address of byte we want to read.
295 if (ti_eeprom_putbyte(sc
, (addr
>> 8) & 0xFF)) {
296 if_printf(ifp
, "failed to send address, status: %x\n",
297 CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
));
301 * Send second byte address of byte we want to read.
303 if (ti_eeprom_putbyte(sc
, addr
& 0xFF)) {
304 if_printf(ifp
, "failed to send address, status: %x\n",
305 CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
));
312 * Send read control code to EEPROM.
314 if (ti_eeprom_putbyte(sc
, EEPROM_CTL_READ
)) {
315 if_printf(ifp
, "failed to send read command, status: %x\n",
316 CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
));
321 * Start reading bits from EEPROM.
323 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_TXEN
);
324 for (i
= 0x80; i
; i
>>= 1) {
325 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
327 if (CSR_READ_4(sc
, TI_MISC_LOCAL_CTL
) & TI_MLC_EE_DIN
)
329 TI_CLRBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_EE_CLK
);
336 * No ACK generated for read, so just return byte.
345 * Read a sequence of bytes from the EEPROM.
348 ti_read_eeprom(struct ti_softc
*sc
, caddr_t dest
, int off
, int cnt
)
353 for (i
= 0; i
< cnt
; i
++) {
354 err
= ti_eeprom_getbyte(sc
, off
+ i
, &byte
);
364 * NIC memory access function. Can be used to either clear a section
365 * of NIC local memory or (if buf is non-NULL) copy data into it.
368 ti_mem(struct ti_softc
*sc
, uint32_t addr
, uint32_t len
, caddr_t buf
)
370 int cnt
, segptr
, segsize
;
371 caddr_t ti_winbase
, ptr
;
375 ti_winbase
= (caddr_t
)(sc
->ti_vhandle
+ TI_WINDOW
);
382 segsize
= TI_WINLEN
- (segptr
% TI_WINLEN
);
383 CSR_WRITE_4(sc
, TI_WINBASE
, (segptr
& ~(TI_WINLEN
- 1)));
385 bzero((char *)ti_winbase
+ (segptr
&
386 (TI_WINLEN
- 1)), segsize
);
388 bcopy((char *)ptr
, (char *)ti_winbase
+
389 (segptr
& (TI_WINLEN
- 1)), segsize
);
398 * Load firmware image into the NIC. Check that the firmware revision
399 * is acceptable and see if we want the firmware for the Tigon 1 or
403 ti_loadfw(struct ti_softc
*sc
)
405 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
407 switch(sc
->ti_hwrev
) {
409 if (tigonFwReleaseMajor
!= TI_FIRMWARE_MAJOR
||
410 tigonFwReleaseMinor
!= TI_FIRMWARE_MINOR
||
411 tigonFwReleaseFix
!= TI_FIRMWARE_FIX
) {
412 if_printf(ifp
, "firmware revision mismatch; want "
413 "%d.%d.%d, got %d.%d.%d\n",
414 TI_FIRMWARE_MAJOR
, TI_FIRMWARE_MINOR
,
415 TI_FIRMWARE_FIX
, tigonFwReleaseMajor
,
416 tigonFwReleaseMinor
, tigonFwReleaseFix
);
419 ti_mem(sc
, tigonFwTextAddr
, tigonFwTextLen
,
420 (caddr_t
)tigonFwText
);
421 ti_mem(sc
, tigonFwDataAddr
, tigonFwDataLen
,
422 (caddr_t
)tigonFwData
);
423 ti_mem(sc
, tigonFwRodataAddr
, tigonFwRodataLen
,
424 (caddr_t
)tigonFwRodata
);
425 ti_mem(sc
, tigonFwBssAddr
, tigonFwBssLen
, NULL
);
426 ti_mem(sc
, tigonFwSbssAddr
, tigonFwSbssLen
, NULL
);
427 CSR_WRITE_4(sc
, TI_CPU_PROGRAM_COUNTER
, tigonFwStartAddr
);
429 case TI_HWREV_TIGON_II
:
430 if (tigon2FwReleaseMajor
!= TI_FIRMWARE_MAJOR
||
431 tigon2FwReleaseMinor
!= TI_FIRMWARE_MINOR
||
432 tigon2FwReleaseFix
!= TI_FIRMWARE_FIX
) {
433 if_printf(ifp
, "firmware revision mismatch; want "
434 "%d.%d.%d, got %d.%d.%d\n",
435 TI_FIRMWARE_MAJOR
, TI_FIRMWARE_MINOR
,
436 TI_FIRMWARE_FIX
, tigon2FwReleaseMajor
,
437 tigon2FwReleaseMinor
, tigon2FwReleaseFix
);
440 ti_mem(sc
, tigon2FwTextAddr
, tigon2FwTextLen
,
441 (caddr_t
)tigon2FwText
);
442 ti_mem(sc
, tigon2FwDataAddr
, tigon2FwDataLen
,
443 (caddr_t
)tigon2FwData
);
444 ti_mem(sc
, tigon2FwRodataAddr
, tigon2FwRodataLen
,
445 (caddr_t
)tigon2FwRodata
);
446 ti_mem(sc
, tigon2FwBssAddr
, tigon2FwBssLen
, NULL
);
447 ti_mem(sc
, tigon2FwSbssAddr
, tigon2FwSbssLen
, NULL
);
448 CSR_WRITE_4(sc
, TI_CPU_PROGRAM_COUNTER
, tigon2FwStartAddr
);
451 if_printf(ifp
, "can't load firmware: unknown hardware rev\n");
457 * Send the NIC a command via the command ring.
460 ti_cmd(struct ti_softc
*sc
, struct ti_cmd_desc
*cmd
)
464 if (sc
->ti_rdata
->ti_cmd_ring
== NULL
)
467 index
= sc
->ti_cmd_saved_prodidx
;
468 CSR_WRITE_4(sc
, TI_GCR_CMDRING
+ (index
* 4), *(uint32_t *)(cmd
));
469 TI_INC(index
, TI_CMD_RING_CNT
);
470 CSR_WRITE_4(sc
, TI_MB_CMDPROD_IDX
, index
);
471 sc
->ti_cmd_saved_prodidx
= index
;
475 * Send the NIC an extended command. The 'len' parameter specifies the
476 * number of command slots to include after the initial command.
479 ti_cmd_ext(struct ti_softc
*sc
, struct ti_cmd_desc
*cmd
, caddr_t arg
, int len
)
484 if (sc
->ti_rdata
->ti_cmd_ring
== NULL
)
487 index
= sc
->ti_cmd_saved_prodidx
;
488 CSR_WRITE_4(sc
, TI_GCR_CMDRING
+ (index
* 4), *(uint32_t *)(cmd
));
489 TI_INC(index
, TI_CMD_RING_CNT
);
490 for (i
= 0; i
< len
; i
++) {
491 CSR_WRITE_4(sc
, TI_GCR_CMDRING
+ (index
* 4),
492 *(uint32_t *)(&arg
[i
* 4]));
493 TI_INC(index
, TI_CMD_RING_CNT
);
495 CSR_WRITE_4(sc
, TI_MB_CMDPROD_IDX
, index
);
496 sc
->ti_cmd_saved_prodidx
= index
;
500 * Handle events that have triggered interrupts.
503 ti_handle_events(struct ti_softc
*sc
)
505 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
506 struct ti_event_desc
*e
;
508 if (sc
->ti_rdata
->ti_event_ring
== NULL
)
511 while (sc
->ti_ev_saved_considx
!= sc
->ti_ev_prodidx
.ti_idx
) {
512 e
= &sc
->ti_rdata
->ti_event_ring
[sc
->ti_ev_saved_considx
];
513 switch(e
->ti_event
) {
514 case TI_EV_LINKSTAT_CHANGED
:
515 sc
->ti_linkstat
= e
->ti_code
;
516 if (e
->ti_code
== TI_EV_CODE_LINK_UP
) {
517 if_printf(ifp
, "10/100 link up\n");
518 } else if (e
->ti_code
== TI_EV_CODE_GIG_LINK_UP
) {
519 if_printf(ifp
, "gigabit link up\n");
520 } else if (e
->ti_code
== TI_EV_CODE_LINK_DOWN
) {
521 if_printf(ifp
, "link down\n");
525 if (e
->ti_code
== TI_EV_CODE_ERR_INVAL_CMD
) {
526 if_printf(ifp
, "invalid command\n");
527 } else if (e
->ti_code
== TI_EV_CODE_ERR_UNIMP_CMD
) {
528 if_printf(ifp
, "unknown command\n");
529 } else if (e
->ti_code
== TI_EV_CODE_ERR_BADCFG
) {
530 if_printf(ifp
, "bad config data\n");
533 case TI_EV_FIRMWARE_UP
:
536 case TI_EV_STATS_UPDATED
:
539 case TI_EV_RESET_JUMBO_RING
:
540 case TI_EV_MCAST_UPDATED
:
544 if_printf(ifp
, "unknown event: %d\n", e
->ti_event
);
547 /* Advance the consumer index. */
548 TI_INC(sc
->ti_ev_saved_considx
, TI_EVENT_RING_CNT
);
549 CSR_WRITE_4(sc
, TI_GCR_EVENTCONS_IDX
, sc
->ti_ev_saved_considx
);
554 * Memory management for the jumbo receive ring is a pain in the
555 * butt. We need to allocate at least 9018 bytes of space per frame,
556 * _and_ it has to be contiguous (unless you use the extended
557 * jumbo descriptor format). Using malloc() all the time won't
558 * work: malloc() allocates memory in powers of two, which means we
559 * would end up wasting a considerable amount of space by allocating
560 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
561 * to do our own memory management.
563 * The driver needs to allocate a contiguous chunk of memory at boot
564 * time. We then chop this up ourselves into 9K pieces and use them
565 * as external mbuf storage.
567 * One issue here is how much memory to allocate. The jumbo ring has
568 * 256 slots in it, but at 9K per slot than can consume over 2MB of
569 * RAM. This is a bit much, especially considering we also need
570 * RAM for the standard ring and mini ring (on the Tigon 2). To
571 * save space, we only actually allocate enough memory for 64 slots
572 * by default, which works out to between 500 and 600K. This can
573 * be tuned by changing a #define in if_tireg.h.
577 ti_alloc_jumbo_mem(struct ti_softc
*sc
)
579 struct ti_jslot
*entry
;
583 /* Grab a big chunk o' storage. */
584 sc
->ti_cdata
.ti_jumbo_buf
= contigmalloc(TI_JMEM
, M_DEVBUF
,
585 M_WAITOK
, 0, 0xffffffff, PAGE_SIZE
, 0);
587 if (sc
->ti_cdata
.ti_jumbo_buf
== NULL
) {
588 if_printf(&sc
->arpcom
.ac_if
, "no memory for jumbo buffers!\n");
592 lwkt_serialize_init(&sc
->ti_jslot_serializer
);
593 SLIST_INIT(&sc
->ti_jfree_listhead
);
596 * Now divide it up into 9K pieces and save the addresses
597 * in an array. Note that we play an evil trick here by using
598 * the first few bytes in the buffer to hold the the address
599 * of the softc structure for this interface. This is because
600 * ti_jfree() needs it, but it is called by the mbuf management
601 * code which will not pass it to us explicitly.
603 ptr
= sc
->ti_cdata
.ti_jumbo_buf
;
604 for (i
= 0; i
< TI_JSLOTS
; i
++) {
605 entry
= &sc
->ti_cdata
.ti_jslots
[i
];
610 SLIST_INSERT_HEAD(&sc
->ti_jfree_listhead
, entry
, jslot_link
);
618 * Allocate a jumbo buffer.
620 static struct ti_jslot
*
621 ti_jalloc(struct ti_softc
*sc
)
623 struct ti_jslot
*entry
;
625 lwkt_serialize_enter(&sc
->ti_jslot_serializer
);
626 entry
= SLIST_FIRST(&sc
->ti_jfree_listhead
);
628 SLIST_REMOVE_HEAD(&sc
->ti_jfree_listhead
, jslot_link
);
631 if_printf(&sc
->arpcom
.ac_if
, "no free jumbo buffers\n");
633 lwkt_serialize_exit(&sc
->ti_jslot_serializer
);
638 * Adjust usage count on a jumbo buffer. In general this doesn't
639 * get used much because our jumbo buffers don't get passed around
640 * too much, but it's implemented for correctness.
645 struct ti_jslot
*entry
= (struct ti_jslot
*)arg
;
646 struct ti_softc
*sc
= entry
->ti_sc
;
649 panic("ti_jref: can't find softc pointer!");
651 if (&sc
->ti_cdata
.ti_jslots
[entry
->ti_slot
] != entry
)
652 panic("ti_jref: asked to reference buffer "
653 "that we don't manage!");
654 if (entry
->ti_inuse
== 0)
655 panic("ti_jref: buffer already free!");
656 atomic_add_int(&entry
->ti_inuse
, 1);
660 * Release a jumbo buffer.
665 struct ti_jslot
*entry
= (struct ti_jslot
*)arg
;
666 struct ti_softc
*sc
= entry
->ti_sc
;
669 panic("ti_jref: can't find softc pointer!");
671 if (&sc
->ti_cdata
.ti_jslots
[entry
->ti_slot
] != entry
)
672 panic("ti_jref: asked to reference buffer "
673 "that we don't manage!");
674 if (entry
->ti_inuse
== 0)
675 panic("ti_jref: buffer already free!");
676 lwkt_serialize_enter(&sc
->ti_jslot_serializer
);
677 atomic_subtract_int(&entry
->ti_inuse
, 1);
678 if (entry
->ti_inuse
== 0)
679 SLIST_INSERT_HEAD(&sc
->ti_jfree_listhead
, entry
, jslot_link
);
680 lwkt_serialize_exit(&sc
->ti_jslot_serializer
);
685 * Intialize a standard receive ring descriptor.
688 ti_newbuf_std(struct ti_softc
*sc
, int i
, struct mbuf
*m
)
691 struct ti_rx_desc
*r
;
694 m_new
= m_getcl(MB_DONTWAIT
, MT_DATA
, M_PKTHDR
);
697 m_new
->m_len
= m_new
->m_pkthdr
.len
= MCLBYTES
;
700 m_new
->m_len
= m_new
->m_pkthdr
.len
= MCLBYTES
;
701 m_new
->m_data
= m_new
->m_ext
.ext_buf
;
705 m_adj(m_new
, ETHER_ALIGN
);
706 sc
->ti_cdata
.ti_rx_std_chain
[i
] = m_new
;
707 r
= &sc
->ti_rdata
->ti_rx_std_ring
[i
];
708 TI_HOSTADDR(r
->ti_addr
) = vtophys(mtod(m_new
, caddr_t
));
709 r
->ti_type
= TI_BDTYPE_RECV_BD
;
711 if (sc
->arpcom
.ac_if
.if_hwassist
)
712 r
->ti_flags
|= TI_BDFLAG_TCP_UDP_CKSUM
| TI_BDFLAG_IP_CKSUM
;
713 r
->ti_len
= m_new
->m_len
;
720 * Intialize a mini receive ring descriptor. This only applies to
724 ti_newbuf_mini(struct ti_softc
*sc
, int i
, struct mbuf
*m
)
727 struct ti_rx_desc
*r
;
730 MGETHDR(m_new
, MB_DONTWAIT
, MT_DATA
);
734 m_new
->m_len
= m_new
->m_pkthdr
.len
= MHLEN
;
737 m_new
->m_data
= m_new
->m_pktdat
;
738 m_new
->m_len
= m_new
->m_pkthdr
.len
= MHLEN
;
741 m_adj(m_new
, ETHER_ALIGN
);
742 r
= &sc
->ti_rdata
->ti_rx_mini_ring
[i
];
743 sc
->ti_cdata
.ti_rx_mini_chain
[i
] = m_new
;
744 TI_HOSTADDR(r
->ti_addr
) = vtophys(mtod(m_new
, caddr_t
));
745 r
->ti_type
= TI_BDTYPE_RECV_BD
;
746 r
->ti_flags
= TI_BDFLAG_MINI_RING
;
747 if (sc
->arpcom
.ac_if
.if_hwassist
)
748 r
->ti_flags
|= TI_BDFLAG_TCP_UDP_CKSUM
| TI_BDFLAG_IP_CKSUM
;
749 r
->ti_len
= m_new
->m_len
;
756 * Initialize a jumbo receive ring descriptor. This allocates
757 * a jumbo buffer from the pool managed internally by the driver.
760 ti_newbuf_jumbo(struct ti_softc
*sc
, int i
, struct mbuf
*m
)
763 struct ti_rx_desc
*r
;
764 struct ti_jslot
*buf
;
767 /* Allocate the mbuf. */
768 MGETHDR(m_new
, MB_DONTWAIT
, MT_DATA
);
773 /* Allocate the jumbo buffer */
777 if_printf(&sc
->arpcom
.ac_if
, "jumbo allocation failed "
778 "-- packet dropped!\n");
782 /* Attach the buffer to the mbuf. */
783 m_new
->m_ext
.ext_arg
= buf
;
784 m_new
->m_ext
.ext_buf
= buf
->ti_buf
;
785 m_new
->m_ext
.ext_free
= ti_jfree
;
786 m_new
->m_ext
.ext_ref
= ti_jref
;
787 m_new
->m_ext
.ext_size
= TI_JUMBO_FRAMELEN
;
789 m_new
->m_flags
|= M_EXT
;
792 * We're re-using a previously allocated mbuf;
793 * be sure to re-init pointers and lengths to
796 KKASSERT(m
->m_flags
& M_EXT
);
799 m_new
->m_data
= m_new
->m_ext
.ext_buf
;
800 m_new
->m_len
= m_new
->m_pkthdr
.len
= m_new
->m_ext
.ext_size
;
802 m_adj(m_new
, ETHER_ALIGN
);
803 /* Set up the descriptor. */
804 r
= &sc
->ti_rdata
->ti_rx_jumbo_ring
[i
];
805 sc
->ti_cdata
.ti_rx_jumbo_chain
[i
] = m_new
;
806 TI_HOSTADDR(r
->ti_addr
) = vtophys(mtod(m_new
, caddr_t
));
807 r
->ti_type
= TI_BDTYPE_RECV_JUMBO_BD
;
808 r
->ti_flags
= TI_BDFLAG_JUMBO_RING
;
809 if (sc
->arpcom
.ac_if
.if_hwassist
)
810 r
->ti_flags
|= TI_BDFLAG_TCP_UDP_CKSUM
| TI_BDFLAG_IP_CKSUM
;
811 r
->ti_len
= m_new
->m_len
;
818 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
819 * that's 1MB or memory, which is a lot. For now, we fill only the first
820 * 256 ring entries and hope that our CPU is fast enough to keep up with
824 ti_init_rx_ring_std(struct ti_softc
*sc
)
827 struct ti_cmd_desc cmd
;
829 for (i
= 0; i
< TI_SSLOTS
; i
++) {
830 if (ti_newbuf_std(sc
, i
, NULL
) == ENOBUFS
)
834 TI_UPDATE_STDPROD(sc
, i
- 1);
841 ti_free_rx_ring_std(struct ti_softc
*sc
)
845 for (i
= 0; i
< TI_STD_RX_RING_CNT
; i
++) {
846 if (sc
->ti_cdata
.ti_rx_std_chain
[i
] != NULL
) {
847 m_freem(sc
->ti_cdata
.ti_rx_std_chain
[i
]);
848 sc
->ti_cdata
.ti_rx_std_chain
[i
] = NULL
;
850 bzero(&sc
->ti_rdata
->ti_rx_std_ring
[i
],
851 sizeof(struct ti_rx_desc
));
856 ti_init_rx_ring_jumbo(struct ti_softc
*sc
)
859 struct ti_cmd_desc cmd
;
861 for (i
= 0; i
< TI_JUMBO_RX_RING_CNT
; i
++) {
862 if (ti_newbuf_jumbo(sc
, i
, NULL
) == ENOBUFS
)
866 TI_UPDATE_JUMBOPROD(sc
, i
- 1);
867 sc
->ti_jumbo
= i
- 1;
873 ti_free_rx_ring_jumbo(struct ti_softc
*sc
)
877 for (i
= 0; i
< TI_JUMBO_RX_RING_CNT
; i
++) {
878 if (sc
->ti_cdata
.ti_rx_jumbo_chain
[i
] != NULL
) {
879 m_freem(sc
->ti_cdata
.ti_rx_jumbo_chain
[i
]);
880 sc
->ti_cdata
.ti_rx_jumbo_chain
[i
] = NULL
;
882 bzero(&sc
->ti_rdata
->ti_rx_jumbo_ring
[i
],
883 sizeof(struct ti_rx_desc
));
888 ti_init_rx_ring_mini(struct ti_softc
*sc
)
892 for (i
= 0; i
< TI_MSLOTS
; i
++) {
893 if (ti_newbuf_mini(sc
, i
, NULL
) == ENOBUFS
)
897 TI_UPDATE_MINIPROD(sc
, i
- 1);
904 ti_free_rx_ring_mini(struct ti_softc
*sc
)
908 for (i
= 0; i
< TI_MINI_RX_RING_CNT
; i
++) {
909 if (sc
->ti_cdata
.ti_rx_mini_chain
[i
] != NULL
) {
910 m_freem(sc
->ti_cdata
.ti_rx_mini_chain
[i
]);
911 sc
->ti_cdata
.ti_rx_mini_chain
[i
] = NULL
;
913 bzero(&sc
->ti_rdata
->ti_rx_mini_ring
[i
],
914 sizeof(struct ti_rx_desc
));
919 ti_free_tx_ring(struct ti_softc
*sc
)
923 if (sc
->ti_rdata
->ti_tx_ring
== NULL
)
926 for (i
= 0; i
< TI_TX_RING_CNT
; i
++) {
927 if (sc
->ti_cdata
.ti_tx_chain
[i
] != NULL
) {
928 m_freem(sc
->ti_cdata
.ti_tx_chain
[i
]);
929 sc
->ti_cdata
.ti_tx_chain
[i
] = NULL
;
931 bzero(&sc
->ti_rdata
->ti_tx_ring
[i
],
932 sizeof(struct ti_tx_desc
));
937 ti_init_tx_ring(struct ti_softc
*sc
)
940 sc
->ti_tx_saved_considx
= 0;
941 CSR_WRITE_4(sc
, TI_MB_SENDPROD_IDX
, 0);
946 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
947 * but we have to support the old way too so that Tigon 1 cards will
951 ti_add_mcast(struct ti_softc
*sc
, struct ether_addr
*addr
)
953 struct ti_cmd_desc cmd
;
955 uint32_t ext
[2] = {0, 0};
957 m
= (uint16_t *)&addr
->octet
[0];
959 switch(sc
->ti_hwrev
) {
961 CSR_WRITE_4(sc
, TI_GCR_MAR0
, htons(m
[0]));
962 CSR_WRITE_4(sc
, TI_GCR_MAR1
, (htons(m
[1]) << 16) | htons(m
[2]));
963 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR
, 0, 0);
965 case TI_HWREV_TIGON_II
:
966 ext
[0] = htons(m
[0]);
967 ext
[1] = (htons(m
[1]) << 16) | htons(m
[2]);
968 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST
, 0, 0, (caddr_t
)&ext
, 2);
971 if_printf(&sc
->arpcom
.ac_if
, "unknown hwrev\n");
977 ti_del_mcast(struct ti_softc
*sc
, struct ether_addr
*addr
)
979 struct ti_cmd_desc cmd
;
981 uint32_t ext
[2] = {0, 0};
983 m
= (uint16_t *)&addr
->octet
[0];
985 switch(sc
->ti_hwrev
) {
987 CSR_WRITE_4(sc
, TI_GCR_MAR0
, htons(m
[0]));
988 CSR_WRITE_4(sc
, TI_GCR_MAR1
, (htons(m
[1]) << 16) | htons(m
[2]));
989 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR
, 0, 0);
991 case TI_HWREV_TIGON_II
:
992 ext
[0] = htons(m
[0]);
993 ext
[1] = (htons(m
[1]) << 16) | htons(m
[2]);
994 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST
, 0, 0, (caddr_t
)&ext
, 2);
997 if_printf(&sc
->arpcom
.ac_if
, "unknown hwrev\n");
1003 * Configure the Tigon's multicast address filter.
1005 * The actual multicast table management is a bit of a pain, thanks to
1006 * slight brain damage on the part of both Alteon and us. With our
1007 * multicast code, we are only alerted when the multicast address table
1008 * changes and at that point we only have the current list of addresses:
1009 * we only know the current state, not the previous state, so we don't
1010 * actually know what addresses were removed or added. The firmware has
1011 * state, but we can't get our grubby mits on it, and there is no 'delete
1012 * all multicast addresses' command. Hence, we have to maintain our own
1013 * state so we know what addresses have been programmed into the NIC at
1017 ti_setmulti(struct ti_softc
*sc
)
1019 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1020 struct ifmultiaddr
*ifma
;
1021 struct ti_cmd_desc cmd
;
1022 struct ti_mc_entry
*mc
;
1025 if (ifp
->if_flags
& IFF_ALLMULTI
) {
1026 TI_DO_CMD(TI_CMD_SET_ALLMULTI
, TI_CMD_CODE_ALLMULTI_ENB
, 0);
1030 TI_DO_CMD(TI_CMD_SET_ALLMULTI
, TI_CMD_CODE_ALLMULTI_DIS
, 0);
1032 /* Disable interrupts. */
1033 intrs
= CSR_READ_4(sc
, TI_MB_HOSTINTR
);
1034 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 1);
1036 /* First, zot all the existing filters. */
1037 while (sc
->ti_mc_listhead
.slh_first
!= NULL
) {
1038 mc
= sc
->ti_mc_listhead
.slh_first
;
1039 ti_del_mcast(sc
, &mc
->mc_addr
);
1040 SLIST_REMOVE_HEAD(&sc
->ti_mc_listhead
, mc_entries
);
1041 kfree(mc
, M_DEVBUF
);
1044 /* Now program new ones. */
1045 LIST_FOREACH(ifma
, &ifp
->if_multiaddrs
, ifma_link
) {
1046 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
1048 mc
= kmalloc(sizeof(struct ti_mc_entry
), M_DEVBUF
, M_INTWAIT
);
1049 bcopy(LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
),
1050 &mc
->mc_addr
, ETHER_ADDR_LEN
);
1051 SLIST_INSERT_HEAD(&sc
->ti_mc_listhead
, mc
, mc_entries
);
1052 ti_add_mcast(sc
, &mc
->mc_addr
);
1055 /* Re-enable interrupts. */
1056 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, intrs
);
1060 * Check to see if the BIOS has configured us for a 64 bit slot when
1061 * we aren't actually in one. If we detect this condition, we can work
1062 * around it on the Tigon 2 by setting a bit in the PCI state register,
1063 * but for the Tigon 1 we must give up and abort the interface attach.
1066 ti_64bitslot_war(struct ti_softc
*sc
)
1068 if ((CSR_READ_4(sc
, TI_PCI_STATE
) & TI_PCISTATE_32BIT_BUS
) == 0) {
1069 CSR_WRITE_4(sc
, 0x600, 0);
1070 CSR_WRITE_4(sc
, 0x604, 0);
1071 CSR_WRITE_4(sc
, 0x600, 0x5555AAAA);
1072 if (CSR_READ_4(sc
, 0x604) == 0x5555AAAA) {
1073 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1075 TI_SETBIT(sc
, TI_PCI_STATE
, TI_PCISTATE_32BIT_BUS
);
1084 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1085 * self-test results.
1088 ti_chipinit(struct ti_softc
*sc
)
1090 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1092 uint32_t pci_writemax
= 0;
1094 /* Initialize link to down state. */
1095 sc
->ti_linkstat
= TI_EV_CODE_LINK_DOWN
;
1097 if (ifp
->if_capenable
& IFCAP_HWCSUM
)
1098 ifp
->if_hwassist
= TI_CSUM_FEATURES
;
1100 ifp
->if_hwassist
= 0;
1102 /* Set endianness before we access any non-PCI registers. */
1103 #if BYTE_ORDER == BIG_ENDIAN
1104 CSR_WRITE_4(sc
, TI_MISC_HOST_CTL
,
1105 TI_MHC_BIGENDIAN_INIT
| (TI_MHC_BIGENDIAN_INIT
<< 24));
1107 CSR_WRITE_4(sc
, TI_MISC_HOST_CTL
,
1108 TI_MHC_LITTLEENDIAN_INIT
| (TI_MHC_LITTLEENDIAN_INIT
<< 24));
1111 /* Check the ROM failed bit to see if self-tests passed. */
1112 if (CSR_READ_4(sc
, TI_CPU_STATE
) & TI_CPUSTATE_ROMFAIL
) {
1113 if_printf(ifp
, "board self-diagnostics failed!\n");
1118 TI_SETBIT(sc
, TI_CPU_STATE
, TI_CPUSTATE_HALT
);
1120 /* Figure out the hardware revision. */
1121 switch(CSR_READ_4(sc
, TI_MISC_HOST_CTL
) & TI_MHC_CHIP_REV_MASK
) {
1122 case TI_REV_TIGON_I
:
1123 sc
->ti_hwrev
= TI_HWREV_TIGON
;
1125 case TI_REV_TIGON_II
:
1126 sc
->ti_hwrev
= TI_HWREV_TIGON_II
;
1129 if_printf(ifp
, "unsupported chip revision\n");
1133 /* Do special setup for Tigon 2. */
1134 if (sc
->ti_hwrev
== TI_HWREV_TIGON_II
) {
1135 TI_SETBIT(sc
, TI_CPU_CTL_B
, TI_CPUSTATE_HALT
);
1136 TI_SETBIT(sc
, TI_MISC_LOCAL_CTL
, TI_MLC_SRAM_BANK_512K
);
1137 TI_SETBIT(sc
, TI_MISC_CONF
, TI_MCR_SRAM_SYNCHRONOUS
);
1140 /* Set up the PCI state register. */
1141 CSR_WRITE_4(sc
, TI_PCI_STATE
, TI_PCI_READ_CMD
|TI_PCI_WRITE_CMD
);
1142 if (sc
->ti_hwrev
== TI_HWREV_TIGON_II
) {
1143 TI_SETBIT(sc
, TI_PCI_STATE
, TI_PCISTATE_USE_MEM_RD_MULT
);
1146 /* Clear the read/write max DMA parameters. */
1147 TI_CLRBIT(sc
, TI_PCI_STATE
, (TI_PCISTATE_WRITE_MAXDMA
|
1148 TI_PCISTATE_READ_MAXDMA
));
1150 /* Get cache line size. */
1151 cacheline
= CSR_READ_4(sc
, TI_PCI_BIST
) & 0xFF;
1154 * If the system has set enabled the PCI memory write
1155 * and invalidate command in the command register, set
1156 * the write max parameter accordingly. This is necessary
1157 * to use MWI with the Tigon 2.
1159 if (CSR_READ_4(sc
, TI_PCI_CMDSTAT
) & PCIM_CMD_MWIEN
) {
1169 /* Disable PCI memory write and invalidate. */
1171 if_printf(ifp
, "cache line size %d not "
1172 "supported; disabling PCI MWI\n",
1175 CSR_WRITE_4(sc
, TI_PCI_CMDSTAT
, CSR_READ_4(sc
,
1176 TI_PCI_CMDSTAT
) & ~PCIM_CMD_MWIEN
);
1181 TI_SETBIT(sc
, TI_PCI_STATE
, pci_writemax
);
1183 /* This sets the min dma param all the way up (0xff). */
1184 TI_SETBIT(sc
, TI_PCI_STATE
, TI_PCISTATE_MINDMA
);
1186 /* Configure DMA variables. */
1187 #if BYTE_ORDER == BIG_ENDIAN
1188 CSR_WRITE_4(sc
, TI_GCR_OPMODE
, TI_OPMODE_BYTESWAP_BD
|
1189 TI_OPMODE_BYTESWAP_DATA
| TI_OPMODE_WORDSWAP_BD
|
1190 TI_OPMODE_WARN_ENB
| TI_OPMODE_FATAL_ENB
|
1191 TI_OPMODE_DONT_FRAG_JUMBO
);
1193 CSR_WRITE_4(sc
, TI_GCR_OPMODE
, TI_OPMODE_BYTESWAP_DATA
|
1194 TI_OPMODE_WORDSWAP_BD
|TI_OPMODE_DONT_FRAG_JUMBO
|
1195 TI_OPMODE_WARN_ENB
|TI_OPMODE_FATAL_ENB
);
1199 * Only allow 1 DMA channel to be active at a time.
1200 * I don't think this is a good idea, but without it
1201 * the firmware racks up lots of nicDmaReadRingFull
1202 * errors. This is not compatible with hardware checksums.
1204 if (ifp
->if_hwassist
== 0)
1205 TI_SETBIT(sc
, TI_GCR_OPMODE
, TI_OPMODE_1_DMA_ACTIVE
);
1207 /* Recommended settings from Tigon manual. */
1208 CSR_WRITE_4(sc
, TI_GCR_DMA_WRITECFG
, TI_DMA_STATE_THRESH_8W
);
1209 CSR_WRITE_4(sc
, TI_GCR_DMA_READCFG
, TI_DMA_STATE_THRESH_8W
);
1211 if (ti_64bitslot_war(sc
)) {
1212 if_printf(ifp
, "bios thinks we're in a 64 bit slot, "
1221 * Initialize the general information block and firmware, and
1222 * start the CPU(s) running.
1225 ti_gibinit(struct ti_softc
*sc
)
1227 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1231 /* Disable interrupts for now. */
1232 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 1);
1234 /* Tell the chip where to find the general information block. */
1235 CSR_WRITE_4(sc
, TI_GCR_GENINFO_HI
, 0);
1236 CSR_WRITE_4(sc
, TI_GCR_GENINFO_LO
, vtophys(&sc
->ti_rdata
->ti_info
));
1238 /* Load the firmware into SRAM. */
1241 /* Set up the contents of the general info and ring control blocks. */
1243 /* Set up the event ring and producer pointer. */
1244 rcb
= &sc
->ti_rdata
->ti_info
.ti_ev_rcb
;
1246 TI_HOSTADDR(rcb
->ti_hostaddr
) = vtophys(&sc
->ti_rdata
->ti_event_ring
);
1248 TI_HOSTADDR(sc
->ti_rdata
->ti_info
.ti_ev_prodidx_ptr
) =
1249 vtophys(&sc
->ti_ev_prodidx
);
1250 sc
->ti_ev_prodidx
.ti_idx
= 0;
1251 CSR_WRITE_4(sc
, TI_GCR_EVENTCONS_IDX
, 0);
1252 sc
->ti_ev_saved_considx
= 0;
1254 /* Set up the command ring and producer mailbox. */
1255 rcb
= &sc
->ti_rdata
->ti_info
.ti_cmd_rcb
;
1257 sc
->ti_rdata
->ti_cmd_ring
=
1258 (struct ti_cmd_desc
*)(sc
->ti_vhandle
+ TI_GCR_CMDRING
);
1259 TI_HOSTADDR(rcb
->ti_hostaddr
) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING
);
1261 rcb
->ti_max_len
= 0;
1262 for (i
= 0; i
< TI_CMD_RING_CNT
; i
++)
1263 CSR_WRITE_4(sc
, TI_GCR_CMDRING
+ (i
* 4), 0);
1264 CSR_WRITE_4(sc
, TI_GCR_CMDCONS_IDX
, 0);
1265 CSR_WRITE_4(sc
, TI_MB_CMDPROD_IDX
, 0);
1266 sc
->ti_cmd_saved_prodidx
= 0;
1269 * Assign the address of the stats refresh buffer.
1270 * We re-use the current stats buffer for this to
1273 TI_HOSTADDR(sc
->ti_rdata
->ti_info
.ti_refresh_stats_ptr
) =
1274 vtophys(&sc
->ti_rdata
->ti_info
.ti_stats
);
1276 /* Set up the standard receive ring. */
1277 rcb
= &sc
->ti_rdata
->ti_info
.ti_std_rx_rcb
;
1278 TI_HOSTADDR(rcb
->ti_hostaddr
) = vtophys(&sc
->ti_rdata
->ti_rx_std_ring
);
1279 rcb
->ti_max_len
= TI_FRAMELEN
;
1281 if (ifp
->if_hwassist
)
1282 rcb
->ti_flags
|= TI_RCB_FLAG_TCP_UDP_CKSUM
|
1283 TI_RCB_FLAG_IP_CKSUM
| TI_RCB_FLAG_NO_PHDR_CKSUM
;
1284 rcb
->ti_flags
|= TI_RCB_FLAG_VLAN_ASSIST
;
1286 /* Set up the jumbo receive ring. */
1287 rcb
= &sc
->ti_rdata
->ti_info
.ti_jumbo_rx_rcb
;
1288 TI_HOSTADDR(rcb
->ti_hostaddr
) =
1289 vtophys(&sc
->ti_rdata
->ti_rx_jumbo_ring
);
1290 rcb
->ti_max_len
= TI_JUMBO_FRAMELEN
;
1292 if (ifp
->if_hwassist
)
1293 rcb
->ti_flags
|= TI_RCB_FLAG_TCP_UDP_CKSUM
|
1294 TI_RCB_FLAG_IP_CKSUM
| TI_RCB_FLAG_NO_PHDR_CKSUM
;
1295 rcb
->ti_flags
|= TI_RCB_FLAG_VLAN_ASSIST
;
1298 * Set up the mini ring. Only activated on the
1299 * Tigon 2 but the slot in the config block is
1300 * still there on the Tigon 1.
1302 rcb
= &sc
->ti_rdata
->ti_info
.ti_mini_rx_rcb
;
1303 TI_HOSTADDR(rcb
->ti_hostaddr
) =
1304 vtophys(&sc
->ti_rdata
->ti_rx_mini_ring
);
1305 rcb
->ti_max_len
= MHLEN
- ETHER_ALIGN
;
1306 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1307 rcb
->ti_flags
= TI_RCB_FLAG_RING_DISABLED
;
1310 if (ifp
->if_hwassist
)
1311 rcb
->ti_flags
|= TI_RCB_FLAG_TCP_UDP_CKSUM
|
1312 TI_RCB_FLAG_IP_CKSUM
| TI_RCB_FLAG_NO_PHDR_CKSUM
;
1313 rcb
->ti_flags
|= TI_RCB_FLAG_VLAN_ASSIST
;
1316 * Set up the receive return ring.
1318 rcb
= &sc
->ti_rdata
->ti_info
.ti_return_rcb
;
1319 TI_HOSTADDR(rcb
->ti_hostaddr
) =
1320 vtophys(&sc
->ti_rdata
->ti_rx_return_ring
);
1322 rcb
->ti_max_len
= TI_RETURN_RING_CNT
;
1323 TI_HOSTADDR(sc
->ti_rdata
->ti_info
.ti_return_prodidx_ptr
) =
1324 vtophys(&sc
->ti_return_prodidx
);
1327 * Set up the tx ring. Note: for the Tigon 2, we have the option
1328 * of putting the transmit ring in the host's address space and
1329 * letting the chip DMA it instead of leaving the ring in the NIC's
1330 * memory and accessing it through the shared memory region. We
1331 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1332 * so we have to revert to the shared memory scheme if we detect
1335 CSR_WRITE_4(sc
, TI_WINBASE
, TI_TX_RING_BASE
);
1336 if (sc
->ti_hwrev
== TI_HWREV_TIGON
) {
1337 sc
->ti_rdata
->ti_tx_ring_nic
=
1338 (struct ti_tx_desc
*)(sc
->ti_vhandle
+ TI_WINDOW
);
1340 bzero(sc
->ti_rdata
->ti_tx_ring
,
1341 TI_TX_RING_CNT
* sizeof(struct ti_tx_desc
));
1342 rcb
= &sc
->ti_rdata
->ti_info
.ti_tx_rcb
;
1343 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1346 rcb
->ti_flags
= TI_RCB_FLAG_HOST_RING
;
1347 rcb
->ti_flags
|= TI_RCB_FLAG_VLAN_ASSIST
;
1348 if (ifp
->if_hwassist
)
1349 rcb
->ti_flags
|= TI_RCB_FLAG_TCP_UDP_CKSUM
|
1350 TI_RCB_FLAG_IP_CKSUM
| TI_RCB_FLAG_NO_PHDR_CKSUM
;
1351 rcb
->ti_max_len
= TI_TX_RING_CNT
;
1352 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1353 TI_HOSTADDR(rcb
->ti_hostaddr
) = TI_TX_RING_BASE
;
1355 TI_HOSTADDR(rcb
->ti_hostaddr
) =
1356 vtophys(&sc
->ti_rdata
->ti_tx_ring
);
1357 TI_HOSTADDR(sc
->ti_rdata
->ti_info
.ti_tx_considx_ptr
) =
1358 vtophys(&sc
->ti_tx_considx
);
1360 /* Set up tuneables */
1361 if (ifp
->if_mtu
> (ETHERMTU
+ ETHER_HDR_LEN
+ ETHER_CRC_LEN
))
1362 CSR_WRITE_4(sc
, TI_GCR_RX_COAL_TICKS
,
1363 (sc
->ti_rx_coal_ticks
/ 10));
1365 CSR_WRITE_4(sc
, TI_GCR_RX_COAL_TICKS
, sc
->ti_rx_coal_ticks
);
1366 CSR_WRITE_4(sc
, TI_GCR_TX_COAL_TICKS
, sc
->ti_tx_coal_ticks
);
1367 CSR_WRITE_4(sc
, TI_GCR_STAT_TICKS
, sc
->ti_stat_ticks
);
1368 CSR_WRITE_4(sc
, TI_GCR_RX_MAX_COAL_BD
, sc
->ti_rx_max_coal_bds
);
1369 CSR_WRITE_4(sc
, TI_GCR_TX_MAX_COAL_BD
, sc
->ti_tx_max_coal_bds
);
1370 CSR_WRITE_4(sc
, TI_GCR_TX_BUFFER_RATIO
, sc
->ti_tx_buf_ratio
);
1372 /* Turn interrupts on. */
1373 CSR_WRITE_4(sc
, TI_GCR_MASK_INTRS
, 0);
1374 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 0);
1377 TI_CLRBIT(sc
, TI_CPU_STATE
, (TI_CPUSTATE_HALT
|TI_CPUSTATE_STEP
));
1383 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1384 * against our list and return its name if we find a match.
1387 ti_probe(device_t dev
)
1390 uint16_t vendor
, product
;
1392 vendor
= pci_get_vendor(dev
);
1393 product
= pci_get_device(dev
);
1395 for (t
= ti_devs
; t
->ti_name
!= NULL
; t
++) {
1396 if (vendor
== t
->ti_vid
&& product
== t
->ti_did
) {
1397 device_set_desc(dev
, t
->ti_name
);
1406 ti_attach(device_t dev
)
1408 struct ti_softc
*sc
;
1411 uint8_t eaddr
[ETHER_ADDR_LEN
];
1413 sc
= device_get_softc(dev
);
1414 ifp
= &sc
->arpcom
.ac_if
;
1415 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
1416 ifp
->if_capabilities
= IFCAP_HWCSUM
|
1417 IFCAP_VLAN_HWTAGGING
| IFCAP_VLAN_MTU
;
1418 ifp
->if_capenable
= ifp
->if_capabilities
;
1420 pci_enable_busmaster(dev
);
1423 * Initialize media before any possible error may occur,
1424 * so we can destroy it unconditionally, if an error occurs later on.
1426 ifmedia_init(&sc
->ifmedia
, IFM_IMASK
, ti_ifmedia_upd
, ti_ifmedia_sts
);
1429 sc
->ti_res
= bus_alloc_resource_any(dev
, SYS_RES_MEMORY
, &rid
,
1432 if (sc
->ti_res
== NULL
) {
1433 device_printf(dev
, "couldn't map memory\n");
1438 sc
->ti_btag
= rman_get_bustag(sc
->ti_res
);
1439 sc
->ti_bhandle
= rman_get_bushandle(sc
->ti_res
);
1440 sc
->ti_vhandle
= (vm_offset_t
)rman_get_virtual(sc
->ti_res
);
1442 /* Allocate interrupt */
1444 sc
->ti_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
1445 RF_SHAREABLE
| RF_ACTIVE
);
1446 if (sc
->ti_irq
== NULL
) {
1447 device_printf(dev
, "couldn't map interrupt\n");
1452 if (ti_chipinit(sc
)) {
1453 device_printf(dev
, "chip initialization failed\n");
1458 /* Zero out the NIC's on-board SRAM. */
1459 ti_mem(sc
, 0x2000, 0x100000 - 0x2000, NULL
);
1461 /* Init again -- zeroing memory may have clobbered some registers. */
1462 if (ti_chipinit(sc
)) {
1463 device_printf(dev
, "chip initialization failed\n");
1469 * Get station address from the EEPROM. Note: the manual states
1470 * that the MAC address is at offset 0x8c, however the data is
1471 * stored as two longwords (since that's how it's loaded into
1472 * the NIC). This means the MAC address is actually preceeded
1473 * by two zero bytes. We need to skip over those.
1475 if (ti_read_eeprom(sc
, eaddr
, TI_EE_MAC_OFFSET
+ 2, ETHER_ADDR_LEN
)) {
1476 device_printf(dev
, "failed to read station address\n");
1481 /* Allocate the general information block and ring buffers. */
1482 sc
->ti_rdata
= contigmalloc(sizeof(struct ti_ring_data
), M_DEVBUF
,
1483 M_WAITOK
, 0, 0xffffffff, PAGE_SIZE
, 0);
1485 if (sc
->ti_rdata
== NULL
) {
1486 device_printf(dev
, "no memory for list buffers!\n");
1491 bzero(sc
->ti_rdata
, sizeof(struct ti_ring_data
));
1493 /* Try to allocate memory for jumbo buffers. */
1494 if (ti_alloc_jumbo_mem(sc
)) {
1495 device_printf(dev
, "jumbo buffer allocation failed\n");
1501 * We really need a better way to tell a 1000baseTX card
1502 * from a 1000baseSX one, since in theory there could be
1503 * OEMed 1000baseTX cards from lame vendors who aren't
1504 * clever enough to change the PCI ID. For the moment
1505 * though, the AceNIC is the only copper card available.
1507 if (pci_get_vendor(dev
) == ALT_VENDORID
&&
1508 pci_get_device(dev
) == ALT_DEVICEID_ACENIC_COPPER
)
1510 /* Ok, it's not the only copper card available. */
1511 if (pci_get_vendor(dev
) == NG_VENDORID
&&
1512 pci_get_device(dev
) == NG_DEVICEID_GA620T
)
1515 /* Set default tuneable values. */
1516 sc
->ti_stat_ticks
= 2 * TI_TICKS_PER_SEC
;
1517 sc
->ti_rx_coal_ticks
= TI_TICKS_PER_SEC
/ 5000;
1518 sc
->ti_tx_coal_ticks
= TI_TICKS_PER_SEC
/ 500;
1519 sc
->ti_rx_max_coal_bds
= 64;
1520 sc
->ti_tx_max_coal_bds
= 128;
1521 sc
->ti_tx_buf_ratio
= 21;
1523 /* Set up ifnet structure */
1525 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
1526 ifp
->if_ioctl
= ti_ioctl
;
1527 ifp
->if_start
= ti_start
;
1528 ifp
->if_watchdog
= ti_watchdog
;
1529 ifp
->if_init
= ti_init
;
1530 ifp
->if_mtu
= ETHERMTU
;
1531 ifq_set_maxlen(&ifp
->if_snd
, TI_TX_RING_CNT
- 1);
1532 ifq_set_ready(&ifp
->if_snd
);
1534 /* Set up ifmedia support. */
1535 if (sc
->ti_copper
) {
1537 * Copper cards allow manual 10/100 mode selection,
1538 * but not manual 1000baseTX mode selection. Why?
1539 * Becuase currently there's no way to specify the
1540 * master/slave setting through the firmware interface,
1541 * so Alteon decided to just bag it and handle it
1542 * via autonegotiation.
1544 ifmedia_add(&sc
->ifmedia
, IFM_ETHER
|IFM_10_T
, 0, NULL
);
1545 ifmedia_add(&sc
->ifmedia
,
1546 IFM_ETHER
|IFM_10_T
|IFM_FDX
, 0, NULL
);
1547 ifmedia_add(&sc
->ifmedia
, IFM_ETHER
|IFM_100_TX
, 0, NULL
);
1548 ifmedia_add(&sc
->ifmedia
,
1549 IFM_ETHER
|IFM_100_TX
|IFM_FDX
, 0, NULL
);
1550 ifmedia_add(&sc
->ifmedia
, IFM_ETHER
| IFM_1000_T
, 0, NULL
);
1551 ifmedia_add(&sc
->ifmedia
,
1552 IFM_ETHER
|IFM_1000_T
| IFM_FDX
, 0, NULL
);
1554 /* Fiber cards don't support 10/100 modes. */
1555 ifmedia_add(&sc
->ifmedia
, IFM_ETHER
|IFM_1000_SX
, 0, NULL
);
1556 ifmedia_add(&sc
->ifmedia
,
1557 IFM_ETHER
|IFM_1000_SX
|IFM_FDX
, 0, NULL
);
1559 ifmedia_add(&sc
->ifmedia
, IFM_ETHER
|IFM_AUTO
, 0, NULL
);
1560 ifmedia_set(&sc
->ifmedia
, IFM_ETHER
|IFM_AUTO
);
1563 * Call MI attach routine.
1565 ether_ifattach(ifp
, eaddr
, NULL
);
1567 error
= bus_setup_intr(dev
, sc
->ti_irq
, INTR_NETSAFE
,
1568 ti_intr
, sc
, &sc
->ti_intrhand
,
1569 ifp
->if_serializer
);
1571 device_printf(dev
, "couldn't set up irq\n");
1572 ether_ifdetach(ifp
);
1583 ti_detach(device_t dev
)
1585 struct ti_softc
*sc
= device_get_softc(dev
);
1586 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1588 if (device_is_attached(dev
)) {
1589 lwkt_serialize_enter(ifp
->if_serializer
);
1591 bus_teardown_intr(dev
, sc
->ti_irq
, sc
->ti_intrhand
);
1592 lwkt_serialize_exit(ifp
->if_serializer
);
1594 ether_ifdetach(ifp
);
1597 if (sc
->ti_irq
!= NULL
)
1598 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->ti_irq
);
1599 if (sc
->ti_res
!= NULL
) {
1600 bus_release_resource(dev
, SYS_RES_MEMORY
,
1601 TI_PCI_LOMEM
, sc
->ti_res
);
1603 if (sc
->ti_cdata
.ti_jumbo_buf
!= NULL
)
1604 contigfree(sc
->ti_cdata
.ti_jumbo_buf
, TI_JMEM
, M_DEVBUF
);
1605 if (sc
->ti_rdata
!= NULL
)
1606 contigfree(sc
->ti_rdata
, sizeof(struct ti_ring_data
), M_DEVBUF
);
1607 ifmedia_removeall(&sc
->ifmedia
);
1614 * Frame reception handling. This is called if there's a frame
1615 * on the receive return list.
1617 * Note: we have to be able to handle three possibilities here:
1618 * 1) the frame is from the mini receive ring (can only happen)
1619 * on Tigon 2 boards)
1620 * 2) the frame is from the jumbo recieve ring
1621 * 3) the frame is from the standard receive ring
1624 ti_rxeof(struct ti_softc
*sc
)
1626 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1627 struct ti_cmd_desc cmd
;
1629 while(sc
->ti_rx_saved_considx
!= sc
->ti_return_prodidx
.ti_idx
) {
1630 struct ti_rx_desc
*cur_rx
;
1633 uint16_t vlan_tag
= 0;
1637 &sc
->ti_rdata
->ti_rx_return_ring
[sc
->ti_rx_saved_considx
];
1638 rxidx
= cur_rx
->ti_idx
;
1639 TI_INC(sc
->ti_rx_saved_considx
, TI_RETURN_RING_CNT
);
1641 if (cur_rx
->ti_flags
& TI_BDFLAG_VLAN_TAG
) {
1643 vlan_tag
= cur_rx
->ti_vlan_tag
& 0xfff;
1646 if (cur_rx
->ti_flags
& TI_BDFLAG_JUMBO_RING
) {
1647 TI_INC(sc
->ti_jumbo
, TI_JUMBO_RX_RING_CNT
);
1648 m
= sc
->ti_cdata
.ti_rx_jumbo_chain
[rxidx
];
1649 sc
->ti_cdata
.ti_rx_jumbo_chain
[rxidx
] = NULL
;
1650 if (cur_rx
->ti_flags
& TI_BDFLAG_ERROR
) {
1652 ti_newbuf_jumbo(sc
, sc
->ti_jumbo
, m
);
1655 if (ti_newbuf_jumbo(sc
, sc
->ti_jumbo
, NULL
) == ENOBUFS
) {
1657 ti_newbuf_jumbo(sc
, sc
->ti_jumbo
, m
);
1660 } else if (cur_rx
->ti_flags
& TI_BDFLAG_MINI_RING
) {
1661 TI_INC(sc
->ti_mini
, TI_MINI_RX_RING_CNT
);
1662 m
= sc
->ti_cdata
.ti_rx_mini_chain
[rxidx
];
1663 sc
->ti_cdata
.ti_rx_mini_chain
[rxidx
] = NULL
;
1664 if (cur_rx
->ti_flags
& TI_BDFLAG_ERROR
) {
1666 ti_newbuf_mini(sc
, sc
->ti_mini
, m
);
1669 if (ti_newbuf_mini(sc
, sc
->ti_mini
, NULL
) == ENOBUFS
) {
1671 ti_newbuf_mini(sc
, sc
->ti_mini
, m
);
1675 TI_INC(sc
->ti_std
, TI_STD_RX_RING_CNT
);
1676 m
= sc
->ti_cdata
.ti_rx_std_chain
[rxidx
];
1677 sc
->ti_cdata
.ti_rx_std_chain
[rxidx
] = NULL
;
1678 if (cur_rx
->ti_flags
& TI_BDFLAG_ERROR
) {
1680 ti_newbuf_std(sc
, sc
->ti_std
, m
);
1683 if (ti_newbuf_std(sc
, sc
->ti_std
, NULL
) == ENOBUFS
) {
1685 ti_newbuf_std(sc
, sc
->ti_std
, m
);
1690 m
->m_pkthdr
.len
= m
->m_len
= cur_rx
->ti_len
;
1692 m
->m_pkthdr
.rcvif
= ifp
;
1694 if (ifp
->if_hwassist
) {
1695 m
->m_pkthdr
.csum_flags
|= CSUM_IP_CHECKED
|
1697 if ((cur_rx
->ti_ip_cksum
^ 0xffff) == 0)
1698 m
->m_pkthdr
.csum_flags
|= CSUM_IP_VALID
;
1699 m
->m_pkthdr
.csum_data
= cur_rx
->ti_tcp_udp_cksum
;
1703 * If we received a packet with a vlan tag, pass it
1704 * to vlan_input() instead of ether_input().
1707 VLAN_INPUT_TAG(m
, vlan_tag
);
1709 ifp
->if_input(ifp
, m
);
1712 /* Only necessary on the Tigon 1. */
1713 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1714 CSR_WRITE_4(sc
, TI_GCR_RXRETURNCONS_IDX
,
1715 sc
->ti_rx_saved_considx
);
1717 TI_UPDATE_STDPROD(sc
, sc
->ti_std
);
1718 TI_UPDATE_MINIPROD(sc
, sc
->ti_mini
);
1719 TI_UPDATE_JUMBOPROD(sc
, sc
->ti_jumbo
);
1723 ti_txeof(struct ti_softc
*sc
)
1725 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1726 struct ti_tx_desc
*cur_tx
= NULL
;
1729 * Go through our tx ring and free mbufs for those
1730 * frames that have been sent.
1732 while (sc
->ti_tx_saved_considx
!= sc
->ti_tx_considx
.ti_idx
) {
1735 idx
= sc
->ti_tx_saved_considx
;
1736 if (sc
->ti_hwrev
== TI_HWREV_TIGON
) {
1738 CSR_WRITE_4(sc
, TI_WINBASE
,
1739 TI_TX_RING_BASE
+ 6144);
1741 CSR_WRITE_4(sc
, TI_WINBASE
,
1742 TI_TX_RING_BASE
+ 4096);
1744 CSR_WRITE_4(sc
, TI_WINBASE
,
1745 TI_TX_RING_BASE
+ 2048);
1747 CSR_WRITE_4(sc
, TI_WINBASE
,
1749 cur_tx
= &sc
->ti_rdata
->ti_tx_ring_nic
[idx
% 128];
1751 cur_tx
= &sc
->ti_rdata
->ti_tx_ring
[idx
];
1752 if (cur_tx
->ti_flags
& TI_BDFLAG_END
)
1754 if (sc
->ti_cdata
.ti_tx_chain
[idx
] != NULL
) {
1755 m_freem(sc
->ti_cdata
.ti_tx_chain
[idx
]);
1756 sc
->ti_cdata
.ti_tx_chain
[idx
] = NULL
;
1759 TI_INC(sc
->ti_tx_saved_considx
, TI_TX_RING_CNT
);
1764 ifp
->if_flags
&= ~IFF_OACTIVE
;
1770 struct ti_softc
*sc
= xsc
;
1771 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1774 /* Avoid this for now -- checking this register is expensive. */
1775 /* Make sure this is really our interrupt. */
1776 if ((CSR_READ_4(sc
, TI_MISC_HOST_CTL
) & TI_MHC_INTSTATE
) == 0)
1780 /* Ack interrupt and stop others from occuring. */
1781 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 1);
1783 if (ifp
->if_flags
& IFF_RUNNING
) {
1784 /* Check RX return ring producer/consumer */
1787 /* Check TX ring producer/consumer */
1791 ti_handle_events(sc
);
1793 /* Re-enable interrupts. */
1794 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 0);
1796 if ((ifp
->if_flags
& IFF_RUNNING
) && !ifq_is_empty(&ifp
->if_snd
))
1801 ti_stats_update(struct ti_softc
*sc
)
1803 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1805 ifp
->if_collisions
+=
1806 (sc
->ti_rdata
->ti_info
.ti_stats
.dot3StatsSingleCollisionFrames
+
1807 sc
->ti_rdata
->ti_info
.ti_stats
.dot3StatsMultipleCollisionFrames
+
1808 sc
->ti_rdata
->ti_info
.ti_stats
.dot3StatsExcessiveCollisions
+
1809 sc
->ti_rdata
->ti_info
.ti_stats
.dot3StatsLateCollisions
) -
1814 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1815 * pointers to descriptors.
1818 ti_encap(struct ti_softc
*sc
, struct mbuf
*m_head
, uint32_t *txidx
)
1820 struct ti_tx_desc
*f
= NULL
;
1822 struct ifvlan
*ifv
= NULL
;
1823 uint32_t cnt
= 0, cur
, frag
;
1824 uint16_t csum_flags
= 0;
1826 if ((m_head
->m_flags
& (M_PROTO1
|M_PKTHDR
)) == (M_PROTO1
|M_PKTHDR
) &&
1827 m_head
->m_pkthdr
.rcvif
!= NULL
&&
1828 m_head
->m_pkthdr
.rcvif
->if_type
== IFT_L2VLAN
)
1829 ifv
= m_head
->m_pkthdr
.rcvif
->if_softc
;
1832 cur
= frag
= *txidx
;
1834 if (m_head
->m_pkthdr
.csum_flags
) {
1835 if (m_head
->m_pkthdr
.csum_flags
& CSUM_IP
)
1836 csum_flags
|= TI_BDFLAG_IP_CKSUM
;
1837 if (m_head
->m_pkthdr
.csum_flags
& (CSUM_TCP
| CSUM_UDP
))
1838 csum_flags
|= TI_BDFLAG_TCP_UDP_CKSUM
;
1839 if (m_head
->m_flags
& M_LASTFRAG
)
1840 csum_flags
|= TI_BDFLAG_IP_FRAG_END
;
1841 else if (m_head
->m_flags
& M_FRAG
)
1842 csum_flags
|= TI_BDFLAG_IP_FRAG
;
1845 * Start packing the mbufs in this chain into
1846 * the fragment pointers. Stop when we run out
1847 * of fragments or hit the end of the mbuf chain.
1849 for (m
= m_head
; m
!= NULL
; m
= m
->m_next
) {
1850 if (m
->m_len
!= 0) {
1851 if (sc
->ti_hwrev
== TI_HWREV_TIGON
) {
1853 CSR_WRITE_4(sc
, TI_WINBASE
,
1854 TI_TX_RING_BASE
+ 6144);
1855 else if (frag
> 255)
1856 CSR_WRITE_4(sc
, TI_WINBASE
,
1857 TI_TX_RING_BASE
+ 4096);
1858 else if (frag
> 127)
1859 CSR_WRITE_4(sc
, TI_WINBASE
,
1860 TI_TX_RING_BASE
+ 2048);
1862 CSR_WRITE_4(sc
, TI_WINBASE
,
1864 f
= &sc
->ti_rdata
->ti_tx_ring_nic
[frag
% 128];
1866 f
= &sc
->ti_rdata
->ti_tx_ring
[frag
];
1867 if (sc
->ti_cdata
.ti_tx_chain
[frag
] != NULL
)
1869 TI_HOSTADDR(f
->ti_addr
) = vtophys(mtod(m
, vm_offset_t
));
1870 f
->ti_len
= m
->m_len
;
1871 f
->ti_flags
= csum_flags
;
1874 f
->ti_flags
|= TI_BDFLAG_VLAN_TAG
;
1875 f
->ti_vlan_tag
= ifv
->ifv_tag
& 0xfff;
1881 * Sanity check: avoid coming within 16 descriptors
1882 * of the end of the ring.
1884 if ((TI_TX_RING_CNT
- (sc
->ti_txcnt
+ cnt
)) < 16)
1887 TI_INC(frag
, TI_TX_RING_CNT
);
1895 if (frag
== sc
->ti_tx_saved_considx
)
1898 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
1899 sc
->ti_rdata
->ti_tx_ring_nic
[cur
% 128].ti_flags
|=
1902 sc
->ti_rdata
->ti_tx_ring
[cur
].ti_flags
|= TI_BDFLAG_END
;
1903 sc
->ti_cdata
.ti_tx_chain
[cur
] = m_head
;
1904 sc
->ti_txcnt
+= cnt
;
1912 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1913 * to the mbuf data regions directly in the transmit descriptors.
1916 ti_start(struct ifnet
*ifp
)
1918 struct ti_softc
*sc
= ifp
->if_softc
;
1919 struct mbuf
*m_head
= NULL
;
1920 uint32_t prodidx
= 0;
1923 prodidx
= CSR_READ_4(sc
, TI_MB_SENDPROD_IDX
);
1926 while(sc
->ti_cdata
.ti_tx_chain
[prodidx
] == NULL
) {
1927 m_head
= ifq_poll(&ifp
->if_snd
);
1933 * safety overkill. If this is a fragmented packet chain
1934 * with delayed TCP/UDP checksums, then only encapsulate
1935 * it if we have enough descriptors to handle the entire
1937 * (paranoia -- may not actually be needed)
1939 if (m_head
->m_flags
& M_FIRSTFRAG
&&
1940 m_head
->m_pkthdr
.csum_flags
& (CSUM_DELAY_DATA
)) {
1941 if ((TI_TX_RING_CNT
- sc
->ti_txcnt
) <
1942 m_head
->m_pkthdr
.csum_data
+ 16) {
1943 ifp
->if_flags
|= IFF_OACTIVE
;
1949 * Pack the data into the transmit ring. If we
1950 * don't have room, set the OACTIVE flag and wait
1951 * for the NIC to drain the ring.
1953 if (ti_encap(sc
, m_head
, &prodidx
)) {
1954 ifp
->if_flags
|= IFF_OACTIVE
;
1957 ifq_dequeue(&ifp
->if_snd
, m_head
);
1960 BPF_MTAP(ifp
, m_head
);
1967 CSR_WRITE_4(sc
, TI_MB_SENDPROD_IDX
, prodidx
);
1970 * Set a timeout in case the chip goes out to lunch.
1978 struct ti_softc
*sc
= xsc
;
1980 /* Cancel pending I/O and flush buffers. */
1983 /* Init the gen info block, ring control blocks and firmware. */
1984 if (ti_gibinit(sc
)) {
1985 if_printf(&sc
->arpcom
.ac_if
, "initialization failure\n");
1991 ti_init2(struct ti_softc
*sc
)
1993 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1994 struct ti_cmd_desc cmd
;
1996 struct ifmedia
*ifm
;
1999 /* Specify MTU and interface index. */
2000 CSR_WRITE_4(sc
, TI_GCR_IFINDEX
, ifp
->if_dunit
);
2001 CSR_WRITE_4(sc
, TI_GCR_IFMTU
, ifp
->if_mtu
+
2002 ETHER_HDR_LEN
+ ETHER_CRC_LEN
);
2003 TI_DO_CMD(TI_CMD_UPDATE_GENCOM
, 0, 0);
2005 /* Load our MAC address. */
2006 m
= (uint16_t *)&sc
->arpcom
.ac_enaddr
[0];
2007 CSR_WRITE_4(sc
, TI_GCR_PAR0
, htons(m
[0]));
2008 CSR_WRITE_4(sc
, TI_GCR_PAR1
, (htons(m
[1]) << 16) | htons(m
[2]));
2009 TI_DO_CMD(TI_CMD_SET_MAC_ADDR
, 0, 0);
2011 /* Enable or disable promiscuous mode as needed. */
2012 if (ifp
->if_flags
& IFF_PROMISC
)
2013 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE
, TI_CMD_CODE_PROMISC_ENB
, 0);
2015 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE
, TI_CMD_CODE_PROMISC_DIS
, 0);
2017 /* Program multicast filter. */
2021 * If this is a Tigon 1, we should tell the
2022 * firmware to use software packet filtering.
2024 if (sc
->ti_hwrev
== TI_HWREV_TIGON
)
2025 TI_DO_CMD(TI_CMD_FDR_FILTERING
, TI_CMD_CODE_FILT_ENB
, 0);
2028 ti_init_rx_ring_std(sc
);
2030 /* Init jumbo RX ring. */
2031 if (ifp
->if_mtu
> (ETHERMTU
+ ETHER_HDR_LEN
+ ETHER_CRC_LEN
))
2032 ti_init_rx_ring_jumbo(sc
);
2035 * If this is a Tigon 2, we can also configure the
2038 if (sc
->ti_hwrev
== TI_HWREV_TIGON_II
)
2039 ti_init_rx_ring_mini(sc
);
2041 CSR_WRITE_4(sc
, TI_GCR_RXRETURNCONS_IDX
, 0);
2042 sc
->ti_rx_saved_considx
= 0;
2045 ti_init_tx_ring(sc
);
2047 /* Tell firmware we're alive. */
2048 TI_DO_CMD(TI_CMD_HOST_STATE
, TI_CMD_CODE_STACK_UP
, 0);
2050 /* Enable host interrupts. */
2051 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 0);
2053 ifp
->if_flags
|= IFF_RUNNING
;
2054 ifp
->if_flags
&= ~IFF_OACTIVE
;
2057 * Make sure to set media properly. We have to do this
2058 * here since we have to issue commands in order to set
2059 * the link negotiation and we can't issue commands until
2060 * the firmware is running.
2063 tmp
= ifm
->ifm_media
;
2064 ifm
->ifm_media
= ifm
->ifm_cur
->ifm_media
;
2065 ti_ifmedia_upd(ifp
);
2066 ifm
->ifm_media
= tmp
;
2070 * Set media options.
2073 ti_ifmedia_upd(struct ifnet
*ifp
)
2075 struct ti_softc
*sc
= ifp
->if_softc
;
2076 struct ifmedia
*ifm
= &sc
->ifmedia
;
2077 struct ti_cmd_desc cmd
;
2079 if (IFM_TYPE(ifm
->ifm_media
) != IFM_ETHER
)
2082 switch(IFM_SUBTYPE(ifm
->ifm_media
)) {
2084 CSR_WRITE_4(sc
, TI_GCR_GLINK
, TI_GLNK_PREF
| TI_GLNK_1000MB
|
2085 TI_GLNK_FULL_DUPLEX
| TI_GLNK_RX_FLOWCTL_Y
|
2086 TI_GLNK_AUTONEGENB
| TI_GLNK_ENB
);
2087 CSR_WRITE_4(sc
, TI_GCR_LINK
, TI_LNK_100MB
| TI_LNK_10MB
|
2088 TI_LNK_FULL_DUPLEX
| TI_LNK_HALF_DUPLEX
|
2089 TI_LNK_AUTONEGENB
| TI_LNK_ENB
);
2090 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION
,
2091 TI_CMD_CODE_NEGOTIATE_BOTH
, 0);
2095 CSR_WRITE_4(sc
, TI_GCR_GLINK
, TI_GLNK_PREF
|TI_GLNK_1000MB
|
2096 TI_GLNK_RX_FLOWCTL_Y
| TI_GLNK_ENB
);
2097 CSR_WRITE_4(sc
, TI_GCR_LINK
, 0);
2098 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
2099 TI_SETBIT(sc
, TI_GCR_GLINK
, TI_GLNK_FULL_DUPLEX
);
2100 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION
,
2101 TI_CMD_CODE_NEGOTIATE_GIGABIT
, 0);
2107 CSR_WRITE_4(sc
, TI_GCR_GLINK
, 0);
2108 CSR_WRITE_4(sc
, TI_GCR_LINK
, TI_LNK_ENB
| TI_LNK_PREF
);
2109 if (IFM_SUBTYPE(ifm
->ifm_media
) == IFM_100_FX
||
2110 IFM_SUBTYPE(ifm
->ifm_media
) == IFM_100_TX
)
2111 TI_SETBIT(sc
, TI_GCR_LINK
, TI_LNK_100MB
);
2113 TI_SETBIT(sc
, TI_GCR_LINK
, TI_LNK_10MB
);
2114 if ((ifm
->ifm_media
& IFM_GMASK
) == IFM_FDX
)
2115 TI_SETBIT(sc
, TI_GCR_LINK
, TI_LNK_FULL_DUPLEX
);
2117 TI_SETBIT(sc
, TI_GCR_LINK
, TI_LNK_HALF_DUPLEX
);
2118 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION
,
2119 TI_CMD_CODE_NEGOTIATE_10_100
, 0);
2127 * Report current media status.
2130 ti_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
2132 struct ti_softc
*sc
= ifp
->if_softc
;
2135 ifmr
->ifm_status
= IFM_AVALID
;
2136 ifmr
->ifm_active
= IFM_ETHER
;
2138 if (sc
->ti_linkstat
== TI_EV_CODE_LINK_DOWN
)
2141 ifmr
->ifm_status
|= IFM_ACTIVE
;
2143 if (sc
->ti_linkstat
== TI_EV_CODE_GIG_LINK_UP
) {
2144 media
= CSR_READ_4(sc
, TI_GCR_GLINK_STAT
);
2146 ifmr
->ifm_active
|= IFM_1000_T
;
2148 ifmr
->ifm_active
|= IFM_1000_SX
;
2149 if (media
& TI_GLNK_FULL_DUPLEX
)
2150 ifmr
->ifm_active
|= IFM_FDX
;
2152 ifmr
->ifm_active
|= IFM_HDX
;
2153 } else if (sc
->ti_linkstat
== TI_EV_CODE_LINK_UP
) {
2154 media
= CSR_READ_4(sc
, TI_GCR_LINK_STAT
);
2155 if (sc
->ti_copper
) {
2156 if (media
& TI_LNK_100MB
)
2157 ifmr
->ifm_active
|= IFM_100_TX
;
2158 if (media
& TI_LNK_10MB
)
2159 ifmr
->ifm_active
|= IFM_10_T
;
2161 if (media
& TI_LNK_100MB
)
2162 ifmr
->ifm_active
|= IFM_100_FX
;
2163 if (media
& TI_LNK_10MB
)
2164 ifmr
->ifm_active
|= IFM_10_FL
;
2166 if (media
& TI_LNK_FULL_DUPLEX
)
2167 ifmr
->ifm_active
|= IFM_FDX
;
2168 if (media
& TI_LNK_HALF_DUPLEX
)
2169 ifmr
->ifm_active
|= IFM_HDX
;
2174 ti_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
2176 struct ti_softc
*sc
= ifp
->if_softc
;
2177 struct ifreq
*ifr
= (struct ifreq
*) data
;
2178 struct ti_cmd_desc cmd
;
2179 int error
= 0, mask
;
2183 if (ifr
->ifr_mtu
> TI_JUMBO_MTU
)
2186 ifp
->if_mtu
= ifr
->ifr_mtu
;
2191 if (ifp
->if_flags
& IFF_UP
) {
2193 * If only the state of the PROMISC flag changed,
2194 * then just use the 'set promisc mode' command
2195 * instead of reinitializing the entire NIC. Doing
2196 * a full re-init means reloading the firmware and
2197 * waiting for it to start up, which may take a
2200 if (ifp
->if_flags
& IFF_RUNNING
&&
2201 ifp
->if_flags
& IFF_PROMISC
&&
2202 !(sc
->ti_if_flags
& IFF_PROMISC
)) {
2203 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE
,
2204 TI_CMD_CODE_PROMISC_ENB
, 0);
2205 } else if (ifp
->if_flags
& IFF_RUNNING
&&
2206 !(ifp
->if_flags
& IFF_PROMISC
) &&
2207 sc
->ti_if_flags
& IFF_PROMISC
) {
2208 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE
,
2209 TI_CMD_CODE_PROMISC_DIS
, 0);
2212 } else if (ifp
->if_flags
& IFF_RUNNING
) {
2215 sc
->ti_if_flags
= ifp
->if_flags
;
2220 if (ifp
->if_flags
& IFF_RUNNING
) {
2227 error
= ifmedia_ioctl(ifp
, ifr
, &sc
->ifmedia
, command
);
2230 mask
= ifr
->ifr_reqcap
^ ifp
->if_capenable
;
2231 if (mask
& IFCAP_HWCSUM
) {
2232 if (IFCAP_HWCSUM
& ifp
->if_capenable
)
2233 ifp
->if_capenable
&= ~IFCAP_HWCSUM
;
2235 ifp
->if_capenable
|= IFCAP_HWCSUM
;
2236 if (ifp
->if_flags
& IFF_RUNNING
)
2242 error
= ether_ioctl(ifp
, command
, data
);
2249 ti_watchdog(struct ifnet
*ifp
)
2251 struct ti_softc
*sc
= ifp
->if_softc
;
2253 if_printf(ifp
, "watchdog timeout -- resetting\n");
2259 if (!ifq_is_empty(&ifp
->if_snd
))
2264 * Stop the adapter and free any mbufs allocated to the
2268 ti_stop(struct ti_softc
*sc
)
2270 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
2271 struct ti_cmd_desc cmd
;
2273 /* Disable host interrupts. */
2274 CSR_WRITE_4(sc
, TI_MB_HOSTINTR
, 1);
2276 * Tell firmware we're shutting down.
2278 TI_DO_CMD(TI_CMD_HOST_STATE
, TI_CMD_CODE_STACK_DOWN
, 0);
2280 /* Halt and reinitialize. */
2282 ti_mem(sc
, 0x2000, 0x100000 - 0x2000, NULL
);
2285 /* Free the RX lists. */
2286 ti_free_rx_ring_std(sc
);
2288 /* Free jumbo RX list. */
2289 ti_free_rx_ring_jumbo(sc
);
2291 /* Free mini RX list. */
2292 ti_free_rx_ring_mini(sc
);
2294 /* Free TX buffers. */
2295 ti_free_tx_ring(sc
);
2297 sc
->ti_ev_prodidx
.ti_idx
= 0;
2298 sc
->ti_return_prodidx
.ti_idx
= 0;
2299 sc
->ti_tx_considx
.ti_idx
= 0;
2300 sc
->ti_tx_saved_considx
= TI_TXCONS_UNSET
;
2302 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
2306 * Stop all chip I/O so that the kernel's probe routines don't
2307 * get confused by errant DMAs when rebooting.
2310 ti_shutdown(device_t dev
)
2312 struct ti_softc
*sc
= device_get_softc(dev
);