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- Fix headphone jack sensing support for Olivetti Olibook 610-430 XPSE.
[dragonfly/vkernel-mp.git] / sys / dev / sound / pci / hda / hdac.c
blobdae054b7966b10b98107d90653b3986196af47bb
1 /*-
2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/sound/pci/hda/hdac.c,v 1.36.2.3 2007/06/21 20:58:44 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.5 2007/06/26 11:04:50 hasso Exp $
29 */
30
31 /*
32 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
33 * that this driver still in its early stage, and possible of rewrite are
34 * pretty much guaranteed. There are supposedly several distinct parent/child
35 * busses to make this "perfect", but as for now and for the sake of
36 * simplicity, everything is gobble up within single source.
37 *
38 * List of subsys:
39 * 1) HDA Controller support
40 * 2) HDA Codecs support, which may include
41 * - HDA
42 * - Modem
43 * - HDMI
44 * 3) Widget parser - the real magic of why this driver works on so
45 * many hardwares with minimal vendor specific quirk. The original
46 * parser was written using Ruby and can be found at
47 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
48 * ruby parser take the verbose dmesg dump as its input. Refer to
49 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
50 * interesting documents, especially UAA (Universal Audio Architecture).
51 * 4) Possible vendor specific support.
52 * (snd_hda_intel, snd_hda_ati, etc..)
53 *
54 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
55 * Compaq V3000 with Conexant HDA.
56 *
57 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
58 * * *
59 * * This driver is a collaborative effort made by: *
60 * * *
61 * * Stephane E. Potvin <sepotvin@videotron.ca> *
62 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
63 * * Wesley Morgan <morganw@chemikals.org> *
64 * * Daniel Eischen <deischen@FreeBSD.org> *
65 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
66 * * Ariff Abdullah <ariff@FreeBSD.org> *
67 * * *
68 * * ....and various people from freebsd-multimedia@FreeBSD.org *
69 * * *
70 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 */
72
73 #include <sys/ctype.h>
74
75 #include <dev/sound/pcm/sound.h>
76 #include <bus/pci/pcireg.h>
77 #include <bus/pci/pcivar.h>
78
79 #include <dev/sound/pci/hda/hdac_private.h>
80 #include <dev/sound/pci/hda/hdac_reg.h>
81 #include <dev/sound/pci/hda/hda_reg.h>
82 #include <dev/sound/pci/hda/hdac.h>
83
84 #include "mixer_if.h"
85
86 #define HDA_DRV_TEST_REV "20070619_0045"
87 #define HDA_WIDGET_PARSER_REV 1
88
89 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/hda/hdac.c,v 1.5 2007/06/26 11:04:50 hasso Exp $");
90
91 #define HDA_BOOTVERBOSE(stmt) do { \
92 if (bootverbose != 0) { \
93 stmt \
94 } \
95 } while(0)
96
97 #if 1
98 #undef HDAC_INTR_EXTRA
99 #define HDAC_INTR_EXTRA 1
100 #endif
101
102 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
103 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
104 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
105 #define hdac_lockowned(sc) (1)/* mtx_owned((sc)->lock) */
106
107 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
108 #include <machine/specialreg.h>
109 #define HDAC_DMA_ATTR(sc, v, s, attr) do { \
110 vm_offset_t va = (vm_offset_t)(v); \
111 vm_size_t sz = (vm_size_t)(s); \
112 if ((sc) != NULL && (sc)->nocache != 0 && va != 0 && sz != 0) \
113 (void)pmap_change_attr(va, sz, (attr)); \
114 } while(0)
115 #else
116 #define HDAC_DMA_ATTR(...)
117 #endif
118
119 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
120 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
121 (fl) == 0xffffffff || \
122 (((fl) & 0xffff0000) == 0xffff0000 && \
123 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
124 (((fl) & 0x0000ffff) == 0x0000ffff && \
125 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
126 #define HDA_MATCH_ALL 0xffffffff
127 #define HDAC_INVALID 0xffffffff
128
129 /* Default controller / jack sense poll: 250ms */
130 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
131
132 #define HDA_MODEL_CONSTRUCT(vendor, model) \
133 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
134
135 /* Controller models */
136
137 /* Intel */
138 #define INTEL_VENDORID 0x8086
139 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
140 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
141 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
142 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
143 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
144
145 /* Nvidia */
146 #define NVIDIA_VENDORID 0x10de
147 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
148 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
149 #define HDA_NVIDIA_MCP61A HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
150 #define HDA_NVIDIA_MCP61B HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
151 #define HDA_NVIDIA_MCP65A HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
152 #define HDA_NVIDIA_MCP65B HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
153 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
154
155 /* ATI */
156 #define ATI_VENDORID 0x1002
157 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
158 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
159 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
160
161 /* VIA */
162 #define VIA_VENDORID 0x1106
163 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
164 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
165
166 /* SiS */
167 #define SIS_VENDORID 0x1039
168 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
169 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
170
171 /* OEM/subvendors */
172
173 /* Intel */
174 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
175
176 /* HP/Compaq */
177 #define HP_VENDORID 0x103c
178 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
179 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
180 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
181 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
182 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
183 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
184 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
185 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
186 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
187 #define HP_NX6325_SUBVENDORX 0x103c30b0
188
189 /* Dell */
190 #define DELL_VENDORID 0x1028
191 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
192 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
193 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
194 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
195 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
196
197 /* Clevo */
198 #define CLEVO_VENDORID 0x1558
199 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
200 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
201
202 /* Acer */
203 #define ACER_VENDORID 0x1025
204 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
205 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
206 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
207
208 /* Asus */
209 #define ASUS_VENDORID 0x1043
210 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
211 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
212 #define ASUS_A8JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
213 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
214 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
215 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
216 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
217 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
218 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
219 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
220 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
221 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
222 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
223 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
224
225 /* IBM / Lenovo */
226 #define IBM_VENDORID 0x1014
227 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
228 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
229
230 /* Lenovo */
231 #define LENOVO_VENDORID 0x17aa
232 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
233 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
234
235 /* Samsung */
236 #define SAMSUNG_VENDORID 0x144d
237 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
238 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
239
240 /* Medion ? */
241 #define MEDION_VENDORID 0x161f
242 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
243 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
244
245 /*
246 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
247 * instead of their own, which is beyond my comprehension
248 * (see HDA_CODEC_STAC9221 below).
249 */
250 #define APPLE_INTEL_MAC 0x76808384
251
252 /* LG Electronics */
253 #define LG_VENDORID 0x1854
254 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
255 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
256
257 /* Fujitsu Siemens */
258 #define FS_VENDORID 0x1734
259 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
260 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
261
262 /* Toshiba */
263 #define TOSHIBA_VENDORID 0x1179
264 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
265 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
266
267 /* Micro-Star International (MSI) */
268 #define MSI_VENDORID 0x1462
269 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
270 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
271
272 /* Uniwill ? */
273 #define UNIWILL_VENDORID 0x1584
274 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
275 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
276
277
278 /* Misc constants.. */
279 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
280 #define HDA_AMP_MUTE_NONE (0)
281 #define HDA_AMP_MUTE_LEFT (1 << 0)
282 #define HDA_AMP_MUTE_RIGHT (1 << 1)
283 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
284
285 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
286 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
287
288 #define HDA_DAC_PATH (1 << 0)
289 #define HDA_ADC_PATH (1 << 1)
290 #define HDA_ADC_RECSEL (1 << 2)
291
292 #define HDA_DAC_LOCKED (1 << 3)
293 #define HDA_ADC_LOCKED (1 << 4)
294
295 #define HDA_CTL_OUT (1 << 0)
296 #define HDA_CTL_IN (1 << 1)
297 #define HDA_CTL_BOTH (HDA_CTL_IN | HDA_CTL_OUT)
298
299 #define HDA_GPIO_MAX 8
300 /* 0 - 7 = GPIO , 8 = Flush */
301 #define HDA_QUIRK_GPIO0 (1 << 0)
302 #define HDA_QUIRK_GPIO1 (1 << 1)
303 #define HDA_QUIRK_GPIO2 (1 << 2)
304 #define HDA_QUIRK_GPIO3 (1 << 3)
305 #define HDA_QUIRK_GPIO4 (1 << 4)
306 #define HDA_QUIRK_GPIO5 (1 << 5)
307 #define HDA_QUIRK_GPIO6 (1 << 6)
308 #define HDA_QUIRK_GPIO7 (1 << 7)
309 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
310
311 /* 9 - 25 = anything else */
312 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
313 #define HDA_QUIRK_FIXEDRATE (1 << 10)
314 #define HDA_QUIRK_FORCESTEREO (1 << 11)
315 #define HDA_QUIRK_EAPDINV (1 << 12)
316 #define HDA_QUIRK_DMAPOS (1 << 13)
317
318 /* 26 - 31 = vrefs */
319 #define HDA_QUIRK_IVREF50 (1 << 26)
320 #define HDA_QUIRK_IVREF80 (1 << 27)
321 #define HDA_QUIRK_IVREF100 (1 << 28)
322 #define HDA_QUIRK_OVREF50 (1 << 29)
323 #define HDA_QUIRK_OVREF80 (1 << 30)
324 #define HDA_QUIRK_OVREF100 (1 << 31)
325
326 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
327 HDA_QUIRK_IVREF100)
328 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
329 HDA_QUIRK_OVREF100)
330 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
331
332 #define SOUND_MASK_SKIP (1 << 30)
333 #define SOUND_MASK_DISABLE (1 << 31)
334
335 static const struct {
336 char *key;
337 uint32_t value;
338 } hdac_quirks_tab[] = {
339 { "gpio0", HDA_QUIRK_GPIO0 },
340 { "gpio1", HDA_QUIRK_GPIO1 },
341 { "gpio2", HDA_QUIRK_GPIO2 },
342 { "gpio3", HDA_QUIRK_GPIO3 },
343 { "gpio4", HDA_QUIRK_GPIO4 },
344 { "gpio5", HDA_QUIRK_GPIO5 },
345 { "gpio6", HDA_QUIRK_GPIO6 },
346 { "gpio7", HDA_QUIRK_GPIO7 },
347 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
348 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
349 { "fixedrate", HDA_QUIRK_FIXEDRATE },
350 { "forcestereo", HDA_QUIRK_FORCESTEREO },
351 { "eapdinv", HDA_QUIRK_EAPDINV },
352 { "dmapos", HDA_QUIRK_DMAPOS },
353 { "ivref50", HDA_QUIRK_IVREF50 },
354 { "ivref80", HDA_QUIRK_IVREF80 },
355 { "ivref100", HDA_QUIRK_IVREF100 },
356 { "ovref50", HDA_QUIRK_OVREF50 },
357 { "ovref80", HDA_QUIRK_OVREF80 },
358 { "ovref100", HDA_QUIRK_OVREF100 },
359 { "ivref", HDA_QUIRK_IVREF },
360 { "ovref", HDA_QUIRK_OVREF },
361 { "vref", HDA_QUIRK_VREF },
362 };
363 #define HDAC_QUIRKS_TAB_LEN \
364 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
365
366 #define HDA_BDL_MIN 2
367 #define HDA_BDL_MAX 256
368 #define HDA_BDL_DEFAULT HDA_BDL_MIN
369
370 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
371 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
372
373 #define HDA_BUFSZ_MIN 4096
374 #define HDA_BUFSZ_MAX 65536
375 #define HDA_BUFSZ_DEFAULT 16384
376
377 #define HDA_PARSE_MAXDEPTH 10
378
379 #define HDAC_UNSOLTAG_EVENT_HP 0x00
380 #define HDAC_UNSOLTAG_EVENT_TEST 0x01
381
382 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
383
384 enum {
385 HDA_PARSE_MIXER,
386 HDA_PARSE_DIRECT
387 };
388
389 /* Default */
390 static uint32_t hdac_fmt[] = {
391 AFMT_STEREO | AFMT_S16_LE,
392 0
393 };
394
395 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
396
397 static const struct {
398 uint32_t model;
399 char *desc;
400 } hdac_devices[] = {
401 { HDA_INTEL_82801F, "Intel 82801F" },
402 { HDA_INTEL_82801G, "Intel 82801G" },
403 { HDA_INTEL_82801H, "Intel 82801H" },
404 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" },
405 { HDA_NVIDIA_MCP51, "NVidia MCP51" },
406 { HDA_NVIDIA_MCP55, "NVidia MCP55" },
407 { HDA_NVIDIA_MCP61A, "NVidia MCP61A" },
408 { HDA_NVIDIA_MCP61B, "NVidia MCP61B" },
409 { HDA_NVIDIA_MCP65A, "NVidia MCP65A" },
410 { HDA_NVIDIA_MCP65B, "NVidia MCP65B" },
411 { HDA_ATI_SB450, "ATI SB450" },
412 { HDA_ATI_SB600, "ATI SB600" },
413 { HDA_VIA_VT82XX, "VIA VT8251/8237A" },
414 { HDA_SIS_966, "SiS 966" },
415 /* Unknown */
416 { HDA_INTEL_ALL, "Intel (Unknown)" },
417 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
418 { HDA_ATI_ALL, "ATI (Unknown)" },
419 { HDA_VIA_ALL, "VIA (Unknown)" },
420 { HDA_SIS_ALL, "SiS (Unknown)" },
421 };
422 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
423
424 static const struct {
425 uint16_t vendor;
426 uint8_t reg;
427 uint8_t mask;
428 uint8_t enable;
429 } hdac_pcie_snoop[] = {
430 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
431 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
432 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
433 };
434 #define HDAC_PCIESNOOP_LEN \
435 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
436
437 static const struct {
438 uint32_t rate;
439 int valid;
440 uint16_t base;
441 uint16_t mul;
442 uint16_t div;
443 } hda_rate_tab[] = {
444 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
445 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
446 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
447 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
448 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
449 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
450 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
451 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
452 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
453 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
454 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
455 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
456 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
457 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
458 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
459 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
460 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
461 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
462 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
463 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
464 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
465 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
466 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
467 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
468 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
469 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
470 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
471 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
472 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
473 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
474 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
475 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
476 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
477 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
478 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
479 };
480 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
481
482 /* All codecs you can eat... */
483 #define HDA_CODEC_CONSTRUCT(vendor, id) \
484 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
485
486 /* Realtek */
487 #define REALTEK_VENDORID 0x10ec
488 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
489 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
490 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
491 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
492 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
493 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
494 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
495 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
496 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
497 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
498 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
499
500 /* Analog Devices */
501 #define ANALOGDEVICES_VENDORID 0x11d4
502 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
503 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
504 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
505 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
506 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
507 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
508
509 /* CMedia */
510 #define CMEDIA_VENDORID 0x434d
511 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
512 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
513
514 /* Sigmatel */
515 #define SIGMATEL_VENDORID 0x8384
516 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
517 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
518 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
519 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
520 #define HDA_CODEC_STAC9227 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
521 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
522 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
523
524 /*
525 * Conexant
526 *
527 * Ok, the truth is, I don't have any idea at all whether
528 * it is "Venice" or "Waikiki" or other unnamed CXyadayada. The only
529 * place that tell me it is "Venice" is from its Windows driver INF.
530 *
531 * Venice - CX?????
532 * Waikiki - CX20551-22
533 */
534 #define CONEXANT_VENDORID 0x14f1
535 #define HDA_CODEC_CXVENICE HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
536 #define HDA_CODEC_CXWAIKIKI HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
537 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
538
539 /* VIA */
540 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
541 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
542 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
543 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
544 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
545 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
546 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
547 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
548 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
549 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
550 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
551 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
552 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
553
554
555 /* Codecs */
556 static const struct {
557 uint32_t id;
558 char *name;
559 } hdac_codecs[] = {
560 { HDA_CODEC_ALC260, "Realtek ALC260" },
561 { HDA_CODEC_ALC262, "Realtek ALC262" },
562 { HDA_CODEC_ALC660, "Realtek ALC660" },
563 { HDA_CODEC_ALC861, "Realtek ALC861" },
564 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
565 { HDA_CODEC_ALC880, "Realtek ALC880" },
566 { HDA_CODEC_ALC882, "Realtek ALC882" },
567 { HDA_CODEC_ALC883, "Realtek ALC883" },
568 { HDA_CODEC_ALC885, "Realtek ALC885" },
569 { HDA_CODEC_ALC888, "Realtek ALC888" },
570 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
571 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
572 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
573 { HDA_CODEC_AD1988, "Analog Devices AD1988" },
574 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
575 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
576 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
577 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
578 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
579 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
580 { HDA_CODEC_STAC9227, "Sigmatel STAC9227" },
581 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
582 { HDA_CODEC_CXVENICE, "Conexant Venice" },
583 { HDA_CODEC_CXWAIKIKI, "Conexant Waikiki" },
584 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
585 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
586 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
587 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
588 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
589 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
590 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
591 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
592 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
593 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
594 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
595 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
596 /* Unknown codec */
597 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
598 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
599 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
600 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
601 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
602 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
603 };
604 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
605
606 enum {
607 HDAC_HP_SWITCH_CTL,
608 HDAC_HP_SWITCH_CTRL,
609 HDAC_HP_SWITCH_DEBUG
610 };
611
612 static const struct {
613 uint32_t model;
614 uint32_t id;
615 int type;
616 int inverted;
617 int polling;
618 int execsense;
619 nid_t hpnid;
620 nid_t spkrnid[8];
621 nid_t eapdnid;
622 } hdac_hp_switch[] = {
623 /* Specific OEM models */
624 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
625 0, 0, -1, 17, { 16, -1 }, 16 },
626 /* { HP_XW4300_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_CTL,
627 0, 0, -1, 21, { 16, 17, -1 }, -1 } */
628 /*{ HP_3010_SUBVENDOR, HDA_CODEC_ALC260, HDAC_HP_SWITCH_DEBUG,
629 0, 1, 0, 16, { 15, 18, 19, 20, 21, -1 }, -1 },*/
630 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
631 0, 0, -1, 6, { 5, -1 }, 5 },
632 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
633 0, 0, -1, 6, { 5, -1 }, 5 },
634 { HP_NX6325_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
635 0, 0, -1, 6, { 5, -1 }, 5 },
636 { TOSHIBA_U200_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
637 0, 0, -1, 6, { 5, -1 }, -1 },
638 { DELL_D820_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
639 0, 0, -1, 13, { 14, -1 }, -1 },
640 { DELL_I1300_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
641 0, 0, -1, 13, { 14, -1 }, -1 },
642 { DELL_OPLX745_SUBVENDOR, HDA_CODEC_AD1983, HDAC_HP_SWITCH_CTL,
643 0, 0, -1, 6, { 5, 7, -1 }, -1 },
644 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, HDAC_HP_SWITCH_CTRL,
645 0, 0, -1, 10, { 13, -1 }, -1 },
646 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
647 1, 0, -1, 26, { 27, -1 }, -1 },
648 { LG_LW20_SUBVENDOR, HDA_CODEC_ALC880, HDAC_HP_SWITCH_CTL,
649 0, 0, -1, 27, { 20, -1 }, -1 },
650 { ACER_A5050_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
651 0, 0, -1, 20, { 21, -1 }, -1 },
652 { ACER_3681WXM_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
653 0, 0, -1, 20, { 21, -1 }, -1 },
654 { UNIWILL_9080_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
655 0, 0, -1, 20, { 21, -1 }, -1 },
656 { MSI_MS1034_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
657 0, 0, -1, 20, { 27, -1 }, -1 },
658 /*
659 * All models that at least come from the same vendor with
660 * simmilar codec.
661 */
662 { HP_ALL_SUBVENDOR, HDA_CODEC_CXVENICE, HDAC_HP_SWITCH_CTL,
663 0, 0, -1, 17, { 16, -1 }, 16 },
664 { HP_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
665 0, 0, -1, 6, { 5, -1 }, 5 },
666 { TOSHIBA_ALL_SUBVENDOR, HDA_CODEC_AD1981HD, HDAC_HP_SWITCH_CTL,
667 0, 0, -1, 6, { 5, -1 }, -1 },
668 { DELL_ALL_SUBVENDOR, HDA_CODEC_STAC9220, HDAC_HP_SWITCH_CTRL,
669 0, 0, -1, 13, { 14, -1 }, -1 },
670 { LENOVO_ALL_SUBVENDOR, HDA_CODEC_AD1986A, HDAC_HP_SWITCH_CTL,
671 1, 0, -1, 26, { 27, -1 }, -1 },
672 #if 0
673 { ACER_ALL_SUBVENDOR, HDA_CODEC_ALC883, HDAC_HP_SWITCH_CTL,
674 0, 0, -1, 20, { 21, -1 }, -1 },
675 #endif
676 };
677 #define HDAC_HP_SWITCH_LEN \
678 (sizeof(hdac_hp_switch) / sizeof(hdac_hp_switch[0]))
679
680 static const struct {
681 uint32_t model;
682 uint32_t id;
683 nid_t eapdnid;
684 int hp_switch;
685 } hdac_eapd_switch[] = {
686 { HP_V3000_SUBVENDOR, HDA_CODEC_CXVENICE, 16, 1 },
687 { HP_NX7400_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
688 { HP_NX6310_SUBVENDOR, HDA_CODEC_AD1981HD, 5, 1 },
689 };
690 #define HDAC_EAPD_SWITCH_LEN \
691 (sizeof(hdac_eapd_switch) / sizeof(hdac_eapd_switch[0]))
692
693 /****************************************************************************
694 * Function prototypes
695 ****************************************************************************/
696 static void hdac_intr_handler(void *);
697 static int hdac_reset(struct hdac_softc *);
698 static int hdac_get_capabilities(struct hdac_softc *);
699 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
700 static int hdac_dma_alloc(struct hdac_softc *,
701 struct hdac_dma *, bus_size_t);
702 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
703 static int hdac_mem_alloc(struct hdac_softc *);
704 static void hdac_mem_free(struct hdac_softc *);
705 static int hdac_irq_alloc(struct hdac_softc *);
706 static void hdac_irq_free(struct hdac_softc *);
707 static void hdac_corb_init(struct hdac_softc *);
708 static void hdac_rirb_init(struct hdac_softc *);
709 static void hdac_corb_start(struct hdac_softc *);
710 static void hdac_rirb_start(struct hdac_softc *);
711 static void hdac_scan_codecs(struct hdac_softc *);
712 static int hdac_probe_codec(struct hdac_codec *);
713 static struct hdac_devinfo *hdac_probe_function(struct hdac_codec *, nid_t);
714 static void hdac_add_child(struct hdac_softc *, struct hdac_devinfo *);
715
716 static void hdac_attach2(void *);
717
718 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
719 uint32_t, int);
720 static void hdac_command_send_internal(struct hdac_softc *,
721 struct hdac_command_list *, int);
722
723 static int hdac_probe(device_t);
724 static int hdac_attach(device_t);
725 static int hdac_detach(device_t);
726 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
727 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
728 uint32_t, int, int);
729 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
730 nid_t, int, int);
731 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
732 nid_t, nid_t, int, int, int, int, int, int);
733 static int hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *);
734 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
735
736 static int hdac_rirb_flush(struct hdac_softc *sc);
737 static int hdac_unsolq_flush(struct hdac_softc *sc);
738
739 #define hdac_command(a1, a2, a3) \
740 hdac_command_sendone_internal(a1, a2, a3)
741
742 #define hdac_codec_id(d) \
743 ((uint32_t)((d == NULL) ? 0x00000000 : \
744 ((((uint32_t)(d)->vendor_id & 0x0000ffff) << 16) | \
745 ((uint32_t)(d)->device_id & 0x0000ffff))))
746
747 static char *
748 hdac_codec_name(struct hdac_devinfo *devinfo)
749 {
750 uint32_t id;
751 int i;
752
753 id = hdac_codec_id(devinfo);
754
755 for (i = 0; i < HDAC_CODECS_LEN; i++) {
756 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
757 return (hdac_codecs[i].name);
758 }
759
760 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
761 }
762
763 static char *
764 hdac_audio_ctl_ossmixer_mask2name(uint32_t devmask)
765 {
766 static char *ossname[] = SOUND_DEVICE_NAMES;
767 static char *unknown = "???";
768 int i;
769
770 for (i = SOUND_MIXER_NRDEVICES - 1; i >= 0; i--) {
771 if (devmask & (1 << i))
772 return (ossname[i]);
773 }
774 return (unknown);
775 }
776
777 static void
778 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
779 {
780 static char *ossname[] = SOUND_DEVICE_NAMES;
781 int i, first = 1;
782
783 bzero(buf, len);
784 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
785 if (mask & (1 << i)) {
786 if (first == 0)
787 strlcat(buf, ", ", len);
788 strlcat(buf, ossname[i], len);
789 first = 0;
790 }
791 }
792 }
793
794 static struct hdac_audio_ctl *
795 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
796 {
797 if (devinfo == NULL ||
798 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
799 index == NULL || devinfo->function.audio.ctl == NULL ||
800 devinfo->function.audio.ctlcnt < 1 ||
801 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
802 return (NULL);
803 return (&devinfo->function.audio.ctl[(*index)++]);
804 }
805
806 static struct hdac_audio_ctl *
807 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid,
808 int index, int cnt)
809 {
810 struct hdac_audio_ctl *ctl, *retctl = NULL;
811 int i, at, atindex, found = 0;
812
813 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
814 return (NULL);
815
816 at = cnt;
817 if (at == 0)
818 at = 1;
819 else if (at < 0)
820 at = -1;
821 atindex = index;
822 if (atindex < 0)
823 atindex = -1;
824
825 i = 0;
826 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
827 if (ctl->enable == 0 || ctl->widget == NULL)
828 continue;
829 if (!(ctl->widget->nid == nid && (atindex == -1 ||
830 ctl->index == atindex)))
831 continue;
832 found++;
833 if (found == cnt)
834 return (ctl);
835 retctl = ctl;
836 }
837
838 return ((at == -1) ? retctl : NULL);
839 }
840
841 static void
842 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
843 {
844 struct hdac_softc *sc;
845 struct hdac_widget *w;
846 struct hdac_audio_ctl *ctl;
847 uint32_t val, id, res;
848 int i = 0, j, forcemute;
849 nid_t cad;
850
851 if (devinfo == NULL || devinfo->codec == NULL ||
852 devinfo->codec->sc == NULL)
853 return;
854
855 sc = devinfo->codec->sc;
856 cad = devinfo->codec->cad;
857 id = hdac_codec_id(devinfo);
858 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
859 if (HDA_DEV_MATCH(hdac_hp_switch[i].model,
860 sc->pci_subvendor) &&
861 hdac_hp_switch[i].id == id)
862 break;
863 }
864
865 if (i >= HDAC_HP_SWITCH_LEN)
866 return;
867
868 forcemute = 0;
869 if (hdac_hp_switch[i].eapdnid != -1) {
870 w = hdac_widget_get(devinfo, hdac_hp_switch[i].eapdnid);
871 if (w != NULL && w->param.eapdbtl != HDAC_INVALID)
872 forcemute = (w->param.eapdbtl &
873 HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD) ? 0 : 1;
874 }
875
876 if (hdac_hp_switch[i].execsense != -1)
877 hdac_command(sc,
878 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
879 hdac_hp_switch[i].execsense), cad);
880 res = hdac_command(sc,
881 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
882 HDA_BOOTVERBOSE(
883 device_printf(sc->dev,
884 "HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
885 hdac_hp_switch[i].hpnid, res);
886 );
887 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
888 res ^= hdac_hp_switch[i].inverted;
889
890 switch (hdac_hp_switch[i].type) {
891 case HDAC_HP_SWITCH_CTL:
892 ctl = hdac_audio_ctl_amp_get(devinfo,
893 hdac_hp_switch[i].hpnid, 0, 1);
894 if (ctl != NULL) {
895 val = (res != 0 && forcemute == 0) ?
896 HDA_AMP_MUTE_NONE : HDA_AMP_MUTE_ALL;
897 if (val != ctl->muted) {
898 ctl->muted = val;
899 hdac_audio_ctl_amp_set(ctl,
900 HDA_AMP_MUTE_DEFAULT, ctl->left,
901 ctl->right);
902 }
903 }
904 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
905 ctl = hdac_audio_ctl_amp_get(devinfo,
906 hdac_hp_switch[i].spkrnid[j], 0, 1);
907 if (ctl == NULL)
908 continue;
909 val = (res != 0 || forcemute == 1) ?
910 HDA_AMP_MUTE_ALL : HDA_AMP_MUTE_NONE;
911 if (val == ctl->muted)
912 continue;
913 ctl->muted = val;
914 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
915 ctl->left, ctl->right);
916 }
917 break;
918 case HDAC_HP_SWITCH_CTRL:
919 if (res != 0) {
920 /* HP in */
921 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
922 if (w != NULL && w->type ==
923 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
924 if (forcemute == 0)
925 val = w->wclass.pin.ctrl |
926 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
927 else
928 val = w->wclass.pin.ctrl &
929 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
930 if (val != w->wclass.pin.ctrl) {
931 w->wclass.pin.ctrl = val;
932 hdac_command(sc,
933 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
934 w->nid, w->wclass.pin.ctrl), cad);
935 }
936 }
937 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
938 w = hdac_widget_get(devinfo,
939 hdac_hp_switch[i].spkrnid[j]);
940 if (w == NULL || w->type !=
941 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
942 continue;
943 val = w->wclass.pin.ctrl &
944 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
945 if (val == w->wclass.pin.ctrl)
946 continue;
947 w->wclass.pin.ctrl = val;
948 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
949 cad, w->nid, w->wclass.pin.ctrl), cad);
950 }
951 } else {
952 /* HP out */
953 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
954 if (w != NULL && w->type ==
955 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
956 val = w->wclass.pin.ctrl &
957 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
958 if (val != w->wclass.pin.ctrl) {
959 w->wclass.pin.ctrl = val;
960 hdac_command(sc,
961 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
962 w->nid, w->wclass.pin.ctrl), cad);
963 }
964 }
965 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
966 w = hdac_widget_get(devinfo,
967 hdac_hp_switch[i].spkrnid[j]);
968 if (w == NULL || w->type !=
969 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
970 continue;
971 if (forcemute == 0)
972 val = w->wclass.pin.ctrl |
973 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
974 else
975 val = w->wclass.pin.ctrl &
976 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
977 if (val == w->wclass.pin.ctrl)
978 continue;
979 w->wclass.pin.ctrl = val;
980 hdac_command(sc, HDA_CMD_SET_PIN_WIDGET_CTRL(
981 cad, w->nid, w->wclass.pin.ctrl), cad);
982 }
983 }
984 break;
985 case HDAC_HP_SWITCH_DEBUG:
986 if (hdac_hp_switch[i].execsense != -1)
987 hdac_command(sc,
988 HDA_CMD_SET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid,
989 hdac_hp_switch[i].execsense), cad);
990 res = hdac_command(sc,
991 HDA_CMD_GET_PIN_SENSE(cad, hdac_hp_switch[i].hpnid), cad);
992 device_printf(sc->dev,
993 "[ 0] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
994 hdac_hp_switch[i].hpnid, res);
995 for (j = 0; hdac_hp_switch[i].spkrnid[j] != -1; j++) {
996 w = hdac_widget_get(devinfo,
997 hdac_hp_switch[i].spkrnid[j]);
998 if (w == NULL || w->type !=
999 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1000 continue;
1001 if (hdac_hp_switch[i].execsense != -1)
1002 hdac_command(sc,
1003 HDA_CMD_SET_PIN_SENSE(cad, w->nid,
1004 hdac_hp_switch[i].execsense), cad);
1005 res = hdac_command(sc,
1006 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
1007 device_printf(sc->dev,
1008 "[%2d] HDA_DEBUG: Pin sense: nid=%d res=0x%08x\n",
1009 j + 1, w->nid, res);
1010 }
1011 break;
1012 default:
1013 break;
1014 }
1015 }
1016
1017 static void
1018 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1019 {
1020 struct hdac_softc *sc;
1021 struct hdac_devinfo *devinfo = NULL;
1022 device_t *devlist = NULL;
1023 int devcount, i;
1024
1025 if (codec == NULL || codec->sc == NULL)
1026 return;
1027
1028 sc = codec->sc;
1029
1030 HDA_BOOTVERBOSE(
1031 device_printf(sc->dev, "HDA_DEBUG: Unsol Tag: 0x%08x\n", tag);
1032 );
1033
1034 device_get_children(sc->dev, &devlist, &devcount);
1035 for (i = 0; devlist != NULL && i < devcount; i++) {
1036 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
1037 if (devinfo != NULL && devinfo->node_type ==
1038 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
1039 devinfo->codec != NULL &&
1040 devinfo->codec->cad == codec->cad) {
1041 break;
1042 } else
1043 devinfo = NULL;
1044 }
1045 if (devlist != NULL)
1046 kfree(devlist, M_TEMP);
1047
1048 if (devinfo == NULL)
1049 return;
1050
1051 switch (tag) {
1052 case HDAC_UNSOLTAG_EVENT_HP:
1053 hdac_hp_switch_handler(devinfo);
1054 break;
1055 case HDAC_UNSOLTAG_EVENT_TEST:
1056 device_printf(sc->dev, "Unsol Test!\n");
1057 break;
1058 default:
1059 break;
1060 }
1061 }
1062
1063 static int
1064 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1065 {
1066 /* XXX to be removed */
1067 #ifdef HDAC_INTR_EXTRA
1068 uint32_t res;
1069 #endif
1070
1071 if (ch->blkcnt == 0)
1072 return (0);
1073
1074 /* XXX to be removed */
1075 #ifdef HDAC_INTR_EXTRA
1076 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1077 #endif
1078
1079 /* XXX to be removed */
1080 #ifdef HDAC_INTR_EXTRA
1081 HDA_BOOTVERBOSE(
1082 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1083 device_printf(sc->dev,
1084 "PCMDIR_%s intr triggered beyond stream boundary:"
1085 "%08x\n",
1086 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1087 );
1088 #endif
1089
1090 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1091 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1092
1093 /* XXX to be removed */
1094 #ifdef HDAC_INTR_EXTRA
1095 if (res & HDAC_SDSTS_BCIS) {
1096 #endif
1097 return (1);
1098 /* XXX to be removed */
1099 #ifdef HDAC_INTR_EXTRA
1100 }
1101 #endif
1102
1103 return (0);
1104 }
1105
1106 /****************************************************************************
1107 * void hdac_intr_handler(void *)
1108 *
1109 * Interrupt handler. Processes interrupts received from the hdac.
1110 ****************************************************************************/
1111 static void
1112 hdac_intr_handler(void *context)
1113 {
1114 struct hdac_softc *sc;
1115 uint32_t intsts;
1116 uint8_t rirbsts;
1117 struct hdac_rirb *rirb_base;
1118 uint32_t trigger = 0;
1119
1120 sc = (struct hdac_softc *)context;
1121
1122 hdac_lock(sc);
1123 if (sc->polling != 0) {
1124 hdac_unlock(sc);
1125 return;
1126 }
1127 /* Do we have anything to do? */
1128 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1129 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1130 hdac_unlock(sc);
1131 return;
1132 }
1133
1134 /* Was this a controller interrupt? */
1135 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1136 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1137 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1138 /* Get as many responses that we can */
1139 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1140 HDAC_WRITE_1(&sc->mem,
1141 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1142 hdac_rirb_flush(sc);
1143 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1144 }
1145 /* XXX to be removed */
1146 /* Clear interrupt and exit */
1147 #ifdef HDAC_INTR_EXTRA
1148 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1149 #endif
1150 }
1151
1152 hdac_unsolq_flush(sc);
1153
1154 if (intsts & HDAC_INTSTS_SIS_MASK) {
1155 if ((intsts & (1 << sc->num_iss)) &&
1156 hdac_stream_intr(sc, &sc->play) != 0)
1157 trigger |= 1;
1158 if ((intsts & (1 << 0)) &&
1159 hdac_stream_intr(sc, &sc->rec) != 0)
1160 trigger |= 2;
1161 /* XXX to be removed */
1162 #ifdef HDAC_INTR_EXTRA
1163 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1164 HDAC_INTSTS_SIS_MASK);
1165 #endif
1166 }
1167
1168 hdac_unlock(sc);
1169
1170 if (trigger & 1)
1171 chn_intr(sc->play.c);
1172 if (trigger & 2)
1173 chn_intr(sc->rec.c);
1174 }
1175
1176 /****************************************************************************
1177 * int hdac_reset(hdac_softc *)
1178 *
1179 * Reset the hdac to a quiescent and known state.
1180 ****************************************************************************/
1181 static int
1182 hdac_reset(struct hdac_softc *sc)
1183 {
1184 uint32_t gctl;
1185 int count, i;
1186
1187 /*
1188 * Stop all Streams DMA engine
1189 */
1190 for (i = 0; i < sc->num_iss; i++)
1191 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1192 for (i = 0; i < sc->num_oss; i++)
1193 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1194 for (i = 0; i < sc->num_bss; i++)
1195 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1196
1197 /*
1198 * Stop Control DMA engines.
1199 */
1200 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1201 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1202
1203 /*
1204 * Reset DMA position buffer.
1205 */
1206 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1207 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1208
1209 /*
1210 * Reset the controller. The reset must remain asserted for
1211 * a minimum of 100us.
1212 */
1213 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1214 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1215 count = 10000;
1216 do {
1217 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1218 if (!(gctl & HDAC_GCTL_CRST))
1219 break;
1220 DELAY(10);
1221 } while (--count);
1222 if (gctl & HDAC_GCTL_CRST) {
1223 device_printf(sc->dev, "Unable to put hdac in reset\n");
1224 return (ENXIO);
1225 }
1226 DELAY(100);
1227 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1228 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1229 count = 10000;
1230 do {
1231 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1232 if (gctl & HDAC_GCTL_CRST)
1233 break;
1234 DELAY(10);
1235 } while (--count);
1236 if (!(gctl & HDAC_GCTL_CRST)) {
1237 device_printf(sc->dev, "Device stuck in reset\n");
1238 return (ENXIO);
1239 }
1240
1241 /*
1242 * Wait for codecs to finish their own reset sequence. The delay here
1243 * should be of 250us but for some reasons, on it's not enough on my
1244 * computer. Let's use twice as much as necessary to make sure that
1245 * it's reset properly.
1246 */
1247 DELAY(1000);
1248
1249 return (0);
1250 }
1251
1252
1253 /****************************************************************************
1254 * int hdac_get_capabilities(struct hdac_softc *);
1255 *
1256 * Retreive the general capabilities of the hdac;
1257 * Number of Input Streams
1258 * Number of Output Streams
1259 * Number of bidirectional Streams
1260 * 64bit ready
1261 * CORB and RIRB sizes
1262 ****************************************************************************/
1263 static int
1264 hdac_get_capabilities(struct hdac_softc *sc)
1265 {
1266 uint16_t gcap;
1267 uint8_t corbsize, rirbsize;
1268
1269 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1270 sc->num_iss = HDAC_GCAP_ISS(gcap);
1271 sc->num_oss = HDAC_GCAP_OSS(gcap);
1272 sc->num_bss = HDAC_GCAP_BSS(gcap);
1273
1274 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1275
1276 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1277 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1278 HDAC_CORBSIZE_CORBSZCAP_256)
1279 sc->corb_size = 256;
1280 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1281 HDAC_CORBSIZE_CORBSZCAP_16)
1282 sc->corb_size = 16;
1283 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1284 HDAC_CORBSIZE_CORBSZCAP_2)
1285 sc->corb_size = 2;
1286 else {
1287 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1288 __func__, corbsize);
1289 return (ENXIO);
1290 }
1291
1292 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1293 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1294 HDAC_RIRBSIZE_RIRBSZCAP_256)
1295 sc->rirb_size = 256;
1296 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1297 HDAC_RIRBSIZE_RIRBSZCAP_16)
1298 sc->rirb_size = 16;
1299 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1300 HDAC_RIRBSIZE_RIRBSZCAP_2)
1301 sc->rirb_size = 2;
1302 else {
1303 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1304 __func__, rirbsize);
1305 return (ENXIO);
1306 }
1307
1308 return (0);
1309 }
1310
1311
1312 /****************************************************************************
1313 * void hdac_dma_cb
1314 *
1315 * This function is called by bus_dmamap_load when the mapping has been
1316 * established. We just record the physical address of the mapping into
1317 * the struct hdac_dma passed in.
1318 ****************************************************************************/
1319 static void
1320 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1321 {
1322 struct hdac_dma *dma;
1323
1324 if (error == 0) {
1325 dma = (struct hdac_dma *)callback_arg;
1326 dma->dma_paddr = segs[0].ds_addr;
1327 }
1328 }
1329
1330
1331 /****************************************************************************
1332 * int hdac_dma_alloc
1333 *
1334 * This function allocate and setup a dma region (struct hdac_dma).
1335 * It must be freed by a corresponding hdac_dma_free.
1336 ****************************************************************************/
1337 static int
1338 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1339 {
1340 bus_size_t roundsz;
1341 int result;
1342 int lowaddr;
1343
1344 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1345 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1346 BUS_SPACE_MAXADDR_32BIT;
1347 bzero(dma, sizeof(*dma));
1348
1349 /*
1350 * Create a DMA tag
1351 */
1352 result = bus_dma_tag_create(NULL, /* parent */
1353 HDAC_DMA_ALIGNMENT, /* alignment */
1354 0, /* boundary */
1355 lowaddr, /* lowaddr */
1356 BUS_SPACE_MAXADDR, /* highaddr */
1357 NULL, /* filtfunc */
1358 NULL, /* fistfuncarg */
1359 roundsz, /* maxsize */
1360 1, /* nsegments */
1361 roundsz, /* maxsegsz */
1362 0, /* flags */
1363 &dma->dma_tag); /* dmat */
1364 if (result != 0) {
1365 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1366 __func__, result);
1367 goto hdac_dma_alloc_fail;
1368 }
1369
1370 /*
1371 * Allocate DMA memory
1372 */
1373 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1374 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1375 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1376 ((sc->nocache != 0) ? BUS_DMA_NOCACHE : 0), &dma->dma_map);
1377 #else
1378 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1379 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &dma->dma_map);
1380 #endif
1381 if (result != 0) {
1382 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1383 __func__, result);
1384 goto hdac_dma_alloc_fail;
1385 }
1386
1387 dma->dma_size = roundsz;
1388
1389 /*
1390 * Map the memory
1391 */
1392 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1393 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1394 if (result != 0 || dma->dma_paddr == 0) {
1395 if (result == 0)
1396 result = ENOMEM;
1397 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1398 __func__, result);
1399 goto hdac_dma_alloc_fail;
1400 }
1401
1402 HDA_BOOTVERBOSE(
1403 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1404 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1405 );
1406
1407 return (0);
1408
1409 hdac_dma_alloc_fail:
1410 hdac_dma_free(sc, dma);
1411
1412 return (result);
1413 }
1414
1415
1416 /****************************************************************************
1417 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1418 *
1419 * Free a struct dhac_dma that has been previously allocated via the
1420 * hdac_dma_alloc function.
1421 ****************************************************************************/
1422 static void
1423 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1424 {
1425 if (dma->dma_map != NULL) {
1426 #if 0
1427 /* Flush caches */
1428 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1429 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1430 #endif
1431 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1432 }
1433 if (dma->dma_vaddr != NULL) {
1434 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1435 dma->dma_vaddr = NULL;
1436 }
1437 dma->dma_map = NULL;
1438 if (dma->dma_tag != NULL) {
1439 bus_dma_tag_destroy(dma->dma_tag);
1440 dma->dma_tag = NULL;
1441 }
1442 dma->dma_size = 0;
1443 }
1444
1445 /****************************************************************************
1446 * int hdac_mem_alloc(struct hdac_softc *)
1447 *
1448 * Allocate all the bus resources necessary to speak with the physical
1449 * controller.
1450 ****************************************************************************/
1451 static int
1452 hdac_mem_alloc(struct hdac_softc *sc)
1453 {
1454 struct hdac_mem *mem;
1455
1456 mem = &sc->mem;
1457 mem->mem_rid = PCIR_BAR(0);
1458 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1459 &mem->mem_rid, RF_ACTIVE);
1460 if (mem->mem_res == NULL) {
1461 device_printf(sc->dev,
1462 "%s: Unable to allocate memory resource\n", __func__);
1463 return (ENOMEM);
1464 }
1465 mem->mem_tag = rman_get_bustag(mem->mem_res);
1466 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1467
1468 return (0);
1469 }
1470
1471 /****************************************************************************
1472 * void hdac_mem_free(struct hdac_softc *)
1473 *
1474 * Free up resources previously allocated by hdac_mem_alloc.
1475 ****************************************************************************/
1476 static void
1477 hdac_mem_free(struct hdac_softc *sc)
1478 {
1479 struct hdac_mem *mem;
1480
1481 mem = &sc->mem;
1482 if (mem->mem_res != NULL)
1483 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1484 mem->mem_res);
1485 mem->mem_res = NULL;
1486 }
1487
1488 /****************************************************************************
1489 * int hdac_irq_alloc(struct hdac_softc *)
1490 *
1491 * Allocate and setup the resources necessary for interrupt handling.
1492 ****************************************************************************/
1493 static int
1494 hdac_irq_alloc(struct hdac_softc *sc)
1495 {
1496 struct hdac_irq *irq;
1497 int result;
1498
1499 irq = &sc->irq;
1500 irq->irq_rid = 0x0;
1501 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1502 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1503 if (irq->irq_res == NULL) {
1504 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1505 __func__);
1506 goto hdac_irq_alloc_fail;
1507 }
1508 result = snd_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE,
1509 hdac_intr_handler, sc, &irq->irq_handle);
1510 if (result != 0) {
1511 device_printf(sc->dev,
1512 "%s: Unable to setup interrupt handler (%x)\n",
1513 __func__, result);
1514 goto hdac_irq_alloc_fail;
1515 }
1516
1517 return (0);
1518
1519 hdac_irq_alloc_fail:
1520 hdac_irq_free(sc);
1521
1522 return (ENXIO);
1523 }
1524
1525 /****************************************************************************
1526 * void hdac_irq_free(struct hdac_softc *)
1527 *
1528 * Free up resources previously allocated by hdac_irq_alloc.
1529 ****************************************************************************/
1530 static void
1531 hdac_irq_free(struct hdac_softc *sc)
1532 {
1533 struct hdac_irq *irq;
1534
1535 irq = &sc->irq;
1536 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1537 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1538 if (irq->irq_res != NULL)
1539 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1540 irq->irq_res);
1541 irq->irq_handle = NULL;
1542 irq->irq_res = NULL;
1543 }
1544
1545 /****************************************************************************
1546 * void hdac_corb_init(struct hdac_softc *)
1547 *
1548 * Initialize the corb registers for operations but do not start it up yet.
1549 * The CORB engine must not be running when this function is called.
1550 ****************************************************************************/
1551 static void
1552 hdac_corb_init(struct hdac_softc *sc)
1553 {
1554 uint8_t corbsize;
1555 uint64_t corbpaddr;
1556
1557 /* Setup the CORB size. */
1558 switch (sc->corb_size) {
1559 case 256:
1560 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1561 break;
1562 case 16:
1563 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1564 break;
1565 case 2:
1566 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1567 break;
1568 default:
1569 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1570 }
1571 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1572
1573 /* Setup the CORB Address in the hdac */
1574 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1575 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1576 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1577
1578 /* Set the WP and RP */
1579 sc->corb_wp = 0;
1580 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1581 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1582 /*
1583 * The HDA specification indicates that the CORBRPRST bit will always
1584 * read as zero. Unfortunately, it seems that at least the 82801G
1585 * doesn't reset the bit to zero, which stalls the corb engine.
1586 * manually reset the bit to zero before continuing.
1587 */
1588 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1589
1590 /* Enable CORB error reporting */
1591 #if 0
1592 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1593 #endif
1594 }
1595
1596 /****************************************************************************
1597 * void hdac_rirb_init(struct hdac_softc *)
1598 *
1599 * Initialize the rirb registers for operations but do not start it up yet.
1600 * The RIRB engine must not be running when this function is called.
1601 ****************************************************************************/
1602 static void
1603 hdac_rirb_init(struct hdac_softc *sc)
1604 {
1605 uint8_t rirbsize;
1606 uint64_t rirbpaddr;
1607
1608 /* Setup the RIRB size. */
1609 switch (sc->rirb_size) {
1610 case 256:
1611 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1612 break;
1613 case 16:
1614 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1615 break;
1616 case 2:
1617 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1618 break;
1619 default:
1620 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1621 }
1622 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1623
1624 /* Setup the RIRB Address in the hdac */
1625 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
1626 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
1627 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
1628
1629 /* Setup the WP and RP */
1630 sc->rirb_rp = 0;
1631 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
1632
1633 if (sc->polling == 0) {
1634 /* Setup the interrupt threshold */
1635 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
1636
1637 /* Enable Overrun and response received reporting */
1638 #if 0
1639 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
1640 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
1641 #else
1642 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
1643 #endif
1644 }
1645
1646 #if 0
1647 /*
1648 * Make sure that the Host CPU cache doesn't contain any dirty
1649 * cache lines that falls in the rirb. If I understood correctly, it
1650 * should be sufficient to do this only once as the rirb is purely
1651 * read-only from now on.
1652 */
1653 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
1654 BUS_DMASYNC_PREREAD);
1655 #endif
1656 }
1657
1658 /****************************************************************************
1659 * void hdac_corb_start(hdac_softc *)
1660 *
1661 * Startup the corb DMA engine
1662 ****************************************************************************/
1663 static void
1664 hdac_corb_start(struct hdac_softc *sc)
1665 {
1666 uint32_t corbctl;
1667
1668 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
1669 corbctl |= HDAC_CORBCTL_CORBRUN;
1670 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
1671 }
1672
1673 /****************************************************************************
1674 * void hdac_rirb_start(hdac_softc *)
1675 *
1676 * Startup the rirb DMA engine
1677 ****************************************************************************/
1678 static void
1679 hdac_rirb_start(struct hdac_softc *sc)
1680 {
1681 uint32_t rirbctl;
1682
1683 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
1684 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
1685 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
1686 }
1687
1688
1689 /****************************************************************************
1690 * void hdac_scan_codecs(struct hdac_softc *)
1691 *
1692 * Scan the bus for available codecs.
1693 ****************************************************************************/
1694 static void
1695 hdac_scan_codecs(struct hdac_softc *sc)
1696 {
1697 struct hdac_codec *codec;
1698 int i;
1699 uint16_t statests;
1700
1701 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1702 for (i = 0; i < HDAC_CODEC_MAX; i++) {
1703 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1704 /* We have found a codec. */
1705 codec = (struct hdac_codec *)kmalloc(sizeof(*codec),
1706 M_HDAC, M_ZERO | M_NOWAIT);
1707 if (codec == NULL) {
1708 device_printf(sc->dev,
1709 "Unable to allocate memory for codec\n");
1710 continue;
1711 }
1712 codec->commands = NULL;
1713 codec->responses_received = 0;
1714 codec->verbs_sent = 0;
1715 codec->sc = sc;
1716 codec->cad = i;
1717 sc->codecs[i] = codec;
1718 if (hdac_probe_codec(codec) != 0)
1719 break;
1720 }
1721 }
1722 /* All codecs have been probed, now try to attach drivers to them */
1723 /* bus_generic_attach(sc->dev); */
1724 }
1725
1726 /****************************************************************************
1727 * void hdac_probe_codec(struct hdac_softc *, int)
1728 *
1729 * Probe a the given codec_id for available function groups.
1730 ****************************************************************************/
1731 static int
1732 hdac_probe_codec(struct hdac_codec *codec)
1733 {
1734 struct hdac_softc *sc = codec->sc;
1735 struct hdac_devinfo *devinfo;
1736 uint32_t vendorid, revisionid, subnode;
1737 int startnode;
1738 int endnode;
1739 int i;
1740 nid_t cad = codec->cad;
1741
1742 HDA_BOOTVERBOSE(
1743 device_printf(sc->dev, "HDA_DEBUG: Probing codec: %d\n", cad);
1744 );
1745 vendorid = hdac_command(sc,
1746 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
1747 cad);
1748 revisionid = hdac_command(sc,
1749 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
1750 cad);
1751 subnode = hdac_command(sc,
1752 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
1753 cad);
1754 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
1755 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
1756
1757 HDA_BOOTVERBOSE(
1758 device_printf(sc->dev, "HDA_DEBUG: \tstartnode=%d endnode=%d\n",
1759 startnode, endnode);
1760 );
1761 for (i = startnode; i < endnode; i++) {
1762 devinfo = hdac_probe_function(codec, i);
1763 if (devinfo != NULL) {
1764 /* XXX Ignore other FG. */
1765 devinfo->vendor_id =
1766 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1767 devinfo->device_id =
1768 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1769 devinfo->revision_id =
1770 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1771 devinfo->stepping_id =
1772 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1773 HDA_BOOTVERBOSE(
1774 device_printf(sc->dev,
1775 "HDA_DEBUG: \tFound AFG nid=%d "
1776 "[startnode=%d endnode=%d]\n",
1777 devinfo->nid, startnode, endnode);
1778 );
1779 return (1);
1780 }
1781 }
1782
1783 HDA_BOOTVERBOSE(
1784 device_printf(sc->dev, "HDA_DEBUG: \tAFG not found\n");
1785 );
1786 return (0);
1787 }
1788
1789 static struct hdac_devinfo *
1790 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
1791 {
1792 struct hdac_softc *sc = codec->sc;
1793 struct hdac_devinfo *devinfo;
1794 uint32_t fctgrptype;
1795 nid_t cad = codec->cad;
1796
1797 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
1798 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
1799
1800 /* XXX For now, ignore other FG. */
1801 if (fctgrptype != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
1802 return (NULL);
1803
1804 devinfo = (struct hdac_devinfo *)kmalloc(sizeof(*devinfo), M_HDAC,
1805 M_NOWAIT | M_ZERO);
1806 if (devinfo == NULL) {
1807 device_printf(sc->dev, "%s: Unable to allocate ivar\n",
1808 __func__);
1809 return (NULL);
1810 }
1811
1812 devinfo->nid = nid;
1813 devinfo->node_type = fctgrptype;
1814 devinfo->codec = codec;
1815
1816 hdac_add_child(sc, devinfo);
1817
1818 return (devinfo);
1819 }
1820
1821 static void
1822 hdac_add_child(struct hdac_softc *sc, struct hdac_devinfo *devinfo)
1823 {
1824 devinfo->dev = device_add_child(sc->dev, NULL, -1);
1825 device_set_ivars(devinfo->dev, (void *)devinfo);
1826 /* XXX - Print more information when booting verbose??? */
1827 }
1828
1829 static void
1830 hdac_widget_connection_parse(struct hdac_widget *w)
1831 {
1832 struct hdac_softc *sc = w->devinfo->codec->sc;
1833 uint32_t res;
1834 int i, j, max, ents, entnum;
1835 nid_t cad = w->devinfo->codec->cad;
1836 nid_t nid = w->nid;
1837 nid_t cnid, addcnid, prevcnid;
1838
1839 w->nconns = 0;
1840
1841 res = hdac_command(sc,
1842 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
1843
1844 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
1845
1846 if (ents < 1)
1847 return;
1848
1849 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
1850 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
1851 prevcnid = 0;
1852
1853 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
1854 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
1855 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
1856 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
1857 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
1858
1859 for (i = 0; i < ents; i += entnum) {
1860 res = hdac_command(sc,
1861 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
1862 for (j = 0; j < entnum; j++) {
1863 cnid = CONN_CNID(res, entnum, j);
1864 if (cnid == 0) {
1865 if (w->nconns < ents)
1866 device_printf(sc->dev,
1867 "%s: nid=%d WARNING: zero cnid "
1868 "entnum=%d j=%d index=%d "
1869 "entries=%d found=%d res=0x%08x\n",
1870 __func__, nid, entnum, j, i,
1871 ents, w->nconns, res);
1872 else
1873 goto getconns_out;
1874 }
1875 if (cnid < w->devinfo->startnode ||
1876 cnid >= w->devinfo->endnode) {
1877 HDA_BOOTVERBOSE(
1878 device_printf(sc->dev,
1879 "%s: GHOST: nid=%d j=%d "
1880 "entnum=%d index=%d res=0x%08x\n",
1881 __func__, nid, j, entnum, i, res);
1882 );
1883 }
1884 if (CONN_RANGE(res, entnum, j) == 0)
1885 addcnid = cnid;
1886 else if (prevcnid == 0 || prevcnid >= cnid) {
1887 device_printf(sc->dev,
1888 "%s: WARNING: Invalid child range "
1889 "nid=%d index=%d j=%d entnum=%d "
1890 "prevcnid=%d cnid=%d res=0x%08x\n",
1891 __func__, nid, i, j, entnum, prevcnid,
1892 cnid, res);
1893 addcnid = cnid;
1894 } else
1895 addcnid = prevcnid + 1;
1896 while (addcnid <= cnid) {
1897 if (w->nconns > max) {
1898 device_printf(sc->dev,
1899 "%s: nid=%d: Adding %d: "
1900 "Max connection reached! max=%d\n",
1901 __func__, nid, addcnid, max + 1);
1902 goto getconns_out;
1903 }
1904 w->conns[w->nconns++] = addcnid++;
1905 }
1906 prevcnid = cnid;
1907 }
1908 }
1909
1910 getconns_out:
1911 HDA_BOOTVERBOSE(
1912 device_printf(sc->dev,
1913 "HDA_DEBUG: %s: nid=%d entries=%d found=%d\n",
1914 __func__, nid, ents, w->nconns);
1915 );
1916 return;
1917 }
1918
1919 static uint32_t
1920 hdac_widget_pin_getconfig(struct hdac_widget *w)
1921 {
1922 struct hdac_softc *sc;
1923 uint32_t config, orig, id;
1924 nid_t cad, nid;
1925
1926 sc = w->devinfo->codec->sc;
1927 cad = w->devinfo->codec->cad;
1928 nid = w->nid;
1929 id = hdac_codec_id(w->devinfo);
1930
1931 config = hdac_command(sc,
1932 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
1933 cad);
1934 orig = config;
1935
1936 /*
1937 * XXX REWRITE!!!! Don't argue!
1938 */
1939 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
1940 switch (nid) {
1941 case 26:
1942 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1943 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1944 break;
1945 case 27:
1946 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1947 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
1948 break;
1949 default:
1950 break;
1951 }
1952 } else if (id == HDA_CODEC_ALC880 &&
1953 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
1954 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
1955 /*
1956 * Super broken BIOS
1957 */
1958 switch (nid) {
1959 case 20:
1960 break;
1961 case 21:
1962 break;
1963 case 22:
1964 break;
1965 case 23:
1966 break;
1967 case 24: /* MIC1 */
1968 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1969 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1970 break;
1971 case 25: /* XXX MIC2 */
1972 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1973 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
1974 break;
1975 case 26: /* LINE1 */
1976 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1977 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1978 break;
1979 case 27: /* XXX LINE2 */
1980 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1981 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
1982 break;
1983 case 28: /* CD */
1984 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
1985 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
1986 break;
1987 case 30:
1988 break;
1989 case 31:
1990 break;
1991 default:
1992 break;
1993 }
1994 } else if (id == HDA_CODEC_ALC883 &&
1995 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) {
1996 switch (nid) {
1997 case 25:
1998 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
1999 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2000 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2001 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2002 break;
2003 case 28:
2004 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2005 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2006 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2007 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2008 break;
2009 default:
2010 break;
2011 }
2012 } else if (id == HDA_CODEC_CXVENICE && sc->pci_subvendor ==
2013 HP_V3000_SUBVENDOR) {
2014 switch (nid) {
2015 case 18:
2016 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2017 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2018 break;
2019 case 20:
2020 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2021 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2022 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2023 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2024 break;
2025 case 21:
2026 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2027 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2028 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2029 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2030 break;
2031 default:
2032 break;
2033 }
2034 } else if (id == HDA_CODEC_CXWAIKIKI && sc->pci_subvendor ==
2035 HP_DV5000_SUBVENDOR) {
2036 switch (nid) {
2037 case 20:
2038 case 21:
2039 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2040 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2041 break;
2042 default:
2043 break;
2044 }
2045 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2046 ASUS_W6F_SUBVENDOR) {
2047 switch (nid) {
2048 case 11:
2049 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2050 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2051 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2052 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2053 break;
2054 case 15:
2055 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2056 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2057 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2058 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2059 break;
2060 default:
2061 break;
2062 }
2063 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2064 UNIWILL_9075_SUBVENDOR) {
2065 switch (nid) {
2066 case 15:
2067 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2068 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2069 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2070 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2071 break;
2072 default:
2073 break;
2074 }
2075 } else if (id == HDA_CODEC_AD1986A && sc->pci_subvendor ==
2076 ASUS_M2NPVMX_SUBVENDOR) {
2077 switch (nid) {
2078 case 28: /* LINE */
2079 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2080 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2081 break;
2082 case 29: /* MIC */
2083 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2084 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2085 break;
2086 default:
2087 break;
2088 }
2089 }
2090
2091 HDA_BOOTVERBOSE(
2092 if (config != orig)
2093 device_printf(sc->dev,
2094 "HDA_DEBUG: Pin config nid=%u 0x%08x -> 0x%08x\n",
2095 nid, orig, config);
2096 );
2097
2098 return (config);
2099 }
2100
2101 static uint32_t
2102 hdac_widget_pin_getcaps(struct hdac_widget *w)
2103 {
2104 struct hdac_softc *sc;
2105 uint32_t caps, orig, id;
2106 nid_t cad, nid;
2107
2108 sc = w->devinfo->codec->sc;
2109 cad = w->devinfo->codec->cad;
2110 nid = w->nid;
2111 id = hdac_codec_id(w->devinfo);
2112
2113 caps = hdac_command(sc,
2114 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2115 orig = caps;
2116
2117 HDA_BOOTVERBOSE(
2118 if (caps != orig)
2119 device_printf(sc->dev,
2120 "HDA_DEBUG: Pin caps nid=%u 0x%08x -> 0x%08x\n",
2121 nid, orig, caps);
2122 );
2123
2124 return (caps);
2125 }
2126
2127 static void
2128 hdac_widget_pin_parse(struct hdac_widget *w)
2129 {
2130 struct hdac_softc *sc = w->devinfo->codec->sc;
2131 uint32_t config, pincap;
2132 char *devstr, *connstr;
2133 nid_t cad = w->devinfo->codec->cad;
2134 nid_t nid = w->nid;
2135
2136 config = hdac_widget_pin_getconfig(w);
2137 w->wclass.pin.config = config;
2138
2139 pincap = hdac_widget_pin_getcaps(w);
2140 w->wclass.pin.cap = pincap;
2141
2142 w->wclass.pin.ctrl = hdac_command(sc,
2143 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad) &
2144 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
2145 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
2146 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
2147 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
2148
2149 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
2150 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
2151 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
2152 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
2153 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
2154 w->wclass.pin.ctrl |= HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
2155 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2156 w->param.eapdbtl = hdac_command(sc,
2157 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2158 w->param.eapdbtl &= 0x7;
2159 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2160 } else
2161 w->param.eapdbtl = HDAC_INVALID;
2162
2163 switch (config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
2164 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
2165 devstr = "line out";
2166 break;
2167 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
2168 devstr = "speaker";
2169 break;
2170 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
2171 devstr = "headphones out";
2172 break;
2173 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
2174 devstr = "CD";
2175 break;
2176 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
2177 devstr = "SPDIF out";
2178 break;
2179 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
2180 devstr = "digital (other) out";
2181 break;
2182 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE:
2183 devstr = "modem, line side";
2184 break;
2185 case HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET:
2186 devstr = "modem, handset side";
2187 break;
2188 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
2189 devstr = "line in";
2190 break;
2191 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
2192 devstr = "AUX";
2193 break;
2194 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
2195 devstr = "Mic in";
2196 break;
2197 case HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY:
2198 devstr = "telephony";
2199 break;
2200 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
2201 devstr = "SPDIF in";
2202 break;
2203 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
2204 devstr = "digital (other) in";
2205 break;
2206 case HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER:
2207 devstr = "other";
2208 break;
2209 default:
2210 devstr = "unknown";
2211 break;
2212 }
2213
2214 switch (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) {
2215 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK:
2216 connstr = "jack";
2217 break;
2218 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE:
2219 connstr = "none";
2220 break;
2221 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED:
2222 connstr = "fixed";
2223 break;
2224 case HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH:
2225 connstr = "jack / fixed";
2226 break;
2227 default:
2228 connstr = "unknown";
2229 break;
2230 }
2231
2232 strlcat(w->name, ": ", sizeof(w->name));
2233 strlcat(w->name, devstr, sizeof(w->name));
2234 strlcat(w->name, " (", sizeof(w->name));
2235 strlcat(w->name, connstr, sizeof(w->name));
2236 strlcat(w->name, ")", sizeof(w->name));
2237 }
2238
2239 static void
2240 hdac_widget_parse(struct hdac_widget *w)
2241 {
2242 struct hdac_softc *sc = w->devinfo->codec->sc;
2243 uint32_t wcap, cap;
2244 char *typestr;
2245 nid_t cad = w->devinfo->codec->cad;
2246 nid_t nid = w->nid;
2247
2248 wcap = hdac_command(sc,
2249 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2250 cad);
2251 w->param.widget_cap = wcap;
2252 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2253
2254 switch (w->type) {
2255 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2256 typestr = "audio output";
2257 break;
2258 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2259 typestr = "audio input";
2260 break;
2261 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2262 typestr = "audio mixer";
2263 break;
2264 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2265 typestr = "audio selector";
2266 break;
2267 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2268 typestr = "pin";
2269 break;
2270 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2271 typestr = "power widget";
2272 break;
2273 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2274 typestr = "volume widget";
2275 break;
2276 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2277 typestr = "beep widget";
2278 break;
2279 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2280 typestr = "vendor widget";
2281 break;
2282 default:
2283 typestr = "unknown type";
2284 break;
2285 }
2286
2287 strlcpy(w->name, typestr, sizeof(w->name));
2288
2289 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(wcap)) {
2290 hdac_command(sc,
2291 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0),
2292 cad);
2293 DELAY(1000);
2294 }
2295
2296 hdac_widget_connection_parse(w);
2297
2298 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2299 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2300 w->param.outamp_cap =
2301 hdac_command(sc,
2302 HDA_CMD_GET_PARAMETER(cad, nid,
2303 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2304 else
2305 w->param.outamp_cap =
2306 w->devinfo->function.audio.outamp_cap;
2307 } else
2308 w->param.outamp_cap = 0;
2309
2310 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2311 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2312 w->param.inamp_cap =
2313 hdac_command(sc,
2314 HDA_CMD_GET_PARAMETER(cad, nid,
2315 HDA_PARAM_INPUT_AMP_CAP), cad);
2316 else
2317 w->param.inamp_cap =
2318 w->devinfo->function.audio.inamp_cap;
2319 } else
2320 w->param.inamp_cap = 0;
2321
2322 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2323 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2324 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2325 cap = hdac_command(sc,
2326 HDA_CMD_GET_PARAMETER(cad, nid,
2327 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2328 w->param.supp_stream_formats = (cap != 0) ? cap :
2329 w->devinfo->function.audio.supp_stream_formats;
2330 cap = hdac_command(sc,
2331 HDA_CMD_GET_PARAMETER(cad, nid,
2332 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2333 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2334 w->devinfo->function.audio.supp_pcm_size_rate;
2335 } else {
2336 w->param.supp_stream_formats =
2337 w->devinfo->function.audio.supp_stream_formats;
2338 w->param.supp_pcm_size_rate =
2339 w->devinfo->function.audio.supp_pcm_size_rate;
2340 }
2341 } else {
2342 w->param.supp_stream_formats = 0;
2343 w->param.supp_pcm_size_rate = 0;
2344 }
2345
2346 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2347 hdac_widget_pin_parse(w);
2348 }
2349
2350 static struct hdac_widget *
2351 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2352 {
2353 if (devinfo == NULL || devinfo->widget == NULL ||
2354 nid < devinfo->startnode || nid >= devinfo->endnode)
2355 return (NULL);
2356 return (&devinfo->widget[nid - devinfo->startnode]);
2357 }
2358
2359 static __inline int
2360 hda_poll_channel(struct hdac_chan *ch)
2361 {
2362 uint32_t sz, delta;
2363 volatile uint32_t ptr;
2364
2365 if (ch->active == 0)
2366 return (0);
2367
2368 sz = ch->blksz * ch->blkcnt;
2369 if (ch->dmapos != NULL)
2370 ptr = *(ch->dmapos);
2371 else
2372 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2373 ch->off + HDAC_SDLPIB);
2374 ch->ptr = ptr;
2375 ptr %= sz;
2376 ptr &= ~(ch->blksz - 1);
2377 delta = (sz + ptr - ch->prevptr) % sz;
2378
2379 if (delta < ch->blksz)
2380 return (0);
2381
2382 ch->prevptr = ptr;
2383
2384 return (1);
2385 }
2386
2387 #define hda_chan_active(sc) ((sc)->play.active + (sc)->rec.active)
2388
2389 static void
2390 hda_poll_callback(void *arg)
2391 {
2392 struct hdac_softc *sc = arg;
2393 uint32_t trigger = 0;
2394
2395 if (sc == NULL)
2396 return;
2397
2398 hdac_lock(sc);
2399 if (sc->polling == 0 || hda_chan_active(sc) == 0) {
2400 hdac_unlock(sc);
2401 return;
2402 }
2403
2404 trigger |= (hda_poll_channel(&sc->play) != 0) ? 1 : 0;
2405 trigger |= (hda_poll_channel(&sc->rec) != 0) ? 2 : 0;
2406
2407 /* XXX */
2408 callout_reset(&sc->poll_hda, 1/*sc->poll_ticks*/,
2409 hda_poll_callback, sc);
2410
2411 hdac_unlock(sc);
2412
2413 if (trigger & 1)
2414 chn_intr(sc->play.c);
2415 if (trigger & 2)
2416 chn_intr(sc->rec.c);
2417 }
2418
2419 static int
2420 hdac_rirb_flush(struct hdac_softc *sc)
2421 {
2422 struct hdac_rirb *rirb_base, *rirb;
2423 struct hdac_codec *codec;
2424 struct hdac_command_list *commands;
2425 nid_t cad;
2426 uint32_t resp;
2427 uint8_t rirbwp;
2428 int ret = 0;
2429
2430 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2431 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2432 #if 0
2433 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2434 BUS_DMASYNC_POSTREAD);
2435 #endif
2436
2437 while (sc->rirb_rp != rirbwp) {
2438 sc->rirb_rp++;
2439 sc->rirb_rp %= sc->rirb_size;
2440 rirb = &rirb_base[sc->rirb_rp];
2441 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2442 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2443 sc->codecs[cad] == NULL)
2444 continue;
2445 resp = rirb->response;
2446 codec = sc->codecs[cad];
2447 commands = codec->commands;
2448 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2449 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2450 ((resp >> 26) & 0xffff);
2451 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2452 } else if (commands != NULL && commands->num_commands > 0 &&
2453 codec->responses_received < commands->num_commands)
2454 commands->responses[codec->responses_received++] =
2455 resp;
2456 ret++;
2457 }
2458
2459 return (ret);
2460 }
2461
2462 static int
2463 hdac_unsolq_flush(struct hdac_softc *sc)
2464 {
2465 nid_t cad;
2466 uint32_t tag;
2467 int ret = 0;
2468
2469 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2470 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2471 while (sc->unsolq_rp != sc->unsolq_wp) {
2472 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2473 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2474 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2475 hdac_unsolicited_handler(sc->codecs[cad], tag);
2476 ret++;
2477 }
2478 sc->unsolq_st = HDAC_UNSOLQ_READY;
2479 }
2480
2481 return (ret);
2482 }
2483
2484 static void
2485 hdac_poll_callback(void *arg)
2486 {
2487 struct hdac_softc *sc = arg;
2488 if (sc == NULL)
2489 return;
2490
2491 hdac_lock(sc);
2492 if (sc->polling == 0 || sc->poll_ival == 0) {
2493 hdac_unlock(sc);
2494 return;
2495 }
2496 hdac_rirb_flush(sc);
2497 hdac_unsolq_flush(sc);
2498 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
2499 hdac_unlock(sc);
2500 }
2501
2502 static void
2503 hdac_stream_stop(struct hdac_chan *ch)
2504 {
2505 struct hdac_softc *sc = ch->devinfo->codec->sc;
2506 uint32_t ctl;
2507
2508 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2509 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2510 HDAC_SDCTL_RUN);
2511 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2512
2513 ch->active = 0;
2514
2515 if (sc->polling != 0) {
2516 int pollticks;
2517
2518 if (hda_chan_active(sc) == 0) {
2519 callout_stop(&sc->poll_hda);
2520 sc->poll_ticks = 1;
2521 } else {
2522 if (sc->play.active != 0)
2523 ch = &sc->play;
2524 else
2525 ch = &sc->rec;
2526 pollticks = ((uint64_t)hz * ch->blksz) /
2527 ((uint64_t)sndbuf_getbps(ch->b) *
2528 sndbuf_getspd(ch->b));
2529 pollticks >>= 2;
2530 if (pollticks > hz)
2531 pollticks = hz;
2532 if (pollticks < 1) {
2533 HDA_BOOTVERBOSE(
2534 device_printf(sc->dev,
2535 "%s: pollticks=%d < 1 !\n",
2536 __func__, pollticks);
2537 );
2538 pollticks = 1;
2539 }
2540 if (pollticks > sc->poll_ticks) {
2541 HDA_BOOTVERBOSE(
2542 device_printf(sc->dev,
2543 "%s: pollticks %d -> %d\n",
2544 __func__, sc->poll_ticks,
2545 pollticks);
2546 );
2547 sc->poll_ticks = pollticks;
2548 callout_reset(&sc->poll_hda, 1,
2549 hda_poll_callback, sc);
2550 }
2551 }
2552 } else {
2553 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2554 ctl &= ~(1 << (ch->off >> 5));
2555 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2556 }
2557 }
2558
2559 static void
2560 hdac_stream_start(struct hdac_chan *ch)
2561 {
2562 struct hdac_softc *sc = ch->devinfo->codec->sc;
2563 uint32_t ctl;
2564
2565 if (sc->polling != 0) {
2566 int pollticks;
2567
2568 pollticks = ((uint64_t)hz * ch->blksz) /
2569 ((uint64_t)sndbuf_getbps(ch->b) * sndbuf_getspd(ch->b));
2570 pollticks >>= 2;
2571 if (pollticks > hz)
2572 pollticks = hz;
2573 if (pollticks < 1) {
2574 HDA_BOOTVERBOSE(
2575 device_printf(sc->dev,
2576 "%s: pollticks=%d < 1 !\n",
2577 __func__, pollticks);
2578 );
2579 pollticks = 1;
2580 }
2581 if (hda_chan_active(sc) == 0 || pollticks < sc->poll_ticks) {
2582 HDA_BOOTVERBOSE(
2583 if (hda_chan_active(sc) == 0) {
2584 device_printf(sc->dev,
2585 "%s: pollticks=%d\n",
2586 __func__, pollticks);
2587 } else {
2588 device_printf(sc->dev,
2589 "%s: pollticks %d -> %d\n",
2590 __func__, sc->poll_ticks,
2591 pollticks);
2592 }
2593 );
2594 sc->poll_ticks = pollticks;
2595 callout_reset(&sc->poll_hda, 1, hda_poll_callback,
2596 sc);
2597 }
2598 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2599 ctl |= HDAC_SDCTL_RUN;
2600 } else {
2601 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
2602 ctl |= 1 << (ch->off >> 5);
2603 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
2604 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2605 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
2606 HDAC_SDCTL_RUN;
2607 }
2608 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2609
2610 ch->active = 1;
2611 }
2612
2613 static void
2614 hdac_stream_reset(struct hdac_chan *ch)
2615 {
2616 struct hdac_softc *sc = ch->devinfo->codec->sc;
2617 int timeout = 1000;
2618 int to = timeout;
2619 uint32_t ctl;
2620
2621 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2622 ctl |= HDAC_SDCTL_SRST;
2623 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2624 do {
2625 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2626 if (ctl & HDAC_SDCTL_SRST)
2627 break;
2628 DELAY(10);
2629 } while (--to);
2630 if (!(ctl & HDAC_SDCTL_SRST)) {
2631 device_printf(sc->dev, "timeout in reset\n");
2632 }
2633 ctl &= ~HDAC_SDCTL_SRST;
2634 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
2635 to = timeout;
2636 do {
2637 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
2638 if (!(ctl & HDAC_SDCTL_SRST))
2639 break;
2640 DELAY(10);
2641 } while (--to);
2642 if (ctl & HDAC_SDCTL_SRST)
2643 device_printf(sc->dev, "can't reset!\n");
2644 }
2645
2646 static void
2647 hdac_stream_setid(struct hdac_chan *ch)
2648 {
2649 struct hdac_softc *sc = ch->devinfo->codec->sc;
2650 uint32_t ctl;
2651
2652 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
2653 ctl &= ~HDAC_SDCTL2_STRM_MASK;
2654 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
2655 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
2656 }
2657
2658 static void
2659 hdac_bdl_setup(struct hdac_chan *ch)
2660 {
2661 struct hdac_softc *sc = ch->devinfo->codec->sc;
2662 struct hdac_bdle *bdle;
2663 uint64_t addr;
2664 uint32_t blksz, blkcnt;
2665 int i;
2666
2667 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
2668 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
2669
2670 if (sc->polling != 0) {
2671 blksz = ch->blksz * ch->blkcnt;
2672 blkcnt = 1;
2673 } else {
2674 blksz = ch->blksz;
2675 blkcnt = ch->blkcnt;
2676 }
2677
2678 for (i = 0; i < blkcnt; i++, bdle++) {
2679 bdle->addrl = (uint32_t)addr;
2680 bdle->addrh = (uint32_t)(addr >> 32);
2681 bdle->len = blksz;
2682 bdle->ioc = 1 ^ sc->polling;
2683 addr += blksz;
2684 }
2685
2686 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
2687 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
2688 addr = ch->bdl_dma.dma_paddr;
2689 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
2690 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
2691 if (ch->dmapos != NULL &&
2692 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
2693 addr = sc->pos_dma.dma_paddr;
2694 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
2695 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
2696 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
2697 }
2698 }
2699
2700 static int
2701 hdac_bdl_alloc(struct hdac_chan *ch)
2702 {
2703 struct hdac_softc *sc = ch->devinfo->codec->sc;
2704 int rc;
2705
2706 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
2707 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
2708 if (rc) {
2709 device_printf(sc->dev, "can't alloc bdl\n");
2710 return (rc);
2711 }
2712
2713 return (0);
2714 }
2715
2716 static void
2717 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
2718 int index, int lmute, int rmute,
2719 int left, int right, int dir)
2720 {
2721 uint16_t v = 0;
2722
2723 if (sc == NULL)
2724 return;
2725
2726 if (left != right || lmute != rmute) {
2727 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
2728 (lmute << 7) | left;
2729 hdac_command(sc,
2730 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2731 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
2732 (rmute << 7) | right;
2733 } else
2734 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
2735 (lmute << 7) | left;
2736
2737 hdac_command(sc,
2738 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
2739 }
2740
2741 static void
2742 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
2743 int left, int right)
2744 {
2745 struct hdac_softc *sc;
2746 nid_t nid, cad;
2747 int lmute, rmute;
2748
2749 if (ctl == NULL || ctl->widget == NULL ||
2750 ctl->widget->devinfo == NULL ||
2751 ctl->widget->devinfo->codec == NULL ||
2752 ctl->widget->devinfo->codec->sc == NULL)
2753 return;
2754
2755 sc = ctl->widget->devinfo->codec->sc;
2756 cad = ctl->widget->devinfo->codec->cad;
2757 nid = ctl->widget->nid;
2758
2759 if (mute == HDA_AMP_MUTE_DEFAULT) {
2760 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
2761 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
2762 } else {
2763 lmute = HDA_AMP_LEFT_MUTED(mute);
2764 rmute = HDA_AMP_RIGHT_MUTED(mute);
2765 }
2766
2767 if (ctl->dir & HDA_CTL_OUT)
2768 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2769 lmute, rmute, left, right, 0);
2770 if (ctl->dir & HDA_CTL_IN)
2771 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
2772 lmute, rmute, left, right, 1);
2773 ctl->left = left;
2774 ctl->right = right;
2775 }
2776
2777 static void
2778 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
2779 {
2780 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
2781 return;
2782 hdac_command(w->devinfo->codec->sc,
2783 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
2784 w->nid, index), w->devinfo->codec->cad);
2785 w->selconn = index;
2786 }
2787
2788
2789 /****************************************************************************
2790 * uint32_t hdac_command_sendone_internal
2791 *
2792 * Wrapper function that sends only one command to a given codec
2793 ****************************************************************************/
2794 static uint32_t
2795 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
2796 {
2797 struct hdac_command_list cl;
2798 uint32_t response = HDAC_INVALID;
2799
2800 if (!hdac_lockowned(sc))
2801 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
2802 cl.num_commands = 1;
2803 cl.verbs = &verb;
2804 cl.responses = &response;
2805
2806 hdac_command_send_internal(sc, &cl, cad);
2807
2808 return (response);
2809 }
2810
2811 /****************************************************************************
2812 * hdac_command_send_internal
2813 *
2814 * Send a command list to the codec via the corb. We queue as much verbs as
2815 * we can and msleep on the codec. When the interrupt get the responses
2816 * back from the rirb, it will wake us up so we can queue the remaining verbs
2817 * if any.
2818 ****************************************************************************/
2819 static void
2820 hdac_command_send_internal(struct hdac_softc *sc,
2821 struct hdac_command_list *commands, nid_t cad)
2822 {
2823 struct hdac_codec *codec;
2824 int corbrp;
2825 uint32_t *corb;
2826 int timeout;
2827 int retry = 10;
2828 struct hdac_rirb *rirb_base;
2829
2830 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
2831 commands->num_commands < 1)
2832 return;
2833
2834 codec = sc->codecs[cad];
2835 codec->commands = commands;
2836 codec->responses_received = 0;
2837 codec->verbs_sent = 0;
2838 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
2839 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2840
2841 do {
2842 if (codec->verbs_sent != commands->num_commands) {
2843 /* Queue as many verbs as possible */
2844 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
2845 #if 0
2846 bus_dmamap_sync(sc->corb_dma.dma_tag,
2847 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
2848 #endif
2849 while (codec->verbs_sent != commands->num_commands &&
2850 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
2851 sc->corb_wp++;
2852 sc->corb_wp %= sc->corb_size;
2853 corb[sc->corb_wp] =
2854 commands->verbs[codec->verbs_sent++];
2855 }
2856
2857 /* Send the verbs to the codecs */
2858 #if 0
2859 bus_dmamap_sync(sc->corb_dma.dma_tag,
2860 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
2861 #endif
2862 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
2863 }
2864
2865 timeout = 1000;
2866 while (hdac_rirb_flush(sc) == 0 && --timeout)
2867 DELAY(10);
2868 } while ((codec->verbs_sent != commands->num_commands ||
2869 codec->responses_received != commands->num_commands) && --retry);
2870
2871 if (retry == 0)
2872 device_printf(sc->dev,
2873 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
2874 __func__, commands->num_commands, codec->verbs_sent,
2875 codec->responses_received);
2876
2877 codec->commands = NULL;
2878 codec->responses_received = 0;
2879 codec->verbs_sent = 0;
2880
2881 hdac_unsolq_flush(sc);
2882 }
2883
2884
2885 /****************************************************************************
2886 * Device Methods
2887 ****************************************************************************/
2888
2889 /****************************************************************************
2890 * int hdac_probe(device_t)
2891 *
2892 * Probe for the presence of an hdac. If none is found, check for a generic
2893 * match using the subclass of the device.
2894 ****************************************************************************/
2895 static int
2896 hdac_probe(device_t dev)
2897 {
2898 int i, result;
2899 uint32_t model;
2900 uint16_t class, subclass;
2901 char desc[64];
2902
2903 model = (uint32_t)pci_get_device(dev) << 16;
2904 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
2905 class = pci_get_class(dev);
2906 subclass = pci_get_subclass(dev);
2907
2908 bzero(desc, sizeof(desc));
2909 result = ENXIO;
2910 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
2911 if (hdac_devices[i].model == model) {
2912 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2913 result = BUS_PROBE_DEFAULT;
2914 break;
2915 }
2916 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
2917 class == PCIC_MULTIMEDIA &&
2918 subclass == PCIS_MULTIMEDIA_HDA) {
2919 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
2920 result = BUS_PROBE_GENERIC;
2921 break;
2922 }
2923 }
2924 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
2925 subclass == PCIS_MULTIMEDIA_HDA) {
2926 strlcpy(desc, "Generic", sizeof(desc));
2927 result = BUS_PROBE_GENERIC;
2928 }
2929 if (result != ENXIO) {
2930 strlcat(desc, " High Definition Audio Controller",
2931 sizeof(desc));
2932 device_set_desc_copy(dev, desc);
2933 }
2934
2935 return (result);
2936 }
2937
2938 static void *
2939 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
2940 struct pcm_channel *c, int dir)
2941 {
2942 struct hdac_devinfo *devinfo = data;
2943 struct hdac_softc *sc = devinfo->codec->sc;
2944 struct hdac_chan *ch;
2945
2946 hdac_lock(sc);
2947 if (dir == PCMDIR_PLAY) {
2948 ch = &sc->play;
2949 ch->off = (sc->num_iss + devinfo->function.audio.playcnt) << 5;
2950 devinfo->function.audio.playcnt++;
2951 } else {
2952 ch = &sc->rec;
2953 ch->off = devinfo->function.audio.reccnt << 5;
2954 devinfo->function.audio.reccnt++;
2955 }
2956 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
2957 ch->caps.minspeed = ch->caps.maxspeed = 48000;
2958 ch->pcmrates[0] = 48000;
2959 ch->pcmrates[1] = 0;
2960 }
2961 if (sc->pos_dma.dma_vaddr != NULL)
2962 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
2963 (sc->streamcnt * 8));
2964 else
2965 ch->dmapos = NULL;
2966 ch->sid = ++sc->streamcnt;
2967 ch->dir = dir;
2968 ch->b = b;
2969 ch->c = c;
2970 ch->devinfo = devinfo;
2971 ch->blksz = sc->chan_size / sc->chan_blkcnt;
2972 ch->blkcnt = sc->chan_blkcnt;
2973 hdac_unlock(sc);
2974
2975 if (hdac_bdl_alloc(ch) != 0) {
2976 ch->blkcnt = 0;
2977 return (NULL);
2978 }
2979
2980 if (sndbuf_alloc(ch->b, sc->chan_dmat, sc->chan_size) != 0)
2981 return (NULL);
2982
2983 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b), sndbuf_getmaxsize(ch->b),
2984 PAT_UNCACHEABLE);
2985
2986 return (ch);
2987 }
2988
2989 static int
2990 hdac_channel_free(kobj_t obj, void *data)
2991 {
2992 struct hdac_softc *sc;
2993 struct hdac_chan *ch;
2994
2995 ch = (struct hdac_chan *)data;
2996 sc = (ch != NULL && ch->devinfo != NULL && ch->devinfo->codec != NULL) ?
2997 ch->devinfo->codec->sc : NULL;
2998 if (ch != NULL && sc != NULL) {
2999 HDAC_DMA_ATTR(sc, sndbuf_getbuf(ch->b),
3000 sndbuf_getmaxsize(ch->b), PAT_WRITE_BACK);
3001 }
3002
3003 return (1);
3004 }
3005
3006 static int
3007 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3008 {
3009 struct hdac_chan *ch = data;
3010 int i;
3011
3012 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3013 if (format == ch->caps.fmtlist[i]) {
3014 ch->fmt = format;
3015 return (0);
3016 }
3017 }
3018
3019 return (EINVAL);
3020 }
3021
3022 static int
3023 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3024 {
3025 struct hdac_chan *ch = data;
3026 uint32_t spd = 0, threshold;
3027 int i;
3028
3029 for (i = 0; ch->pcmrates[i] != 0; i++) {
3030 spd = ch->pcmrates[i];
3031 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3032 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3033 if (speed < threshold)
3034 break;
3035 }
3036
3037 if (spd == 0) /* impossible */
3038 ch->spd = 48000;
3039 else
3040 ch->spd = spd;
3041
3042 return (ch->spd);
3043 }
3044
3045 static void
3046 hdac_stream_setup(struct hdac_chan *ch)
3047 {
3048 struct hdac_softc *sc = ch->devinfo->codec->sc;
3049 int i;
3050 nid_t cad = ch->devinfo->codec->cad;
3051 uint16_t fmt;
3052
3053 fmt = 0;
3054 if (ch->fmt & AFMT_S16_LE)
3055 fmt |= ch->bit16 << 4;
3056 else if (ch->fmt & AFMT_S32_LE)
3057 fmt |= ch->bit32 << 4;
3058 else
3059 fmt |= 1 << 4;
3060
3061 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3062 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3063 fmt |= hda_rate_tab[i].base;
3064 fmt |= hda_rate_tab[i].mul;
3065 fmt |= hda_rate_tab[i].div;
3066 break;
3067 }
3068 }
3069
3070 if (ch->fmt & AFMT_STEREO)
3071 fmt |= 1;
3072
3073 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3074
3075 for (i = 0; ch->io[i] != -1; i++) {
3076 HDA_BOOTVERBOSE(
3077 device_printf(sc->dev,
3078 "HDA_DEBUG: PCMDIR_%s: Stream setup nid=%d "
3079 "fmt=0x%08x\n",
3080 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3081 ch->io[i], fmt);
3082 );
3083 hdac_command(sc,
3084 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3085 hdac_command(sc,
3086 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3087 ch->sid << 4), cad);
3088 }
3089 }
3090
3091 static int
3092 hdac_channel_setfragments(kobj_t obj, void *data,
3093 uint32_t blksz, uint32_t blkcnt)
3094 {
3095 struct hdac_chan *ch = data;
3096 struct hdac_softc *sc = ch->devinfo->codec->sc;
3097
3098 blksz &= HDA_BLK_ALIGN;
3099
3100 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3101 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3102 if (blksz < HDA_BLK_MIN)
3103 blksz = HDA_BLK_MIN;
3104 if (blkcnt > HDA_BDL_MAX)
3105 blkcnt = HDA_BDL_MAX;
3106 if (blkcnt < HDA_BDL_MIN)
3107 blkcnt = HDA_BDL_MIN;
3108
3109 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3110 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3111 blkcnt >>= 1;
3112 else if ((blksz >> 1) >= HDA_BLK_MIN)
3113 blksz >>= 1;
3114 else
3115 break;
3116 }
3117
3118 if ((sndbuf_getblksz(ch->b) != blksz ||
3119 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3120 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3121 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3122 __func__, blksz, blkcnt);
3123
3124 ch->blksz = sndbuf_getblksz(ch->b);
3125 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3126
3127 return (1);
3128 }
3129
3130 static int
3131 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3132 {
3133 struct hdac_chan *ch = data;
3134 struct hdac_softc *sc = ch->devinfo->codec->sc;
3135
3136 hdac_channel_setfragments(obj, data, blksz, sc->chan_blkcnt);
3137
3138 return (ch->blksz);
3139 }
3140
3141 static void
3142 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3143 {
3144 struct hdac_devinfo *devinfo = ch->devinfo;
3145 nid_t cad = devinfo->codec->cad;
3146 int i;
3147
3148 hdac_stream_stop(ch);
3149
3150 for (i = 0; ch->io[i] != -1; i++) {
3151 hdac_command(sc,
3152 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3153 0), cad);
3154 }
3155 }
3156
3157 static void
3158 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3159 {
3160 ch->ptr = 0;
3161 ch->prevptr = 0;
3162 hdac_stream_stop(ch);
3163 hdac_stream_reset(ch);
3164 hdac_bdl_setup(ch);
3165 hdac_stream_setid(ch);
3166 hdac_stream_setup(ch);
3167 hdac_stream_start(ch);
3168 }
3169
3170 static int
3171 hdac_channel_trigger(kobj_t obj, void *data, int go)
3172 {
3173 struct hdac_chan *ch = data;
3174 struct hdac_softc *sc = ch->devinfo->codec->sc;
3175
3176 if (!(go == PCMTRIG_START || go == PCMTRIG_STOP || go == PCMTRIG_ABORT))
3177 return (0);
3178
3179 hdac_lock(sc);
3180 switch (go) {
3181 case PCMTRIG_START:
3182 hdac_channel_start(sc, ch);
3183 break;
3184 case PCMTRIG_STOP:
3185 case PCMTRIG_ABORT:
3186 hdac_channel_stop(sc, ch);
3187 break;
3188 default:
3189 break;
3190 }
3191 hdac_unlock(sc);
3192
3193 return (0);
3194 }
3195
3196 static int
3197 hdac_channel_getptr(kobj_t obj, void *data)
3198 {
3199 struct hdac_chan *ch = data;
3200 struct hdac_softc *sc = ch->devinfo->codec->sc;
3201 uint32_t ptr;
3202
3203 hdac_lock(sc);
3204 if (sc->polling != 0)
3205 ptr = ch->ptr;
3206 else if (ch->dmapos != NULL)
3207 ptr = *(ch->dmapos);
3208 else
3209 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3210 hdac_unlock(sc);
3211
3212 /*
3213 * Round to available space and force 128 bytes aligment.
3214 */
3215 ptr %= ch->blksz * ch->blkcnt;
3216 ptr &= HDA_BLK_ALIGN;
3217
3218 return (ptr);
3219 }
3220
3221 static struct pcmchan_caps *
3222 hdac_channel_getcaps(kobj_t obj, void *data)
3223 {
3224 return (&((struct hdac_chan *)data)->caps);
3225 }
3226
3227 static kobj_method_t hdac_channel_methods[] = {
3228 KOBJMETHOD(channel_init, hdac_channel_init),
3229 KOBJMETHOD(channel_free, hdac_channel_free),
3230 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3231 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3232 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3233 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3234 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3235 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3236 { 0, 0 }
3237 };
3238 CHANNEL_DECLARE(hdac_channel);
3239
3240 static void
3241 hdac_jack_poll_callback(void *arg)
3242 {
3243 struct hdac_devinfo *devinfo = arg;
3244 struct hdac_softc *sc;
3245
3246 if (devinfo == NULL || devinfo->codec == NULL ||
3247 devinfo->codec->sc == NULL)
3248 return;
3249 sc = devinfo->codec->sc;
3250 hdac_lock(sc);
3251 if (sc->poll_ival == 0) {
3252 hdac_unlock(sc);
3253 return;
3254 }
3255 hdac_hp_switch_handler(devinfo);
3256 callout_reset(&sc->poll_jack, sc->poll_ival,
3257 hdac_jack_poll_callback, devinfo);
3258 hdac_unlock(sc);
3259 }
3260
3261 static int
3262 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3263 {
3264 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3265 struct hdac_softc *sc = devinfo->codec->sc;
3266 struct hdac_widget *w, *cw;
3267 struct hdac_audio_ctl *ctl;
3268 uint32_t mask, recmask, id;
3269 int i, j, softpcmvol;
3270 nid_t cad;
3271
3272 hdac_lock(sc);
3273
3274 mask = 0;
3275 recmask = 0;
3276
3277 id = hdac_codec_id(devinfo);
3278 cad = devinfo->codec->cad;
3279 for (i = 0; i < HDAC_HP_SWITCH_LEN; i++) {
3280 if (!(HDA_DEV_MATCH(hdac_hp_switch[i].model,
3281 sc->pci_subvendor) && hdac_hp_switch[i].id == id))
3282 continue;
3283 w = hdac_widget_get(devinfo, hdac_hp_switch[i].hpnid);
3284 if (w == NULL || w->enable == 0 || w->type !=
3285 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
3286 continue;
3287 if (hdac_hp_switch[i].polling != 0)
3288 callout_reset(&sc->poll_jack, 1,
3289 hdac_jack_poll_callback, devinfo);
3290 else if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
3291 hdac_command(sc,
3292 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
3293 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
3294 HDAC_UNSOLTAG_EVENT_HP), cad);
3295 else
3296 continue;
3297 hdac_hp_switch_handler(devinfo);
3298 HDA_BOOTVERBOSE(
3299 device_printf(sc->dev,
3300 "HDA_DEBUG: Enabling headphone/speaker "
3301 "audio routing switching:\n");
3302 device_printf(sc->dev,
3303 "HDA_DEBUG: \tindex=%d nid=%d "
3304 "pci_subvendor=0x%08x "
3305 "codec=0x%08x [%s]\n",
3306 i, w->nid, sc->pci_subvendor, id,
3307 (hdac_hp_switch[i].polling != 0) ? "POLL" :
3308 "UNSOL");
3309 );
3310 break;
3311 }
3312 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3313 if (!(HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3314 sc->pci_subvendor) &&
3315 hdac_eapd_switch[i].id == id))
3316 continue;
3317 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3318 if (w == NULL || w->enable == 0)
3319 break;
3320 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3321 w->param.eapdbtl == HDAC_INVALID)
3322 break;
3323 mask |= SOUND_MASK_OGAIN;
3324 break;
3325 }
3326
3327 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3328 w = hdac_widget_get(devinfo, i);
3329 if (w == NULL || w->enable == 0)
3330 continue;
3331 mask |= w->ctlflags;
3332 if (!(w->pflags & HDA_ADC_RECSEL))
3333 continue;
3334 for (j = 0; j < w->nconns; j++) {
3335 cw = hdac_widget_get(devinfo, w->conns[j]);
3336 if (cw == NULL || cw->enable == 0)
3337 continue;
3338 recmask |= cw->ctlflags;
3339 }
3340 }
3341
3342 if (!(mask & SOUND_MASK_PCM)) {
3343 softpcmvol = 1;
3344 mask |= SOUND_MASK_PCM;
3345 } else
3346 softpcmvol = (devinfo->function.audio.quirks &
3347 HDA_QUIRK_SOFTPCMVOL) ? 1 : 0;
3348
3349 i = 0;
3350 ctl = NULL;
3351 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3352 if (ctl->widget == NULL || ctl->enable == 0)
3353 continue;
3354 if (!(ctl->ossmask & SOUND_MASK_PCM))
3355 continue;
3356 if (ctl->step > 0)
3357 break;
3358 }
3359
3360 if (softpcmvol == 1 || ctl == NULL) {
3361 pcm_setflags(sc->dev, pcm_getflags(sc->dev) | SD_F_SOFTPCMVOL);
3362 HDA_BOOTVERBOSE(
3363 device_printf(sc->dev,
3364 "HDA_DEBUG: %s Soft PCM volume\n",
3365 (softpcmvol == 1) ?
3366 "Forcing" : "Enabling");
3367 );
3368 i = 0;
3369 /*
3370 * XXX Temporary quirk for STAC9220, until the parser
3371 * become smarter.
3372 */
3373 if (id == HDA_CODEC_STAC9220) {
3374 mask |= SOUND_MASK_VOLUME;
3375 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3376 NULL) {
3377 if (ctl->widget == NULL || ctl->enable == 0)
3378 continue;
3379 if (ctl->widget->nid == 11 && ctl->index == 0) {
3380 ctl->ossmask = SOUND_MASK_VOLUME;
3381 ctl->ossval = 100 | (100 << 8);
3382 } else
3383 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3384 }
3385 } else if (id == HDA_CODEC_STAC9221) {
3386 mask |= SOUND_MASK_VOLUME;
3387 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3388 NULL) {
3389 if (ctl->widget == NULL)
3390 continue;
3391 if (ctl->widget->type ==
3392 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
3393 ctl->index == 0 && (ctl->widget->nid == 2 ||
3394 ctl->widget->enable != 0)) {
3395 ctl->enable = 1;
3396 ctl->ossmask = SOUND_MASK_VOLUME;
3397 ctl->ossval = 100 | (100 << 8);
3398 } else if (ctl->enable == 0)
3399 continue;
3400 else
3401 ctl->ossmask &= ~SOUND_MASK_VOLUME;
3402 }
3403 } else {
3404 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3405 SOUND_MASK_PCM);
3406 if (!(mask & SOUND_MASK_VOLUME))
3407 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3408 SOUND_MIXER_NONE);
3409 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) !=
3410 NULL) {
3411 if (ctl->widget == NULL || ctl->enable == 0)
3412 continue;
3413 if (!HDA_FLAG_MATCH(ctl->ossmask,
3414 SOUND_MASK_VOLUME | SOUND_MASK_PCM))
3415 continue;
3416 if (!(ctl->mute == 1 && ctl->step == 0))
3417 ctl->enable = 0;
3418 }
3419 }
3420 }
3421
3422 recmask &= ~(SOUND_MASK_PCM | SOUND_MASK_RECLEV | SOUND_MASK_SPEAKER |
3423 SOUND_MASK_BASS | SOUND_MASK_TREBLE | SOUND_MASK_IGAIN |
3424 SOUND_MASK_OGAIN);
3425 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3426 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3427
3428 mix_setrecdevs(m, recmask);
3429 mix_setdevs(m, mask);
3430
3431 hdac_unlock(sc);
3432
3433 return (0);
3434 }
3435
3436 static int
3437 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3438 unsigned left, unsigned right)
3439 {
3440 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3441 struct hdac_softc *sc = devinfo->codec->sc;
3442 struct hdac_widget *w;
3443 struct hdac_audio_ctl *ctl;
3444 uint32_t id, mute;
3445 int lvol, rvol, mlvol, mrvol;
3446 int i = 0;
3447
3448 hdac_lock(sc);
3449 if (dev == SOUND_MIXER_OGAIN) {
3450 uint32_t orig;
3451 /*if (left != right || !(left == 0 || left == 1)) {
3452 hdac_unlock(sc);
3453 return (-1);
3454 }*/
3455 id = hdac_codec_id(devinfo);
3456 for (i = 0; i < HDAC_EAPD_SWITCH_LEN; i++) {
3457 if (HDA_DEV_MATCH(hdac_eapd_switch[i].model,
3458 sc->pci_subvendor) &&
3459 hdac_eapd_switch[i].id == id)
3460 break;
3461 }
3462 if (i >= HDAC_EAPD_SWITCH_LEN) {
3463 hdac_unlock(sc);
3464 return (-1);
3465 }
3466 w = hdac_widget_get(devinfo, hdac_eapd_switch[i].eapdnid);
3467 if (w == NULL ||
3468 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3469 w->param.eapdbtl == HDAC_INVALID) {
3470 hdac_unlock(sc);
3471 return (-1);
3472 }
3473 orig = w->param.eapdbtl;
3474 if (left == 0)
3475 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3476 else
3477 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3478 if (orig != w->param.eapdbtl) {
3479 uint32_t val;
3480
3481 if (hdac_eapd_switch[i].hp_switch != 0)
3482 hdac_hp_switch_handler(devinfo);
3483 val = w->param.eapdbtl;
3484 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3485 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3486 hdac_command(sc,
3487 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3488 w->nid, val), devinfo->codec->cad);
3489 }
3490 hdac_unlock(sc);
3491 return (left | (left << 8));
3492 }
3493 if (dev == SOUND_MIXER_VOLUME)
3494 devinfo->function.audio.mvol = left | (right << 8);
3495
3496 mlvol = devinfo->function.audio.mvol & 0x7f;
3497 mrvol = (devinfo->function.audio.mvol >> 8) & 0x7f;
3498 lvol = 0;
3499 rvol = 0;
3500
3501 i = 0;
3502 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3503 if (ctl->widget == NULL || ctl->enable == 0 ||
3504 !(ctl->ossmask & (1 << dev)))
3505 continue;
3506 switch (dev) {
3507 case SOUND_MIXER_VOLUME:
3508 lvol = ((ctl->ossval & 0x7f) * left) / 100;
3509 lvol = (lvol * ctl->step) / 100;
3510 rvol = (((ctl->ossval >> 8) & 0x7f) * right) / 100;
3511 rvol = (rvol * ctl->step) / 100;
3512 break;
3513 default:
3514 if (ctl->ossmask & SOUND_MASK_VOLUME) {
3515 lvol = (left * mlvol) / 100;
3516 lvol = (lvol * ctl->step) / 100;
3517 rvol = (right * mrvol) / 100;
3518 rvol = (rvol * ctl->step) / 100;
3519 } else {
3520 lvol = (left * ctl->step) / 100;
3521 rvol = (right * ctl->step) / 100;
3522 }
3523 ctl->ossval = left | (right << 8);
3524 break;
3525 }
3526 mute = 0;
3527 if (ctl->step < 1) {
3528 mute |= (left == 0) ? HDA_AMP_MUTE_LEFT :
3529 (ctl->muted & HDA_AMP_MUTE_LEFT);
3530 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT :
3531 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3532 } else {
3533 mute |= (lvol == 0) ? HDA_AMP_MUTE_LEFT :
3534 (ctl->muted & HDA_AMP_MUTE_LEFT);
3535 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT :
3536 (ctl->muted & HDA_AMP_MUTE_RIGHT);
3537 }
3538 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
3539 }
3540 hdac_unlock(sc);
3541
3542 return (left | (right << 8));
3543 }
3544
3545 static int
3546 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
3547 {
3548 struct hdac_devinfo *devinfo = mix_getdevinfo(m);
3549 struct hdac_widget *w, *cw;
3550 struct hdac_softc *sc = devinfo->codec->sc;
3551 uint32_t ret = src, target;
3552 int i, j;
3553
3554 target = 0;
3555 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3556 if (src & (1 << i)) {
3557 target = 1 << i;
3558 break;
3559 }
3560 }
3561
3562 hdac_lock(sc);
3563
3564 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3565 w = hdac_widget_get(devinfo, i);
3566 if (w == NULL || w->enable == 0)
3567 continue;
3568 if (!(w->pflags & HDA_ADC_RECSEL))
3569 continue;
3570 for (j = 0; j < w->nconns; j++) {
3571 cw = hdac_widget_get(devinfo, w->conns[j]);
3572 if (cw == NULL || cw->enable == 0)
3573 continue;
3574 if ((target == SOUND_MASK_VOLUME &&
3575 cw->type !=
3576 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
3577 (target != SOUND_MASK_VOLUME &&
3578 cw->type ==
3579 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER))
3580 continue;
3581 if (cw->ctlflags & target) {
3582 if (!(w->pflags & HDA_ADC_LOCKED))
3583 hdac_widget_connection_select(w, j);
3584 ret = target;
3585 j += w->nconns;
3586 }
3587 }
3588 }
3589
3590 hdac_unlock(sc);
3591
3592 return (ret);
3593 }
3594
3595 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
3596 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
3597 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
3598 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
3599 { 0, 0 }
3600 };
3601 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
3602
3603 /****************************************************************************
3604 * int hdac_attach(device_t)
3605 *
3606 * Attach the device into the kernel. Interrupts usually won't be enabled
3607 * when this function is called. Setup everything that doesn't require
3608 * interrupts and defer probing of codecs until interrupts are enabled.
3609 ****************************************************************************/
3610 static int
3611 hdac_attach(device_t dev)
3612 {
3613 struct hdac_softc *sc;
3614 int result;
3615 int i;
3616 uint16_t vendor;
3617 uint8_t v;
3618
3619 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
3620 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
3621 sc->dev = dev;
3622 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
3623 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
3624 vendor = pci_get_vendor(dev);
3625
3626 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
3627 /* Screw nx6325 - subdevice/subvendor swapped */
3628 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
3629 }
3630
3631 callout_init(&sc->poll_hda);
3632 callout_init(&sc->poll_hdac);
3633 callout_init(&sc->poll_jack);
3634
3635 sc->poll_ticks = 1;
3636 sc->poll_ival = HDAC_POLL_INTERVAL;
3637 if (resource_int_value(device_get_name(dev),
3638 device_get_unit(dev), "polling", &i) == 0 && i != 0)
3639 sc->polling = 1;
3640 else
3641 sc->polling = 0;
3642
3643 sc->chan_size = pcm_getbuffersize(dev,
3644 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
3645
3646 if (resource_int_value(device_get_name(dev),
3647 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
3648 i &= HDA_BLK_ALIGN;
3649 if (i < HDA_BLK_MIN)
3650 i = HDA_BLK_MIN;
3651 sc->chan_blkcnt = sc->chan_size / i;
3652 i = 0;
3653 while (sc->chan_blkcnt >> i)
3654 i++;
3655 sc->chan_blkcnt = 1 << (i - 1);
3656 if (sc->chan_blkcnt < HDA_BDL_MIN)
3657 sc->chan_blkcnt = HDA_BDL_MIN;
3658 else if (sc->chan_blkcnt > HDA_BDL_MAX)
3659 sc->chan_blkcnt = HDA_BDL_MAX;
3660 } else
3661 sc->chan_blkcnt = HDA_BDL_DEFAULT;
3662
3663 result = bus_dma_tag_create(NULL, /* parent */
3664 HDAC_DMA_ALIGNMENT, /* alignment */
3665 0, /* boundary */
3666 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3667 BUS_SPACE_MAXADDR, /* highaddr */
3668 NULL, /* filtfunc */
3669 NULL, /* fistfuncarg */
3670 sc->chan_size, /* maxsize */
3671 1, /* nsegments */
3672 sc->chan_size, /* maxsegsz */
3673 0, /* flags */
3674 &sc->chan_dmat); /* dmat */
3675 if (result != 0) {
3676 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
3677 __func__, result);
3678 snd_mtxfree(sc->lock);
3679 kfree(sc, M_DEVBUF);
3680 return (ENXIO);
3681 }
3682
3683
3684 sc->hdabus = NULL;
3685 for (i = 0; i < HDAC_CODEC_MAX; i++)
3686 sc->codecs[i] = NULL;
3687
3688 pci_enable_busmaster(dev);
3689
3690 if (vendor == INTEL_VENDORID) {
3691 /* TCSEL -> TC0 */
3692 v = pci_read_config(dev, 0x44, 1);
3693 pci_write_config(dev, 0x44, v & 0xf8, 1);
3694 HDA_BOOTVERBOSE(
3695 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
3696 pci_read_config(dev, 0x44, 1));
3697 );
3698 }
3699
3700 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3701 sc->nocache = 1;
3702
3703 if (resource_int_value(device_get_name(dev),
3704 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
3705 #else
3706 sc->nocache = 0;
3707 #endif
3708 /*
3709 * Try to enable PCIe snoop to avoid messing around with
3710 * uncacheable DMA attribute. Since PCIe snoop register
3711 * config is pretty much vendor specific, there are no
3712 * general solutions on how to enable it, forcing us (even
3713 * Microsoft) to enable uncacheable or write combined DMA
3714 * by default.
3715 *
3716 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
3717 */
3718 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
3719 if (hdac_pcie_snoop[i].vendor != vendor)
3720 continue;
3721 sc->nocache = 0;
3722 if (hdac_pcie_snoop[i].reg == 0x00)
3723 break;
3724 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3725 if ((v & hdac_pcie_snoop[i].enable) ==
3726 hdac_pcie_snoop[i].enable)
3727 break;
3728 v &= hdac_pcie_snoop[i].mask;
3729 v |= hdac_pcie_snoop[i].enable;
3730 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
3731 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
3732 if ((v & hdac_pcie_snoop[i].enable) !=
3733 hdac_pcie_snoop[i].enable) {
3734 HDA_BOOTVERBOSE(
3735 device_printf(dev,
3736 "WARNING: Failed to enable PCIe "
3737 "snoop!\n");
3738 );
3739 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3740 sc->nocache = 1;
3741 #endif
3742 }
3743 break;
3744 }
3745 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
3746 }
3747 #endif
3748
3749 HDA_BOOTVERBOSE(
3750 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
3751 (sc->nocache == 0) ? "PCIe snoop" : "Uncacheable", vendor);
3752 );
3753
3754 /* Allocate resources */
3755 result = hdac_mem_alloc(sc);
3756 if (result != 0)
3757 goto hdac_attach_fail;
3758 result = hdac_irq_alloc(sc);
3759 if (result != 0)
3760 goto hdac_attach_fail;
3761
3762 /* Get Capabilities */
3763 result = hdac_get_capabilities(sc);
3764 if (result != 0)
3765 goto hdac_attach_fail;
3766
3767 /* Allocate CORB and RIRB dma memory */
3768 result = hdac_dma_alloc(sc, &sc->corb_dma,
3769 sc->corb_size * sizeof(uint32_t));
3770 if (result != 0)
3771 goto hdac_attach_fail;
3772 result = hdac_dma_alloc(sc, &sc->rirb_dma,
3773 sc->rirb_size * sizeof(struct hdac_rirb));
3774 if (result != 0)
3775 goto hdac_attach_fail;
3776
3777 /* Quiesce everything */
3778 hdac_reset(sc);
3779
3780 /* Initialize the CORB and RIRB */
3781 hdac_corb_init(sc);
3782 hdac_rirb_init(sc);
3783
3784 /* Defer remaining of initialization until interrupts are enabled */
3785 sc->intrhook.ich_func = hdac_attach2;
3786 sc->intrhook.ich_arg = (void *)sc;
3787 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
3788 sc->intrhook.ich_func = NULL;
3789 hdac_attach2((void *)sc);
3790 }
3791
3792 return (0);
3793
3794 hdac_attach_fail:
3795 hdac_irq_free(sc);
3796 hdac_dma_free(sc, &sc->rirb_dma);
3797 hdac_dma_free(sc, &sc->corb_dma);
3798 hdac_mem_free(sc);
3799 snd_mtxfree(sc->lock);
3800 kfree(sc, M_DEVBUF);
3801
3802 return (ENXIO);
3803 }
3804
3805 static void
3806 hdac_audio_parse(struct hdac_devinfo *devinfo)
3807 {
3808 struct hdac_softc *sc = devinfo->codec->sc;
3809 struct hdac_widget *w;
3810 uint32_t res;
3811 int i;
3812 nid_t cad, nid;
3813
3814 cad = devinfo->codec->cad;
3815 nid = devinfo->nid;
3816
3817 hdac_command(sc,
3818 HDA_CMD_SET_POWER_STATE(cad, nid, HDA_CMD_POWER_STATE_D0), cad);
3819
3820 DELAY(100);
3821
3822 res = hdac_command(sc,
3823 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
3824
3825 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
3826 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
3827 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
3828
3829 res = hdac_command(sc,
3830 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
3831 devinfo->function.audio.gpio = res;
3832
3833 HDA_BOOTVERBOSE(
3834 device_printf(sc->dev, " Vendor: 0x%08x\n",
3835 devinfo->vendor_id);
3836 device_printf(sc->dev, " Device: 0x%08x\n",
3837 devinfo->device_id);
3838 device_printf(sc->dev, " Revision: 0x%08x\n",
3839 devinfo->revision_id);
3840 device_printf(sc->dev, " Stepping: 0x%08x\n",
3841 devinfo->stepping_id);
3842 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
3843 sc->pci_subvendor);
3844 device_printf(sc->dev, " Nodes: start=%d "
3845 "endnode=%d total=%d\n",
3846 devinfo->startnode, devinfo->endnode, devinfo->nodecnt);
3847 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size);
3848 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size);
3849 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n",
3850 sc->num_iss, sc->num_oss, sc->num_bss);
3851 device_printf(sc->dev, " GPIO: 0x%08x\n",
3852 devinfo->function.audio.gpio);
3853 device_printf(sc->dev, " NumGPIO=%d NumGPO=%d "
3854 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
3855 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
3856 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
3857 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
3858 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
3859 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
3860 );
3861
3862 res = hdac_command(sc,
3863 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
3864 cad);
3865 devinfo->function.audio.supp_stream_formats = res;
3866
3867 res = hdac_command(sc,
3868 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
3869 cad);
3870 devinfo->function.audio.supp_pcm_size_rate = res;
3871
3872 res = hdac_command(sc,
3873 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
3874 cad);
3875 devinfo->function.audio.outamp_cap = res;
3876
3877 res = hdac_command(sc,
3878 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
3879 cad);
3880 devinfo->function.audio.inamp_cap = res;
3881
3882 if (devinfo->nodecnt > 0)
3883 devinfo->widget = (struct hdac_widget *)kmalloc(
3884 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
3885 M_NOWAIT | M_ZERO);
3886 else
3887 devinfo->widget = NULL;
3888
3889 if (devinfo->widget == NULL) {
3890 device_printf(sc->dev, "unable to allocate widgets!\n");
3891 devinfo->endnode = devinfo->startnode;
3892 devinfo->nodecnt = 0;
3893 return;
3894 }
3895
3896 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3897 w = hdac_widget_get(devinfo, i);
3898 if (w == NULL)
3899 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
3900 else {
3901 w->devinfo = devinfo;
3902 w->nid = i;
3903 w->enable = 1;
3904 w->selconn = -1;
3905 w->pflags = 0;
3906 w->ctlflags = 0;
3907 w->param.eapdbtl = HDAC_INVALID;
3908 hdac_widget_parse(w);
3909 }
3910 }
3911 }
3912
3913 static void
3914 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
3915 {
3916 struct hdac_softc *sc = devinfo->codec->sc;
3917 struct hdac_audio_ctl *ctls;
3918 struct hdac_widget *w, *cw;
3919 int i, j, cnt, max, ocap, icap;
3920 int mute, offset, step, size;
3921
3922 /* XXX This is redundant */
3923 max = 0;
3924 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3925 w = hdac_widget_get(devinfo, i);
3926 if (w == NULL || w->enable == 0)
3927 continue;
3928 if (w->param.outamp_cap != 0)
3929 max++;
3930 if (w->param.inamp_cap != 0) {
3931 switch (w->type) {
3932 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
3933 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
3934 for (j = 0; j < w->nconns; j++) {
3935 cw = hdac_widget_get(devinfo,
3936 w->conns[j]);
3937 if (cw == NULL || cw->enable == 0)
3938 continue;
3939 max++;
3940 }
3941 break;
3942 default:
3943 max++;
3944 break;
3945 }
3946 }
3947 }
3948
3949 devinfo->function.audio.ctlcnt = max;
3950
3951 if (max < 1)
3952 return;
3953
3954 ctls = (struct hdac_audio_ctl *)kmalloc(
3955 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
3956
3957 if (ctls == NULL) {
3958 /* Blekh! */
3959 device_printf(sc->dev, "unable to allocate ctls!\n");
3960 devinfo->function.audio.ctlcnt = 0;
3961 return;
3962 }
3963
3964 cnt = 0;
3965 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
3966 if (cnt >= max) {
3967 device_printf(sc->dev, "%s: Ctl overflow!\n",
3968 __func__);
3969 break;
3970 }
3971 w = hdac_widget_get(devinfo, i);
3972 if (w == NULL || w->enable == 0)
3973 continue;
3974 ocap = w->param.outamp_cap;
3975 icap = w->param.inamp_cap;
3976 if (ocap != 0) {
3977 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
3978 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
3979 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
3980 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
3981 /*if (offset > step) {
3982 HDA_BOOTVERBOSE(
3983 device_printf(sc->dev,
3984 "HDA_DEBUG: BUGGY outamp: nid=%d "
3985 "[offset=%d > step=%d]\n",
3986 w->nid, offset, step);
3987 );
3988 offset = step;
3989 }*/
3990 ctls[cnt].enable = 1;
3991 ctls[cnt].widget = w;
3992 ctls[cnt].mute = mute;
3993 ctls[cnt].step = step;
3994 ctls[cnt].size = size;
3995 ctls[cnt].offset = offset;
3996 ctls[cnt].left = offset;
3997 ctls[cnt].right = offset;
3998 ctls[cnt++].dir = HDA_CTL_OUT;
3999 }
4000
4001 if (icap != 0) {
4002 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4003 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4004 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4005 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4006 /*if (offset > step) {
4007 HDA_BOOTVERBOSE(
4008 device_printf(sc->dev,
4009 "HDA_DEBUG: BUGGY inamp: nid=%d "
4010 "[offset=%d > step=%d]\n",
4011 w->nid, offset, step);
4012 );
4013 offset = step;
4014 }*/
4015 switch (w->type) {
4016 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4017 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4018 for (j = 0; j < w->nconns; j++) {
4019 if (cnt >= max) {
4020 device_printf(sc->dev,
4021 "%s: Ctl overflow!\n",
4022 __func__);
4023 break;
4024 }
4025 cw = hdac_widget_get(devinfo,
4026 w->conns[j]);
4027 if (cw == NULL || cw->enable == 0)
4028 continue;
4029 ctls[cnt].enable = 1;
4030 ctls[cnt].widget = w;
4031 ctls[cnt].childwidget = cw;
4032 ctls[cnt].index = j;
4033 ctls[cnt].mute = mute;
4034 ctls[cnt].step = step;
4035 ctls[cnt].size = size;
4036 ctls[cnt].offset = offset;
4037 ctls[cnt].left = offset;
4038 ctls[cnt].right = offset;
4039 ctls[cnt++].dir = HDA_CTL_IN;
4040 }
4041 break;
4042 default:
4043 if (cnt >= max) {
4044 device_printf(sc->dev,
4045 "%s: Ctl overflow!\n",
4046 __func__);
4047 break;
4048 }
4049 ctls[cnt].enable = 1;
4050 ctls[cnt].widget = w;
4051 ctls[cnt].mute = mute;
4052 ctls[cnt].step = step;
4053 ctls[cnt].size = size;
4054 ctls[cnt].offset = offset;
4055 ctls[cnt].left = offset;
4056 ctls[cnt].right = offset;
4057 ctls[cnt++].dir = HDA_CTL_IN;
4058 break;
4059 }
4060 }
4061 }
4062
4063 devinfo->function.audio.ctl = ctls;
4064 }
4065
4066 static const struct {
4067 uint32_t model;
4068 uint32_t id;
4069 uint32_t set, unset;
4070 } hdac_quirks[] = {
4071 /*
4072 * XXX Force stereo quirk. Monoural recording / playback
4073 * on few codecs (especially ALC880) seems broken or
4074 * perhaps unsupported.
4075 */
4076 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4077 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4078 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4079 HDA_QUIRK_GPIO0, 0 },
4080 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4081 HDA_QUIRK_GPIO0, 0 },
4082 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4083 HDA_QUIRK_GPIO0, 0 },
4084 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4085 HDA_QUIRK_GPIO0, 0 },
4086 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4087 HDA_QUIRK_GPIO0, 0 },
4088 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4089 HDA_QUIRK_EAPDINV, 0 },
4090 { ASUS_A8JC_SUBVENDOR, HDA_CODEC_AD1986A,
4091 HDA_QUIRK_EAPDINV, 0 },
4092 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4093 HDA_QUIRK_OVREF, 0 },
4094 { ASUS_W6F_SUBVENDOR, HDA_CODEC_ALC861,
4095 HDA_QUIRK_OVREF, 0 },
4096 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4097 HDA_QUIRK_OVREF, 0 },
4098 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4099 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4100 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4101 HDA_QUIRK_GPIO1, 0 },
4102 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4103 HDA_QUIRK_EAPDINV, 0 },
4104 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4105 HDA_QUIRK_EAPDINV, 0 },
4106 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4107 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4108 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4109 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4110 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4111 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4112 { HDA_MATCH_ALL, HDA_CODEC_CXVENICE,
4113 0, HDA_QUIRK_FORCESTEREO },
4114 { HDA_MATCH_ALL, HDA_CODEC_STACXXXX,
4115 HDA_QUIRK_SOFTPCMVOL, 0 }
4116 };
4117 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4118
4119 static void
4120 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4121 {
4122 struct hdac_widget *w;
4123 struct hdac_audio_ctl *ctl;
4124 uint32_t id, subvendor;
4125 int i;
4126
4127 id = hdac_codec_id(devinfo);
4128 subvendor = devinfo->codec->sc->pci_subvendor;
4129
4130 /*
4131 * Quirks
4132 */
4133 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4134 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4135 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4136 continue;
4137 if (hdac_quirks[i].set != 0)
4138 devinfo->function.audio.quirks |=
4139 hdac_quirks[i].set;
4140 if (hdac_quirks[i].unset != 0)
4141 devinfo->function.audio.quirks &=
4142 ~(hdac_quirks[i].unset);
4143 }
4144
4145 switch (id) {
4146 case HDA_CODEC_ALC260:
4147 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4148 w = hdac_widget_get(devinfo, i);
4149 if (w == NULL || w->enable == 0)
4150 continue;
4151 if (w->type !=
4152 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4153 continue;
4154 if (w->nid != 5)
4155 w->enable = 0;
4156 }
4157 if (subvendor == HP_XW4300_SUBVENDOR) {
4158 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4159 if (ctl != NULL && ctl->widget != NULL) {
4160 ctl->ossmask = SOUND_MASK_SPEAKER;
4161 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4162 }
4163 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4164 if (ctl != NULL && ctl->widget != NULL) {
4165 ctl->ossmask = SOUND_MASK_SPEAKER;
4166 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4167 }
4168 } else if (subvendor == HP_3010_SUBVENDOR) {
4169 ctl = hdac_audio_ctl_amp_get(devinfo, 17, 0, 1);
4170 if (ctl != NULL && ctl->widget != NULL) {
4171 ctl->ossmask = SOUND_MASK_SPEAKER;
4172 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4173 }
4174 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 0, 1);
4175 if (ctl != NULL && ctl->widget != NULL) {
4176 ctl->ossmask = SOUND_MASK_SPEAKER;
4177 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4178 }
4179 }
4180 break;
4181 case HDA_CODEC_ALC861:
4182 ctl = hdac_audio_ctl_amp_get(devinfo, 21, 2, 1);
4183 if (ctl != NULL)
4184 ctl->muted = HDA_AMP_MUTE_ALL;
4185 break;
4186 case HDA_CODEC_ALC880:
4187 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4188 w = hdac_widget_get(devinfo, i);
4189 if (w == NULL || w->enable == 0)
4190 continue;
4191 if (w->type ==
4192 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4193 w->nid != 9 && w->nid != 29) {
4194 w->enable = 0;
4195 } else if (w->type !=
4196 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET &&
4197 w->nid == 29) {
4198 w->type =
4199 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET;
4200 w->param.widget_cap &=
4201 ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
4202 w->param.widget_cap |=
4203 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
4204 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
4205 strlcpy(w->name, "beep widget", sizeof(w->name));
4206 }
4207 }
4208 break;
4209 case HDA_CODEC_ALC883:
4210 /*
4211 * nid: 24/25 = External (jack) or Internal (fixed) Mic.
4212 * Clear vref cap for jack connectivity.
4213 */
4214 w = hdac_widget_get(devinfo, 24);
4215 if (w != NULL && w->enable != 0 && w->type ==
4216 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4217 (w->wclass.pin.config &
4218 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4219 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4220 w->wclass.pin.cap &= ~(
4221 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4222 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4223 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4224 w = hdac_widget_get(devinfo, 25);
4225 if (w != NULL && w->enable != 0 && w->type ==
4226 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4227 (w->wclass.pin.config &
4228 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
4229 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
4230 w->wclass.pin.cap &= ~(
4231 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK |
4232 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK |
4233 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK);
4234 /*
4235 * nid: 26 = Line-in, leave it alone.
4236 */
4237 break;
4238 case HDA_CODEC_AD1981HD:
4239 w = hdac_widget_get(devinfo, 11);
4240 if (w != NULL && w->enable != 0 && w->nconns > 3)
4241 w->selconn = 3;
4242 if (subvendor == IBM_M52_SUBVENDOR) {
4243 ctl = hdac_audio_ctl_amp_get(devinfo, 7, 0, 1);
4244 if (ctl != NULL)
4245 ctl->ossmask = SOUND_MASK_SPEAKER;
4246 }
4247 break;
4248 case HDA_CODEC_AD1986A:
4249 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4250 w = hdac_widget_get(devinfo, i);
4251 if (w == NULL || w->enable == 0)
4252 continue;
4253 if (w->type !=
4254 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4255 continue;
4256 if (w->nid != 3)
4257 w->enable = 0;
4258 }
4259 if (subvendor == ASUS_M2NPVMX_SUBVENDOR) {
4260 /* nid 28 is mic, nid 29 is line-in */
4261 w = hdac_widget_get(devinfo, 15);
4262 if (w != NULL)
4263 w->selconn = 2;
4264 w = hdac_widget_get(devinfo, 16);
4265 if (w != NULL)
4266 w->selconn = 1;
4267 }
4268 break;
4269 case HDA_CODEC_AD1988:
4270 case HDA_CODEC_AD1988B:
4271 /*w = hdac_widget_get(devinfo, 12);
4272 if (w != NULL) {
4273 w->selconn = 1;
4274 w->pflags |= HDA_ADC_LOCKED;
4275 }
4276 w = hdac_widget_get(devinfo, 13);
4277 if (w != NULL) {
4278 w->selconn = 4;
4279 w->pflags |= HDA_ADC_LOCKED;
4280 }
4281 w = hdac_widget_get(devinfo, 14);
4282 if (w != NULL) {
4283 w->selconn = 2;
4284 w->pflags |= HDA_ADC_LOCKED;
4285 }*/
4286 ctl = hdac_audio_ctl_amp_get(devinfo, 57, 0, 1);
4287 if (ctl != NULL) {
4288 ctl->ossmask = SOUND_MASK_IGAIN;
4289 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4290 }
4291 ctl = hdac_audio_ctl_amp_get(devinfo, 58, 0, 1);
4292 if (ctl != NULL) {
4293 ctl->ossmask = SOUND_MASK_IGAIN;
4294 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4295 }
4296 ctl = hdac_audio_ctl_amp_get(devinfo, 60, 0, 1);
4297 if (ctl != NULL) {
4298 ctl->ossmask = SOUND_MASK_IGAIN;
4299 ctl->widget->ctlflags |= SOUND_MASK_IGAIN;
4300 }
4301 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 0, 1);
4302 if (ctl != NULL) {
4303 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4304 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4305 }
4306 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 4, 1);
4307 if (ctl != NULL) {
4308 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4309 ctl->widget->ctlflags |= SOUND_MASK_MIC;
4310 }
4311 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 1, 1);
4312 if (ctl != NULL) {
4313 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4314 ctl->widget->ctlflags |= SOUND_MASK_LINE;
4315 }
4316 ctl = hdac_audio_ctl_amp_get(devinfo, 32, 7, 1);
4317 if (ctl != NULL) {
4318 ctl->ossmask = SOUND_MASK_SPEAKER | SOUND_MASK_VOLUME;
4319 ctl->widget->ctlflags |= SOUND_MASK_SPEAKER;
4320 }
4321 break;
4322 case HDA_CODEC_STAC9221:
4323 /*
4324 * Dell XPS M1210 need all DACs for each output jacks
4325 */
4326 if (subvendor == DELL_XPSM1210_SUBVENDOR)
4327 break;
4328 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4329 w = hdac_widget_get(devinfo, i);
4330 if (w == NULL || w->enable == 0)
4331 continue;
4332 if (w->type !=
4333 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT)
4334 continue;
4335 if (w->nid != 2)
4336 w->enable = 0;
4337 }
4338 break;
4339 case HDA_CODEC_STAC9221D:
4340 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4341 w = hdac_widget_get(devinfo, i);
4342 if (w == NULL || w->enable == 0)
4343 continue;
4344 if (w->type ==
4345 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4346 w->nid != 6)
4347 w->enable = 0;
4348
4349 }
4350 break;
4351 case HDA_CODEC_STAC9227:
4352 w = hdac_widget_get(devinfo, 8);
4353 if (w != NULL)
4354 w->enable = 0;
4355 w = hdac_widget_get(devinfo, 9);
4356 if (w != NULL)
4357 w->enable = 0;
4358 break;
4359 case HDA_CODEC_CXWAIKIKI:
4360 if (subvendor == HP_DV5000_SUBVENDOR) {
4361 w = hdac_widget_get(devinfo, 27);
4362 if (w != NULL)
4363 w->enable = 0;
4364 }
4365 ctl = hdac_audio_ctl_amp_get(devinfo, 16, 0, 1);
4366 if (ctl != NULL)
4367 ctl->ossmask = SOUND_MASK_SKIP;
4368 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 0, 1);
4369 if (ctl != NULL && ctl->childwidget != NULL &&
4370 ctl->childwidget->enable != 0) {
4371 ctl->ossmask = SOUND_MASK_PCM | SOUND_MASK_VOLUME;
4372 ctl->childwidget->ctlflags |= SOUND_MASK_PCM;
4373 }
4374 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 1, 1);
4375 if (ctl != NULL && ctl->childwidget != NULL &&
4376 ctl->childwidget->enable != 0) {
4377 ctl->ossmask = SOUND_MASK_LINE | SOUND_MASK_VOLUME;
4378 ctl->childwidget->ctlflags |= SOUND_MASK_LINE;
4379 }
4380 ctl = hdac_audio_ctl_amp_get(devinfo, 25, 2, 1);
4381 if (ctl != NULL && ctl->childwidget != NULL &&
4382 ctl->childwidget->enable != 0) {
4383 ctl->ossmask = SOUND_MASK_MIC | SOUND_MASK_VOLUME;
4384 ctl->childwidget->ctlflags |= SOUND_MASK_MIC;
4385 }
4386 ctl = hdac_audio_ctl_amp_get(devinfo, 26, 0, 1);
4387 if (ctl != NULL) {
4388 ctl->ossmask = SOUND_MASK_SKIP;
4389 /* XXX mixer \=rec mic broken.. why?!? */
4390 /* ctl->widget->ctlflags |= SOUND_MASK_MIC; */
4391 }
4392 break;
4393 default:
4394 break;
4395 }
4396 }
4397
4398 static int
4399 hdac_audio_ctl_ossmixer_getnextdev(struct hdac_devinfo *devinfo)
4400 {
4401 int *dev = &devinfo->function.audio.ossidx;
4402
4403 while (*dev < SOUND_MIXER_NRDEVICES) {
4404 switch (*dev) {
4405 case SOUND_MIXER_VOLUME:
4406 case SOUND_MIXER_BASS:
4407 case SOUND_MIXER_TREBLE:
4408 case SOUND_MIXER_PCM:
4409 case SOUND_MIXER_SPEAKER:
4410 case SOUND_MIXER_LINE:
4411 case SOUND_MIXER_MIC:
4412 case SOUND_MIXER_CD:
4413 case SOUND_MIXER_RECLEV:
4414 case SOUND_MIXER_IGAIN:
4415 case SOUND_MIXER_OGAIN: /* reserved for EAPD switch */
4416 (*dev)++;
4417 break;
4418 default:
4419 return (*dev)++;
4420 break;
4421 }
4422 }
4423
4424 return (-1);
4425 }
4426
4427 static int
4428 hdac_widget_find_dac_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4429 {
4430 struct hdac_widget *w;
4431 int i, ret = 0;
4432
4433 if (depth > HDA_PARSE_MAXDEPTH)
4434 return (0);
4435 w = hdac_widget_get(devinfo, nid);
4436 if (w == NULL || w->enable == 0)
4437 return (0);
4438 switch (w->type) {
4439 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
4440 w->pflags |= HDA_DAC_PATH;
4441 ret = 1;
4442 break;
4443 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4444 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4445 for (i = 0; i < w->nconns; i++) {
4446 if (hdac_widget_find_dac_path(devinfo,
4447 w->conns[i], depth + 1) != 0) {
4448 if (w->selconn == -1)
4449 w->selconn = i;
4450 ret = 1;
4451 w->pflags |= HDA_DAC_PATH;
4452 }
4453 }
4454 break;
4455 default:
4456 break;
4457 }
4458 return (ret);
4459 }
4460
4461 static int
4462 hdac_widget_find_adc_path(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4463 {
4464 struct hdac_widget *w;
4465 int i, conndev, ret = 0;
4466
4467 if (depth > HDA_PARSE_MAXDEPTH)
4468 return (0);
4469 w = hdac_widget_get(devinfo, nid);
4470 if (w == NULL || w->enable == 0)
4471 return (0);
4472 switch (w->type) {
4473 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
4474 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4475 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4476 for (i = 0; i < w->nconns; i++) {
4477 if (hdac_widget_find_adc_path(devinfo, w->conns[i],
4478 depth + 1) != 0) {
4479 if (w->selconn == -1)
4480 w->selconn = i;
4481 w->pflags |= HDA_ADC_PATH;
4482 ret = 1;
4483 }
4484 }
4485 break;
4486 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
4487 conndev = w->wclass.pin.config &
4488 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4489 if (HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4490 (conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_CD ||
4491 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN ||
4492 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN)) {
4493 w->pflags |= HDA_ADC_PATH;
4494 ret = 1;
4495 }
4496 break;
4497 /*case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4498 if (w->pflags & HDA_DAC_PATH) {
4499 w->pflags |= HDA_ADC_PATH;
4500 ret = 1;
4501 }
4502 break;*/
4503 default:
4504 break;
4505 }
4506 return (ret);
4507 }
4508
4509 static uint32_t
4510 hdac_audio_ctl_outamp_build(struct hdac_devinfo *devinfo,
4511 nid_t nid, nid_t pnid, int index, int depth)
4512 {
4513 struct hdac_widget *w, *pw;
4514 struct hdac_audio_ctl *ctl;
4515 uint32_t fl = 0;
4516 int i, ossdev, conndev, strategy;
4517
4518 if (depth > HDA_PARSE_MAXDEPTH)
4519 return (0);
4520
4521 w = hdac_widget_get(devinfo, nid);
4522 if (w == NULL || w->enable == 0)
4523 return (0);
4524
4525 pw = hdac_widget_get(devinfo, pnid);
4526 strategy = devinfo->function.audio.parsing_strategy;
4527
4528 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER
4529 || w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) {
4530 for (i = 0; i < w->nconns; i++) {
4531 fl |= hdac_audio_ctl_outamp_build(devinfo, w->conns[i],
4532 w->nid, i, depth + 1);
4533 }
4534 w->ctlflags |= fl;
4535 return (fl);
4536 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT &&
4537 (w->pflags & HDA_DAC_PATH)) {
4538 i = 0;
4539 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4540 if (ctl->enable == 0 || ctl->widget == NULL)
4541 continue;
4542 /* XXX This should be compressed! */
4543 if (((ctl->widget->nid == w->nid) ||
4544 (ctl->widget->nid == pnid && ctl->index == index &&
4545 (ctl->dir & HDA_CTL_IN)) ||
4546 (ctl->widget->nid == pnid && pw != NULL &&
4547 pw->type ==
4548 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4549 (pw->nconns < 2 || pw->selconn == index ||
4550 pw->selconn == -1) &&
4551 (ctl->dir & HDA_CTL_OUT)) ||
4552 (strategy == HDA_PARSE_DIRECT &&
4553 ctl->widget->nid == w->nid)) &&
4554 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4555 /*if (pw != NULL && pw->selconn == -1)
4556 pw->selconn = index;
4557 fl |= SOUND_MASK_VOLUME;
4558 fl |= SOUND_MASK_PCM;
4559 ctl->ossmask |= SOUND_MASK_VOLUME;
4560 ctl->ossmask |= SOUND_MASK_PCM;
4561 ctl->ossdev = SOUND_MIXER_PCM;*/
4562 if (!(w->ctlflags & SOUND_MASK_PCM) ||
4563 (pw != NULL &&
4564 !(pw->ctlflags & SOUND_MASK_PCM))) {
4565 fl |= SOUND_MASK_VOLUME;
4566 fl |= SOUND_MASK_PCM;
4567 ctl->ossmask |= SOUND_MASK_VOLUME;
4568 ctl->ossmask |= SOUND_MASK_PCM;
4569 ctl->ossdev = SOUND_MIXER_PCM;
4570 w->ctlflags |= SOUND_MASK_VOLUME;
4571 w->ctlflags |= SOUND_MASK_PCM;
4572 if (pw != NULL) {
4573 if (pw->selconn == -1)
4574 pw->selconn = index;
4575 pw->ctlflags |=
4576 SOUND_MASK_VOLUME;
4577 pw->ctlflags |=
4578 SOUND_MASK_PCM;
4579 }
4580 }
4581 }
4582 }
4583 w->ctlflags |= fl;
4584 return (fl);
4585 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4586 HDA_PARAM_PIN_CAP_INPUT_CAP(w->wclass.pin.cap) &&
4587 (w->pflags & HDA_ADC_PATH)) {
4588 conndev = w->wclass.pin.config &
4589 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4590 i = 0;
4591 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4592 if (ctl->enable == 0 || ctl->widget == NULL)
4593 continue;
4594 /* XXX This should be compressed! */
4595 if (((ctl->widget->nid == pnid && ctl->index == index &&
4596 (ctl->dir & HDA_CTL_IN)) ||
4597 (ctl->widget->nid == pnid && pw != NULL &&
4598 pw->type ==
4599 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4600 (pw->nconns < 2 || pw->selconn == index ||
4601 pw->selconn == -1) &&
4602 (ctl->dir & HDA_CTL_OUT)) ||
4603 (strategy == HDA_PARSE_DIRECT &&
4604 ctl->widget->nid == w->nid)) &&
4605 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4606 if (pw != NULL && pw->selconn == -1)
4607 pw->selconn = index;
4608 ossdev = 0;
4609 switch (conndev) {
4610 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
4611 ossdev = SOUND_MIXER_MIC;
4612 break;
4613 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
4614 ossdev = SOUND_MIXER_LINE;
4615 break;
4616 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
4617 ossdev = SOUND_MIXER_CD;
4618 break;
4619 default:
4620 ossdev =
4621 hdac_audio_ctl_ossmixer_getnextdev(
4622 devinfo);
4623 if (ossdev < 0)
4624 ossdev = 0;
4625 break;
4626 }
4627 if (strategy == HDA_PARSE_MIXER) {
4628 fl |= SOUND_MASK_VOLUME;
4629 ctl->ossmask |= SOUND_MASK_VOLUME;
4630 }
4631 fl |= 1 << ossdev;
4632 ctl->ossmask |= 1 << ossdev;
4633 ctl->ossdev = ossdev;
4634 }
4635 }
4636 w->ctlflags |= fl;
4637 return (fl);
4638 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4639 i = 0;
4640 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4641 if (ctl->enable == 0 || ctl->widget == NULL)
4642 continue;
4643 /* XXX This should be compressed! */
4644 if (((ctl->widget->nid == pnid && ctl->index == index &&
4645 (ctl->dir & HDA_CTL_IN)) ||
4646 (ctl->widget->nid == pnid && pw != NULL &&
4647 pw->type ==
4648 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
4649 (pw->nconns < 2 || pw->selconn == index ||
4650 pw->selconn == -1) &&
4651 (ctl->dir & HDA_CTL_OUT)) ||
4652 (strategy == HDA_PARSE_DIRECT &&
4653 ctl->widget->nid == w->nid)) &&
4654 !(ctl->ossmask & ~SOUND_MASK_VOLUME)) {
4655 if (pw != NULL && pw->selconn == -1)
4656 pw->selconn = index;
4657 fl |= SOUND_MASK_VOLUME;
4658 fl |= SOUND_MASK_SPEAKER;
4659 ctl->ossmask |= SOUND_MASK_VOLUME;
4660 ctl->ossmask |= SOUND_MASK_SPEAKER;
4661 ctl->ossdev = SOUND_MIXER_SPEAKER;
4662 }
4663 }
4664 w->ctlflags |= fl;
4665 return (fl);
4666 }
4667 return (0);
4668 }
4669
4670 static uint32_t
4671 hdac_audio_ctl_inamp_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4672 {
4673 struct hdac_widget *w, *cw;
4674 struct hdac_audio_ctl *ctl;
4675 uint32_t fl;
4676 int i;
4677
4678 if (depth > HDA_PARSE_MAXDEPTH)
4679 return (0);
4680
4681 w = hdac_widget_get(devinfo, nid);
4682 if (w == NULL || w->enable == 0)
4683 return (0);
4684 /*if (!(w->pflags & HDA_ADC_PATH))
4685 return (0);
4686 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4687 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4688 return (0);*/
4689 i = 0;
4690 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
4691 if (ctl->enable == 0 || ctl->widget == NULL)
4692 continue;
4693 if (ctl->widget->nid == nid) {
4694 ctl->ossmask |= SOUND_MASK_RECLEV;
4695 w->ctlflags |= SOUND_MASK_RECLEV;
4696 return (SOUND_MASK_RECLEV);
4697 }
4698 }
4699 for (i = 0; i < w->nconns; i++) {
4700 cw = hdac_widget_get(devinfo, w->conns[i]);
4701 if (cw == NULL || cw->enable == 0)
4702 continue;
4703 if (cw->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4704 continue;
4705 fl = hdac_audio_ctl_inamp_build(devinfo, cw->nid, depth + 1);
4706 if (fl != 0) {
4707 cw->ctlflags |= fl;
4708 w->ctlflags |= fl;
4709 return (fl);
4710 }
4711 }
4712 return (0);
4713 }
4714
4715 static int
4716 hdac_audio_ctl_recsel_build(struct hdac_devinfo *devinfo, nid_t nid, int depth)
4717 {
4718 struct hdac_widget *w, *cw;
4719 int i, child = 0;
4720
4721 if (depth > HDA_PARSE_MAXDEPTH)
4722 return (0);
4723
4724 w = hdac_widget_get(devinfo, nid);
4725 if (w == NULL || w->enable == 0)
4726 return (0);
4727 /*if (!(w->pflags & HDA_ADC_PATH))
4728 return (0);
4729 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
4730 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4731 return (0);*/
4732 /* XXX weak! */
4733 for (i = 0; i < w->nconns; i++) {
4734 cw = hdac_widget_get(devinfo, w->conns[i]);
4735 if (cw == NULL)
4736 continue;
4737 if (++child > 1) {
4738 w->pflags |= HDA_ADC_RECSEL;
4739 return (1);
4740 }
4741 }
4742 for (i = 0; i < w->nconns; i++) {
4743 if (hdac_audio_ctl_recsel_build(devinfo,
4744 w->conns[i], depth + 1) != 0)
4745 return (1);
4746 }
4747 return (0);
4748 }
4749
4750 static int
4751 hdac_audio_build_tree_strategy(struct hdac_devinfo *devinfo)
4752 {
4753 struct hdac_widget *w, *cw;
4754 int i, j, conndev, found_dac = 0;
4755 int strategy;
4756
4757 strategy = devinfo->function.audio.parsing_strategy;
4758
4759 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4760 w = hdac_widget_get(devinfo, i);
4761 if (w == NULL || w->enable == 0)
4762 continue;
4763 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4764 continue;
4765 if (!HDA_PARAM_PIN_CAP_OUTPUT_CAP(w->wclass.pin.cap))
4766 continue;
4767 conndev = w->wclass.pin.config &
4768 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4769 if (!(conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4770 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4771 conndev == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT))
4772 continue;
4773 for (j = 0; j < w->nconns; j++) {
4774 cw = hdac_widget_get(devinfo, w->conns[j]);
4775 if (cw == NULL || cw->enable == 0)
4776 continue;
4777 if (strategy == HDA_PARSE_MIXER && !(cw->type ==
4778 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4779 cw->type ==
4780 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
4781 continue;
4782 if (hdac_widget_find_dac_path(devinfo, cw->nid, 0)
4783 != 0) {
4784 if (w->selconn == -1)
4785 w->selconn = j;
4786 w->pflags |= HDA_DAC_PATH;
4787 found_dac++;
4788 }
4789 }
4790 }
4791
4792 return (found_dac);
4793 }
4794
4795 static void
4796 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
4797 {
4798 struct hdac_widget *w;
4799 struct hdac_audio_ctl *ctl;
4800 int i, j, dacs, strategy;
4801
4802 /* Construct DAC path */
4803 strategy = HDA_PARSE_MIXER;
4804 devinfo->function.audio.parsing_strategy = strategy;
4805 HDA_BOOTVERBOSE(
4806 device_printf(devinfo->codec->sc->dev,
4807 "HDA_DEBUG: HWiP: HDA Widget Parser - Revision %d\n",
4808 HDA_WIDGET_PARSER_REV);
4809 );
4810 dacs = hdac_audio_build_tree_strategy(devinfo);
4811 if (dacs == 0) {
4812 HDA_BOOTVERBOSE(
4813 device_printf(devinfo->codec->sc->dev,
4814 "HDA_DEBUG: HWiP: 0 DAC path found! "
4815 "Retrying parser "
4816 "using HDA_PARSE_DIRECT strategy.\n");
4817 );
4818 strategy = HDA_PARSE_DIRECT;
4819 devinfo->function.audio.parsing_strategy = strategy;
4820 dacs = hdac_audio_build_tree_strategy(devinfo);
4821 }
4822
4823 HDA_BOOTVERBOSE(
4824 device_printf(devinfo->codec->sc->dev,
4825 "HDA_DEBUG: HWiP: Found %d DAC path using HDA_PARSE_%s "
4826 "strategy.\n",
4827 dacs, (strategy == HDA_PARSE_MIXER) ? "MIXER" : "DIRECT");
4828 );
4829
4830 /* Construct ADC path */
4831 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4832 w = hdac_widget_get(devinfo, i);
4833 if (w == NULL || w->enable == 0)
4834 continue;
4835 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
4836 continue;
4837 (void)hdac_widget_find_adc_path(devinfo, w->nid, 0);
4838 }
4839
4840 /* Output mixers */
4841 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4842 w = hdac_widget_get(devinfo, i);
4843 if (w == NULL || w->enable == 0)
4844 continue;
4845 if ((strategy == HDA_PARSE_MIXER &&
4846 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER ||
4847 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)
4848 && (w->pflags & HDA_DAC_PATH)) ||
4849 (strategy == HDA_PARSE_DIRECT && (w->pflags &
4850 (HDA_DAC_PATH | HDA_ADC_PATH)))) {
4851 w->ctlflags |= hdac_audio_ctl_outamp_build(devinfo,
4852 w->nid, devinfo->startnode - 1, 0, 0);
4853 } else if (w->type ==
4854 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) {
4855 j = 0;
4856 while ((ctl = hdac_audio_ctl_each(devinfo, &j)) !=
4857 NULL) {
4858 if (ctl->enable == 0 || ctl->widget == NULL)
4859 continue;
4860 if (ctl->widget->nid != w->nid)
4861 continue;
4862 ctl->ossmask |= SOUND_MASK_VOLUME;
4863 ctl->ossmask |= SOUND_MASK_SPEAKER;
4864 ctl->ossdev = SOUND_MIXER_SPEAKER;
4865 w->ctlflags |= SOUND_MASK_VOLUME;
4866 w->ctlflags |= SOUND_MASK_SPEAKER;
4867 }
4868 }
4869 }
4870
4871 /* Input mixers (rec) */
4872 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4873 w = hdac_widget_get(devinfo, i);
4874 if (w == NULL || w->enable == 0)
4875 continue;
4876 if (!(w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT &&
4877 w->pflags & HDA_ADC_PATH))
4878 continue;
4879 hdac_audio_ctl_inamp_build(devinfo, w->nid, 0);
4880 hdac_audio_ctl_recsel_build(devinfo, w->nid, 0);
4881 }
4882 }
4883
4884 #define HDA_COMMIT_CONN (1 << 0)
4885 #define HDA_COMMIT_CTRL (1 << 1)
4886 #define HDA_COMMIT_EAPD (1 << 2)
4887 #define HDA_COMMIT_GPIO (1 << 3)
4888 #define HDA_COMMIT_MISC (1 << 4)
4889 #define HDA_COMMIT_ALL (HDA_COMMIT_CONN | HDA_COMMIT_CTRL | \
4890 HDA_COMMIT_EAPD | HDA_COMMIT_GPIO | HDA_COMMIT_MISC)
4891
4892 static void
4893 hdac_audio_commit(struct hdac_devinfo *devinfo, uint32_t cfl)
4894 {
4895 struct hdac_softc *sc = devinfo->codec->sc;
4896 struct hdac_widget *w;
4897 nid_t cad;
4898 int i;
4899
4900 if (!(cfl & HDA_COMMIT_ALL))
4901 return;
4902
4903 cad = devinfo->codec->cad;
4904
4905 if ((cfl & HDA_COMMIT_MISC)) {
4906 if (sc->pci_subvendor == APPLE_INTEL_MAC)
4907 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
4908 0x7e7, 0), cad);
4909 }
4910
4911 if (cfl & HDA_COMMIT_GPIO) {
4912 uint32_t gdata, gmask, gdir;
4913 int commitgpio, numgpio;
4914
4915 gdata = 0;
4916 gmask = 0;
4917 gdir = 0;
4918 commitgpio = 0;
4919
4920 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
4921 devinfo->function.audio.gpio);
4922
4923 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
4924 commitgpio = (numgpio > 0) ? 1 : 0;
4925 else {
4926 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
4927 if (!(devinfo->function.audio.quirks &
4928 (1 << i)))
4929 continue;
4930 if (commitgpio == 0) {
4931 commitgpio = 1;
4932 HDA_BOOTVERBOSE(
4933 gdata = hdac_command(sc,
4934 HDA_CMD_GET_GPIO_DATA(cad,
4935 devinfo->nid), cad);
4936 gmask = hdac_command(sc,
4937 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
4938 devinfo->nid), cad);
4939 gdir = hdac_command(sc,
4940 HDA_CMD_GET_GPIO_DIRECTION(cad,
4941 devinfo->nid), cad);
4942 device_printf(sc->dev,
4943 "GPIO init: data=0x%08x "
4944 "mask=0x%08x dir=0x%08x\n",
4945 gdata, gmask, gdir);
4946 gdata = 0;
4947 gmask = 0;
4948 gdir = 0;
4949 );
4950 }
4951 gdata |= 1 << i;
4952 gmask |= 1 << i;
4953 gdir |= 1 << i;
4954 }
4955 }
4956
4957 if (commitgpio != 0) {
4958 HDA_BOOTVERBOSE(
4959 device_printf(sc->dev,
4960 "GPIO commit: data=0x%08x mask=0x%08x "
4961 "dir=0x%08x\n",
4962 gdata, gmask, gdir);
4963 );
4964 hdac_command(sc,
4965 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
4966 gmask), cad);
4967 hdac_command(sc,
4968 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
4969 gdir), cad);
4970 hdac_command(sc,
4971 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
4972 gdata), cad);
4973 }
4974 }
4975
4976 for (i = 0; i < devinfo->nodecnt; i++) {
4977 w = &devinfo->widget[i];
4978 if (w == NULL || w->enable == 0)
4979 continue;
4980 if (cfl & HDA_COMMIT_CONN) {
4981 if (w->selconn == -1)
4982 w->selconn = 0;
4983 if (w->nconns > 0)
4984 hdac_widget_connection_select(w, w->selconn);
4985 }
4986 if ((cfl & HDA_COMMIT_CTRL) &&
4987 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
4988 uint32_t pincap;
4989
4990 pincap = w->wclass.pin.cap;
4991
4992 if ((w->pflags & (HDA_DAC_PATH | HDA_ADC_PATH)) ==
4993 (HDA_DAC_PATH | HDA_ADC_PATH))
4994 device_printf(sc->dev, "WARNING: node %d "
4995 "participate both for DAC/ADC!\n", w->nid);
4996 if (w->pflags & HDA_DAC_PATH) {
4997 w->wclass.pin.ctrl &=
4998 ~HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
4999 if ((w->wclass.pin.config &
5000 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) !=
5001 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
5002 w->wclass.pin.ctrl &=
5003 ~HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
5004 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
5005 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5006 w->wclass.pin.ctrl |=
5007 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5008 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5009 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
5010 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5011 w->wclass.pin.ctrl |=
5012 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5013 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5014 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
5015 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5016 w->wclass.pin.ctrl |=
5017 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5018 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5019 } else if (w->pflags & HDA_ADC_PATH) {
5020 w->wclass.pin.ctrl &=
5021 ~(HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5022 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE);
5023 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
5024 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5025 w->wclass.pin.ctrl |=
5026 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5027 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
5028 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
5029 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5030 w->wclass.pin.ctrl |=
5031 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5032 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
5033 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
5034 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5035 w->wclass.pin.ctrl |=
5036 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
5037 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
5038 } else
5039 w->wclass.pin.ctrl &= ~(
5040 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
5041 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
5042 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
5043 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
5044 hdac_command(sc,
5045 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
5046 w->wclass.pin.ctrl), cad);
5047 }
5048 if ((cfl & HDA_COMMIT_EAPD) &&
5049 w->param.eapdbtl != HDAC_INVALID) {
5050 uint32_t val;
5051
5052 val = w->param.eapdbtl;
5053 if (devinfo->function.audio.quirks &
5054 HDA_QUIRK_EAPDINV)
5055 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
5056 hdac_command(sc,
5057 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
5058 val), cad);
5059
5060 }
5061 DELAY(1000);
5062 }
5063 }
5064
5065 static void
5066 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
5067 {
5068 struct hdac_softc *sc = devinfo->codec->sc;
5069 struct hdac_audio_ctl *ctl;
5070 int i;
5071
5072 devinfo->function.audio.mvol = 100 | (100 << 8);
5073 i = 0;
5074 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5075 if (ctl->enable == 0 || ctl->widget == NULL) {
5076 HDA_BOOTVERBOSE(
5077 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5078 i, (ctl->widget != NULL) ?
5079 ctl->widget->nid : -1);
5080 if (ctl->childwidget != NULL)
5081 kprintf(" childnid=%d",
5082 ctl->childwidget->nid);
5083 if (ctl->widget == NULL)
5084 kprintf(" NULL WIDGET!");
5085 kprintf(" DISABLED\n");
5086 );
5087 continue;
5088 }
5089 HDA_BOOTVERBOSE(
5090 if (ctl->ossmask == 0) {
5091 device_printf(sc->dev, "[%2d] Ctl nid=%d",
5092 i, ctl->widget->nid);
5093 if (ctl->childwidget != NULL)
5094 kprintf(" childnid=%d",
5095 ctl->childwidget->nid);
5096 kprintf(" Bind to NONE\n");
5097 }
5098 );
5099 if (ctl->step > 0) {
5100 ctl->ossval = (ctl->left * 100) / ctl->step;
5101 ctl->ossval |= ((ctl->right * 100) / ctl->step) << 8;
5102 } else
5103 ctl->ossval = 0;
5104 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_DEFAULT,
5105 ctl->left, ctl->right);
5106 }
5107 }
5108
5109 static int
5110 hdac_pcmchannel_setup(struct hdac_devinfo *devinfo, int dir)
5111 {
5112 struct hdac_chan *ch;
5113 struct hdac_widget *w;
5114 uint32_t cap, fmtcap, pcmcap, path;
5115 int i, type, ret, max;
5116
5117 if (dir == PCMDIR_PLAY) {
5118 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT;
5119 ch = &devinfo->codec->sc->play;
5120 path = HDA_DAC_PATH;
5121 } else {
5122 type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT;
5123 ch = &devinfo->codec->sc->rec;
5124 path = HDA_ADC_PATH;
5125 }
5126
5127 ch->caps = hdac_caps;
5128 ch->caps.fmtlist = ch->fmtlist;
5129 ch->bit16 = 1;
5130 ch->bit32 = 0;
5131 ch->pcmrates[0] = 48000;
5132 ch->pcmrates[1] = 0;
5133
5134 ret = 0;
5135 fmtcap = devinfo->function.audio.supp_stream_formats;
5136 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
5137 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1;
5138
5139 for (i = devinfo->startnode; i < devinfo->endnode && ret < max; i++) {
5140 w = hdac_widget_get(devinfo, i);
5141 if (w == NULL || w->enable == 0 || w->type != type ||
5142 !(w->pflags & path))
5143 continue;
5144 cap = w->param.widget_cap;
5145 /*if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(cap))
5146 continue;*/
5147 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(cap))
5148 continue;
5149 cap = w->param.supp_stream_formats;
5150 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) {
5151 }
5152 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) {
5153 }*/
5154 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5155 continue;
5156 if (ret == 0) {
5157 fmtcap = w->param.supp_stream_formats;
5158 pcmcap = w->param.supp_pcm_size_rate;
5159 } else {
5160 fmtcap &= w->param.supp_stream_formats;
5161 pcmcap &= w->param.supp_pcm_size_rate;
5162 }
5163 ch->io[ret++] = i;
5164 }
5165 ch->io[ret] = -1;
5166
5167 ch->supp_stream_formats = fmtcap;
5168 ch->supp_pcm_size_rate = pcmcap;
5169
5170 /*
5171 * 8bit = 0
5172 * 16bit = 1
5173 * 20bit = 2
5174 * 24bit = 3
5175 * 32bit = 4
5176 */
5177 if (ret > 0) {
5178 cap = pcmcap;
5179 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5180 ch->bit16 = 1;
5181 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5182 ch->bit16 = 0;
5183 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5184 ch->bit32 = 4;
5185 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5186 ch->bit32 = 3;
5187 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5188 ch->bit32 = 2;
5189 i = 0;
5190 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO))
5191 ch->fmtlist[i++] = AFMT_S16_LE;
5192 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO;
5193 if (ch->bit32 > 0) {
5194 if (!(devinfo->function.audio.quirks &
5195 HDA_QUIRK_FORCESTEREO))
5196 ch->fmtlist[i++] = AFMT_S32_LE;
5197 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO;
5198 }
5199 ch->fmtlist[i] = 0;
5200 i = 0;
5201 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5202 ch->pcmrates[i++] = 8000;
5203 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5204 ch->pcmrates[i++] = 11025;
5205 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5206 ch->pcmrates[i++] = 16000;
5207 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5208 ch->pcmrates[i++] = 22050;
5209 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5210 ch->pcmrates[i++] = 32000;
5211 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5212 ch->pcmrates[i++] = 44100;
5213 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(cap)) */
5214 ch->pcmrates[i++] = 48000;
5215 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5216 ch->pcmrates[i++] = 88200;
5217 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5218 ch->pcmrates[i++] = 96000;
5219 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5220 ch->pcmrates[i++] = 176400;
5221 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5222 ch->pcmrates[i++] = 192000;
5223 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(cap)) */
5224 ch->pcmrates[i] = 0;
5225 if (i > 0) {
5226 ch->caps.minspeed = ch->pcmrates[0];
5227 ch->caps.maxspeed = ch->pcmrates[i - 1];
5228 }
5229 }
5230
5231 return (ret);
5232 }
5233
5234 static void
5235 hdac_dump_ctls(struct hdac_devinfo *devinfo, const char *banner, uint32_t flag)
5236 {
5237 struct hdac_audio_ctl *ctl;
5238 struct hdac_softc *sc = devinfo->codec->sc;
5239 int i;
5240 uint32_t fl = 0;
5241
5242
5243 if (flag == 0) {
5244 fl = SOUND_MASK_VOLUME | SOUND_MASK_PCM |
5245 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
5246 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN;
5247 }
5248
5249 i = 0;
5250 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5251 if (ctl->enable == 0 || ctl->widget == NULL ||
5252 ctl->widget->enable == 0 || (ctl->ossmask &
5253 (SOUND_MASK_SKIP | SOUND_MASK_DISABLE)))
5254 continue;
5255 if ((flag == 0 && (ctl->ossmask & ~fl)) ||
5256 (flag != 0 && (ctl->ossmask & flag))) {
5257 if (banner != NULL) {
5258 device_printf(sc->dev, "\n");
5259 device_printf(sc->dev, "%s\n", banner);
5260 }
5261 goto hdac_ctl_dump_it_all;
5262 }
5263 }
5264
5265 return;
5266
5267 hdac_ctl_dump_it_all:
5268 i = 0;
5269 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5270 if (ctl->enable == 0 || ctl->widget == NULL ||
5271 ctl->widget->enable == 0)
5272 continue;
5273 if (!((flag == 0 && (ctl->ossmask & ~fl)) ||
5274 (flag != 0 && (ctl->ossmask & flag))))
5275 continue;
5276 if (flag == 0) {
5277 device_printf(sc->dev, "\n");
5278 device_printf(sc->dev, "Unknown Ctl (OSS: %s)\n",
5279 hdac_audio_ctl_ossmixer_mask2name(ctl->ossmask));
5280 }
5281 device_printf(sc->dev, " |\n");
5282 device_printf(sc->dev, " +- nid: %2d index: %2d ",
5283 ctl->widget->nid, ctl->index);
5284 if (ctl->childwidget != NULL)
5285 kprintf("(nid: %2d) ", ctl->childwidget->nid);
5286 else
5287 kprintf(" ");
5288 kprintf("mute: %d step: %3d size: %3d off: %3d dir=0x%x ossmask=0x%08x\n",
5289 ctl->mute, ctl->step, ctl->size, ctl->offset, ctl->dir,
5290 ctl->ossmask);
5291 }
5292 }
5293
5294 static void
5295 hdac_dump_audio_formats(struct hdac_softc *sc, uint32_t fcap, uint32_t pcmcap)
5296 {
5297 uint32_t cap;
5298
5299 cap = fcap;
5300 if (cap != 0) {
5301 device_printf(sc->dev, " Stream cap: 0x%08x\n", cap);
5302 device_printf(sc->dev, " Format:");
5303 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
5304 kprintf(" AC3");
5305 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
5306 kprintf(" FLOAT32");
5307 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
5308 kprintf(" PCM");
5309 kprintf("\n");
5310 }
5311 cap = pcmcap;
5312 if (cap != 0) {
5313 device_printf(sc->dev, " PCM cap: 0x%08x\n", cap);
5314 device_printf(sc->dev, " PCM size:");
5315 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
5316 kprintf(" 8");
5317 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
5318 kprintf(" 16");
5319 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
5320 kprintf(" 20");
5321 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
5322 kprintf(" 24");
5323 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
5324 kprintf(" 32");
5325 kprintf("\n");
5326 device_printf(sc->dev, " PCM rate:");
5327 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
5328 kprintf(" 8");
5329 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
5330 kprintf(" 11");
5331 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
5332 kprintf(" 16");
5333 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
5334 kprintf(" 22");
5335 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
5336 kprintf(" 32");
5337 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
5338 kprintf(" 44");
5339 kprintf(" 48");
5340 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
5341 kprintf(" 88");
5342 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
5343 kprintf(" 96");
5344 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
5345 kprintf(" 176");
5346 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
5347 kprintf(" 192");
5348 kprintf("\n");
5349 }
5350 }
5351
5352 static void
5353 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
5354 {
5355 uint32_t pincap, wcap;
5356
5357 pincap = w->wclass.pin.cap;
5358 wcap = w->param.widget_cap;
5359
5360 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
5361 device_printf(sc->dev, " ");
5362 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
5363 kprintf(" ISC");
5364 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
5365 kprintf(" TRQD");
5366 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
5367 kprintf(" PDC");
5368 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
5369 kprintf(" HP");
5370 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
5371 kprintf(" OUT");
5372 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
5373 kprintf(" IN");
5374 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
5375 kprintf(" BAL");
5376 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
5377 kprintf(" VREF[");
5378 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
5379 kprintf(" 50");
5380 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
5381 kprintf(" 80");
5382 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
5383 kprintf(" 100");
5384 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
5385 kprintf(" GROUND");
5386 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
5387 kprintf(" HIZ");
5388 kprintf(" ]");
5389 }
5390 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
5391 kprintf(" EAPD");
5392 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(wcap))
5393 kprintf(" : UNSOL");
5394 kprintf("\n");
5395 device_printf(sc->dev, " Pin config: 0x%08x\n",
5396 w->wclass.pin.config);
5397 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
5398 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
5399 kprintf(" HP");
5400 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
5401 kprintf(" IN");
5402 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
5403 kprintf(" OUT");
5404 kprintf("\n");
5405 }
5406
5407 static void
5408 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
5409 {
5410 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
5411 device_printf(sc->dev, " "
5412 "mute=%d step=%d size=%d offset=%d\n",
5413 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
5414 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
5415 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
5416 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
5417 }
5418
5419 static void
5420 hdac_dump_nodes(struct hdac_devinfo *devinfo)
5421 {
5422 struct hdac_softc *sc = devinfo->codec->sc;
5423 struct hdac_widget *w, *cw;
5424 int i, j;
5425
5426 device_printf(sc->dev, "\n");
5427 device_printf(sc->dev, "Default Parameter\n");
5428 device_printf(sc->dev, "-----------------\n");
5429 hdac_dump_audio_formats(sc,
5430 devinfo->function.audio.supp_stream_formats,
5431 devinfo->function.audio.supp_pcm_size_rate);
5432 device_printf(sc->dev, " IN amp: 0x%08x\n",
5433 devinfo->function.audio.inamp_cap);
5434 device_printf(sc->dev, " OUT amp: 0x%08x\n",
5435 devinfo->function.audio.outamp_cap);
5436 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5437 w = hdac_widget_get(devinfo, i);
5438 if (w == NULL) {
5439 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
5440 continue;
5441 }
5442 device_printf(sc->dev, "\n");
5443 device_printf(sc->dev, " nid: %d [%s]%s\n", w->nid,
5444 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap) ?
5445 "DIGITAL" : "ANALOG",
5446 (w->enable == 0) ? " [DISABLED]" : "");
5447 device_printf(sc->dev, " name: %s\n", w->name);
5448 device_printf(sc->dev, " widget_cap: 0x%08x\n",
5449 w->param.widget_cap);
5450 device_printf(sc->dev, " Parse flags: 0x%08x\n",
5451 w->pflags);
5452 device_printf(sc->dev, " Ctl flags: 0x%08x\n",
5453 w->ctlflags);
5454 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
5455 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
5456 hdac_dump_audio_formats(sc,
5457 w->param.supp_stream_formats,
5458 w->param.supp_pcm_size_rate);
5459 } else if (w->type ==
5460 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5461 hdac_dump_pin(sc, w);
5462 if (w->param.eapdbtl != HDAC_INVALID)
5463 device_printf(sc->dev, " EAPD: 0x%08x\n",
5464 w->param.eapdbtl);
5465 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
5466 w->param.outamp_cap != 0)
5467 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
5468 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
5469 w->param.inamp_cap != 0)
5470 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
5471 device_printf(sc->dev, " connections: %d\n", w->nconns);
5472 for (j = 0; j < w->nconns; j++) {
5473 cw = hdac_widget_get(devinfo, w->conns[j]);
5474 device_printf(sc->dev, " |\n");
5475 device_printf(sc->dev, " + <- nid=%d [%s]",
5476 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
5477 if (cw == NULL)
5478 kprintf(" [UNKNOWN]");
5479 else if (cw->enable == 0)
5480 kprintf(" [DISABLED]");
5481 if (w->nconns > 1 && w->selconn == j && w->type !=
5482 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5483 kprintf(" (selected)");
5484 kprintf("\n");
5485 }
5486 }
5487
5488 }
5489
5490 static int
5491 hdac_dump_dac_internal(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5492 {
5493 struct hdac_widget *w, *cw;
5494 struct hdac_softc *sc = devinfo->codec->sc;
5495 int i;
5496
5497 if (depth > HDA_PARSE_MAXDEPTH)
5498 return (0);
5499
5500 w = hdac_widget_get(devinfo, nid);
5501 if (w == NULL || w->enable == 0 || !(w->pflags & HDA_DAC_PATH))
5502 return (0);
5503
5504 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5505 device_printf(sc->dev, "\n");
5506 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5507 device_printf(sc->dev, " ^\n");
5508 device_printf(sc->dev, " |\n");
5509 device_printf(sc->dev, " +-----<------+\n");
5510 } else {
5511 device_printf(sc->dev, " ^\n");
5512 device_printf(sc->dev, " |\n");
5513 device_printf(sc->dev, " ");
5514 kprintf(" nid=%d [%s]\n", w->nid, w->name);
5515 }
5516
5517 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT) {
5518 return (1);
5519 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
5520 for (i = 0; i < w->nconns; i++) {
5521 cw = hdac_widget_get(devinfo, w->conns[i]);
5522 if (cw == NULL || cw->enable == 0 || cw->type ==
5523 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5524 continue;
5525 if (hdac_dump_dac_internal(devinfo, cw->nid,
5526 depth + 1) != 0)
5527 return (1);
5528 }
5529 } else if ((w->type ==
5530 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR ||
5531 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5532 w->selconn > -1 && w->selconn < w->nconns) {
5533 if (hdac_dump_dac_internal(devinfo, w->conns[w->selconn],
5534 depth + 1) != 0)
5535 return (1);
5536 }
5537
5538 return (0);
5539 }
5540
5541 static void
5542 hdac_dump_dac(struct hdac_devinfo *devinfo)
5543 {
5544 struct hdac_widget *w;
5545 struct hdac_softc *sc = devinfo->codec->sc;
5546 int i, printed = 0;
5547
5548 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5549 w = hdac_widget_get(devinfo, i);
5550 if (w == NULL || w->enable == 0)
5551 continue;
5552 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
5553 !(w->pflags & HDA_DAC_PATH))
5554 continue;
5555 if (printed == 0) {
5556 printed = 1;
5557 device_printf(sc->dev, "\n");
5558 device_printf(sc->dev, "Playback path:\n");
5559 }
5560 hdac_dump_dac_internal(devinfo, w->nid, 0);
5561 }
5562 }
5563
5564 static void
5565 hdac_dump_adc(struct hdac_devinfo *devinfo)
5566 {
5567 struct hdac_widget *w, *cw;
5568 struct hdac_softc *sc = devinfo->codec->sc;
5569 int i, j;
5570 int printed = 0;
5571 char ossdevs[256];
5572
5573 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5574 w = hdac_widget_get(devinfo, i);
5575 if (w == NULL || w->enable == 0)
5576 continue;
5577 if (!(w->pflags & HDA_ADC_RECSEL))
5578 continue;
5579 if (printed == 0) {
5580 printed = 1;
5581 device_printf(sc->dev, "\n");
5582 device_printf(sc->dev, "Recording sources:\n");
5583 }
5584 device_printf(sc->dev, "\n");
5585 device_printf(sc->dev, " nid=%d [%s]\n", w->nid, w->name);
5586 for (j = 0; j < w->nconns; j++) {
5587 cw = hdac_widget_get(devinfo, w->conns[j]);
5588 if (cw == NULL || cw->enable == 0)
5589 continue;
5590 hdac_audio_ctl_ossmixer_mask2allname(cw->ctlflags,
5591 ossdevs, sizeof(ossdevs));
5592 device_printf(sc->dev, " |\n");
5593 device_printf(sc->dev, " + <- nid=%d [%s]",
5594 cw->nid, cw->name);
5595 if (strlen(ossdevs) > 0) {
5596 kprintf(" [recsrc: %s]", ossdevs);
5597 }
5598 kprintf("\n");
5599 }
5600 }
5601 }
5602
5603 static void
5604 hdac_dump_pcmchannels(struct hdac_softc *sc, int pcnt, int rcnt)
5605 {
5606 nid_t *nids;
5607
5608 if (pcnt > 0) {
5609 device_printf(sc->dev, "\n");
5610 device_printf(sc->dev, " PCM Playback: %d\n", pcnt);
5611 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5612 sc->play.supp_pcm_size_rate);
5613 device_printf(sc->dev, " DAC:");
5614 for (nids = sc->play.io; *nids != -1; nids++)
5615 kprintf(" %d", *nids);
5616 kprintf("\n");
5617 }
5618
5619 if (rcnt > 0) {
5620 device_printf(sc->dev, "\n");
5621 device_printf(sc->dev, " PCM Record: %d\n", rcnt);
5622 hdac_dump_audio_formats(sc, sc->play.supp_stream_formats,
5623 sc->rec.supp_pcm_size_rate);
5624 device_printf(sc->dev, " ADC:");
5625 for (nids = sc->rec.io; *nids != -1; nids++)
5626 kprintf(" %d", *nids);
5627 kprintf("\n");
5628 }
5629 }
5630
5631 static void
5632 hdac_release_resources(struct hdac_softc *sc)
5633 {
5634 struct hdac_devinfo *devinfo = NULL;
5635 device_t *devlist = NULL;
5636 int i, devcount;
5637
5638 if (sc == NULL)
5639 return;
5640
5641 hdac_lock(sc);
5642 sc->polling = 0;
5643 sc->poll_ival = 0;
5644 callout_stop(&sc->poll_hda);
5645 callout_stop(&sc->poll_hdac);
5646 callout_stop(&sc->poll_jack);
5647 hdac_reset(sc);
5648 hdac_unlock(sc);
5649 #if 0 /* TODO: No callout_drain() in DragonFly. */
5650 callout_drain(&sc->poll_hda);
5651 callout_drain(&sc->poll_hdac);
5652 callout_drain(&sc->poll_jack);
5653 #else
5654 callout_stop(&sc->poll_hda);
5655 callout_stop(&sc->poll_hdac);
5656 callout_stop(&sc->poll_jack);
5657 #endif
5658
5659 hdac_irq_free(sc);
5660
5661 device_get_children(sc->dev, &devlist, &devcount);
5662 for (i = 0; devlist != NULL && i < devcount; i++) {
5663 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
5664 if (devinfo == NULL)
5665 continue;
5666 if (devinfo->widget != NULL)
5667 kfree(devinfo->widget, M_HDAC);
5668 if (devinfo->node_type ==
5669 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO &&
5670 devinfo->function.audio.ctl != NULL)
5671 kfree(devinfo->function.audio.ctl, M_HDAC);
5672 kfree(devinfo, M_HDAC);
5673 device_delete_child(sc->dev, devlist[i]);
5674 }
5675 if (devlist != NULL)
5676 kfree(devlist, M_TEMP);
5677
5678 for (i = 0; i < HDAC_CODEC_MAX; i++) {
5679 if (sc->codecs[i] != NULL)
5680 kfree(sc->codecs[i], M_HDAC);
5681 sc->codecs[i] = NULL;
5682 }
5683
5684 hdac_dma_free(sc, &sc->pos_dma);
5685 hdac_dma_free(sc, &sc->rirb_dma);
5686 hdac_dma_free(sc, &sc->corb_dma);
5687 if (sc->play.blkcnt > 0)
5688 hdac_dma_free(sc, &sc->play.bdl_dma);
5689 if (sc->rec.blkcnt > 0)
5690 hdac_dma_free(sc, &sc->rec.bdl_dma);
5691 if (sc->chan_dmat != NULL) {
5692 bus_dma_tag_destroy(sc->chan_dmat);
5693 sc->chan_dmat = NULL;
5694 }
5695 hdac_mem_free(sc);
5696 snd_mtxfree(sc->lock);
5697 kfree(sc, M_DEVBUF);
5698 }
5699
5700 /* This function surely going to make its way into upper level someday. */
5701 static void
5702 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
5703 {
5704 char *res = NULL;
5705 int i = 0, j, k, len, inv;
5706
5707 if (on != NULL)
5708 *on = 0;
5709 if (off != NULL)
5710 *off = 0;
5711 if (sc == NULL)
5712 return;
5713 if (resource_string_value(device_get_name(sc->dev),
5714 device_get_unit(sc->dev), "config", &res) != 0)
5715 return;
5716 if (!(res != NULL && strlen(res) > 0))
5717 return;
5718 HDA_BOOTVERBOSE(
5719 device_printf(sc->dev, "HDA_DEBUG: HDA Config:");
5720 );
5721 for (;;) {
5722 while (res[i] != '\0' &&
5723 (res[i] == ',' || isspace(res[i]) != 0))
5724 i++;
5725 if (res[i] == '\0') {
5726 HDA_BOOTVERBOSE(
5727 kprintf("\n");
5728 );
5729 return;
5730 }
5731 j = i;
5732 while (res[j] != '\0' &&
5733 !(res[j] == ',' || isspace(res[j]) != 0))
5734 j++;
5735 len = j - i;
5736 if (len > 2 && strncmp(res + i, "no", 2) == 0)
5737 inv = 2;
5738 else
5739 inv = 0;
5740 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
5741 if (strncmp(res + i + inv,
5742 hdac_quirks_tab[k].key, len - inv) != 0)
5743 continue;
5744 if (len - inv != strlen(hdac_quirks_tab[k].key))
5745 break;
5746 HDA_BOOTVERBOSE(
5747 kprintf(" %s%s", (inv != 0) ? "no" : "",
5748 hdac_quirks_tab[k].key);
5749 );
5750 if (inv == 0 && on != NULL)
5751 *on |= hdac_quirks_tab[k].value;
5752 else if (inv != 0 && off != NULL)
5753 *off |= hdac_quirks_tab[k].value;
5754 break;
5755 }
5756 i = j;
5757 }
5758 }
5759
5760 #ifdef SND_DYNSYSCTL
5761 static int
5762 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
5763 {
5764 struct hdac_softc *sc;
5765 struct hdac_devinfo *devinfo;
5766 device_t dev;
5767 uint32_t ctl;
5768 int err, val;
5769
5770 dev = oidp->oid_arg1;
5771 devinfo = pcm_getdevinfo(dev);
5772 if (devinfo == NULL || devinfo->codec == NULL ||
5773 devinfo->codec->sc == NULL)
5774 return (EINVAL);
5775 sc = devinfo->codec->sc;
5776 hdac_lock(sc);
5777 val = sc->polling;
5778 hdac_unlock(sc);
5779 err = sysctl_handle_int(oidp, &val, 0, req);
5780
5781 if (err != 0 || req->newptr == NULL)
5782 return (err);
5783 if (val < 0 || val > 1)
5784 return (EINVAL);
5785
5786 hdac_lock(sc);
5787 if (val != sc->polling) {
5788 if (hda_chan_active(sc) != 0)
5789 err = EBUSY;
5790 else if (val == 0) {
5791 callout_stop(&sc->poll_hdac);
5792 hdac_unlock(sc);
5793 #if 0 /* TODO: No callout_drain() in DragonFly. */
5794 callout_drain(&sc->poll_hdac);
5795 #else
5796 callout_stop(&sc->poll_hdac);
5797 #endif
5798 hdac_lock(sc);
5799 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT,
5800 sc->rirb_size / 2);
5801 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5802 ctl |= HDAC_RIRBCTL_RINTCTL;
5803 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5804 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
5805 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
5806 sc->polling = 0;
5807 DELAY(1000);
5808 } else {
5809 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 0);
5810 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, 0);
5811 ctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
5812 ctl &= ~HDAC_RIRBCTL_RINTCTL;
5813 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, ctl);
5814 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback,
5815 sc);
5816 sc->polling = 1;
5817 DELAY(1000);
5818 }
5819 }
5820 hdac_unlock(sc);
5821
5822 return (err);
5823 }
5824
5825 static int
5826 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
5827 {
5828 struct hdac_softc *sc;
5829 struct hdac_devinfo *devinfo;
5830 device_t dev;
5831 int err, val;
5832
5833 dev = oidp->oid_arg1;
5834 devinfo = pcm_getdevinfo(dev);
5835 if (devinfo == NULL || devinfo->codec == NULL ||
5836 devinfo->codec->sc == NULL)
5837 return (EINVAL);
5838 sc = devinfo->codec->sc;
5839 hdac_lock(sc);
5840 val = ((uint64_t)sc->poll_ival * 1000) / hz;
5841 hdac_unlock(sc);
5842 err = sysctl_handle_int(oidp, &val, 0, req);
5843
5844 if (err != 0 || req->newptr == NULL)
5845 return (err);
5846
5847 if (val < 1)
5848 val = 1;
5849 if (val > 5000)
5850 val = 5000;
5851 val = ((uint64_t)val * hz) / 1000;
5852 if (val < 1)
5853 val = 1;
5854 if (val > (hz * 5))
5855 val = hz * 5;
5856
5857 hdac_lock(sc);
5858 sc->poll_ival = val;
5859 hdac_unlock(sc);
5860
5861 return (err);
5862 }
5863
5864 #ifdef SND_DEBUG
5865 static int
5866 sysctl_hdac_dump(SYSCTL_HANDLER_ARGS)
5867 {
5868 struct hdac_softc *sc;
5869 struct hdac_devinfo *devinfo;
5870 struct hdac_widget *w;
5871 device_t dev;
5872 uint32_t res, execres;
5873 int i, err, val;
5874 nid_t cad;
5875
5876 dev = oidp->oid_arg1;
5877 devinfo = pcm_getdevinfo(dev);
5878 if (devinfo == NULL || devinfo->codec == NULL ||
5879 devinfo->codec->sc == NULL)
5880 return (EINVAL);
5881 val = 0;
5882 err = sysctl_handle_int(oidp, &val, 0, req);
5883 if (err != 0 || req->newptr == NULL || val == 0)
5884 return (err);
5885 sc = devinfo->codec->sc;
5886 cad = devinfo->codec->cad;
5887 hdac_lock(sc);
5888 device_printf(dev, "HDAC Dump AFG [nid=%d]:\n", devinfo->nid);
5889 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5890 w = hdac_widget_get(devinfo, i);
5891 if (w == NULL || w->type !=
5892 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5893 continue;
5894 execres = hdac_command(sc, HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0),
5895 cad);
5896 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
5897 device_printf(dev, "nid=%-3d exec=0x%08x sense=0x%08x [%s]\n",
5898 w->nid, execres, res,
5899 (w->enable == 0) ? "DISABLED" : "ENABLED");
5900 }
5901 device_printf(dev,
5902 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
5903 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
5904 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
5905 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
5906 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
5907 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
5908 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
5909 device_printf(dev, " GPI:");
5910 res = hdac_command(sc,
5911 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
5912 kprintf(" data=0x%08x", res);
5913 res = hdac_command(sc,
5914 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
5915 cad);
5916 kprintf(" wake=0x%08x", res);
5917 res = hdac_command(sc,
5918 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5919 cad);
5920 kprintf(" unsol=0x%08x", res);
5921 res = hdac_command(sc,
5922 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
5923 kprintf(" sticky=0x%08x\n", res);
5924 }
5925 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
5926 device_printf(dev, " GPO:");
5927 res = hdac_command(sc,
5928 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
5929 kprintf(" data=0x%08x\n", res);
5930 }
5931 if (1 || HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
5932 device_printf(dev, "GPI0:");
5933 res = hdac_command(sc,
5934 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
5935 kprintf(" data=0x%08x", res);
5936 res = hdac_command(sc,
5937 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
5938 kprintf(" enable=0x%08x", res);
5939 res = hdac_command(sc,
5940 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
5941 kprintf(" direction=0x%08x\n", res);
5942 res = hdac_command(sc,
5943 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
5944 device_printf(dev, " wake=0x%08x", res);
5945 res = hdac_command(sc,
5946 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
5947 cad);
5948 kprintf(" unsol=0x%08x", res);
5949 res = hdac_command(sc,
5950 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
5951 kprintf(" sticky=0x%08x\n", res);
5952 }
5953 hdac_unlock(sc);
5954 return (0);
5955 }
5956 #endif
5957 #endif
5958
5959 static void
5960 hdac_attach2(void *arg)
5961 {
5962 struct hdac_softc *sc;
5963 struct hdac_widget *w;
5964 struct hdac_audio_ctl *ctl;
5965 uint32_t quirks_on, quirks_off;
5966 int pcnt, rcnt;
5967 int i;
5968 char status[SND_STATUSLEN];
5969 device_t *devlist = NULL;
5970 int devcount;
5971 struct hdac_devinfo *devinfo = NULL;
5972
5973 sc = (struct hdac_softc *)arg;
5974
5975 hdac_config_fetch(sc, &quirks_on, &quirks_off);
5976
5977 HDA_BOOTVERBOSE(
5978 device_printf(sc->dev, "HDA_DEBUG: HDA Config: on=0x%08x off=0x%08x\n",
5979 quirks_on, quirks_off);
5980 );
5981
5982 hdac_lock(sc);
5983
5984 /* Remove ourselves from the config hooks */
5985 if (sc->intrhook.ich_func != NULL) {
5986 config_intrhook_disestablish(&sc->intrhook);
5987 sc->intrhook.ich_func = NULL;
5988 }
5989
5990 /* Start the corb and rirb engines */
5991 HDA_BOOTVERBOSE(
5992 device_printf(sc->dev, "HDA_DEBUG: Starting CORB Engine...\n");
5993 );
5994 hdac_corb_start(sc);
5995 HDA_BOOTVERBOSE(
5996 device_printf(sc->dev, "HDA_DEBUG: Starting RIRB Engine...\n");
5997 );
5998 hdac_rirb_start(sc);
5999
6000 HDA_BOOTVERBOSE(
6001 device_printf(sc->dev,
6002 "HDA_DEBUG: Enabling controller interrupt...\n");
6003 );
6004 if (sc->polling == 0)
6005 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
6006 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
6007 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
6008 HDAC_GCTL_UNSOL);
6009
6010 DELAY(1000);
6011
6012 HDA_BOOTVERBOSE(
6013 device_printf(sc->dev, "HDA_DEBUG: Scanning HDA codecs...\n");
6014 );
6015 hdac_scan_codecs(sc);
6016
6017 device_get_children(sc->dev, &devlist, &devcount);
6018 for (i = 0; devlist != NULL && i < devcount; i++) {
6019 devinfo = (struct hdac_devinfo *)device_get_ivars(devlist[i]);
6020 if (devinfo != NULL && devinfo->node_type ==
6021 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
6022 break;
6023 } else
6024 devinfo = NULL;
6025 }
6026 if (devlist != NULL)
6027 kfree(devlist, M_TEMP);
6028
6029 if (devinfo == NULL) {
6030 hdac_unlock(sc);
6031 device_printf(sc->dev, "Audio Function Group not found!\n");
6032 hdac_release_resources(sc);
6033 return;
6034 }
6035
6036 HDA_BOOTVERBOSE(
6037 device_printf(sc->dev,
6038 "HDA_DEBUG: Parsing AFG nid=%d cad=%d\n",
6039 devinfo->nid, devinfo->codec->cad);
6040 );
6041 hdac_audio_parse(devinfo);
6042 HDA_BOOTVERBOSE(
6043 device_printf(sc->dev, "HDA_DEBUG: Parsing Ctls...\n");
6044 );
6045 hdac_audio_ctl_parse(devinfo);
6046 HDA_BOOTVERBOSE(
6047 device_printf(sc->dev, "HDA_DEBUG: Parsing vendor patch...\n");
6048 );
6049 hdac_vendor_patch_parse(devinfo);
6050 if (quirks_on != 0)
6051 devinfo->function.audio.quirks |= quirks_on;
6052 if (quirks_off != 0)
6053 devinfo->function.audio.quirks &= ~quirks_off;
6054
6055 /* XXX Disable all DIGITAL path. */
6056 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6057 w = hdac_widget_get(devinfo, i);
6058 if (w == NULL)
6059 continue;
6060 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
6061 w->enable = 0;
6062 continue;
6063 }
6064 /* XXX Disable useless pin ? */
6065 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6066 (w->wclass.pin.config &
6067 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
6068 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
6069 w->enable = 0;
6070 }
6071 i = 0;
6072 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6073 if (ctl->widget == NULL)
6074 continue;
6075 if (ctl->ossmask & SOUND_MASK_DISABLE)
6076 ctl->enable = 0;
6077 w = ctl->widget;
6078 if (w->enable == 0 ||
6079 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6080 ctl->enable = 0;
6081 w = ctl->childwidget;
6082 if (w == NULL)
6083 continue;
6084 if (w->enable == 0 ||
6085 HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6086 ctl->enable = 0;
6087 }
6088
6089 HDA_BOOTVERBOSE(
6090 device_printf(sc->dev, "HDA_DEBUG: Building AFG tree...\n");
6091 );
6092 hdac_audio_build_tree(devinfo);
6093
6094 i = 0;
6095 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6096 if (ctl->ossmask & (SOUND_MASK_SKIP | SOUND_MASK_DISABLE))
6097 ctl->ossmask = 0;
6098 }
6099 HDA_BOOTVERBOSE(
6100 device_printf(sc->dev, "HDA_DEBUG: AFG commit...\n");
6101 );
6102 hdac_audio_commit(devinfo, HDA_COMMIT_ALL);
6103 HDA_BOOTVERBOSE(
6104 device_printf(sc->dev, "HDA_DEBUG: Ctls commit...\n");
6105 );
6106 hdac_audio_ctl_commit(devinfo);
6107
6108 HDA_BOOTVERBOSE(
6109 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_PLAY setup...\n");
6110 );
6111 pcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_PLAY);
6112 HDA_BOOTVERBOSE(
6113 device_printf(sc->dev, "HDA_DEBUG: PCMDIR_REC setup...\n");
6114 );
6115 rcnt = hdac_pcmchannel_setup(devinfo, PCMDIR_REC);
6116
6117 hdac_unlock(sc);
6118 HDA_BOOTVERBOSE(
6119 device_printf(sc->dev,
6120 "HDA_DEBUG: OSS mixer initialization...\n");
6121 );
6122
6123 /*
6124 * There is no point of return after this. If the driver failed,
6125 * so be it. Let the detach procedure do all the cleanup.
6126 */
6127 if (mixer_init(sc->dev, &hdac_audio_ctl_ossmixer_class, devinfo) != 0)
6128 device_printf(sc->dev, "Can't register mixer\n");
6129
6130 if (pcnt > 0)
6131 pcnt = 1;
6132 if (rcnt > 0)
6133 rcnt = 1;
6134
6135 HDA_BOOTVERBOSE(
6136 device_printf(sc->dev,
6137 "HDA_DEBUG: Registering PCM channels...\n");
6138 );
6139 if (pcm_register(sc->dev, devinfo, pcnt, rcnt) != 0)
6140 device_printf(sc->dev, "Can't register PCM\n");
6141
6142 sc->registered++;
6143
6144 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
6145 hdac_dma_alloc(sc, &sc->pos_dma,
6146 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
6147 HDA_BOOTVERBOSE(
6148 device_printf(sc->dev,
6149 "Failed to allocate DMA pos buffer (non-fatal)\n");
6150 );
6151 }
6152
6153 for (i = 0; i < pcnt; i++)
6154 pcm_addchan(sc->dev, PCMDIR_PLAY, &hdac_channel_class, devinfo);
6155 for (i = 0; i < rcnt; i++)
6156 pcm_addchan(sc->dev, PCMDIR_REC, &hdac_channel_class, devinfo);
6157
6158 #ifdef SND_DYNSYSCTL
6159 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6160 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6161 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6162 sysctl_hdac_polling, "I", "Enable polling mode");
6163 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6164 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6165 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
6166 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
6167 "Controller/Jack Sense polling interval (1-1000 ms)");
6168 #ifdef SND_DEBUG
6169 SYSCTL_ADD_PROC(snd_sysctl_tree(sc->dev),
6170 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)), OID_AUTO,
6171 "dump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
6172 sysctl_hdac_dump, "I", "Dump states");
6173 #endif
6174 #endif
6175
6176 ksnprintf(status, SND_STATUSLEN, "at memory 0x%lx irq %ld %s [%s]",
6177 rman_get_start(sc->mem.mem_res), rman_get_start(sc->irq.irq_res),
6178 PCM_KLDSTRING(snd_hda), HDA_DRV_TEST_REV);
6179 pcm_setstatus(sc->dev, status);
6180 device_printf(sc->dev, "<HDA Codec: %s>\n", hdac_codec_name(devinfo));
6181 HDA_BOOTVERBOSE(
6182 device_printf(sc->dev, "<HDA Codec ID: 0x%08x>\n",
6183 hdac_codec_id(devinfo));
6184 );
6185 device_printf(sc->dev, "<HDA Driver Revision: %s>\n",
6186 HDA_DRV_TEST_REV);
6187
6188 HDA_BOOTVERBOSE(
6189 if (devinfo->function.audio.quirks != 0) {
6190 device_printf(sc->dev, "\n");
6191 device_printf(sc->dev, "HDA config/quirks:");
6192 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
6193 if ((devinfo->function.audio.quirks &
6194 hdac_quirks_tab[i].value) ==
6195 hdac_quirks_tab[i].value)
6196 kprintf(" %s", hdac_quirks_tab[i].key);
6197 }
6198 kprintf("\n");
6199 }
6200 device_printf(sc->dev, "\n");
6201 device_printf(sc->dev, "+-------------------+\n");
6202 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
6203 device_printf(sc->dev, "+-------------------+\n");
6204 hdac_dump_nodes(devinfo);
6205 device_printf(sc->dev, "\n");
6206 device_printf(sc->dev, "+------------------------+\n");
6207 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
6208 device_printf(sc->dev, "+------------------------+\n");
6209 device_printf(sc->dev, "\n");
6210 i = 0;
6211 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6212 device_printf(sc->dev, "%3d: nid=%d", i,
6213 (ctl->widget != NULL) ? ctl->widget->nid : -1);
6214 if (ctl->childwidget != NULL)
6215 kprintf(" cnid=%d", ctl->childwidget->nid);
6216 kprintf(" dir=0x%x index=%d "
6217 "ossmask=0x%08x ossdev=%d%s\n",
6218 ctl->dir, ctl->index,
6219 ctl->ossmask, ctl->ossdev,
6220 (ctl->enable == 0) ? " [DISABLED]" : "");
6221 }
6222 device_printf(sc->dev, "\n");
6223 device_printf(sc->dev, "+-----------------------------------+\n");
6224 device_printf(sc->dev, "| DUMPING HDA AUDIO/VOLUME CONTROLS |\n");
6225 device_printf(sc->dev, "+-----------------------------------+\n");
6226 hdac_dump_ctls(devinfo, "Master Volume (OSS: vol)", SOUND_MASK_VOLUME);
6227 hdac_dump_ctls(devinfo, "PCM Volume (OSS: pcm)", SOUND_MASK_PCM);
6228 hdac_dump_ctls(devinfo, "CD Volume (OSS: cd)", SOUND_MASK_CD);
6229 hdac_dump_ctls(devinfo, "Microphone Volume (OSS: mic)", SOUND_MASK_MIC);
6230 hdac_dump_ctls(devinfo, "Line-in Volume (OSS: line)", SOUND_MASK_LINE);
6231 hdac_dump_ctls(devinfo, "Recording Level (OSS: rec)", SOUND_MASK_RECLEV);
6232 hdac_dump_ctls(devinfo, "Speaker/Beep (OSS: speaker)", SOUND_MASK_SPEAKER);
6233 hdac_dump_ctls(devinfo, NULL, 0);
6234 hdac_dump_dac(devinfo);
6235 hdac_dump_adc(devinfo);
6236 device_printf(sc->dev, "\n");
6237 device_printf(sc->dev, "+--------------------------------------+\n");
6238 device_printf(sc->dev, "| DUMPING PCM Playback/Record Channels |\n");
6239 device_printf(sc->dev, "+--------------------------------------+\n");
6240 hdac_dump_pcmchannels(sc, pcnt, rcnt);
6241 );
6242
6243 if (sc->polling != 0) {
6244 hdac_lock(sc);
6245 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
6246 hdac_unlock(sc);
6247 }
6248 }
6249
6250 /****************************************************************************
6251 * int hdac_detach(device_t)
6252 *
6253 * Detach and free up resources utilized by the hdac device.
6254 ****************************************************************************/
6255 static int
6256 hdac_detach(device_t dev)
6257 {
6258 struct hdac_softc *sc = NULL;
6259 struct hdac_devinfo *devinfo = NULL;
6260 int err;
6261
6262 devinfo = (struct hdac_devinfo *)pcm_getdevinfo(dev);
6263 if (devinfo != NULL && devinfo->codec != NULL)
6264 sc = devinfo->codec->sc;
6265 if (sc == NULL)
6266 return (0);
6267
6268 if (sc->registered > 0) {
6269 err = pcm_unregister(dev);
6270 if (err != 0)
6271 return (err);
6272 }
6273
6274 hdac_release_resources(sc);
6275
6276 return (0);
6277 }
6278
6279 static device_method_t hdac_methods[] = {
6280 /* device interface */
6281 DEVMETHOD(device_probe, hdac_probe),
6282 DEVMETHOD(device_attach, hdac_attach),
6283 DEVMETHOD(device_detach, hdac_detach),
6284 { 0, 0 }
6285 };
6286
6287 static driver_t hdac_driver = {
6288 "pcm",
6289 hdac_methods,
6290 PCM_SOFTC_SIZE,
6291 };
6292
6293 DRIVER_MODULE(snd_hda, pci, hdac_driver, pcm_devclass, 0, 0);
6294 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
6295 MODULE_VERSION(snd_hda, 1);
DragonFly vkernel multiprocessor port