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Nuke device_ptr_t, USBBASEDEVICE, USBDEVNAME(), USBDEVUNIT(), USBGETSOFTC(),
[dragonfly/vkernel-mp.git] / sys / dev / misc / ppc / ppc.c
blobc8d77fb65d16cfd91bf14ecc0950b5ad9d2c727b
1 /*-
2 * Copyright (c) 2001 Alcove - Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/isa/ppc.c,v 1.26.2.5 2001/10/02 05:21:45 nsouch Exp $
27 * $DragonFly: src/sys/dev/misc/ppc/ppc.c,v 1.14 2006/12/23 00:26:18 swildner Exp $
28 *
29 */
30
31 #include "opt_ppc.h"
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/malloc.h>
38 #include <sys/rman.h>
39 #include <sys/thread2.h>
40
41 #include <vm/vm.h>
42 #include <vm/pmap.h>
43 #include <machine/clock.h>
44 #include <machine/vmparam.h>
45
46 #include <bus/isa/isareg.h>
47 #include <bus/isa/isavar.h>
48
49 #include <bus/ppbus/ppbconf.h>
50 #include <bus/ppbus/ppb_msq.h>
51
52 #include "ppcreg.h"
53
54 #include "ppbus_if.h"
55
56 #define LOG_PPC(function, ppc, string) \
57 if (bootverbose) kprintf("%s: %s\n", function, string)
58
59
60 #define DEVTOSOFTC(dev) ((struct ppc_data *)device_get_softc(dev))
61
62 devclass_t ppc_devclass;
63
64 static int ppc_probe(device_t dev);
65 static int ppc_attach(device_t dev);
66 static int ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val);
67
68 static void ppc_reset_epp(device_t);
69 static void ppc_ecp_sync(device_t);
70 static void ppcintr(void *arg);
71
72 static int ppc_exec_microseq(device_t, struct ppb_microseq **);
73 static int ppc_setmode(device_t, int);
74
75 static int ppc_read(device_t, char *, int, int);
76 static int ppc_write(device_t, char *, int, int);
77
78 static u_char ppc_io(device_t, int, u_char *, int, u_char);
79
80 static int ppc_setup_intr(device_t, device_t, struct resource *, int,
81 void (*)(void *), void *, void **, lwkt_serialize_t);
82 static int ppc_teardown_intr(device_t, device_t, struct resource *, void *);
83
84 static device_method_t ppc_methods[] = {
85 /* device interface */
86 DEVMETHOD(device_probe, ppc_probe),
87 DEVMETHOD(device_attach, ppc_attach),
88
89 /* bus interface */
90 DEVMETHOD(bus_read_ivar, ppc_read_ivar),
91 DEVMETHOD(bus_setup_intr, ppc_setup_intr),
92 DEVMETHOD(bus_teardown_intr, ppc_teardown_intr),
93 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
94
95 /* ppbus interface */
96 DEVMETHOD(ppbus_io, ppc_io),
97 DEVMETHOD(ppbus_exec_microseq, ppc_exec_microseq),
98 DEVMETHOD(ppbus_reset_epp, ppc_reset_epp),
99 DEVMETHOD(ppbus_setmode, ppc_setmode),
100 DEVMETHOD(ppbus_ecp_sync, ppc_ecp_sync),
101 DEVMETHOD(ppbus_read, ppc_read),
102 DEVMETHOD(ppbus_write, ppc_write),
103
104 { 0, 0 }
105 };
106
107 static driver_t ppc_driver = {
108 "ppc",
109 ppc_methods,
110 sizeof(struct ppc_data),
111 };
112
113 static char *ppc_models[] = {
114 "SMC-like", "SMC FDC37C665GT", "SMC FDC37C666GT", "PC87332", "PC87306",
115 "82091AA", "Generic", "W83877F", "W83877AF", "Winbond", "PC87334",
116 "SMC FDC37C935", "PC87303", 0
117 };
118
119 /* list of available modes */
120 static char *ppc_avms[] = {
121 "COMPATIBLE", "NIBBLE-only", "PS2-only", "PS2/NIBBLE", "EPP-only",
122 "EPP/NIBBLE", "EPP/PS2", "EPP/PS2/NIBBLE", "ECP-only",
123 "ECP/NIBBLE", "ECP/PS2", "ECP/PS2/NIBBLE", "ECP/EPP",
124 "ECP/EPP/NIBBLE", "ECP/EPP/PS2", "ECP/EPP/PS2/NIBBLE", 0
125 };
126
127 /* list of current executing modes
128 * Note that few modes do not actually exist.
129 */
130 static char *ppc_modes[] = {
131 "COMPATIBLE", "NIBBLE", "PS/2", "PS/2", "EPP",
132 "EPP", "EPP", "EPP", "ECP",
133 "ECP", "ECP+PS2", "ECP+PS2", "ECP+EPP",
134 "ECP+EPP", "ECP+EPP", "ECP+EPP", 0
135 };
136
137 static char *ppc_epp_protocol[] = { " (EPP 1.9)", " (EPP 1.7)", 0 };
138
139 #ifdef __i386__
140 /*
141 * BIOS printer list - used by BIOS probe.
142 */
143 #define BIOS_PPC_PORTS 0x408
144 #define BIOS_PORTS (short *)(KERNBASE+BIOS_PPC_PORTS)
145 #define BIOS_MAX_PPC 4
146 #endif
147
148 /*
149 * ppc_ecp_sync() XXX
150 */
151 static void
152 ppc_ecp_sync(device_t dev)
153 {
154 int i, r;
155 struct ppc_data *ppc = DEVTOSOFTC(dev);
156
157 if (!(ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_dtm & PPB_ECP))
158 return;
159
160 r = r_ecr(ppc);
161 if ((r & 0xe0) != PPC_ECR_EPP)
162 return;
163
164 for (i = 0; i < 100; i++) {
165 r = r_ecr(ppc);
166 if (r & 0x1)
167 return;
168 DELAY(100);
169 }
170
171 kprintf("ppc%d: ECP sync failed as data still " \
172 "present in FIFO.\n", ppc->ppc_unit);
173
174 return;
175 }
176
177 /*
178 * ppc_detect_fifo()
179 *
180 * Detect parallel port FIFO
181 */
182 static int
183 ppc_detect_fifo(struct ppc_data *ppc)
184 {
185 char ecr_sav;
186 char ctr_sav, ctr, cc;
187 short i;
188
189 /* save registers */
190 ecr_sav = r_ecr(ppc);
191 ctr_sav = r_ctr(ppc);
192
193 /* enter ECP configuration mode, no interrupt, no DMA */
194 w_ecr(ppc, 0xf4);
195
196 /* read PWord size - transfers in FIFO mode must be PWord aligned */
197 ppc->ppc_pword = (r_cnfgA(ppc) & PPC_PWORD_MASK);
198
199 /* XXX 16 and 32 bits implementations not supported */
200 if (ppc->ppc_pword != PPC_PWORD_8) {
201 LOG_PPC(__func__, ppc, "PWord not supported");
202 goto error;
203 }
204
205 w_ecr(ppc, 0x34); /* byte mode, no interrupt, no DMA */
206 ctr = r_ctr(ppc);
207 w_ctr(ppc, ctr | PCD); /* set direction to 1 */
208
209 /* enter ECP test mode, no interrupt, no DMA */
210 w_ecr(ppc, 0xd4);
211
212 /* flush the FIFO */
213 for (i=0; i<1024; i++) {
214 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
215 break;
216 cc = r_fifo(ppc);
217 }
218
219 if (i >= 1024) {
220 LOG_PPC(__func__, ppc, "can't flush FIFO");
221 goto error;
222 }
223
224 /* enable interrupts, no DMA */
225 w_ecr(ppc, 0xd0);
226
227 /* determine readIntrThreshold
228 * fill the FIFO until serviceIntr is set
229 */
230 for (i=0; i<1024; i++) {
231 w_fifo(ppc, (char)i);
232 if (!ppc->ppc_rthr && (r_ecr(ppc) & PPC_SERVICE_INTR)) {
233 /* readThreshold reached */
234 ppc->ppc_rthr = i+1;
235 }
236 if (r_ecr(ppc) & PPC_FIFO_FULL) {
237 ppc->ppc_fifo = i+1;
238 break;
239 }
240 }
241
242 if (i >= 1024) {
243 LOG_PPC(__func__, ppc, "can't fill FIFO");
244 goto error;
245 }
246
247 w_ecr(ppc, 0xd4); /* test mode, no interrupt, no DMA */
248 w_ctr(ppc, ctr & ~PCD); /* set direction to 0 */
249 w_ecr(ppc, 0xd0); /* enable interrupts */
250
251 /* determine writeIntrThreshold
252 * empty the FIFO until serviceIntr is set
253 */
254 for (i=ppc->ppc_fifo; i>0; i--) {
255 if (r_fifo(ppc) != (char)(ppc->ppc_fifo-i)) {
256 LOG_PPC(__func__, ppc, "invalid data in FIFO");
257 goto error;
258 }
259 if (r_ecr(ppc) & PPC_SERVICE_INTR) {
260 /* writeIntrThreshold reached */
261 ppc->ppc_wthr = ppc->ppc_fifo - i+1;
262 }
263 /* if FIFO empty before the last byte, error */
264 if (i>1 && (r_ecr(ppc) & PPC_FIFO_EMPTY)) {
265 LOG_PPC(__func__, ppc, "data lost in FIFO");
266 goto error;
267 }
268 }
269
270 /* FIFO must be empty after the last byte */
271 if (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
272 LOG_PPC(__func__, ppc, "can't empty the FIFO");
273 goto error;
274 }
275
276 w_ctr(ppc, ctr_sav);
277 w_ecr(ppc, ecr_sav);
278
279 return (0);
280
281 error:
282 w_ctr(ppc, ctr_sav);
283 w_ecr(ppc, ecr_sav);
284
285 return (EINVAL);
286 }
287
288 static int
289 ppc_detect_port(struct ppc_data *ppc)
290 {
291
292 w_ctr(ppc, 0x0c); /* To avoid missing PS2 ports */
293 w_dtr(ppc, 0xaa);
294 if (r_dtr(ppc) != 0xaa)
295 return (0);
296
297 return (1);
298 }
299
300 /*
301 * EPP timeout, according to the PC87332 manual
302 * Semantics of clearing EPP timeout bit.
303 * PC87332 - reading SPP_STR does it...
304 * SMC - write 1 to EPP timeout bit XXX
305 * Others - (?) write 0 to EPP timeout bit
306 */
307 static void
308 ppc_reset_epp_timeout(struct ppc_data *ppc)
309 {
310 char r;
311
312 r = r_str(ppc);
313 w_str(ppc, r | 0x1);
314 w_str(ppc, r & 0xfe);
315
316 return;
317 }
318
319 static int
320 ppc_check_epp_timeout(struct ppc_data *ppc)
321 {
322 ppc_reset_epp_timeout(ppc);
323
324 return (!(r_str(ppc) & TIMEOUT));
325 }
326
327 /*
328 * Configure current operating mode
329 */
330 static int
331 ppc_generic_setmode(struct ppc_data *ppc, int mode)
332 {
333 u_char ecr = 0;
334
335 /* check if mode is available */
336 if (mode && !(ppc->ppc_avm & mode))
337 return (EINVAL);
338
339 /* if ECP mode, configure ecr register */
340 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
341 /* return to byte mode (keeping direction bit),
342 * no interrupt, no DMA to be able to change to
343 * ECP
344 */
345 w_ecr(ppc, PPC_ECR_RESET);
346 ecr = PPC_DISABLE_INTR;
347
348 if (mode & PPB_EPP)
349 return (EINVAL);
350 else if (mode & PPB_ECP)
351 /* select ECP mode */
352 ecr |= PPC_ECR_ECP;
353 else if (mode & PPB_PS2)
354 /* select PS2 mode with ECP */
355 ecr |= PPC_ECR_PS2;
356 else
357 /* select COMPATIBLE/NIBBLE mode */
358 ecr |= PPC_ECR_STD;
359
360 w_ecr(ppc, ecr);
361 }
362
363 ppc->ppc_mode = mode;
364
365 return (0);
366 }
367
368 /*
369 * The ppc driver is free to choose options like FIFO or DMA
370 * if ECP mode is available.
371 *
372 * The 'RAW' option allows the upper drivers to force the ppc mode
373 * even with FIFO, DMA available.
374 */
375 static int
376 ppc_smclike_setmode(struct ppc_data *ppc, int mode)
377 {
378 u_char ecr = 0;
379
380 /* check if mode is available */
381 if (mode && !(ppc->ppc_avm & mode))
382 return (EINVAL);
383
384 /* if ECP mode, configure ecr register */
385 if ((ppc->ppc_avm & PPB_ECP) || (ppc->ppc_dtm & PPB_ECP)) {
386 /* return to byte mode (keeping direction bit),
387 * no interrupt, no DMA to be able to change to
388 * ECP or EPP mode
389 */
390 w_ecr(ppc, PPC_ECR_RESET);
391 ecr = PPC_DISABLE_INTR;
392
393 if (mode & PPB_EPP)
394 /* select EPP mode */
395 ecr |= PPC_ECR_EPP;
396 else if (mode & PPB_ECP)
397 /* select ECP mode */
398 ecr |= PPC_ECR_ECP;
399 else if (mode & PPB_PS2)
400 /* select PS2 mode with ECP */
401 ecr |= PPC_ECR_PS2;
402 else
403 /* select COMPATIBLE/NIBBLE mode */
404 ecr |= PPC_ECR_STD;
405
406 w_ecr(ppc, ecr);
407 }
408
409 ppc->ppc_mode = mode;
410
411 return (0);
412 }
413
414 #ifdef PPC_PROBE_CHIPSET
415 /*
416 * ppc_pc873xx_detect
417 *
418 * Probe for a Natsemi PC873xx-family part.
419 *
420 * References in this function are to the National Semiconductor
421 * PC87332 datasheet TL/C/11930, May 1995 revision.
422 */
423 static int pc873xx_basetab[] = {0x0398, 0x026e, 0x015c, 0x002e, 0};
424 static int pc873xx_porttab[] = {0x0378, 0x03bc, 0x0278, 0};
425 static int pc873xx_irqtab[] = {5, 7, 5, 0};
426
427 static int pc873xx_regstab[] = {
428 PC873_FER, PC873_FAR, PC873_PTR,
429 PC873_FCR, PC873_PCR, PC873_PMC,
430 PC873_TUP, PC873_SID, PC873_PNP0,
431 PC873_PNP1, PC873_LPTBA, -1
432 };
433
434 static char *pc873xx_rnametab[] = {
435 "FER", "FAR", "PTR", "FCR", "PCR",
436 "PMC", "TUP", "SID", "PNP0", "PNP1",
437 "LPTBA", NULL
438 };
439
440 static int
441 ppc_pc873xx_detect(struct ppc_data *ppc, int chipset_mode) /* XXX mode never forced */
442 {
443 static int index = 0;
444 int idport, irq;
445 int ptr, pcr, val, i;
446
447 while ((idport = pc873xx_basetab[index++])) {
448
449 /* XXX should check first to see if this location is already claimed */
450
451 /*
452 * Pull the 873xx through the power-on ID cycle (2.2,1.).
453 * We can't use this to locate the chip as it may already have
454 * been used by the BIOS.
455 */
456 (void)inb(idport); (void)inb(idport);
457 (void)inb(idport); (void)inb(idport);
458
459 /*
460 * Read the SID byte. Possible values are :
461 *
462 * 01010xxx PC87334
463 * 0001xxxx PC87332
464 * 01110xxx PC87306
465 * 00110xxx PC87303
466 */
467 outb(idport, PC873_SID);
468 val = inb(idport + 1);
469 if ((val & 0xf0) == 0x10) {
470 ppc->ppc_model = NS_PC87332;
471 } else if ((val & 0xf8) == 0x70) {
472 ppc->ppc_model = NS_PC87306;
473 } else if ((val & 0xf8) == 0x50) {
474 ppc->ppc_model = NS_PC87334;
475 } else if ((val & 0xf8) == 0x40) { /* Should be 0x30 by the
476 documentation, but probing
477 yielded 0x40... */
478 ppc->ppc_model = NS_PC87303;
479 } else {
480 if (bootverbose && (val != 0xff))
481 kprintf("PC873xx probe at 0x%x got unknown ID 0x%x\n", idport, val);
482 continue ; /* not recognised */
483 }
484
485 /* print registers */
486 if (bootverbose) {
487 kprintf("PC873xx");
488 for (i=0; pc873xx_regstab[i] != -1; i++) {
489 outb(idport, pc873xx_regstab[i]);
490 kprintf(" %s=0x%x", pc873xx_rnametab[i],
491 inb(idport + 1) & 0xff);
492 }
493 kprintf("\n");
494 }
495
496 /*
497 * We think we have one. Is it enabled and where we want it to be?
498 */
499 outb(idport, PC873_FER);
500 val = inb(idport + 1);
501 if (!(val & PC873_PPENABLE)) {
502 if (bootverbose)
503 kprintf("PC873xx parallel port disabled\n");
504 continue;
505 }
506 outb(idport, PC873_FAR);
507 val = inb(idport + 1);
508 /* XXX we should create a driver instance for every port found */
509 if (pc873xx_porttab[val & 0x3] != ppc->ppc_base) {
510
511 /* First try to change the port address to that requested... */
512
513 switch(ppc->ppc_base) {
514 case 0x378:
515 val &= 0xfc;
516 break;
517
518 case 0x3bc:
519 val &= 0xfd;
520 break;
521
522 case 0x278:
523 val &= 0xfe;
524 break;
525
526 default:
527 val &= 0xfd;
528 break;
529 }
530
531 outb(idport, PC873_FAR);
532 outb(idport + 1, val);
533 outb(idport + 1, val);
534
535 /* Check for success by reading back the value we supposedly
536 wrote and comparing...*/
537
538 outb(idport, PC873_FAR);
539 val = inb(idport + 1) & 0x3;
540
541 /* If we fail, report the failure... */
542
543 if (pc873xx_porttab[val] != ppc->ppc_base) {
544 if (bootverbose)
545 kprintf("PC873xx at 0x%x not for driver at port 0x%x\n",
546 pc873xx_porttab[val], ppc->ppc_base);
547 }
548 continue;
549 }
550
551 outb(idport, PC873_PTR);
552 ptr = inb(idport + 1);
553
554 /* get irq settings */
555 if (ppc->ppc_base == 0x378)
556 irq = (ptr & PC873_LPTBIRQ7) ? 7 : 5;
557 else
558 irq = pc873xx_irqtab[val];
559
560 if (bootverbose)
561 kprintf("PC873xx irq %d at 0x%x\n", irq, ppc->ppc_base);
562
563 /*
564 * Check if irq settings are correct
565 */
566 if (irq != ppc->ppc_irq) {
567 /*
568 * If the chipset is not locked and base address is 0x378,
569 * we have another chance
570 */
571 if (ppc->ppc_base == 0x378 && !(ptr & PC873_CFGLOCK)) {
572 if (ppc->ppc_irq == 7) {
573 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
574 outb(idport + 1, (ptr | PC873_LPTBIRQ7));
575 } else {
576 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
577 outb(idport + 1, (ptr & ~PC873_LPTBIRQ7));
578 }
579 if (bootverbose)
580 kprintf("PC873xx irq set to %d\n", ppc->ppc_irq);
581 } else {
582 if (bootverbose)
583 kprintf("PC873xx sorry, can't change irq setting\n");
584 }
585 } else {
586 if (bootverbose)
587 kprintf("PC873xx irq settings are correct\n");
588 }
589
590 outb(idport, PC873_PCR);
591 pcr = inb(idport + 1);
592
593 if ((ptr & PC873_CFGLOCK) || !chipset_mode) {
594 if (bootverbose)
595 kprintf("PC873xx %s", (ptr & PC873_CFGLOCK)?"locked":"unlocked");
596
597 ppc->ppc_avm |= PPB_NIBBLE;
598 if (bootverbose)
599 kprintf(", NIBBLE");
600
601 if (pcr & PC873_EPPEN) {
602 ppc->ppc_avm |= PPB_EPP;
603
604 if (bootverbose)
605 kprintf(", EPP");
606
607 if (pcr & PC873_EPP19)
608 ppc->ppc_epp = EPP_1_9;
609 else
610 ppc->ppc_epp = EPP_1_7;
611
612 if ((ppc->ppc_model == NS_PC87332) && bootverbose) {
613 outb(idport, PC873_PTR);
614 ptr = inb(idport + 1);
615 if (ptr & PC873_EPPRDIR)
616 kprintf(", Regular mode");
617 else
618 kprintf(", Automatic mode");
619 }
620 } else if (pcr & PC873_ECPEN) {
621 ppc->ppc_avm |= PPB_ECP;
622 if (bootverbose)
623 kprintf(", ECP");
624
625 if (pcr & PC873_ECPCLK) { /* XXX */
626 ppc->ppc_avm |= PPB_PS2;
627 if (bootverbose)
628 kprintf(", PS/2");
629 }
630 } else {
631 outb(idport, PC873_PTR);
632 ptr = inb(idport + 1);
633 if (ptr & PC873_EXTENDED) {
634 ppc->ppc_avm |= PPB_SPP;
635 if (bootverbose)
636 kprintf(", SPP");
637 }
638 }
639 } else {
640 if (bootverbose)
641 kprintf("PC873xx unlocked");
642
643 if (chipset_mode & PPB_ECP) {
644 if ((chipset_mode & PPB_EPP) && bootverbose)
645 kprintf(", ECP+EPP not supported");
646
647 pcr &= ~PC873_EPPEN;
648 pcr |= (PC873_ECPEN | PC873_ECPCLK); /* XXX */
649 outb(idport + 1, pcr);
650 outb(idport + 1, pcr);
651
652 if (bootverbose)
653 kprintf(", ECP");
654
655 } else if (chipset_mode & PPB_EPP) {
656 pcr &= ~(PC873_ECPEN | PC873_ECPCLK);
657 pcr |= (PC873_EPPEN | PC873_EPP19);
658 outb(idport + 1, pcr);
659 outb(idport + 1, pcr);
660
661 ppc->ppc_epp = EPP_1_9; /* XXX */
662
663 if (bootverbose)
664 kprintf(", EPP1.9");
665
666 /* enable automatic direction turnover */
667 if (ppc->ppc_model == NS_PC87332) {
668 outb(idport, PC873_PTR);
669 ptr = inb(idport + 1);
670 ptr &= ~PC873_EPPRDIR;
671 outb(idport + 1, ptr);
672 outb(idport + 1, ptr);
673
674 if (bootverbose)
675 kprintf(", Automatic mode");
676 }
677 } else {
678 pcr &= ~(PC873_ECPEN | PC873_ECPCLK | PC873_EPPEN);
679 outb(idport + 1, pcr);
680 outb(idport + 1, pcr);
681
682 /* configure extended bit in PTR */
683 outb(idport, PC873_PTR);
684 ptr = inb(idport + 1);
685
686 if (chipset_mode & PPB_PS2) {
687 ptr |= PC873_EXTENDED;
688
689 if (bootverbose)
690 kprintf(", PS/2");
691
692 } else {
693 /* default to NIBBLE mode */
694 ptr &= ~PC873_EXTENDED;
695
696 if (bootverbose)
697 kprintf(", NIBBLE");
698 }
699 outb(idport + 1, ptr);
700 outb(idport + 1, ptr);
701 }
702
703 ppc->ppc_avm = chipset_mode;
704 }
705
706 if (bootverbose)
707 kprintf("\n");
708
709 ppc->ppc_type = PPC_TYPE_GENERIC;
710 ppc_generic_setmode(ppc, chipset_mode);
711
712 return(chipset_mode);
713 }
714 return(-1);
715 }
716
717 /*
718 * ppc_smc37c66xgt_detect
719 *
720 * SMC FDC37C66xGT configuration.
721 */
722 static int
723 ppc_smc37c66xgt_detect(struct ppc_data *ppc, int chipset_mode)
724 {
725 int i;
726 u_char r;
727 int type = -1;
728 int csr = SMC66x_CSR; /* initial value is 0x3F0 */
729
730 int port_address[] = { -1 /* disabled */ , 0x3bc, 0x378, 0x278 };
731
732
733 #define cio csr+1 /* config IO port is either 0x3F1 or 0x371 */
734
735 /*
736 * Detection: enter configuration mode and read CRD register.
737 */
738
739 crit_enter();
740 outb(csr, SMC665_iCODE);
741 outb(csr, SMC665_iCODE);
742 crit_exit();
743
744 outb(csr, 0xd);
745 if (inb(cio) == 0x65) {
746 type = SMC_37C665GT;
747 goto config;
748 }
749
750 for (i = 0; i < 2; i++) {
751 crit_enter();
752 outb(csr, SMC666_iCODE);
753 outb(csr, SMC666_iCODE);
754 crit_exit();
755
756 outb(csr, 0xd);
757 if (inb(cio) == 0x66) {
758 type = SMC_37C666GT;
759 break;
760 }
761
762 /* Another chance, CSR may be hard-configured to be at 0x370 */
763 csr = SMC666_CSR;
764 }
765
766 config:
767 /*
768 * If chipset not found, do not continue.
769 */
770 if (type == -1)
771 return (-1);
772
773 /* select CR1 */
774 outb(csr, 0x1);
775
776 /* read the port's address: bits 0 and 1 of CR1 */
777 r = inb(cio) & SMC_CR1_ADDR;
778 if (port_address[(int)r] != ppc->ppc_base)
779 return (-1);
780
781 ppc->ppc_model = type;
782
783 /*
784 * CR1 and CR4 registers bits 3 and 0/1 for mode configuration
785 * If SPP mode is detected, try to set ECP+EPP mode
786 */
787
788 if (bootverbose) {
789 outb(csr, 0x1);
790 kprintf("ppc%d: SMC registers CR1=0x%x", ppc->ppc_unit,
791 inb(cio) & 0xff);
792
793 outb(csr, 0x4);
794 kprintf(" CR4=0x%x", inb(cio) & 0xff);
795 }
796
797 /* select CR1 */
798 outb(csr, 0x1);
799
800 if (!chipset_mode) {
801 /* autodetect mode */
802
803 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
804 if (type == SMC_37C666GT) {
805 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
806 if (bootverbose)
807 kprintf(" configuration hardwired, supposing " \
808 "ECP+EPP SPP");
809
810 } else
811 if ((inb(cio) & SMC_CR1_MODE) == 0) {
812 /* already in extended parallel port mode, read CR4 */
813 outb(csr, 0x4);
814 r = (inb(cio) & SMC_CR4_EMODE);
815
816 switch (r) {
817 case SMC_SPP:
818 ppc->ppc_avm |= PPB_SPP;
819 if (bootverbose)
820 kprintf(" SPP");
821 break;
822
823 case SMC_EPPSPP:
824 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
825 if (bootverbose)
826 kprintf(" EPP SPP");
827 break;
828
829 case SMC_ECP:
830 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
831 if (bootverbose)
832 kprintf(" ECP SPP");
833 break;
834
835 case SMC_ECPEPP:
836 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
837 if (bootverbose)
838 kprintf(" ECP+EPP SPP");
839 break;
840 }
841 } else {
842 /* not an extended port mode */
843 ppc->ppc_avm |= PPB_SPP;
844 if (bootverbose)
845 kprintf(" SPP");
846 }
847
848 } else {
849 /* mode forced */
850 ppc->ppc_avm = chipset_mode;
851
852 /* 666GT is ~certainly~ hardwired to an extended ECP+EPP mode */
853 if (type == SMC_37C666GT)
854 goto end_detect;
855
856 r = inb(cio);
857 if ((chipset_mode & (PPB_ECP | PPB_EPP)) == 0) {
858 /* do not use ECP when the mode is not forced to */
859 outb(cio, r | SMC_CR1_MODE);
860 if (bootverbose)
861 kprintf(" SPP");
862 } else {
863 /* an extended mode is selected */
864 outb(cio, r & ~SMC_CR1_MODE);
865
866 /* read CR4 register and reset mode field */
867 outb(csr, 0x4);
868 r = inb(cio) & ~SMC_CR4_EMODE;
869
870 if (chipset_mode & PPB_ECP) {
871 if (chipset_mode & PPB_EPP) {
872 outb(cio, r | SMC_ECPEPP);
873 if (bootverbose)
874 kprintf(" ECP+EPP");
875 } else {
876 outb(cio, r | SMC_ECP);
877 if (bootverbose)
878 kprintf(" ECP");
879 }
880 } else {
881 /* PPB_EPP is set */
882 outb(cio, r | SMC_EPPSPP);
883 if (bootverbose)
884 kprintf(" EPP SPP");
885 }
886 }
887 ppc->ppc_avm = chipset_mode;
888 }
889
890 /* set FIFO threshold to 16 */
891 if (ppc->ppc_avm & PPB_ECP) {
892 /* select CRA */
893 outb(csr, 0xa);
894 outb(cio, 16);
895 }
896
897 end_detect:
898
899 if (bootverbose)
900 kprintf ("\n");
901
902 if (ppc->ppc_avm & PPB_EPP) {
903 /* select CR4 */
904 outb(csr, 0x4);
905 r = inb(cio);
906
907 /*
908 * Set the EPP protocol...
909 * Low=EPP 1.9 (1284 standard) and High=EPP 1.7
910 */
911 if (ppc->ppc_epp == EPP_1_9)
912 outb(cio, (r & ~SMC_CR4_EPPTYPE));
913 else
914 outb(cio, (r | SMC_CR4_EPPTYPE));
915 }
916
917 /* end config mode */
918 outb(csr, 0xaa);
919
920 ppc->ppc_type = PPC_TYPE_SMCLIKE;
921 ppc_smclike_setmode(ppc, chipset_mode);
922
923 return (chipset_mode);
924 }
925
926 /*
927 * SMC FDC37C935 configuration
928 * Found on many Alpha machines
929 */
930 static int
931 ppc_smc37c935_detect(struct ppc_data *ppc, int chipset_mode)
932 {
933 int type = -1;
934
935 crit_enter();
936 outb(SMC935_CFG, 0x55); /* enter config mode */
937 outb(SMC935_CFG, 0x55);
938 crit_exit();
939
940 outb(SMC935_IND, SMC935_ID); /* check device id */
941 if (inb(SMC935_DAT) == 0x2)
942 type = SMC_37C935;
943
944 if (type == -1) {
945 outb(SMC935_CFG, 0xaa); /* exit config mode */
946 return (-1);
947 }
948
949 ppc->ppc_model = type;
950
951 outb(SMC935_IND, SMC935_LOGDEV); /* select parallel port, */
952 outb(SMC935_DAT, 3); /* which is logical device 3 */
953
954 /* set io port base */
955 outb(SMC935_IND, SMC935_PORTHI);
956 outb(SMC935_DAT, (u_char)((ppc->ppc_base & 0xff00) >> 8));
957 outb(SMC935_IND, SMC935_PORTLO);
958 outb(SMC935_DAT, (u_char)(ppc->ppc_base & 0xff));
959
960 if (!chipset_mode)
961 ppc->ppc_avm = PPB_COMPATIBLE; /* default mode */
962 else {
963 ppc->ppc_avm = chipset_mode;
964 outb(SMC935_IND, SMC935_PPMODE);
965 outb(SMC935_DAT, SMC935_CENT); /* start in compatible mode */
966
967 /* SPP + EPP or just plain SPP */
968 if (chipset_mode & (PPB_SPP)) {
969 if (chipset_mode & PPB_EPP) {
970 if (ppc->ppc_epp == EPP_1_9) {
971 outb(SMC935_IND, SMC935_PPMODE);
972 outb(SMC935_DAT, SMC935_EPP19SPP);
973 }
974 if (ppc->ppc_epp == EPP_1_7) {
975 outb(SMC935_IND, SMC935_PPMODE);
976 outb(SMC935_DAT, SMC935_EPP17SPP);
977 }
978 } else {
979 outb(SMC935_IND, SMC935_PPMODE);
980 outb(SMC935_DAT, SMC935_SPP);
981 }
982 }
983
984 /* ECP + EPP or just plain ECP */
985 if (chipset_mode & PPB_ECP) {
986 if (chipset_mode & PPB_EPP) {
987 if (ppc->ppc_epp == EPP_1_9) {
988 outb(SMC935_IND, SMC935_PPMODE);
989 outb(SMC935_DAT, SMC935_ECPEPP19);
990 }
991 if (ppc->ppc_epp == EPP_1_7) {
992 outb(SMC935_IND, SMC935_PPMODE);
993 outb(SMC935_DAT, SMC935_ECPEPP17);
994 }
995 } else {
996 outb(SMC935_IND, SMC935_PPMODE);
997 outb(SMC935_DAT, SMC935_ECP);
998 }
999 }
1000 }
1001
1002 outb(SMC935_CFG, 0xaa); /* exit config mode */
1003
1004 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1005 ppc_smclike_setmode(ppc, chipset_mode);
1006
1007 return (chipset_mode);
1008 }
1009
1010 /*
1011 * Winbond W83877F stuff
1012 *
1013 * EFER: extended function enable register
1014 * EFIR: extended function index register
1015 * EFDR: extended function data register
1016 */
1017 #define efir ((efer == 0x250) ? 0x251 : 0x3f0)
1018 #define efdr ((efer == 0x250) ? 0x252 : 0x3f1)
1019
1020 static int w83877f_efers[] = { 0x250, 0x3f0, 0x3f0, 0x250 };
1021 static int w83877f_keys[] = { 0x89, 0x86, 0x87, 0x88 };
1022 static int w83877f_keyiter[] = { 1, 2, 2, 1 };
1023 static int w83877f_hefs[] = { WINB_HEFERE, WINB_HEFRAS, WINB_HEFERE | WINB_HEFRAS, 0 };
1024
1025 static int
1026 ppc_w83877f_detect(struct ppc_data *ppc, int chipset_mode)
1027 {
1028 int i, j, efer;
1029 unsigned char r, hefere, hefras;
1030
1031 for (i = 0; i < 4; i ++) {
1032 /* first try to enable configuration registers */
1033 efer = w83877f_efers[i];
1034
1035 /* write the key to the EFER */
1036 for (j = 0; j < w83877f_keyiter[i]; j ++)
1037 outb (efer, w83877f_keys[i]);
1038
1039 /* then check HEFERE and HEFRAS bits */
1040 outb (efir, 0x0c);
1041 hefere = inb(efdr) & WINB_HEFERE;
1042
1043 outb (efir, 0x16);
1044 hefras = inb(efdr) & WINB_HEFRAS;
1045
1046 /*
1047 * HEFRAS HEFERE
1048 * 0 1 write 89h to 250h (power-on default)
1049 * 1 0 write 86h twice to 3f0h
1050 * 1 1 write 87h twice to 3f0h
1051 * 0 0 write 88h to 250h
1052 */
1053 if ((hefere | hefras) == w83877f_hefs[i])
1054 goto found;
1055 }
1056
1057 return (-1); /* failed */
1058
1059 found:
1060 /* check base port address - read from CR23 */
1061 outb(efir, 0x23);
1062 if (ppc->ppc_base != inb(efdr) * 4) /* 4 bytes boundaries */
1063 return (-1);
1064
1065 /* read CHIP ID from CR9/bits0-3 */
1066 outb(efir, 0x9);
1067
1068 switch (inb(efdr) & WINB_CHIPID) {
1069 case WINB_W83877F_ID:
1070 ppc->ppc_model = WINB_W83877F;
1071 break;
1072
1073 case WINB_W83877AF_ID:
1074 ppc->ppc_model = WINB_W83877AF;
1075 break;
1076
1077 default:
1078 ppc->ppc_model = WINB_UNKNOWN;
1079 }
1080
1081 if (bootverbose) {
1082 /* dump of registers */
1083 kprintf("ppc%d: 0x%x - ", ppc->ppc_unit, w83877f_keys[i]);
1084 for (i = 0; i <= 0xd; i ++) {
1085 outb(efir, i);
1086 kprintf("0x%x ", inb(efdr));
1087 }
1088 for (i = 0x10; i <= 0x17; i ++) {
1089 outb(efir, i);
1090 kprintf("0x%x ", inb(efdr));
1091 }
1092 outb(efir, 0x1e);
1093 kprintf("0x%x ", inb(efdr));
1094 for (i = 0x20; i <= 0x29; i ++) {
1095 outb(efir, i);
1096 kprintf("0x%x ", inb(efdr));
1097 }
1098 kprintf("\n");
1099 kprintf("ppc%d:", ppc->ppc_unit);
1100 }
1101
1102 ppc->ppc_type = PPC_TYPE_GENERIC;
1103
1104 if (!chipset_mode) {
1105 /* autodetect mode */
1106
1107 /* select CR0 */
1108 outb(efir, 0x0);
1109 r = inb(efdr) & (WINB_PRTMODS0 | WINB_PRTMODS1);
1110
1111 /* select CR9 */
1112 outb(efir, 0x9);
1113 r |= (inb(efdr) & WINB_PRTMODS2);
1114
1115 switch (r) {
1116 case WINB_W83757:
1117 if (bootverbose)
1118 kprintf("ppc%d: W83757 compatible mode\n",
1119 ppc->ppc_unit);
1120 return (-1); /* generic or SMC-like */
1121
1122 case WINB_EXTFDC:
1123 case WINB_EXTADP:
1124 case WINB_EXT2FDD:
1125 case WINB_JOYSTICK:
1126 if (bootverbose)
1127 kprintf(" not in parallel port mode\n");
1128 return (-1);
1129
1130 case (WINB_PARALLEL | WINB_EPP_SPP):
1131 ppc->ppc_avm |= PPB_EPP | PPB_SPP;
1132 if (bootverbose)
1133 kprintf(" EPP SPP");
1134 break;
1135
1136 case (WINB_PARALLEL | WINB_ECP):
1137 ppc->ppc_avm |= PPB_ECP | PPB_SPP;
1138 if (bootverbose)
1139 kprintf(" ECP SPP");
1140 break;
1141
1142 case (WINB_PARALLEL | WINB_ECP_EPP):
1143 ppc->ppc_avm |= PPB_ECP | PPB_EPP | PPB_SPP;
1144 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1145
1146 if (bootverbose)
1147 kprintf(" ECP+EPP SPP");
1148 break;
1149 default:
1150 kprintf("%s: unknown case (0x%x)!\n", __func__, r);
1151 }
1152
1153 } else {
1154 /* mode forced */
1155
1156 /* select CR9 and set PRTMODS2 bit */
1157 outb(efir, 0x9);
1158 outb(efdr, inb(efdr) & ~WINB_PRTMODS2);
1159
1160 /* select CR0 and reset PRTMODSx bits */
1161 outb(efir, 0x0);
1162 outb(efdr, inb(efdr) & ~(WINB_PRTMODS0 | WINB_PRTMODS1));
1163
1164 if (chipset_mode & PPB_ECP) {
1165 if (chipset_mode & PPB_EPP) {
1166 outb(efdr, inb(efdr) | WINB_ECP_EPP);
1167 if (bootverbose)
1168 kprintf(" ECP+EPP");
1169
1170 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1171
1172 } else {
1173 outb(efdr, inb(efdr) | WINB_ECP);
1174 if (bootverbose)
1175 kprintf(" ECP");
1176 }
1177 } else {
1178 /* select EPP_SPP otherwise */
1179 outb(efdr, inb(efdr) | WINB_EPP_SPP);
1180 if (bootverbose)
1181 kprintf(" EPP SPP");
1182 }
1183 ppc->ppc_avm = chipset_mode;
1184 }
1185
1186 if (bootverbose)
1187 kprintf("\n");
1188
1189 /* exit configuration mode */
1190 outb(efer, 0xaa);
1191
1192 switch (ppc->ppc_type) {
1193 case PPC_TYPE_SMCLIKE:
1194 ppc_smclike_setmode(ppc, chipset_mode);
1195 break;
1196 default:
1197 ppc_generic_setmode(ppc, chipset_mode);
1198 break;
1199 }
1200
1201 return (chipset_mode);
1202 }
1203 #endif
1204
1205 /*
1206 * ppc_generic_detect
1207 */
1208 static int
1209 ppc_generic_detect(struct ppc_data *ppc, int chipset_mode)
1210 {
1211 /* default to generic */
1212 ppc->ppc_type = PPC_TYPE_GENERIC;
1213
1214 if (bootverbose)
1215 kprintf("ppc%d:", ppc->ppc_unit);
1216
1217 /* first, check for ECP */
1218 w_ecr(ppc, PPC_ECR_PS2);
1219 if ((r_ecr(ppc) & 0xe0) == PPC_ECR_PS2) {
1220 ppc->ppc_dtm |= PPB_ECP | PPB_SPP;
1221 if (bootverbose)
1222 kprintf(" ECP SPP");
1223
1224 /* search for SMC style ECP+EPP mode */
1225 w_ecr(ppc, PPC_ECR_EPP);
1226 }
1227
1228 /* try to reset EPP timeout bit */
1229 if (ppc_check_epp_timeout(ppc)) {
1230 ppc->ppc_dtm |= PPB_EPP;
1231
1232 if (ppc->ppc_dtm & PPB_ECP) {
1233 /* SMC like chipset found */
1234 ppc->ppc_model = SMC_LIKE;
1235 ppc->ppc_type = PPC_TYPE_SMCLIKE;
1236
1237 if (bootverbose)
1238 kprintf(" ECP+EPP");
1239 } else {
1240 if (bootverbose)
1241 kprintf(" EPP");
1242 }
1243 } else {
1244 /* restore to standard mode */
1245 w_ecr(ppc, PPC_ECR_STD);
1246 }
1247
1248 /* XXX try to detect NIBBLE and PS2 modes */
1249 ppc->ppc_dtm |= PPB_NIBBLE;
1250
1251 if (bootverbose)
1252 kprintf(" SPP");
1253
1254 if (chipset_mode)
1255 ppc->ppc_avm = chipset_mode;
1256 else
1257 ppc->ppc_avm = ppc->ppc_dtm;
1258
1259 if (bootverbose)
1260 kprintf("\n");
1261
1262 switch (ppc->ppc_type) {
1263 case PPC_TYPE_SMCLIKE:
1264 ppc_smclike_setmode(ppc, chipset_mode);
1265 break;
1266 default:
1267 ppc_generic_setmode(ppc, chipset_mode);
1268 break;
1269 }
1270
1271 return (chipset_mode);
1272 }
1273
1274 /*
1275 * ppc_detect()
1276 *
1277 * mode is the mode suggested at boot
1278 */
1279 static int
1280 ppc_detect(struct ppc_data *ppc, int chipset_mode)
1281 {
1282 #ifdef PPC_PROBE_CHIPSET
1283 int i, mode;
1284
1285 /* list of supported chipsets */
1286 int (*chipset_detect[])(struct ppc_data *, int) = {
1287 ppc_pc873xx_detect,
1288 ppc_smc37c66xgt_detect,
1289 ppc_w83877f_detect,
1290 ppc_smc37c935_detect,
1291 ppc_generic_detect,
1292 NULL
1293 };
1294 #endif
1295
1296 /* if can't find the port and mode not forced return error */
1297 if (!ppc_detect_port(ppc) && chipset_mode == 0)
1298 return (EIO); /* failed, port not present */
1299
1300 /* assume centronics compatible mode is supported */
1301 ppc->ppc_avm = PPB_COMPATIBLE;
1302
1303 #ifdef PPC_PROBE_CHIPSET
1304 /* we have to differenciate available chipset modes,
1305 * chipset running modes and IEEE-1284 operating modes
1306 *
1307 * after detection, the port must support running in compatible mode
1308 */
1309 if (ppc->ppc_flags & 0x40) {
1310 if (bootverbose)
1311 kprintf("ppc: chipset forced to generic\n");
1312 #endif
1313
1314 ppc->ppc_mode = ppc_generic_detect(ppc, chipset_mode);
1315
1316 #ifdef PPC_PROBE_CHIPSET
1317 } else {
1318 for (i=0; chipset_detect[i] != NULL; i++) {
1319 if ((mode = chipset_detect[i](ppc, chipset_mode)) != -1) {
1320 ppc->ppc_mode = mode;
1321 break;
1322 }
1323 }
1324 }
1325 #endif
1326
1327 /* configure/detect ECP FIFO */
1328 if ((ppc->ppc_avm & PPB_ECP) && !(ppc->ppc_flags & 0x80))
1329 ppc_detect_fifo(ppc);
1330
1331 return (0);
1332 }
1333
1334 /*
1335 * ppc_exec_microseq()
1336 *
1337 * Execute a microsequence.
1338 * Microsequence mechanism is supposed to handle fast I/O operations.
1339 */
1340 static int
1341 ppc_exec_microseq(device_t dev, struct ppb_microseq **p_msq)
1342 {
1343 struct ppc_data *ppc = DEVTOSOFTC(dev);
1344 struct ppb_microseq *mi;
1345 char cc, *p;
1346 int i, iter, len;
1347 int error;
1348
1349 int reg;
1350 char mask;
1351 int accum = 0;
1352 char *ptr = 0;
1353
1354 struct ppb_microseq *stack = 0;
1355
1356 /* microsequence registers are equivalent to PC-like port registers */
1357
1358 #define r_reg(register,ppc) (bus_space_read_1((ppc)->bst, (ppc)->bsh, register))
1359 #define w_reg(register, ppc, byte) (bus_space_write_1((ppc)->bst, (ppc)->bsh, register, byte))
1360
1361 #define INCR_PC (mi ++) /* increment program counter */
1362
1363 mi = *p_msq;
1364 for (;;) {
1365 switch (mi->opcode) {
1366 case MS_OP_RSET:
1367 cc = r_reg(mi->arg[0].i, ppc);
1368 cc &= (char)mi->arg[2].i; /* clear mask */
1369 cc |= (char)mi->arg[1].i; /* assert mask */
1370 w_reg(mi->arg[0].i, ppc, cc);
1371 INCR_PC;
1372 break;
1373
1374 case MS_OP_RASSERT_P:
1375 reg = mi->arg[1].i;
1376 ptr = ppc->ppc_ptr;
1377
1378 if ((len = mi->arg[0].i) == MS_ACCUM) {
1379 accum = ppc->ppc_accum;
1380 for (; accum; accum--)
1381 w_reg(reg, ppc, *ptr++);
1382 ppc->ppc_accum = accum;
1383 } else
1384 for (i=0; i<len; i++)
1385 w_reg(reg, ppc, *ptr++);
1386 ppc->ppc_ptr = ptr;
1387
1388 INCR_PC;
1389 break;
1390
1391 case MS_OP_RFETCH_P:
1392 reg = mi->arg[1].i;
1393 mask = (char)mi->arg[2].i;
1394 ptr = ppc->ppc_ptr;
1395
1396 if ((len = mi->arg[0].i) == MS_ACCUM) {
1397 accum = ppc->ppc_accum;
1398 for (; accum; accum--)
1399 *ptr++ = r_reg(reg, ppc) & mask;
1400 ppc->ppc_accum = accum;
1401 } else
1402 for (i=0; i<len; i++)
1403 *ptr++ = r_reg(reg, ppc) & mask;
1404 ppc->ppc_ptr = ptr;
1405
1406 INCR_PC;
1407 break;
1408
1409 case MS_OP_RFETCH:
1410 *((char *) mi->arg[2].p) = r_reg(mi->arg[0].i, ppc) &
1411 (char)mi->arg[1].i;
1412 INCR_PC;
1413 break;
1414
1415 case MS_OP_RASSERT:
1416 case MS_OP_DELAY:
1417
1418 /* let's suppose the next instr. is the same */
1419 prefetch:
1420 for (;mi->opcode == MS_OP_RASSERT; INCR_PC)
1421 w_reg(mi->arg[0].i, ppc, (char)mi->arg[1].i);
1422
1423 if (mi->opcode == MS_OP_DELAY) {
1424 DELAY(mi->arg[0].i);
1425 INCR_PC;
1426 goto prefetch;
1427 }
1428 break;
1429
1430 case MS_OP_ADELAY:
1431 if (mi->arg[0].i)
1432 tsleep(NULL, 0, "ppbdelay",
1433 mi->arg[0].i * (hz/1000));
1434 INCR_PC;
1435 break;
1436
1437 case MS_OP_TRIG:
1438 reg = mi->arg[0].i;
1439 iter = mi->arg[1].i;
1440 p = (char *)mi->arg[2].p;
1441
1442 /* XXX delay limited to 255 us */
1443 for (i=0; i<iter; i++) {
1444 w_reg(reg, ppc, *p++);
1445 DELAY((unsigned char)*p++);
1446 }
1447 INCR_PC;
1448 break;
1449
1450 case MS_OP_SET:
1451 ppc->ppc_accum = mi->arg[0].i;
1452 INCR_PC;
1453 break;
1454
1455 case MS_OP_DBRA:
1456 if (--ppc->ppc_accum > 0)
1457 mi += mi->arg[0].i;
1458 INCR_PC;
1459 break;
1460
1461 case MS_OP_BRSET:
1462 cc = r_str(ppc);
1463 if ((cc & (char)mi->arg[0].i) == (char)mi->arg[0].i)
1464 mi += mi->arg[1].i;
1465 INCR_PC;
1466 break;
1467
1468 case MS_OP_BRCLEAR:
1469 cc = r_str(ppc);
1470 if ((cc & (char)mi->arg[0].i) == 0)
1471 mi += mi->arg[1].i;
1472 INCR_PC;
1473 break;
1474
1475 case MS_OP_BRSTAT:
1476 cc = r_str(ppc);
1477 if ((cc & ((char)mi->arg[0].i | (char)mi->arg[1].i)) ==
1478 (char)mi->arg[0].i)
1479 mi += mi->arg[2].i;
1480 INCR_PC;
1481 break;
1482
1483 case MS_OP_C_CALL:
1484 /*
1485 * If the C call returns !0 then end the microseq.
1486 * The current state of ptr is passed to the C function
1487 */
1488 if ((error = mi->arg[0].f(mi->arg[1].p, ppc->ppc_ptr)))
1489 return (error);
1490
1491 INCR_PC;
1492 break;
1493
1494 case MS_OP_PTR:
1495 ppc->ppc_ptr = (char *)mi->arg[0].p;
1496 INCR_PC;
1497 break;
1498
1499 case MS_OP_CALL:
1500 if (stack)
1501 panic("%s: too much calls", __func__);
1502
1503 if (mi->arg[0].p) {
1504 /* store the state of the actual
1505 * microsequence
1506 */
1507 stack = mi;
1508
1509 /* jump to the new microsequence */
1510 mi = (struct ppb_microseq *)mi->arg[0].p;
1511 } else
1512 INCR_PC;
1513
1514 break;
1515
1516 case MS_OP_SUBRET:
1517 /* retrieve microseq and pc state before the call */
1518 mi = stack;
1519
1520 /* reset the stack */
1521 stack = 0;
1522
1523 /* XXX return code */
1524
1525 INCR_PC;
1526 break;
1527
1528 case MS_OP_PUT:
1529 case MS_OP_GET:
1530 case MS_OP_RET:
1531 /* can't return to ppb level during the execution
1532 * of a submicrosequence */
1533 if (stack)
1534 panic("%s: can't return to ppb level",
1535 __func__);
1536
1537 /* update pc for ppb level of execution */
1538 *p_msq = mi;
1539
1540 /* return to ppb level of execution */
1541 return (0);
1542
1543 default:
1544 panic("%s: unknown microsequence opcode 0x%x",
1545 __func__, mi->opcode);
1546 }
1547 }
1548
1549 /* unreached */
1550 }
1551
1552 static void
1553 ppcintr(void *arg)
1554 {
1555 device_t dev = (device_t)arg;
1556 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(dev);
1557 u_char ctr, ecr, str;
1558
1559 str = r_str(ppc);
1560 ctr = r_ctr(ppc);
1561 ecr = r_ecr(ppc);
1562
1563 #if PPC_DEBUG > 1
1564 kprintf("![%x/%x/%x]", ctr, ecr, str);
1565 #endif
1566
1567 /* don't use ecp mode with IRQENABLE set */
1568 if (ctr & IRQENABLE) {
1569 return;
1570 }
1571
1572 /* interrupts are generated by nFault signal
1573 * only in ECP mode */
1574 if ((str & nFAULT) && (ppc->ppc_mode & PPB_ECP)) {
1575 /* check if ppc driver has programmed the
1576 * nFault interrupt */
1577 if (ppc->ppc_irqstat & PPC_IRQ_nFAULT) {
1578
1579 w_ecr(ppc, ecr | PPC_nFAULT_INTR);
1580 ppc->ppc_irqstat &= ~PPC_IRQ_nFAULT;
1581 } else {
1582 /* shall be handled by underlying layers XXX */
1583 return;
1584 }
1585 }
1586
1587 if (ppc->ppc_irqstat & PPC_IRQ_DMA) {
1588 /* disable interrupts (should be done by hardware though) */
1589 w_ecr(ppc, ecr | PPC_SERVICE_INTR);
1590 ppc->ppc_irqstat &= ~PPC_IRQ_DMA;
1591 ecr = r_ecr(ppc);
1592
1593 /* check if DMA completed */
1594 if ((ppc->ppc_avm & PPB_ECP) && (ecr & PPC_ENABLE_DMA)) {
1595 #ifdef PPC_DEBUG
1596 kprintf("a");
1597 #endif
1598 /* stop DMA */
1599 w_ecr(ppc, ecr & ~PPC_ENABLE_DMA);
1600 ecr = r_ecr(ppc);
1601
1602 if (ppc->ppc_dmastat == PPC_DMA_STARTED) {
1603 #ifdef PPC_DEBUG
1604 kprintf("d");
1605 #endif
1606 isa_dmadone(
1607 ppc->ppc_dmaflags,
1608 ppc->ppc_dmaddr,
1609 ppc->ppc_dmacnt,
1610 ppc->ppc_dmachan);
1611
1612 ppc->ppc_dmastat = PPC_DMA_COMPLETE;
1613
1614 /* wakeup the waiting process */
1615 wakeup((caddr_t)ppc);
1616 }
1617 }
1618 } else if (ppc->ppc_irqstat & PPC_IRQ_FIFO) {
1619
1620 /* classic interrupt I/O */
1621 ppc->ppc_irqstat &= ~PPC_IRQ_FIFO;
1622 }
1623
1624 return;
1625 }
1626
1627 static int
1628 ppc_read(device_t dev, char *buf, int len, int mode)
1629 {
1630 return (EINVAL);
1631 }
1632
1633 /*
1634 * Call this function if you want to send data in any advanced mode
1635 * of your parallel port: FIFO, DMA
1636 *
1637 * If what you want is not possible (no ECP, no DMA...),
1638 * EINVAL is returned
1639 */
1640 static int
1641 ppc_write(device_t dev, char *buf, int len, int how)
1642 {
1643 struct ppc_data *ppc = DEVTOSOFTC(dev);
1644 char ecr, ecr_sav, ctr, ctr_sav;
1645 int error = 0;
1646 int spin;
1647
1648 #ifdef PPC_DEBUG
1649 kprintf("w");
1650 #endif
1651
1652 ecr_sav = r_ecr(ppc);
1653 ctr_sav = r_ctr(ppc);
1654
1655 /*
1656 * Send buffer with DMA, FIFO and interrupts
1657 */
1658 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_registered)) {
1659
1660 if (ppc->ppc_dmachan > 0) {
1661
1662 /* byte mode, no intr, no DMA, dir=0, flush fifo
1663 */
1664 ecr = PPC_ECR_STD | PPC_DISABLE_INTR;
1665 w_ecr(ppc, ecr);
1666
1667 /* disable nAck interrupts */
1668 ctr = r_ctr(ppc);
1669 ctr &= ~IRQENABLE;
1670 w_ctr(ppc, ctr);
1671
1672 ppc->ppc_dmaflags = ISADMA_WRITE;
1673 ppc->ppc_dmaddr = (caddr_t)buf;
1674 ppc->ppc_dmacnt = (u_int)len;
1675
1676 switch (ppc->ppc_mode) {
1677 case PPB_COMPATIBLE:
1678 /* compatible mode with FIFO, no intr, DMA, dir=0 */
1679 ecr = PPC_ECR_FIFO | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1680 break;
1681 case PPB_ECP:
1682 ecr = PPC_ECR_ECP | PPC_DISABLE_INTR | PPC_ENABLE_DMA;
1683 break;
1684 default:
1685 error = EINVAL;
1686 goto error;
1687 }
1688
1689 w_ecr(ppc, ecr);
1690 ecr = r_ecr(ppc);
1691
1692 /* enter splhigh() not to be preempted
1693 * by the dma interrupt, we may miss
1694 * the wakeup otherwise
1695 */
1696 crit_enter();
1697
1698 ppc->ppc_dmastat = PPC_DMA_INIT;
1699
1700 /* enable interrupts */
1701 ecr &= ~PPC_SERVICE_INTR;
1702 ppc->ppc_irqstat = PPC_IRQ_DMA;
1703 w_ecr(ppc, ecr);
1704
1705 isa_dmastart(
1706 ppc->ppc_dmaflags,
1707 ppc->ppc_dmaddr,
1708 ppc->ppc_dmacnt,
1709 ppc->ppc_dmachan);
1710 #ifdef PPC_DEBUG
1711 kprintf("s%d", ppc->ppc_dmacnt);
1712 #endif
1713 ppc->ppc_dmastat = PPC_DMA_STARTED;
1714
1715 /* Wait for the DMA completed interrupt. We hope we won't
1716 * miss it, otherwise a signal will be necessary to unlock the
1717 * process.
1718 */
1719 do {
1720 /* release CPU */
1721 error = tsleep((caddr_t)ppc, PCATCH, "ppcdma", 0);
1722
1723 } while (error == EWOULDBLOCK);
1724
1725 crit_exit();
1726
1727 if (error) {
1728 #ifdef PPC_DEBUG
1729 kprintf("i");
1730 #endif
1731 /* stop DMA */
1732 isa_dmadone(
1733 ppc->ppc_dmaflags,
1734 ppc->ppc_dmaddr, ppc->ppc_dmacnt,
1735 ppc->ppc_dmachan);
1736
1737 /* no dma, no interrupt, flush the fifo */
1738 w_ecr(ppc, PPC_ECR_RESET);
1739
1740 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1741 goto error;
1742 }
1743
1744 /* wait for an empty fifo */
1745 while (!(r_ecr(ppc) & PPC_FIFO_EMPTY)) {
1746
1747 for (spin=100; spin; spin--)
1748 if (r_ecr(ppc) & PPC_FIFO_EMPTY)
1749 goto fifo_empty;
1750 #ifdef PPC_DEBUG
1751 kprintf("Z");
1752 #endif
1753 error = tsleep((caddr_t)ppc, PCATCH, "ppcfifo", hz/100);
1754 if (error != EWOULDBLOCK) {
1755 #ifdef PPC_DEBUG
1756 kprintf("I");
1757 #endif
1758 /* no dma, no interrupt, flush the fifo */
1759 w_ecr(ppc, PPC_ECR_RESET);
1760
1761 ppc->ppc_dmastat = PPC_DMA_INTERRUPTED;
1762 error = EINTR;
1763 goto error;
1764 }
1765 }
1766
1767 fifo_empty:
1768 /* no dma, no interrupt, flush the fifo */
1769 w_ecr(ppc, PPC_ECR_RESET);
1770
1771 } else
1772 error = EINVAL; /* XXX we should FIFO and
1773 * interrupts */
1774 } else
1775 error = EINVAL;
1776
1777 error:
1778
1779 /* PDRQ must be kept unasserted until nPDACK is
1780 * deasserted for a minimum of 350ns (SMC datasheet)
1781 *
1782 * Consequence may be a FIFO that never empty
1783 */
1784 DELAY(1);
1785
1786 w_ecr(ppc, ecr_sav);
1787 w_ctr(ppc, ctr_sav);
1788
1789 return (error);
1790 }
1791
1792 static void
1793 ppc_reset_epp(device_t dev)
1794 {
1795 struct ppc_data *ppc = DEVTOSOFTC(dev);
1796
1797 ppc_reset_epp_timeout(ppc);
1798
1799 return;
1800 }
1801
1802 static int
1803 ppc_setmode(device_t dev, int mode)
1804 {
1805 struct ppc_data *ppc = DEVTOSOFTC(dev);
1806
1807 switch (ppc->ppc_type) {
1808 case PPC_TYPE_SMCLIKE:
1809 return (ppc_smclike_setmode(ppc, mode));
1810 break;
1811
1812 case PPC_TYPE_GENERIC:
1813 default:
1814 return (ppc_generic_setmode(ppc, mode));
1815 break;
1816 }
1817
1818 /* not reached */
1819 return (ENXIO);
1820 }
1821
1822 static struct isa_pnp_id lpc_ids[] = {
1823 { 0x0004d041, "Standard parallel printer port" }, /* PNP0400 */
1824 { 0x0104d041, "ECP parallel printer port" }, /* PNP0401 */
1825 { 0 }
1826 };
1827
1828 static int
1829 ppc_probe(device_t dev)
1830 {
1831 #ifdef __i386__
1832 static short next_bios_ppc = 0;
1833 #endif
1834 struct ppc_data *ppc;
1835 device_t parent;
1836 int error;
1837 u_long port;
1838
1839 parent = device_get_parent(dev);
1840
1841 error = ISA_PNP_PROBE(parent, dev, lpc_ids);
1842 if (error == ENXIO)
1843 return (ENXIO);
1844 else if (error != 0) /* XXX shall be set after detection */
1845 device_set_desc(dev, "Parallel port");
1846
1847 /*
1848 * Allocate the ppc_data structure.
1849 */
1850 ppc = DEVTOSOFTC(dev);
1851 bzero(ppc, sizeof(struct ppc_data));
1852
1853 ppc->rid_irq = ppc->rid_drq = ppc->rid_ioport = 0;
1854 ppc->res_irq = ppc->res_drq = ppc->res_ioport = 0;
1855
1856 /* retrieve ISA parameters */
1857 error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, NULL);
1858
1859 #ifdef __i386__
1860 /*
1861 * If port not specified, use bios list.
1862 */
1863 if (error) {
1864 if((next_bios_ppc < BIOS_MAX_PPC) &&
1865 (*(BIOS_PORTS+next_bios_ppc) != 0) ) {
1866 port = *(BIOS_PORTS+next_bios_ppc++);
1867 if (bootverbose)
1868 device_printf(dev, "parallel port found at 0x%x\n",
1869 (int) port);
1870 } else {
1871 device_printf(dev, "parallel port not found.\n");
1872 return ENXIO;
1873 }
1874 bus_set_resource(dev, SYS_RES_IOPORT, 0, port,
1875 IO_LPTSIZE_EXTENDED);
1876 }
1877 #endif
1878
1879 /* IO port is mandatory */
1880
1881 /* Try "extended" IO port range...*/
1882 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1883 &ppc->rid_ioport, 0, ~0,
1884 IO_LPTSIZE_EXTENDED, RF_ACTIVE);
1885
1886 if (ppc->res_ioport != 0) {
1887 if (bootverbose)
1888 device_printf(dev, "using extended I/O port range\n");
1889 } else {
1890 /* Failed? If so, then try the "normal" IO port range... */
1891 ppc->res_ioport = bus_alloc_resource(dev, SYS_RES_IOPORT,
1892 &ppc->rid_ioport, 0, ~0,
1893 IO_LPTSIZE_NORMAL,
1894 RF_ACTIVE);
1895 if (ppc->res_ioport != 0) {
1896 if (bootverbose)
1897 device_printf(dev, "using normal I/O port range\n");
1898 } else {
1899 device_printf(dev, "cannot reserve I/O port range\n");
1900 goto error;
1901 }
1902 }
1903
1904 ppc->ppc_base = rman_get_start(ppc->res_ioport);
1905
1906 ppc->bsh = rman_get_bushandle(ppc->res_ioport);
1907 ppc->bst = rman_get_bustag(ppc->res_ioport);
1908
1909 ppc->ppc_flags = device_get_flags(dev);
1910
1911 if (!(ppc->ppc_flags & 0x20)) {
1912 ppc->res_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &ppc->rid_irq,
1913 0ul, ~0ul, 1, RF_SHAREABLE);
1914 ppc->res_drq = bus_alloc_resource(dev, SYS_RES_DRQ, &ppc->rid_drq,
1915 0ul, ~0ul, 1, RF_ACTIVE);
1916 }
1917
1918 if (ppc->res_irq)
1919 ppc->ppc_irq = rman_get_start(ppc->res_irq);
1920 if (ppc->res_drq)
1921 ppc->ppc_dmachan = rman_get_start(ppc->res_drq);
1922
1923 ppc->ppc_unit = device_get_unit(dev);
1924 ppc->ppc_model = GENERIC;
1925
1926 ppc->ppc_mode = PPB_COMPATIBLE;
1927 ppc->ppc_epp = (ppc->ppc_flags & 0x10) >> 4;
1928
1929 ppc->ppc_type = PPC_TYPE_GENERIC;
1930
1931 /*
1932 * Try to detect the chipset and its mode.
1933 */
1934 if (ppc_detect(ppc, ppc->ppc_flags & 0xf))
1935 goto error;
1936
1937 return (0);
1938
1939 error:
1940 if (ppc->res_irq != 0) {
1941 bus_release_resource(dev, SYS_RES_IRQ, ppc->rid_irq,
1942 ppc->res_irq);
1943 }
1944 if (ppc->res_ioport != 0) {
1945 bus_deactivate_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1946 ppc->res_ioport);
1947 bus_release_resource(dev, SYS_RES_IOPORT, ppc->rid_ioport,
1948 ppc->res_ioport);
1949 }
1950 if (ppc->res_drq != 0) {
1951 bus_deactivate_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1952 ppc->res_drq);
1953 bus_release_resource(dev, SYS_RES_DRQ, ppc->rid_drq,
1954 ppc->res_drq);
1955 }
1956 return (ENXIO);
1957 }
1958
1959 static int
1960 ppc_attach(device_t dev)
1961 {
1962 struct ppc_data *ppc = DEVTOSOFTC(dev);
1963
1964 device_t ppbus;
1965 device_t parent = device_get_parent(dev);
1966
1967 device_printf(dev, "%s chipset (%s) in %s mode%s\n",
1968 ppc_models[ppc->ppc_model], ppc_avms[ppc->ppc_avm],
1969 ppc_modes[ppc->ppc_mode], (PPB_IS_EPP(ppc->ppc_mode)) ?
1970 ppc_epp_protocol[ppc->ppc_epp] : "");
1971
1972 if (ppc->ppc_fifo)
1973 device_printf(dev, "FIFO with %d/%d/%d bytes threshold\n",
1974 ppc->ppc_fifo, ppc->ppc_wthr, ppc->ppc_rthr);
1975
1976 if ((ppc->ppc_avm & PPB_ECP) && (ppc->ppc_dmachan > 0)) {
1977 /* acquire the DMA channel forever */ /* XXX */
1978 isa_dma_acquire(ppc->ppc_dmachan);
1979 isa_dmainit(ppc->ppc_dmachan, 1024); /* nlpt.BUFSIZE */
1980 }
1981
1982 /* add ppbus as a child of this isa to parallel bridge */
1983 ppbus = device_add_child(dev, "ppbus", -1);
1984
1985 /*
1986 * Probe the ppbus and attach devices found.
1987 */
1988 device_probe_and_attach(ppbus);
1989
1990 /* register the ppc interrupt handler as default */
1991 if (ppc->res_irq) {
1992 /* default to the tty mask for registration */ /* XXX */
1993 if (BUS_SETUP_INTR(parent, dev, ppc->res_irq, 0,
1994 ppcintr, dev,
1995 &ppc->intr_cookie, NULL) == 0) {
1996 /* remember the ppcintr is registered */
1997 ppc->ppc_registered = 1;
1998 }
1999 }
2000
2001 return (0);
2002 }
2003
2004 static u_char
2005 ppc_io(device_t ppcdev, int iop, u_char *addr, int cnt, u_char byte)
2006 {
2007 struct ppc_data *ppc = DEVTOSOFTC(ppcdev);
2008 switch (iop) {
2009 case PPB_OUTSB_EPP:
2010 bus_space_write_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2011 break;
2012 case PPB_OUTSW_EPP:
2013 bus_space_write_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2014 break;
2015 case PPB_OUTSL_EPP:
2016 bus_space_write_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2017 break;
2018 case PPB_INSB_EPP:
2019 bus_space_read_multi_1(ppc->bst, ppc->bsh, PPC_EPP_DATA, addr, cnt);
2020 break;
2021 case PPB_INSW_EPP:
2022 bus_space_read_multi_2(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int16_t *)addr, cnt);
2023 break;
2024 case PPB_INSL_EPP:
2025 bus_space_read_multi_4(ppc->bst, ppc->bsh, PPC_EPP_DATA, (u_int32_t *)addr, cnt);
2026 break;
2027 case PPB_RDTR:
2028 return (r_dtr(ppc));
2029 break;
2030 case PPB_RSTR:
2031 return (r_str(ppc));
2032 break;
2033 case PPB_RCTR:
2034 return (r_ctr(ppc));
2035 break;
2036 case PPB_REPP_A:
2037 return (r_epp_A(ppc));
2038 break;
2039 case PPB_REPP_D:
2040 return (r_epp_D(ppc));
2041 break;
2042 case PPB_RECR:
2043 return (r_ecr(ppc));
2044 break;
2045 case PPB_RFIFO:
2046 return (r_fifo(ppc));
2047 break;
2048 case PPB_WDTR:
2049 w_dtr(ppc, byte);
2050 break;
2051 case PPB_WSTR:
2052 w_str(ppc, byte);
2053 break;
2054 case PPB_WCTR:
2055 w_ctr(ppc, byte);
2056 break;
2057 case PPB_WEPP_A:
2058 w_epp_A(ppc, byte);
2059 break;
2060 case PPB_WEPP_D:
2061 w_epp_D(ppc, byte);
2062 break;
2063 case PPB_WECR:
2064 w_ecr(ppc, byte);
2065 break;
2066 case PPB_WFIFO:
2067 w_fifo(ppc, byte);
2068 break;
2069 default:
2070 panic("%s: unknown I/O operation", __func__);
2071 break;
2072 }
2073
2074 return (0); /* not significative */
2075 }
2076
2077 static int
2078 ppc_read_ivar(device_t bus, device_t dev, int index, uintptr_t *val)
2079 {
2080 struct ppc_data *ppc = (struct ppc_data *)device_get_softc(bus);
2081
2082 switch (index) {
2083 case PPC_IVAR_EPP_PROTO:
2084 *val = (u_long)ppc->ppc_epp;
2085 break;
2086 case PPC_IVAR_IRQ:
2087 *val = (u_long)ppc->ppc_irq;
2088 break;
2089 default:
2090 return (ENOENT);
2091 }
2092
2093 return (0);
2094 }
2095
2096 /*
2097 * Resource is useless here since ppbus devices' interrupt handlers are
2098 * multiplexed to the same resource initially allocated by ppc
2099 */
2100 static int
2101 ppc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
2102 void (*ihand)(void *), void *arg,
2103 void **cookiep, lwkt_serialize_t serializer)
2104 {
2105 int error;
2106 struct ppc_data *ppc = DEVTOSOFTC(bus);
2107
2108 if (ppc->ppc_registered) {
2109 /* XXX refuse registration if DMA is in progress */
2110
2111 /* first, unregister the default interrupt handler */
2112 if ((error = BUS_TEARDOWN_INTR(device_get_parent(bus),
2113 bus, ppc->res_irq, ppc->intr_cookie)))
2114 return (error);
2115
2116 /* bus_deactivate_resource(bus, SYS_RES_IRQ, ppc->rid_irq, */
2117 /* ppc->res_irq); */
2118
2119 /* DMA/FIFO operation won't be possible anymore */
2120 ppc->ppc_registered = 0;
2121 }
2122
2123 /* pass registration to the upper layer, ignore the incoming resource */
2124 return (BUS_SETUP_INTR(device_get_parent(bus), child,
2125 r, flags, ihand, arg, cookiep, serializer));
2126 }
2127
2128 /*
2129 * When no underlying device has a registered interrupt, register the ppc
2130 * layer one
2131 */
2132 static int
2133 ppc_teardown_intr(device_t bus, device_t child, struct resource *r, void *ih)
2134 {
2135 int error;
2136 struct ppc_data *ppc = DEVTOSOFTC(bus);
2137 device_t parent = device_get_parent(bus);
2138
2139 /* pass unregistration to the upper layer */
2140 if ((error = BUS_TEARDOWN_INTR(parent, child, r, ih)))
2141 return (error);
2142
2143 /* default to the tty mask for registration */ /* XXX */
2144 if (ppc->ppc_irq &&
2145 !(error = BUS_SETUP_INTR(parent, bus, ppc->res_irq,
2146 0, ppcintr, bus,
2147 &ppc->intr_cookie, NULL))
2148 ) {
2149 /* remember the ppcintr is registered */
2150 ppc->ppc_registered = 1;
2151 }
2152
2153 return (error);
2154 }
2155
2156 DRIVER_MODULE(ppc, isa, ppc_driver, ppc_devclass, 0, 0);
DragonFly vkernel multiprocessor port