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Revert rtw.c rev1.7, though it works well with my ral(4)/ath(4) based
[dragonfly/vkernel-mp.git] / sys / dev / netif / rtw / rtw.c
blobf591cb201fc714caa86fe33ad0f75be7a66a4a54
1 /*
2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $NetBSD: rtw.c,v 1.72 2006/03/28 00:48:10 dyoung Exp $
35 * $DragonFly: src/sys/dev/netif/rtw/rtw.c,v 1.8 2007/03/19 12:38:47 sephe Exp $
36 */
37
38 /*
39 * Copyright (c) 2004, 2005 David Young. All rights reserved.
40 *
41 * Programmed for NetBSD by David Young.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. The name of David Young may not be used to endorse or promote
52 * products derived from this software without specific prior
53 * written permission.
54 *
55 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
57 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
58 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
59 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
60 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
61 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
63 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
66 * OF SUCH DAMAGE.
67 */
68
69 /*
70 * Device driver for the Realtek RTL8180 802.11 MAC/BBP.
71 */
72
73 #include <sys/param.h>
74 #include <sys/bus.h>
75 #include <sys/endian.h>
76 #include <sys/kernel.h>
77 #include <sys/rman.h>
78 #include <sys/socket.h>
79 #include <sys/sockio.h>
80 #include <sys/serialize.h>
81 #include <sys/sysctl.h>
82
83 #include <net/if.h>
84 #include <net/if_arp.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/ifq_var.h>
88 #include <net/ethernet.h>
89 #include <net/bpf.h>
90
91 #include <netproto/802_11/ieee80211_var.h>
92 #include <netproto/802_11/ieee80211_radiotap.h>
93
94 #include "rtwbitop.h"
95 #include "rtwreg.h"
96 #include "rtwvar.h"
97 #include "rtwphyio.h"
98 #include "rtwphy.h"
99 #include "smc93cx6var.h"
100 #include "sa2400reg.h"
101
102 /* XXX */
103 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
104 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
105 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
106 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
107 #define IEEE80211_DUR_DS_SLOW_ACK 112
108 #define IEEE80211_DUR_DS_SLOW_CTS 112
109 #define IEEE80211_DUR_DS_SIFS 10
110
111 struct rtw_txsegs {
112 int nseg;
113 bus_dma_segment_t segs[RTW_MAXPKTSEGS];
114 };
115
116 devclass_t rtw_devclass;
117
118 static const struct ieee80211_rateset rtw_rates_11b = { 4, { 2, 4, 11, 22 } };
119
120 SYSCTL_NODE(_hw, OID_AUTO, rtw, CTLFLAG_RD, 0,
121 "Realtek RTL818x 802.11 controls");
122
123 /* [0, SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)] */
124 static int rtw_rfprog_fallback = 0;
125 SYSCTL_INT(_hw_rtw, OID_AUTO, rfprog_fallback, CTLFLAG_RW,
126 &rtw_rfprog_fallback, 0, "fallback RF programming method");
127
128 static int rtw_host_rfio = 0; /* 0/1 */
129 SYSCTL_INT(_hw_rtw, OID_AUTO, host_rfio, CTLFLAG_RW,
130 &rtw_host_rfio, 0, "enable host control of RF I/O");
131
132 #ifdef RTW_DEBUG
133 int rtw_debug = 0; /* [0, RTW_DEBUG_MAX] */
134 SYSCTL_INT(_hw_rtw, OID_AUTO, debug, CTLFLAG_RW, &rtw_debug, 0, "debug level");
135
136 static int rtw_rxbufs_limit = RTW_RXQLEN; /* [0, RTW_RXQLEN] */
137 SYSCTL_INT(_hw_rtw, OID_AUTO, rxbufs_limit, CTLFLAG_RW, &rtw_rxbufs_limit, 0,
138 "rx buffers limit");
139 #endif /* RTW_DEBUG */
140
141 #if 0
142 static int rtw_xmtr_restart = 0;
143 SYSCTL_INT(_hw_rtw, OID_AUTO, xmtr_restart, CTLFLAG_RW, &rtw_xmtr_restart, 0,
144 "gratuitously reset xmtr on rcvr error");
145
146 static int rtw_ring_reset = 0;
147 SYSCTL_INT(_hw_rtw, OID_AUTO, ring_reset, CTLFLAG_RW, &rtw_ring_reset, 0,
148 "reset ring pointers on rcvr error");
149 #endif
150
151 static int rtw_do_chip_reset = 0;
152 SYSCTL_INT(_hw_rtw, OID_AUTO, chip_reset, CTLFLAG_RW, &rtw_do_chip_reset, 0,
153 "gratuitously reset chip on rcvr error");
154
155 int rtw_dwelltime = 200; /* milliseconds */
156
157 /* XXX */
158 static struct ieee80211_cipher rtw_cipher_wep;
159
160 static void rtw_led_init(struct rtw_softc *);
161 static void rtw_led_newstate(struct rtw_softc *, enum ieee80211_state);
162 static void rtw_led_slowblink(void *);
163 static void rtw_led_fastblink(void *);
164 static void rtw_led_set(struct rtw_softc *);
165
166 static void rtw_init(void *);
167 static void rtw_start(struct ifnet *);
168 static int rtw_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
169 static void rtw_watchdog(struct ifnet *);
170 static void rtw_intr(void *);
171
172 static void rtw_intr_rx(struct rtw_softc *, uint16_t);
173 static void rtw_intr_tx(struct rtw_softc *, uint16_t);
174 static void rtw_intr_beacon(struct rtw_softc *, uint16_t);
175 static void rtw_intr_atim(struct rtw_softc *);
176 static void rtw_intr_ioerror(struct rtw_softc *, uint16_t);
177 static void rtw_intr_timeout(struct rtw_softc *);
178
179 static int rtw_dequeue(struct ifnet *, struct rtw_txsoft_blk **,
180 struct rtw_txdesc_blk **, struct mbuf **,
181 struct ieee80211_node **);
182 static struct mbuf *rtw_load_txbuf(struct rtw_softc *, struct rtw_txsoft *,
183 struct rtw_txsegs *, int, struct mbuf *);
184
185 static void rtw_idle(struct rtw_softc *);
186 static void rtw_txring_fixup(struct rtw_softc *);
187 static void rtw_rxring_fixup(struct rtw_softc *);
188 static int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *);
189 static void rtw_reset_oactive(struct rtw_softc *);
190
191 static int rtw_enable(struct rtw_softc *);
192 static void rtw_disable(struct rtw_softc *);
193 static void rtw_io_enable(struct rtw_softc *, uint8_t, int);
194 static int rtw_pwrstate(struct rtw_softc *, enum rtw_pwrstate);
195 static void rtw_set_access(struct rtw_softc *, enum rtw_access);
196
197 static void rtw_continuous_tx_enable(struct rtw_softc *, int);
198 static void rtw_txdac_enable(struct rtw_softc *, int);
199 static void rtw_anaparm_enable(struct rtw_regs *, int);
200 static void rtw_config0123_enable(struct rtw_regs *, int);
201
202 static void rtw_transmit_config(struct rtw_regs *);
203 static void rtw_set_rfprog(struct rtw_softc *);
204 static void rtw_enable_interrupts(struct rtw_softc *);
205 static void rtw_pktfilt_load(struct rtw_softc *);
206 static void rtw_wep_setkeys(struct rtw_softc *);
207 static void rtw_resume_ticks(struct rtw_softc *);
208 static void rtw_set_nettype(struct rtw_softc *, enum ieee80211_opmode);
209
210 static int rtw_reset(struct rtw_softc *);
211 static int rtw_chip_reset(struct rtw_softc *);
212 static int rtw_recall_eeprom(struct rtw_softc *);
213 static int rtw_srom_read(struct rtw_softc *);
214 static int rtw_srom_parse(struct rtw_softc *);
215 static struct rtw_rf *rtw_rf_attach(struct rtw_softc *, enum rtw_rfchipid, int);
216
217 static uint8_t rtw_check_phydelay(struct rtw_regs *, uint32_t);
218 static void rtw_identify_country(struct rtw_softc *);
219 static int rtw_identify_sta(struct rtw_softc *);
220
221 static int rtw_swring_setup(struct rtw_softc *);
222 static void rtw_hwring_setup(struct rtw_softc *);
223
224 static int rtw_desc_blk_alloc(struct rtw_softc *);
225 static void rtw_desc_blk_free(struct rtw_softc *);
226 static int rtw_soft_blk_alloc(struct rtw_softc *);
227 static void rtw_soft_blk_free(struct rtw_softc *);
228
229 static void rtw_txdesc_blk_init_all(struct rtw_softc *);
230 static void rtw_txsoft_blk_init_all(struct rtw_softc *);
231 static void rtw_rxdesc_blk_init_all(struct rtw_softc *);
232 static int rtw_rxsoft_blk_init_all(struct rtw_softc *);
233
234 static void rtw_txdesc_blk_reset_all(struct rtw_softc *);
235
236 static int rtw_rxsoft_alloc(struct rtw_softc *, struct rtw_rxsoft *, int);
237 static void rtw_rxdesc_init(struct rtw_softc *, int idx, int);
238
239 #ifdef RTW_DEBUG
240 static void rtw_print_txdesc(struct rtw_softc *, const char *,
241 struct rtw_txsoft *, struct rtw_txdesc_blk *,
242 int);
243 #endif /* RTW_DEBUG */
244
245 static int rtw_newstate(struct ieee80211com *, enum ieee80211_state, int);
246 static void rtw_next_scan(void *);
247
248 static int rtw_key_delete(struct ieee80211com *,
249 const struct ieee80211_key *);
250 static int rtw_key_set(struct ieee80211com *,
251 const struct ieee80211_key *,
252 const u_int8_t[IEEE80211_ADDR_LEN]);
253 static void rtw_key_update_end(struct ieee80211com *);
254 static void rtw_key_update_begin(struct ieee80211com *);
255 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int);
256
257 static int rtw_compute_duration1(int, int, uint32_t, int,
258 struct rtw_duration *);
259 static int rtw_compute_duration(const struct ieee80211_frame_min *,
260 const struct ieee80211_key *, int,
261 uint32_t, int, int,
262 struct rtw_duration *,
263 struct rtw_duration *, int *, int);
264
265 static int rtw_get_rssi(struct rtw_softc *, uint8_t, uint8_t);
266 static int rtw_maxim_getrssi(uint8_t, uint8_t);
267 static int rtw_gct_getrssi(uint8_t, uint8_t);
268 static int rtw_philips_getrssi(uint8_t, uint8_t);
269
270 #ifdef RTW_DEBUG
271 static void
272 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
273 {
274 #define PRINTREG32(sc, reg) \
275 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
276 ("%s: reg[ " #reg " / %03x ] = %08x\n", \
277 dvname, reg, RTW_READ(regs, reg)))
278
279 #define PRINTREG16(sc, reg) \
280 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
281 ("%s: reg[ " #reg " / %03x ] = %04x\n", \
282 dvname, reg, RTW_READ16(regs, reg)))
283
284 #define PRINTREG8(sc, reg) \
285 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
286 ("%s: reg[ " #reg " / %03x ] = %02x\n", \
287 dvname, reg, RTW_READ8(regs, reg)))
288
289 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where));
290
291 PRINTREG32(regs, RTW_IDR0);
292 PRINTREG32(regs, RTW_IDR1);
293 PRINTREG32(regs, RTW_MAR0);
294 PRINTREG32(regs, RTW_MAR1);
295 PRINTREG32(regs, RTW_TSFTRL);
296 PRINTREG32(regs, RTW_TSFTRH);
297 PRINTREG32(regs, RTW_TLPDA);
298 PRINTREG32(regs, RTW_TNPDA);
299 PRINTREG32(regs, RTW_THPDA);
300 PRINTREG32(regs, RTW_TCR);
301 PRINTREG32(regs, RTW_RCR);
302 PRINTREG32(regs, RTW_TINT);
303 PRINTREG32(regs, RTW_TBDA);
304 PRINTREG32(regs, RTW_ANAPARM);
305 PRINTREG32(regs, RTW_BB);
306 PRINTREG32(regs, RTW_PHYCFG);
307 PRINTREG32(regs, RTW_WAKEUP0L);
308 PRINTREG32(regs, RTW_WAKEUP0H);
309 PRINTREG32(regs, RTW_WAKEUP1L);
310 PRINTREG32(regs, RTW_WAKEUP1H);
311 PRINTREG32(regs, RTW_WAKEUP2LL);
312 PRINTREG32(regs, RTW_WAKEUP2LH);
313 PRINTREG32(regs, RTW_WAKEUP2HL);
314 PRINTREG32(regs, RTW_WAKEUP2HH);
315 PRINTREG32(regs, RTW_WAKEUP3LL);
316 PRINTREG32(regs, RTW_WAKEUP3LH);
317 PRINTREG32(regs, RTW_WAKEUP3HL);
318 PRINTREG32(regs, RTW_WAKEUP3HH);
319 PRINTREG32(regs, RTW_WAKEUP4LL);
320 PRINTREG32(regs, RTW_WAKEUP4LH);
321 PRINTREG32(regs, RTW_WAKEUP4HL);
322 PRINTREG32(regs, RTW_WAKEUP4HH);
323 PRINTREG32(regs, RTW_DK0);
324 PRINTREG32(regs, RTW_DK1);
325 PRINTREG32(regs, RTW_DK2);
326 PRINTREG32(regs, RTW_DK3);
327 PRINTREG32(regs, RTW_RETRYCTR);
328 PRINTREG32(regs, RTW_RDSAR);
329 PRINTREG32(regs, RTW_FER);
330 PRINTREG32(regs, RTW_FEMR);
331 PRINTREG32(regs, RTW_FPSR);
332 PRINTREG32(regs, RTW_FFER);
333
334 /* 16-bit registers */
335 PRINTREG16(regs, RTW_BRSR);
336 PRINTREG16(regs, RTW_IMR);
337 PRINTREG16(regs, RTW_ISR);
338 PRINTREG16(regs, RTW_BCNITV);
339 PRINTREG16(regs, RTW_ATIMWND);
340 PRINTREG16(regs, RTW_BINTRITV);
341 PRINTREG16(regs, RTW_ATIMTRITV);
342 PRINTREG16(regs, RTW_CRC16ERR);
343 PRINTREG16(regs, RTW_CRC0);
344 PRINTREG16(regs, RTW_CRC1);
345 PRINTREG16(regs, RTW_CRC2);
346 PRINTREG16(regs, RTW_CRC3);
347 PRINTREG16(regs, RTW_CRC4);
348 PRINTREG16(regs, RTW_CWR);
349
350 /* 8-bit registers */
351 PRINTREG8(regs, RTW_CR);
352 PRINTREG8(regs, RTW_9346CR);
353 PRINTREG8(regs, RTW_CONFIG0);
354 PRINTREG8(regs, RTW_CONFIG1);
355 PRINTREG8(regs, RTW_CONFIG2);
356 PRINTREG8(regs, RTW_MSR);
357 PRINTREG8(regs, RTW_CONFIG3);
358 PRINTREG8(regs, RTW_CONFIG4);
359 PRINTREG8(regs, RTW_TESTR);
360 PRINTREG8(regs, RTW_PSR);
361 PRINTREG8(regs, RTW_SCR);
362 PRINTREG8(regs, RTW_PHYDELAY);
363 PRINTREG8(regs, RTW_CRCOUNT);
364 PRINTREG8(regs, RTW_PHYADDR);
365 PRINTREG8(regs, RTW_PHYDATAW);
366 PRINTREG8(regs, RTW_PHYDATAR);
367 PRINTREG8(regs, RTW_CONFIG5);
368 PRINTREG8(regs, RTW_TPPOLL);
369
370 PRINTREG16(regs, RTW_BSSID16);
371 PRINTREG32(regs, RTW_BSSID32);
372 #undef PRINTREG32
373 #undef PRINTREG16
374 #undef PRINTREG8
375 }
376 #endif /* RTW_DEBUG */
377
378 static void
379 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
380 {
381 struct rtw_regs *regs = &sc->sc_regs;
382 uint32_t tcr;
383
384 tcr = RTW_READ(regs, RTW_TCR);
385 tcr &= ~RTW_TCR_LBK_MASK;
386 if (enable)
387 tcr |= RTW_TCR_LBK_CONT;
388 else
389 tcr |= RTW_TCR_LBK_NORMAL;
390 RTW_WRITE(regs, RTW_TCR, tcr);
391 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
392 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
393 rtw_txdac_enable(sc, !enable);
394 rtw_set_access(sc, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
395 rtw_set_access(sc, RTW_ACCESS_NONE);
396 }
397
398 #ifdef RTW_DEBUG
399 static const char *
400 rtw_access_string(enum rtw_access access)
401 {
402 switch (access) {
403 case RTW_ACCESS_NONE:
404 return "none";
405 case RTW_ACCESS_CONFIG:
406 return "config";
407 case RTW_ACCESS_ANAPARM:
408 return "anaparm";
409 default:
410 return "unknown";
411 }
412 }
413 #endif /* RTW_DEBUG */
414
415 static void
416 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
417 {
418 KKASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM);
419 KKASSERT(regs->r_access >= RTW_ACCESS_NONE &&
420 regs->r_access <= RTW_ACCESS_ANAPARM);
421
422 if (naccess == regs->r_access)
423 return;
424
425 switch (naccess) {
426 case RTW_ACCESS_NONE:
427 switch (regs->r_access) {
428 case RTW_ACCESS_ANAPARM:
429 rtw_anaparm_enable(regs, 0);
430 /*FALLTHROUGH*/
431 case RTW_ACCESS_CONFIG:
432 rtw_config0123_enable(regs, 0);
433 /*FALLTHROUGH*/
434 case RTW_ACCESS_NONE:
435 break;
436 }
437 break;
438 case RTW_ACCESS_CONFIG:
439 switch (regs->r_access) {
440 case RTW_ACCESS_NONE:
441 rtw_config0123_enable(regs, 1);
442 /*FALLTHROUGH*/
443 case RTW_ACCESS_CONFIG:
444 break;
445 case RTW_ACCESS_ANAPARM:
446 rtw_anaparm_enable(regs, 0);
447 break;
448 }
449 break;
450 case RTW_ACCESS_ANAPARM:
451 switch (regs->r_access) {
452 case RTW_ACCESS_NONE:
453 rtw_config0123_enable(regs, 1);
454 /*FALLTHROUGH*/
455 case RTW_ACCESS_CONFIG:
456 rtw_anaparm_enable(regs, 1);
457 /*FALLTHROUGH*/
458 case RTW_ACCESS_ANAPARM:
459 break;
460 }
461 break;
462 }
463 }
464
465 static void
466 rtw_set_access(struct rtw_softc *sc, enum rtw_access access)
467 {
468 struct rtw_regs *regs = &sc->sc_regs;
469
470 rtw_set_access1(regs, access);
471 RTW_DPRINTF(RTW_DEBUG_ACCESS,
472 ("%s: access %s -> %s\n", sc->sc_ic.ic_if.if_xname,
473 rtw_access_string(regs->r_access),
474 rtw_access_string(access)));
475 regs->r_access = access;
476 }
477
478 /*
479 * Enable registers, switch register banks.
480 */
481 static void
482 rtw_config0123_enable(struct rtw_regs *regs, int enable)
483 {
484 uint8_t ecr;
485
486 ecr = RTW_READ8(regs, RTW_9346CR);
487 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);
488 if (enable) {
489 ecr |= RTW_9346CR_EEM_CONFIG;
490 } else {
491 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
492 ecr |= RTW_9346CR_EEM_NORMAL;
493 }
494 RTW_WRITE8(regs, RTW_9346CR, ecr);
495 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
496 }
497
498 /* requires rtw_config0123_enable(, 1) */
499 static void
500 rtw_anaparm_enable(struct rtw_regs *regs, int enable)
501 {
502 uint8_t cfg3;
503
504 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
505 cfg3 |= RTW_CONFIG3_CLKRUNEN;
506 if (enable)
507 cfg3 |= RTW_CONFIG3_PARMEN;
508 else
509 cfg3 &= ~RTW_CONFIG3_PARMEN;
510 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
511 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
512 }
513
514 /* requires rtw_anaparm_enable(, 1) */
515 static void
516 rtw_txdac_enable(struct rtw_softc *sc, int enable)
517 {
518 uint32_t anaparm;
519 struct rtw_regs *regs = &sc->sc_regs;
520
521 anaparm = RTW_READ(regs, RTW_ANAPARM);
522 if (enable)
523 anaparm &= ~RTW_ANAPARM_TXDACOFF;
524 else
525 anaparm |= RTW_ANAPARM_TXDACOFF;
526 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
527 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
528 }
529
530 static int
531 rtw_chip_reset1(struct rtw_softc *sc)
532 {
533 struct rtw_regs *regs = &sc->sc_regs;
534 uint8_t cr;
535 int i;
536
537 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
538
539 RTW_WBR(regs, RTW_CR, RTW_CR);
540
541 for (i = 0; i < 1000; i++) {
542 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
543 RTW_DPRINTF(RTW_DEBUG_RESET,
544 ("%s: reset in %dus\n",
545 sc->sc_ic.ic_if.if_xname, i));
546 return 0;
547 }
548 RTW_RBR(regs, RTW_CR, RTW_CR);
549 DELAY(10); /* 10us */
550 }
551
552 if_printf(&sc->sc_ic.ic_if, "reset failed\n");
553 return ETIMEDOUT;
554 }
555
556 static int
557 rtw_chip_reset(struct rtw_softc *sc)
558 {
559 struct rtw_regs *regs = &sc->sc_regs;
560 uint32_t tcr;
561
562 /* from Linux driver */
563 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 |
564 SHIFTIN(7, RTW_TCR_SRL_MASK) | SHIFTIN(7, RTW_TCR_LRL_MASK);
565
566 RTW_WRITE(regs, RTW_TCR, tcr);
567
568 RTW_WBW(regs, RTW_CR, RTW_TCR);
569
570 return rtw_chip_reset1(sc);
571 }
572
573 static int
574 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen)
575 {
576 struct ieee80211_key keycopy;
577 const struct ieee80211_cipher *wep_cipher;
578
579 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__));
580
581 keycopy = *k;
582 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT;
583
584 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
585 KKASSERT(wep_cipher != NULL);
586
587 return wep_cipher->ic_decap(&keycopy, m, hdrlen);
588 }
589
590 static int
591 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
592 {
593 struct rtw_softc *sc = ic->ic_ifp->if_softc;
594 u_int keyix = k->wk_keyix;
595
596 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix));
597
598 if (keyix >= IEEE80211_WEP_NKID)
599 return 0;
600 if (k->wk_keylen != 0)
601 sc->sc_flags &= ~RTW_F_DK_VALID;
602 return 1;
603 }
604
605 static int
606 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
607 const u_int8_t mac[IEEE80211_ADDR_LEN])
608 {
609 struct rtw_softc *sc = ic->ic_ifp->if_softc;
610
611 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix));
612
613 if (k->wk_keyix >= IEEE80211_WEP_NKID)
614 return 0;
615
616 sc->sc_flags &= ~RTW_F_DK_VALID;
617 return 1;
618 }
619
620 static void
621 rtw_key_update_begin(struct ieee80211com *ic)
622 {
623 #ifdef RTW_DEBUG
624 struct ifnet *ifp = ic->ic_ifp;
625 struct rtw_softc *sc = ifp->if_softc;
626 #endif
627
628 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
629 }
630
631 static void
632 rtw_key_update_end(struct ieee80211com *ic)
633 {
634 struct ifnet *ifp = ic->ic_ifp;
635 struct rtw_softc *sc = ifp->if_softc;
636
637 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
638
639 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 ||
640 (sc->sc_flags & RTW_F_ENABLED) == 0 ||
641 (sc->sc_flags & RTW_F_INVALID) != 0)
642 return;
643
644 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
645 rtw_wep_setkeys(sc);
646 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE,
647 (ifp->if_flags & IFF_RUNNING) != 0);
648 }
649
650 static __inline int
651 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k)
652 {
653 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
654 return 0;
655
656 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) ||
657 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13);
658 }
659
660 static void
661 rtw_wep_setkeys(struct rtw_softc *sc)
662 {
663 struct ieee80211com *ic = &sc->sc_ic;
664 struct ieee80211_key *wk = ic->ic_nw_keys;
665 const struct ieee80211_cipher *wep_cipher;
666 struct rtw_regs *regs = &sc->sc_regs;
667 union rtw_keys *rk = &sc->sc_keys;
668 uint8_t psr, scr;
669 int i, keylen;
670
671 memset(rk->rk_keys, 0, sizeof(rk->rk_keys));
672
673 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
674 KKASSERT(wep_cipher != NULL);
675
676 /* Temporarily use software crypto for all keys. */
677 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
678 if (wk[i].wk_cipher == &rtw_cipher_wep)
679 wk[i].wk_cipher = wep_cipher;
680 }
681
682 rtw_set_access(sc, RTW_ACCESS_CONFIG);
683
684 psr = RTW_READ8(regs, RTW_PSR);
685 scr = RTW_READ8(regs, RTW_SCR);
686 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON);
687
688 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
689 goto out;
690
691 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) {
692 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i]))
693 continue;
694 if (i == ic->ic_def_txkey) {
695 keylen = wk[i].wk_keylen;
696 break;
697 }
698 keylen = MAX(keylen, wk[i].wk_keylen);
699 }
700
701 if (keylen == 5)
702 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON;
703 else if (keylen == 13)
704 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON;
705
706 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
707 if (wk[i].wk_keylen != keylen ||
708 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
709 continue;
710 /* h/w will decrypt, s/w still strips headers */
711 wk[i].wk_cipher = &rtw_cipher_wep;
712 memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen);
713 }
714 out:
715 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN);
716
717 bus_space_write_region_4(regs->r_bt, regs->r_bh, RTW_DK0, rk->rk_words,
718 sizeof(rk->rk_words) / sizeof(rk->rk_words[0]));
719
720 RTW_WBW(regs, RTW_DK0, RTW_PSR);
721 RTW_WRITE8(regs, RTW_PSR, psr);
722 RTW_WBW(regs, RTW_PSR, RTW_SCR);
723 RTW_WRITE8(regs, RTW_SCR, scr);
724 RTW_SYNC(regs, RTW_SCR, RTW_SCR);
725 rtw_set_access(sc, RTW_ACCESS_NONE);
726 sc->sc_flags |= RTW_F_DK_VALID;
727 }
728
729 static int
730 rtw_recall_eeprom(struct rtw_softc *sc)
731 {
732 struct rtw_regs *regs = &sc->sc_regs;
733 int i;
734 uint8_t ecr;
735
736 ecr = RTW_READ8(regs, RTW_9346CR);
737 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;
738 RTW_WRITE8(regs, RTW_9346CR, ecr);
739
740 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
741
742 /* wait 25ms for completion */
743 for (i = 0; i < 250; i++) {
744 ecr = RTW_READ8(regs, RTW_9346CR);
745 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {
746 RTW_DPRINTF(RTW_DEBUG_RESET,
747 ("%s: recall EEPROM in %dus\n",
748 sc->sc_ic.ic_if.if_xname, i * 100));
749 return 0;
750 }
751 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
752 DELAY(100);
753 }
754 if_printf(&sc->sc_ic.ic_if, "recall EEPROM failed\n");
755 return ETIMEDOUT;
756 }
757
758 static int
759 rtw_reset(struct rtw_softc *sc)
760 {
761 struct rtw_regs *regs = &sc->sc_regs;
762 uint8_t config1;
763 int rc;
764
765 sc->sc_flags &= ~RTW_F_DK_VALID;
766
767 rc = rtw_chip_reset(sc);
768 if (rc)
769 return rc;
770
771 rtw_recall_eeprom(sc); /* ignore err */
772
773 config1 = RTW_READ8(regs, RTW_CONFIG1);
774 RTW_WRITE8(regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN);
775 /* TBD turn off maximum power saving? */
776 return 0;
777 }
778
779 static int
780 rtw_srom_parse(struct rtw_softc *sc)
781 {
782 struct rtw_srom *sr = &sc->sc_srom;
783 char scratch[sizeof("unknown 0xXX")];
784 uint8_t mac[IEEE80211_ADDR_LEN];
785 const char *rfname, *paname;
786 uint16_t srom_version;
787 int i;
788
789 sc->sc_flags &= ~(RTW_F_DIGPHY | RTW_F_DFLANTB | RTW_F_ANTDIV);
790 sc->sc_rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
791
792 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION);
793 if_printf(&sc->sc_ic.ic_if, "SROM version %d.%d",
794 srom_version >> 8, srom_version & 0xff);
795
796 if (srom_version <= 0x0101) {
797 kprintf(" is not understood, limping along with defaults\n");
798
799 /* Default values */
800 sc->sc_flags |= (RTW_F_DIGPHY | RTW_F_ANTDIV);
801 sc->sc_csthr = RTW_SR_ENERGYDETTHR_DEFAULT;
802 sc->sc_rcr |= RTW_RCR_ENCS1;
803 sc->sc_rfchipid = RTW_RFCHIPID_PHILIPS;
804 return 0;
805 }
806 kprintf("\n");
807
808 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
809 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);
810
811 RTW_DPRINTF(RTW_DEBUG_ATTACH,
812 ("%s: EEPROM MAC %6D\n", sc->sc_ic.ic_if.if_xname, mac, ":"));
813
814 sc->sc_csthr = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);
815
816 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)
817 sc->sc_flags |= RTW_F_ANTDIV;
818
819 /*
820 * Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems
821 * to be reversed.
822 */
823 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)
824 sc->sc_flags |= RTW_F_DIGPHY;
825 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)
826 sc->sc_flags |= RTW_F_DFLANTB;
827
828 sc->sc_rcr |= SHIFTIN(SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
829 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);
830
831 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0)
832 sc->sc_flags |= RTW_C_RXWEP_104;
833
834 sc->sc_flags |= RTW_C_RXWEP_40; /* XXX */
835
836 sc->sc_rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);
837 switch (sc->sc_rfchipid) {
838 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */
839 rfname = "GCT GRF5101";
840 paname = "Winspring WS9901";
841 break;
842 case RTW_RFCHIPID_MAXIM:
843 rfname = "Maxim MAX2820"; /* guess */
844 paname = "Maxim MAX2422"; /* guess */
845 break;
846 case RTW_RFCHIPID_INTERSIL:
847 rfname = "Intersil HFA3873"; /* guess */
848 paname = "Intersil <unknown>";
849 break;
850 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */
851 rfname = "Philips SA2400A";
852 paname = "Philips SA2411";
853 break;
854 case RTW_RFCHIPID_RFMD:
855 /* this is the same front-end as an atw(4)! */
856 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */
857 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */
858 "SYN: Silicon Labs Si4126"; /* inferred from
859 * reference driver
860 */
861 paname = "RFMD RF2189"; /* mentioned in Realtek docs */
862 break;
863 case RTW_RFCHIPID_RESERVED:
864 rfname = paname = "reserved";
865 break;
866 default:
867 ksnprintf(scratch, sizeof(scratch), "unknown 0x%02x",
868 sc->sc_rfchipid);
869 rfname = paname = scratch;
870 }
871 if_printf(&sc->sc_ic.ic_if, "RF: %s, PA: %s\n", rfname, paname);
872
873 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {
874 case RTW_CONFIG0_GL_USA:
875 case _RTW_CONFIG0_GL_USA:
876 sc->sc_locale = RTW_LOCALE_USA;
877 break;
878 case RTW_CONFIG0_GL_EUROPE:
879 sc->sc_locale = RTW_LOCALE_EUROPE;
880 break;
881 case RTW_CONFIG0_GL_JAPAN:
882 sc->sc_locale = RTW_LOCALE_JAPAN;
883 break;
884 default:
885 sc->sc_locale = RTW_LOCALE_UNKNOWN;
886 break;
887 }
888 return 0;
889 }
890
891 static int
892 rtw_srom_read(struct rtw_softc *sc)
893 {
894 struct rtw_regs *regs = &sc->sc_regs;
895 struct rtw_srom *sr = &sc->sc_srom;
896 struct seeprom_descriptor sd;
897 uint8_t ecr;
898 int rc;
899
900 memset(&sd, 0, sizeof(sd));
901
902 ecr = RTW_READ8(regs, RTW_9346CR);
903
904 if ((sc->sc_flags & RTW_F_9356SROM) != 0) {
905 RTW_DPRINTF(RTW_DEBUG_ATTACH,
906 ("%s: 93c56 SROM\n", sc->sc_ic.ic_if.if_xname));
907 sr->sr_size = 256;
908 sd.sd_chip = C56_66;
909 } else {
910 RTW_DPRINTF(RTW_DEBUG_ATTACH,
911 ("%s: 93c46 SROM\n", sc->sc_ic.ic_if.if_xname));
912 sr->sr_size = 128;
913 sd.sd_chip = C46;
914 }
915
916 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
917 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
918 ecr |= RTW_9346CR_EEM_PROGRAM;
919
920 RTW_WRITE8(regs, RTW_9346CR, ecr);
921
922 sr->sr_content = kmalloc(sr->sr_size, M_DEVBUF, M_WAITOK | M_ZERO);
923
924 /*
925 * RTL8180 has a single 8-bit register for controlling the
926 * 93cx6 SROM. There is no "ready" bit. The RTL8180
927 * input/output sense is the reverse of read_seeprom's.
928 */
929 sd.sd_tag = regs->r_bt;
930 sd.sd_bsh = regs->r_bh;
931 sd.sd_regsize = 1;
932 sd.sd_control_offset = RTW_9346CR;
933 sd.sd_status_offset = RTW_9346CR;
934 sd.sd_dataout_offset = RTW_9346CR;
935 sd.sd_CK = RTW_9346CR_EESK;
936 sd.sd_CS = RTW_9346CR_EECS;
937 sd.sd_DI = RTW_9346CR_EEDO;
938 sd.sd_DO = RTW_9346CR_EEDI;
939 /* make read_seeprom enter EEPROM read/write mode */
940 sd.sd_MS = ecr;
941 sd.sd_RDY = 0;
942
943 /* TBD bus barriers */
944 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size / 2)) {
945 if_printf(&sc->sc_ic.ic_if, "could not read SROM\n");
946 kfree(sr->sr_content, M_DEVBUF);
947 sr->sr_content = NULL;
948 return EIO; /* XXX */
949 }
950
951 /* end EEPROM read/write mode */
952 RTW_WRITE8(regs, RTW_9346CR,
953 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);
954 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
955
956 rc = rtw_recall_eeprom(sc);
957 if (rc)
958 return rc;
959
960 #ifdef RTW_DEBUG
961 {
962 int i;
963 RTW_DPRINTF(RTW_DEBUG_ATTACH,
964 ("\n%s: serial ROM:\n\t", sc->sc_ic.ic_if.if_xname));
965 for (i = 0; i < sr->sr_size/2; i++) {
966 if (((i % 8) == 0) && (i != 0))
967 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t"));
968 RTW_DPRINTF(RTW_DEBUG_ATTACH,
969 (" %04x", sr->sr_content[i]));
970 }
971 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n"));
972 }
973 #endif /* RTW_DEBUG */
974 return 0;
975 }
976
977 static void
978 rtw_set_rfprog(struct rtw_softc *sc)
979 {
980 struct rtw_regs *regs = &sc->sc_regs;
981 const char *method;
982 uint8_t cfg4;
983
984 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
985
986 switch (sc->sc_rfchipid) {
987 default:
988 cfg4 |= SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
989 method = "fallback";
990 break;
991 case RTW_RFCHIPID_INTERSIL:
992 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;
993 method = "Intersil";
994 break;
995 case RTW_RFCHIPID_PHILIPS:
996 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;
997 method = "Philips";
998 break;
999 case RTW_RFCHIPID_GCT: /* XXX a guess */
1000 case RTW_RFCHIPID_RFMD:
1001 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;
1002 method = "RFMD";
1003 break;
1004 }
1005
1006 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
1007
1008 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
1009
1010 RTW_DPRINTF(RTW_DEBUG_INIT,
1011 ("%s: %s RF programming method, %#02x\n",
1012 sc->sc_ic.ic_if.if_xname, method,
1013 RTW_READ8(regs, RTW_CONFIG4)));
1014 }
1015
1016 static __inline void
1017 rtw_init_channels(struct rtw_softc *sc)
1018 {
1019 const char *name = NULL;
1020 struct ieee80211_channel *chans = sc->sc_ic.ic_channels;
1021 int i;
1022 #define ADD_CHANNEL(_chans, _chan) do { \
1023 _chans[_chan].ic_flags = IEEE80211_CHAN_B; \
1024 _chans[_chan].ic_freq = \
1025 ieee80211_ieee2mhz(_chan, _chans[_chan].ic_flags); \
1026 } while (0)
1027
1028 switch (sc->sc_locale) {
1029 case RTW_LOCALE_USA: /* 1-11 */
1030 name = "USA";
1031 for (i = 1; i <= 11; i++)
1032 ADD_CHANNEL(chans, i);
1033 break;
1034 case RTW_LOCALE_JAPAN: /* 1-14 */
1035 name = "Japan";
1036 ADD_CHANNEL(chans, 14);
1037 for (i = 1; i <= 14; i++)
1038 ADD_CHANNEL(chans, i);
1039 break;
1040 case RTW_LOCALE_EUROPE: /* 1-13 */
1041 name = "Europe";
1042 for (i = 1; i <= 13; i++)
1043 ADD_CHANNEL(chans, i);
1044 break;
1045 default: /* 10-11 allowed by most countries */
1046 name = "<unknown>";
1047 for (i = 10; i <= 11; i++)
1048 ADD_CHANNEL(chans, i);
1049 break;
1050 }
1051 if_printf(&sc->sc_ic.ic_if, "Geographic Location %s\n", name);
1052 #undef ADD_CHANNEL
1053 }
1054
1055
1056 static void
1057 rtw_identify_country(struct rtw_softc *sc)
1058 {
1059 uint8_t cfg0;
1060
1061 cfg0 = RTW_READ8(&sc->sc_regs, RTW_CONFIG0);
1062 switch (cfg0 & RTW_CONFIG0_GL_MASK) {
1063 case RTW_CONFIG0_GL_USA:
1064 case _RTW_CONFIG0_GL_USA:
1065 sc->sc_locale = RTW_LOCALE_USA;
1066 break;
1067 case RTW_CONFIG0_GL_JAPAN:
1068 sc->sc_locale = RTW_LOCALE_JAPAN;
1069 break;
1070 case RTW_CONFIG0_GL_EUROPE:
1071 sc->sc_locale = RTW_LOCALE_EUROPE;
1072 break;
1073 default:
1074 sc->sc_locale = RTW_LOCALE_UNKNOWN;
1075 break;
1076 }
1077 }
1078
1079 static int
1080 rtw_identify_sta(struct rtw_softc *sc)
1081 {
1082 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
1083 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1084 };
1085 struct rtw_regs *regs = &sc->sc_regs;
1086 uint8_t *addr = sc->sc_ic.ic_myaddr;
1087 uint32_t idr0, idr1;
1088
1089 idr0 = RTW_READ(regs, RTW_IDR0);
1090 idr1 = RTW_READ(regs, RTW_IDR1);
1091
1092 addr[0] = SHIFTOUT(idr0, __BITS(0, 7));
1093 addr[1] = SHIFTOUT(idr0, __BITS(8, 15));
1094 addr[2] = SHIFTOUT(idr0, __BITS(16, 23));
1095 addr[3] = SHIFTOUT(idr0, __BITS(24 ,31));
1096
1097 addr[4] = SHIFTOUT(idr1, __BITS(0, 7));
1098 addr[5] = SHIFTOUT(idr1, __BITS(8, 15));
1099
1100 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) {
1101 if_printf(&sc->sc_ic.ic_if, "could not get mac address\n");
1102 return ENXIO;
1103 }
1104 return 0;
1105 }
1106
1107 static uint8_t
1108 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,
1109 struct ieee80211_channel *chan)
1110 {
1111 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;
1112
1113 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14,
1114 ("%s: channel %d out of range", __func__,
1115 idx - RTW_SR_TXPOWER1 + 1));
1116 return RTW_SR_GET(sr, idx);
1117 }
1118
1119 static void
1120 rtw_txdesc_blk_init_all(struct rtw_softc *sc)
1121 {
1122 /* nfree: the number of free descriptors in each ring.
1123 * The beacon ring is a special case: I do not let the
1124 * driver use all of the descriptors on the beacon ring.
1125 * The reasons are two-fold:
1126 *
1127 * (1) A BEACON descriptor's OWN bit is (apparently) not
1128 * updated, so the driver cannot easily know if the descriptor
1129 * belongs to it, or if it is racing the NIC. If the NIC
1130 * does not OWN every descriptor, then the driver can safely
1131 * update the descriptors when RTW_TBDA points at tdb_next.
1132 *
1133 * (2) I hope that the NIC will process more than one BEACON
1134 * descriptor in a single beacon interval, since that will
1135 * enable multiple-BSS support. Since the NIC does not
1136 * clear the OWN bit, there is no natural place for it to
1137 * stop processing BEACON desciptors. Maybe it will *not*
1138 * stop processing them! I do not want to chance the NIC
1139 * looping around and around a saturated beacon ring, so
1140 * I will leave one descriptor unOWNed at all times.
1141 */
1142 int nfree[RTW_NTXPRI] = {
1143 RTW_NTXDESCLO,
1144 RTW_NTXDESCMD,
1145 RTW_NTXDESCHI,
1146 RTW_NTXDESCBCN - 1
1147 };
1148 struct rtw_txdesc_blk *tdb;
1149 int pri;
1150
1151 for (tdb = sc->sc_txdesc_blk, pri = 0; pri < RTW_NTXPRI; tdb++, pri++) {
1152 tdb->tdb_nfree = nfree[pri];
1153 tdb->tdb_next = 0;
1154
1155 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1156 BUS_DMASYNC_PREWRITE);
1157 }
1158 }
1159
1160 static void
1161 rtw_txsoft_blk_init_all(struct rtw_softc *sc)
1162 {
1163 struct rtw_txsoft_blk *tsb;
1164 int pri;
1165
1166 for (tsb = sc->sc_txsoft_blk, pri = 0; pri < RTW_NTXPRI; tsb++, pri++) {
1167 int i;
1168
1169 STAILQ_INIT(&tsb->tsb_dirtyq);
1170 STAILQ_INIT(&tsb->tsb_freeq);
1171 for (i = 0; i < tsb->tsb_ndesc; i++) {
1172 struct rtw_txsoft *ts;
1173
1174 ts = &tsb->tsb_desc[i];
1175 ts->ts_mbuf = NULL;
1176 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1177 }
1178 tsb->tsb_tx_timer = 0;
1179 }
1180 }
1181
1182 static void
1183 rtw_rxbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
1184 bus_size_t mapsize, int error)
1185 {
1186 if (error)
1187 return;
1188
1189 KASSERT(nseg == 1, ("too many rx mbuf seg\n"));
1190
1191 *((bus_addr_t *)arg) = seg->ds_addr;
1192 }
1193
1194 static int
1195 rtw_rxsoft_alloc(struct rtw_softc *sc, struct rtw_rxsoft *rs, int waitok)
1196 {
1197 bus_addr_t paddr;
1198 bus_dmamap_t map;
1199 struct mbuf *m;
1200 int rc;
1201
1202 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1203 if (m == NULL)
1204 return ENOBUFS;
1205
1206 m->m_pkthdr.len = m->m_len = MCLBYTES;
1207
1208 rc = bus_dmamap_load_mbuf(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap, m,
1209 rtw_rxbuf_dma_map, &paddr,
1210 waitok ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1211 if (rc) {
1212 if_printf(&sc->sc_ic.ic_if, "can't load rx mbuf\n");
1213 m_freem(m);
1214 return rc;
1215 }
1216
1217 if (rs->rs_mbuf != NULL)
1218 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
1219
1220 /* Swap DMA map */
1221 map = rs->rs_dmamap;
1222 rs->rs_dmamap = sc->sc_rxsoft_dmamap;
1223 sc->sc_rxsoft_dmamap = map;
1224
1225 rs->rs_mbuf = m;
1226 rs->rs_phyaddr = paddr;
1227
1228 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap, BUS_DMASYNC_PREREAD);
1229 return 0;
1230 }
1231
1232 static int
1233 rtw_rxsoft_blk_init_all(struct rtw_softc *sc)
1234 {
1235 int i, rc = 0;
1236
1237 for (i = 0; i < RTW_RXQLEN; i++) {
1238 struct rtw_rxsoft *rs;
1239
1240 rs = &sc->sc_rxsoft[i];
1241 /* we're in rtw_init, so there should be no mbufs allocated */
1242 KKASSERT(rs->rs_mbuf == NULL);
1243 #ifdef RTW_DEBUG
1244 if (i == rtw_rxbufs_limit) {
1245 if_printf(&sc->sc_ic.ic_if,
1246 "TEST hit %d-buffer limit\n", i);
1247 rc = ENOBUFS;
1248 break;
1249 }
1250 #endif /* RTW_DEBUG */
1251 rc = rtw_rxsoft_alloc(sc, rs, 1);
1252 if (rc)
1253 break;
1254 }
1255 return rc;
1256 }
1257
1258 static void
1259 rtw_rxdesc_init(struct rtw_softc *sc, int idx, int kick)
1260 {
1261 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1262 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx];
1263 struct rtw_rxsoft *rs = &sc->sc_rxsoft[idx];
1264 uint32_t ctl;
1265
1266 #ifdef RTW_DEBUG
1267 uint32_t octl, obuf;
1268
1269 obuf = rd->rd_buf;
1270 octl = rd->rd_ctl;
1271 #endif /* RTW_DEBUG */
1272
1273 rd->rd_buf = htole32(rs->rs_phyaddr);
1274
1275 ctl = SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
1276 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS;
1277
1278 if (idx == rdb->rdb_ndesc - 1)
1279 ctl |= RTW_RXCTL_EOR;
1280
1281 rd->rd_ctl = htole32(ctl);
1282
1283 RTW_DPRINTF(kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK)
1284 : RTW_DEBUG_RECV_DESC,
1285 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n",
1286 sc->sc_ic.ic_if.if_xname, rd, le32toh(obuf),
1287 le32toh(rd->rd_buf), le32toh(octl), le32toh(rd->rd_ctl)));
1288 }
1289
1290 static void
1291 rtw_rxdesc_blk_init_all(struct rtw_softc *sc)
1292 {
1293 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1294 int i;
1295
1296 for (i = 0; i < rdb->rdb_ndesc; i++)
1297 rtw_rxdesc_init(sc, i, 1);
1298
1299 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_PREWRITE);
1300 }
1301
1302 static void
1303 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable)
1304 {
1305 struct rtw_regs *regs = &sc->sc_regs;
1306 uint8_t cr;
1307
1308 RTW_DPRINTF(RTW_DEBUG_IOSTATE,
1309 ("%s: %s 0x%02x\n", sc->sc_ic.ic_if.if_xname,
1310 enable ? "enable" : "disable", flags));
1311
1312 cr = RTW_READ8(regs, RTW_CR);
1313
1314 /* XXX reference source does not enable MULRW */
1315 #if 0
1316 /* enable PCI Read/Write Multiple */
1317 cr |= RTW_CR_MULRW;
1318 #endif
1319
1320 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
1321 if (enable)
1322 cr |= flags;
1323 else
1324 cr &= ~flags;
1325 RTW_WRITE8(regs, RTW_CR, cr);
1326 RTW_SYNC(regs, RTW_CR, RTW_CR);
1327 }
1328
1329 static void
1330 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr)
1331 {
1332 #define IS_BEACON(__fc0) \
1333 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\
1334 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON))
1335
1336 /*
1337 * convert rates:
1338 * hardware -> net80211
1339 */
1340 static const int ratetbl[4] = { 2, 4, 11, 22 };
1341 struct ifnet *ifp = &sc->sc_if;
1342 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1343 int next, nproc = 0, sync = 0;
1344
1345 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1346
1347 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_POSTREAD);
1348
1349 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) {
1350 struct ieee80211_node *ni;
1351 struct ieee80211_frame_min *wh;
1352 struct rtw_rxdesc *rd;
1353 struct rtw_rxsoft *rs;
1354 struct mbuf *m;
1355 int hwrate, len, rate, rssi, sq, error;
1356 uint32_t hrssi, hstat, htsfth, htsftl;
1357
1358 rd = &rdb->rdb_desc[next];
1359 rs = &sc->sc_rxsoft[next];
1360
1361 hstat = le32toh(rd->rd_stat);
1362 hrssi = le32toh(rd->rd_rssi);
1363 htsfth = le32toh(rd->rd_tsfth);
1364 htsftl = le32toh(rd->rd_tsftl);
1365
1366 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1367 ("%s: rxdesc[%d] hstat %08x hrssi %08x "
1368 "htsft %08x%08x\n", ifp->if_xname,
1369 next, hstat, hrssi, htsfth, htsftl));
1370
1371 ++nproc;
1372
1373 /* still belongs to NIC */
1374 if (hstat & RTW_RXSTAT_OWN) {
1375 if (nproc > 1)
1376 break;
1377
1378 /* sometimes the NIC skips to the 0th descriptor */
1379 rd = &rdb->rdb_desc[0];
1380 if (rd->rd_stat & htole32(RTW_RXSTAT_OWN))
1381 break;
1382 RTW_DPRINTF(RTW_DEBUG_BUGS,
1383 ("%s: NIC skipped from rxdesc[%u] "
1384 "to rxdesc[0]\n", ifp->if_xname, next));
1385 next = rdb->rdb_ndesc - 1;
1386 continue;
1387 }
1388
1389 #ifdef RTW_DEBUG
1390 #define PRINTSTAT(flag) do { \
1391 if ((hstat & flag) != 0) { \
1392 kprintf("%s" #flag, delim); \
1393 delim = ","; \
1394 } \
1395 } while (0)
1396 if (rtw_debug & RTW_DEBUG_RECV_DESC) {
1397 const char *delim = "<";
1398
1399 if_printf(ifp, "%s", "");
1400 if ((hstat & RTW_RXSTAT_DEBUG) != 0) {
1401 kprintf("status %08x", hstat);
1402 PRINTSTAT(RTW_RXSTAT_SPLCP);
1403 PRINTSTAT(RTW_RXSTAT_MAR);
1404 PRINTSTAT(RTW_RXSTAT_PAR);
1405 PRINTSTAT(RTW_RXSTAT_BAR);
1406 PRINTSTAT(RTW_RXSTAT_PWRMGT);
1407 PRINTSTAT(RTW_RXSTAT_CRC32);
1408 PRINTSTAT(RTW_RXSTAT_ICV);
1409 kprintf(">, ");
1410 }
1411 }
1412 #endif /* RTW_DEBUG */
1413
1414 if (hstat & RTW_RXSTAT_IOERROR) {
1415 if_printf(ifp, "DMA error/FIFO overflow %08x, "
1416 "rx descriptor %d\n",
1417 hstat & RTW_RXSTAT_IOERROR, next);
1418 ifp->if_ierrors++;
1419 goto next;
1420 }
1421
1422 len = SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);
1423 if (len < IEEE80211_MIN_LEN) {
1424 sc->sc_ic.ic_stats.is_rx_tooshort++;
1425 goto next;
1426 }
1427
1428 /* CRC is included with the packet; trim it off. */
1429 len -= IEEE80211_CRC_LEN;
1430
1431 hwrate = SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);
1432 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) {
1433 if_printf(ifp, "unknown rate #%d\n",
1434 SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));
1435 ifp->if_ierrors++;
1436 goto next;
1437 }
1438 rate = ratetbl[hwrate];
1439
1440 #ifdef RTW_DEBUG
1441 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1442 ("%s rate %d.%d Mb/s, time %08x%08x\n",
1443 ifp->if_xname, (rate * 5) / 10,
1444 (rate * 5) % 10, htsfth, htsftl));
1445 #endif /* RTW_DEBUG */
1446
1447 if ((hstat & RTW_RXSTAT_RES) &&
1448 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
1449 goto next;
1450
1451 /* if bad flags, skip descriptor */
1452 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) {
1453 if_printf(ifp, "too many rx segments\n");
1454 goto next;
1455 }
1456
1457 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
1458 BUS_DMASYNC_POSTREAD);
1459
1460 m = rs->rs_mbuf;
1461
1462 /* if temporarily out of memory, re-use mbuf */
1463 error = rtw_rxsoft_alloc(sc, rs, 0);
1464 if (error) {
1465 if_printf(ifp, "%s: rtw_rxsoft_alloc(, %d) failed, "
1466 "dropping packet\n", ifp->if_xname, next);
1467 goto next;
1468 }
1469
1470 rssi = SHIFTOUT(hrssi, RTW_RXRSSI_RSSI);
1471 sq = SHIFTOUT(hrssi, RTW_RXRSSI_SQ);
1472
1473 rssi = rtw_get_rssi(sc, rssi, sq);
1474
1475 /*
1476 * Note well: now we cannot recycle the rs_mbuf unless
1477 * we restore its original length.
1478 */
1479 m->m_pkthdr.rcvif = ifp;
1480 m->m_pkthdr.len = m->m_len = len;
1481
1482 wh = mtod(m, struct ieee80211_frame_min *);
1483
1484 if (!IS_BEACON(wh->i_fc[0]))
1485 sc->sc_led_state.ls_event |= RTW_LED_S_RX;
1486
1487 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */
1488 ni = ieee80211_find_rxnode(&sc->sc_ic, wh);
1489
1490 sc->sc_tsfth = htsfth;
1491
1492 #ifdef RTW_DEBUG
1493 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
1494 (IFF_DEBUG | IFF_LINK2)) {
1495 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len,
1496 rate, rssi);
1497 }
1498 #endif /* RTW_DEBUG */
1499
1500 if (sc->sc_radiobpf != NULL) {
1501 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
1502
1503 rr->rr_tsft =
1504 htole64(((uint64_t)htsfth << 32) | htsftl);
1505
1506 if ((hstat & RTW_RXSTAT_SPLCP) != 0)
1507 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE;
1508
1509 rr->rr_flags = 0;
1510 rr->rr_rate = rate;
1511 rr->rr_antsignal = rssi;
1512 rr->rr_barker_lock = htole16(sq);
1513
1514 bpf_ptap(sc->sc_radiobpf, m, rr, sizeof(sc->sc_rxtapu));
1515 }
1516
1517 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl);
1518 ieee80211_free_node(ni);
1519 next:
1520 rtw_rxdesc_init(sc, next, 0);
1521 sync = 1;
1522 }
1523
1524 if (sync) {
1525 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1526 BUS_DMASYNC_PREWRITE);
1527 }
1528
1529 rdb->rdb_next = next;
1530 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1531 #undef IS_BEACON
1532 }
1533
1534 static __inline void
1535 rtw_txsoft_release(bus_dma_tag_t dmat, struct rtw_txsoft *ts,
1536 int data_retry, int rts_retry, int error, int ratectl)
1537 {
1538 struct mbuf *m;
1539 struct ieee80211_node *ni;
1540
1541 if (!ts->ts_ratectl)
1542 ratectl = 0;
1543
1544 m = ts->ts_mbuf;
1545 ni = ts->ts_ni;
1546 KKASSERT(m != NULL);
1547 KKASSERT(ni != NULL);
1548 ts->ts_mbuf = NULL;
1549 ts->ts_ni = NULL;
1550
1551 if (ratectl) {
1552 struct ieee80211_ratectl_res rc_res;
1553
1554 rc_res.rc_res_rateidx = ts->ts_rateidx;
1555 rc_res.rc_res_tries = data_retry + rts_retry + 1;
1556
1557 ieee80211_ratectl_tx_complete(ni, m->m_pkthdr.len,
1558 &rc_res, 1,
1559 data_retry, rts_retry,
1560 error);
1561 }
1562
1563 bus_dmamap_sync(dmat, ts->ts_dmamap, BUS_DMASYNC_POSTWRITE);
1564 bus_dmamap_unload(dmat, ts->ts_dmamap);
1565 m_freem(m);
1566 ieee80211_free_node(ni);
1567 }
1568
1569 static __inline void
1570 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb,
1571 struct rtw_txsoft *ts, int ndesc)
1572 {
1573 uint32_t hstat;
1574 int data_retry, rts_retry, error;
1575 struct rtw_txdesc *tdn;
1576 const char *condstring;
1577 struct ifnet *ifp = &sc->sc_if;
1578
1579 tdb->tdb_nfree += ndesc;
1580
1581 tdn = &tdb->tdb_desc[ts->ts_last];
1582
1583 hstat = le32toh(tdn->td_stat);
1584 rts_retry = SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);
1585 data_retry = SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);
1586
1587 ifp->if_collisions += rts_retry + data_retry;
1588
1589 if ((hstat & RTW_TXSTAT_TOK) != 0) {
1590 condstring = "ok";
1591 error = 0;
1592 } else {
1593 ifp->if_oerrors++;
1594 condstring = "error";
1595 error = 1;
1596 }
1597
1598 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, data_retry, rts_retry,
1599 error, 1);
1600
1601 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
1602 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n",
1603 ifp->if_xname, ts, ts->ts_first, ts->ts_last,
1604 condstring, rts_retry, data_retry));
1605 }
1606
1607 static void
1608 rtw_reset_oactive(struct rtw_softc *sc)
1609 {
1610 int pri;
1611 #ifdef RTW_DEBUG
1612 short oflags = sc->sc_if.if_flags;
1613 #endif
1614
1615 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1616 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
1617 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1618
1619 if (!STAILQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0)
1620 sc->sc_if.if_flags &= ~IFF_OACTIVE;
1621 }
1622
1623 #ifdef RTW_DEBUG
1624 if (oflags != sc->sc_if.if_flags) {
1625 DPRINTF(sc, RTW_DEBUG_OACTIVE,
1626 ("%s: reset OACTIVE\n", sc->sc_ic.ic_if.if_xname));
1627 }
1628 #endif
1629 }
1630
1631 /* Collect transmitted packets. */
1632 static __inline void
1633 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb,
1634 struct rtw_txdesc_blk *tdb, int force)
1635 {
1636 struct rtw_txsoft *ts;
1637 int ndesc;
1638
1639 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1640 ndesc = 1 + ts->ts_last - ts->ts_first;
1641 if (ts->ts_last < ts->ts_first)
1642 ndesc += tdb->tdb_ndesc;
1643
1644 KKASSERT(ndesc > 0);
1645
1646 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1647 BUS_DMASYNC_POSTREAD);
1648
1649 if (force) {
1650 int i;
1651
1652 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) {
1653 tdb->tdb_desc[i].td_stat &=
1654 ~htole32(RTW_TXSTAT_OWN);
1655 if (i == ts->ts_last)
1656 break;
1657 }
1658 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1659 BUS_DMASYNC_PREWRITE);
1660 } else if ((tdb->tdb_desc[ts->ts_last].td_stat &
1661 htole32(RTW_TXSTAT_OWN)) != 0) {
1662 break;
1663 }
1664
1665 rtw_collect_txpkt(sc, tdb, ts, ndesc);
1666 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1667 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1668 }
1669 /* no more pending transmissions, cancel watchdog */
1670 if (ts == NULL)
1671 tsb->tsb_tx_timer = 0;
1672 rtw_reset_oactive(sc);
1673 }
1674
1675 static void
1676 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr)
1677 {
1678 int pri;
1679
1680 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1681 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1682 &sc->sc_txdesc_blk[pri], 0);
1683 }
1684 if (isr)
1685 rtw_start(&sc->sc_ic.ic_if);
1686 }
1687
1688 static __inline struct mbuf *
1689 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni)
1690 {
1691 struct ieee80211com *ic = &sc->sc_ic;
1692 struct ieee80211_beacon_offsets boff;
1693 struct mbuf *m;
1694
1695 m = ieee80211_beacon_alloc(ic, ni, &boff);
1696 if (m != NULL) {
1697 RTW_DPRINTF(RTW_DEBUG_BEACON,
1698 ("%s: m %p len %u\n", ic->ic_if.if_xname, m,
1699 m->m_len));
1700 }
1701 return m;
1702 }
1703
1704 static void
1705 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr)
1706 {
1707 struct ieee80211com *ic = &sc->sc_ic;
1708 struct rtw_regs *regs = &sc->sc_regs;
1709 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN];
1710 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN];
1711
1712 #ifdef RTW_DEBUG
1713 uint32_t tsfth, tsftl;
1714
1715 tsfth = RTW_READ(regs, RTW_TSFTRH);
1716 tsftl = RTW_READ(regs, RTW_TSFTRL);
1717 #endif
1718
1719 if (isr & (RTW_INTR_TBDOK | RTW_INTR_TBDER)) {
1720 #ifdef RTW_DEBUG
1721 int next = rtw_txring_next(regs, tdb);
1722 #endif
1723
1724 RTW_DPRINTF(RTW_DEBUG_BEACON,
1725 ("%s: beacon ring %sprocessed, "
1726 "isr = %#04x, next %d expected %d, %llu\n",
1727 ic->ic_if.if_xname,
1728 (next == tdb->tdb_next) ? "" : "un",
1729 isr, next, tdb->tdb_next,
1730 (uint64_t)tsfth << 32 | tsftl));
1731
1732 if ((RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){
1733 rtw_collect_txring(sc, tsb, tdb, 1);
1734 tdb->tdb_next = 0;
1735 }
1736 }
1737 /* Start beacon transmission. */
1738
1739 if ((isr & RTW_INTR_BCNINT) && ic->ic_state == IEEE80211_S_RUN &&
1740 STAILQ_EMPTY(&tsb->tsb_dirtyq)) {
1741 struct mbuf *m;
1742
1743 RTW_DPRINTF(RTW_DEBUG_BEACON,
1744 ("%s: beacon prep. time, isr = %#04x, %llu\n",
1745 ic->ic_if.if_xname, isr,
1746 (uint64_t)tsfth << 32 | tsftl));
1747
1748 m = rtw_beacon_alloc(sc, ic->ic_bss);
1749 if (m == NULL) {
1750 if_printf(&ic->ic_if, "could not allocate beacon\n");
1751 return;
1752 }
1753
1754 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss);
1755
1756 IF_ENQUEUE(&sc->sc_beaconq, m);
1757
1758 rtw_start(&ic->ic_if);
1759 }
1760 }
1761
1762 static void
1763 rtw_intr_atim(struct rtw_softc *sc)
1764 {
1765 /* TBD */
1766 return;
1767 }
1768
1769 #ifdef RTW_DEBUG
1770 static void
1771 rtw_dump_rings(struct rtw_softc *sc)
1772 {
1773 struct rtw_rxdesc_blk *rdb;
1774 int desc, pri;
1775
1776 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0)
1777 return;
1778
1779 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1780 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1781
1782 if_printf(&sc->sc_ic.ic_if, "txpri %d ndesc %d nfree %d\n",
1783 pri, tdb->tdb_ndesc, tdb->tdb_nfree);
1784 for (desc = 0; desc < tdb->tdb_ndesc; desc++)
1785 rtw_print_txdesc(sc, ".", NULL, tdb, desc);
1786 }
1787
1788 rdb = &sc->sc_rxdesc_blk;
1789
1790 for (desc = 0; desc < RTW_RXQLEN; desc++) {
1791 struct rtw_rxdesc *rd = &rdb->rdb_desc[desc];
1792
1793 if_printf(&sc->sc_ic.ic_if,
1794 "%sctl %08x rsvd0/rssi %08x buf/tsftl %08x "
1795 "rsvd1/tsfth %08x\n",
1796 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "",
1797 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi),
1798 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth));
1799 }
1800 }
1801 #endif /* RTW_DEBUG */
1802
1803 static void
1804 rtw_hwring_setup(struct rtw_softc *sc)
1805 {
1806 struct rtw_regs *regs = &sc->sc_regs;
1807 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1808 int pri;
1809
1810 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1811 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1812
1813 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
1814 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC,
1815 ("%s: reg[tdb->tdb_basereg] <- %u\n",
1816 sc->sc_ic.ic_if.if_xname, tdb->tdb_base));
1817 }
1818
1819 RTW_WRITE(regs, RTW_RDSAR, rdb->rdb_base);
1820 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1821 ("%s: reg[RDSAR] <- %u\n", sc->sc_ic.ic_if.if_xname,
1822 rdb->rdb_base));
1823
1824 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
1825 }
1826
1827 static int
1828 rtw_swring_setup(struct rtw_softc *sc)
1829 {
1830 int rc;
1831
1832 rtw_txdesc_blk_init_all(sc);
1833 rtw_txsoft_blk_init_all(sc);
1834
1835 rc = rtw_rxsoft_blk_init_all(sc);
1836 if (rc) {
1837 if_printf(&sc->sc_ic.ic_if, "could not allocate rx buffers\n");
1838 return rc;
1839 }
1840
1841 rtw_rxdesc_blk_init_all(sc);
1842 sc->sc_rxdesc_blk.rdb_next = 0;
1843 return 0;
1844 }
1845
1846 static int
1847 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
1848 {
1849 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
1850 sizeof(struct rtw_txdesc);
1851 }
1852
1853 static void
1854 rtw_txring_fixup(struct rtw_softc *sc)
1855 {
1856 struct rtw_regs *regs = &sc->sc_regs;
1857 int pri;
1858
1859 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1860 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1861 int next;
1862
1863 next = rtw_txring_next(regs, tdb);
1864 if (tdb->tdb_next == next)
1865 continue;
1866 if_printf(&sc->sc_ic.ic_if,
1867 "tx-ring %d expected next %d, read %d\n",
1868 pri, tdb->tdb_next, next);
1869 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1);
1870 }
1871 }
1872
1873 static void
1874 rtw_rxring_fixup(struct rtw_softc *sc)
1875 {
1876 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1877 uint32_t rdsar;
1878 int next;
1879
1880 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR));
1881 next = (rdsar - rdb->rdb_base) / sizeof(struct rtw_rxdesc);
1882
1883 if (rdb->rdb_next != next) {
1884 if_printf(&sc->sc_ic.ic_if,
1885 "rx-ring expected next %d, read %d\n",
1886 rdb->rdb_next, next);
1887 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1);
1888 }
1889 }
1890
1891 static void
1892 rtw_txdesc_blk_reset_all(struct rtw_softc *sc)
1893 {
1894 int pri;
1895
1896 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1897 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1898 &sc->sc_txdesc_blk[pri], 1);
1899 }
1900 }
1901
1902 static void
1903 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr)
1904 {
1905 struct rtw_regs *regs = &sc->sc_regs;
1906 int xmtr = 0, rcvr = 0;
1907 uint8_t cr = 0;
1908
1909 if (isr & RTW_INTR_TXFOVW) {
1910 if_printf(&sc->sc_ic.ic_if, "tx fifo underflow\n");
1911 rcvr = xmtr = 1;
1912 cr |= RTW_CR_TE | RTW_CR_RE;
1913 }
1914
1915 if (isr & (RTW_INTR_RDU | RTW_INTR_RXFOVW)) {
1916 cr |= RTW_CR_RE;
1917 rcvr = 1;
1918 }
1919
1920 RTW_DPRINTF(RTW_DEBUG_BUGS,
1921 ("%s: restarting xmit/recv, isr %04x\n",
1922 sc->sc_ic.ic_if.if_xname, isr));
1923
1924 #ifdef RTW_DEBUG
1925 rtw_dump_rings(sc);
1926 #endif /* RTW_DEBUG */
1927
1928 rtw_io_enable(sc, cr, 0);
1929
1930 /* Collect rx'd packets. Refresh rx buffers. */
1931 if (rcvr)
1932 rtw_intr_rx(sc, 0);
1933
1934 /*
1935 * Collect tx'd packets.
1936 * XXX let's hope this stops the transmit timeouts.
1937 */
1938 if (xmtr)
1939 rtw_txdesc_blk_reset_all(sc);
1940
1941 RTW_WRITE16(regs, RTW_IMR, 0);
1942 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1943
1944 if (rtw_do_chip_reset) {
1945 rtw_chip_reset1(sc);
1946 rtw_wep_setkeys(sc);
1947 }
1948
1949 rtw_rxdesc_blk_init_all(sc);
1950
1951 #ifdef RTW_DEBUG
1952 rtw_dump_rings(sc);
1953 #endif /* RTW_DEBUG */
1954
1955 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
1956 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1957
1958 if (rcvr)
1959 rtw_rxring_fixup(sc);
1960
1961 rtw_io_enable(sc, cr, 1);
1962
1963 if (xmtr)
1964 rtw_txring_fixup(sc);
1965 }
1966
1967 static __inline void
1968 rtw_suspend_ticks(struct rtw_softc *sc)
1969 {
1970 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1971 ("%s: suspending ticks\n", sc->sc_ic.ic_if.if_xname));
1972 sc->sc_do_tick = 0;
1973 }
1974
1975 static void
1976 rtw_resume_ticks(struct rtw_softc *sc)
1977 {
1978 uint32_t tsftrl0, tsftrl1, next_tick;
1979 struct rtw_regs *regs = &sc->sc_regs;
1980
1981 tsftrl0 = RTW_READ(regs, RTW_TSFTRL);
1982
1983 tsftrl1 = RTW_READ(regs, RTW_TSFTRL);
1984 next_tick = tsftrl1 + 1000000;
1985 RTW_WRITE(regs, RTW_TINT, next_tick);
1986
1987 sc->sc_do_tick = 1;
1988
1989 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1990 ("%s: resume ticks delta %#08x now %#08x next %#08x\n",
1991 sc->sc_ic.ic_if.if_xname, tsftrl1 - tsftrl0, tsftrl1,
1992 next_tick));
1993 }
1994
1995 static void
1996 rtw_intr_timeout(struct rtw_softc *sc)
1997 {
1998 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1999 ("%s: timeout\n", sc->sc_ic.ic_if.if_xname));
2000 if (sc->sc_do_tick)
2001 rtw_resume_ticks(sc);
2002 }
2003
2004 static void
2005 rtw_intr(void *arg)
2006 {
2007 struct rtw_softc *sc = arg;
2008 struct rtw_regs *regs = &sc->sc_regs;
2009 struct ifnet *ifp = &sc->sc_if;
2010 int i;
2011
2012 /*
2013 * If the interface isn't running, the interrupt couldn't
2014 * possibly have come from us.
2015 */
2016 if ((sc->sc_flags & RTW_F_ENABLED) == 0 ||
2017 (ifp->if_flags & IFF_RUNNING) == 0) {
2018 RTW_DPRINTF(RTW_DEBUG_INTR,
2019 ("%s: stray interrupt\n", ifp->if_xname));
2020 return;
2021 }
2022
2023 for (i = 0; i < 10; i++) {
2024 uint16_t isr;
2025
2026 isr = RTW_READ16(regs, RTW_ISR);
2027
2028 RTW_WRITE16(regs, RTW_ISR, isr);
2029 RTW_WBR(regs, RTW_ISR, RTW_ISR);
2030
2031 if (sc->sc_intr_ack != NULL)
2032 sc->sc_intr_ack(regs);
2033
2034 if (isr == 0)
2035 break;
2036
2037 #ifdef RTW_DEBUG
2038 #define PRINTINTR(flag) do { \
2039 if ((isr & flag) != 0) { \
2040 kprintf("%s" #flag, delim); \
2041 delim = ","; \
2042 } \
2043 } while (0)
2044
2045 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) {
2046 const char *delim = "<";
2047
2048 if_printf(ifp, "reg[ISR] = %x", isr);
2049
2050 PRINTINTR(RTW_INTR_TXFOVW);
2051 PRINTINTR(RTW_INTR_TIMEOUT);
2052 PRINTINTR(RTW_INTR_BCNINT);
2053 PRINTINTR(RTW_INTR_ATIMINT);
2054 PRINTINTR(RTW_INTR_TBDER);
2055 PRINTINTR(RTW_INTR_TBDOK);
2056 PRINTINTR(RTW_INTR_THPDER);
2057 PRINTINTR(RTW_INTR_THPDOK);
2058 PRINTINTR(RTW_INTR_TNPDER);
2059 PRINTINTR(RTW_INTR_TNPDOK);
2060 PRINTINTR(RTW_INTR_RXFOVW);
2061 PRINTINTR(RTW_INTR_RDU);
2062 PRINTINTR(RTW_INTR_TLPDER);
2063 PRINTINTR(RTW_INTR_TLPDOK);
2064 PRINTINTR(RTW_INTR_RER);
2065 PRINTINTR(RTW_INTR_ROK);
2066
2067 kprintf(">\n");
2068 }
2069 #undef PRINTINTR
2070 #endif /* RTW_DEBUG */
2071
2072 if (isr & RTW_INTR_RX)
2073 rtw_intr_rx(sc, isr & RTW_INTR_RX);
2074 if (isr & RTW_INTR_TX)
2075 rtw_intr_tx(sc, isr & RTW_INTR_TX);
2076 if (isr & RTW_INTR_BEACON)
2077 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON);
2078 if (isr & RTW_INTR_ATIMINT)
2079 rtw_intr_atim(sc);
2080 if (isr & RTW_INTR_IOERROR)
2081 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR);
2082 if (isr & RTW_INTR_TIMEOUT)
2083 rtw_intr_timeout(sc);
2084 }
2085 }
2086
2087 /* Must be called at splnet. */
2088 void
2089 rtw_stop(struct rtw_softc *sc, int disable)
2090 {
2091 struct ieee80211com *ic = &sc->sc_ic;
2092 struct ifnet *ifp = &ic->ic_if;
2093 struct rtw_regs *regs = &sc->sc_regs;
2094 int i;
2095
2096 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2097 return;
2098
2099 rtw_suspend_ticks(sc);
2100
2101 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2102
2103 if ((sc->sc_flags & RTW_F_INVALID) == 0) {
2104 /* Disable interrupts. */
2105 RTW_WRITE16(regs, RTW_IMR, 0);
2106
2107 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
2108
2109 /*
2110 * Stop the transmit and receive processes. First stop DMA,
2111 * then disable receiver and transmitter.
2112 */
2113 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2114
2115 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
2116
2117 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2118 }
2119
2120 /* Free pending TX mbufs */
2121 for (i = 0; i < RTW_NTXPRI; ++i) {
2122 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[i];
2123 struct rtw_txsoft *ts;
2124
2125 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
2126 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, 0, 0, 0, 0);
2127 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
2128 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
2129 }
2130 tsb->tsb_tx_timer = 0;
2131 }
2132
2133 /* Free pending RX mbufs */
2134 for (i = 0; i < RTW_RXQLEN; i++) {
2135 struct rtw_rxsoft *rs = &sc->sc_rxsoft[i];
2136
2137 if (rs->rs_mbuf != NULL) {
2138 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
2139 BUS_DMASYNC_POSTREAD);
2140 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
2141 m_freem(rs->rs_mbuf);
2142 rs->rs_mbuf = NULL;
2143 }
2144 }
2145
2146 if (disable)
2147 rtw_disable(sc);
2148
2149 /* Mark the interface as not running. Cancel the watchdog timer. */
2150 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2151 ifp->if_timer = 0;
2152 }
2153
2154 #ifdef RTW_DEBUG
2155 const char *
2156 rtw_pwrstate_string(enum rtw_pwrstate power)
2157 {
2158 switch (power) {
2159 case RTW_ON:
2160 return "on";
2161 case RTW_SLEEP:
2162 return "sleep";
2163 case RTW_OFF:
2164 return "off";
2165 default:
2166 return "unknown";
2167 }
2168 }
2169 #endif /* RTW_DEBUG */
2170
2171 /*
2172 * XXX For Maxim, I am using the RFMD settings gleaned from the
2173 * reference driver, plus a magic Maxim "ON" value that comes from
2174 * the Realtek document "Windows PG for Rtl8180."
2175 */
2176 static void
2177 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2178 int before_rf, int digphy)
2179 {
2180 uint32_t anaparm;
2181
2182 anaparm = RTW_READ(regs, RTW_ANAPARM);
2183 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2184
2185 switch (power) {
2186 case RTW_OFF:
2187 if (before_rf)
2188 return;
2189 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF;
2190 anaparm |= RTW_ANAPARM_TXDACOFF;
2191 break;
2192 case RTW_SLEEP:
2193 if (!before_rf)
2194 return;
2195 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP;
2196 anaparm |= RTW_ANAPARM_TXDACOFF;
2197 break;
2198 case RTW_ON:
2199 if (!before_rf)
2200 return;
2201 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON;
2202 break;
2203 }
2204 RTW_DPRINTF(RTW_DEBUG_PWR,
2205 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2206 __func__, rtw_pwrstate_string(power),
2207 (before_rf) ? "before" : "after", anaparm));
2208
2209 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2210 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2211 }
2212
2213 /* XXX I am using the RFMD settings gleaned from the reference
2214 * driver. They agree
2215 */
2216 static void
2217 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2218 int before_rf, int digphy)
2219 {
2220 uint32_t anaparm;
2221
2222 anaparm = RTW_READ(regs, RTW_ANAPARM);
2223 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2224
2225 switch (power) {
2226 case RTW_OFF:
2227 if (before_rf)
2228 return;
2229 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF;
2230 anaparm |= RTW_ANAPARM_TXDACOFF;
2231 break;
2232 case RTW_SLEEP:
2233 if (!before_rf)
2234 return;
2235 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP;
2236 anaparm |= RTW_ANAPARM_TXDACOFF;
2237 break;
2238 case RTW_ON:
2239 if (!before_rf)
2240 return;
2241 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON;
2242 break;
2243 }
2244 RTW_DPRINTF(RTW_DEBUG_PWR,
2245 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2246 __func__, rtw_pwrstate_string(power),
2247 (before_rf) ? "before" : "after", anaparm));
2248
2249 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2250 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2251 }
2252
2253 static void
2254 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2255 int before_rf, int digphy)
2256 {
2257 uint32_t anaparm;
2258
2259 anaparm = RTW_READ(regs, RTW_ANAPARM);
2260 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2261
2262 switch (power) {
2263 case RTW_OFF:
2264 if (before_rf)
2265 return;
2266 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF;
2267 anaparm |= RTW_ANAPARM_TXDACOFF;
2268 break;
2269 case RTW_SLEEP:
2270 if (!before_rf)
2271 return;
2272 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP;
2273 anaparm |= RTW_ANAPARM_TXDACOFF;
2274 break;
2275 case RTW_ON:
2276 if (!before_rf)
2277 return;
2278 if (digphy) {
2279 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON;
2280 /* XXX guess */
2281 anaparm |= RTW_ANAPARM_TXDACOFF;
2282 } else
2283 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON;
2284 break;
2285 }
2286 RTW_DPRINTF(RTW_DEBUG_PWR,
2287 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2288 __func__, rtw_pwrstate_string(power),
2289 (before_rf) ? "before" : "after", anaparm));
2290
2291 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2292 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2293 }
2294
2295 static __inline void
2296 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf,
2297 int digphy)
2298 {
2299 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2300 sc->sc_pwrstate_cb(&sc->sc_regs, power, before_rf, digphy);
2301 rtw_set_access(sc, RTW_ACCESS_NONE);
2302 }
2303
2304 static int
2305 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power)
2306 {
2307 int rc;
2308
2309 RTW_DPRINTF(RTW_DEBUG_PWR,
2310 ("%s: %s->%s\n", sc->sc_ic.ic_if.if_xname,
2311 rtw_pwrstate_string(sc->sc_pwrstate),
2312 rtw_pwrstate_string(power)));
2313
2314 if (sc->sc_pwrstate == power)
2315 return 0;
2316
2317 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY);
2318 rc = rtw_rf_pwrstate(sc->sc_rf, power);
2319 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY);
2320
2321 switch (power) {
2322 case RTW_ON:
2323 /* TBD set LEDs */
2324 break;
2325 case RTW_SLEEP:
2326 /* TBD */
2327 break;
2328 case RTW_OFF:
2329 /* TBD */
2330 break;
2331 }
2332 if (rc == 0)
2333 sc->sc_pwrstate = power;
2334 else
2335 sc->sc_pwrstate = RTW_OFF;
2336 return rc;
2337 }
2338
2339 static int
2340 rtw_tune(struct rtw_softc *sc)
2341 {
2342 struct ieee80211com *ic = &sc->sc_ic;
2343 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
2344 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
2345 u_int chan;
2346 int rc, antdiv, dflantb;
2347
2348 antdiv = sc->sc_flags & RTW_F_ANTDIV;
2349 dflantb = sc->sc_flags & RTW_F_DFLANTB;
2350
2351 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2352 if (chan == IEEE80211_CHAN_ANY)
2353 panic("%s: chan == IEEE80211_CHAN_ANY\n", ic->ic_if.if_xname);
2354
2355 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2356 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2357
2358 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2359 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2360
2361 if (chan == sc->sc_cur_chan) {
2362 RTW_DPRINTF(RTW_DEBUG_TUNE,
2363 ("%s: already tuned chan #%d\n",
2364 ic->ic_if.if_xname, chan));
2365 return 0;
2366 }
2367
2368 rtw_suspend_ticks(sc);
2369
2370 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2371
2372 /* TBD wait for Tx to complete */
2373
2374 KKASSERT((sc->sc_flags & RTW_F_ENABLED) != 0);
2375
2376 rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf,
2377 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan),
2378 sc->sc_csthr, ic->ic_curchan->ic_freq, antdiv,
2379 dflantb, RTW_ON);
2380 if (rc != 0) {
2381 /* XXX condition on powersaving */
2382 kprintf("%s: phy init failed\n", ic->ic_if.if_xname);
2383 }
2384
2385 sc->sc_cur_chan = chan;
2386
2387 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2388
2389 rtw_resume_ticks(sc);
2390
2391 return rc;
2392 }
2393
2394 static void
2395 rtw_disable(struct rtw_softc *sc)
2396 {
2397 int rc;
2398
2399 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2400 return;
2401
2402 /* turn off PHY */
2403 if ((sc->sc_flags & RTW_F_INVALID) == 0 &&
2404 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0)
2405 if_printf(&sc->sc_ic.ic_if, "failed to turn off PHY\n");
2406
2407 sc->sc_flags &= ~RTW_F_ENABLED;
2408 }
2409
2410 static int
2411 rtw_enable(struct rtw_softc *sc)
2412 {
2413 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
2414 sc->sc_flags |= RTW_F_ENABLED;
2415 /*
2416 * Power may have been removed, and WEP keys thus reset.
2417 */
2418 sc->sc_flags &= ~RTW_F_DK_VALID;
2419 }
2420 return (0);
2421 }
2422
2423 static void
2424 rtw_transmit_config(struct rtw_regs *regs)
2425 {
2426 uint32_t tcr;
2427
2428 tcr = RTW_READ(regs, RTW_TCR);
2429
2430 tcr |= RTW_TCR_CWMIN;
2431 tcr &= ~RTW_TCR_MXDMA_MASK;
2432 tcr |= RTW_TCR_MXDMA_256;
2433 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */
2434 tcr &= ~RTW_TCR_LBK_MASK;
2435 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */
2436
2437 /* set short/long retry limits */
2438 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK);
2439 tcr |= SHIFTIN(4, RTW_TCR_SRL_MASK) | SHIFTIN(4, RTW_TCR_LRL_MASK);
2440
2441 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */
2442
2443 RTW_WRITE(regs, RTW_TCR, tcr);
2444 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
2445 }
2446
2447 static void
2448 rtw_enable_interrupts(struct rtw_softc *sc)
2449 {
2450 struct rtw_regs *regs = &sc->sc_regs;
2451
2452 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT;
2453 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT;
2454
2455 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
2456 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2457 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2458 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2459
2460 /* XXX necessary? */
2461 if (sc->sc_intr_ack != NULL)
2462 sc->sc_intr_ack(regs);
2463 }
2464
2465 static void
2466 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode)
2467 {
2468 struct rtw_regs *regs = &sc->sc_regs;
2469 uint8_t msr;
2470
2471 /* I'm guessing that MSR is protected as CONFIG[0123] are. */
2472 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2473
2474 msr = RTW_READ8(regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK;
2475
2476 switch (opmode) {
2477 case IEEE80211_M_AHDEMO:
2478 case IEEE80211_M_IBSS:
2479 msr |= RTW_MSR_NETYPE_ADHOC_OK;
2480 break;
2481 case IEEE80211_M_HOSTAP:
2482 msr |= RTW_MSR_NETYPE_AP_OK;
2483 break;
2484 case IEEE80211_M_MONITOR:
2485 /* XXX */
2486 msr |= RTW_MSR_NETYPE_NOLINK;
2487 break;
2488 case IEEE80211_M_STA:
2489 msr |= RTW_MSR_NETYPE_INFRA_OK;
2490 break;
2491 }
2492 RTW_WRITE8(regs, RTW_MSR, msr);
2493
2494 rtw_set_access(sc, RTW_ACCESS_NONE);
2495 }
2496
2497 #define rtw_calchash(addr) \
2498 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26)
2499
2500 static void
2501 rtw_pktfilt_load(struct rtw_softc *sc)
2502 {
2503 struct rtw_regs *regs = &sc->sc_regs;
2504 struct ieee80211com *ic = &sc->sc_ic;
2505 struct ifnet *ifp = &ic->ic_if;
2506 struct ifmultiaddr *ifma;
2507 uint32_t hashes[2] = { 0, 0 };
2508 int hash;
2509
2510 /* XXX might be necessary to stop Rx/Tx engines while setting filters */
2511
2512 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK;
2513 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK);
2514
2515 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT;
2516 /* MAC auto-reset PHY (huh?) */
2517 sc->sc_rcr |= RTW_RCR_ENMARP;
2518 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */
2519 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE;
2520
2521 switch (ic->ic_opmode) {
2522 case IEEE80211_M_MONITOR:
2523 sc->sc_rcr |= RTW_RCR_MONITOR;
2524 break;
2525 case IEEE80211_M_AHDEMO:
2526 case IEEE80211_M_IBSS:
2527 /* receive broadcasts in our BSS */
2528 sc->sc_rcr |= RTW_RCR_ADD3;
2529 break;
2530 default:
2531 break;
2532 }
2533
2534 ifp->if_flags &= ~IFF_ALLMULTI;
2535
2536 /* XXX accept all broadcast if scanning */
2537 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2538 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2539
2540 if (ifp->if_flags & IFF_PROMISC) {
2541 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2542 allmulti:
2543 ifp->if_flags |= IFF_ALLMULTI;
2544 goto setit;
2545 }
2546
2547 /*
2548 * Program the 64-bit multicast hash filter.
2549 */
2550 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2551 if (ifma->ifma_addr->sa_family != AF_LINK)
2552 continue;
2553
2554 hash = rtw_calchash(
2555 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
2556 hashes[hash >> 5] |= (1 << (hash & 0x1f));
2557 sc->sc_rcr |= RTW_RCR_AM;
2558 }
2559
2560 /* all bits set => hash is useless */
2561 if (~(hashes[0] & hashes[1]) == 0)
2562 goto allmulti;
2563
2564 setit:
2565 if (ifp->if_flags & IFF_ALLMULTI) {
2566 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */
2567 hashes[0] = hashes[1] = 0xffffffff;
2568 }
2569
2570 RTW_WRITE(regs, RTW_MAR0, hashes[0]);
2571 RTW_WRITE(regs, RTW_MAR1, hashes[1]);
2572 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
2573 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
2574
2575 DPRINTF(sc, RTW_DEBUG_PKTFILT,
2576 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n",
2577 ifp->if_xname, RTW_READ(regs, RTW_MAR0),
2578 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
2579 }
2580
2581 /* Must be called at splnet. */
2582 static void
2583 rtw_init(void *xsc)
2584 {
2585 struct rtw_softc *sc = xsc;
2586 struct ieee80211com *ic = &sc->sc_ic;
2587 struct ifnet *ifp = &ic->ic_if;
2588 struct rtw_regs *regs = &sc->sc_regs;
2589 int rc = 0;
2590
2591 rc = rtw_enable(sc);
2592 if (rc)
2593 goto out;
2594
2595 /* Cancel pending I/O and reset. */
2596 rtw_stop(sc, 0);
2597
2598 DPRINTF(sc, RTW_DEBUG_TUNE,
2599 ("%s: channel %d freq %d flags 0x%04x\n", ifp->if_xname,
2600 ieee80211_chan2ieee(ic, ic->ic_curchan),
2601 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
2602
2603 rc = rtw_pwrstate(sc, RTW_OFF);
2604 if (rc)
2605 goto out;
2606
2607 rc = rtw_swring_setup(sc);
2608 if (rc)
2609 goto out;
2610
2611 rtw_transmit_config(regs);
2612
2613 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2614
2615 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
2616 RTW_WBW(regs, RTW_MSR, RTW_BRSR);
2617
2618 /* long PLCP header, 1Mb/2Mb basic rate */
2619 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS);
2620 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
2621
2622 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2623 rtw_set_access(sc, RTW_ACCESS_NONE);
2624
2625 /* XXX from reference sources */
2626 RTW_WRITE(regs, RTW_FEMR, 0xffff);
2627 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
2628
2629 rtw_set_rfprog(sc);
2630
2631 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
2632 /* from Linux driver */
2633 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
2634
2635 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
2636
2637 rtw_enable_interrupts(sc);
2638
2639 rtw_pktfilt_load(sc);
2640
2641 rtw_hwring_setup(sc);
2642
2643 rtw_wep_setkeys(sc);
2644
2645 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2646
2647 ifp->if_flags |= IFF_RUNNING;
2648 ic->ic_state = IEEE80211_S_INIT;
2649
2650 RTW_WRITE16(regs, RTW_BSSID16, 0x0);
2651 RTW_WRITE(regs, RTW_BSSID32, 0x0);
2652
2653 rtw_resume_ticks(sc);
2654
2655 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
2656
2657 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2658 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2659 else
2660 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2661
2662 out:
2663 if (rc)
2664 if_printf(ifp, "interface not running\n");
2665 }
2666
2667 static void
2668 rtw_led_init(struct rtw_softc *sc)
2669 {
2670 struct rtw_regs *regs = &sc->sc_regs;
2671 uint8_t cfg0, cfg1;
2672
2673 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2674
2675 cfg0 = RTW_READ8(regs, RTW_CONFIG0);
2676 cfg0 |= RTW_CONFIG0_LEDGPOEN;
2677 RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
2678
2679 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2680 RTW_DPRINTF(RTW_DEBUG_LED,
2681 ("%s: read %02x from reg[CONFIG1]\n",
2682 sc->sc_ic.ic_if.if_xname, cfg1));
2683
2684 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2685 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2686 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
2687
2688 rtw_set_access(sc, RTW_ACCESS_NONE);
2689 }
2690
2691 /*
2692 * IEEE80211_S_INIT: LED1 off
2693 *
2694 * IEEE80211_S_AUTH,
2695 * IEEE80211_S_ASSOC,
2696 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx
2697 *
2698 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx
2699 */
2700 static void
2701 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate)
2702 {
2703 struct rtw_led_state *ls = &sc->sc_led_state;
2704
2705 switch (nstate) {
2706 case IEEE80211_S_INIT:
2707 rtw_led_init(sc);
2708 callout_stop(&ls->ls_slow_ch);
2709 callout_stop(&ls->ls_fast_ch);
2710 ls->ls_slowblink = 0;
2711 ls->ls_actblink = 0;
2712 ls->ls_default = 0;
2713 break;
2714 case IEEE80211_S_SCAN:
2715 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2716 rtw_led_slowblink, sc);
2717 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2718 rtw_led_fastblink, sc);
2719 /*FALLTHROUGH*/
2720 case IEEE80211_S_AUTH:
2721 case IEEE80211_S_ASSOC:
2722 ls->ls_default = RTW_LED1;
2723 ls->ls_actblink = RTW_LED1;
2724 ls->ls_slowblink = RTW_LED1;
2725 break;
2726 case IEEE80211_S_RUN:
2727 ls->ls_slowblink = 0;
2728 break;
2729 }
2730 rtw_led_set(sc);
2731 }
2732
2733 static void
2734 rtw_led_set(struct rtw_softc *sc)
2735 {
2736 struct rtw_led_state *ls = &sc->sc_led_state;
2737 struct rtw_regs *regs = &sc->sc_regs;
2738 uint8_t led_condition, mask, newval, val;
2739 bus_size_t ofs;
2740
2741 led_condition = ls->ls_default;
2742
2743 if (ls->ls_state & RTW_LED_S_SLOW)
2744 led_condition ^= ls->ls_slowblink;
2745 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX))
2746 led_condition ^= ls->ls_actblink;
2747
2748 RTW_DPRINTF(RTW_DEBUG_LED,
2749 ("%s: LED condition %02x\n", sc->sc_ic.ic_if.if_xname,
2750 led_condition));
2751
2752 switch (sc->sc_hwverid) {
2753 default:
2754 case 'F':
2755 ofs = RTW_PSR;
2756 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;
2757 if (led_condition & RTW_LED0)
2758 newval &= ~RTW_PSR_LEDGPO0;
2759 if (led_condition & RTW_LED1)
2760 newval &= ~RTW_PSR_LEDGPO1;
2761 break;
2762 case 'D':
2763 ofs = RTW_9346CR;
2764 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;
2765 newval = RTW_9346CR_EEM_PROGRAM;
2766 if (led_condition & RTW_LED0)
2767 newval |= RTW_9346CR_EEDI;
2768 if (led_condition & RTW_LED1)
2769 newval |= RTW_9346CR_EECS;
2770 break;
2771 }
2772 val = RTW_READ8(regs, ofs);
2773 RTW_DPRINTF(RTW_DEBUG_LED,
2774 ("%s: read %02x from reg[%02x]\n",
2775 sc->sc_ic.ic_if.if_xname, val, ofs));
2776 val &= ~mask;
2777 val |= newval;
2778 RTW_WRITE8(regs, ofs, val);
2779 RTW_DPRINTF(RTW_DEBUG_LED,
2780 ("%s: wrote %02x to reg[%02x]\n",
2781 sc->sc_ic.ic_if.if_xname, val, ofs));
2782 RTW_SYNC(regs, ofs, ofs);
2783 }
2784
2785 static void
2786 rtw_led_fastblink(void *arg)
2787 {
2788 struct rtw_softc *sc = arg;
2789 struct ifnet *ifp = &sc->sc_ic.ic_if;
2790 struct rtw_led_state *ls = &sc->sc_led_state;
2791 int ostate;
2792
2793 lwkt_serialize_enter(ifp->if_serializer);
2794
2795 ostate = ls->ls_state;
2796 ls->ls_state ^= ls->ls_event;
2797
2798 if ((ls->ls_event & RTW_LED_S_TX) == 0)
2799 ls->ls_state &= ~RTW_LED_S_TX;
2800
2801 if ((ls->ls_event & RTW_LED_S_RX) == 0)
2802 ls->ls_state &= ~RTW_LED_S_RX;
2803
2804 ls->ls_event = 0;
2805
2806 if (ostate != ls->ls_state)
2807 rtw_led_set(sc);
2808
2809 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2810 rtw_led_fastblink, sc);
2811
2812 lwkt_serialize_exit(ifp->if_serializer);
2813 }
2814
2815 static void
2816 rtw_led_slowblink(void *arg)
2817 {
2818 struct rtw_softc *sc = arg;
2819 struct ifnet *ifp = &sc->sc_ic.ic_if;
2820 struct rtw_led_state *ls = &sc->sc_led_state;
2821
2822 lwkt_serialize_enter(ifp->if_serializer);
2823
2824 ls->ls_state ^= RTW_LED_S_SLOW;
2825 rtw_led_set(sc);
2826 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2827 rtw_led_slowblink, sc);
2828
2829 lwkt_serialize_exit(ifp->if_serializer);
2830 }
2831
2832 static int
2833 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2834 {
2835 struct rtw_softc *sc = ifp->if_softc;
2836 int rc = 0;
2837
2838 switch (cmd) {
2839 case SIOCSIFFLAGS:
2840 if (ifp->if_flags & IFF_UP) {
2841 if ((ifp->if_flags & IFF_RUNNING) == 0)
2842 rtw_init(sc);
2843 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2844 } else if (sc->sc_flags & RTW_F_ENABLED) {
2845 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2846 rtw_stop(sc, 1);
2847 }
2848 break;
2849 case SIOCADDMULTI:
2850 case SIOCDELMULTI:
2851 if (ifp->if_flags & IFF_RUNNING)
2852 rtw_pktfilt_load(sc);
2853 break;
2854 default:
2855 rc = ieee80211_ioctl(&sc->sc_ic, cmd, data, cr);
2856 if (rc == ENETRESET) {
2857 if (sc->sc_flags & RTW_F_ENABLED)
2858 rtw_init(sc);
2859 rc = 0;
2860 }
2861 break;
2862 }
2863 return rc;
2864 }
2865
2866 /*
2867 * Select a transmit ring with at least one h/w and s/w descriptor free.
2868 * Return 0 on success, -1 on failure.
2869 */
2870 static __inline int
2871 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp,
2872 struct rtw_txdesc_blk **tdbp, int pri)
2873 {
2874 struct rtw_txsoft_blk *tsb;
2875 struct rtw_txdesc_blk *tdb;
2876
2877 KKASSERT(pri >= 0 && pri < RTW_NTXPRI);
2878
2879 tsb = &sc->sc_txsoft_blk[pri];
2880 tdb = &sc->sc_txdesc_blk[pri];
2881
2882 if (STAILQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) {
2883 if (tsb->tsb_tx_timer == 0)
2884 tsb->tsb_tx_timer = 5;
2885 *tsbp = NULL;
2886 *tdbp = NULL;
2887 return -1;
2888 }
2889 *tsbp = tsb;
2890 *tdbp = tdb;
2891 return 0;
2892 }
2893
2894 static __inline struct mbuf *
2895 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri,
2896 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp,
2897 struct ieee80211_node **nip, int *if_flagsp)
2898 {
2899 struct mbuf *m;
2900 struct ifnet *ifp = &sc->sc_if;
2901
2902 if (IF_QEMPTY(ifq))
2903 return NULL;
2904 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2905 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2906 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2907 *if_flagsp |= IFF_OACTIVE;
2908 ifp->if_timer = 1;
2909 return NULL;
2910 }
2911 IF_DEQUEUE(ifq, m);
2912 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2913 m->m_pkthdr.rcvif = NULL;
2914 KKASSERT(*nip != NULL);
2915 return m;
2916 }
2917
2918 /*
2919 * Point *mp at the next 802.11 frame to transmit. Point *tsbp
2920 * at the driver's selection of transmit control block for the packet.
2921 */
2922 static int
2923 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp,
2924 struct rtw_txdesc_blk **tdbp, struct mbuf **mp,
2925 struct ieee80211_node **nip)
2926 {
2927 struct rtw_softc *sc = ifp->if_softc;
2928 int *if_flagsp = &ifp->if_flags;
2929 struct ether_header *eh;
2930 struct mbuf *m0;
2931 int pri;
2932
2933 DPRINTF(sc, RTW_DEBUG_XMIT,
2934 ("%s: enter %s\n", ifp->if_xname, __func__));
2935
2936 if (sc->sc_ic.ic_state == IEEE80211_S_RUN &&
2937 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp,
2938 tdbp, nip, if_flagsp)) != NULL) {
2939 DPRINTF(sc, RTW_DEBUG_XMIT,
2940 ("%s: dequeue beacon frame\n", ifp->if_xname));
2941 return 0;
2942 }
2943
2944 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp,
2945 tdbp, nip, if_flagsp)) != NULL) {
2946 DPRINTF(sc, RTW_DEBUG_XMIT,
2947 ("%s: dequeue mgt frame\n", ifp->if_xname));
2948 return 0;
2949 }
2950
2951 *mp = NULL;
2952
2953 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) {
2954 DPRINTF(sc, RTW_DEBUG_XMIT,
2955 ("%s: not running\n", ifp->if_xname));
2956 return 0;
2957 }
2958
2959 m0 = ifq_poll(&ifp->if_snd);
2960 if (m0 == NULL) {
2961 DPRINTF(sc, RTW_DEBUG_XMIT,
2962 ("%s: no frame ready\n", ifp->if_xname));
2963 return 0;
2964 }
2965
2966 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD;
2967
2968 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2969 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2970 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2971 *if_flagsp |= IFF_OACTIVE;
2972 sc->sc_if.if_timer = 1;
2973 return 0;
2974 }
2975
2976 ifq_dequeue(&ifp->if_snd, m0);
2977 DPRINTF(sc, RTW_DEBUG_XMIT,
2978 ("%s: dequeue data frame\n", ifp->if_xname));
2979
2980 BPF_MTAP(ifp, m0);
2981
2982 eh = mtod(m0, struct ether_header *);
2983 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost);
2984 if (*nip == NULL) {
2985 /* NB: ieee80211_find_txnode does stat+msg */
2986 m_freem(m0);
2987 return -1;
2988 }
2989
2990 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) {
2991 DPRINTF(sc, RTW_DEBUG_XMIT,
2992 ("%s: encap error\n", ifp->if_xname));
2993 ieee80211_free_node(*nip);
2994 ifp->if_oerrors++;
2995 return -1;
2996 }
2997
2998 ifp->if_opackets++;
2999 DPRINTF(sc, RTW_DEBUG_XMIT,
3000 ("%s: leave %s\n", ifp->if_xname, __func__));
3001 *mp = m0;
3002 return 0;
3003 }
3004
3005 static __inline int
3006 rtw_txsegs_too_short(struct rtw_txsegs *segs)
3007 {
3008 int i;
3009
3010 for (i = 0; i < segs->nseg; i++) {
3011 if (segs->segs[i].ds_len < 4)
3012 return 1;
3013 }
3014 return 0;
3015 }
3016
3017 static __inline int
3018 rtw_txsegs_too_long(struct rtw_txsegs *segs)
3019 {
3020 int i;
3021
3022 for (i = 0; i < segs->nseg; i++) {
3023 if (segs->segs[i].ds_len > RTW_TXLEN_LENGTH_MASK)
3024 return 1;
3025 }
3026 return 0;
3027 }
3028
3029 static void
3030 rtw_txbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
3031 bus_size_t mapsize, int error)
3032 {
3033 struct rtw_txsegs *s = arg;
3034
3035 if (error)
3036 return;
3037
3038 KASSERT(nseg <= RTW_MAXPKTSEGS, ("too many tx mbuf seg\n"));
3039
3040 s->nseg = nseg;
3041 bcopy(seg, s->segs, sizeof(*seg) * nseg);
3042 }
3043
3044 static struct mbuf *
3045 rtw_load_txbuf(struct rtw_softc *sc, struct rtw_txsoft *ts,
3046 struct rtw_txsegs *segs, int ndesc_free, struct mbuf *m)
3047 {
3048 int unload = 0, error;
3049
3050 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap, m,
3051 rtw_txbuf_dma_map, segs, BUS_DMA_NOWAIT);
3052 if (error && error != E2BIG) {
3053 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf1\n");
3054 goto back;
3055 }
3056
3057 if (error || segs->nseg > ndesc_free || rtw_txsegs_too_short(segs)) {
3058 struct mbuf *m_new;
3059
3060 if (error == 0)
3061 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3062
3063 m_new = m_defrag(m, MB_DONTWAIT);
3064 if (m_new == NULL) {
3065 if_printf(&sc->sc_ic.ic_if, "can't defrag tx mbuf\n");
3066 error = ENOBUFS;
3067 goto back;
3068 }
3069 m = m_new;
3070
3071 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap,
3072 m, rtw_txbuf_dma_map, segs,
3073 BUS_DMA_NOWAIT);
3074 if (error) {
3075 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf2\n");
3076 goto back;
3077 }
3078 unload = 1;
3079
3080 error = E2BIG;
3081 if (segs->nseg > ndesc_free) {
3082 if_printf(&sc->sc_ic.ic_if, "not enough free txdesc\n");
3083 goto back;
3084 }
3085 if (rtw_txsegs_too_short(segs)) {
3086 if_printf(&sc->sc_ic.ic_if, "segment too short\n");
3087 goto back;
3088 }
3089 error = 0;
3090 }
3091
3092 if (rtw_txsegs_too_long(segs)) {
3093 if_printf(&sc->sc_ic.ic_if, "segment too long\n");
3094 unload = 1;
3095 error = E2BIG;
3096 }
3097
3098 back:
3099 if (error) {
3100 if (unload)
3101 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3102 m_freem(m);
3103 m = NULL;
3104 } else {
3105 bus_dmamap_sync(sc->sc_txsoft_dmat, ts->ts_dmamap,
3106 BUS_DMASYNC_PREWRITE);
3107 }
3108 return m;
3109 }
3110
3111 #ifdef RTW_DEBUG
3112 static void
3113 rtw_print_txdesc(struct rtw_softc *sc, const char *action,
3114 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc)
3115 {
3116 struct rtw_txdesc *td = &tdb->tdb_desc[desc];
3117
3118 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
3119 ("%s: %p %s txdesc[%d] "
3120 "next %#08x buf %#08x "
3121 "ctl0 %#08x ctl1 %#08x len %#08x\n",
3122 sc->sc_ic.ic_if.if_xname, ts, action,
3123 desc, le32toh(td->td_buf), le32toh(td->td_next),
3124 le32toh(td->td_ctl0), le32toh(td->td_ctl1),
3125 le32toh(td->td_len)));
3126 }
3127 #endif /* RTW_DEBUG */
3128
3129 static void
3130 rtw_start(struct ifnet *ifp)
3131 {
3132 struct rtw_softc *sc = ifp->if_softc;
3133 struct ieee80211com *ic = &sc->sc_ic;
3134 struct ieee80211_node *ni;
3135 struct rtw_txsoft *ts;
3136 struct mbuf *m0;
3137 uint32_t proto_ctl0;
3138
3139 DPRINTF(sc, RTW_DEBUG_XMIT,
3140 ("%s: enter %s\n", ifp->if_xname, __func__));
3141
3142 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3143 goto out;
3144
3145 /* XXX do real rate control */
3146 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS;
3147
3148 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3149 proto_ctl0 |= RTW_TXCTL0_SPLCP;
3150
3151 for (;;) {
3152 struct rtw_txsegs segs;
3153 struct rtw_duration *d0;
3154 struct ieee80211_frame_min *wh;
3155 struct rtw_txsoft_blk *tsb;
3156 struct rtw_txdesc_blk *tdb;
3157 struct rtw_txdesc *td;
3158 struct ieee80211_key *k;
3159 uint32_t ctl0, ctl1;
3160 uint8_t tppoll;
3161 int desc, i, lastdesc, npkt, rate, rateidx, ratectl;
3162
3163 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1)
3164 continue;
3165 if (m0 == NULL)
3166 break;
3167
3168 wh = mtod(m0, struct ieee80211_frame_min *);
3169
3170 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 &&
3171 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3172 ieee80211_free_node(ni);
3173 m_freem(m0);
3174 break;
3175 } else {
3176 k = NULL;
3177 }
3178
3179 ts = STAILQ_FIRST(&tsb->tsb_freeq);
3180
3181 m0 = rtw_load_txbuf(sc, ts, &segs, tdb->tdb_nfree, m0);
3182 if (m0 == NULL || segs.nseg == 0) {
3183 DPRINTF(sc, RTW_DEBUG_XMIT,
3184 ("%s: %s failed\n", ifp->if_xname, __func__));
3185 goto post_dequeue_err;
3186 }
3187
3188 /*
3189 * Note well: rtw_load_txbuf may have created a new chain,
3190 * so we must find the header once more.
3191 */
3192 wh = mtod(m0, struct ieee80211_frame_min *);
3193
3194 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3195 IEEE80211_FC0_TYPE_MGT) {
3196 rateidx = 0;
3197 rate = 2; /* 1Mbit/s */
3198 ratectl = 0;
3199 } else {
3200 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len,
3201 &rateidx, 1);
3202 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx);
3203 ratectl =1;
3204
3205 if (rate == 0) {
3206 if_printf(ifp, "incorrect rate\n");
3207 rateidx = 0;
3208 rate = 2; /* 1Mbit/s */
3209 ratectl = 0;
3210 }
3211 }
3212
3213 #ifdef RTW_DEBUG
3214 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
3215 (IFF_DEBUG | IFF_LINK2)) {
3216 ieee80211_dump_pkt(mtod(m0, uint8_t *),
3217 (segs.nseg == 1) ? m0->m_pkthdr.len
3218 : sizeof(wh),
3219 rate, 0);
3220 }
3221 #endif /* RTW_DEBUG */
3222 ctl0 = proto_ctl0 |
3223 SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
3224
3225 switch (rate) {
3226 default:
3227 case 2:
3228 ctl0 |= RTW_TXCTL0_RATE_1MBPS;
3229 break;
3230 case 4:
3231 ctl0 |= RTW_TXCTL0_RATE_2MBPS;
3232 break;
3233 case 11:
3234 ctl0 |= RTW_TXCTL0_RATE_5MBPS;
3235 break;
3236 case 22:
3237 ctl0 |= RTW_TXCTL0_RATE_11MBPS;
3238 break;
3239 }
3240 /* XXX >= ? Compare after fragmentation? */
3241 if (m0->m_pkthdr.len > ic->ic_rtsthreshold)
3242 ctl0 |= RTW_TXCTL0_RTSEN;
3243
3244 /*
3245 * XXX Sometimes writes a bogus keyid; h/w doesn't
3246 * seem to care, since we don't activate h/w Tx
3247 * encryption.
3248 */
3249 if (k != NULL) {
3250 ctl0 |= SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &
3251 RTW_TXCTL0_KEYID_MASK;
3252 }
3253
3254 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3255 IEEE80211_FC0_TYPE_MGT) {
3256 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
3257 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3258 IEEE80211_FC0_SUBTYPE_BEACON)
3259 ctl0 |= RTW_TXCTL0_BEACON;
3260 }
3261
3262 if (rtw_compute_duration(wh, k, m0->m_pkthdr.len,
3263 ic->ic_flags, ic->ic_fragthreshold,
3264 rate, &ts->ts_d0, &ts->ts_dn, &npkt,
3265 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3266 (IFF_DEBUG|IFF_LINK2)) == -1) {
3267 DPRINTF(sc, RTW_DEBUG_XMIT,
3268 ("%s: fail compute duration\n", __func__));
3269 goto post_load_err;
3270 }
3271
3272 d0 = &ts->ts_d0;
3273
3274 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur);
3275
3276 ctl1 = SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
3277 SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
3278
3279 if (d0->d_residue)
3280 ctl1 |= RTW_TXCTL1_LENGEXT;
3281
3282 /* TBD fragmentation */
3283
3284 ts->ts_first = tdb->tdb_next;
3285 KKASSERT(ts->ts_first < tdb->tdb_ndesc);
3286
3287 if (ic->ic_rawbpf != NULL)
3288 bpf_mtap(ic->ic_rawbpf, m0);
3289
3290 if (sc->sc_radiobpf != NULL) {
3291 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
3292
3293 rt->rt_flags = 0;
3294 rt->rt_rate = rate;
3295
3296 bpf_ptap(sc->sc_radiobpf, m0, rt,
3297 sizeof(sc->sc_txtapu));
3298 }
3299
3300 for (i = 0, lastdesc = desc = ts->ts_first; i < segs.nseg;
3301 i++, desc = RTW_NEXT_IDX(tdb, desc)) {
3302 td = &tdb->tdb_desc[desc];
3303 td->td_ctl0 = htole32(ctl0);
3304 if (i != 0)
3305 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3306 td->td_ctl1 = htole32(ctl1);
3307 td->td_buf = htole32(segs.segs[i].ds_addr);
3308 td->td_len = htole32(segs.segs[i].ds_len);
3309 lastdesc = desc;
3310 #ifdef RTW_DEBUG
3311 rtw_print_txdesc(sc, "load", ts, tdb, desc);
3312 #endif /* RTW_DEBUG */
3313 }
3314
3315 KKASSERT(desc < tdb->tdb_ndesc);
3316
3317 ts->ts_ni = ni;
3318 KKASSERT(ni != NULL);
3319 ts->ts_mbuf = m0;
3320 ts->ts_rateidx = rateidx;
3321 ts->ts_ratectl = ratectl;
3322 ts->ts_last = lastdesc;
3323 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS);
3324 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_FS);
3325
3326 #ifdef RTW_DEBUG
3327 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first);
3328 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last);
3329 #endif /* RTW_DEBUG */
3330
3331 tdb->tdb_nfree -= segs.nseg;
3332 tdb->tdb_next = desc;
3333
3334 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3335
3336 #ifdef RTW_DEBUG
3337 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first);
3338 #endif /* RTW_DEBUG */
3339
3340 STAILQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q);
3341 STAILQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q);
3342
3343 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN])
3344 sc->sc_led_state.ls_event |= RTW_LED_S_TX;
3345 tsb->tsb_tx_timer = 5;
3346 ifp->if_timer = 1;
3347 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL);
3348 tppoll &= ~RTW_TPPOLL_SALL;
3349 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL;
3350 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll);
3351 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL);
3352
3353 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
3354 BUS_DMASYNC_PREWRITE);
3355 }
3356 out:
3357 DPRINTF(sc, RTW_DEBUG_XMIT,
3358 ("%s: leave %s\n", ifp->if_xname, __func__));
3359 return;
3360
3361 post_load_err:
3362 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3363 m_freem(m0);
3364 post_dequeue_err:
3365 ieee80211_free_node(ni);
3366
3367 DPRINTF(sc, RTW_DEBUG_XMIT,
3368 ("%s: leave %s\n", ifp->if_xname, __func__));
3369 }
3370
3371 static void
3372 rtw_idle(struct rtw_softc *sc)
3373 {
3374 struct rtw_regs *regs = &sc->sc_regs;
3375 int active;
3376
3377 /* request stop DMA; wait for packets to stop transmitting. */
3378
3379 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
3380 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
3381
3382 for (active = 0;
3383 active < 300 &&
3384 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0;
3385 active++)
3386 DELAY(10);
3387 if_printf(&sc->sc_ic.ic_if, "transmit DMA idle in %dus\n", active * 10);
3388 }
3389
3390 static void
3391 rtw_watchdog(struct ifnet *ifp)
3392 {
3393 int pri, tx_timeouts = 0;
3394 struct rtw_softc *sc = ifp->if_softc;
3395
3396 ifp->if_timer = 0;
3397
3398 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
3399 return;
3400
3401 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3402 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
3403
3404 if (tsb->tsb_tx_timer == 0)
3405 continue;
3406 else if (--tsb->tsb_tx_timer == 0) {
3407 if (STAILQ_EMPTY(&tsb->tsb_dirtyq))
3408 continue;
3409 if_printf(ifp, "transmit timeout, priority %d\n", pri);
3410 ifp->if_oerrors++;
3411 tx_timeouts++;
3412 } else {
3413 ifp->if_timer = 1;
3414 }
3415 }
3416
3417 if (tx_timeouts > 0) {
3418 /*
3419 * Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr,
3420 * reset s/w tx-ring pointers, and start transmission.
3421 *
3422 * TBD Stop/restart just the broken rings?
3423 */
3424 rtw_idle(sc);
3425 rtw_io_enable(sc, RTW_CR_TE, 0);
3426 rtw_txdesc_blk_reset_all(sc);
3427 rtw_io_enable(sc, RTW_CR_TE, 1);
3428 rtw_txring_fixup(sc);
3429 rtw_start(ifp);
3430 }
3431 ieee80211_watchdog(&sc->sc_ic);
3432 }
3433
3434 static void
3435 rtw_next_scan(void *arg)
3436 {
3437 struct ieee80211com *ic = arg;
3438 struct ifnet *ifp = &ic->ic_if;
3439
3440 lwkt_serialize_enter(ifp->if_serializer);
3441
3442 /* don't call rtw_start w/o network interrupts blocked */
3443 if (ic->ic_state == IEEE80211_S_SCAN)
3444 ieee80211_next_scan(ic);
3445
3446 lwkt_serialize_exit(ifp->if_serializer);
3447 }
3448
3449 static void
3450 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0)
3451 {
3452 uint16_t bcnitv, bintritv, intval;
3453 int i;
3454 struct rtw_regs *regs = &sc->sc_regs;
3455
3456 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3457 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
3458
3459 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
3460
3461 rtw_set_access(sc, RTW_ACCESS_CONFIG);
3462
3463 intval = MIN(intval0, SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK));
3464
3465 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
3466 bcnitv |= SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);
3467 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
3468 /* interrupt host 1ms before the TBTT */
3469 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
3470 bintritv |= SHIFTIN(1000, RTW_BINTRITV_BINTRITV);
3471 RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
3472 /* magic from Linux */
3473 RTW_WRITE16(regs, RTW_ATIMWND, SHIFTIN(1, RTW_ATIMWND_ATIMWND));
3474 RTW_WRITE16(regs, RTW_ATIMTRITV, SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));
3475 rtw_set_access(sc, RTW_ACCESS_NONE);
3476
3477 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3478 }
3479
3480 /* Synchronize the hardware state with the software state. */
3481 static int
3482 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3483 {
3484 struct ifnet *ifp = ic->ic_ifp;
3485 struct rtw_softc *sc = ifp->if_softc;
3486 enum ieee80211_state ostate;
3487 int error;
3488
3489 ostate = ic->ic_state;
3490
3491 ieee80211_ratectl_newstate(ic, nstate);
3492 rtw_led_newstate(sc, nstate);
3493
3494 if (nstate == IEEE80211_S_INIT) {
3495 callout_stop(&sc->sc_scan_ch);
3496 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
3497 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3498 }
3499
3500 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT)
3501 rtw_pwrstate(sc, RTW_ON);
3502
3503 error = rtw_tune(sc);
3504 if (error != 0)
3505 return error;
3506
3507 switch (nstate) {
3508 case IEEE80211_S_INIT:
3509 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__);
3510 break;
3511 case IEEE80211_S_SCAN:
3512 if (ostate != IEEE80211_S_SCAN) {
3513 memset(ic->ic_bss->ni_bssid, 0, IEEE80211_ADDR_LEN);
3514 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3515 }
3516
3517 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000,
3518 rtw_next_scan, ic);
3519
3520 break;
3521 case IEEE80211_S_RUN:
3522 switch (ic->ic_opmode) {
3523 case IEEE80211_M_HOSTAP:
3524 case IEEE80211_M_IBSS:
3525 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3526 /*FALLTHROUGH*/
3527 case IEEE80211_M_AHDEMO:
3528 case IEEE80211_M_STA:
3529 rtw_join_bss(sc, ic->ic_bss->ni_bssid,
3530 ic->ic_bss->ni_intval);
3531 break;
3532 case IEEE80211_M_MONITOR:
3533 break;
3534 }
3535 rtw_set_nettype(sc, ic->ic_opmode);
3536 break;
3537 case IEEE80211_S_ASSOC:
3538 case IEEE80211_S_AUTH:
3539 break;
3540 }
3541
3542 if (nstate != IEEE80211_S_SCAN)
3543 callout_stop(&sc->sc_scan_ch);
3544
3545 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3546 }
3547
3548 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */
3549 static uint64_t
3550 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp)
3551 {
3552 uint32_t tsftl, tsfth;
3553
3554 tsfth = RTW_READ(regs, RTW_TSFTRH);
3555 tsftl = RTW_READ(regs, RTW_TSFTRL);
3556 if (tsftl < rstamp) /* Compensate for rollover. */
3557 tsfth--;
3558 return ((uint64_t)tsfth << 32) | rstamp;
3559 }
3560
3561 static void
3562 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
3563 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
3564 {
3565 struct ifnet *ifp = &ic->ic_if;
3566 struct rtw_softc *sc = ifp->if_softc;
3567
3568 sc->sc_mtbl.mt_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
3569
3570 switch (subtype) {
3571 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3572 case IEEE80211_FC0_SUBTYPE_BEACON:
3573 if (ic->ic_opmode == IEEE80211_M_IBSS &&
3574 ic->ic_state == IEEE80211_S_RUN) {
3575 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp);
3576
3577 if (le64toh(ni->ni_tstamp.tsf) >= tsf)
3578 ieee80211_ibss_merge(ni);
3579 }
3580 break;
3581 default:
3582 break;
3583 }
3584 }
3585
3586 #ifdef foo
3587 static struct ieee80211_node *
3588 rtw_node_alloc(struct ieee80211_node_table *nt)
3589 {
3590 struct ifnet *ifp = nt->nt_ic->ic_ifp;
3591 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3592 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt);
3593
3594 DPRINTF(sc, RTW_DEBUG_NODE,
3595 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
3596 return ni;
3597 }
3598
3599 static void
3600 rtw_node_free(struct ieee80211_node *ni)
3601 {
3602 struct ieee80211com *ic = ni->ni_ic;
3603 struct ifnet *ifp = ic->ic_ifp;
3604 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3605
3606 DPRINTF(sc, RTW_DEBUG_NODE,
3607 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
3608 ether_sprintf(ni->ni_bssid)));
3609 sc->sc_mtbl.mt_node_free(ni);
3610 }
3611 #endif
3612
3613 static int
3614 rtw_media_change(struct ifnet *ifp)
3615 {
3616 int error;
3617
3618 error = ieee80211_media_change(ifp);
3619 if (error == ENETRESET) {
3620 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
3621 (IFF_RUNNING|IFF_UP))
3622 rtw_init(ifp); /* XXX lose error */
3623 error = 0;
3624 }
3625 return error;
3626 }
3627
3628 static void
3629 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
3630 {
3631 struct rtw_softc *sc = ifp->if_softc;
3632
3633 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
3634 imr->ifm_active = IFM_IEEE80211 | IFM_NONE;
3635 imr->ifm_status = 0;
3636 return;
3637 }
3638 ieee80211_media_status(ifp, imr);
3639 }
3640
3641 static __inline void
3642 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic)
3643 {
3644 mtbl->mt_newstate = ic->ic_newstate;
3645 ic->ic_newstate = rtw_newstate;
3646
3647 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt;
3648 ic->ic_recv_mgmt = rtw_recv_mgmt;
3649
3650 #ifdef foo
3651 mtbl->mt_node_free = ic->ic_node_free;
3652 ic->ic_node_free = rtw_node_free;
3653
3654 mtbl->mt_node_alloc = ic->ic_node_alloc;
3655 ic->ic_node_alloc = rtw_node_alloc;
3656 #endif
3657
3658 ic->ic_crypto.cs_key_delete = rtw_key_delete;
3659 ic->ic_crypto.cs_key_set = rtw_key_set;
3660 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin;
3661 ic->ic_crypto.cs_key_update_end = rtw_key_update_end;
3662 }
3663
3664 static __inline void
3665 rtw_init_radiotap(struct rtw_softc *sc)
3666 {
3667 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
3668 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT);
3669
3670 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
3671 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT);
3672 }
3673
3674 static struct rtw_rf *
3675 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy)
3676 {
3677 rtw_rf_write_t rf_write;
3678 struct rtw_rf *rf;
3679
3680 switch (rfchipid) {
3681 default:
3682 rf_write = rtw_rf_hostwrite;
3683 break;
3684 case RTW_RFCHIPID_INTERSIL:
3685 case RTW_RFCHIPID_PHILIPS:
3686 case RTW_RFCHIPID_GCT: /* XXX a guess */
3687 case RTW_RFCHIPID_RFMD:
3688 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite;
3689 break;
3690 }
3691
3692 switch (rfchipid) {
3693 case RTW_RFCHIPID_GCT:
3694 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0);
3695 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3696 sc->sc_getrssi = rtw_gct_getrssi;
3697 break;
3698 case RTW_RFCHIPID_MAXIM:
3699 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0);
3700 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3701 sc->sc_getrssi = rtw_maxim_getrssi;
3702 break;
3703 case RTW_RFCHIPID_PHILIPS:
3704 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy);
3705 sc->sc_pwrstate_cb = rtw_philips_pwrstate;
3706 sc->sc_getrssi = rtw_philips_getrssi;
3707 break;
3708 case RTW_RFCHIPID_RFMD:
3709 /* XXX RFMD has no RF constructor */
3710 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate;
3711 /*FALLTHROUGH*/
3712 default:
3713 return NULL;
3714 }
3715 rf->rf_continuous_tx_cb =
3716 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable;
3717 rf->rf_continuous_tx_arg = sc;
3718 return rf;
3719 }
3720
3721 /* Revision C and later use a different PHY delay setting than
3722 * revisions A and B.
3723 */
3724 static uint8_t
3725 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr)
3726 {
3727 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV)
3728 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE)
3729
3730 uint8_t phydelay = SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);
3731
3732 RTW_WRITE(regs, RTW_RCR, REVAB);
3733 RTW_WBW(regs, RTW_RCR, RTW_RCR);
3734 RTW_WRITE(regs, RTW_RCR, REVC);
3735
3736 RTW_WBR(regs, RTW_RCR, RTW_RCR);
3737 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
3738 phydelay |= RTW_PHYDELAY_REVC_MAGIC;
3739
3740 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
3741 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
3742
3743 return phydelay;
3744 #undef REVC
3745 #undef REVAB
3746 }
3747
3748 int
3749 rtw_attach(device_t dev)
3750 {
3751 struct rtw_softc *sc = device_get_softc(dev);
3752 struct ieee80211com *ic = &sc->sc_ic;
3753 const struct ieee80211_cipher *wep_cipher;
3754 struct ifnet *ifp = &ic->ic_if;
3755 int rc;
3756
3757 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
3758 KKASSERT(wep_cipher != NULL);
3759
3760 memcpy(&rtw_cipher_wep, wep_cipher, sizeof(rtw_cipher_wep));
3761 rtw_cipher_wep.ic_decap = rtw_wep_decap;
3762
3763 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3764
3765 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
3766 case RTW_TCR_HWVERID_F:
3767 sc->sc_hwverid = 'F';
3768 break;
3769 case RTW_TCR_HWVERID_D:
3770 sc->sc_hwverid = 'D';
3771 break;
3772 default:
3773 sc->sc_hwverid = '?';
3774 break;
3775 }
3776
3777 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3778 &sc->sc_irq_rid,
3779 RF_ACTIVE | RF_SHAREABLE);
3780 if (sc->sc_irq_res == NULL) {
3781 device_printf(dev, "could not alloc irq res\n");
3782 return ENXIO;
3783 }
3784
3785 /* Allocate h/w desc blocks */
3786 rc = rtw_desc_blk_alloc(sc);
3787 if (rc)
3788 goto err;
3789
3790 /* Allocate s/w desc blocks */
3791 rc = rtw_soft_blk_alloc(sc);
3792 if (rc)
3793 goto err;
3794
3795 /* Reset the chip to a known state. */
3796 rc = rtw_reset(sc);
3797 if (rc) {
3798 device_printf(dev, "could not reset\n");
3799 goto err;
3800 }
3801
3802 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
3803
3804 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0)
3805 sc->sc_flags |= RTW_F_9356SROM;
3806
3807 rc = rtw_srom_read(sc);
3808 if (rc)
3809 goto err;
3810
3811 rc = rtw_srom_parse(sc);
3812 if (rc) {
3813 device_printf(dev, "malformed serial ROM\n");
3814 goto err;
3815 }
3816
3817 device_printf(dev, "%s PHY\n",
3818 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital"
3819 : "analog");
3820
3821 device_printf(dev, "CS threshold %u\n", sc->sc_csthr);
3822
3823 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid,
3824 sc->sc_flags & RTW_F_DIGPHY);
3825 if (sc->sc_rf == NULL) {
3826 device_printf(dev, "could not attach RF\n");
3827 rc = ENXIO;
3828 goto err;
3829 }
3830
3831 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr);
3832
3833 RTW_DPRINTF(RTW_DEBUG_ATTACH,
3834 ("%s: PHY delay %d\n", ifp->if_xname, sc->sc_phydelay));
3835
3836 if (sc->sc_locale == RTW_LOCALE_UNKNOWN)
3837 rtw_identify_country(sc);
3838
3839 rtw_init_channels(sc);
3840
3841 rc = rtw_identify_sta(sc);
3842 if (rc)
3843 goto err;
3844
3845 ifp->if_softc = sc;
3846 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
3847 ifp->if_init = rtw_init;
3848 ifp->if_ioctl = rtw_ioctl;
3849 ifp->if_start = rtw_start;
3850 ifp->if_watchdog = rtw_watchdog;
3851 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
3852 ifq_set_ready(&ifp->if_snd);
3853
3854 ic->ic_phytype = IEEE80211_T_DS;
3855 ic->ic_opmode = IEEE80211_M_STA;
3856 ic->ic_caps = IEEE80211_C_PMGT |
3857 IEEE80211_C_IBSS |
3858 IEEE80211_C_HOSTAP |
3859 IEEE80211_C_MONITOR;
3860 ic->ic_sup_rates[IEEE80211_MODE_11B] = rtw_rates_11b;
3861
3862 /* initialize led callout */
3863 callout_init(&sc->sc_led_state.ls_fast_ch);
3864 callout_init(&sc->sc_led_state.ls_slow_ch);
3865
3866 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
3867 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
3868
3869 /*
3870 * Call MI attach routines.
3871 */
3872 ieee80211_ifattach(&sc->sc_ic);
3873
3874 /* Override some ieee80211 methods */
3875 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic);
3876
3877 /*
3878 * possibly we should fill in our own sc_send_prresp, since
3879 * the RTL8180 is probably sending probe responses in ad hoc
3880 * mode.
3881 */
3882
3883 /* complete initialization */
3884 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status);
3885 callout_init(&sc->sc_scan_ch);
3886
3887 rtw_init_radiotap(sc);
3888
3889 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
3890 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
3891
3892 rc = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, rtw_intr, sc,
3893 &sc->sc_irq_handle, ifp->if_serializer);
3894 if (rc) {
3895 device_printf(dev, "can't set up interrupt\n");
3896 bpfdetach(ifp);
3897 ieee80211_ifdetach(ic);
3898 goto err;
3899 }
3900
3901 device_printf(dev, "hardware version %c\n", sc->sc_hwverid);
3902 if (bootverbose)
3903 ieee80211_announce(ic);
3904 return 0;
3905 err:
3906 rtw_detach(dev);
3907 return rc;
3908 }
3909
3910 int
3911 rtw_detach(device_t dev)
3912 {
3913 struct rtw_softc *sc = device_get_softc(dev);
3914 struct ifnet *ifp = &sc->sc_ic.ic_if;
3915
3916 if (device_is_attached(dev)) {
3917 lwkt_serialize_enter(ifp->if_serializer);
3918
3919 rtw_stop(sc, 1);
3920 sc->sc_flags |= RTW_F_INVALID;
3921
3922 callout_stop(&sc->sc_scan_ch);
3923 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
3924
3925 lwkt_serialize_exit(ifp->if_serializer);
3926
3927 ieee80211_ifdetach(&sc->sc_ic);
3928 }
3929
3930 if (sc->sc_rf != NULL)
3931 rtw_rf_destroy(sc->sc_rf);
3932
3933 if (sc->sc_srom.sr_content != NULL)
3934 kfree(sc->sc_srom.sr_content, M_DEVBUF);
3935
3936 if (sc->sc_irq_res != NULL) {
3937 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
3938 sc->sc_irq_res);
3939 }
3940
3941 rtw_soft_blk_free(sc);
3942 rtw_desc_blk_free(sc);
3943 return 0;
3944 }
3945
3946 static void
3947 rtw_desc_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3948 {
3949 if (error)
3950 return;
3951
3952 KASSERT(nseg == 1, ("too many desc segments\n"));
3953 *((uint32_t *)arg) = seg->ds_addr; /* XXX bus_addr_t */
3954 }
3955
3956 static int
3957 rtw_dma_alloc(struct rtw_softc *sc, bus_dma_tag_t *dmat, int len,
3958 void **desc, uint32_t *phyaddr, bus_dmamap_t *dmamap)
3959 {
3960 int error;
3961
3962 error = bus_dma_tag_create(NULL, RTW_DESC_ALIGNMENT, 0,
3963 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3964 NULL, NULL, len, 1, len, 0, dmat);
3965 if (error) {
3966 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA tag");
3967 return error;
3968 }
3969
3970 error = bus_dmamem_alloc(*dmat, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3971 dmamap);
3972 if (error) {
3973 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA mem");
3974 return error;
3975 }
3976
3977 error = bus_dmamap_load(*dmat, *dmamap, *desc, len,
3978 rtw_desc_dma_addr, phyaddr, BUS_DMA_WAITOK);
3979 if (error) {
3980 if_printf(&sc->sc_ic.ic_if, "could not load desc DMA mem");
3981 bus_dmamem_free(*dmat, *desc, *dmamap);
3982 *desc = NULL;
3983 return error;
3984 }
3985 return 0;
3986 }
3987
3988 static void
3989 rtw_dma_free(struct rtw_softc *sc __unused, bus_dma_tag_t *dmat, void **desc,
3990 bus_dmamap_t *dmamap)
3991 {
3992 if (*desc != NULL) {
3993 bus_dmamap_unload(*dmat, *dmamap);
3994 bus_dmamem_free(*dmat, *desc, *dmamap);
3995 *desc = NULL;
3996 }
3997
3998 if (*dmat != NULL) {
3999 bus_dma_tag_destroy(*dmat);
4000 *dmat = NULL;
4001 }
4002 }
4003
4004 static void
4005 rtw_txdesc_blk_free(struct rtw_softc *sc, int q_no)
4006 {
4007 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4008
4009 rtw_dma_free(sc, &tdb->tdb_dmat, (void **)&tdb->tdb_desc,
4010 &tdb->tdb_dmamap);
4011 }
4012
4013 static int
4014 rtw_txdesc_blk_alloc(struct rtw_softc *sc, int q_len, int q_no,
4015 bus_size_t q_basereg)
4016 {
4017 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4018 int i, error;
4019
4020 /*
4021 * Setup TX h/w desc
4022 */
4023 error = rtw_dma_alloc(sc, &tdb->tdb_dmat,
4024 q_len * sizeof(*tdb->tdb_desc),
4025 (void **)&tdb->tdb_desc, &tdb->tdb_base,
4026 &tdb->tdb_dmamap);
4027 if (error) {
4028 kprintf("%dth tx\n", q_no);
4029 return error;
4030 }
4031 tdb->tdb_basereg = q_basereg;
4032
4033 tdb->tdb_ndesc = q_len;
4034 for (i = 0; i < tdb->tdb_ndesc; ++i)
4035 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i));
4036
4037 return 0;
4038 }
4039
4040 static void
4041 rtw_rxdesc_blk_free(struct rtw_softc *sc)
4042 {
4043 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4044
4045 rtw_dma_free(sc, &rdb->rdb_dmat, (void **)&rdb->rdb_desc,
4046 &rdb->rdb_dmamap);
4047 }
4048
4049 static int
4050 rtw_rxdesc_blk_alloc(struct rtw_softc *sc, int q_len)
4051 {
4052 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4053 int error;
4054
4055 /*
4056 * Setup RX h/w desc
4057 */
4058 error = rtw_dma_alloc(sc, &rdb->rdb_dmat,
4059 q_len * sizeof(*rdb->rdb_desc),
4060 (void **)&rdb->rdb_desc, &rdb->rdb_base,
4061 &rdb->rdb_dmamap);
4062 if (error) {
4063 kprintf("rx\n");
4064 } else {
4065 rdb->rdb_ndesc = q_len;
4066 }
4067
4068 return error;
4069 }
4070
4071 static void
4072 rtw_txsoft_blk_free(struct rtw_softc *sc, int n_sd, int q_no)
4073 {
4074 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4075
4076 if (tsb->tsb_desc != NULL) {
4077 int i;
4078
4079 for (i = 0; i < n_sd; ++i) {
4080 bus_dmamap_destroy(sc->sc_txsoft_dmat,
4081 tsb->tsb_desc[i].ts_dmamap);
4082 }
4083 kfree(tsb->tsb_desc, M_DEVBUF);
4084 tsb->tsb_desc = NULL;
4085 }
4086 }
4087
4088 static int
4089 rtw_txsoft_blk_alloc(struct rtw_softc *sc, int q_len, int q_no, uint8_t q_poll)
4090 {
4091 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4092 int i, error;
4093
4094 STAILQ_INIT(&tsb->tsb_dirtyq);
4095 STAILQ_INIT(&tsb->tsb_freeq);
4096 tsb->tsb_ndesc = q_len;
4097 tsb->tsb_desc = kmalloc(q_len * sizeof(*tsb->tsb_desc), M_DEVBUF,
4098 M_WAITOK | M_ZERO);
4099 tsb->tsb_poll = q_poll;
4100
4101 for (i = 0; i < tsb->tsb_ndesc; ++i) {
4102 error = bus_dmamap_create(sc->sc_txsoft_dmat, 0,
4103 &tsb->tsb_desc[i].ts_dmamap);
4104 if (error) {
4105 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4106 "for soft tx desc\n");
4107 rtw_txsoft_blk_free(sc, i, q_no);
4108 return error;
4109 }
4110 }
4111 return 0;
4112 }
4113
4114 static void
4115 rtw_rxsoft_blk_free(struct rtw_softc *sc, int n_sd)
4116 {
4117 if (sc->sc_rxsoft_free) {
4118 int i;
4119
4120 for (i = 0; i < n_sd; ++i) {
4121 bus_dmamap_destroy(sc->sc_rxsoft_dmat,
4122 sc->sc_rxsoft[i].rs_dmamap);
4123 }
4124 sc->sc_rxsoft_free = 0;
4125 }
4126 }
4127
4128 static int
4129 rtw_rxsoft_blk_alloc(struct rtw_softc *sc, int q_len)
4130 {
4131 int i, error;
4132
4133 sc->sc_rxsoft_free = 1;
4134
4135 /*
4136 * Setup RX s/w desc
4137 */
4138 for (i = 0; i < q_len; ++i) {
4139 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0,
4140 &sc->sc_rxsoft[i].rs_dmamap);
4141 if (error) {
4142 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4143 "for soft rx desc\n");
4144 rtw_rxsoft_blk_free(sc, i);
4145 return error;
4146 }
4147 }
4148 return 0;
4149 }
4150
4151 #define TXQ_PARAM(q, poll, breg) \
4152 [RTW_TXPRI ## q] = { \
4153 .txq_len = RTW_TXQLEN ## q, \
4154 .txq_poll = poll, \
4155 .txq_basereg = breg \
4156 }
4157 static const struct {
4158 int txq_len;
4159 uint8_t txq_poll;
4160 bus_size_t txq_basereg;
4161 } txq_params[RTW_NTXPRI] = {
4162 TXQ_PARAM(LO, RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ, RTW_TLPDA),
4163 TXQ_PARAM(MD, RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ, RTW_TNPDA),
4164 TXQ_PARAM(HI, RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ, RTW_THPDA),
4165 TXQ_PARAM(BCN, RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ, RTW_TBDA)
4166 };
4167 #undef TXQ_PARAM
4168
4169 static int
4170 rtw_desc_blk_alloc(struct rtw_softc *sc)
4171 {
4172 int i, error;
4173
4174 /* Create h/w TX desc */
4175 for (i = 0; i < RTW_NTXPRI; ++i) {
4176 error = rtw_txdesc_blk_alloc(sc, txq_params[i].txq_len, i,
4177 txq_params[i].txq_basereg);
4178 if (error)
4179 return error;
4180 }
4181
4182 /* Create h/w RX desc */
4183 return rtw_rxdesc_blk_alloc(sc, RTW_RXQLEN);
4184 }
4185
4186 static void
4187 rtw_desc_blk_free(struct rtw_softc *sc)
4188 {
4189 int i;
4190
4191 for (i = 0; i < RTW_NTXPRI; ++i)
4192 rtw_txdesc_blk_free(sc, i);
4193 rtw_rxdesc_blk_free(sc);
4194 }
4195
4196 static int
4197 rtw_soft_blk_alloc(struct rtw_softc *sc)
4198 {
4199 int i, error;
4200
4201 /* Create DMA tag for TX mbuf */
4202 error = bus_dma_tag_create(NULL, 1, 0,
4203 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4204 NULL, NULL,
4205 MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES,
4206 0, &sc->sc_txsoft_dmat);
4207 if (error) {
4208 if_printf(&sc->sc_ic.ic_if, "could not alloc txsoft DMA tag\n");
4209 return error;
4210 }
4211
4212 /* Create DMA tag for RX mbuf */
4213 error = bus_dma_tag_create(NULL, 1, 0,
4214 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4215 NULL, NULL,
4216 MCLBYTES, 1, MCLBYTES,
4217 0, &sc->sc_rxsoft_dmat);
4218 if (error) {
4219 if_printf(&sc->sc_ic.ic_if, "could not alloc rxsoft DMA tag\n");
4220 return error;
4221 }
4222
4223 /* Create a spare DMA map for RX mbuf */
4224 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0, &sc->sc_rxsoft_dmamap);
4225 if (error) {
4226 if_printf(&sc->sc_ic.ic_if, "could not alloc spare rxsoft "
4227 "DMA map\n");
4228 bus_dma_tag_destroy(sc->sc_rxsoft_dmat);
4229 sc->sc_rxsoft_dmat = NULL;
4230 return error;
4231 }
4232
4233 /* Create s/w TX desc */
4234 for (i = 0; i < RTW_NTXPRI; ++i) {
4235 error = rtw_txsoft_blk_alloc(sc, txq_params[i].txq_len, i,
4236 txq_params[i].txq_poll);
4237 if (error)
4238 return error;
4239 }
4240
4241 /* Create s/w RX desc */
4242 return rtw_rxsoft_blk_alloc(sc, RTW_RXQLEN);
4243 }
4244
4245 static void
4246 rtw_soft_blk_free(struct rtw_softc *sc)
4247 {
4248 int i;
4249
4250 for (i = 0; i < RTW_NTXPRI; ++i)
4251 rtw_txsoft_blk_free(sc, txq_params[i].txq_len, i);
4252
4253 rtw_rxsoft_blk_free(sc, RTW_RXQLEN);
4254
4255 if (sc->sc_txsoft_dmat != NULL) {
4256 bus_dma_tag_destroy(sc->sc_txsoft_dmat);
4257 sc->sc_txsoft_dmat = NULL;
4258 }
4259
4260 if (sc->sc_rxsoft_dmat != NULL) {
4261 bus_dmamap_destroy(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap);
4262 bus_dma_tag_destroy(sc->sc_rxsoft_dmat);
4263 sc->sc_rxsoft_dmat = NULL;
4264 }
4265 }
4266
4267 /*
4268 * Arguments in:
4269 *
4270 * paylen: payload length (no FCS, no WEP header)
4271 *
4272 * hdrlen: header length
4273 *
4274 * rate: MSDU speed, units 500kb/s
4275 *
4276 * flags: IEEE80211_F_SHPREAMBLE (use short preamble),
4277 * IEEE80211_F_SHSLOT (use short slot length)
4278 *
4279 * Arguments out:
4280 *
4281 * d: 802.11 Duration field for RTS,
4282 * 802.11 Duration field for data frame,
4283 * PLCP Length for data frame,
4284 * residual octets at end of data slot
4285 */
4286 static int
4287 rtw_compute_duration1(int len, int use_ack, uint32_t icflags, int rate,
4288 struct rtw_duration *d)
4289 {
4290 int pre, ctsrate;
4291 int ack, bitlen, data_dur, remainder;
4292
4293 /*
4294 * RTS reserves medium for SIFS | CTS | SIFS | (DATA) | SIFS | ACK
4295 * DATA reserves medium for SIFS | ACK
4296 *
4297 * XXXMYC: no ACK on multicast/broadcast or control packets
4298 */
4299
4300 bitlen = len * 8;
4301
4302 pre = IEEE80211_DUR_DS_SIFS;
4303 if (icflags & IEEE80211_F_SHPREAMBLE) {
4304 pre += IEEE80211_DUR_DS_SHORT_PREAMBLE +
4305 IEEE80211_DUR_DS_FAST_PLCPHDR;
4306 } else {
4307 pre += IEEE80211_DUR_DS_LONG_PREAMBLE +
4308 IEEE80211_DUR_DS_SLOW_PLCPHDR;
4309 }
4310
4311 d->d_residue = 0;
4312 data_dur = (bitlen * 2) / rate;
4313 remainder = (bitlen * 2) % rate;
4314 if (remainder != 0) {
4315 d->d_residue = (rate - remainder) / 16;
4316 data_dur++;
4317 }
4318
4319 switch (rate) {
4320 case 2: /* 1 Mb/s */
4321 case 4: /* 2 Mb/s */
4322 /* 1 - 2 Mb/s WLAN: send ACK/CTS at 1 Mb/s */
4323 ctsrate = 2;
4324 break;
4325 case 11: /* 5.5 Mb/s */
4326 case 22: /* 11 Mb/s */
4327 case 44: /* 22 Mb/s */
4328 /* 5.5 - 11 Mb/s WLAN: send ACK/CTS at 2 Mb/s */
4329 ctsrate = 4;
4330 break;
4331 default:
4332 /* TBD */
4333 return -1;
4334 }
4335
4336 d->d_plcp_len = data_dur;
4337
4338 ack = (use_ack) ? pre + (IEEE80211_DUR_DS_SLOW_ACK * 2) / ctsrate : 0;
4339
4340 d->d_rts_dur = pre + (IEEE80211_DUR_DS_SLOW_CTS * 2) / ctsrate +
4341 pre + data_dur +
4342 ack;
4343
4344 d->d_data_dur = ack;
4345 return 0;
4346 }
4347
4348 /*
4349 * Arguments in:
4350 *
4351 * wh: 802.11 header
4352 *
4353 * paylen: payload length (no FCS, no WEP header)
4354 *
4355 * rate: MSDU speed, units 500kb/s
4356 *
4357 * fraglen: fragment length, set to maximum (or higher) for no
4358 * fragmentation
4359 *
4360 * flags: IEEE80211_F_PRIVACY (hardware adds WEP),
4361 * IEEE80211_F_SHPREAMBLE (use short preamble),
4362 * IEEE80211_F_SHSLOT (use short slot length)
4363 *
4364 * Arguments out:
4365 *
4366 * d0: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields
4367 * of first/only fragment
4368 *
4369 * dn: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields
4370 * of last fragment
4371 *
4372 * rtw_compute_duration assumes crypto-encapsulation, if any,
4373 * has already taken place.
4374 */
4375 static int
4376 rtw_compute_duration(const struct ieee80211_frame_min *wh,
4377 const struct ieee80211_key *wk, int len,
4378 uint32_t icflags, int fraglen, int rate,
4379 struct rtw_duration *d0, struct rtw_duration *dn,
4380 int *npktp, int debug)
4381 {
4382 int ack, rc;
4383 int cryptolen, /* crypto overhead: header+trailer */
4384 firstlen, /* first fragment's payload + overhead length */
4385 hdrlen, /* header length w/o driver padding */
4386 lastlen, /* last fragment's payload length w/ overhead */
4387 lastlen0, /* last fragment's payload length w/o overhead */
4388 npkt, /* number of fragments */
4389 overlen, /* non-802.11 header overhead per fragment */
4390 paylen; /* payload length w/o overhead */
4391
4392 hdrlen = ieee80211_anyhdrsize((const void *)wh);
4393
4394 /* Account for padding required by the driver. */
4395 if (icflags & IEEE80211_F_DATAPAD)
4396 paylen = len - roundup(hdrlen, sizeof(u_int32_t));
4397 else
4398 paylen = len - hdrlen;
4399
4400 overlen = IEEE80211_CRC_LEN;
4401
4402 if (wk != NULL) {
4403 cryptolen = wk->wk_cipher->ic_header +
4404 wk->wk_cipher->ic_trailer;
4405 paylen -= cryptolen;
4406 overlen += cryptolen;
4407 }
4408
4409 npkt = paylen / fraglen;
4410 lastlen0 = paylen % fraglen;
4411
4412 if (npkt == 0) { /* no fragments */
4413 lastlen = paylen + overlen;
4414 } else if (lastlen0 != 0) { /* a short "tail" fragment */
4415 lastlen = lastlen0 + overlen;
4416 npkt++;
4417 } else { /* full-length "tail" fragment */
4418 lastlen = fraglen + overlen;
4419 }
4420
4421 if (npktp != NULL)
4422 *npktp = npkt;
4423
4424 if (npkt > 1)
4425 firstlen = fraglen + overlen;
4426 else
4427 firstlen = paylen + overlen;
4428
4429 if (debug) {
4430 kprintf("%s: npkt %d firstlen %d lastlen0 %d lastlen %d "
4431 "fraglen %d overlen %d len %d rate %d icflags %08x\n",
4432 __func__, npkt, firstlen, lastlen0, lastlen, fraglen,
4433 overlen, len, rate, icflags);
4434 }
4435
4436 ack = (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
4437 (wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) !=
4438 IEEE80211_FC0_TYPE_CTL);
4439
4440 rc = rtw_compute_duration1(firstlen + hdrlen, ack, icflags, rate, d0);
4441 if (rc == -1)
4442 return rc;
4443
4444 if (npkt <= 1) {
4445 *dn = *d0;
4446 return 0;
4447 }
4448 return rtw_compute_duration1(lastlen + hdrlen, ack, icflags, rate, dn);
4449 }
4450
4451 static int
4452 rtw_get_rssi(struct rtw_softc *sc, uint8_t raw, uint8_t sq)
4453 {
4454 int rssi;
4455
4456 rssi = sc->sc_getrssi(raw, sq);
4457
4458 if (rssi == 0)
4459 rssi = 1;
4460 else if (rssi > 100)
4461 rssi = 100;
4462
4463 if (rssi > (RTW_NOISE_FLOOR + RTW_RSSI_CORR))
4464 rssi -= (RTW_NOISE_FLOOR + RTW_RSSI_CORR);
4465 else
4466 rssi = 0;
4467
4468 return rssi;
4469 }
4470
4471 static int
4472 rtw_maxim_getrssi(uint8_t raw, uint8_t sq __unused)
4473 {
4474 int rssi = raw;
4475
4476 rssi &= 0x7e;
4477 rssi >>= 1;
4478 rssi += 0x42;
4479 if (raw & 0x1)
4480 rssi += 0xa;
4481 rssi &= 0xff;
4482
4483 return rssi;
4484 }
4485
4486 static int
4487 rtw_gct_getrssi(uint8_t raw, uint8_t sq __unused)
4488 {
4489 int rssi = raw;
4490
4491 rssi &= 0x7e;
4492 if ((raw & 0x1) == 0 || rssi > 0x3c)
4493 rssi = 100;
4494 else
4495 rssi = (100 * rssi) / 0x3c;
4496 rssi &= 0xff;
4497
4498 return rssi;
4499 }
4500
4501 static int
4502 rtw_philips_getrssi(uint8_t raw, uint8_t sq)
4503 {
4504 static const uint8_t sq_rssi_map[SA2400_SQ_RSSI_MAP_MAX] =
4505 { SA2400_SQ_RSSI_MAP };
4506
4507 if (sq < SA2400_SQ_RSSI_MAP_MAX - 1) /* NB: -1 is intended */
4508 return sq_rssi_map[sq];
4509
4510 if (sq == 0x80)
4511 return 1;
4512 else
4513 return 0x32;
4514 }
DragonFly vkernel multiprocessor port