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- PHY error bit no longer exists in RX descriptor flags.
[dragonfly/port-amd64.git] / sys / dev / netif / ral / rt2661reg.h
blob304a239f8650cd089ffde6ed318d38858e49117e
1 /*
2 * Copyright (c) 2006
3 * Damien Bergamini <damien.bergamini@free.fr>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: src/sys/dev/ral/rt2661reg.h,v 1.1 2006/03/05 20:36:56 damien Exp $
18 * $DragonFly: src/sys/dev/netif/ral/rt2661reg.h,v 1.8 2007/04/28 14:40:13 sephe Exp $
19 */
20
21 #define RT2661_NOISE_FLOOR -95
22
23 #define RT2661_TX_RING_COUNT 32
24 #define RT2661_MGT_RING_COUNT 32
25 #define RT2661_RX_RING_COUNT 64
26
27 #define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc))
28 #define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4)
29 #define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc))
30 #define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4)
31
32 #define RT2661_MAX_SCATTER 5
33
34 /*
35 * Control and status registers.
36 */
37 #define RT2661_HOST_CMD_CSR 0x0008
38 #define RT2661_MCU_CNTL_CSR 0x000c
39 #define RT2661_SOFT_RESET_CSR 0x0010
40 #define RT2661_MCU_INT_SOURCE_CSR 0x0014
41 #define RT2661_MCU_INT_MASK_CSR 0x0018
42 #define RT2661_PCI_USEC_CSR 0x001c
43 #define RT2661_H2M_MAILBOX_CSR 0x2100
44 #define RT2661_M2H_CMD_DONE_CSR 0x2104
45 #define RT2661_HW_BEACON_BASE0 0x2c00
46 #define RT2661_MAC_CSR0 0x3000
47 #define RT2661_MAC_CSR1 0x3004
48 #define RT2661_MAC_CSR2 0x3008
49 #define RT2661_MAC_CSR3 0x300c
50 #define RT2661_MAC_CSR4 0x3010
51 #define RT2661_MAC_CSR5 0x3014
52 #define RT2661_MAC_CSR6 0x3018
53 #define RT2661_MAC_CSR7 0x301c
54 #define RT2661_MAC_CSR8 0x3020
55 #define RT2661_MAC_CSR9 0x3024
56 #define RT2661_MAC_CSR10 0x3028
57 #define RT2661_MAC_CSR11 0x302c
58 #define RT2661_MAC_CSR12 0x3030
59 #define RT2661_MAC_CSR13 0x3034
60 #define RT2661_MAC_CSR14 0x3038
61 #define RT2661_MAC_CSR15 0x303c
62 #define RT2661_TXRX_CSR0 0x3040
63 #define RT2661_TXRX_CSR1 0x3044
64 #define RT2661_TXRX_CSR2 0x3048
65 #define RT2661_TXRX_CSR3 0x304c
66 #define RT2661_TXRX_CSR4 0x3050
67 #define RT2661_TXRX_CSR5 0x3054
68 #define RT2661_TXRX_CSR6 0x3058
69 #define RT2661_TXRX_CSR7 0x305c
70 #define RT2661_TXRX_CSR8 0x3060
71 #define RT2661_TXRX_CSR9 0x3064
72 #define RT2661_TXRX_CSR10 0x3068
73 #define RT2661_TXRX_CSR11 0x306c
74 #define RT2661_TXRX_CSR12 0x3070
75 #define RT2661_TXRX_CSR13 0x3074
76 #define RT2661_TXRX_CSR14 0x3078
77 #define RT2661_TXRX_CSR15 0x307c
78 #define RT2661_PHY_CSR0 0x3080
79 #define RT2661_PHY_CSR1 0x3084
80 #define RT2661_PHY_CSR2 0x3088
81 #define RT2661_PHY_CSR3 0x308c
82 #define RT2661_PHY_CSR4 0x3090
83 #define RT2661_PHY_CSR5 0x3094
84 #define RT2661_PHY_CSR6 0x3098
85 #define RT2661_PHY_CSR7 0x309c
86 #define RT2661_SEC_CSR0 0x30a0
87 #define RT2661_SEC_CSR1 0x30a4
88 #define RT2661_SEC_CSR2 0x30a8
89 #define RT2661_SEC_CSR3 0x30ac
90 #define RT2661_SEC_CSR4 0x30b0
91 #define RT2661_SEC_CSR5 0x30b4
92 #define RT2661_STA_CSR0 0x30c0
93 #define RT2661_STA_CSR1 0x30c4
94 #define RT2661_STA_CSR2 0x30c8
95 #define RT2661_STA_CSR3 0x30cc
96 #define RT2661_STA_CSR4 0x30d0
97 #define RT2661_AC0_BASE_CSR 0x3400
98 #define RT2661_AC1_BASE_CSR 0x3404
99 #define RT2661_AC2_BASE_CSR 0x3408
100 #define RT2661_AC3_BASE_CSR 0x340c
101 #define RT2661_MGT_BASE_CSR 0x3410
102 #define RT2661_TX_RING_CSR0 0x3418
103 #define RT2661_TX_RING_CSR1 0x341c
104 #define RT2661_AIFSN_CSR 0x3420
105 #define RT2661_CWMIN_CSR 0x3424
106 #define RT2661_CWMAX_CSR 0x3428
107 #define RT2661_TX_DMA_DST_CSR 0x342c
108 #define RT2661_TX_CNTL_CSR 0x3430
109 #define RT2661_LOAD_TX_RING_CSR 0x3434
110 #define RT2661_RX_BASE_CSR 0x3450
111 #define RT2661_RX_RING_CSR 0x3454
112 #define RT2661_RX_CNTL_CSR 0x3458
113 #define RT2661_PCI_CFG_CSR 0x3460
114 #define RT2661_INT_SOURCE_CSR 0x3468
115 #define RT2661_INT_MASK_CSR 0x346c
116 #define RT2661_E2PROM_CSR 0x3470
117 #define RT2661_AC_TXOP_CSR0 0x3474
118 #define RT2661_AC_TXOP_CSR1 0x3478
119 #define RT2661_TEST_MODE_CSR 0x3484
120 #define RT2661_IO_CNTL_CSR 0x3498
121 #define RT2661_MCU_CODE_BASE 0x4000
122
123
124 /* possible flags for register HOST_CMD_CSR */
125 #define RT2661_KICK_CMD (1 << 7)
126 /* Host to MCU (8051) command identifiers */
127 #define RT2661_MCU_CMD_SLEEP 0x30
128 #define RT2661_MCU_CMD_WAKEUP 0x31
129 #define RT2661_MCU_SET_LED 0x50
130 #define RT2661_MCU_SET_RSSI_LED 0x52
131
132 /* possible flags for register MCU_CNTL_CSR */
133 #define RT2661_MCU_SEL (1 << 0)
134 #define RT2661_MCU_RESET (1 << 1)
135 #define RT2661_MCU_READY (1 << 2)
136
137 /* possible flags for register MCU_INT_SOURCE_CSR */
138 #define RT2661_MCU_CMD_DONE 0xff
139 #define RT2661_MCU_WAKEUP (1 << 8)
140 #define RT2661_MCU_BEACON_EXPIRE (1 << 9)
141
142 /* possible flags for register H2M_MAILBOX_CSR */
143 #define RT2661_H2M_BUSY (1 << 24)
144 #define RT2661_TOKEN_NO_INTR 0xff
145
146 /* possible flags for register MAC_CSR5 */
147 #define RT2661_ONE_BSSID 3
148
149 /* possible flags for register TXRX_CSR0 */
150 /* Tx filter flags are in the low 16 bits */
151 #define RT2661_AUTO_TX_SEQ (1 << 15)
152 /* Rx filter flags are in the high 16 bits */
153 #define RT2661_DISABLE_RX (1 << 16)
154 #define RT2661_DROP_CRC_ERROR (1 << 17)
155 #define RT2661_DROP_PHY_ERROR (1 << 18)
156 #define RT2661_DROP_CTL (1 << 19)
157 #define RT2661_DROP_NOT_TO_ME (1 << 20)
158 #define RT2661_DROP_TODS (1 << 21)
159 #define RT2661_DROP_VER_ERROR (1 << 22)
160 #define RT2661_DROP_MULTICAST (1 << 23)
161 #define RT2661_DROP_BROADCAST (1 << 24)
162 #define RT2661_DROP_ACKCTS (1 << 25)
163
164 /* possible flags for register TXRX_CSR4 */
165 #define RT2661_SHORT_PREAMBLE (1 << 18)
166 #define RT2661_MRR_ENABLED (1 << 19)
167 #define RT2661_MRR_CCK_FALLBACK (1 << 22)
168 #define RT2661_LRETRY_LIMIT(n) (((n) & 0xf) << 24)
169 #define RT2661_SRETRY_LIMIT(n) (((n) & 0xf) << 28)
170
171 /* possible flags for register TXRX_CSR9 */
172 #define RT2661_TSF_TICKING (1 << 16)
173 #define RT2661_TSF_MODE(x) (((x) & 0x3) << 17)
174 /* TBTT stands for Target Beacon Transmission Time */
175 #define RT2661_ENABLE_TBTT (1 << 19)
176 #define RT2661_GENERATE_BEACON (1 << 20)
177
178 /* possible flags for register PHY_CSR0 */
179 #define RT2661_PA_PE_2GHZ (1 << 16)
180 #define RT2661_PA_PE_5GHZ (1 << 17)
181
182 /* possible flags for register PHY_CSR3 */
183 #define RT2661_BBP_READ (1 << 15)
184 #define RT2661_BBP_BUSY (1 << 16)
185
186 /* possible flags for register PHY_CSR4 */
187 #define RT2661_RF_21BIT (21 << 24)
188 #define RT2661_RF_BUSY (1 << 31)
189
190 /* possible values for register STA_CSR4 */
191 #define RT2661_TX_STAT_VALID (1 << 0)
192 #define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7)
193 #define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf)
194 #define RT2661_TX_QID(v) (((v) >> 8) & 0xf)
195 #define RT2661_TX_SUCCESS 0
196 #define RT2661_TX_RETRY_FAIL 6
197
198 /* possible flags for register TX_CNTL_CSR */
199 #define RT2661_KICK_MGT (1 << 4)
200
201 /* possible flags for register INT_SOURCE_CSR */
202 #define RT2661_TX_DONE (1 << 0)
203 #define RT2661_RX_DONE (1 << 1)
204 #define RT2661_TX0_DMA_DONE (1 << 16)
205 #define RT2661_TX1_DMA_DONE (1 << 17)
206 #define RT2661_TX2_DMA_DONE (1 << 18)
207 #define RT2661_TX3_DMA_DONE (1 << 19)
208 #define RT2661_MGT_DONE (1 << 20)
209
210 /* possible flags for register E2PROM_CSR */
211 #define RT2661_C (1 << 1)
212 #define RT2661_S (1 << 2)
213 #define RT2661_D (1 << 3)
214 #define RT2661_Q (1 << 4)
215 #define RT2661_93C46 (1 << 5)
216
217 /* Tx descriptor */
218 struct rt2661_tx_desc {
219 uint32_t flags;
220 #define RT2661_TX_BUSY (1 << 0)
221 #define RT2661_TX_VALID (1 << 1)
222 #define RT2661_TX_MORE_FRAG (1 << 2)
223 #define RT2661_TX_NEED_ACK (1 << 3)
224 #define RT2661_TX_TIMESTAMP (1 << 4)
225 #define RT2661_TX_OFDM (1 << 5)
226 #define RT2661_TX_IFS (1 << 6)
227 #define RT2661_TX_LONG_RETRY (1 << 7)
228 #define RT2661_TX_BURST (1 << 28)
229
230 uint16_t wme;
231 #define RT2661_QID(v) (v)
232 #define RT2661_AIFSN(v) ((v) << 4)
233 #define RT2661_LOGCWMIN(v) ((v) << 8)
234 #define RT2661_LOGCWMAX(v) ((v) << 12)
235
236 uint16_t xflags;
237 #define RT2661_TX_HWSEQ (1 << 12)
238
239 uint8_t plcp_signal;
240 uint8_t plcp_service;
241 #define RT2661_PLCP_LENGEXT 0x80
242
243 uint8_t plcp_length_lo;
244 uint8_t plcp_length_hi;
245
246 uint32_t iv;
247 uint32_t eiv;
248
249 uint8_t offset;
250 uint8_t qid;
251 #define RT2661_QID_MGT 13
252
253 uint8_t txpower;
254 #define RT2661_DEFAULT_TXPOWER 0
255
256 uint8_t reserved1;
257
258 uint32_t addr[RT2661_MAX_SCATTER];
259 uint16_t len[RT2661_MAX_SCATTER];
260
261 uint16_t reserved2;
262 } __packed;
263
264 /* Rx descriptor */
265 struct rt2661_rx_desc {
266 uint32_t flags;
267 #define RT2661_RX_BUSY (1 << 0)
268 #define RT2661_RX_DROP (1 << 1)
269 #define RT2661_RX_CRC_ERROR (1 << 6)
270 #define RT2661_RX_OFDM (1 << 7)
271 #define RT2661_RX_CIPHER_MASK 0x00000300
272
273 uint8_t rate;
274 uint8_t rssi;
275 uint8_t reserved1;
276 uint8_t offset;
277 uint32_t iv;
278 uint32_t eiv;
279 uint32_t reserved2;
280 uint32_t physaddr;
281 uint32_t reserved3[10];
282 } __packed;
283
284 #define RAL_RF1 0
285 #define RAL_RF2 2
286 #define RAL_RF3 1
287 #define RAL_RF4 3
288
289 /* dual-band RF */
290 #define RT2661_RF_5225 1
291 #define RT2661_RF_5325 2
292 /* single-band RF */
293 #define RT2661_RF_2527 3
294 #define RT2661_RF_2529 4
295
296 #define RT2661_BBP_2661D 0x2661d
297
298 #define RT2661_RX_DESC_BACK 4
299
300 #define RT2661_SMART_MODE (1 << 0)
301
302 #define RT2661_BBPR94_DEFAULT 6
303
304 #define RT2661_SHIFT_D 3
305 #define RT2661_SHIFT_Q 4
306
307 #define RT2661_EEPROM_MAC01 0x02
308 #define RT2661_EEPROM_MAC23 0x03
309 #define RT2661_EEPROM_MAC45 0x04
310 #define RT2661_EEPROM_ANTENNA 0x10
311 #define RT2661_EEPROM_CONFIG2 0x11
312 #define RT2661_EEPROM_BBP_BASE 0x13
313 #define RT2661_EEPROM_TXPOWER_2GHZ 0x23
314 #define RT2661_EEPROM_FREQ_OFFSET 0x2f
315 #define RT2661_EEPROM_LED_OFFSET 0x30
316 #define RT2661_EEPROM_TXPOWER_5GHZ 0x31
317 #define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d
318 #define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e
319
320 #define RT2661_EE_LED_RDYG 0x01
321 #define RT2661_EE_LED_RDYA 0x02
322 #define RT2661_EE_LED_ACT 0x04
323 #define RT2661_EE_LED_GPIO0 0x08
324 #define RT2661_EE_LED_GPIO1 0x10
325 #define RT2661_EE_LED_GPIO2 0x20
326 #define RT2661_EE_LED_GPIO3 0x40
327 #define RT2661_EE_LED_GPIO4 0x80
328 #define RT2661_EE_LED_MODE_SHIFT 8
329 #define RT2661_EE_LED_MODE_MASK 0x1f
330
331 #define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
332
333 #define RT2661_MCU_LED_RF (1 << 5)
334 #define RT2661_MCU_LED_LINKG (1 << 6)
335 #define RT2661_MCU_LED_LINKA (1 << 7)
336 #define RT2661_MCU_LED_GPIO0 (1 << 8)
337 #define RT2661_MCU_LED_GPIO1 (1 << 9)
338 #define RT2661_MCU_LED_GPIO2 (1 << 10)
339 #define RT2661_MCU_LED_GPIO3 (1 << 11)
340 #define RT2661_MCU_LED_GPIO4 (1 << 12)
341 #define RT2661_MCU_LED_ACT (1 << 13)
342 #define RT2661_MCU_LED_RDYG (1 << 14)
343 #define RT2661_MCU_LED_RDYA (1 << 15)
344
345 #define RT2661_MCU_LED_DEFAULT \
346 (RT2661_MCU_LED_GPIO0 | RT2661_MCU_LED_GPIO1 | RT2661_MCU_LED_GPIO2 | \
347 RT2661_MCU_LED_GPIO3 | RT2661_MCU_LED_GPIO4 | RT2661_MCU_LED_ACT | \
348 RT2661_MCU_LED_RDYG | RT2661_MCU_LED_RDYA)
349
350 #define RT2661_TXPOWER_DEFAULT 5
351 #define RT2661_TXPOWER_MAX 36
352
353 /*
354 * control and status registers access macros
355 */
356 #define RAL_READ(sc, reg) \
357 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
358
359 #define RAL_READ_REGION_4(sc, offset, datap, count) \
360 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
361 (datap), (count))
362
363 #define RAL_WRITE(sc, reg, val) \
364 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
365
366 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \
367 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \
368 (datap), (count))
369
370 /*
371 * EEPROM access macro
372 */
373 #define RT2661_EEPROM_CTL(sc, val) do { \
374 RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
375 DELAY(RT2661_EEPROM_DELAY); \
376 } while (/* CONSTCOND */0)
377
378 /*
379 * Default values for MAC registers; values taken from the reference driver.
380 */
381 #define RT2661_DEF_MAC \
382 { RT2661_TXRX_CSR0, 0x0000b032 }, \
383 { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \
384 { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \
385 { RT2661_TXRX_CSR3, 0x00858687 }, \
386 { RT2661_TXRX_CSR7, 0x2e31353b }, \
387 { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \
388 { RT2661_TXRX_CSR15, 0x0000000f }, \
389 { RT2661_MAC_CSR6, 0x00000fff }, \
390 { RT2661_MAC_CSR8, 0x016c030a }, \
391 { RT2661_MAC_CSR10, 0x00000718 }, \
392 { RT2661_MAC_CSR12, 0x00000004 }, \
393 { RT2661_MAC_CSR13, 0x0000e000 }, \
394 { RT2661_SEC_CSR0, 0x00000000 }, \
395 { RT2661_SEC_CSR1, 0x00000000 }, \
396 { RT2661_SEC_CSR5, 0x00000000 }, \
397 { RT2661_PHY_CSR1, 0x000023b0 }, \
398 { RT2661_PHY_CSR5, 0x060a100c }, \
399 { RT2661_PHY_CSR6, 0x00080606 }, \
400 { RT2661_PHY_CSR7, 0x00000a08 }, \
401 { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \
402 { RT2661_AIFSN_CSR, 0x00002273 }, \
403 { RT2661_CWMIN_CSR, 0x00002344 }, \
404 { RT2661_CWMAX_CSR, 0x000034aa }, \
405 { RT2661_TEST_MODE_CSR, 0x00000200 }, \
406 { RT2661_M2H_CMD_DONE_CSR, 0xffffffff }
407
408 /*
409 * Default values for BBP registers; values taken from the reference driver.
410 */
411 #define RT2661_DEF_BBP \
412 { 3, 0x00 }, \
413 { 15, 0x30 }, \
414 { 17, 0x20 }, \
415 { 21, 0xc8 }, \
416 { 22, 0x38 }, \
417 { 23, 0x06 }, \
418 { 24, 0xfe }, \
419 { 25, 0x0a }, \
420 { 26, 0x0d }, \
421 { 34, 0x12 }, \
422 { 37, 0x07 }, \
423 { 39, 0xf8 }, \
424 { 41, 0x60 }, \
425 { 53, 0x10 }, \
426 { 54, 0x18 }, \
427 { 60, 0x10 }, \
428 { 61, 0x04 }, \
429 { 62, 0x04 }, \
430 { 75, 0xfe }, \
431 { 86, 0xfe }, \
432 { 88, 0xfe }, \
433 { 90, 0x0f }, \
434 { 99, 0x00 }, \
435 { 102, 0x16 }, \
436 { 107, 0x04 }
437
438 /*
439 * Default settings for RF registers; values taken from the reference driver.
440 */
441 #define RT2661_RF5225_1 \
442 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
443 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
444 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
445 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
446 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
447 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
448 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
449 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
450 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
451 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
452 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
453 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
454 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
455 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
456 \
457 { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \
458 { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \
459 { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \
460 { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \
461 { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \
462 { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \
463 { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \
464 { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \
465 \
466 { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \
467 { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \
468 { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \
469 { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \
470 { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \
471 { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \
472 { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \
473 { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \
474 { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \
475 { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \
476 { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \
477 \
478 { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \
479 { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \
480 { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \
481 { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \
482 { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
483
484 #define RT2661_RF5225_2 \
485 { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
486 { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
487 { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
488 { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
489 { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
490 { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
491 { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
492 { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
493 { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
494 { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
495 { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
496 { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
497 { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
498 { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
499 \
500 { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \
501 { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \
502 { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \
503 { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \
504 { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \
505 { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \
506 { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \
507 { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \
508 \
509 { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \
510 { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \
511 { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \
512 { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \
513 { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \
514 { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \
515 { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \
516 { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \
517 { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \
518 { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \
519 { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \
520 \
521 { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \
522 { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \
523 { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \
524 { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \
525 { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }
A repo for keeping AMD64 port code before merging with the master