?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
When performing our register test, be careful
[dragonfly/port-amd64.git] / sys / dev / disk / aic7xxx / aic7xxx_pci.c
blobb74a594de38bacff4542ca61a6e84ef077c1d4f3
1 /*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#72 $
43 *
44 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.31 2003/09/25 23:36:41 scottl Exp $
45 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.9 2007/07/05 05:17:39 pavalos Exp $
46 */
47
48 #ifdef __linux__
49 #include "aic7xxx_osm.h"
50 #include "aic7xxx_inline.h"
51 #include "aic7xxx_93cx6.h"
52 #else
53 #include "aic7xxx_osm.h"
54 #include "aic7xxx_inline.h"
55 #include "aic7xxx_93cx6.h"
56 #endif
57
58 #ifdef AHC_PCI_CONFIG
59
60 #define AHC_PCI_IOADDR PCIR_BAR(0) /* I/O Address */
61 #define AHC_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
62
63 static __inline uint64_t
64 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
65 {
66 uint64_t id;
67
68 id = subvendor
69 | (subdevice << 16)
70 | ((uint64_t)vendor << 32)
71 | ((uint64_t)device << 48);
72
73 return (id);
74 }
75
76 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
77 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
78 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
79 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
80 #define ID_9005_SISL_ID 0x0005900500000000ull
81 #define ID_AIC7850 0x5078900400000000ull
82 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
83 #define ID_AIC7855 0x5578900400000000ull
84 #define ID_AIC7859 0x3860900400000000ull
85 #define ID_AHA_2930CU 0x3860900438699004ull
86 #define ID_AIC7860 0x6078900400000000ull
87 #define ID_AIC7860C 0x6078900478609004ull
88 #define ID_AHA_1480A 0x6075900400000000ull
89 #define ID_AHA_2940AU_0 0x6178900400000000ull
90 #define ID_AHA_2940AU_1 0x6178900478619004ull
91 #define ID_AHA_2940AU_CN 0x2178900478219004ull
92 #define ID_AHA_2930C_VAR 0x6038900438689004ull
93
94 #define ID_AIC7870 0x7078900400000000ull
95 #define ID_AHA_2940 0x7178900400000000ull
96 #define ID_AHA_3940 0x7278900400000000ull
97 #define ID_AHA_398X 0x7378900400000000ull
98 #define ID_AHA_2944 0x7478900400000000ull
99 #define ID_AHA_3944 0x7578900400000000ull
100 #define ID_AHA_4944 0x7678900400000000ull
101
102 #define ID_AIC7880 0x8078900400000000ull
103 #define ID_AIC7880_B 0x8078900478809004ull
104 #define ID_AHA_2940U 0x8178900400000000ull
105 #define ID_AHA_3940U 0x8278900400000000ull
106 #define ID_AHA_2944U 0x8478900400000000ull
107 #define ID_AHA_3944U 0x8578900400000000ull
108 #define ID_AHA_398XU 0x8378900400000000ull
109 #define ID_AHA_4944U 0x8678900400000000ull
110 #define ID_AHA_2940UB 0x8178900478819004ull
111 #define ID_AHA_2930U 0x8878900478889004ull
112 #define ID_AHA_2940U_PRO 0x8778900478879004ull
113 #define ID_AHA_2940U_CN 0x0078900478009004ull
114
115 #define ID_AIC7895 0x7895900478959004ull
116 #define ID_AIC7895_ARO 0x7890900478939004ull
117 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
118 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
119 #define ID_AHA_3940AU 0x7895900478929004ull
120 #define ID_AHA_3944AU 0x7895900478949004ull
121
122 #define ID_AIC7890 0x001F9005000F9005ull
123 #define ID_AIC7890_ARO 0x00139005000F9005ull
124 #define ID_AAA_131U2 0x0013900500039005ull
125 #define ID_AHA_2930U2 0x0011900501819005ull
126 #define ID_AHA_2940U2B 0x00109005A1009005ull
127 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
128 #define ID_AHA_2940U2 0x00109005A1809005ull
129 #define ID_AHA_2950U2B 0x00109005E1009005ull
130
131 #define ID_AIC7892 0x008F9005FFFF9005ull
132 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
133 #define ID_AHA_29160 0x00809005E2A09005ull
134 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
135 #define ID_AHA_29160N 0x0080900562A09005ull
136 #define ID_AHA_29160C 0x0080900562209005ull
137 #define ID_AHA_29160B 0x00809005E2209005ull
138 #define ID_AHA_19160B 0x0081900562A19005ull
139
140 #define ID_AIC7896 0x005F9005FFFF9005ull
141 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
142 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
143 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
144 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
145 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
146
147 #define ID_AIC7899 0x00CF9005FFFF9005ull
148 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
149 #define ID_AHA_3960D 0x00C09005F6209005ull
150 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
151
152 #define ID_AIC7810 0x1078900400000000ull
153 #define ID_AIC7815 0x7815900400000000ull
154
155 #define DEVID_9005_TYPE(id) ((id) & 0xF)
156 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
157 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
158 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
159 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
160
161 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
162 #define DEVID_9005_MAXRATE_U160 0x0
163 #define DEVID_9005_MAXRATE_ULTRA2 0x1
164 #define DEVID_9005_MAXRATE_ULTRA 0x2
165 #define DEVID_9005_MAXRATE_FAST 0x3
166
167 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
168
169 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
170 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
171
172 #define SUBID_9005_TYPE(id) ((id) & 0xF)
173 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
174 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
175 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
176 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
177
178 #define SUBID_9005_TYPE_KNOWN(id) \
179 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
180 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
181 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
182 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
183
184 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
185 #define SUBID_9005_MAXRATE_ULTRA2 0x0
186 #define SUBID_9005_MAXRATE_ULTRA 0x1
187 #define SUBID_9005_MAXRATE_U160 0x2
188 #define SUBID_9005_MAXRATE_RESERVED 0x3
189
190 #define SUBID_9005_SEEPTYPE(id) \
191 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
192 ? ((id) & 0xC0) >> 6 \
193 : ((id) & 0x300) >> 8)
194 #define SUBID_9005_SEEPTYPE_NONE 0x0
195 #define SUBID_9005_SEEPTYPE_1K 0x1
196 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
197 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
198 #define SUBID_9005_AUTOTERM(id) \
199 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
200 ? (((id) & 0x400) >> 10) == 0 \
201 : (((id) & 0x40) >> 6) == 0)
202
203 #define SUBID_9005_NUMCHAN(id) \
204 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
205 ? ((id) & 0x300) >> 8 \
206 : ((id) & 0xC00) >> 10)
207
208 #define SUBID_9005_LEGACYCONN(id) \
209 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
210 ? 0 \
211 : ((id) & 0x80) >> 7)
212
213 #define SUBID_9005_MFUNCENB(id) \
214 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
215 ? ((id) & 0x800) >> 11 \
216 : ((id) & 0x1000) >> 12)
217 /*
218 * Informational only. Should use chip register to be
219 * certain, but may be use in identification strings.
220 */
221 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
222 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
223 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
224
225 static ahc_device_setup_t ahc_aic785X_setup;
226 static ahc_device_setup_t ahc_aic7860_setup;
227 static ahc_device_setup_t ahc_apa1480_setup;
228 static ahc_device_setup_t ahc_aic7870_setup;
229 static ahc_device_setup_t ahc_aha394X_setup;
230 static ahc_device_setup_t ahc_aha494X_setup;
231 static ahc_device_setup_t ahc_aha398X_setup;
232 static ahc_device_setup_t ahc_aic7880_setup;
233 static ahc_device_setup_t ahc_aha2940Pro_setup;
234 static ahc_device_setup_t ahc_aha394XU_setup;
235 static ahc_device_setup_t ahc_aha398XU_setup;
236 static ahc_device_setup_t ahc_aic7890_setup;
237 static ahc_device_setup_t ahc_aic7892_setup;
238 static ahc_device_setup_t ahc_aic7895_setup;
239 static ahc_device_setup_t ahc_aic7896_setup;
240 static ahc_device_setup_t ahc_aic7899_setup;
241 static ahc_device_setup_t ahc_aha29160C_setup;
242 static ahc_device_setup_t ahc_raid_setup;
243 static ahc_device_setup_t ahc_aha394XX_setup;
244 static ahc_device_setup_t ahc_aha494XX_setup;
245 static ahc_device_setup_t ahc_aha398XX_setup;
246
247 struct ahc_pci_identity ahc_pci_ident_table [] =
248 {
249 /* aic7850 based controllers */
250 {
251 ID_AHA_2902_04_10_15_20C_30C,
252 ID_ALL_MASK,
253 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
254 ahc_aic785X_setup
255 },
256 /* aic7860 based controllers */
257 {
258 ID_AHA_2930CU,
259 ID_ALL_MASK,
260 "Adaptec 2930CU SCSI adapter",
261 ahc_aic7860_setup
262 },
263 {
264 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
265 ID_DEV_VENDOR_MASK,
266 "Adaptec 1480A Ultra SCSI adapter",
267 ahc_apa1480_setup
268 },
269 {
270 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
271 ID_DEV_VENDOR_MASK,
272 "Adaptec 2940A Ultra SCSI adapter",
273 ahc_aic7860_setup
274 },
275 {
276 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
277 ID_DEV_VENDOR_MASK,
278 "Adaptec 2940A/CN Ultra SCSI adapter",
279 ahc_aic7860_setup
280 },
281 {
282 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
283 ID_DEV_VENDOR_MASK,
284 "Adaptec 2930C Ultra SCSI adapter (VAR)",
285 ahc_aic7860_setup
286 },
287 /* aic7870 based controllers */
288 {
289 ID_AHA_2940,
290 ID_ALL_MASK,
291 "Adaptec 2940 SCSI adapter",
292 ahc_aic7870_setup
293 },
294 {
295 ID_AHA_3940,
296 ID_ALL_MASK,
297 "Adaptec 3940 SCSI adapter",
298 ahc_aha394X_setup
299 },
300 {
301 ID_AHA_398X,
302 ID_ALL_MASK,
303 "Adaptec 398X SCSI RAID adapter",
304 ahc_aha398X_setup
305 },
306 {
307 ID_AHA_2944,
308 ID_ALL_MASK,
309 "Adaptec 2944 SCSI adapter",
310 ahc_aic7870_setup
311 },
312 {
313 ID_AHA_3944,
314 ID_ALL_MASK,
315 "Adaptec 3944 SCSI adapter",
316 ahc_aha394X_setup
317 },
318 {
319 ID_AHA_4944,
320 ID_ALL_MASK,
321 "Adaptec 4944 SCSI adapter",
322 ahc_aha494X_setup
323 },
324 /* aic7880 based controllers */
325 {
326 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
327 ID_DEV_VENDOR_MASK,
328 "Adaptec 2940 Ultra SCSI adapter",
329 ahc_aic7880_setup
330 },
331 {
332 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
333 ID_DEV_VENDOR_MASK,
334 "Adaptec 3940 Ultra SCSI adapter",
335 ahc_aha394XU_setup
336 },
337 {
338 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
339 ID_DEV_VENDOR_MASK,
340 "Adaptec 2944 Ultra SCSI adapter",
341 ahc_aic7880_setup
342 },
343 {
344 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
345 ID_DEV_VENDOR_MASK,
346 "Adaptec 3944 Ultra SCSI adapter",
347 ahc_aha394XU_setup
348 },
349 {
350 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
351 ID_DEV_VENDOR_MASK,
352 "Adaptec 398X Ultra SCSI RAID adapter",
353 ahc_aha398XU_setup
354 },
355 {
356 /*
357 * XXX Don't know the slot numbers
358 * so we can't identify channels
359 */
360 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
361 ID_DEV_VENDOR_MASK,
362 "Adaptec 4944 Ultra SCSI adapter",
363 ahc_aic7880_setup
364 },
365 {
366 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
367 ID_DEV_VENDOR_MASK,
368 "Adaptec 2930 Ultra SCSI adapter",
369 ahc_aic7880_setup
370 },
371 {
372 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
373 ID_DEV_VENDOR_MASK,
374 "Adaptec 2940 Pro Ultra SCSI adapter",
375 ahc_aha2940Pro_setup
376 },
377 {
378 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
379 ID_DEV_VENDOR_MASK,
380 "Adaptec 2940/CN Ultra SCSI adapter",
381 ahc_aic7880_setup
382 },
383 /* Ignore all SISL (AAC on MB) based controllers. */
384 {
385 ID_9005_SISL_ID,
386 ID_9005_SISL_MASK,
387 NULL,
388 NULL
389 },
390 /* aic7890 based controllers */
391 {
392 ID_AHA_2930U2,
393 ID_ALL_MASK,
394 "Adaptec 2930 Ultra2 SCSI adapter",
395 ahc_aic7890_setup
396 },
397 {
398 ID_AHA_2940U2B,
399 ID_ALL_MASK,
400 "Adaptec 2940B Ultra2 SCSI adapter",
401 ahc_aic7890_setup
402 },
403 {
404 ID_AHA_2940U2_OEM,
405 ID_ALL_MASK,
406 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
407 ahc_aic7890_setup
408 },
409 {
410 ID_AHA_2940U2,
411 ID_ALL_MASK,
412 "Adaptec 2940 Ultra2 SCSI adapter",
413 ahc_aic7890_setup
414 },
415 {
416 ID_AHA_2950U2B,
417 ID_ALL_MASK,
418 "Adaptec 2950 Ultra2 SCSI adapter",
419 ahc_aic7890_setup
420 },
421 {
422 ID_AIC7890_ARO,
423 ID_ALL_MASK,
424 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
425 ahc_aic7890_setup
426 },
427 {
428 ID_AAA_131U2,
429 ID_ALL_MASK,
430 "Adaptec AAA-131 Ultra2 RAID adapter",
431 ahc_aic7890_setup
432 },
433 /* aic7892 based controllers */
434 {
435 ID_AHA_29160,
436 ID_ALL_MASK,
437 "Adaptec 29160 Ultra160 SCSI adapter",
438 ahc_aic7892_setup
439 },
440 {
441 ID_AHA_29160_CPQ,
442 ID_ALL_MASK,
443 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
444 ahc_aic7892_setup
445 },
446 {
447 ID_AHA_29160N,
448 ID_ALL_MASK,
449 "Adaptec 29160N Ultra160 SCSI adapter",
450 ahc_aic7892_setup
451 },
452 {
453 ID_AHA_29160C,
454 ID_ALL_MASK,
455 "Adaptec 29160C Ultra160 SCSI adapter",
456 ahc_aha29160C_setup
457 },
458 {
459 ID_AHA_29160B,
460 ID_ALL_MASK,
461 "Adaptec 29160B Ultra160 SCSI adapter",
462 ahc_aic7892_setup
463 },
464 {
465 ID_AHA_19160B,
466 ID_ALL_MASK,
467 "Adaptec 19160B Ultra160 SCSI adapter",
468 ahc_aic7892_setup
469 },
470 {
471 ID_AIC7892_ARO,
472 ID_ALL_MASK,
473 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
474 ahc_aic7892_setup
475 },
476 /* aic7895 based controllers */
477 {
478 ID_AHA_2940U_DUAL,
479 ID_ALL_MASK,
480 "Adaptec 2940/DUAL Ultra SCSI adapter",
481 ahc_aic7895_setup
482 },
483 {
484 ID_AHA_3940AU,
485 ID_ALL_MASK,
486 "Adaptec 3940A Ultra SCSI adapter",
487 ahc_aic7895_setup
488 },
489 {
490 ID_AHA_3944AU,
491 ID_ALL_MASK,
492 "Adaptec 3944A Ultra SCSI adapter",
493 ahc_aic7895_setup
494 },
495 {
496 ID_AIC7895_ARO,
497 ID_AIC7895_ARO_MASK,
498 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
499 ahc_aic7895_setup
500 },
501 /* aic7896/97 based controllers */
502 {
503 ID_AHA_3950U2B_0,
504 ID_ALL_MASK,
505 "Adaptec 3950B Ultra2 SCSI adapter",
506 ahc_aic7896_setup
507 },
508 {
509 ID_AHA_3950U2B_1,
510 ID_ALL_MASK,
511 "Adaptec 3950B Ultra2 SCSI adapter",
512 ahc_aic7896_setup
513 },
514 {
515 ID_AHA_3950U2D_0,
516 ID_ALL_MASK,
517 "Adaptec 3950D Ultra2 SCSI adapter",
518 ahc_aic7896_setup
519 },
520 {
521 ID_AHA_3950U2D_1,
522 ID_ALL_MASK,
523 "Adaptec 3950D Ultra2 SCSI adapter",
524 ahc_aic7896_setup
525 },
526 {
527 ID_AIC7896_ARO,
528 ID_ALL_MASK,
529 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
530 ahc_aic7896_setup
531 },
532 /* aic7899 based controllers */
533 {
534 ID_AHA_3960D,
535 ID_ALL_MASK,
536 "Adaptec 3960D Ultra160 SCSI adapter",
537 ahc_aic7899_setup
538 },
539 {
540 ID_AHA_3960D_CPQ,
541 ID_ALL_MASK,
542 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
543 ahc_aic7899_setup
544 },
545 {
546 ID_AIC7899_ARO,
547 ID_ALL_MASK,
548 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
549 ahc_aic7899_setup
550 },
551 /* Generic chip probes for devices we don't know 'exactly' */
552 {
553 ID_AIC7850 & ID_DEV_VENDOR_MASK,
554 ID_DEV_VENDOR_MASK,
555 "Adaptec aic7850 SCSI adapter",
556 ahc_aic785X_setup
557 },
558 {
559 ID_AIC7855 & ID_DEV_VENDOR_MASK,
560 ID_DEV_VENDOR_MASK,
561 "Adaptec aic7855 SCSI adapter",
562 ahc_aic785X_setup
563 },
564 {
565 ID_AIC7859 & ID_DEV_VENDOR_MASK,
566 ID_DEV_VENDOR_MASK,
567 "Adaptec aic7859 SCSI adapter",
568 ahc_aic7860_setup
569 },
570 {
571 ID_AIC7860 & ID_DEV_VENDOR_MASK,
572 ID_DEV_VENDOR_MASK,
573 "Adaptec aic7860 Ultra SCSI adapter",
574 ahc_aic7860_setup
575 },
576 {
577 ID_AIC7870 & ID_DEV_VENDOR_MASK,
578 ID_DEV_VENDOR_MASK,
579 "Adaptec aic7870 SCSI adapter",
580 ahc_aic7870_setup
581 },
582 {
583 ID_AIC7880 & ID_DEV_VENDOR_MASK,
584 ID_DEV_VENDOR_MASK,
585 "Adaptec aic7880 Ultra SCSI adapter",
586 ahc_aic7880_setup
587 },
588 {
589 ID_AIC7890 & ID_9005_GENERIC_MASK,
590 ID_9005_GENERIC_MASK,
591 "Adaptec aic7890/91 Ultra2 SCSI adapter",
592 ahc_aic7890_setup
593 },
594 {
595 ID_AIC7892 & ID_9005_GENERIC_MASK,
596 ID_9005_GENERIC_MASK,
597 "Adaptec aic7892 Ultra160 SCSI adapter",
598 ahc_aic7892_setup
599 },
600 {
601 ID_AIC7895 & ID_DEV_VENDOR_MASK,
602 ID_DEV_VENDOR_MASK,
603 "Adaptec aic7895 Ultra SCSI adapter",
604 ahc_aic7895_setup
605 },
606 {
607 ID_AIC7896 & ID_9005_GENERIC_MASK,
608 ID_9005_GENERIC_MASK,
609 "Adaptec aic7896/97 Ultra2 SCSI adapter",
610 ahc_aic7896_setup
611 },
612 {
613 ID_AIC7899 & ID_9005_GENERIC_MASK,
614 ID_9005_GENERIC_MASK,
615 "Adaptec aic7899 Ultra160 SCSI adapter",
616 ahc_aic7899_setup
617 },
618 {
619 ID_AIC7810 & ID_DEV_VENDOR_MASK,
620 ID_DEV_VENDOR_MASK,
621 "Adaptec aic7810 RAID memory controller",
622 ahc_raid_setup
623 },
624 {
625 ID_AIC7815 & ID_DEV_VENDOR_MASK,
626 ID_DEV_VENDOR_MASK,
627 "Adaptec aic7815 RAID memory controller",
628 ahc_raid_setup
629 }
630 };
631
632 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
633
634 #define AHC_394X_SLOT_CHANNEL_A 4
635 #define AHC_394X_SLOT_CHANNEL_B 5
636
637 #define AHC_398X_SLOT_CHANNEL_A 4
638 #define AHC_398X_SLOT_CHANNEL_B 8
639 #define AHC_398X_SLOT_CHANNEL_C 12
640
641 #define AHC_494X_SLOT_CHANNEL_A 4
642 #define AHC_494X_SLOT_CHANNEL_B 5
643 #define AHC_494X_SLOT_CHANNEL_C 6
644 #define AHC_494X_SLOT_CHANNEL_D 7
645
646 #define DEVCONFIG 0x40
647 #define PCIERRGENDIS 0x80000000ul
648 #define SCBSIZE32 0x00010000ul /* aic789X only */
649 #define REXTVALID 0x00001000ul /* ultra cards only */
650 #define MPORTMODE 0x00000400ul /* aic7870+ only */
651 #define RAMPSM 0x00000200ul /* aic7870+ only */
652 #define VOLSENSE 0x00000100ul
653 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
654 #define SCBRAMSEL 0x00000080ul
655 #define MRDCEN 0x00000040ul
656 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
657 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
658 #define BERREN 0x00000008ul
659 #define DACEN 0x00000004ul
660 #define STPWLEVEL 0x00000002ul
661 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
662
663 #define CSIZE_LATTIME 0x0c
664 #define CACHESIZE 0x0000003ful /* only 5 bits */
665 #define LATTIME 0x0000ff00ul
666
667 /* PCI STATUS definitions */
668 #define DPE 0x80
669 #define SSE 0x40
670 #define RMA 0x20
671 #define RTA 0x10
672 #define STA 0x08
673 #define DPR 0x01
674
675 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
676 uint16_t subvendor, uint16_t subdevice);
677 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
678 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
679 int pcheck, int fast, int large);
680 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
681 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
682 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
683 struct seeprom_config *sc);
684 static void configure_termination(struct ahc_softc *ahc,
685 struct seeprom_descriptor *sd,
686 u_int adapter_control,
687 u_int *sxfrctl1);
688
689 static void ahc_new_term_detect(struct ahc_softc *ahc,
690 int *enableSEC_low,
691 int *enableSEC_high,
692 int *enablePRI_low,
693 int *enablePRI_high,
694 int *eeprom_present);
695 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
696 int *internal68_present,
697 int *externalcable_present,
698 int *eeprom_present);
699 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
700 int *externalcable_present,
701 int *eeprom_present);
702 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
703 static uint8_t read_brdctl(struct ahc_softc *ahc);
704 static void ahc_pci_intr(struct ahc_softc *ahc);
705 static int ahc_pci_chip_init(struct ahc_softc *ahc);
706 static int ahc_pci_suspend(struct ahc_softc *ahc);
707 static int ahc_pci_resume(struct ahc_softc *ahc);
708
709 static int
710 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
711 uint16_t subdevice, uint16_t subvendor)
712 {
713 int result;
714
715 /* Default to invalid. */
716 result = 0;
717 if (vendor == 0x9005
718 && subvendor == 0x9005
719 && subdevice != device
720 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
721
722 switch (SUBID_9005_TYPE(subdevice)) {
723 case SUBID_9005_TYPE_MB:
724 break;
725 case SUBID_9005_TYPE_CARD:
726 case SUBID_9005_TYPE_LCCARD:
727 /*
728 * Currently only trust Adaptec cards to
729 * get the sub device info correct.
730 */
731 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
732 result = 1;
733 break;
734 case SUBID_9005_TYPE_RAID:
735 break;
736 default:
737 break;
738 }
739 }
740 return (result);
741 }
742
743 struct ahc_pci_identity *
744 ahc_find_pci_device(ahc_dev_softc_t pci)
745 {
746 uint64_t full_id;
747 uint16_t device;
748 uint16_t vendor;
749 uint16_t subdevice;
750 uint16_t subvendor;
751 struct ahc_pci_identity *entry;
752 u_int i;
753
754 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
755 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
756 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
757 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
758 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
759
760 /*
761 * If the second function is not hooked up, ignore it.
762 * Unfortunately, not all MB vendors implement the
763 * subdevice ID as per the Adaptec spec, so do our best
764 * to sanity check it prior to accepting the subdevice
765 * ID as valid.
766 */
767 if (ahc_get_pci_function(pci) > 0
768 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
769 && SUBID_9005_MFUNCENB(subdevice) == 0)
770 return (NULL);
771
772 for (i = 0; i < ahc_num_pci_devs; i++) {
773 entry = &ahc_pci_ident_table[i];
774 if (entry->full_id == (full_id & entry->id_mask)) {
775 /* Honor exclusion entries. */
776 if (entry->name == NULL)
777 return (NULL);
778 return (entry);
779 }
780 }
781 return (NULL);
782 }
783
784 int
785 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
786 {
787 u_int command;
788 u_int our_id;
789 u_int sxfrctl1;
790 u_int scsiseq;
791 u_int dscommand0;
792 uint32_t devconfig;
793 int error;
794 uint8_t sblkctl;
795
796 our_id = 0;
797 error = entry->setup(ahc);
798 if (error != 0)
799 return (error);
800 ahc->chip |= AHC_PCI;
801 ahc->description = entry->name;
802
803 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
804
805 error = ahc_pci_map_registers(ahc);
806 if (error != 0)
807 return (error);
808
809 /*
810 * Before we continue probing the card, ensure that
811 * its interrupts are *disabled*. We don't want
812 * a misstep to hang the machine in an interrupt
813 * storm.
814 */
815 ahc_intr_enable(ahc, FALSE);
816
817 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
818
819 /*
820 * If we need to support high memory, enable dual
821 * address cycles. This bit must be set to enable
822 * high address bit generation even if we are on a
823 * 64bit bus (PCI64BIT set in devconfig).
824 */
825 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
826
827 if (bootverbose)
828 kprintf("%s: Enabling 39Bit Addressing\n",
829 ahc_name(ahc));
830 devconfig |= DACEN;
831 }
832
833 /* Ensure that pci error generation, a test feature, is disabled. */
834 devconfig |= PCIERRGENDIS;
835
836 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
837
838 /* Ensure busmastering is enabled */
839 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
840 command |= PCIM_CMD_BUSMASTEREN;
841
842 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
843
844 /* On all PCI adapters, we allow SCB paging */
845 ahc->flags |= AHC_PAGESCBS;
846
847 error = ahc_softc_init(ahc);
848 if (error != 0)
849 return (error);
850
851 /*
852 * Disable PCI parity error checking. Users typically
853 * do this to work around broken PCI chipsets that get
854 * the parity timing wrong and thus generate lots of spurious
855 * errors. The chip only allows us to disable *all* parity
856 * error reporting when doing this, so CIO bus, scb ram, and
857 * scratch ram parity errors will be ignored too.
858 */
859 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
860 ahc->seqctl |= FAILDIS;
861
862 ahc->bus_intr = ahc_pci_intr;
863 ahc->bus_chip_init = ahc_pci_chip_init;
864 ahc->bus_suspend = ahc_pci_suspend;
865 ahc->bus_resume = ahc_pci_resume;
866
867 /* Remeber how the card was setup in case there is no SEEPROM */
868 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
869 ahc_pause(ahc);
870 if ((ahc->features & AHC_ULTRA2) != 0)
871 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
872 else
873 our_id = ahc_inb(ahc, SCSIID) & OID;
874 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
875 scsiseq = ahc_inb(ahc, SCSISEQ);
876 } else {
877 sxfrctl1 = STPWEN;
878 our_id = 7;
879 scsiseq = 0;
880 }
881
882 error = ahc_reset(ahc, /*reinit*/FALSE);
883 if (error != 0)
884 return (ENXIO);
885
886 if ((ahc->features & AHC_DT) != 0) {
887 u_int sfunct;
888
889 /* Perform ALT-Mode Setup */
890 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
891 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
892 ahc_outb(ahc, OPTIONMODE,
893 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
894 ahc_outb(ahc, SFUNCT, sfunct);
895
896 /* Normal mode setup */
897 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
898 |TARGCRCENDEN);
899 }
900
901 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
902 dscommand0 |= MPARCKEN|CACHETHEN;
903 if ((ahc->features & AHC_ULTRA2) != 0) {
904
905 /*
906 * DPARCKEN doesn't work correctly on
907 * some MBs so don't use it.
908 */
909 dscommand0 &= ~DPARCKEN;
910 }
911
912 /*
913 * Handle chips that must have cache line
914 * streaming (dis/en)abled.
915 */
916 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
917 dscommand0 |= CACHETHEN;
918
919 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
920 dscommand0 &= ~CACHETHEN;
921
922 ahc_outb(ahc, DSCOMMAND0, dscommand0);
923
924 ahc->pci_cachesize =
925 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
926 /*bytes*/1) & CACHESIZE;
927 ahc->pci_cachesize *= 4;
928
929 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
930 && ahc->pci_cachesize == 4) {
931
932 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
933 0, /*bytes*/1);
934 ahc->pci_cachesize = 0;
935 }
936
937 /*
938 * We cannot perform ULTRA speeds without the presense
939 * of the external precision resistor.
940 */
941 if ((ahc->features & AHC_ULTRA) != 0) {
942 uint32_t devconfig;
943
944 devconfig = ahc_pci_read_config(ahc->dev_softc,
945 DEVCONFIG, /*bytes*/4);
946 if ((devconfig & REXTVALID) == 0)
947 ahc->features &= ~AHC_ULTRA;
948 }
949
950 /* See if we have a SEEPROM and perform auto-term */
951 check_extport(ahc, &sxfrctl1);
952
953 /*
954 * Take the LED out of diagnostic mode
955 */
956 sblkctl = ahc_inb(ahc, SBLKCTL);
957 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
958
959 if ((ahc->features & AHC_ULTRA2) != 0) {
960 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
961 } else {
962 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
963 }
964
965 if (ahc->flags & AHC_USEDEFAULTS) {
966 /*
967 * PCI Adapter default setup
968 * Should only be used if the adapter does not have
969 * a SEEPROM.
970 */
971 /* See if someone else set us up already */
972 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
973 && scsiseq != 0) {
974 kprintf("%s: Using left over BIOS settings\n",
975 ahc_name(ahc));
976 ahc->flags &= ~AHC_USEDEFAULTS;
977 ahc->flags |= AHC_BIOS_ENABLED;
978 } else {
979 /*
980 * Assume only one connector and always turn
981 * on termination.
982 */
983 our_id = 0x07;
984 sxfrctl1 = STPWEN;
985 }
986 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
987
988 ahc->our_id = our_id;
989 }
990
991 /*
992 * Take a look to see if we have external SRAM.
993 * We currently do not attempt to use SRAM that is
994 * shared among multiple controllers.
995 */
996 ahc_probe_ext_scbram(ahc);
997
998 /*
999 * Record our termination setting for the
1000 * generic initialization routine.
1001 */
1002 if ((sxfrctl1 & STPWEN) != 0)
1003 ahc->flags |= AHC_TERM_ENB_A;
1004
1005 /*
1006 * Save chip register configuration data for chip resets
1007 * that occur during runtime and resume events.
1008 */
1009 ahc->bus_softc.pci_softc.devconfig =
1010 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1011 ahc->bus_softc.pci_softc.command =
1012 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1013 ahc->bus_softc.pci_softc.csize_lattime =
1014 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1015 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1016 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1017 if ((ahc->features & AHC_DT) != 0) {
1018 u_int sfunct;
1019
1020 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1021 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1022 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1023 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1024 ahc_outb(ahc, SFUNCT, sfunct);
1025 ahc->bus_softc.pci_softc.crccontrol1 =
1026 ahc_inb(ahc, CRCCONTROL1);
1027 }
1028 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1029 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1030
1031 if ((ahc->features & AHC_ULTRA2) != 0)
1032 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1033
1034 /* Core initialization */
1035 error = ahc_init(ahc);
1036 if (error != 0)
1037 return (error);
1038
1039 /*
1040 * Allow interrupts now that we are completely setup.
1041 */
1042 error = ahc_pci_map_int(ahc);
1043 if (error != 0)
1044 return (error);
1045
1046 /*
1047 * Link this softc in with all other ahc instances.
1048 */
1049 ahc_softc_insert(ahc);
1050 return (0);
1051 }
1052
1053 /*
1054 * Test for the presense of external sram in an
1055 * "unshared" configuration.
1056 */
1057 static int
1058 ahc_ext_scbram_present(struct ahc_softc *ahc)
1059 {
1060 u_int chip;
1061 int ramps;
1062 int single_user;
1063 uint32_t devconfig;
1064
1065 chip = ahc->chip & AHC_CHIPID_MASK;
1066 devconfig = ahc_pci_read_config(ahc->dev_softc,
1067 DEVCONFIG, /*bytes*/4);
1068 single_user = (devconfig & MPORTMODE) != 0;
1069
1070 if ((ahc->features & AHC_ULTRA2) != 0)
1071 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1072 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1073 /*
1074 * External SCBRAM arbitration is flakey
1075 * on these chips. Unfortunately this means
1076 * we don't use the extra SCB ram space on the
1077 * 3940AUW.
1078 */
1079 ramps = 0;
1080 else if (chip >= AHC_AIC7870)
1081 ramps = (devconfig & RAMPSM) != 0;
1082 else
1083 ramps = 0;
1084
1085 if (ramps && single_user)
1086 return (1);
1087 return (0);
1088 }
1089
1090 /*
1091 * Enable external scbram.
1092 */
1093 static void
1094 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1095 int fast, int large)
1096 {
1097 uint32_t devconfig;
1098
1099 if (ahc->features & AHC_MULTI_FUNC) {
1100 /*
1101 * Set the SCB Base addr (highest address bit)
1102 * depending on which channel we are.
1103 */
1104 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc));
1105 }
1106
1107 ahc->flags &= ~AHC_LSCBS_ENABLED;
1108 if (large)
1109 ahc->flags |= AHC_LSCBS_ENABLED;
1110 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1111 if ((ahc->features & AHC_ULTRA2) != 0) {
1112 u_int dscommand0;
1113
1114 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1115 if (enable)
1116 dscommand0 &= ~INTSCBRAMSEL;
1117 else
1118 dscommand0 |= INTSCBRAMSEL;
1119 if (large)
1120 dscommand0 &= ~USCBSIZE32;
1121 else
1122 dscommand0 |= USCBSIZE32;
1123 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1124 } else {
1125 if (fast)
1126 devconfig &= ~EXTSCBTIME;
1127 else
1128 devconfig |= EXTSCBTIME;
1129 if (enable)
1130 devconfig &= ~SCBRAMSEL;
1131 else
1132 devconfig |= SCBRAMSEL;
1133 if (large)
1134 devconfig &= ~SCBSIZE32;
1135 else
1136 devconfig |= SCBSIZE32;
1137 }
1138 if (pcheck)
1139 devconfig |= EXTSCBPEN;
1140 else
1141 devconfig &= ~EXTSCBPEN;
1142
1143 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1144 }
1145
1146 /*
1147 * Take a look to see if we have external SRAM.
1148 * We currently do not attempt to use SRAM that is
1149 * shared among multiple controllers.
1150 */
1151 static void
1152 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1153 {
1154 int num_scbs;
1155 int test_num_scbs;
1156 int enable;
1157 int pcheck;
1158 int fast;
1159 int large;
1160
1161 enable = FALSE;
1162 pcheck = FALSE;
1163 fast = FALSE;
1164 large = FALSE;
1165 num_scbs = 0;
1166
1167 if (ahc_ext_scbram_present(ahc) == 0)
1168 goto done;
1169
1170 /*
1171 * Probe for the best parameters to use.
1172 */
1173 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1174 num_scbs = ahc_probe_scbs(ahc);
1175 if (num_scbs == 0) {
1176 /* The SRAM wasn't really present. */
1177 goto done;
1178 }
1179 enable = TRUE;
1180
1181 /*
1182 * Clear any outstanding parity error
1183 * and ensure that parity error reporting
1184 * is enabled.
1185 */
1186 ahc_outb(ahc, SEQCTL, 0);
1187 ahc_outb(ahc, CLRINT, CLRPARERR);
1188 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1189
1190 /* Now see if we can do parity */
1191 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1192 num_scbs = ahc_probe_scbs(ahc);
1193 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1194 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1195 pcheck = TRUE;
1196
1197 /* Clear any resulting parity error */
1198 ahc_outb(ahc, CLRINT, CLRPARERR);
1199 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1200
1201 /* Now see if we can do fast timing */
1202 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1203 test_num_scbs = ahc_probe_scbs(ahc);
1204 if (test_num_scbs == num_scbs
1205 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1206 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1207 fast = TRUE;
1208
1209 /*
1210 * See if we can use large SCBs and still maintain
1211 * the same overall count of SCBs.
1212 */
1213 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1214 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1215 test_num_scbs = ahc_probe_scbs(ahc);
1216 if (test_num_scbs >= num_scbs) {
1217 large = TRUE;
1218 num_scbs = test_num_scbs;
1219 if (num_scbs >= 64) {
1220 /*
1221 * We have enough space to move the
1222 * "busy targets table" into SCB space
1223 * and make it qualify all the way to the
1224 * lun level.
1225 */
1226 ahc->flags |= AHC_SCB_BTT;
1227 }
1228 }
1229 }
1230 done:
1231 /*
1232 * Disable parity error reporting until we
1233 * can load instruction ram.
1234 */
1235 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1236 /* Clear any latched parity error */
1237 ahc_outb(ahc, CLRINT, CLRPARERR);
1238 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1239 if (bootverbose && enable) {
1240 kprintf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1241 ahc_name(ahc), fast ? "fast" : "slow",
1242 pcheck ? ", parity checking enabled" : "",
1243 large ? 64 : 32);
1244 }
1245 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1246 }
1247
1248 /*
1249 * Perform some simple tests that should catch situations where
1250 * our registers are invalidly mapped.
1251 */
1252 int
1253 ahc_pci_test_register_access(struct ahc_softc *ahc)
1254 {
1255 int error;
1256 u_int status1;
1257 uint32_t cmd;
1258 uint8_t hcntrl;
1259
1260 error = EIO;
1261
1262 /*
1263 * Enable PCI error interrupt status, but suppress NMIs
1264 * generated by SERR raised due to target aborts.
1265 */
1266 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1267 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1268 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1269
1270 /*
1271 * First a simple test to see if any
1272 * registers can be read. Reading
1273 * HCNTRL has no side effects and has
1274 * at least one bit that is guaranteed to
1275 * be zero so it is a good register to
1276 * use for this test.
1277 */
1278 hcntrl = ahc_inb(ahc, HCNTRL);
1279 if (hcntrl == 0xFF)
1280 goto fail;
1281
1282 /*
1283 * Next create a situation where write combining
1284 * or read prefetching could be initiated by the
1285 * CPU or host bridge. Our device does not support
1286 * either, so look for data corruption and/or flagged
1287 * PCI errors. First pause without causing another
1288 * chip reset.
1289 */
1290 hcntrl &= ~CHIPRST;
1291 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1292 while (ahc_is_paused(ahc) == 0)
1293 ;
1294
1295 /* Clear any PCI errors that occurred before our driver attached. */
1296 status1 = ahc_pci_read_config(ahc->dev_softc,
1297 PCIR_STATUS + 1, /*bytes*/1);
1298 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1299 status1, /*bytes*/1);
1300 ahc_outb(ahc, CLRINT, CLRPARERR);
1301
1302 ahc_outb(ahc, SEQCTL, PERRORDIS);
1303 ahc_outb(ahc, SCBPTR, 0);
1304 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1305 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1306 goto fail;
1307
1308 status1 = ahc_pci_read_config(ahc->dev_softc,
1309 PCIR_STATUS + 1, /*bytes*/1);
1310 if ((status1 & STA) != 0)
1311 goto fail;
1312
1313 error = 0;
1314
1315 fail:
1316 /* Silently clear any latched errors. */
1317 status1 = ahc_pci_read_config(ahc->dev_softc,
1318 PCIR_STATUS + 1, /*bytes*/1);
1319 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1320 status1, /*bytes*/1);
1321 ahc_outb(ahc, CLRINT, CLRPARERR);
1322 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1323 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1324 return (error);
1325 }
1326
1327 /*
1328 * Check the external port logic for a serial eeprom
1329 * and termination/cable detection contrls.
1330 */
1331 static void
1332 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1333 {
1334 struct seeprom_descriptor sd;
1335 struct seeprom_config *sc;
1336 int have_seeprom;
1337 int have_autoterm;
1338
1339 sd.sd_ahc = ahc;
1340 sd.sd_control_offset = SEECTL;
1341 sd.sd_status_offset = SEECTL;
1342 sd.sd_dataout_offset = SEECTL;
1343 sc = ahc->seep_config;
1344
1345 /*
1346 * For some multi-channel devices, the c46 is simply too
1347 * small to work. For the other controller types, we can
1348 * get our information from either SEEPROM type. Set the
1349 * type to start our probe with accordingly.
1350 */
1351 if (ahc->flags & AHC_LARGE_SEEPROM)
1352 sd.sd_chip = C56_66;
1353 else
1354 sd.sd_chip = C46;
1355
1356 sd.sd_MS = SEEMS;
1357 sd.sd_RDY = SEERDY;
1358 sd.sd_CS = SEECS;
1359 sd.sd_CK = SEECK;
1360 sd.sd_DO = SEEDO;
1361 sd.sd_DI = SEEDI;
1362
1363 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1364 if (have_seeprom) {
1365
1366 if (bootverbose)
1367 kprintf("%s: Reading SEEPROM...", ahc_name(ahc));
1368
1369 for (;;) {
1370 u_int start_addr;
1371
1372 start_addr = 32 * (ahc->channel - 'A');
1373
1374 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1375 start_addr,
1376 sizeof(*sc)/2);
1377
1378 if (have_seeprom)
1379 have_seeprom = ahc_verify_cksum(sc);
1380
1381 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1382 if (bootverbose) {
1383 if (have_seeprom == 0)
1384 kprintf ("checksum error\n");
1385 else
1386 kprintf ("done.\n");
1387 }
1388 break;
1389 }
1390 sd.sd_chip = C56_66;
1391 }
1392 ahc_release_seeprom(&sd);
1393 }
1394
1395 if (!have_seeprom) {
1396 /*
1397 * Pull scratch ram settings and treat them as
1398 * if they are the contents of an seeprom if
1399 * the 'ADPT' signature is found in SCB2.
1400 * We manually compose the data as 16bit values
1401 * to avoid endian issues.
1402 */
1403 ahc_outb(ahc, SCBPTR, 2);
1404 if (ahc_inb(ahc, SCB_BASE) == 'A'
1405 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1406 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1407 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1408 uint16_t *sc_data;
1409 int i;
1410
1411 sc_data = (uint16_t *)sc;
1412 for (i = 0; i < 32; i++, sc_data++) {
1413 int j;
1414
1415 j = i * 2;
1416 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1417 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1418 }
1419 have_seeprom = ahc_verify_cksum(sc);
1420 if (have_seeprom)
1421 ahc->flags |= AHC_SCB_CONFIG_USED;
1422 }
1423 /*
1424 * Clear any SCB parity errors in case this data and
1425 * its associated parity was not initialized by the BIOS
1426 */
1427 ahc_outb(ahc, CLRINT, CLRPARERR);
1428 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1429 }
1430
1431 if (!have_seeprom) {
1432 if (bootverbose)
1433 kprintf("%s: No SEEPROM available.\n", ahc_name(ahc));
1434 ahc->flags |= AHC_USEDEFAULTS;
1435 kfree(ahc->seep_config, M_DEVBUF);
1436 ahc->seep_config = NULL;
1437 sc = NULL;
1438 } else {
1439 ahc_parse_pci_eeprom(ahc, sc);
1440 }
1441
1442 /*
1443 * Cards that have the external logic necessary to talk to
1444 * a SEEPROM, are almost certain to have the remaining logic
1445 * necessary for auto-termination control. This assumption
1446 * hasn't failed yet...
1447 */
1448 have_autoterm = have_seeprom;
1449
1450 /*
1451 * Some low-cost chips have SEEPROM and auto-term control built
1452 * in, instead of using a GAL. They can tell us directly
1453 * if the termination logic is enabled.
1454 */
1455 if ((ahc->features & AHC_SPIOCAP) != 0) {
1456 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1457 have_autoterm = FALSE;
1458 }
1459
1460 if (have_autoterm) {
1461 ahc->flags |= AHC_HAS_TERM_LOGIC;
1462 ahc_acquire_seeprom(ahc, &sd);
1463 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1464 ahc_release_seeprom(&sd);
1465 } else if (have_seeprom) {
1466 *sxfrctl1 &= ~STPWEN;
1467 if ((sc->adapter_control & CFSTERM) != 0)
1468 *sxfrctl1 |= STPWEN;
1469 if (bootverbose)
1470 kprintf("%s: Low byte termination %sabled\n",
1471 ahc_name(ahc),
1472 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1473 }
1474 }
1475
1476 static void
1477 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1478 {
1479 /*
1480 * Put the data we've collected down into SRAM
1481 * where ahc_init will find it.
1482 */
1483 int i;
1484 int max_targ = sc->max_targets & CFMAXTARG;
1485 u_int scsi_conf;
1486 uint16_t discenable;
1487 uint16_t ultraenb;
1488
1489 discenable = 0;
1490 ultraenb = 0;
1491 if ((sc->adapter_control & CFULTRAEN) != 0) {
1492 /*
1493 * Determine if this adapter has a "newstyle"
1494 * SEEPROM format.
1495 */
1496 for (i = 0; i < max_targ; i++) {
1497 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1498 ahc->flags |= AHC_NEWEEPROM_FMT;
1499 break;
1500 }
1501 }
1502 }
1503
1504 for (i = 0; i < max_targ; i++) {
1505 u_int scsirate;
1506 uint16_t target_mask;
1507
1508 target_mask = 0x01 << i;
1509 if (sc->device_flags[i] & CFDISC)
1510 discenable |= target_mask;
1511 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1512 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1513 ultraenb |= target_mask;
1514 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1515 ultraenb |= target_mask;
1516 }
1517 if ((sc->device_flags[i] & CFXFER) == 0x04
1518 && (ultraenb & target_mask) != 0) {
1519 /* Treat 10MHz as a non-ultra speed */
1520 sc->device_flags[i] &= ~CFXFER;
1521 ultraenb &= ~target_mask;
1522 }
1523 if ((ahc->features & AHC_ULTRA2) != 0) {
1524 u_int offset;
1525
1526 if (sc->device_flags[i] & CFSYNCH)
1527 offset = MAX_OFFSET_ULTRA2;
1528 else
1529 offset = 0;
1530 ahc_outb(ahc, TARG_OFFSET + i, offset);
1531
1532 /*
1533 * The ultra enable bits contain the
1534 * high bit of the ultra2 sync rate
1535 * field.
1536 */
1537 scsirate = (sc->device_flags[i] & CFXFER)
1538 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1539 if (sc->device_flags[i] & CFWIDEB)
1540 scsirate |= WIDEXFER;
1541 } else {
1542 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1543 if (sc->device_flags[i] & CFSYNCH)
1544 scsirate |= SOFS;
1545 if (sc->device_flags[i] & CFWIDEB)
1546 scsirate |= WIDEXFER;
1547 }
1548 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1549 }
1550 ahc->our_id = sc->brtime_id & CFSCSIID;
1551
1552 scsi_conf = (ahc->our_id & 0x7);
1553 if (sc->adapter_control & CFSPARITY)
1554 scsi_conf |= ENSPCHK;
1555 if (sc->adapter_control & CFRESETB)
1556 scsi_conf |= RESET_SCSI;
1557
1558 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1559
1560 if (sc->bios_control & CFEXTEND)
1561 ahc->flags |= AHC_EXTENDED_TRANS_A;
1562
1563 if (sc->bios_control & CFBIOSEN)
1564 ahc->flags |= AHC_BIOS_ENABLED;
1565 if (ahc->features & AHC_ULTRA
1566 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1567 /* Should we enable Ultra mode? */
1568 if (!(sc->adapter_control & CFULTRAEN))
1569 /* Treat us as a non-ultra card */
1570 ultraenb = 0;
1571 }
1572
1573 if (sc->signature == CFSIGNATURE
1574 || sc->signature == CFSIGNATURE2) {
1575 uint32_t devconfig;
1576
1577 /* Honor the STPWLEVEL settings */
1578 devconfig = ahc_pci_read_config(ahc->dev_softc,
1579 DEVCONFIG, /*bytes*/4);
1580 devconfig &= ~STPWLEVEL;
1581 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1582 devconfig |= STPWLEVEL;
1583 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG,
1584 devconfig, /*bytes*/4);
1585 }
1586 /* Set SCSICONF info */
1587 ahc_outb(ahc, SCSICONF, scsi_conf);
1588 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1589 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1590 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1591 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1592 }
1593
1594 static void
1595 configure_termination(struct ahc_softc *ahc,
1596 struct seeprom_descriptor *sd,
1597 u_int adapter_control,
1598 u_int *sxfrctl1)
1599 {
1600 uint8_t brddat;
1601
1602 brddat = 0;
1603
1604 /*
1605 * Update the settings in sxfrctl1 to match the
1606 * termination settings
1607 */
1608 *sxfrctl1 = 0;
1609
1610 /*
1611 * SEECS must be on for the GALS to latch
1612 * the data properly. Be sure to leave MS
1613 * on or we will release the seeprom.
1614 */
1615 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1616 if ((adapter_control & CFAUTOTERM) != 0
1617 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1618 int internal50_present;
1619 int internal68_present;
1620 int externalcable_present;
1621 int eeprom_present;
1622 int enableSEC_low;
1623 int enableSEC_high;
1624 int enablePRI_low;
1625 int enablePRI_high;
1626 int sum;
1627
1628 enableSEC_low = 0;
1629 enableSEC_high = 0;
1630 enablePRI_low = 0;
1631 enablePRI_high = 0;
1632 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1633 ahc_new_term_detect(ahc, &enableSEC_low,
1634 &enableSEC_high,
1635 &enablePRI_low,
1636 &enablePRI_high,
1637 &eeprom_present);
1638 if ((adapter_control & CFSEAUTOTERM) == 0) {
1639 if (bootverbose)
1640 kprintf("%s: Manual SE Termination\n",
1641 ahc_name(ahc));
1642 enableSEC_low = (adapter_control & CFSELOWTERM);
1643 enableSEC_high =
1644 (adapter_control & CFSEHIGHTERM);
1645 }
1646 if ((adapter_control & CFAUTOTERM) == 0) {
1647 if (bootverbose)
1648 kprintf("%s: Manual LVD Termination\n",
1649 ahc_name(ahc));
1650 enablePRI_low = (adapter_control & CFSTERM);
1651 enablePRI_high = (adapter_control & CFWSTERM);
1652 }
1653 /* Make the table calculations below happy */
1654 internal50_present = 0;
1655 internal68_present = 1;
1656 externalcable_present = 1;
1657 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1658 aic785X_cable_detect(ahc, &internal50_present,
1659 &externalcable_present,
1660 &eeprom_present);
1661 /* Can never support a wide connector. */
1662 internal68_present = 0;
1663 } else {
1664 aic787X_cable_detect(ahc, &internal50_present,
1665 &internal68_present,
1666 &externalcable_present,
1667 &eeprom_present);
1668 }
1669
1670 if ((ahc->features & AHC_WIDE) == 0)
1671 internal68_present = 0;
1672
1673 if (bootverbose
1674 && (ahc->features & AHC_ULTRA2) == 0) {
1675 kprintf("%s: internal 50 cable %s present",
1676 ahc_name(ahc),
1677 internal50_present ? "is":"not");
1678
1679 if ((ahc->features & AHC_WIDE) != 0)
1680 kprintf(", internal 68 cable %s present",
1681 internal68_present ? "is":"not");
1682 kprintf("\n%s: external cable %s present\n",
1683 ahc_name(ahc),
1684 externalcable_present ? "is":"not");
1685 }
1686 if (bootverbose)
1687 kprintf("%s: BIOS eeprom %s present\n",
1688 ahc_name(ahc), eeprom_present ? "is" : "not");
1689
1690 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1691 /*
1692 * The 50 pin connector is a separate bus,
1693 * so force it to always be terminated.
1694 * In the future, perform current sensing
1695 * to determine if we are in the middle of
1696 * a properly terminated bus.
1697 */
1698 internal50_present = 0;
1699 }
1700
1701 /*
1702 * Now set the termination based on what
1703 * we found.
1704 * Flash Enable = BRDDAT7
1705 * Secondary High Term Enable = BRDDAT6
1706 * Secondary Low Term Enable = BRDDAT5 (7890)
1707 * Primary High Term Enable = BRDDAT4 (7890)
1708 */
1709 if ((ahc->features & AHC_ULTRA2) == 0
1710 && (internal50_present != 0)
1711 && (internal68_present != 0)
1712 && (externalcable_present != 0)) {
1713 kprintf("%s: Illegal cable configuration!!. "
1714 "Only two connectors on the "
1715 "adapter may be used at a "
1716 "time!\n", ahc_name(ahc));
1717
1718 /*
1719 * Pretend there are no cables in the hope
1720 * that having all of the termination on
1721 * gives us a more stable bus.
1722 */
1723 internal50_present = 0;
1724 internal68_present = 0;
1725 externalcable_present = 0;
1726 }
1727
1728 if ((ahc->features & AHC_WIDE) != 0
1729 && ((externalcable_present == 0)
1730 || (internal68_present == 0)
1731 || (enableSEC_high != 0))) {
1732 brddat |= BRDDAT6;
1733 if (bootverbose) {
1734 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1735 kprintf("%s: 68 pin termination "
1736 "Enabled\n", ahc_name(ahc));
1737 else
1738 kprintf("%s: %sHigh byte termination "
1739 "Enabled\n", ahc_name(ahc),
1740 enableSEC_high ? "Secondary "
1741 : "");
1742 }
1743 }
1744
1745 sum = internal50_present + internal68_present
1746 + externalcable_present;
1747 if (sum < 2 || (enableSEC_low != 0)) {
1748 if ((ahc->features & AHC_ULTRA2) != 0)
1749 brddat |= BRDDAT5;
1750 else
1751 *sxfrctl1 |= STPWEN;
1752 if (bootverbose) {
1753 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1754 kprintf("%s: 50 pin termination "
1755 "Enabled\n", ahc_name(ahc));
1756 else
1757 kprintf("%s: %sLow byte termination "
1758 "Enabled\n", ahc_name(ahc),
1759 enableSEC_low ? "Secondary "
1760 : "");
1761 }
1762 }
1763
1764 if (enablePRI_low != 0) {
1765 *sxfrctl1 |= STPWEN;
1766 if (bootverbose)
1767 kprintf("%s: Primary Low Byte termination "
1768 "Enabled\n", ahc_name(ahc));
1769 }
1770
1771 /*
1772 * Setup STPWEN before setting up the rest of
1773 * the termination per the tech note on the U160 cards.
1774 */
1775 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1776
1777 if (enablePRI_high != 0) {
1778 brddat |= BRDDAT4;
1779 if (bootverbose)
1780 kprintf("%s: Primary High Byte "
1781 "termination Enabled\n",
1782 ahc_name(ahc));
1783 }
1784
1785 write_brdctl(ahc, brddat);
1786
1787 } else {
1788 if ((adapter_control & CFSTERM) != 0) {
1789 *sxfrctl1 |= STPWEN;
1790
1791 if (bootverbose)
1792 kprintf("%s: %sLow byte termination Enabled\n",
1793 ahc_name(ahc),
1794 (ahc->features & AHC_ULTRA2) ? "Primary "
1795 : "");
1796 }
1797
1798 if ((adapter_control & CFWSTERM) != 0
1799 && (ahc->features & AHC_WIDE) != 0) {
1800 brddat |= BRDDAT6;
1801 if (bootverbose)
1802 kprintf("%s: %sHigh byte termination Enabled\n",
1803 ahc_name(ahc),
1804 (ahc->features & AHC_ULTRA2)
1805 ? "Secondary " : "");
1806 }
1807
1808 /*
1809 * Setup STPWEN before setting up the rest of
1810 * the termination per the tech note on the U160 cards.
1811 */
1812 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1813
1814 if ((ahc->features & AHC_WIDE) != 0)
1815 write_brdctl(ahc, brddat);
1816 }
1817 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1818 }
1819
1820 static void
1821 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1822 int *enableSEC_high, int *enablePRI_low,
1823 int *enablePRI_high, int *eeprom_present)
1824 {
1825 uint8_t brdctl;
1826
1827 /*
1828 * BRDDAT7 = Eeprom
1829 * BRDDAT6 = Enable Secondary High Byte termination
1830 * BRDDAT5 = Enable Secondary Low Byte termination
1831 * BRDDAT4 = Enable Primary high byte termination
1832 * BRDDAT3 = Enable Primary low byte termination
1833 */
1834 brdctl = read_brdctl(ahc);
1835 *eeprom_present = brdctl & BRDDAT7;
1836 *enableSEC_high = (brdctl & BRDDAT6);
1837 *enableSEC_low = (brdctl & BRDDAT5);
1838 *enablePRI_high = (brdctl & BRDDAT4);
1839 *enablePRI_low = (brdctl & BRDDAT3);
1840 }
1841
1842 static void
1843 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1844 int *internal68_present, int *externalcable_present,
1845 int *eeprom_present)
1846 {
1847 uint8_t brdctl;
1848
1849 /*
1850 * First read the status of our cables.
1851 * Set the rom bank to 0 since the
1852 * bank setting serves as a multiplexor
1853 * for the cable detection logic.
1854 * BRDDAT5 controls the bank switch.
1855 */
1856 write_brdctl(ahc, 0);
1857
1858 /*
1859 * Now read the state of the internal
1860 * connectors. BRDDAT6 is INT50 and
1861 * BRDDAT7 is INT68.
1862 */
1863 brdctl = read_brdctl(ahc);
1864 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1865 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1866
1867 /*
1868 * Set the rom bank to 1 and determine
1869 * the other signals.
1870 */
1871 write_brdctl(ahc, BRDDAT5);
1872
1873 /*
1874 * Now read the state of the external
1875 * connectors. BRDDAT6 is EXT68 and
1876 * BRDDAT7 is EPROMPS.
1877 */
1878 brdctl = read_brdctl(ahc);
1879 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1880 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1881 }
1882
1883 static void
1884 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1885 int *externalcable_present, int *eeprom_present)
1886 {
1887 uint8_t brdctl;
1888 uint8_t spiocap;
1889
1890 spiocap = ahc_inb(ahc, SPIOCAP);
1891 spiocap &= ~SOFTCMDEN;
1892 spiocap |= EXT_BRDCTL;
1893 ahc_outb(ahc, SPIOCAP, spiocap);
1894 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1895 ahc_flush_device_writes(ahc);
1896 ahc_delay(500);
1897 ahc_outb(ahc, BRDCTL, 0);
1898 ahc_flush_device_writes(ahc);
1899 ahc_delay(500);
1900 brdctl = ahc_inb(ahc, BRDCTL);
1901 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1902 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1903 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1904 }
1905
1906 int
1907 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1908 {
1909 int wait;
1910
1911 if ((ahc->features & AHC_SPIOCAP) != 0
1912 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1913 return (0);
1914
1915 /*
1916 * Request access of the memory port. When access is
1917 * granted, SEERDY will go high. We use a 1 second
1918 * timeout which should be near 1 second more than
1919 * is needed. Reason: after the chip reset, there
1920 * should be no contention.
1921 */
1922 SEEPROM_OUTB(sd, sd->sd_MS);
1923 wait = 1000; /* 1 second timeout in msec */
1924 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1925 ahc_delay(1000); /* delay 1 msec */
1926 }
1927 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1928 SEEPROM_OUTB(sd, 0);
1929 return (0);
1930 }
1931 return(1);
1932 }
1933
1934 void
1935 ahc_release_seeprom(struct seeprom_descriptor *sd)
1936 {
1937 /* Release access to the memory port and the serial EEPROM. */
1938 SEEPROM_OUTB(sd, 0);
1939 }
1940
1941 static void
1942 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1943 {
1944 uint8_t brdctl;
1945
1946 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1947 brdctl = BRDSTB;
1948 if (ahc->channel == 'B')
1949 brdctl |= BRDCS;
1950 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1951 brdctl = 0;
1952 } else {
1953 brdctl = BRDSTB|BRDCS;
1954 }
1955 ahc_outb(ahc, BRDCTL, brdctl);
1956 ahc_flush_device_writes(ahc);
1957 brdctl |= value;
1958 ahc_outb(ahc, BRDCTL, brdctl);
1959 ahc_flush_device_writes(ahc);
1960 if ((ahc->features & AHC_ULTRA2) != 0)
1961 brdctl |= BRDSTB_ULTRA2;
1962 else
1963 brdctl &= ~BRDSTB;
1964 ahc_outb(ahc, BRDCTL, brdctl);
1965 ahc_flush_device_writes(ahc);
1966 if ((ahc->features & AHC_ULTRA2) != 0)
1967 brdctl = 0;
1968 else
1969 brdctl &= ~BRDCS;
1970 ahc_outb(ahc, BRDCTL, brdctl);
1971 }
1972
1973 static uint8_t
1974 read_brdctl(struct ahc_softc *ahc)
1975 {
1976 uint8_t brdctl;
1977 uint8_t value;
1978
1979 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1980 brdctl = BRDRW;
1981 if (ahc->channel == 'B')
1982 brdctl |= BRDCS;
1983 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1984 brdctl = BRDRW_ULTRA2;
1985 } else {
1986 brdctl = BRDRW|BRDCS;
1987 }
1988 ahc_outb(ahc, BRDCTL, brdctl);
1989 ahc_flush_device_writes(ahc);
1990 value = ahc_inb(ahc, BRDCTL);
1991 ahc_outb(ahc, BRDCTL, 0);
1992 return (value);
1993 }
1994
1995 static void
1996 ahc_pci_intr(struct ahc_softc *ahc)
1997 {
1998 u_int error;
1999 u_int status1;
2000
2001 error = ahc_inb(ahc, ERROR);
2002 if ((error & PCIERRSTAT) == 0)
2003 return;
2004
2005 status1 = ahc_pci_read_config(ahc->dev_softc,
2006 PCIR_STATUS + 1, /*bytes*/1);
2007
2008 kprintf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2009 ahc_name(ahc),
2010 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2011
2012 if (status1 & DPE) {
2013 ahc->pci_target_perr_count++;
2014 kprintf("%s: Data Parity Error Detected during address "
2015 "or write data phase\n", ahc_name(ahc));
2016 }
2017 if (status1 & SSE) {
2018 kprintf("%s: Signal System Error Detected\n", ahc_name(ahc));
2019 }
2020 if (status1 & RMA) {
2021 kprintf("%s: Received a Master Abort\n", ahc_name(ahc));
2022 }
2023 if (status1 & RTA) {
2024 kprintf("%s: Received a Target Abort\n", ahc_name(ahc));
2025 }
2026 if (status1 & STA) {
2027 kprintf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2028 }
2029 if (status1 & DPR) {
2030 kprintf("%s: Data Parity Error has been reported via PERR#\n",
2031 ahc_name(ahc));
2032 }
2033
2034 /* Clear latched errors. */
2035 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2036 status1, /*bytes*/1);
2037
2038 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2039 kprintf("%s: Latched PCIERR interrupt with "
2040 "no status bits set\n", ahc_name(ahc));
2041 } else {
2042 ahc_outb(ahc, CLRINT, CLRPARERR);
2043 }
2044
2045 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) {
2046 kprintf(
2047 "%s: WARNING WARNING WARNING WARNING\n"
2048 "%s: Too many PCI parity errors observed as a target.\n"
2049 "%s: Some device on this bus is generating bad parity.\n"
2050 "%s: This is an error *observed by*, not *generated by*, this controller.\n"
2051 "%s: PCI parity error checking has been disabled.\n"
2052 "%s: WARNING WARNING WARNING WARNING\n",
2053 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2054 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc));
2055 ahc->seqctl |= FAILDIS;
2056 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2057 }
2058 ahc_unpause(ahc);
2059 }
2060
2061 static int
2062 ahc_pci_chip_init(struct ahc_softc *ahc)
2063 {
2064 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2065 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2066 if ((ahc->features & AHC_DT) != 0) {
2067 u_int sfunct;
2068
2069 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2070 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2071 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2072 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2073 ahc_outb(ahc, SFUNCT, sfunct);
2074 ahc_outb(ahc, CRCCONTROL1,
2075 ahc->bus_softc.pci_softc.crccontrol1);
2076 }
2077 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2078 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2079
2080 if ((ahc->features & AHC_ULTRA2) != 0)
2081 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2082
2083 return (ahc_chip_init(ahc));
2084 }
2085
2086 static int
2087 ahc_pci_suspend(struct ahc_softc *ahc)
2088 {
2089 return (ahc_suspend(ahc));
2090 }
2091
2092 static int
2093 ahc_pci_resume(struct ahc_softc *ahc)
2094 {
2095
2096 ahc_power_state_change(ahc, AHC_POWER_STATE_D0);
2097
2098 /*
2099 * We assume that the OS has restored our register
2100 * mappings, etc. Just update the config space registers
2101 * that the OS doesn't know about and rely on our chip
2102 * reset handler to handle the rest.
2103 */
2104 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4,
2105 ahc->bus_softc.pci_softc.devconfig);
2106 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1,
2107 ahc->bus_softc.pci_softc.command);
2108 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1,
2109 ahc->bus_softc.pci_softc.csize_lattime);
2110 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2111 struct seeprom_descriptor sd;
2112 u_int sxfrctl1;
2113
2114 sd.sd_ahc = ahc;
2115 sd.sd_control_offset = SEECTL;
2116 sd.sd_status_offset = SEECTL;
2117 sd.sd_dataout_offset = SEECTL;
2118
2119 ahc_acquire_seeprom(ahc, &sd);
2120 configure_termination(ahc, &sd,
2121 ahc->seep_config->adapter_control,
2122 &sxfrctl1);
2123 ahc_release_seeprom(&sd);
2124 }
2125 return (ahc_resume(ahc));
2126 }
2127
2128 static int
2129 ahc_aic785X_setup(struct ahc_softc *ahc)
2130 {
2131 ahc_dev_softc_t pci;
2132 uint8_t rev;
2133
2134 pci = ahc->dev_softc;
2135 ahc->channel = 'A';
2136 ahc->chip = AHC_AIC7850;
2137 ahc->features = AHC_AIC7850_FE;
2138 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2139 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2140 if (rev >= 1)
2141 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2142 ahc->instruction_ram_size = 512;
2143 return (0);
2144 }
2145
2146 static int
2147 ahc_aic7860_setup(struct ahc_softc *ahc)
2148 {
2149 ahc_dev_softc_t pci;
2150 uint8_t rev;
2151
2152 pci = ahc->dev_softc;
2153 ahc->channel = 'A';
2154 ahc->chip = AHC_AIC7860;
2155 ahc->features = AHC_AIC7860_FE;
2156 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2157 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2158 if (rev >= 1)
2159 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2160 ahc->instruction_ram_size = 512;
2161 return (0);
2162 }
2163
2164 static int
2165 ahc_apa1480_setup(struct ahc_softc *ahc)
2166 {
2167 int error;
2168
2169 error = ahc_aic7860_setup(ahc);
2170 if (error != 0)
2171 return (error);
2172 ahc->features |= AHC_REMOVABLE;
2173 return (0);
2174 }
2175
2176 static int
2177 ahc_aic7870_setup(struct ahc_softc *ahc)
2178 {
2179
2180 ahc->channel = 'A';
2181 ahc->chip = AHC_AIC7870;
2182 ahc->features = AHC_AIC7870_FE;
2183 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2184 ahc->instruction_ram_size = 512;
2185 return (0);
2186 }
2187
2188 static int
2189 ahc_aha394X_setup(struct ahc_softc *ahc)
2190 {
2191 int error;
2192
2193 error = ahc_aic7870_setup(ahc);
2194 if (error == 0)
2195 error = ahc_aha394XX_setup(ahc);
2196 return (error);
2197 }
2198
2199 static int
2200 ahc_aha398X_setup(struct ahc_softc *ahc)
2201 {
2202 int error;
2203
2204 error = ahc_aic7870_setup(ahc);
2205 if (error == 0)
2206 error = ahc_aha398XX_setup(ahc);
2207 return (error);
2208 }
2209
2210 static int
2211 ahc_aha494X_setup(struct ahc_softc *ahc)
2212 {
2213 int error;
2214
2215 error = ahc_aic7870_setup(ahc);
2216 if (error == 0)
2217 error = ahc_aha494XX_setup(ahc);
2218 return (error);
2219 }
2220
2221 static int
2222 ahc_aic7880_setup(struct ahc_softc *ahc)
2223 {
2224 ahc_dev_softc_t pci;
2225 uint8_t rev;
2226
2227 pci = ahc->dev_softc;
2228 ahc->channel = 'A';
2229 ahc->chip = AHC_AIC7880;
2230 ahc->features = AHC_AIC7880_FE;
2231 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2232 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2233 if (rev >= 1) {
2234 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2235 } else {
2236 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2237 }
2238 ahc->instruction_ram_size = 512;
2239 return (0);
2240 }
2241
2242 static int
2243 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2244 {
2245
2246 ahc->flags |= AHC_INT50_SPEEDFLEX;
2247 return (ahc_aic7880_setup(ahc));
2248 }
2249
2250 static int
2251 ahc_aha394XU_setup(struct ahc_softc *ahc)
2252 {
2253 int error;
2254
2255 error = ahc_aic7880_setup(ahc);
2256 if (error == 0)
2257 error = ahc_aha394XX_setup(ahc);
2258 return (error);
2259 }
2260
2261 static int
2262 ahc_aha398XU_setup(struct ahc_softc *ahc)
2263 {
2264 int error;
2265
2266 error = ahc_aic7880_setup(ahc);
2267 if (error == 0)
2268 error = ahc_aha398XX_setup(ahc);
2269 return (error);
2270 }
2271
2272 static int
2273 ahc_aic7890_setup(struct ahc_softc *ahc)
2274 {
2275 ahc_dev_softc_t pci;
2276 uint8_t rev;
2277
2278 pci = ahc->dev_softc;
2279 ahc->channel = 'A';
2280 ahc->chip = AHC_AIC7890;
2281 ahc->features = AHC_AIC7890_FE;
2282 ahc->flags |= AHC_NEWEEPROM_FMT;
2283 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2284 if (rev == 0)
2285 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2286 ahc->instruction_ram_size = 768;
2287 return (0);
2288 }
2289
2290 static int
2291 ahc_aic7892_setup(struct ahc_softc *ahc)
2292 {
2293
2294 ahc->channel = 'A';
2295 ahc->chip = AHC_AIC7892;
2296 ahc->features = AHC_AIC7892_FE;
2297 ahc->flags |= AHC_NEWEEPROM_FMT;
2298 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2299 ahc->instruction_ram_size = 1024;
2300 return (0);
2301 }
2302
2303 static int
2304 ahc_aic7895_setup(struct ahc_softc *ahc)
2305 {
2306 ahc_dev_softc_t pci;
2307 uint8_t rev;
2308
2309 pci = ahc->dev_softc;
2310 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2311 /*
2312 * The 'C' revision of the aic7895 has a few additional features.
2313 */
2314 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2315 if (rev >= 4) {
2316 ahc->chip = AHC_AIC7895C;
2317 ahc->features = AHC_AIC7895C_FE;
2318 } else {
2319 u_int command;
2320
2321 ahc->chip = AHC_AIC7895;
2322 ahc->features = AHC_AIC7895_FE;
2323
2324 /*
2325 * The BIOS disables the use of MWI transactions
2326 * since it does not have the MWI bug work around
2327 * we have. Disabling MWI reduces performance, so
2328 * turn it on again.
2329 */
2330 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2331 command |= PCIM_CMD_MWRICEN;
2332 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2333 ahc->bugs |= AHC_PCI_MWI_BUG;
2334 }
2335 /*
2336 * XXX Does CACHETHEN really not work??? What about PCI retry?
2337 * on C level chips. Need to test, but for now, play it safe.
2338 */
2339 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2340 | AHC_CACHETHEN_BUG;
2341
2342 #if 0
2343 uint32_t devconfig;
2344
2345 /*
2346 * Cachesize must also be zero due to stray DAC
2347 * problem when sitting behind some bridges.
2348 */
2349 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2350 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2351 devconfig |= MRDCEN;
2352 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2353 #endif
2354 ahc->flags |= AHC_NEWEEPROM_FMT;
2355 ahc->instruction_ram_size = 512;
2356 return (0);
2357 }
2358
2359 static int
2360 ahc_aic7896_setup(struct ahc_softc *ahc)
2361 {
2362 ahc_dev_softc_t pci;
2363
2364 pci = ahc->dev_softc;
2365 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2366 ahc->chip = AHC_AIC7896;
2367 ahc->features = AHC_AIC7896_FE;
2368 ahc->flags |= AHC_NEWEEPROM_FMT;
2369 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2370 ahc->instruction_ram_size = 768;
2371 return (0);
2372 }
2373
2374 static int
2375 ahc_aic7899_setup(struct ahc_softc *ahc)
2376 {
2377 ahc_dev_softc_t pci;
2378
2379 pci = ahc->dev_softc;
2380 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A';
2381 ahc->chip = AHC_AIC7899;
2382 ahc->features = AHC_AIC7899_FE;
2383 ahc->flags |= AHC_NEWEEPROM_FMT;
2384 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2385 ahc->instruction_ram_size = 1024;
2386 return (0);
2387 }
2388
2389 static int
2390 ahc_aha29160C_setup(struct ahc_softc *ahc)
2391 {
2392 int error;
2393
2394 error = ahc_aic7899_setup(ahc);
2395 if (error != 0)
2396 return (error);
2397 ahc->features |= AHC_REMOVABLE;
2398 return (0);
2399 }
2400
2401 static int
2402 ahc_raid_setup(struct ahc_softc *ahc)
2403 {
2404 kprintf("RAID functionality unsupported\n");
2405 return (ENXIO);
2406 }
2407
2408 static int
2409 ahc_aha394XX_setup(struct ahc_softc *ahc)
2410 {
2411 ahc_dev_softc_t pci;
2412
2413 pci = ahc->dev_softc;
2414 switch (ahc_get_pci_slot(pci)) {
2415 case AHC_394X_SLOT_CHANNEL_A:
2416 ahc->channel = 'A';
2417 break;
2418 case AHC_394X_SLOT_CHANNEL_B:
2419 ahc->channel = 'B';
2420 break;
2421 default:
2422 kprintf("adapter at unexpected slot %d\n"
2423 "unable to map to a channel\n",
2424 ahc_get_pci_slot(pci));
2425 ahc->channel = 'A';
2426 }
2427 return (0);
2428 }
2429
2430 static int
2431 ahc_aha398XX_setup(struct ahc_softc *ahc)
2432 {
2433 ahc_dev_softc_t pci;
2434
2435 pci = ahc->dev_softc;
2436 switch (ahc_get_pci_slot(pci)) {
2437 case AHC_398X_SLOT_CHANNEL_A:
2438 ahc->channel = 'A';
2439 break;
2440 case AHC_398X_SLOT_CHANNEL_B:
2441 ahc->channel = 'B';
2442 break;
2443 case AHC_398X_SLOT_CHANNEL_C:
2444 ahc->channel = 'C';
2445 break;
2446 default:
2447 kprintf("adapter at unexpected slot %d\n"
2448 "unable to map to a channel\n",
2449 ahc_get_pci_slot(pci));
2450 ahc->channel = 'A';
2451 break;
2452 }
2453 ahc->flags |= AHC_LARGE_SEEPROM;
2454 return (0);
2455 }
2456
2457 static int
2458 ahc_aha494XX_setup(struct ahc_softc *ahc)
2459 {
2460 ahc_dev_softc_t pci;
2461
2462 pci = ahc->dev_softc;
2463 switch (ahc_get_pci_slot(pci)) {
2464 case AHC_494X_SLOT_CHANNEL_A:
2465 ahc->channel = 'A';
2466 break;
2467 case AHC_494X_SLOT_CHANNEL_B:
2468 ahc->channel = 'B';
2469 break;
2470 case AHC_494X_SLOT_CHANNEL_C:
2471 ahc->channel = 'C';
2472 break;
2473 case AHC_494X_SLOT_CHANNEL_D:
2474 ahc->channel = 'D';
2475 break;
2476 default:
2477 kprintf("adapter at unexpected slot %d\n"
2478 "unable to map to a channel\n",
2479 ahc_get_pci_slot(pci));
2480 ahc->channel = 'A';
2481 }
2482 ahc->flags |= AHC_LARGE_SEEPROM;
2483 return (0);
2484 }
2485
2486 #endif
A repo for keeping AMD64 port code before merging with the master