2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms are permitted
6 * provided that the following conditions are met:
7 * 1. The materials contained herein are unmodified and are used
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13 * 3. Redistributions in binary form must reproduce at minimum a
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23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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36 * $Id: //depot/sw/branches/sam_hal/ah_desc.h#5 $
39 #ifndef _DEV_ATH_DESC_H
40 #define _DEV_ATH_DESC_H
43 * Transmit descriptor status. This structure is filled
44 * in only after the tx descriptor process method finds a
45 * ``done'' descriptor; at which point it returns something
46 * other than HAL_EINPROGRESS.
48 * Note that ts_antenna may not be valid for all h/w. It
49 * should be used only if non-zero.
51 struct ath_tx_status
{
52 u_int16_t ts_seqnum
; /* h/w assigned sequence number */
53 u_int16_t ts_tstamp
; /* h/w assigned timestamp */
54 u_int8_t ts_status
; /* frame status, 0 => xmit ok */
55 u_int8_t ts_rate
; /* h/w transmit rate index */
56 #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
57 int8_t ts_rssi
; /* tx ack RSSI */
58 u_int8_t ts_shortretry
; /* # short retries */
59 u_int8_t ts_longretry
; /* # long retries */
60 u_int8_t ts_virtcol
; /* virtual collision count */
61 u_int8_t ts_antenna
; /* antenna information */
62 u_int8_t ts_finaltsi
; /* final transmit series index */
65 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */
66 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
67 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */
70 * Receive descriptor status. This structure is filled
71 * in only after the rx descriptor process method finds a
72 * ``done'' descriptor; at which point it returns something
73 * other than HAL_EINPROGRESS.
75 * If rx_status is zero, then the frame was received ok;
76 * otherwise the error information is indicated and rs_phyerr
77 * contains a phy error code if HAL_RXERR_PHY is set. In general
78 * the frame contents is undefined when an error occurred thought
79 * for some errors (e.g. a decryption error), it may be meaningful.
81 * Note that the receive timestamp is expanded using the TSF to
82 * 15 bits (regardless of what the h/w provides directly).
84 * rx_rssi is in units of dbm above the noise floor. This value
85 * is measured during the preamble and PLCP; i.e. with the initial
86 * 4us of detection. The noise floor is typically a consistent
87 * -96dBm absolute power in a 20MHz channel.
89 struct ath_rx_status
{
90 u_int16_t rs_datalen
; /* rx frame length */
91 u_int16_t rs_tstamp
; /* h/w assigned timestamp */
92 u_int8_t rs_status
; /* rx status, 0 => recv ok */
93 u_int8_t rs_phyerr
; /* phy error code */
94 int8_t rs_rssi
; /* rx frame RSSI */
95 u_int8_t rs_keyix
; /* key cache index */
96 u_int8_t rs_rate
; /* h/w receive rate index */
97 u_int8_t rs_antenna
; /* antenna information */
98 u_int8_t rs_more
; /* more descriptors follow */
101 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */
102 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
103 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */
104 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
105 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
108 HAL_PHYERR_UNDERRUN
= 0, /* Transmit underrun */
109 HAL_PHYERR_TIMING
= 1, /* Timing error */
110 HAL_PHYERR_PARITY
= 2, /* Illegal parity */
111 HAL_PHYERR_RATE
= 3, /* Illegal rate */
112 HAL_PHYERR_LENGTH
= 4, /* Illegal length */
113 HAL_PHYERR_RADAR
= 5, /* Radar detect */
114 HAL_PHYERR_SERVICE
= 6, /* Illegal service */
115 HAL_PHYERR_TOR
= 7, /* Transmit override receive */
116 /* NB: these are specific to the 5212 */
117 HAL_PHYERR_OFDM_TIMING
= 17, /* */
118 HAL_PHYERR_OFDM_SIGNAL_PARITY
= 18, /* */
119 HAL_PHYERR_OFDM_RATE_ILLEGAL
= 19, /* */
120 HAL_PHYERR_OFDM_LENGTH_ILLEGAL
= 20, /* */
121 HAL_PHYERR_OFDM_POWER_DROP
= 21, /* */
122 HAL_PHYERR_OFDM_SERVICE
= 22, /* */
123 HAL_PHYERR_OFDM_RESTART
= 23, /* */
124 HAL_PHYERR_CCK_TIMING
= 25, /* */
125 HAL_PHYERR_CCK_HEADER_CRC
= 26, /* */
126 HAL_PHYERR_CCK_RATE_ILLEGAL
= 27, /* */
127 HAL_PHYERR_CCK_SERVICE
= 30, /* */
128 HAL_PHYERR_CCK_RESTART
= 31, /* */
131 /* value found in rs_keyix to mark invalid entries */
132 #define HAL_RXKEYIX_INVALID ((u_int8_t) -1)
133 /* value used to specify no encryption key for xmit */
134 #define HAL_TXKEYIX_INVALID ((u_int) -1)
136 /* XXX rs_antenna definitions */
139 * Definitions for the software frame/packet descriptors used by
140 * the Atheros HAL. This definition obscures hardware-specific
141 * details from the driver. Drivers are expected to fillin the
142 * portions of a descriptor that are not opaque then use HAL calls
143 * to complete the work. Status for completed frames is returned
144 * in a device-independent format.
148 * The following definitions are passed directly
149 * the hardware and managed by the HAL. Drivers
150 * should not touch those elements marked opaque.
152 u_int32_t ds_link
; /* phys address of next descriptor */
153 u_int32_t ds_data
; /* phys address of data buffer */
154 u_int32_t ds_ctl0
; /* opaque DMA control 0 */
155 u_int32_t ds_ctl1
; /* opaque DMA control 1 */
156 u_int32_t ds_hw
[4]; /* opaque h/w region */
159 struct ath_desc_status
{
161 struct ath_tx_status tx
;/* xmit status */
162 struct ath_rx_status rx
;/* recv status */
166 #define ds_txstat ds_us.tx
167 #define ds_rxstat ds_us.rx
169 /* flags passed to tx descriptor setup methods */
170 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
171 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
172 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
173 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
174 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
175 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
176 /* NB: this only affects frame, not any RTS/CTS */
177 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
179 /* flags passed to rx descriptor setup methods */
180 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
181 #endif /* _DEV_ATH_DESC_H */