amd64 port: mainly on the pmap headers, identify_cpu and initcpu
[dragonfly/port-amd64.git] / sys / dev / raid / twe / twereg.h
blob8a26459ada6583c4700a8de30678445c229d82cc
1 /*-
2 * Copyright (c) 2000 Michael Smith
3 * Copyright (c) 2003 Paul Saab
4 * Copyright (c) 2003 Vinod Kashyap
5 * Copyright (c) 2000 BSDi
6 * All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
29 * $FreeBSD: src/sys/dev/twe/twereg.h,v 1.1.2.7 2004/05/12 03:33:37 vkashyap Exp $
30 * $DragonFly: src/sys/dev/raid/twe/twereg.h,v 1.7 2006/12/22 23:26:24 swildner Exp $
33 /*
34 * Register names, bit definitions, structure names and members are
35 * identical with those in the Linux driver where possible and sane
36 * for simplicity's sake. (The TW_ prefix has become TWE_)
37 * Some defines that are clearly irrelevant to FreeBSD have been
38 * removed.
41 /* control register bit definitions */
42 #define TWE_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
43 #define TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
44 #define TWE_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
45 #define TWE_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
46 #define TWE_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
47 #define TWE_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
48 #define TWE_CONTROL_CLEAR_ERROR_STATUS 0x00000200
49 #define TWE_CONTROL_ISSUE_SOFT_RESET 0x00000100
50 #define TWE_CONTROL_ENABLE_INTERRUPTS 0x00000080
51 #define TWE_CONTROL_DISABLE_INTERRUPTS 0x00000040
52 #define TWE_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
53 #define TWE_CONTROL_CLEAR_PARITY_ERROR 0x00800000
54 #define TWE_CONTROL_CLEAR_PCI_ABORT 0x00100000
56 #define TWE_SOFT_RESET(sc) TWE_CONTROL(sc, TWE_CONTROL_ISSUE_SOFT_RESET | \
57 TWE_CONTROL_CLEAR_HOST_INTERRUPT | \
58 TWE_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
59 TWE_CONTROL_MASK_COMMAND_INTERRUPT | \
60 TWE_CONTROL_MASK_RESPONSE_INTERRUPT | \
61 TWE_CONTROL_CLEAR_ERROR_STATUS | \
62 TWE_CONTROL_DISABLE_INTERRUPTS)
64 /* status register bit definitions */
65 #define TWE_STATUS_MAJOR_VERSION_MASK 0xF0000000
66 #define TWE_STATUS_MINOR_VERSION_MASK 0x0F000000
67 #define TWE_STATUS_PCI_PARITY_ERROR 0x00800000
68 #define TWE_STATUS_QUEUE_ERROR 0x00400000
69 #define TWE_STATUS_MICROCONTROLLER_ERROR 0x00200000
70 #define TWE_STATUS_PCI_ABORT 0x00100000
71 #define TWE_STATUS_HOST_INTERRUPT 0x00080000
72 #define TWE_STATUS_ATTENTION_INTERRUPT 0x00040000
73 #define TWE_STATUS_COMMAND_INTERRUPT 0x00020000
74 #define TWE_STATUS_RESPONSE_INTERRUPT 0x00010000
75 #define TWE_STATUS_COMMAND_QUEUE_FULL 0x00008000
76 #define TWE_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
77 #define TWE_STATUS_MICROCONTROLLER_READY 0x00002000
78 #define TWE_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
79 #define TWE_STATUS_ALL_INTERRUPTS 0x000F0000
80 #define TWE_STATUS_CLEARABLE_BITS 0x00D00000
81 #define TWE_STATUS_EXPECTED_BITS 0x00002000
82 #define TWE_STATUS_UNEXPECTED_BITS 0x00F80000
84 /* XXX this is a little harsh, but necessary to chase down firmware problems */
85 #define TWE_STATUS_PANIC_BITS (TWE_STATUS_MICROCONTROLLER_ERROR)
87 /* for use with the %b kprintf format */
88 #define TWE_STATUS_BITS_DESCRIPTION \
89 "\20\15CQEMPTY\16UCREADY\17RQEMPTY\20CQFULL\21RINTR\22CINTR\23AINTR\24HINTR\25PCIABRT\26MCERR\27QERR\30PCIPERR\n"
91 /* detect inconsistencies in the status register */
92 #define TWE_STATUS_ERRORS(x) \
93 (((x & TWE_STATUS_PCI_ABORT) || \
94 (x & TWE_STATUS_PCI_PARITY_ERROR) || \
95 (x & TWE_STATUS_QUEUE_ERROR) || \
96 (x & TWE_STATUS_MICROCONTROLLER_ERROR)) && \
97 (x & TWE_STATUS_MICROCONTROLLER_READY))
99 /* Response queue bit definitions */
100 #define TWE_RESPONSE_ID_MASK 0x00000FF0
102 /* PCI related defines */
103 #define TWE_IO_CONFIG_REG 0x10
104 #define TWE_DEVICE_NAME "3ware Storage Controller"
105 #define TWE_VENDOR_ID 0x13C1
106 #define TWE_DEVICE_ID 0x1000
107 #define TWE_DEVICE_ID_ASIC 0x1001
108 #define TWE_PCI_CLEAR_PARITY_ERROR 0xc100
109 #define TWE_PCI_CLEAR_PCI_ABORT 0x2000
111 /* command packet opcodes */
112 #define TWE_OP_NOP 0x00
113 #define TWE_OP_INIT_CONNECTION 0x01
114 #define TWE_OP_READ 0x02
115 #define TWE_OP_WRITE 0x03
116 #define TWE_OP_READVERIFY 0x04
117 #define TWE_OP_VERIFY 0x05
118 #define TWE_OP_ZEROUNIT 0x08
119 #define TWE_OP_REPLACEUNIT 0x09
120 #define TWE_OP_HOTSWAP 0x0a
121 #define TWE_OP_SETATAFEATURE 0x0c
122 #define TWE_OP_FLUSH 0x0e
123 #define TWE_OP_ABORT 0x0f
124 #define TWE_OP_CHECKSTATUS 0x10
125 #define TWE_OP_ATA_PASSTHROUGH 0x11
126 #define TWE_OP_GET_PARAM 0x12
127 #define TWE_OP_SET_PARAM 0x13
128 #define TWE_OP_CREATEUNIT 0x14
129 #define TWE_OP_DELETEUNIT 0x15
130 #define TWE_OP_REBUILDUNIT 0x17
131 #define TWE_OP_SECTOR_INFO 0x1a
132 #define TWE_OP_AEN_LISTEN 0x1c
133 #define TWE_OP_CMD_PACKET 0x1d
134 #define TWE_OP_CMD_WITH_DATA 0x1f
136 /* command status values */
137 #define TWE_STATUS_RESET 0xff /* controller requests reset */
138 #define TWE_STATUS_FATAL 0xc0 /* fatal errors not requiring reset */
139 #define TWE_STATUS_WARNING 0x80 /* warnings */
140 #define TWE_STAUS_INFO 0x40 /* informative status */
142 /* misc defines */
143 #define TWE_ALIGNMENT 0x200
144 #define TWE_ALIGNMASK (TWE_ALIGNMENT - 1)
145 #define TWE_MAX_UNITS 16
146 #define TWE_COMMAND_ALIGNMENT_MASK 0x1ff
147 #define TWE_INIT_MESSAGE_CREDITS 0xff /* older firmware has issues with 256 commands */
148 #define TWE_SHUTDOWN_MESSAGE_CREDITS 0x001
149 #define TWE_INIT_COMMAND_PACKET_SIZE 0x3
150 #define TWE_MAX_SGL_LENGTH 62
151 #define TWE_MAX_ATA_SGL_LENGTH 60
152 #define TWE_MAX_PASSTHROUGH 4096
153 #define TWE_Q_LENGTH TWE_INIT_MESSAGE_CREDITS
154 #define TWE_Q_START 0
155 #define TWE_MAX_RESET_TRIES 3
156 #define TWE_BLOCK_SIZE 0x200 /* 512-byte blocks */
157 #define TWE_SECTOR_SIZE 0x200 /* generic I/O bufffer */
158 #define TWE_IOCTL 0x80
159 #define TWE_MAX_AEN_TRIES 100
160 #define TWE_UNIT_ONLINE 1
162 /* scatter/gather list entry */
163 typedef struct
165 u_int32_t address;
166 u_int32_t length;
167 } __attribute__ ((packed)) TWE_SG_Entry;
169 typedef struct {
170 u_int8_t opcode:5; /* TWE_OP_INITCONNECTION */
171 u_int8_t res1:3;
172 u_int8_t size;
173 u_int8_t request_id;
174 u_int8_t res2:4;
175 u_int8_t host_id:4;
176 u_int8_t status;
177 u_int8_t flags;
178 u_int16_t message_credits;
179 u_int32_t response_queue_pointer;
180 } __attribute__ ((packed)) TWE_Command_INITCONNECTION;
182 typedef struct
184 u_int8_t opcode:5; /* TWE_OP_READ/TWE_OP_WRITE */
185 u_int8_t res1:3;
186 u_int8_t size;
187 u_int8_t request_id;
188 u_int8_t unit:4;
189 u_int8_t host_id:4;
190 u_int8_t status;
191 u_int8_t flags;
192 u_int16_t block_count;
193 u_int32_t lba;
194 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
195 } __attribute__ ((packed)) TWE_Command_IO;
197 typedef struct
199 u_int8_t opcode:5; /* TWE_OP_HOTSWAP */
200 u_int8_t res1:3;
201 u_int8_t size;
202 u_int8_t request_id;
203 u_int8_t unit:4;
204 u_int8_t host_id:4;
205 u_int8_t status;
206 u_int8_t flags;
207 u_int8_t action;
208 #define TWE_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */
209 #define TWE_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */
210 #define TWE_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */
211 u_int8_t aport;
212 } __attribute__ ((packed)) TWE_Command_HOTSWAP;
214 typedef struct
216 u_int8_t opcode:5; /* TWE_OP_SETATAFEATURE */
217 u_int8_t res1:3;
218 u_int8_t size;
219 u_int8_t request_id;
220 u_int8_t unit:4;
221 u_int8_t host_id:4;
222 u_int8_t status;
223 u_int8_t flags;
224 u_int8_t feature;
225 #define TWE_OP_SETATAFEATURE_WCE 0x02
226 #define TWE_OP_SETATAFEATURE_DIS_WCE 0x82
227 u_int8_t feature_mode;
228 u_int16_t all_units;
229 u_int16_t persistence;
230 } __attribute__ ((packed)) TWE_Command_SETATAFEATURE;
232 typedef struct
234 u_int8_t opcode:5; /* TWE_OP_CHECKSTATUS */
235 u_int8_t res1:3;
236 u_int8_t size;
237 u_int8_t request_id;
238 u_int8_t unit:4;
239 u_int8_t res2:4;
240 u_int8_t status;
241 u_int8_t flags;
242 u_int16_t target_status; /* set low byte to target request's ID */
243 } __attribute__ ((packed)) TWE_Command_CHECKSTATUS;
245 typedef struct
247 u_int8_t opcode:5; /* TWE_OP_GETPARAM, TWE_OP_SETPARAM */
248 u_int8_t res1:3;
249 u_int8_t size;
250 u_int8_t request_id;
251 u_int8_t unit:4;
252 u_int8_t host_id:4;
253 u_int8_t status;
254 u_int8_t flags;
255 u_int16_t param_count;
256 TWE_SG_Entry sgl[TWE_MAX_SGL_LENGTH];
257 } __attribute__ ((packed)) TWE_Command_PARAM;
259 typedef struct
261 u_int8_t opcode:5; /* TWE_OP_REBUILDUNIT */
262 u_int8_t res1:3;
263 u_int8_t size;
264 u_int8_t request_id;
265 u_int8_t src_unit:4;
266 u_int8_t host_id:4;
267 u_int8_t status;
268 u_int8_t flags;
269 u_int8_t action:7;
270 #define TWE_OP_REBUILDUNIT_NOP 0
271 #define TWE_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */
272 #define TWE_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */
273 #define TWE_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */
274 u_int8_t cs:1; /* request state change on src_unit */
275 u_int8_t logical_subunit; /* for RAID10 rebuild of logical subunit */
276 } __attribute__ ((packed)) TWE_Command_REBUILDUNIT;
278 typedef struct
280 u_int8_t opcode:5;
281 u_int8_t sgl_offset:3;
282 u_int8_t size;
283 u_int8_t request_id;
284 u_int8_t unit:4;
285 u_int8_t host_id:4;
286 u_int8_t status;
287 u_int8_t flags;
288 u_int16_t param;
289 u_int16_t features;
290 u_int16_t sector_count;
291 u_int16_t sector_num;
292 u_int16_t cylinder_lo;
293 u_int16_t cylinder_hi;
294 u_int8_t drive_head;
295 u_int8_t command;
296 TWE_SG_Entry sgl[TWE_MAX_ATA_SGL_LENGTH];
297 } __attribute__ ((packed)) TWE_Command_ATA;
299 typedef struct
301 u_int8_t opcode:5;
302 u_int8_t sgl_offset:3;
303 u_int8_t size;
304 u_int8_t request_id;
305 u_int8_t unit:4;
306 u_int8_t host_id:4;
307 u_int8_t status;
308 u_int8_t flags;
309 #define TWE_FLAGS_SUCCESS 0x00
310 #define TWE_FLAGS_INFORMATIONAL 0x01
311 #define TWE_FLAGS_WARNING 0x02
312 #define TWE_FLAGS_FATAL 0x03
313 #define TWE_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */
314 u_int16_t count; /* block count, parameter count, message credits */
315 } __attribute__ ((packed)) TWE_Command_Generic;
317 /* command packet - must be TWE_ALIGNMENT aligned */
318 typedef union
320 TWE_Command_INITCONNECTION initconnection;
321 TWE_Command_IO io;
322 TWE_Command_PARAM param;
323 TWE_Command_CHECKSTATUS checkstatus;
324 TWE_Command_REBUILDUNIT rebuildunit;
325 TWE_Command_SETATAFEATURE setatafeature;
326 TWE_Command_ATA ata;
327 TWE_Command_Generic generic;
328 u_int8_t pad[512];
329 } TWE_Command;
331 /* response queue entry */
332 typedef union
334 struct
336 u_int32_t undefined_1:4;
337 u_int32_t response_id:8;
338 u_int32_t undefined_2:20;
339 } u;
340 u_int32_t value;
341 } TWE_Response_Queue;
344 * From 3ware's documentation:
345 * All parameters maintained by the controller are grouped into related tables.
346 * Tables are are accessed indirectly via get and set parameter commands.
347 * To access a specific parameter in a table, the table ID and parameter index
348 * are used to uniquely identify a parameter. Table 0xffff is the directory
349 * table and provides a list of the table IDs and sizes of all other tables.
350 * Index zero in each table specifies the entire table, and index one specifies
351 * the size of the table. An entire table can be read or set by using index zero.
354 #define TWE_PARAM_PARAM_ALL 0
355 #define TWE_PARAM_PARAM_SIZE 1
357 #define TWE_PARAM_DIRECTORY 0xffff /* size is 4 * number of tables */
358 #define TWE_PARAM_DIRECTORY_TABLES 2 /* 16 bits * number of tables */
359 #define TWE_PARAM_DIRECTORY_SIZES 3 /* 16 bits * number of tables */
361 #define TWE_PARAM_DRIVESUMMARY 0x0002
362 #define TWE_PARAM_DRIVESUMMARY_Num 2 /* number of physical drives [2] */
363 #define TWE_PARAM_DRIVESUMMARY_Status 3 /* array giving drive status per aport */
364 #define TWE_PARAM_DRIVESTATUS_Missing 0x00
365 #define TWE_PARAM_DRIVESTATUS_NotSupp 0xfe
366 #define TWE_PARAM_DRIVESTATUS_Present 0xff
368 #define TWE_PARAM_UNITSUMMARY 0x0003
369 #define TWE_PARAM_UNITSUMMARY_Num 2 /* number of logical units [2] */
370 #define TWE_PARAM_UNITSUMMARY_Status 3 /* array giving unit status [16] */
371 #define TWE_PARAM_UNITSTATUS_Online (1<<0)
372 #define TWE_PARAM_UNITSTATUS_Complete (1<<1)
373 #define TWE_PARAM_UNITSTATUS_MASK 0xfc
374 #define TWE_PARAM_UNITSTATUS_Normal 0xfc
375 #define TWE_PARAM_UNITSTATUS_Initialising 0xf4 /* cannot be incomplete */
376 #define TWE_PARAM_UNITSTATUS_Degraded 0xec
377 #define TWE_PARAM_UNITSTATUS_Rebuilding 0xdc /* cannot be incomplete */
378 #define TWE_PARAM_UNITSTATUS_Verifying 0xcc /* cannot be incomplete */
379 #define TWE_PARAM_UNITSTATUS_Corrupt 0xbc /* cannot be complete */
380 #define TWE_PARAM_UNITSTATUS_Missing 0x00 /* cannot be complete or online */
382 #define TWE_PARAM_DRIVEINFO 0x0200 /* add drive number 0x00-0x0f XXX docco confused 0x0100 vs 0x0200 */
383 #define TWE_PARAM_DRIVEINFO_Size 2 /* size in blocks [4] */
384 #define TWE_PARAM_DRIVEINFO_Model 3 /* drive model string [40] */
385 #define TWE_PARAM_DRIVEINFO_Serial 4 /* drive serial number [20] */
386 #define TWE_PARAM_DRIVEINFO_PhysCylNum 5 /* physical geometry [2] */
387 #define TWE_PARAM_DRIVEINFO_PhysHeadNum 6 /* [2] */
388 #define TWE_PARAM_DRIVEINFO_PhysSectorNym 7 /* [2] */
389 #define TWE_PARAM_DRIVEINFO_LogCylNum 8 /* logical geometry [2] */
390 #define TWE_PARAM_DRIVEINFO_LogHeadNum 9 /* [2] */
391 #define TWE_PARAM_DRIVEINFO_LogSectorNum 10 /* [2] */
392 #define TWE_PARAM_DRIVEINFO_UnitNum 11 /* unit number this drive is associated with or 0xff [1] */
393 #define TWE_PARAM_DRIVEINFO_DriveFlags 12 /* N/A [1] */
395 #define TWE_PARAM_APORTTIMEOUT 0x02c0 /* add (aport_number * 3) to parameter index */
396 #define TWE_PARAM_APORTTIMEOUT_READ 2 /* read timeouts last 24hrs [2] */
397 #define TWE_PARAM_APORTTIMEOUT_WRITE 3 /* write timeouts last 24hrs [2] */
398 #define TWE_PARAM_APORTTIMEOUT_DEGRADE 4 /* degrade threshold [2] */
400 #define TWE_PARAM_UNITINFO 0x0300 /* add unit number 0x00-0x0f */
401 #define TWE_PARAM_UNITINFO_Number 2 /* unit number [1] */
402 #define TWE_PARAM_UNITINFO_Status 3 /* unit status [1] */
403 #define TWE_PARAM_UNITINFO_Capacity 4 /* unit capacity in blocks [4] */
404 #define TWE_PARAM_UNITINFO_DescriptorSize 5 /* unit descriptor size + 3 bytes [2] */
405 #define TWE_PARAM_UNITINFO_Descriptor 6 /* unit descriptor, TWE_UnitDescriptor or TWE_Array_Descriptor */
406 #define TWE_PARAM_UNITINFO_Flags 7 /* unit flags [1] */
407 #define TWE_PARAM_UNITFLAGS_WCE (1<<0)
409 #define TWE_PARAM_AEN 0x0401
410 #define TWE_PARAM_AEN_UnitCode 2 /* (unit number << 8) | AEN code [2] */
411 #define TWE_AEN_QUEUE_EMPTY 0x00
412 #define TWE_AEN_SOFT_RESET 0x01
413 #define TWE_AEN_DEGRADED_MIRROR 0x02 /* reports unit */
414 #define TWE_AEN_CONTROLLER_ERROR 0x03
415 #define TWE_AEN_REBUILD_FAIL 0x04 /* reports unit */
416 #define TWE_AEN_REBUILD_DONE 0x05 /* reports unit */
417 #define TWE_AEN_INCOMP_UNIT 0x06 /* reports unit */
418 #define TWE_AEN_INIT_DONE 0x07 /* reports unit */
419 #define TWE_AEN_UNCLEAN_SHUTDOWN 0x08 /* reports unit */
420 #define TWE_AEN_APORT_TIMEOUT 0x09 /* reports unit, rate limited to 1 per 2^16 errors */
421 #define TWE_AEN_DRIVE_ERROR 0x0a /* reports unit */
422 #define TWE_AEN_REBUILD_STARTED 0x0b /* reports unit */
423 #define TWE_AEN_QUEUE_FULL 0xff
424 #define TWE_AEN_TABLE_UNDEFINED 0x15
425 #define TWE_AEN_CODE(x) ((x) & 0xff)
426 #define TWE_AEN_UNIT(x) ((x) >> 8)
428 #define TWE_PARAM_VERSION 0x0402
429 #define TWE_PARAM_VERSION_Mon 2 /* monitor version [16] */
430 #define TWE_PARAM_VERSION_FW 3 /* firmware version [16] */
431 #define TWE_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
432 #define TWE_PARAM_VERSION_PCB 5 /* PCB version [8] */
433 #define TWE_PARAM_VERSION_ATA 6 /* A-chip version [8] */
434 #define TWE_PARAM_VERSION_PCI 7 /* P-chip version [8] */
435 #define TWE_PARAM_VERSION_CtrlModel 8 /* N/A */
436 #define TWE_PARAM_VERSION_CtrlSerial 9 /* N/A */
437 #define TWE_PARAM_VERSION_SBufSize 10 /* N/A */
438 #define TWE_PARAM_VERSION_CompCode 11 /* compatibility code [4] */
440 #define TWE_PARAM_CONTROLLER 0x0403
441 #define TWE_PARAM_CONTROLLER_DCBSectors 2 /* # sectors reserved for DCB per drive [2] */
442 #define TWE_PARAM_CONTROLLER_PortCount 3 /* number of drive ports [1] */
444 #define TWE_PARAM_FEATURES 0x404
445 #define TWE_PARAM_FEATURES_DriverShutdown 2 /* set to 1 if driver supports shutdown notification [1] */
447 typedef struct
449 u_int8_t num_subunits; /* must be zero */
450 u_int8_t configuration;
451 #define TWE_UD_CONFIG_CBOD 0x0c /* JBOD with DCB, used for mirrors */
452 #define TWE_UD_CONFIG_SPARE 0x0d /* same as CBOD, but firmware will use as spare */
453 #define TWE_UD_CONFIG_SUBUNIT 0x0e /* drive is a subunit in an array */
454 #define TWE_UD_CONFIG_JBOD 0x0f /* plain drive */
455 u_int8_t phys_drv_num; /* may be 0xff if port can't be determined at runtime */
456 u_int8_t log_drv_num; /* must be zero for configuration == 0x0f */
457 u_int32_t start_lba;
458 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
459 } __attribute__ ((packed)) TWE_Unit_Descriptor;
461 typedef struct
463 u_int8_t flag; /* must be 0xff */
464 u_int8_t res1;
465 u_int8_t mirunit_status[4]; /* bitmap of functional subunits in each mirror */
466 u_int8_t res2[6];
467 } __attribute__ ((packed)) TWE_Mirror_Descriptor;
469 typedef struct
471 u_int8_t num_subunits; /* number of subunits, or number of mirror units in RAID10 */
472 u_int8_t configuration;
473 #define TWE_UD_CONFIG_RAID0 0x00
474 #define TWE_UD_CONFIG_RAID1 0x01
475 #define TWE_UD_CONFIG_TwinStor 0x02
476 #define TWE_UD_CONFIG_RAID5 0x05
477 #define TWE_UD_CONFIG_RAID10 0x06
478 u_int8_t stripe_size;
479 #define TWE_UD_STRIPE_4k 0x03
480 #define TWE_UD_STRIPE_8k 0x04
481 #define TWE_UD_STRIPE_16k 0x05
482 #define TWE_UD_STRIPE_32k 0x06
483 #define TWE_UD_STRIPE_64k 0x07
484 u_int8_t log_drv_status; /* bitmap of functional subunits, or mirror units in RAID10 */
485 u_int32_t start_lba;
486 u_int32_t block_count; /* actual drive size if configuration == 0x0f, otherwise less DCB size */
487 TWE_Unit_Descriptor subunit[0]; /* subunit descriptors, in RAID10 mode is [mirunit][subunit] */
488 } __attribute__ ((packed)) TWE_Array_Descriptor;
490 typedef struct
492 u_int16_t table_id;
493 u_int8_t parameter_id;
494 u_int8_t parameter_size_bytes;
495 u_int8_t data[0];
496 } __attribute__ ((packed)) TWE_Param;