| blob | 464c342e417ac493bf6f275238920d24ec780884 |
1 /*
2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.seq,v 1.15 2004/02/04 16:38:38 gibbs Exp $
41 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.seq,v 1.6 2007/07/06 00:56:38 pavalos Exp $
42 */
44 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#118 $"
45 PATCH_ARG_LIST = "struct ahd_softc *ahd"
46 PREFIX = "ahd_"
48 #include "aic79xx.reg"
49 #include "scsi_message.h"
51 restart:
52 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
53 test SEQINTCODE, 0xFF jz idle_loop;
54 SET_SEQINTCODE(NO_SEQINT)
55 }
57 idle_loop:
59 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60 /*
61 * Convert ERROR status into a sequencer
62 * interrupt to handle the case of an
63 * interrupt collision on the hardware
64 * setting of HWERR.
65 */
66 test ERROR, 0xFF jz no_error_set;
67 SET_SEQINTCODE(SAW_HWERR)
68 no_error_set:
69 }
70 SET_MODE(M_SCSI, M_SCSI)
71 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
72 test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
73 /*
74 * If the kernel has caught up with us, thaw the queue.
75 */
76 mov A, KERNEL_QFREEZE_COUNT;
77 cmp QFREEZE_COUNT, A jne check_frozen_completions;
78 mov A, KERNEL_QFREEZE_COUNT[1];
79 cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
80 and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
81 jmp check_waiting_list;
82 check_frozen_completions:
83 test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
84 BEGIN_CRITICAL;
85 /*
86 * If we have completions stalled waiting for the qfreeze
87 * to take effect, move them over to the complete_scb list
88 * now that no selections are pending.
89 */
90 cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
91 /*
92 * Find the end of the qfreeze list. The first element has
93 * to be treated specially.
94 */
95 bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
96 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
97 /*
98 * Now the normal loop.
99 */
100 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
101 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
102 join_lists:
103 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
104 bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
105 mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
106 jmp idle_loop_checkbus;
107 check_waiting_list:
108 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
109 /*
110 * ENSELO is cleared by a SELDO, so we must test for SELDO
111 * one last time.
112 */
113 test SSTAT0, SELDO jnz select_out;
114 END_CRITICAL;
115 call start_selection;
116 idle_loop_checkbus:
117 BEGIN_CRITICAL;
118 test SSTAT0, SELDO jnz select_out;
119 END_CRITICAL;
120 test SSTAT0, SELDI jnz select_in;
121 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
122 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
123 call unexpected_nonpkt_phase_find_ctxt;
124 idle_loop_check_nonpackreq:
125 test SSTAT2, NONPACKREQ jz . + 2;
126 call unexpected_nonpkt_phase_find_ctxt;
127 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
128 /*
129 * On Rev A. hardware, the busy LED is only
130 * turned on automaically during selections
131 * and re-selections. Make the LED status
132 * more useful by forcing it to be on so
133 * long as one of our data FIFOs is active.
134 */
135 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
136 cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
137 and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
138 jmp . + 2;
139 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
140 }
141 call idle_loop_gsfifo_in_scsi_mode;
142 call idle_loop_service_fifos;
143 call idle_loop_cchan;
144 jmp idle_loop;
146 idle_loop_gsfifo:
147 SET_MODE(M_SCSI, M_SCSI)
148 BEGIN_CRITICAL;
149 idle_loop_gsfifo_in_scsi_mode:
150 test LQISTAT2, LQIGSAVAIL jz return;
151 /*
152 * We have received good status for this transaction. There may
153 * still be data in our FIFOs draining to the host. Complete
154 * the SCB only if all data has transferred to the host.
155 */
156 good_status_IU_done:
157 bmov SCBPTR, GSFIFO, 2;
158 clr SCB_SCSI_STATUS;
159 /*
160 * If a command completed before an attempted task management
161 * function completed, notify the host after disabling any
162 * pending select-outs.
163 */
164 test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
165 test SSTAT0, SELDO|SELINGO jnz . + 2;
166 and SCSISEQ0, ~ENSELO;
167 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
168 gsfifo_complete_normally:
169 or SCB_CONTROL, STATUS_RCVD;
171 /*
172 * Since this status did not consume a FIFO, we have to
173 * be a bit more dilligent in how we check for FIFOs pertaining
174 * to this transaction. There are two states that a FIFO still
175 * transferring data may be in.
176 *
177 * 1) Configured and draining to the host, with a FIFO handler.
178 * 2) Pending cfg4data, fifo not empty.
179 *
180 * Case 1 can be detected by noticing a non-zero FIFO active
181 * count in the SCB. In this case, we allow the routine servicing
182 * the FIFO to complete the SCB.
183 *
184 * Case 2 implies either a pending or yet to occur save data
185 * pointers for this same context in the other FIFO. So, if
186 * we detect case 1, we will properly defer the post of the SCB
187 * and achieve the desired result. The pending cfg4data will
188 * notice that status has been received and complete the SCB.
189 */
190 test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
191 call complete;
192 END_CRITICAL;
193 jmp idle_loop_gsfifo_in_scsi_mode;
195 idle_loop_service_fifos:
196 SET_MODE(M_DFF0, M_DFF0)
197 BEGIN_CRITICAL;
198 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
199 call longjmp;
200 END_CRITICAL;
201 idle_loop_next_fifo:
202 SET_MODE(M_DFF1, M_DFF1)
203 BEGIN_CRITICAL;
204 test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
205 END_CRITICAL;
206 return:
207 ret;
209 idle_loop_cchan:
210 SET_MODE(M_CCHAN, M_CCHAN)
211 test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
212 or QOFF_CTLSTA, HS_MAILBOX_ACT;
213 mov LOCAL_HS_MAILBOX, HS_MAILBOX;
214 hs_mailbox_empty:
215 BEGIN_CRITICAL;
216 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
217 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
218 test CCSCBCTL, CCSCBDONE jz return;
219 /* FALLTHROUGH */
220 scbdma_tohost_done:
221 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
222 /*
223 * An SCB has been succesfully uploaded to the host.
224 * If the SCB was uploaded for some reason other than
225 * bad SCSI status (currently only for underruns), we
226 * queue the SCB for normal completion. Otherwise, we
227 * wait until any select-out activity has halted, and
228 * then queue the completion.
229 */
230 and CCSCBCTL, ~(CCARREN|CCSCBEN);
231 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
232 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
233 mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
234 test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
235 bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
236 bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
237 scbdma_queue_completion:
238 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
239 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
240 fill_qoutfifo_dmadone:
241 and CCSCBCTL, ~(CCARREN|CCSCBEN);
242 call qoutfifo_updated;
243 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
244 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
245 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
246 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
247 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
248 END_CRITICAL;
250 qoutfifo_updated:
251 /*
252 * If there are more commands waiting to be dma'ed
253 * to the host, always coalesce. Otherwise honor the
254 * host's wishes.
255 */
256 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
257 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
258 test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
260 /*
261 * If we have relatively few commands outstanding, don't
262 * bother waiting for another command to complete.
263 */
264 test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
265 /* Add -1 so that jnc means <= not just < */
266 add A, -1, INT_COALESCING_MINCMDS;
267 add NONE, A, CMDS_PENDING;
268 jnc issue_cmdcmplt;
270 /*
271 * If coalescing, only coalesce up to the limit
272 * provided by the host driver.
273 */
274 coalesce_by_count:
275 mov A, INT_COALESCING_MAXCMDS;
276 add NONE, A, INT_COALESCING_CMDCOUNT;
277 jc issue_cmdcmplt;
278 /*
279 * If the timer is not currently active,
280 * fire it up.
281 */
282 test INTCTL, SWTMINTMASK jz return;
283 bmov SWTIMER, INT_COALESCING_TIMER, 2;
284 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
285 or INTCTL, SWTMINTEN|SWTIMER_START;
286 and INTCTL, ~SWTMINTMASK ret;
288 issue_cmdcmplt:
289 mvi INTSTAT, CMDCMPLT;
290 clr INT_COALESCING_CMDCOUNT;
291 or INTCTL, SWTMINTMASK ret;
293 BEGIN_CRITICAL;
294 fetch_new_scb_inprog:
295 test CCSCBCTL, ARRDONE jz return;
296 fetch_new_scb_done:
297 and CCSCBCTL, ~(CCARREN|CCSCBEN);
298 bmov REG0, SCBPTR, 2;
299 clr A;
300 add CMDS_PENDING, 1;
301 adc CMDS_PENDING[1], A;
302 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
303 /*
304 * "Short Luns" are not placed into outgoing LQ
305 * packets in the correct byte order. Use a full
306 * sized lun field instead and fill it with the
307 * one byte of lun information we support.
308 */
309 mov SCB_PKT_LUN[6], SCB_LUN;
310 }
311 /*
312 * The FIFO use count field is shared with the
313 * tag set by the host so that our SCB dma engine
314 * knows the correct location to store the SCB.
315 * Set it to zero before processing the SCB.
316 */
317 clr SCB_FIFO_USE_COUNT;
318 /* Update the next SCB address to download. */
319 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
320 mvi SCB_NEXT[1], SCB_LIST_NULL;
321 mvi SCB_NEXT2[1], SCB_LIST_NULL;
322 /* Increment our position in the QINFIFO. */
323 mov NONE, SNSCB_QOFF;
324 /*
325 * SCBs that want to send messages are always
326 * queued independently. This ensures that they
327 * are at the head of the SCB list to select out
328 * to a target and we will see the MK_MESSAGE flag.
329 */
330 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
331 shr SINDEX, 3, SCB_SCSIID;
332 and SINDEX, ~0x1;
333 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
334 bmov DINDEX, SINDEX, 2;
335 bmov SCBPTR, SINDIR, 2;
336 bmov DINDIR, REG0, 2;
337 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
338 bmov SCB_NEXT, REG0, 2 ret;
339 first_new_target_scb:
340 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
341 bmov SCBPTR, WAITING_TID_TAIL, 2;
342 bmov SCB_NEXT2, REG0, 2;
343 bmov WAITING_TID_TAIL, REG0, 2 ret;
344 first_new_scb:
345 bmov WAITING_TID_HEAD, REG0, 2;
346 bmov WAITING_TID_TAIL, REG0, 2 ret;
347 END_CRITICAL;
349 scbdma_idle:
350 /*
351 * Give precedence to downloading new SCBs to execute
352 * unless select-outs are currently frozen.
353 */
354 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
355 BEGIN_CRITICAL;
356 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
357 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
358 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
359 /* FALLTHROUGH */
360 fill_qoutfifo:
361 /*
362 * Keep track of the SCBs we are dmaing just
363 * in case the DMA fails or is aborted.
364 */
365 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
366 mvi CCSCBCTL, CCSCBRESET;
367 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
368 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
369 fill_qoutfifo_loop:
370 bmov CCSCBRAM, SCBPTR, 2;
371 mov CCSCBRAM, SCB_SGPTR[0];
372 bmov CCSCBRAM, ALLZEROS, 4;
373 mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
374 mov NONE, SDSCB_QOFF;
375 inc INT_COALESCING_CMDCOUNT;
376 add CMDS_PENDING, -1;
377 adc CMDS_PENDING[1], -1;
378 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
379 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
380 test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
381 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
382 jmp fill_qoutfifo_loop;
383 fill_qoutfifo_done:
384 mov SCBHCNT, CCSCBADDR;
385 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
386 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
387 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
389 fetch_new_scb:
390 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
391 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
392 dma_complete_scb:
393 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
394 bmov SCBHADDR, SCB_BUSADDR, 4;
395 mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
397 /*
398 * Either post or fetch an SCB from host memory. The caller
399 * is responsible for polling for transfer completion.
400 *
401 * Prerequisits: Mode == M_CCHAN
402 * SINDEX contains CCSCBCTL flags
403 * SCBHADDR set to Host SCB address
404 * SCBPTR set to SCB src location on "push" operations
405 */
406 SET_SRC_MODE M_CCHAN;
407 SET_DST_MODE M_CCHAN;
408 dma_scb:
409 mvi SCBHCNT, SCB_TRANSFER_SIZE;
410 mov CCSCBCTL, SINDEX ret;
412 setjmp:
413 /*
414 * At least on the A, a return in the same
415 * instruction as the bmov results in a return
416 * to the caller, not to the new address at the
417 * top of the stack. Since we want the latter
418 * (we use setjmp to register a handler from an
419 * interrupt context but not invoke that handler
420 * until we return to our idle loop), use a
421 * separate ret instruction.
422 */
423 bmov LONGJMP_ADDR, STACK, 2;
424 ret;
425 setjmp_inline:
426 bmov LONGJMP_ADDR, STACK, 2;
427 longjmp:
428 bmov STACK, LONGJMP_ADDR, 2 ret;
429 END_CRITICAL;
431 /*************************** Chip Bug Work Arounds ****************************/
432 /*
433 * Must disable interrupts when setting the mode pointer
434 * register as an interrupt occurring mid update will
435 * fail to store the new mode value for restoration on
436 * an iret.
437 */
438 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
439 set_mode_work_around:
440 mvi SEQINTCTL, INTVEC1DSL;
441 mov MODE_PTR, SINDEX;
442 clr SEQINTCTL ret;
443 }
446 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
447 set_seqint_work_around:
448 mov SEQINTCODE, SINDEX;
449 mvi SEQINTCODE, NO_SEQINT ret;
450 }
452 /************************ Packetized LongJmp Routines *************************/
453 SET_SRC_MODE M_SCSI;
454 SET_DST_MODE M_SCSI;
455 start_selection:
456 BEGIN_CRITICAL;
457 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
458 /*
459 * Razor #494
460 * Rev A hardware fails to update LAST/CURR/NEXTSCB
461 * correctly after a packetized selection in several
462 * situations:
463 *
464 * 1) If only one command existed in the queue, the
465 * LAST/CURR/NEXTSCB are unchanged.
466 *
467 * 2) In a non QAS, protocol allowed phase change,
468 * the queue is shifted 1 too far. LASTSCB is
469 * the last SCB that was correctly processed.
470 *
471 * 3) In the QAS case, if the full list of commands
472 * was successfully sent, NEXTSCB is NULL and neither
473 * CURRSCB nor LASTSCB can be trusted. We must
474 * manually walk the list counting MAXCMDCNT elements
475 * to find the last SCB that was sent correctly.
476 *
477 * To simplify the workaround for this bug in SELDO
478 * handling, we initialize LASTSCB prior to enabling
479 * selection so we can rely on it even for case #1 above.
480 */
481 bmov LASTSCB, WAITING_TID_HEAD, 2;
482 }
483 bmov CURRSCB, WAITING_TID_HEAD, 2;
484 bmov SCBPTR, WAITING_TID_HEAD, 2;
485 shr SELOID, 4, SCB_SCSIID;
486 /*
487 * If we want to send a message to the device, ensure
488 * we are selecting with atn irregardless of our packetized
489 * agreement. Since SPI4 only allows target reset or PPR
490 * messages if this is a packetized connection, the change
491 * to our negotiation table entry for this selection will
492 * be cleared when the message is acted on.
493 */
494 test SCB_CONTROL, MK_MESSAGE jz . + 3;
495 mov NEGOADDR, SELOID;
496 or NEGCONOPTS, ENAUTOATNO;
497 or SCSISEQ0, ENSELO ret;
498 END_CRITICAL;
500 /*
501 * Allocate a FIFO for a non-packetized transaction.
502 * In RevA hardware, both FIFOs must be free before we
503 * can allocate a FIFO for a non-packetized transaction.
504 */
505 allocate_fifo_loop:
506 /*
507 * Do whatever work is required to free a FIFO.
508 */
509 call idle_loop_service_fifos;
510 SET_MODE(M_SCSI, M_SCSI)
511 allocate_fifo:
512 if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
513 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
514 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
515 } else {
516 test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
517 test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
518 mvi DFFSTAT, B_CURRFIFO_0;
519 SET_MODE(M_DFF0, M_DFF0)
520 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
521 }
522 SET_SRC_MODE M_SCSI;
523 SET_DST_MODE M_SCSI;
524 allocate_fifo1:
525 mvi DFFSTAT, CURRFIFO_1;
526 SET_MODE(M_DFF1, M_DFF1)
527 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
529 /*
530 * We have been reselected as an initiator
531 * or selected as a target.
532 */
533 SET_SRC_MODE M_SCSI;
534 SET_DST_MODE M_SCSI;
535 select_in:
536 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
537 /*
538 * On Rev A. hardware, the busy LED is only
539 * turned on automaically during selections
540 * and re-selections. Make the LED status
541 * more useful by forcing it to be on from
542 * the point of selection until our idle
543 * loop determines that neither of our FIFOs
544 * are busy. This handles the non-packetized
545 * case nicely as we will not return to the
546 * idle loop until the busfree at the end of
547 * each transaction.
548 */
549 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
550 }
551 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
552 /*
553 * Test to ensure that the bus has not
554 * already gone free prior to clearing
555 * any stale busfree status. This avoids
556 * a window whereby a busfree just after
557 * a selection could be missed.
558 */
559 test SCSISIGI, BSYI jz . + 2;
560 mvi CLRSINT1,CLRBUSFREE;
561 or SIMODE1, ENBUSFREE;
562 }
563 or SXFRCTL0, SPIOEN;
564 and SAVED_SCSIID, SELID_MASK, SELID;
565 and A, OID, IOWNID;
566 or SAVED_SCSIID, A;
567 mvi CLRSINT0, CLRSELDI;
568 jmp ITloop;
570 /*
571 * We have successfully selected out.
572 *
573 * Clear SELDO.
574 * Dequeue all SCBs sent from the waiting queue
575 * Requeue all SCBs *not* sent to the tail of the waiting queue
576 * Take Razor #494 into account for above.
577 *
578 * In Packetized Mode:
579 * Return to the idle loop. Our interrupt handler will take
580 * care of any incoming L_Qs.
581 *
582 * In Non-Packetize Mode:
583 * Continue to our normal state machine.
584 */
585 SET_SRC_MODE M_SCSI;
586 SET_DST_MODE M_SCSI;
587 select_out:
588 BEGIN_CRITICAL;
589 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
590 /*
591 * On Rev A. hardware, the busy LED is only
592 * turned on automaically during selections
593 * and re-selections. Make the LED status
594 * more useful by forcing it to be on from
595 * the point of re-selection until our idle
596 * loop determines that neither of our FIFOs
597 * are busy. This handles the non-packetized
598 * case nicely as we will not return to the
599 * idle loop until the busfree at the end of
600 * each transaction.
601 */
602 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
603 }
604 /* Clear out all SCBs that have been successfully sent. */
605 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
606 /*
607 * For packetized, the LQO manager clears ENSELO on
608 * the assertion of SELDO. If we are non-packetized,
609 * LASTSCB and CURRSCB are accurate.
610 */
611 test SCSISEQ0, ENSELO jnz use_lastscb;
613 /*
614 * The update is correct for LQOSTAT1 errors. All
615 * but LQOBUSFREE are handled by kernel interrupts.
616 * If we see LQOBUSFREE, return to the idle loop.
617 * Once we are out of the select_out critical section,
618 * the kernel will cleanup the LQOBUSFREE and we will
619 * eventually restart the selection if appropriate.
620 */
621 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
623 /*
624 * On a phase change oustside of packet boundaries,
625 * LASTSCB points to the currently active SCB context
626 * on the bus.
627 */
628 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
630 /*
631 * If the hardware has traversed the whole list, NEXTSCB
632 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
633 * but MAXCMDCNT is accurate. If we stop part way through
634 * the list or only had one command to issue, NEXTSCB[1] is
635 * not NULL and LASTSCB is the last command to go out.
636 */
637 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
639 /*
640 * Brute force walk.
641 */
642 bmov SCBPTR, WAITING_TID_HEAD, 2;
643 mvi SEQINTCTL, INTVEC1DSL;
644 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
645 mov A, MAXCMDCNT;
646 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
647 clr SEQINTCTL;
648 find_lastscb_loop:
649 dec A;
650 test A, 0xFF jz found_last_sent_scb;
651 bmov SCBPTR, SCB_NEXT, 2;
652 jmp find_lastscb_loop;
653 use_lastscb:
654 bmov SCBPTR, LASTSCB, 2;
655 found_last_sent_scb:
656 bmov CURRSCB, SCBPTR, 2;
657 curscb_ww_done:
658 } else {
659 bmov SCBPTR, CURRSCB, 2;
660 }
662 /*
663 * Requeue any SCBs not sent, to the tail of the waiting Q.
664 */
665 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
667 /*
668 * We know that neither the per-TID list nor the list of
669 * TIDs is empty. Use this knowledge to our advantage.
670 */
671 bmov REG0, SCB_NEXT, 2;
672 bmov SCBPTR, WAITING_TID_TAIL, 2;
673 bmov SCB_NEXT2, REG0, 2;
674 bmov WAITING_TID_TAIL, REG0, 2;
675 jmp select_out_inc_tid_q;
677 select_out_list_done:
678 /*
679 * The whole list made it. Just clear our TID's tail pointer
680 * unless we were queued independently due to our need to
681 * send a message.
682 */
683 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
684 shr DINDEX, 3, SCB_SCSIID;
685 or DINDEX, 1; /* Want only the second byte */
686 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
687 mvi DINDIR, SCB_LIST_NULL;
688 select_out_inc_tid_q:
689 bmov SCBPTR, WAITING_TID_HEAD, 2;
690 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
691 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
692 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
693 bmov SCBPTR, CURRSCB, 2;
694 mvi CLRSINT0, CLRSELDO;
695 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
696 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
698 /*
699 * If this is a packetized connection, return to our
700 * idle_loop and let our interrupt handler deal with
701 * any connection setup/teardown issues. The only
702 * exceptions are the case of MK_MESSAGE and task management
703 * SCBs.
704 */
705 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
706 /*
707 * In the A, the LQO manager transitions to LQOSTOP0 even if
708 * we have selected out with ATN asserted and the target
709 * REQs in a non-packet phase.
710 */
711 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
712 test SCSISIGO, ATNO jnz select_out_non_packetized;
713 select_out_no_message:
714 }
715 test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
716 test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
717 SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
718 jmp idle_loop;
720 select_out_non_packetized:
721 /* Non packetized request. */
722 and SCSISEQ0, ~ENSELO;
723 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
724 /*
725 * Test to ensure that the bus has not
726 * already gone free prior to clearing
727 * any stale busfree status. This avoids
728 * a window whereby a busfree just after
729 * a selection could be missed.
730 */
731 test SCSISIGI, BSYI jz . + 2;
732 mvi CLRSINT1,CLRBUSFREE;
733 or SIMODE1, ENBUSFREE;
734 }
735 mov SAVED_SCSIID, SCB_SCSIID;
736 mov SAVED_LUN, SCB_LUN;
737 mvi SEQ_FLAGS, NO_CDB_SENT;
738 END_CRITICAL;
739 or SXFRCTL0, SPIOEN;
741 /*
742 * As soon as we get a successful selection, the target
743 * should go into the message out phase since we have ATN
744 * asserted.
745 */
746 mvi MSG_OUT, MSG_IDENTIFYFLAG;
748 /*
749 * Main loop for information transfer phases. Wait for the
750 * target to assert REQ before checking MSG, C/D and I/O for
751 * the bus phase.
752 */
753 mesgin_phasemis:
754 ITloop:
755 call phase_lock;
757 mov A, LASTPHASE;
759 test A, ~P_DATAIN_DT jz p_data;
760 cmp A,P_COMMAND je p_command;
761 cmp A,P_MESGOUT je p_mesgout;
762 cmp A,P_STATUS je p_status;
763 cmp A,P_MESGIN je p_mesgin;
765 SET_SEQINTCODE(BAD_PHASE)
766 jmp ITloop; /* Try reading the bus again. */
768 /*
769 * Command phase. Set up the DMA registers and let 'er rip.
770 */
771 p_command:
772 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
773 SET_SEQINTCODE(PROTO_VIOLATION)
774 p_command_okay:
775 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
776 jnz p_command_allocate_fifo;
777 /*
778 * Command retry. Free our current FIFO and
779 * re-allocate a FIFO so transfer state is
780 * reset.
781 */
782 SET_SRC_MODE M_DFF1;
783 SET_DST_MODE M_DFF1;
784 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
785 SET_MODE(M_SCSI, M_SCSI)
786 p_command_allocate_fifo:
787 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
788 call allocate_fifo;
789 SET_SRC_MODE M_DFF1;
790 SET_DST_MODE M_DFF1;
791 add NONE, -17, SCB_CDB_LEN;
792 jnc p_command_embedded;
793 p_command_from_host:
794 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
795 mvi SG_CACHE_PRE, LAST_SEG;
796 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
797 jmp p_command_xfer;
798 p_command_embedded:
799 bmov SHCNT[0], SCB_CDB_LEN, 1;
800 bmov DFDAT, SCB_CDB_STORE, 16;
801 mvi DFCNTRL, SCSIEN;
802 p_command_xfer:
803 and SEQ_FLAGS, ~NO_CDB_SENT;
804 if ((ahd->features & AHD_FAST_CDB_DELIVERY) != 0) {
805 /*
806 * To speed up CDB delivery in Rev B, all CDB acks
807 * are "released" to the output sync as soon as the
808 * command phase starts. There is only one problem
809 * with this approach. If the target changes phase
810 * before all data are sent, we have left over acks
811 * that can go out on the bus in a data phase. Due
812 * to other chip contraints, this only happens if
813 * the target goes to data-in, but if the acks go
814 * out before we can test SDONE, we'll think that
815 * the transfer has completed successfully. Work
816 * around this by taking advantage of the 400ns or
817 * 800ns dead time between command phase and the REQ
818 * of the new phase. If the transfer has completed
819 * successfully, SCSIEN should fall *long* before we
820 * see a phase change. We thus treat any phasemiss
821 * that occurs before SCSIEN falls as an incomplete
822 * transfer.
823 */
824 test SSTAT1, PHASEMIS jnz p_command_xfer_failed;
825 test DFCNTRL, SCSIEN jnz . - 1;
826 } else {
827 test DFCNTRL, SCSIEN jnz .;
828 }
829 /*
830 * DMA Channel automatically disabled.
831 * Don't allow a data phase if the command
832 * was not fully transferred.
833 */
834 test SSTAT2, SDONE jnz ITloop;
835 p_command_xfer_failed:
836 or SEQ_FLAGS, NO_CDB_SENT;
837 jmp ITloop;
840 /*
841 * Status phase. Wait for the data byte to appear, then read it
842 * and store it into the SCB.
843 */
844 SET_SRC_MODE M_SCSI;
845 SET_DST_MODE M_SCSI;
846 p_status:
847 test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
848 p_status_okay:
849 mov SCB_SCSI_STATUS, SCSIDAT;
850 or SCB_CONTROL, STATUS_RCVD;
851 jmp ITloop;
853 /*
854 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
855 * indentify message sequence and send it to the target. The host may
856 * override this behavior by setting the MK_MESSAGE bit in the SCB
857 * control byte. This will cause us to interrupt the host and allow
858 * it to handle the message phase completely on its own. If the bit
859 * associated with this target is set, we will also interrupt the host,
860 * thereby allowing it to send a message on the next selection regardless
861 * of the transaction being sent.
862 *
863 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
864 * This is done to allow the host to send messages outside of an identify
865 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
866 * on an SCB that might not be for the current nexus. (For example, a
867 * BDR message in responce to a bad reselection would leave us pointed to
868 * an SCB that doesn't have anything to do with the current target).
869 *
870 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
871 * bus device reset).
872 *
873 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
874 * in case the target decides to put us in this phase for some strange
875 * reason.
876 */
877 p_mesgout_retry:
878 /* Turn on ATN for the retry */
879 mvi SCSISIGO, ATNO;
880 p_mesgout:
881 mov SINDEX, MSG_OUT;
882 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
883 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
884 p_mesgout_identify:
885 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
886 test SCB_CONTROL, DISCENB jnz . + 2;
887 and SINDEX, ~DISCENB;
888 /*
889 * Send a tag message if TAG_ENB is set in the SCB control block.
890 * Use SCB_NONPACKET_TAG as the tag value.
891 */
892 p_mesgout_tag:
893 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
894 mov SCSIDAT, SINDEX; /* Send the identify message */
895 call phase_lock;
896 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
897 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
898 call phase_lock;
899 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
900 mov SCBPTR jmp p_mesgout_onebyte;
901 /*
902 * Interrupt the driver, and allow it to handle this message
903 * phase and any required retries.
904 */
905 p_mesgout_from_host:
906 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
907 jmp host_message_loop;
909 p_mesgout_onebyte:
910 mvi CLRSINT1, CLRATNO;
911 mov SCSIDAT, SINDEX;
913 /*
914 * If the next bus phase after ATN drops is message out, it means
915 * that the target is requesting that the last message(s) be resent.
916 */
917 call phase_lock;
918 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
920 p_mesgout_done:
921 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
922 mov LAST_MSG, MSG_OUT;
923 mvi MSG_OUT, MSG_NOOP; /* No message left */
924 jmp ITloop;
926 /*
927 * Message in phase. Bytes are read using Automatic PIO mode.
928 */
929 p_mesgin:
930 /* read the 1st message byte */
931 mvi ACCUM call inb_first;
933 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
934 cmp A,MSG_DISCONNECT je mesgin_disconnect;
935 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
936 cmp ALLZEROS,A je mesgin_complete;
937 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
938 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
939 cmp A,MSG_NOOP je mesgin_done;
941 /*
942 * Pushed message loop to allow the kernel to
943 * run it's own message state engine. To avoid an
944 * extra nop instruction after signaling the kernel,
945 * we perform the phase_lock before checking to see
946 * if we should exit the loop and skip the phase_lock
947 * in the ITloop. Performing back to back phase_locks
948 * shouldn't hurt, but why do it twice...
949 */
950 host_message_loop:
951 call phase_lock; /* Benign the first time through. */
952 SET_SEQINTCODE(HOST_MSG_LOOP)
953 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
954 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
955 mov SCSIDAT, RETURN_2;
956 jmp host_message_loop;
957 /* Must be CONT_MSG_LOOP_READ */
958 mov NONE, SCSIDAT; /* ACK Byte */
959 jmp host_message_loop;
961 mesgin_ign_wide_residue:
962 mov SAVED_MODE, MODE_PTR;
963 SET_MODE(M_SCSI, M_SCSI)
964 shr NEGOADDR, 4, SAVED_SCSIID;
965 mov A, NEGCONOPTS;
966 RESTORE_MODE(SAVED_MODE)
967 test A, WIDEXFER jz mesgin_reject;
968 /* Pull the residue byte */
969 mvi REG0 call inb_next;
970 cmp REG0, 0x01 jne mesgin_reject;
971 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
972 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
973 SET_SEQINTCODE(IGN_WIDE_RES)
974 jmp mesgin_done;
976 mesgin_proto_violation:
977 SET_SEQINTCODE(PROTO_VIOLATION)
978 jmp mesgin_done;
979 mesgin_reject:
980 mvi MSG_MESSAGE_REJECT call mk_mesg;
981 mesgin_done:
982 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
983 jmp ITloop;
985 #define INDEX_DISC_LIST(scsiid, lun) \
986 and A, 0xC0, scsiid; \
987 or SCBPTR, A, lun; \
988 clr SCBPTR[1]; \
989 and SINDEX, 0x30, scsiid; \
990 shr SINDEX, 3; /* Multiply by 2 */ \
991 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
992 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
994 mesgin_identify:
995 /*
996 * Determine whether a target is using tagged or non-tagged
997 * transactions by first looking at the transaction stored in
998 * the per-device, disconnected array. If there is no untagged
999 * transaction for this target, this must be a tagged transaction.
1000 */
1001 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1002 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1003 bmov DINDEX, SINDEX, 2;
1004 bmov REG0, SINDIR, 2;
1005 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
1006 /* Untagged. Clear the busy table entry and setup the SCB. */
1007 bmov DINDIR, ALLONES, 2;
1008 bmov SCBPTR, REG0, 2;
1009 jmp setup_SCB;
1011 /*
1012 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1013 * If we get one, we use the tag returned to find the proper
1014 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
1015 * tag + 256.
1016 */
1017 snoop_tag:
1018 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1019 or SEQ_FLAGS, 0x80;
1020 }
1021 mov NONE, SCSIDAT; /* ACK Identify MSG */
1022 call phase_lock;
1023 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1024 or SEQ_FLAGS, 0x1;
1025 }
1026 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
1027 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1028 or SEQ_FLAGS, 0x2;
1029 }
1030 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
1031 get_tag:
1032 clr SCBPTR[1];
1033 mvi SCBPTR call inb_next; /* tag value */
1034 verify_scb:
1035 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
1036 mov A, SAVED_SCSIID;
1037 cmp SCB_SCSIID, A jne verify_other_scb;
1038 mov A, SAVED_LUN;
1039 cmp SCB_LUN, A je setup_SCB_disconnected;
1040 verify_other_scb:
1041 xor SCBPTR[1], 1;
1042 test SCBPTR[1], 0xFF jnz verify_scb;
1043 jmp not_found;
1045 /*
1046 * Ensure that the SCB the tag points to is for
1047 * an SCB transaction to the reconnecting target.
1048 */
1049 setup_SCB:
1050 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1051 or SEQ_FLAGS, 0x10;
1052 }
1053 test SCB_CONTROL,DISCONNECTED jz not_found;
1054 setup_SCB_disconnected:
1055 and SCB_CONTROL,~DISCONNECTED;
1056 clr SEQ_FLAGS; /* make note of IDENTIFY */
1057 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
1058 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
1059 call allocate_fifo;
1060 /* See if the host wants to send a message upon reconnection */
1061 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1062 mvi HOST_MSG call mk_mesg;
1063 jmp mesgin_done;
1065 not_found:
1066 SET_SEQINTCODE(NO_MATCH)
1067 jmp mesgin_done;
1069 not_found_ITloop:
1070 SET_SEQINTCODE(NO_MATCH)
1071 jmp ITloop;
1073 /*
1074 * We received a "command complete" message. Put the SCB on the complete
1075 * queue and trigger a completion interrupt via the idle loop. Before doing
1076 * so, check to see if there is a residual or the status byte is something
1077 * other than STATUS_GOOD (0). In either of these conditions, we upload the
1078 * SCB back to the host so it can process this information.
1079 */
1080 mesgin_complete:
1082 /*
1083 * If ATN is raised, we still want to give the target a message.
1084 * Perhaps there was a parity error on this last message byte.
1085 * Either way, the target should take us to message out phase
1086 * and then attempt to complete the command again. We should use a
1087 * critical section here to guard against a timeout triggering
1088 * for this command and setting ATN while we are still processing
1089 * the completion.
1090 test SCSISIGI, ATNI jnz mesgin_done;
1091 */
1093 /*
1094 * If we are identified and have successfully sent the CDB,
1095 * any status will do. Optimize this fast path.
1096 */
1097 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1098 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1100 /*
1101 * If the target never sent an identify message but instead went
1102 * to mesgin to give an invalid message, let the host abort us.
1103 */
1104 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1106 /*
1107 * If we recevied good status but never successfully sent the
1108 * cdb, abort the command.
1109 */
1110 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1111 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1112 complete_accepted:
1114 /*
1115 * See if we attempted to deliver a message but the target ingnored us.
1116 */
1117 test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1118 SET_SEQINTCODE(MKMSG_FAILED)
1119 complete_nomsg:
1120 call queue_scb_completion;
1121 jmp await_busfree;
1123 BEGIN_CRITICAL;
1124 freeze_queue:
1125 /* Cancel any pending select-out. */
1126 test SSTAT0, SELDO|SELINGO jnz . + 2;
1127 and SCSISEQ0, ~ENSELO;
1128 mov ACCUM_SAVE, A;
1129 clr A;
1130 add QFREEZE_COUNT, 1;
1131 adc QFREEZE_COUNT[1], A;
1132 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1133 mov A, ACCUM_SAVE ret;
1134 END_CRITICAL;
1136 /*
1137 * Complete the current FIFO's SCB if data for this same
1138 * SCB is not transferring in the other FIFO.
1139 */
1140 SET_SRC_MODE M_DFF1;
1141 SET_DST_MODE M_DFF1;
1142 pkt_complete_scb_if_fifos_idle:
1143 bmov ARG_1, SCBPTR, 2;
1144 mvi DFFSXFRCTL, CLRCHN;
1145 SET_MODE(M_SCSI, M_SCSI)
1146 bmov SCBPTR, ARG_1, 2;
1147 test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1148 queue_scb_completion:
1149 test SCB_SCSI_STATUS,0xff jnz bad_status;
1150 /*
1151 * Check for residuals
1152 */
1153 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1154 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1155 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1156 complete:
1157 BEGIN_CRITICAL;
1158 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1159 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1160 END_CRITICAL;
1161 bad_status:
1162 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1163 call freeze_queue;
1164 upload_scb:
1165 /*
1166 * Restore SCB TAG since we reuse this field
1167 * in the sequencer. We don't want to corrupt
1168 * it on the host.
1169 */
1170 bmov SCB_TAG, SCBPTR, 2;
1171 BEGIN_CRITICAL;
1172 or SCB_SGPTR, SG_STATUS_VALID;
1173 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
1174 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
1175 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1176 bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
1177 add_dma_scb_tail:
1178 bmov REG0, SCBPTR, 2;
1179 bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
1180 bmov SCB_NEXT_COMPLETE, REG0, 2;
1181 bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
1182 END_CRITICAL;
1184 /*
1185 * Is it a disconnect message? Set a flag in the SCB to remind us
1186 * and await the bus going free. If this is an untagged transaction
1187 * store the SCB id for it in our untagged target table for lookup on
1188 * a reselction.
1189 */
1190 mesgin_disconnect:
1191 /*
1192 * If ATN is raised, we still want to give the target a message.
1193 * Perhaps there was a parity error on this last message byte
1194 * or we want to abort this command. Either way, the target
1195 * should take us to message out phase and then attempt to
1196 * disconnect again.
1197 * XXX - Wait for more testing.
1198 test SCSISIGI, ATNI jnz mesgin_done;
1199 */
1200 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1201 jnz mesgin_proto_violation;
1202 or SCB_CONTROL,DISCONNECTED;
1203 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1204 queue_disc_scb:
1205 bmov REG0, SCBPTR, 2;
1206 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1207 bmov DINDEX, SINDEX, 2;
1208 bmov DINDIR, REG0, 2;
1209 bmov SCBPTR, REG0, 2;
1210 /* FALLTHROUGH */
1211 await_busfree:
1212 and SIMODE1, ~ENBUSFREE;
1213 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1214 /*
1215 * In the BUSFREEREV_BUG case, the
1216 * busfree status was cleared at the
1217 * beginning of the connection.
1218 */
1219 mvi CLRSINT1,CLRBUSFREE;
1220 }
1221 mov NONE, SCSIDAT; /* Ack the last byte */
1222 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1223 jnz await_busfree_not_m_dff;
1224 SET_SRC_MODE M_DFF1;
1225 SET_DST_MODE M_DFF1;
1226 await_busfree_clrchn:
1227 mvi DFFSXFRCTL, CLRCHN;
1228 await_busfree_not_m_dff:
1229 /* clear target specific flags */
1230 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
1231 test SSTAT1,REQINIT|BUSFREE jz .;
1232 /*
1233 * We only set BUSFREE status once either a new
1234 * phase has been detected or we are really
1235 * BUSFREE. This allows the driver to know
1236 * that we are active on the bus even though
1237 * no identified transaction exists should a
1238 * timeout occur while awaiting busfree.
1239 */
1240 mvi LASTPHASE, P_BUSFREE;
1241 test SSTAT1, BUSFREE jnz idle_loop;
1242 SET_SEQINTCODE(MISSED_BUSFREE)
1245 /*
1246 * Save data pointers message:
1247 * Copying RAM values back to SCB, for Save Data Pointers message, but
1248 * only if we've actually been into a data phase to change them. This
1249 * protects against bogus data in scratch ram and the residual counts
1250 * since they are only initialized when we go into data_in or data_out.
1251 * Ack the message as soon as possible.
1252 */
1253 SET_SRC_MODE M_DFF1;
1254 SET_DST_MODE M_DFF1;
1255 mesgin_sdptrs:
1256 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1257 test SEQ_FLAGS, DPHASE jz ITloop;
1258 call save_pointers;
1259 jmp ITloop;
1261 save_pointers:
1262 /*
1263 * If we are asked to save our position at the end of the
1264 * transfer, just mark us at the end rather than perform a
1265 * full save.
1266 */
1267 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1268 or SCB_SGPTR, SG_LIST_NULL ret;
1270 save_pointers_full:
1271 /*
1272 * The SCB_DATAPTR becomes the current SHADDR.
1273 * All other information comes directly from our residual
1274 * state.
1275 */
1276 bmov SCB_DATAPTR, SHADDR, 8;
1277 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1279 /*
1280 * Restore pointers message? Data pointers are recopied from the
1281 * SCB anytime we enter a data phase for the first time, so all
1282 * we need to do is clear the DPHASE flag and let the data phase
1283 * code do the rest. We also reset/reallocate the FIFO to make
1284 * sure we have a clean start for the next data or command phase.
1285 */
1286 mesgin_rdptrs:
1287 and SEQ_FLAGS, ~DPHASE;
1288 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1289 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1290 SET_MODE(M_SCSI, M_SCSI)
1291 msgin_rdptrs_get_fifo:
1292 call allocate_fifo;
1293 jmp mesgin_done;
1295 phase_lock:
1296 if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1297 /*
1298 * Don't ignore persistent REQ assertions just because
1299 * they were asserted within the bus settle delay window.
1300 * This allows us to tolerate devices like the GEM318
1301 * that violate the SCSI spec. We are careful not to
1302 * count REQ while we are waiting for it to fall during
1303 * an async phase due to our asserted ACK. Each
1304 * sequencer instruction takes ~25ns, so the REQ must
1305 * last at least 100ns in order to be counted as a true
1306 * REQ.
1307 */
1308 test SCSIPHASE, 0xFF jnz phase_locked;
1309 test SCSISIGI, ACKI jnz phase_lock;
1310 test SCSISIGI, REQI jz phase_lock;
1311 test SCSIPHASE, 0xFF jnz phase_locked;
1312 test SCSISIGI, ACKI jnz phase_lock;
1313 test SCSISIGI, REQI jz phase_lock;
1314 phase_locked:
1315 } else {
1316 test SCSIPHASE, 0xFF jz .;
1317 }
1318 test SSTAT1, SCSIPERR jnz phase_lock;
1319 phase_lock_latch_phase:
1320 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1322 /*
1323 * Functions to read data in Automatic PIO mode.
1324 *
1325 * An ACK is not sent on input from the target until SCSIDATL is read from.
1326 * So we wait until SCSIDATL is latched (the usual way), then read the data
1327 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1328 * line, or we just want to acknowledge the byte, then we do a dummy read
1329 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1330 * data byte on the bus until we send our ACK.
1331 *
1332 * The assumption here is that these are called in a particular sequence,
1333 * and that REQ is already set when inb_first is called. inb_{first,next}
1334 * use the same calling convention as inb.
1335 */
1336 inb_next:
1337 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1338 inb_next_wait:
1339 /*
1340 * If there is a parity error, wait for the kernel to
1341 * see the interrupt and prepare our message response
1342 * before continuing.
1343 */
1344 test SCSIPHASE, 0xFF jz .;
1345 test SSTAT1, SCSIPERR jnz inb_next_wait;
1346 inb_next_check_phase:
1347 and LASTPHASE, PHASE_MASK, SCSISIGI;
1348 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1349 inb_first:
1350 clr DINDEX[1];
1351 mov DINDEX,SINDEX;
1352 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1353 inb_last:
1354 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1356 mk_mesg:
1357 mvi SCSISIGO, ATNO;
1358 mov MSG_OUT,SINDEX ret;
1360 SET_SRC_MODE M_DFF1;
1361 SET_DST_MODE M_DFF1;
1362 disable_ccsgen:
1363 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1364 clr CCSGCTL;
1365 disable_ccsgen_fetch_done:
1366 clr SG_STATE ret;
1368 service_fifo:
1369 /*
1370 * Do we have any prefetch left???
1371 */
1372 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1374 /*
1375 * Can this FIFO have access to the S/G cache yet?
1376 */
1377 test CCSGCTL, SG_CACHE_AVAIL jz return;
1379 /* Did we just finish fetching segs? */
1380 test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1382 /* Are we actively fetching segments? */
1383 test CCSGCTL, CCSGENACK jnz return;
1385 /*
1386 * Should the other FIFO get the S/G cache first? If
1387 * both FIFOs have been allocated since we last checked
1388 * any FIFO, it is important that we service a FIFO
1389 * that is not actively on the bus first. This guarantees
1390 * that a FIFO will be freed to handle snapshot requests for
1391 * any FIFO that is still on the bus. Chips with RTI do not
1392 * perform snapshots, so don't bother with this test there.
1393 */
1394 if ((ahd->features & AHD_RTI) == 0) {
1395 /*
1396 * If we're not still receiving SCSI data,
1397 * it is safe to allocate the S/G cache to
1398 * this FIFO.
1399 */
1400 test DFCNTRL, SCSIEN jz idle_sgfetch_start;
1402 /*
1403 * Switch to the other FIFO. Non-RTI chips
1404 * also have the "set mode" bug, so we must
1405 * disable interrupts during the switch.
1406 */
1407 mvi SEQINTCTL, INTVEC1DSL;
1408 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1410 /*
1411 * If the other FIFO needs loading, then it
1412 * must not have claimed the S/G cache yet
1413 * (SG_CACHE_AVAIL would have been cleared in
1414 * the orginal FIFO mode and we test this above).
1415 * Return to the idle loop so we can process the
1416 * FIFO not currently on the bus first.
1417 */
1418 test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
1419 clr SEQINTCTL ret;
1420 idle_sgfetch_okay:
1421 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1422 clr SEQINTCTL;
1423 }
1425 idle_sgfetch_start:
1426 /*
1427 * We fetch a "cacheline aligned" and sized amount of data
1428 * so we don't end up referencing a non-existant page.
1429 * Cacheline aligned is in quotes because the kernel will
1430 * set the prefetch amount to a reasonable level if the
1431 * cacheline size is unknown.
1432 */
1433 bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1434 mvi SGHCNT, SG_PREFETCH_CNT;
1435 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1436 /*
1437 * Need two instructions between "touches" of SGHADDR.
1438 */
1439 nop;
1440 }
1441 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1442 mvi CCSGCTL, CCSGEN|CCSGRESET;
1443 or SG_STATE, FETCH_INPROG ret;
1444 idle_sgfetch_complete:
1445 /*
1446 * Guard against SG_CACHE_AVAIL activating during sg fetch
1447 * request in the other FIFO.
1448 */
1449 test SG_STATE, FETCH_INPROG jz return;
1450 clr CCSGCTL;
1451 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1452 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1453 idle_sg_avail:
1454 /* Does the hardware have space for another SG entry? */
1455 test DFSTATUS, PRELOAD_AVAIL jz return;
1456 /*
1457 * On the A, preloading a segment before HDMAENACK
1458 * comes true can clobber the shaddow address of the
1459 * first segment in the S/G FIFO. Wait until it is
1460 * safe to proceed.
1461 */
1462 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1463 test DFCNTRL, HDMAENACK jz return;
1464 }
1465 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1466 bmov HADDR, CCSGRAM, 8;
1467 } else {
1468 bmov HADDR, CCSGRAM, 4;
1469 }
1470 bmov HCNT, CCSGRAM, 3;
1471 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1472 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1473 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1474 }
1475 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1476 /* Skip 4 bytes of pad. */
1477 add CCSGADDR, 4;
1478 }
1479 sg_advance:
1480 clr A; /* add sizeof(struct scatter) */
1481 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1482 adc SCB_RESIDUAL_SGPTR[1],A;
1483 adc SCB_RESIDUAL_SGPTR[2],A;
1484 adc SCB_RESIDUAL_SGPTR[3],A;
1485 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1486 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1487 or SINDEX, LAST_SEG;
1488 clr SG_STATE;
1489 mov SG_CACHE_PRE, SINDEX;
1490 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1491 /*
1492 * Use SCSIENWRDIS so that SCSIEN is never
1493 * modified by this operation.
1494 */
1495 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1496 } else {
1497 or DFCNTRL, PRELOADEN|HDMAEN;
1498 }
1499 /*
1500 * Do we have another segment in the cache?
1501 */
1502 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1503 jnc return;
1504 and SG_STATE, ~SEGS_AVAIL ret;
1506 /*
1507 * Initialize the DMA address and counter from the SCB.
1508 */
1509 load_first_seg:
1510 bmov HADDR, SCB_DATAPTR, 11;
1511 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1512 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1513 or REG_ISR, LAST_SEG;
1514 mov SG_CACHE_PRE, REG_ISR;
1515 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1516 /*
1517 * Since we've are entering a data phase, we will
1518 * rely on the SCB_RESID* fields. Initialize the
1519 * residual and clear the full residual flag.
1520 */
1521 and SCB_SGPTR[0], ~SG_FULL_RESID;
1522 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1523 /* If we need more S/G elements, tell the idle loop */
1524 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1525 mvi SG_STATE, LOADING_NEEDED ret;
1526 clr SG_STATE ret;
1528 p_data_handle_xfer:
1529 call setjmp;
1530 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1531 p_data_clear_handler:
1532 or LONGJMP_ADDR[1], INVALID_ADDR ret;
1534 p_data:
1535 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1536 SET_SEQINTCODE(PROTO_VIOLATION)
1537 p_data_allowed:
1539 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1541 /*
1542 * If we re-enter the data phase after going through another
1543 * phase, our transfer location has almost certainly been
1544 * corrupted by the interveining, non-data, transfers. Ask
1545 * the host driver to fix us up based on the transfer residual
1546 * unless we already know that we should be bitbucketing.
1547 */
1548 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1549 SET_SEQINTCODE(PDATA_REINIT)
1550 jmp data_phase_inbounds;
1552 p_data_bitbucket:
1553 /*
1554 * Turn on `Bit Bucket' mode, wait until the target takes
1555 * us to another phase, and then notify the host.
1556 */
1557 mov SAVED_MODE, MODE_PTR;
1558 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1559 jnz bitbucket_not_m_dff;
1560 /*
1561 * Ensure that any FIFO contents are cleared out and the
1562 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1563 * doesn't discard data already in the FIFO.
1564 */
1565 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1566 SET_MODE(M_SCSI, M_SCSI)
1567 bitbucket_not_m_dff:
1568 or SXFRCTL1,BITBUCKET;
1569 /* Wait for non-data phase. */
1570 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1571 and SXFRCTL1, ~BITBUCKET;
1572 RESTORE_MODE(SAVED_MODE)
1573 SET_SRC_MODE M_DFF1;
1574 SET_DST_MODE M_DFF1;
1575 SET_SEQINTCODE(DATA_OVERRUN)
1576 jmp ITloop;
1578 data_phase_initialize:
1579 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1580 call load_first_seg;
1581 data_phase_inbounds:
1582 /* We have seen a data phase at least once. */
1583 or SEQ_FLAGS, DPHASE;
1584 mov SAVED_MODE, MODE_PTR;
1585 test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1586 call p_data_handle_xfer;
1587 data_group_dma_loop:
1588 /*
1589 * The transfer is complete if either the last segment
1590 * completes or the target changes phase. Both conditions
1591 * will clear SCSIEN.
1592 */
1593 call idle_loop_service_fifos;
1594 call idle_loop_cchan;
1595 call idle_loop_gsfifo;
1596 RESTORE_MODE(SAVED_MODE)
1597 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1599 data_group_dmafinish:
1600 /*
1601 * The transfer has terminated either due to a phase
1602 * change, and/or the completion of the last segment.
1603 * We have two goals here. Do as much other work
1604 * as possible while the data fifo drains on a read
1605 * and respond as quickly as possible to the standard
1606 * messages (save data pointers/disconnect and command
1607 * complete) that usually follow a data phase.
1608 */
1609 call calc_residual;
1611 /*
1612 * Go ahead and shut down the DMA engine now.
1613 */
1614 test DFCNTRL, DIRECTION jnz data_phase_finish;
1615 data_group_fifoflush:
1616 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1617 or DFCNTRL, FIFOFLUSH;
1618 }
1619 /*
1620 * We have enabled the auto-ack feature. This means
1621 * that the controller may have already transferred
1622 * some overrun bytes into the data FIFO and acked them
1623 * on the bus. The only way to detect this situation is
1624 * to wait for LAST_SEG_DONE to come true on a completed
1625 * transfer and then test to see if the data FIFO is
1626 * non-empty. We know there is more data yet to transfer
1627 * if SG_LIST_NULL is not yet set, thus there cannot be
1628 * an overrun.
1629 */
1630 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1631 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1632 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1633 /* Overrun */
1634 jmp p_data;
1635 data_phase_finish:
1636 /*
1637 * If the target has left us in data phase, loop through
1638 * the dma code again. We will only loop if there is a
1639 * data overrun.
1640 */
1641 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1642 test SSTAT0, TARGET jnz data_phase_done;
1643 }
1644 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1645 test SSTAT1, REQINIT jz .;
1646 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1647 }
1649 data_phase_done:
1650 /* Kill off any pending prefetch */
1651 call disable_ccsgen;
1652 or LONGJMP_ADDR[1], INVALID_ADDR;
1654 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1655 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1656 /*
1657 and SEQ_FLAGS, ~DPHASE_PENDING;
1658 * For data-in phases, wait for any pending acks from the
1659 * initiator before changing phase. We only need to
1660 * send Ignore Wide Residue messages for data-in phases.
1661 test DFCNTRL, DIRECTION jz target_ITloop;
1662 test SSTAT1, REQINIT jnz .;
1663 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1664 SET_MODE(M_SCSI, M_SCSI)
1665 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1666 */
1667 /*
1668 * Issue an Ignore Wide Residue Message.
1669 mvi P_MESGIN|BSYO call change_phase;
1670 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1671 mvi 1 call target_outb;
1672 jmp target_ITloop;
1673 */
1674 } else {
1675 jmp ITloop;
1676 }
1678 /*
1679 * We assume that, even though data may still be
1680 * transferring to the host, that the SCSI side of
1681 * the DMA engine is now in a static state. This
1682 * allows us to update our notion of where we are
1683 * in this transfer.
1684 *
1685 * If, by chance, we stopped before being able
1686 * to fetch additional segments for this transfer,
1687 * yet the last S/G was completely exhausted,
1688 * call our idle loop until it is able to load
1689 * another segment. This will allow us to immediately
1690 * pickup on the next segment on the next data phase.
1691 *
1692 * If we happened to stop on the last segment, then
1693 * our residual information is still correct from
1694 * the idle loop and there is no need to perform
1695 * any fixups.
1696 */
1697 residual_before_last_seg:
1698 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1699 /*
1700 * Can never happen from an interrupt as the packetized
1701 * hardware will only interrupt us once SHVALID or
1702 * LAST_SEG_DONE.
1703 */
1704 call idle_loop_service_fifos;
1705 RESTORE_MODE(SAVED_MODE)
1706 /* FALLTHROUGH */
1707 calc_residual:
1708 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1709 /* Record if we've consumed all S/G entries */
1710 test MDFFSTAT, SHVALID jz . + 2;
1711 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1712 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1714 sgptr_fixup:
1715 /*
1716 * Fixup the residual next S/G pointer. The S/G preload
1717 * feature of the chip allows us to load two elements
1718 * in addition to the currently active element. We
1719 * store the bottom byte of the next S/G pointer in
1720 * the SG_CACHE_PTR register so we can restore the
1721 * correct value when the DMA completes. If the next
1722 * sg ptr value has advanced to the point where higher
1723 * bytes in the address have been affected, fix them
1724 * too.
1725 */
1726 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1727 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1728 add SCB_RESIDUAL_SGPTR[1], -1;
1729 adc SCB_RESIDUAL_SGPTR[2], -1;
1730 adc SCB_RESIDUAL_SGPTR[3], -1;
1731 sgptr_fixup_done:
1732 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1733 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1734 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1736 export timer_isr:
1737 call issue_cmdcmplt;
1738 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1739 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1740 /*
1741 * In H2A4, the mode pointer is not saved
1742 * for intvec2, but is restored on iret.
1743 * This can lead to the restoration of a
1744 * bogus mode ptr. Manually clear the
1745 * intmask bits and do a normal return
1746 * to compensate.
1747 */
1748 and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1749 } else {
1750 or SEQINTCTL, IRET ret;
1751 }
1753 export seq_isr:
1754 if ((ahd->features & AHD_RTI) == 0) {
1755 /*
1756 * On RevA Silicon, if the target returns us to data-out
1757 * after we have already trained for data-out, it is
1758 * possible for us to transition the free running clock to
1759 * data-valid before the required 100ns P1 setup time (8 P1
1760 * assertions in fast-160 mode). This will only happen if
1761 * this L-Q is a continuation of a data transfer for which
1762 * we have already prefetched data into our FIFO (LQ/Data
1763 * followed by LQ/Data for the same write transaction).
1764 * This can cause some target implementations to miss the
1765 * first few data transfers on the bus. We detect this
1766 * situation by noticing that this is the first data transfer
1767 * after an LQ (LQIWORKONLQ true), that the data transfer is
1768 * a continuation of a transfer already setup in our FIFO
1769 * (SAVEPTRS interrupt), and that the transaction is a write
1770 * (DIRECTION set in DFCNTRL). The delay is performed by
1771 * disabling SCSIEN until we see the first REQ from the
1772 * target.
1773 *
1774 * First instruction in an ISR cannot be a branch on
1775 * Rev A. Snapshot LQISTAT2 so the status is not missed
1776 * and deffer the test by one instruction.
1777 */
1778 mov REG_ISR, LQISTAT2;
1779 test REG_ISR, LQIWORKONLQ jz main_isr;
1780 test SEQINTSRC, SAVEPTRS jz main_isr;
1781 test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1782 /*
1783 * Switch to the active FIFO after clearing the snapshot
1784 * savepointer in the current FIFO. We do this so that
1785 * a pending CTXTDONE or SAVEPTR is visible in the active
1786 * FIFO. This status is the only way we can detect if we
1787 * have lost the race (e.g. host paused us) and our attempts
1788 * to disable the channel occurred after all REQs were
1789 * already seen and acked (REQINIT never comes true).
1790 */
1791 mvi DFFSXFRCTL, CLRCHN;
1792 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1793 test DFCNTRL, DIRECTION jz interrupt_return;
1794 and DFCNTRL, ~SCSIEN;
1795 snapshot_wait_data_valid:
1796 test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
1797 test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1798 snapshot_data_valid:
1799 or DFCNTRL, SCSIEN;
1800 or SEQINTCTL, IRET ret;
1801 snapshot_saveptr:
1802 mvi DFFSXFRCTL, CLRCHN;
1803 or SEQINTCTL, IRET ret;
1804 main_isr:
1805 }
1806 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1807 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1808 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1809 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1810 SET_SEQINTCODE(INVALID_SEQINT)
1812 /*
1813 * There are two types of save pointers interrupts:
1814 * The first is a snapshot save pointers where the current FIFO is not
1815 * active and contains a snapshot of the current poniter information.
1816 * This happens between packets in a stream for a single L_Q. Since we
1817 * are not performing a pointer save, we can safely clear the channel
1818 * so it can be used for other transactions. On RTI capable controllers,
1819 * where snapshots can, and are, disabled, the code to handle this type
1820 * of snapshot is not active.
1821 *
1822 * The second case is a save pointers on an active FIFO which occurs
1823 * if the target changes to a new L_Q or busfrees/QASes and the transfer
1824 * has a residual. This should occur coincident with a ctxtdone. We
1825 * disable the interrupt and allow our active routine to handle the
1826 * save.
1827 */
1828 saveptr_intr:
1829 if ((ahd->features & AHD_RTI) == 0) {
1830 test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1831 }
1832 saveptr_active_fifo:
1833 and SEQIMODE, ~ENSAVEPTRS;
1834 or SEQINTCTL, IRET ret;
1836 cfg4data_intr:
1837 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1838 call load_first_seg;
1839 call pkt_handle_xfer;
1840 inc SCB_FIFO_USE_COUNT;
1841 interrupt_return:
1842 or SEQINTCTL, IRET ret;
1844 cfg4istat_intr:
1845 call freeze_queue;
1846 add NONE, -13, SCB_CDB_LEN;
1847 jnc cfg4istat_have_sense_addr;
1848 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1849 /*
1850 * Host sets up address/count and enables transfer.
1851 */
1852 SET_SEQINTCODE(CFG4ISTAT_INTR)
1853 jmp cfg4istat_setup_handler;
1854 cfg4istat_have_sense_addr:
1855 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1856 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1857 mvi SG_CACHE_PRE, LAST_SEG;
1858 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1859 cfg4istat_setup_handler:
1860 /*
1861 * Status pkt is transferring to host.
1862 * Wait in idle loop for transfer to complete.
1863 * If a command completed before an attempted
1864 * task management function completed, notify the host.
1865 */
1866 test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1867 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1868 cfg4istat_no_taskmgmt_func:
1869 call pkt_handle_status;
1870 or SEQINTCTL, IRET ret;
1872 cfg4icmd_intr:
1873 /*
1874 * In the case of DMAing a CDB from the host, the normal
1875 * CDB buffer is formatted with an 8 byte address followed
1876 * by a 1 byte count.
1877 */
1878 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1879 mvi SG_CACHE_PRE, LAST_SEG;
1880 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1881 call pkt_handle_cdb;
1882 or SEQINTCTL, IRET ret;
1884 /*
1885 * See if the target has gone on in this context creating an
1886 * overrun condition. For the write case, the hardware cannot
1887 * ack bytes until data are provided. So, if the target begins
1888 * another packet without changing contexts, implying we are
1889 * not sitting on a packet boundary, we are in an overrun
1890 * situation. For the read case, the hardware will continue to
1891 * ack bytes into the FIFO, and may even ack the last overrun packet
1892 * into the FIFO. If the FIFO should become non-empty, we are in
1893 * a read overrun case.
1894 */
1895 #define check_overrun \
1896 /* Not on a packet boundary. */ \
1897 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1898 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1900 pkt_handle_xfer:
1901 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1902 call setjmp;
1903 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1904 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1905 test SCSISIGO, ATNO jnz . + 2;
1906 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1907 /*
1908 * Defer handling of this NONPACKREQ until we
1909 * can be sure it pertains to this FIFO. SAVEPTRS
1910 * will not be asserted if the NONPACKREQ is for us,
1911 * so we must simulate it if shaddow is valid. If
1912 * shaddow is not valid, keep running this FIFO until we
1913 * have satisfied the transfer by loading segments and
1914 * waiting for either shaddow valid or last_seg_done.
1915 */
1916 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1917 pkt_service_fifo:
1918 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1919 pkt_last_seg:
1920 call setjmp;
1921 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1922 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
1923 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1924 test SCSISIGO, ATNO jnz . + 2;
1925 test SSTAT2, NONPACKREQ jz return;
1926 test MDFFSTAT, SHVALID jz return;
1927 /* FALLTHROUGH */
1929 /*
1930 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1931 * or we have a pending NONPACKREQ for this FIFO. We differentiate
1932 * between the two by capturing the state of the SAVEPTRS interrupt
1933 * prior to clearing this status and executing the common code for
1934 * these two cases.
1935 */
1936 pkt_saveptrs:
1937 BEGIN_CRITICAL;
1938 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1939 or DFCNTRL, FIFOFLUSH;
1940 }
1941 mov REG0, SEQINTSRC;
1942 call calc_residual;
1943 call save_pointers;
1944 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1945 call disable_ccsgen;
1946 or SEQIMODE, ENSAVEPTRS;
1947 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1948 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1949 /*
1950 * Keep a handler around for this FIFO until it drains
1951 * to the host to guarantee that we don't complete the
1952 * command to the host before the data arrives.
1953 */
1954 pkt_saveptrs_wait_fifoemp:
1955 call setjmp;
1956 test DFSTATUS, FIFOEMP jz return;
1957 pkt_saveptrs_check_status:
1958 or LONGJMP_ADDR[1], INVALID_ADDR;
1959 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1960 dec SCB_FIFO_USE_COUNT;
1961 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1962 mvi DFFSXFRCTL, CLRCHN ret;
1964 /*
1965 * LAST_SEG_DONE status has been seen in the current FIFO.
1966 * This indicates that all of the allowed data for this
1967 * command has transferred across the SCSI and host buses.
1968 * Check for overrun and see if we can complete this command.
1969 */
1970 pkt_last_seg_done:
1971 /*
1972 * Mark transfer as completed.
1973 */
1974 or SCB_SGPTR, SG_LIST_NULL;
1976 /*
1977 * Wait for the current context to finish to verify that
1978 * no overrun condition has occurred.
1979 */
1980 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1981 call setjmp;
1982 pkt_wait_ctxt_done_loop:
1983 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1984 /*
1985 * A sufficiently large overrun or a NONPACKREQ may
1986 * prevent CTXTDONE from ever asserting, so we must
1987 * poll for these statuses too.
1988 */
1989 check_overrun;
1990 test SSTAT2, NONPACKREQ jz return;
1991 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
1992 /* FALLTHROUGH */
1994 pkt_ctxt_done:
1995 check_overrun;
1996 or LONGJMP_ADDR[1], INVALID_ADDR;
1997 /*
1998 * If status has been received, it is safe to skip
1999 * the check to see if another FIFO is active because
2000 * LAST_SEG_DONE has been observed. However, we check
2001 * the FIFO anyway since it costs us only one extra
2002 * instruction to leverage common code to perform the
2003 * SCB completion.
2004 */
2005 dec SCB_FIFO_USE_COUNT;
2006 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2007 mvi DFFSXFRCTL, CLRCHN ret;
2008 END_CRITICAL;
2010 /*
2011 * Must wait until CDB xfer is over before issuing the
2012 * clear channel.
2013 */
2014 pkt_handle_cdb:
2015 call setjmp;
2016 test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
2017 or LONGJMP_ADDR[1], INVALID_ADDR;
2018 mvi DFFSXFRCTL, CLRCHN ret;
2020 /*
2021 * Watch over the status transfer. Our host sense buffer is
2022 * large enough to take the maximum allowed status packet.
2023 * None-the-less, we must still catch and report overruns to
2024 * the host. Additionally, properly catch unexpected non-packet
2025 * phases that are typically caused by CRC errors in status packet
2026 * transmission.
2027 */
2028 pkt_handle_status:
2029 call setjmp;
2030 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2031 test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
2032 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2033 pkt_status_IU_done:
2034 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
2035 or DFCNTRL, FIFOFLUSH;
2036 }
2037 test DFSTATUS, FIFOEMP jz return;
2038 BEGIN_CRITICAL;
2039 or LONGJMP_ADDR[1], INVALID_ADDR;
2040 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
2041 or SCB_CONTROL, STATUS_RCVD;
2042 jmp pkt_complete_scb_if_fifos_idle;
2043 END_CRITICAL;
2044 pkt_status_check_overrun:
2045 /*
2046 * Status PKT overruns are uncerimoniously recovered with a
2047 * bus reset. If we've overrun, let the host know so that
2048 * recovery can be performed.
2049 *
2050 * LAST_SEG_DONE has been observed. If either CTXTDONE or
2051 * a NONPACKREQ phase change have occurred and the FIFO is
2052 * empty, there is no overrun.
2053 */
2054 test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
2055 test SEQINTSRC, CTXTDONE jz . + 2;
2056 test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
2057 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2058 test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
2059 pkt_status_report_overrun:
2060 SET_SEQINTCODE(STATUS_OVERRUN)
2061 /* SEQUENCER RESTARTED */
2062 pkt_status_check_nonpackreq:
2063 /*
2064 * CTXTDONE may be held off if a NONPACKREQ is associated with
2065 * the current context. If a NONPACKREQ is observed, decide
2066 * if it is for the current context. If it is for the current
2067 * context, we must defer NONPACKREQ processing until all data
2068 * has transferred to the host.
2069 */
2070 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2071 test SCSISIGO, ATNO jnz . + 2;
2072 test SSTAT2, NONPACKREQ jz return;
2073 test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
2074 test DFSTATUS, FIFOEMP jz return;
2075 /*
2076 * The unexpected nonpkt phase handler assumes that any
2077 * data channel use will have a FIFO reference count. It
2078 * turns out that the status handler doesn't need a refernce
2079 * count since the status received flag, and thus completion
2080 * processing, cannot be set until the handler is finished.
2081 * We increment the count here to make the nonpkt handler
2082 * happy.
2083 */
2084 inc SCB_FIFO_USE_COUNT;
2085 /* FALLTHROUGH */
2087 /*
2088 * Nonpackreq is a polled status. It can come true in three situations:
2089 * we have received an L_Q, we have sent one or more L_Qs, or there is no
2090 * L_Q context associated with this REQ (REQ occurs immediately after a
2091 * (re)selection). Routines that know that the context responsible for this
2092 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
2093 * top level idle loop, we exhaust all active contexts prior to determining that
2094 * we simply do not have the full I_T_L_Q for this phase.
2095 */
2096 unexpected_nonpkt_phase_find_ctxt:
2097 /*
2098 * This nonpackreq is most likely associated with one of the tags
2099 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
2100 * nonpackreq if we've cleared out the FIFOs and handled any
2101 * pending SELDO.
2102 */
2103 SET_SRC_MODE M_SCSI;
2104 SET_DST_MODE M_SCSI;
2105 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
2106 cmp A, FIFO1FREE|FIFO0FREE jne return;
2107 test SSTAT0, SELDO jnz return;
2108 mvi SCBPTR[1], SCB_LIST_NULL;
2109 unexpected_nonpkt_phase:
2110 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
2111 jnz unexpected_nonpkt_mode_cleared;
2112 SET_SRC_MODE M_DFF0;
2113 SET_DST_MODE M_DFF0;
2114 or LONGJMP_ADDR[1], INVALID_ADDR;
2115 dec SCB_FIFO_USE_COUNT;
2116 mvi DFFSXFRCTL, CLRCHN;
2117 unexpected_nonpkt_mode_cleared:
2118 mvi CLRSINT2, CLRNONPACKREQ;
2119 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
2120 SET_SEQINTCODE(ENTERING_NONPACK)
2121 jmp ITloop;
2123 illegal_phase:
2124 SET_SEQINTCODE(ILLEGAL_PHASE)
2125 jmp ITloop;
2127 /*
2128 * We have entered an overrun situation. If we have working
2129 * BITBUCKET, flip that on and let the hardware eat any overrun
2130 * data. Otherwise use an overrun buffer in the host to simulate
2131 * BITBUCKET.
2132 */
2133 pkt_handle_overrun_inc_use_count:
2134 inc SCB_FIFO_USE_COUNT;
2135 pkt_handle_overrun:
2136 SET_SEQINTCODE(CFG4OVERRUN)
2137 call freeze_queue;
2138 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
2139 or DFFSXFRCTL, DFFBITBUCKET;
2140 SET_SRC_MODE M_DFF1;
2141 SET_DST_MODE M_DFF1;
2142 } else {
2143 call load_overrun_buf;
2144 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2145 }
2146 call setjmp;
2147 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2148 test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
2149 call load_overrun_buf;
2150 or DFCNTRL, PRELOADEN;
2151 overrun_load_done:
2152 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2153 } else {
2154 test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2155 }
2156 test SSTAT2, NONPACKREQ jz return;
2157 pkt_overrun_end:
2158 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2159 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2160 dec SCB_FIFO_USE_COUNT;
2161 or LONGJMP_ADDR[1], INVALID_ADDR;
2162 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2163 mvi DFFSXFRCTL, CLRCHN ret;
2165 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2166 load_overrun_buf:
2167 /*
2168 * Load a dummy segment if preload space is available.
2169 */
2170 mov HADDR[0], SHARED_DATA_ADDR;
2171 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2172 mov ACCUM_SAVE, A;
2173 clr A;
2174 adc HADDR[2], A, SHARED_DATA_ADDR[2];
2175 adc HADDR[3], A, SHARED_DATA_ADDR[3];
2176 mov A, ACCUM_SAVE;
2177 bmov HADDR[4], ALLZEROS, 4;
2178 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2179 clr HCNT[0];
2180 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);
2181 clr HCNT[2] ret;
2182 }