?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix a race condition in the flushing of commands that
[dragonfly/port-amd64.git] / sys / dev / disk / aic7xxx / aic79xx.c
blob63667c09e0e833d7cda148183ad92eea52ac3a81
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#202 $
41 *
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.24 2003/06/28 04:46:54 gibbs Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.c,v 1.17 2007/07/05 04:39:25 pavalos Exp $
44 */
45
46 #include "aic79xx_osm.h"
47 #include "aic79xx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49
50 /******************************** Globals *************************************/
51 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
52
53 /***************************** Lookup Tables **********************************/
54 char *ahd_chip_names[] =
55 {
56 "NONE",
57 "aic7901",
58 "aic7902",
59 "aic7901A"
60 };
61 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
62
63 /*
64 * Hardware error codes.
65 */
66 struct ahd_hard_error_entry {
67 uint8_t error;
68 char *errmesg;
69 };
70
71 static struct ahd_hard_error_entry ahd_hard_errors[] = {
72 { DSCTMOUT, "Discard Timer has timed out" },
73 { ILLOPCODE, "Illegal Opcode in sequencer program" },
74 { SQPARERR, "Sequencer Parity Error" },
75 { DPARERR, "Data-path Parity Error" },
76 { MPARERR, "Scratch or SCB Memory Parity Error" },
77 { CIOPARERR, "CIOBUS Parity Error" },
78 };
79 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
80
81 static struct ahd_phase_table_entry ahd_phase_table[] =
82 {
83 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
84 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
85 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
86 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
87 { P_COMMAND, MSG_NOOP, "in Command phase" },
88 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
89 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
90 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
91 { P_BUSFREE, MSG_NOOP, "while idle" },
92 { 0, MSG_NOOP, "in unknown phase" }
93 };
94
95 /*
96 * In most cases we only wish to itterate over real phases, so
97 * exclude the last element from the count.
98 */
99 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
100
101 /* Our Sequencer Program */
102 #include "aic79xx_seq.h"
103
104 /**************************** Function Declarations ***************************/
105 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
106 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
107 u_int lqistat1);
108 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
109 u_int busfreetime);
110 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
111 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
112 static void ahd_force_renegotiation(struct ahd_softc *ahd,
113 struct ahd_devinfo *devinfo);
114
115 static struct ahd_tmode_tstate*
116 ahd_alloc_tstate(struct ahd_softc *ahd,
117 u_int scsi_id, char channel);
118 #ifdef AHD_TARGET_MODE
119 static void ahd_free_tstate(struct ahd_softc *ahd,
120 u_int scsi_id, char channel, int force);
121 #endif
122 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
123 struct ahd_initiator_tinfo *,
124 u_int *period,
125 u_int *ppr_options,
126 role_t role);
127 static void ahd_update_neg_table(struct ahd_softc *ahd,
128 struct ahd_devinfo *devinfo,
129 struct ahd_transinfo *tinfo);
130 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
131 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
132 struct ahd_devinfo *devinfo);
133 static void ahd_scb_devinfo(struct ahd_softc *ahd,
134 struct ahd_devinfo *devinfo,
135 struct scb *scb);
136 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
137 struct ahd_devinfo *devinfo,
138 struct scb *scb);
139 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
140 struct ahd_devinfo *devinfo);
141 static void ahd_construct_sdtr(struct ahd_softc *ahd,
142 struct ahd_devinfo *devinfo,
143 u_int period, u_int offset);
144 static void ahd_construct_wdtr(struct ahd_softc *ahd,
145 struct ahd_devinfo *devinfo,
146 u_int bus_width);
147 static void ahd_construct_ppr(struct ahd_softc *ahd,
148 struct ahd_devinfo *devinfo,
149 u_int period, u_int offset,
150 u_int bus_width, u_int ppr_options);
151 static void ahd_clear_msg_state(struct ahd_softc *ahd);
152 static void ahd_handle_message_phase(struct ahd_softc *ahd);
153 typedef enum {
154 AHDMSG_1B,
155 AHDMSG_2B,
156 AHDMSG_EXT
157 } ahd_msgtype;
158 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
159 u_int msgval, int full);
160 static int ahd_parse_msg(struct ahd_softc *ahd,
161 struct ahd_devinfo *devinfo);
162 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
163 struct ahd_devinfo *devinfo);
164 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
165 struct ahd_devinfo *devinfo);
166 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
167 static void ahd_handle_devreset(struct ahd_softc *ahd,
168 struct ahd_devinfo *devinfo,
169 u_int lun, cam_status status,
170 char *message, int verbose_level);
171 #if AHD_TARGET_MODE
172 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
173 struct ahd_devinfo *devinfo,
174 struct scb *scb);
175 #endif
176
177 static u_int ahd_sglist_size(struct ahd_softc *ahd);
178 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
179 static bus_dmamap_callback_t
180 ahd_dmamap_cb;
181 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
182 static int ahd_init_scbdata(struct ahd_softc *ahd);
183 static void ahd_fini_scbdata(struct ahd_softc *ahd);
184 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
185 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
186 static void ahd_add_col_list(struct ahd_softc *ahd,
187 struct scb *scb, u_int col_idx);
188 static void ahd_rem_col_list(struct ahd_softc *ahd,
189 struct scb *scb);
190 static void ahd_chip_init(struct ahd_softc *ahd);
191 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
192 struct scb *prev_scb,
193 struct scb *scb);
194 static int ahd_qinfifo_count(struct ahd_softc *ahd);
195 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
196 char channel, int lun, u_int tag,
197 role_t role, uint32_t status,
198 ahd_search_action action,
199 u_int *list_head, u_int tid);
200 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
201 u_int tid_prev, u_int tid_cur,
202 u_int tid_next);
203 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
204 u_int scbid);
205 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
206 u_int prev, u_int next, u_int tid);
207 static void ahd_reset_current_bus(struct ahd_softc *ahd);
208 static ahd_callback_t ahd_reset_poll;
209 static ahd_callback_t ahd_stat_timer;
210 #ifdef AHD_DUMP_SEQ
211 static void ahd_dumpseq(struct ahd_softc *ahd);
212 #endif
213 static void ahd_loadseq(struct ahd_softc *ahd);
214 static int ahd_check_patch(struct ahd_softc *ahd,
215 struct patch **start_patch,
216 u_int start_instr, u_int *skip_addr);
217 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
218 u_int address);
219 static void ahd_download_instr(struct ahd_softc *ahd,
220 u_int instrptr, uint8_t *dconsts);
221 static int ahd_probe_stack_size(struct ahd_softc *ahd);
222 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
223 struct scb *scb);
224 static void ahd_run_data_fifo(struct ahd_softc *ahd,
225 struct scb *scb);
226
227 #ifdef AHD_TARGET_MODE
228 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
229 struct ahd_tmode_lstate *lstate,
230 u_int initiator_id,
231 u_int event_type,
232 u_int event_arg);
233 static void ahd_update_scsiid(struct ahd_softc *ahd,
234 u_int targid_mask);
235 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
236 struct target_cmd *cmd);
237 #endif
238
239 /******************************** Private Inlines *****************************/
240 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
241 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
242 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
243
244 static __inline void
245 ahd_assert_atn(struct ahd_softc *ahd)
246 {
247 ahd_outb(ahd, SCSISIGO, ATNO);
248 }
249
250 /*
251 * Determine if the current connection has a packetized
252 * agreement. This does not necessarily mean that we
253 * are currently in a packetized transfer. We could
254 * just as easily be sending or receiving a message.
255 */
256 static __inline int
257 ahd_currently_packetized(struct ahd_softc *ahd)
258 {
259 ahd_mode_state saved_modes;
260 int packetized;
261
262 saved_modes = ahd_save_modes(ahd);
263 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
264 /*
265 * The packetized bit refers to the last
266 * connection, not the current one. Check
267 * for non-zero LQISTATE instead.
268 */
269 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
270 packetized = ahd_inb(ahd, LQISTATE) != 0;
271 } else {
272 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
273 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
274 }
275 ahd_restore_modes(ahd, saved_modes);
276 return (packetized);
277 }
278
279 static __inline int
280 ahd_set_active_fifo(struct ahd_softc *ahd)
281 {
282 u_int active_fifo;
283
284 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
285 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
286 switch (active_fifo) {
287 case 0:
288 case 1:
289 ahd_set_modes(ahd, active_fifo, active_fifo);
290 return (1);
291 default:
292 return (0);
293 }
294 }
295
296 /************************* Sequencer Execution Control ************************/
297 /*
298 * Restart the sequencer program from address zero
299 */
300 void
301 ahd_restart(struct ahd_softc *ahd)
302 {
303
304 ahd_pause(ahd);
305
306 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
307
308 /* No more pending messages */
309 ahd_clear_msg_state(ahd);
310 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
311 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
312 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
313 ahd_outb(ahd, SEQINTCTL, 0);
314 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
315 ahd_outb(ahd, SEQ_FLAGS, 0);
316 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
317 ahd_outb(ahd, SAVED_LUN, 0xFF);
318
319 /*
320 * Ensure that the sequencer's idea of TQINPOS
321 * matches our own. The sequencer increments TQINPOS
322 * only after it sees a DMA complete and a reset could
323 * occur before the increment leaving the kernel to believe
324 * the command arrived but the sequencer to not.
325 */
326 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
327
328 /* Always allow reselection */
329 ahd_outb(ahd, SCSISEQ1,
330 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
331 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
332 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
333 ahd_unpause(ahd);
334 }
335
336 void
337 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
338 {
339 ahd_mode_state saved_modes;
340
341 #ifdef AHD_DEBUG
342 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
343 kprintf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
344 #endif
345 saved_modes = ahd_save_modes(ahd);
346 ahd_set_modes(ahd, fifo, fifo);
347 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
348 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
349 ahd_outb(ahd, CCSGCTL, CCSGRESET);
350 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
351 ahd_outb(ahd, SG_STATE, 0);
352 ahd_restore_modes(ahd, saved_modes);
353 }
354
355 /************************* Input/Output Queues ********************************/
356 /*
357 * Flush and completed commands that are sitting in the command
358 * complete queues down on the chip but have yet to be dma'ed back up.
359 */
360 void
361 ahd_flush_qoutfifo(struct ahd_softc *ahd)
362 {
363 struct scb *scb;
364 ahd_mode_state saved_modes;
365 u_int saved_scbptr;
366 u_int ccscbctl;
367 u_int scbid;
368 u_int next_scbid;
369
370 saved_modes = ahd_save_modes(ahd);
371
372 /*
373 * Complete any SCBs that just finished being
374 * DMA'ed into the qoutfifo.
375 */
376 ahd_run_qoutfifo(ahd);
377
378 /*
379 * Flush the good status FIFO for compelted packetized commands.
380 */
381 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
382 saved_scbptr = ahd_get_scbptr(ahd);
383 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
384 u_int fifo_mode;
385 u_int i;
386
387 scbid = (ahd_inb(ahd, GSFIFO+1) << 8)
388 | ahd_inb(ahd, GSFIFO);
389 scb = ahd_lookup_scb(ahd, scbid);
390 if (scb == NULL) {
391 kprintf("%s: Warning - GSFIFO SCB %d invalid\n",
392 ahd_name(ahd), scbid);
393 continue;
394 }
395 /*
396 * Determine if this transaction is still active in
397 * any FIFO. If it is, we must flush that FIFO to
398 * the host before completing the command.
399 */
400 fifo_mode = 0;
401 for (i = 0; i < 2; i++) {
402 /* Toggle to the other mode. */
403 fifo_mode ^= 1;
404 ahd_set_modes(ahd, fifo_mode, fifo_mode);
405 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
406 continue;
407
408 ahd_run_data_fifo(ahd, scb);
409
410 /*
411 * Clearing this transaction in this FIFO may
412 * cause a CFG4DATA for this same transaction
413 * to assert in the other FIFO. Make sure we
414 * loop one more time and check the other FIFO.
415 */
416 i = 0;
417 }
418 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
419 ahd_set_scbptr(ahd, scbid);
420 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
421 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
422 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
423 & SG_LIST_NULL) != 0)) {
424 u_int comp_head;
425
426 /*
427 * The transfer completed with a residual.
428 * Place this SCB on the complete DMA list
429 * so that we Update our in-core copy of the
430 * SCB before completing the command.
431 */
432 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
433 ahd_outb(ahd, SCB_SGPTR,
434 ahd_inb_scbram(ahd, SCB_SGPTR)
435 | SG_STATUS_VALID);
436 ahd_outw(ahd, SCB_TAG, SCB_GET_TAG(scb));
437 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
438 ahd_outw(ahd, SCB_NEXT_COMPLETE, comp_head);
439 if (SCBID_IS_NULL(comp_head))
440 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD,
441 SCB_GET_TAG(scb));
442 } else
443 ahd_complete_scb(ahd, scb);
444 }
445 ahd_set_scbptr(ahd, saved_scbptr);
446
447 /*
448 * Setup for command channel portion of flush.
449 */
450 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
451
452 /*
453 * Wait for any inprogress DMA to complete and clear DMA state
454 * if this if for an SCB in the qinfifo.
455 */
456 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
457
458 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
459 if ((ccscbctl & ARRDONE) != 0)
460 break;
461 } else if ((ccscbctl & CCSCBDONE) != 0)
462 break;
463 ahd_delay(200);
464 }
465 if ((ccscbctl & CCSCBDIR) != 0)
466 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
467
468 saved_scbptr = ahd_get_scbptr(ahd);
469 /*
470 * Manually update/complete any completed SCBs that are waiting to be
471 * DMA'ed back up to the host.
472 */
473 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
474 while (!SCBID_IS_NULL(scbid)) {
475 uint8_t *hscb_ptr;
476 u_int i;
477
478 ahd_set_scbptr(ahd, scbid);
479 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
480 scb = ahd_lookup_scb(ahd, scbid);
481 if (scb == NULL) {
482 kprintf("%s: Warning - DMA-up and complete "
483 "SCB %d invalid\n", ahd_name(ahd), scbid);
484 continue;
485 }
486 hscb_ptr = (uint8_t *)scb->hscb;
487 for (i = 0; i < sizeof(struct hardware_scb); i++)
488 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
489
490 ahd_complete_scb(ahd, scb);
491 scbid = next_scbid;
492 }
493 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
494
495 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
496 while (!SCBID_IS_NULL(scbid)) {
497
498 ahd_set_scbptr(ahd, scbid);
499 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
500 scb = ahd_lookup_scb(ahd, scbid);
501 if (scb == NULL) {
502 kprintf("%s: Warning - Complete SCB %d invalid\n",
503 ahd_name(ahd), scbid);
504 continue;
505 }
506
507 ahd_complete_scb(ahd, scb);
508 scbid = next_scbid;
509 }
510 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
511
512 /*
513 * Restore state.
514 */
515 ahd_set_scbptr(ahd, saved_scbptr);
516 ahd_restore_modes(ahd, saved_modes);
517 ahd->flags |= AHD_UPDATE_PEND_CMDS;
518 }
519
520 /*
521 * Determine if an SCB for a packetized transaction
522 * is active in a FIFO.
523 */
524 static int
525 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
526 {
527
528 /*
529 * The FIFO is only active for our transaction if
530 * the SCBPTR matches the SCB's ID and the firmware
531 * has installed a handler for the FIFO or we have
532 * a pending SAVEPTRS or CFG4DATA interrupt.
533 */
534 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
535 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
536 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
537 return (0);
538
539 return (1);
540 }
541
542 /*
543 * Run a data fifo to completion for a transaction we know
544 * has completed across the SCSI bus (good status has been
545 * received). We are already set to the correct FIFO mode
546 * on entry to this routine.
547 *
548 * This function attempts to operate exactly as the firmware
549 * would when running this FIFO. Care must be taken to update
550 * this routine any time the firmware's FIFO algorithm is
551 * changed.
552 */
553 static void
554 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
555 {
556 u_int seqintsrc;
557
558 while (1) {
559 seqintsrc = ahd_inb(ahd, SEQINTSRC);
560 if ((seqintsrc & CFG4DATA) != 0) {
561 uint32_t datacnt;
562 uint32_t sgptr;
563
564 /*
565 * Clear full residual flag.
566 */
567 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
568 ahd_outb(ahd, SCB_SGPTR, sgptr);
569
570 /*
571 * Load datacnt and address.
572 */
573 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
574 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
575 sgptr |= LAST_SEG;
576 ahd_outb(ahd, SG_STATE, 0);
577 } else
578 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
579 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
580 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
581 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
582 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
583
584 /*
585 * Initialize Residual Fields.
586 */
587 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
588 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
589
590 /*
591 * Mark the SCB as having a FIFO in use.
592 */
593 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
594 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
595
596 /*
597 * Install a "fake" handler for this FIFO.
598 */
599 ahd_outw(ahd, LONGJMP_ADDR, 0);
600
601 /*
602 * Notify the hardware that we have satisfied
603 * this sequencer interrupt.
604 */
605 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
606 } else if ((seqintsrc & SAVEPTRS) != 0) {
607 uint32_t sgptr;
608 uint32_t resid;
609
610 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
611 /*
612 * Snapshot Save Pointers. Clear
613 * the snapshot and continue.
614 */
615 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
616 continue;
617 }
618
619 /*
620 * Disable S/G fetch so the DMA engine
621 * is available to future users.
622 */
623 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
624 ahd_outb(ahd, CCSGCTL, 0);
625 ahd_outb(ahd, SG_STATE, 0);
626
627 /*
628 * Flush the data FIFO. Strickly only
629 * necessary for Rev A parts.
630 */
631 ahd_outb(ahd, DFCNTRL,
632 ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
633
634 /*
635 * Calculate residual.
636 */
637 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
638 resid = ahd_inl(ahd, SHCNT);
639 resid |=
640 ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
641 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
642 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
643 /*
644 * Must back up to the correct S/G element.
645 * Typically this just means resetting our
646 * low byte to the offset in the SG_CACHE,
647 * but if we wrapped, we have to correct
648 * the other bytes of the sgptr too.
649 */
650 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
651 && (sgptr & 0x80) == 0)
652 sgptr -= 0x100;
653 sgptr &= ~0xFF;
654 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
655 & SG_ADDR_MASK;
656 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
657 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
658 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
659 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
660 sgptr | SG_LIST_NULL);
661 }
662 /*
663 * Save Pointers.
664 */
665 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
666 ahd_outl(ahd, SCB_DATACNT, resid);
667 ahd_outl(ahd, SCB_SGPTR, sgptr);
668 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
669 ahd_outb(ahd, SEQIMODE,
670 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
671 /*
672 * If the data is to the SCSI bus, we are
673 * done, otherwise wait for FIFOEMP.
674 */
675 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
676 break;
677 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
678 uint32_t sgptr;
679 uint64_t data_addr;
680 uint32_t data_len;
681 u_int dfcntrl;
682
683 /*
684 * Disable S/G fetch so the DMA engine
685 * is available to future users.
686 */
687 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
688 ahd_outb(ahd, CCSGCTL, 0);
689 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
690 }
691
692 /*
693 * Wait for the DMA engine to notice that the
694 * host transfer is enabled and that there is
695 * space in the S/G FIFO for new segments before
696 * loading more segments.
697 */
698 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) == 0)
699 continue;
700 if ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) == 0)
701 continue;
702
703 /*
704 * Determine the offset of the next S/G
705 * element to load.
706 */
707 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
708 sgptr &= SG_PTR_MASK;
709 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
710 struct ahd_dma64_seg *sg;
711
712 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
713 data_addr = sg->addr;
714 data_len = sg->len;
715 sgptr += sizeof(*sg);
716 } else {
717 struct ahd_dma_seg *sg;
718
719 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
720 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
721 data_addr <<= 8;
722 data_addr |= sg->addr;
723 data_len = sg->len;
724 sgptr += sizeof(*sg);
725 }
726
727 /*
728 * Update residual information.
729 */
730 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
731 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
732
733 /*
734 * Load the S/G.
735 */
736 if (data_len & AHD_DMA_LAST_SEG) {
737 sgptr |= LAST_SEG;
738 ahd_outb(ahd, SG_STATE, 0);
739 }
740 ahd_outq(ahd, HADDR, data_addr);
741 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
742 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
743
744 /*
745 * Advertise the segment to the hardware.
746 */
747 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
748 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS)!=0) {
749 /*
750 * Use SCSIENWRDIS so that SCSIEN
751 * is never modified by this
752 * operation.
753 */
754 dfcntrl |= SCSIENWRDIS;
755 }
756 ahd_outb(ahd, DFCNTRL, dfcntrl);
757 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW)
758 & LAST_SEG_DONE) != 0) {
759
760 /*
761 * Transfer completed to the end of SG list
762 * and has flushed to the host.
763 */
764 ahd_outb(ahd, SCB_SGPTR,
765 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
766 break;
767 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
768 break;
769 }
770 ahd_delay(200);
771 }
772 /*
773 * Clear any handler for this FIFO, decrement
774 * the FIFO use count for the SCB, and release
775 * the FIFO.
776 */
777 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
778 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
779 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
780 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
781 }
782
783 void
784 ahd_run_qoutfifo(struct ahd_softc *ahd)
785 {
786 struct scb *scb;
787 u_int scb_index;
788
789 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
790 panic("ahd_run_qoutfifo recursion");
791 ahd->flags |= AHD_RUNNING_QOUTFIFO;
792 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
793 while ((ahd->qoutfifo[ahd->qoutfifonext]
794 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) {
795
796 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext]
797 & ~QOUTFIFO_ENTRY_VALID_LE);
798 scb = ahd_lookup_scb(ahd, scb_index);
799 if (scb == NULL) {
800 kprintf("%s: WARNING no command for scb %d "
801 "(cmdcmplt)\nQOUTPOS = %d\n",
802 ahd_name(ahd), scb_index,
803 ahd->qoutfifonext);
804 ahd_dump_card_state(ahd);
805 } else
806 ahd_complete_scb(ahd, scb);
807
808 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
809 if (ahd->qoutfifonext == 0)
810 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE;
811 }
812 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
813 }
814
815 /************************* Interrupt Handling *********************************/
816 void
817 ahd_handle_hwerrint(struct ahd_softc *ahd)
818 {
819 /*
820 * Some catastrophic hardware error has occurred.
821 * Print it for the user and disable the controller.
822 */
823 int i;
824 int error;
825
826 error = ahd_inb(ahd, ERROR);
827 for (i = 0; i < num_errors; i++) {
828 if ((error & ahd_hard_errors[i].error) != 0)
829 kprintf("%s: hwerrint, %s\n",
830 ahd_name(ahd), ahd_hard_errors[i].errmesg);
831 }
832
833 ahd_dump_card_state(ahd);
834 panic("BRKADRINT");
835
836 /* Tell everyone that this HBA is no longer available */
837 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
838 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
839 CAM_NO_HBA);
840
841 /* Tell the system that this controller has gone away. */
842 ahd_free(ahd);
843 }
844
845 void
846 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
847 {
848 u_int seqintcode;
849
850 /*
851 * Save the sequencer interrupt code and clear the SEQINT
852 * bit. We will unpause the sequencer, if appropriate,
853 * after servicing the request.
854 */
855 seqintcode = ahd_inb(ahd, SEQINTCODE);
856 ahd_outb(ahd, CLRINT, CLRSEQINT);
857 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
858 /*
859 * Unpause the sequencer and let it clear
860 * SEQINT by writing NO_SEQINT to it. This
861 * will cause the sequencer to be paused again,
862 * which is the expected state of this routine.
863 */
864 ahd_unpause(ahd);
865 while (!ahd_is_paused(ahd))
866 ;
867 ahd_outb(ahd, CLRINT, CLRSEQINT);
868 }
869 ahd_update_modes(ahd);
870 #ifdef AHD_DEBUG
871 if ((ahd_debug & AHD_SHOW_MISC) != 0)
872 kprintf("%s: Handle Seqint Called for code %d\n",
873 ahd_name(ahd), seqintcode);
874 #endif
875 switch (seqintcode) {
876 case BAD_SCB_STATUS:
877 {
878 struct scb *scb;
879 u_int scbid;
880 int cmds_pending;
881
882 scbid = ahd_get_scbptr(ahd);
883 scb = ahd_lookup_scb(ahd, scbid);
884 if (scb != NULL) {
885 ahd_complete_scb(ahd, scb);
886 } else {
887 kprintf("%s: WARNING no command for scb %d "
888 "(bad status)\n", ahd_name(ahd), scbid);
889 ahd_dump_card_state(ahd);
890 }
891 cmds_pending = ahd_inw(ahd, CMDS_PENDING);
892 if (cmds_pending > 0)
893 ahd_outw(ahd, CMDS_PENDING, cmds_pending - 1);
894 break;
895 }
896 case ENTERING_NONPACK:
897 {
898 struct scb *scb;
899 u_int scbid;
900
901 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
902 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
903 scbid = ahd_get_scbptr(ahd);
904 scb = ahd_lookup_scb(ahd, scbid);
905 if (scb == NULL) {
906 /*
907 * Somehow need to know if this
908 * is from a selection or reselection.
909 * From that, we can determine target
910 * ID so we at least have an I_T nexus.
911 */
912 } else {
913 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
914 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
915 ahd_outb(ahd, SEQ_FLAGS, 0x0);
916 }
917 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
918 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
919 /*
920 * Phase change after read stream with
921 * CRC error with P0 asserted on last
922 * packet.
923 */
924 #ifdef AHD_DEBUG
925 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
926 kprintf("%s: Assuming LQIPHASE_NLQ with "
927 "P0 assertion\n", ahd_name(ahd));
928 #endif
929 }
930 #ifdef AHD_DEBUG
931 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
932 kprintf("%s: Entering NONPACK\n", ahd_name(ahd));
933 #endif
934 break;
935 }
936 case INVALID_SEQINT:
937 kprintf("%s: Invalid Sequencer interrupt occurred.\n",
938 ahd_name(ahd));
939 ahd_dump_card_state(ahd);
940 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
941 break;
942 case STATUS_OVERRUN:
943 {
944 struct scb *scb;
945 u_int scbid;
946
947 scbid = ahd_get_scbptr(ahd);
948 scb = ahd_lookup_scb(ahd, scbid);
949 if (scb != NULL)
950 ahd_print_path(ahd, scb);
951 else
952 kprintf("%s: ", ahd_name(ahd));
953 kprintf("SCB %d Packetized Status Overrun", scbid);
954 ahd_dump_card_state(ahd);
955 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
956 break;
957 }
958 case CFG4ISTAT_INTR:
959 {
960 struct scb *scb;
961 u_int scbid;
962
963 scbid = ahd_get_scbptr(ahd);
964 scb = ahd_lookup_scb(ahd, scbid);
965 if (scb == NULL) {
966 ahd_dump_card_state(ahd);
967 kprintf("CFG4ISTAT: Free SCB %d referenced", scbid);
968 panic("For safety");
969 }
970 ahd_outq(ahd, HADDR, scb->sense_busaddr);
971 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
972 ahd_outb(ahd, HCNT + 2, 0);
973 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
974 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
975 break;
976 }
977 case ILLEGAL_PHASE:
978 {
979 u_int bus_phase;
980
981 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
982 kprintf("%s: ILLEGAL_PHASE 0x%x\n",
983 ahd_name(ahd), bus_phase);
984
985 switch (bus_phase) {
986 case P_DATAOUT:
987 case P_DATAIN:
988 case P_DATAOUT_DT:
989 case P_DATAIN_DT:
990 case P_MESGOUT:
991 case P_STATUS:
992 case P_MESGIN:
993 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
994 kprintf("%s: Issued Bus Reset.\n", ahd_name(ahd));
995 break;
996 case P_COMMAND:
997 {
998 struct ahd_devinfo devinfo;
999 struct scb *scb;
1000 struct ahd_initiator_tinfo *targ_info;
1001 struct ahd_tmode_tstate *tstate;
1002 struct ahd_transinfo *tinfo;
1003 u_int scbid;
1004
1005 /*
1006 * If a target takes us into the command phase
1007 * assume that it has been externally reset and
1008 * has thus lost our previous packetized negotiation
1009 * agreement. Since we have not sent an identify
1010 * message and may not have fully qualified the
1011 * connection, we change our command to TUR, assert
1012 * ATN and ABORT the task when we go to message in
1013 * phase. The OSM will see the REQUEUE_REQUEST
1014 * status and retry the command.
1015 */
1016 scbid = ahd_get_scbptr(ahd);
1017 scb = ahd_lookup_scb(ahd, scbid);
1018 if (scb == NULL) {
1019 kprintf("Invalid phase with no valid SCB. "
1020 "Resetting bus.\n");
1021 ahd_reset_channel(ahd, 'A',
1022 /*Initiate Reset*/TRUE);
1023 break;
1024 }
1025 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1026 SCB_GET_TARGET(ahd, scb),
1027 SCB_GET_LUN(scb),
1028 SCB_GET_CHANNEL(ahd, scb),
1029 ROLE_INITIATOR);
1030 targ_info = ahd_fetch_transinfo(ahd,
1031 devinfo.channel,
1032 devinfo.our_scsiid,
1033 devinfo.target,
1034 &tstate);
1035 tinfo = &targ_info->curr;
1036 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1037 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1038 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1039 /*offset*/0, /*ppr_options*/0,
1040 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1041 ahd_outb(ahd, SCB_CDB_STORE, 0);
1042 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1043 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1044 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1045 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1046 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1047 ahd_outb(ahd, SCB_CDB_LEN, 6);
1048 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1049 scb->hscb->control |= MK_MESSAGE;
1050 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1051 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1052 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1053 /*
1054 * The lun is 0, regardless of the SCB's lun
1055 * as we have not sent an identify message.
1056 */
1057 ahd_outb(ahd, SAVED_LUN, 0);
1058 ahd_outb(ahd, SEQ_FLAGS, 0);
1059 ahd_assert_atn(ahd);
1060 scb->flags &= ~(SCB_PACKETIZED);
1061 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1062 ahd_freeze_devq(ahd, scb);
1063 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
1064 ahd_freeze_scb(scb);
1065
1066 /*
1067 * Allow the sequencer to continue with
1068 * non-pack processing.
1069 */
1070 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1071 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1072 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1073 ahd_outb(ahd, CLRLQOINT1, 0);
1074 }
1075 #ifdef AHD_DEBUG
1076 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1077 ahd_print_path(ahd, scb);
1078 kprintf("Unexpected command phase from "
1079 "packetized target\n");
1080 }
1081 #endif
1082 break;
1083 }
1084 }
1085 break;
1086 }
1087 case CFG4OVERRUN:
1088 {
1089 struct scb *scb;
1090 u_int scb_index;
1091
1092 #ifdef AHD_DEBUG
1093 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1094 kprintf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1095 ahd_inb(ahd, MODE_PTR));
1096 }
1097 #endif
1098 scb_index = ahd_get_scbptr(ahd);
1099 scb = ahd_lookup_scb(ahd, scb_index);
1100 if (scb == NULL) {
1101 /*
1102 * Attempt to transfer to an SCB that is
1103 * not outstanding.
1104 */
1105 ahd_assert_atn(ahd);
1106 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1107 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1108 ahd->msgout_len = 1;
1109 ahd->msgout_index = 0;
1110 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1111 /*
1112 * Clear status received flag to prevent any
1113 * attempt to complete this bogus SCB.
1114 */
1115 ahd_outb(ahd, SCB_CONTROL,
1116 ahd_inb_scbram(ahd, SCB_CONTROL)
1117 & ~STATUS_RCVD);
1118 }
1119 break;
1120 }
1121 case DUMP_CARD_STATE:
1122 {
1123 ahd_dump_card_state(ahd);
1124 break;
1125 }
1126 case PDATA_REINIT:
1127 {
1128 #ifdef AHD_DEBUG
1129 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1130 kprintf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1131 "SG_CACHE_SHADOW = 0x%x\n",
1132 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1133 ahd_inb(ahd, SG_CACHE_SHADOW));
1134 }
1135 #endif
1136 ahd_reinitialize_dataptrs(ahd);
1137 break;
1138 }
1139 case HOST_MSG_LOOP:
1140 {
1141 struct ahd_devinfo devinfo;
1142
1143 /*
1144 * The sequencer has encountered a message phase
1145 * that requires host assistance for completion.
1146 * While handling the message phase(s), we will be
1147 * notified by the sequencer after each byte is
1148 * transfered so we can track bus phase changes.
1149 *
1150 * If this is the first time we've seen a HOST_MSG_LOOP
1151 * interrupt, initialize the state of the host message
1152 * loop.
1153 */
1154 ahd_fetch_devinfo(ahd, &devinfo);
1155 if (ahd->msg_type == MSG_TYPE_NONE) {
1156 struct scb *scb;
1157 u_int scb_index;
1158 u_int bus_phase;
1159
1160 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1161 if (bus_phase != P_MESGIN
1162 && bus_phase != P_MESGOUT) {
1163 kprintf("ahd_intr: HOST_MSG_LOOP bad "
1164 "phase 0x%x\n", bus_phase);
1165 /*
1166 * Probably transitioned to bus free before
1167 * we got here. Just punt the message.
1168 */
1169 ahd_dump_card_state(ahd);
1170 ahd_clear_intstat(ahd);
1171 ahd_restart(ahd);
1172 return;
1173 }
1174
1175 scb_index = ahd_get_scbptr(ahd);
1176 scb = ahd_lookup_scb(ahd, scb_index);
1177 if (devinfo.role == ROLE_INITIATOR) {
1178 if (bus_phase == P_MESGOUT)
1179 ahd_setup_initiator_msgout(ahd,
1180 &devinfo,
1181 scb);
1182 else {
1183 ahd->msg_type =
1184 MSG_TYPE_INITIATOR_MSGIN;
1185 ahd->msgin_index = 0;
1186 }
1187 }
1188 #if AHD_TARGET_MODE
1189 else {
1190 if (bus_phase == P_MESGOUT) {
1191 ahd->msg_type =
1192 MSG_TYPE_TARGET_MSGOUT;
1193 ahd->msgin_index = 0;
1194 }
1195 else
1196 ahd_setup_target_msgin(ahd,
1197 &devinfo,
1198 scb);
1199 }
1200 #endif
1201 }
1202
1203 ahd_handle_message_phase(ahd);
1204 break;
1205 }
1206 case NO_MATCH:
1207 {
1208 /* Ensure we don't leave the selection hardware on */
1209 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1210 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1211
1212 kprintf("%s:%c:%d: no active SCB for reconnecting "
1213 "target - issuing BUS DEVICE RESET\n",
1214 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1215 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1216 "REG0 == 0x%x ACCUM = 0x%x\n",
1217 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1218 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1219 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1220 "SINDEX == 0x%x\n",
1221 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1222 ahd_find_busy_tcl(ahd,
1223 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1224 ahd_inb(ahd, SAVED_LUN))),
1225 ahd_inw(ahd, SINDEX));
1226 kprintf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1227 "SCB_CONTROL == 0x%x\n",
1228 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1229 ahd_inb_scbram(ahd, SCB_LUN),
1230 ahd_inb_scbram(ahd, SCB_CONTROL));
1231 kprintf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1232 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1233 kprintf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1234 kprintf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1235 ahd_dump_card_state(ahd);
1236 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1237 ahd->msgout_len = 1;
1238 ahd->msgout_index = 0;
1239 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1240 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1241 ahd_assert_atn(ahd);
1242 break;
1243 }
1244 case PROTO_VIOLATION:
1245 {
1246 ahd_handle_proto_violation(ahd);
1247 break;
1248 }
1249 case IGN_WIDE_RES:
1250 {
1251 struct ahd_devinfo devinfo;
1252
1253 ahd_fetch_devinfo(ahd, &devinfo);
1254 ahd_handle_ign_wide_residue(ahd, &devinfo);
1255 break;
1256 }
1257 case BAD_PHASE:
1258 {
1259 u_int lastphase;
1260
1261 lastphase = ahd_inb(ahd, LASTPHASE);
1262 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
1263 "lastphase = 0x%x. Attempting to continue\n",
1264 ahd_name(ahd), 'A',
1265 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1266 lastphase, ahd_inb(ahd, SCSISIGI));
1267 break;
1268 }
1269 case MISSED_BUSFREE:
1270 {
1271 u_int lastphase;
1272
1273 lastphase = ahd_inb(ahd, LASTPHASE);
1274 kprintf("%s:%c:%d: Missed busfree. "
1275 "Lastphase = 0x%x, Curphase = 0x%x\n",
1276 ahd_name(ahd), 'A',
1277 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1278 lastphase, ahd_inb(ahd, SCSISIGI));
1279 ahd_restart(ahd);
1280 return;
1281 }
1282 case DATA_OVERRUN:
1283 {
1284 /*
1285 * When the sequencer detects an overrun, it
1286 * places the controller in "BITBUCKET" mode
1287 * and allows the target to complete its transfer.
1288 * Unfortunately, none of the counters get updated
1289 * when the controller is in this mode, so we have
1290 * no way of knowing how large the overrun was.
1291 */
1292 struct scb *scb;
1293 u_int scbindex;
1294 #ifdef AHD_DEBUG
1295 u_int lastphase;
1296 #endif
1297
1298 scbindex = ahd_get_scbptr(ahd);
1299 scb = ahd_lookup_scb(ahd, scbindex);
1300 #ifdef AHD_DEBUG
1301 lastphase = ahd_inb(ahd, LASTPHASE);
1302 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1303 ahd_print_path(ahd, scb);
1304 kprintf("data overrun detected %s. Tag == 0x%x.\n",
1305 ahd_lookup_phase_entry(lastphase)->phasemsg,
1306 SCB_GET_TAG(scb));
1307 ahd_print_path(ahd, scb);
1308 kprintf("%s seen Data Phase. Length = %ld. "
1309 "NumSGs = %d.\n",
1310 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1311 ? "Have" : "Haven't",
1312 ahd_get_transfer_length(scb), scb->sg_count);
1313 ahd_dump_sglist(scb);
1314 }
1315 #endif
1316
1317 /*
1318 * Set this and it will take effect when the
1319 * target does a command complete.
1320 */
1321 ahd_freeze_devq(ahd, scb);
1322 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1323 ahd_freeze_scb(scb);
1324 break;
1325 }
1326 case MKMSG_FAILED:
1327 {
1328 struct ahd_devinfo devinfo;
1329 struct scb *scb;
1330 u_int scbid;
1331
1332 ahd_fetch_devinfo(ahd, &devinfo);
1333 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
1334 ahd_name(ahd), devinfo.channel, devinfo.target,
1335 devinfo.lun);
1336 scbid = ahd_get_scbptr(ahd);
1337 scb = ahd_lookup_scb(ahd, scbid);
1338 if (scb != NULL
1339 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1340 /*
1341 * Ensure that we didn't put a second instance of this
1342 * SCB into the QINFIFO.
1343 */
1344 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1345 SCB_GET_CHANNEL(ahd, scb),
1346 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1347 ROLE_INITIATOR, /*status*/0,
1348 SEARCH_REMOVE);
1349 ahd_outb(ahd, SCB_CONTROL,
1350 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1351 break;
1352 }
1353 case TASKMGMT_FUNC_COMPLETE:
1354 {
1355 u_int scbid;
1356 struct scb *scb;
1357
1358 scbid = ahd_get_scbptr(ahd);
1359 scb = ahd_lookup_scb(ahd, scbid);
1360 if (scb != NULL) {
1361 u_int lun;
1362 u_int tag;
1363 cam_status error;
1364
1365 ahd_print_path(ahd, scb);
1366 kprintf("Task Management Func 0x%x Complete\n",
1367 scb->hscb->task_management);
1368 lun = CAM_LUN_WILDCARD;
1369 tag = SCB_LIST_NULL;
1370
1371 switch (scb->hscb->task_management) {
1372 case SIU_TASKMGMT_ABORT_TASK:
1373 tag = SCB_GET_TAG(scb);
1374 case SIU_TASKMGMT_ABORT_TASK_SET:
1375 case SIU_TASKMGMT_CLEAR_TASK_SET:
1376 lun = scb->hscb->lun;
1377 error = CAM_REQ_ABORTED;
1378 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1379 'A', lun, tag, ROLE_INITIATOR,
1380 error);
1381 break;
1382 case SIU_TASKMGMT_LUN_RESET:
1383 lun = scb->hscb->lun;
1384 case SIU_TASKMGMT_TARGET_RESET:
1385 {
1386 struct ahd_devinfo devinfo;
1387
1388 ahd_scb_devinfo(ahd, &devinfo, scb);
1389 error = CAM_BDR_SENT;
1390 ahd_handle_devreset(ahd, &devinfo, lun,
1391 CAM_BDR_SENT,
1392 lun != CAM_LUN_WILDCARD
1393 ? "Lun Reset"
1394 : "Target Reset",
1395 /*verbose_level*/0);
1396 break;
1397 }
1398 default:
1399 panic("Unexpected TaskMgmt Func\n");
1400 break;
1401 }
1402 }
1403 break;
1404 }
1405 case TASKMGMT_CMD_CMPLT_OKAY:
1406 {
1407 u_int scbid;
1408 struct scb *scb;
1409
1410 /*
1411 * An ABORT TASK TMF failed to be delivered before
1412 * the targeted command completed normally.
1413 */
1414 scbid = ahd_get_scbptr(ahd);
1415 scb = ahd_lookup_scb(ahd, scbid);
1416 if (scb != NULL) {
1417 /*
1418 * Remove the second instance of this SCB from
1419 * the QINFIFO if it is still there.
1420 */
1421 ahd_print_path(ahd, scb);
1422 kprintf("SCB completes before TMF\n");
1423 /*
1424 * Handle losing the race. Wait until any
1425 * current selection completes. We will then
1426 * set the TMF back to zero in this SCB so that
1427 * the sequencer doesn't bother to issue another
1428 * sequencer interrupt for its completion.
1429 */
1430 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1431 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1432 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1433 ;
1434 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1435 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1436 SCB_GET_CHANNEL(ahd, scb),
1437 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1438 ROLE_INITIATOR, /*status*/0,
1439 SEARCH_REMOVE);
1440 }
1441 break;
1442 }
1443 case TRACEPOINT0:
1444 case TRACEPOINT1:
1445 case TRACEPOINT2:
1446 case TRACEPOINT3:
1447 kprintf("%s: Tracepoint %d\n", ahd_name(ahd),
1448 seqintcode - TRACEPOINT0);
1449 break;
1450 case NO_SEQINT:
1451 break;
1452 case SAW_HWERR:
1453 ahd_handle_hwerrint(ahd);
1454 break;
1455 default:
1456 kprintf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1457 seqintcode);
1458 break;
1459 }
1460 /*
1461 * The sequencer is paused immediately on
1462 * a SEQINT, so we should restart it when
1463 * we're done.
1464 */
1465 ahd_unpause(ahd);
1466 }
1467
1468 void
1469 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1470 {
1471 struct scb *scb;
1472 u_int status0;
1473 u_int status3;
1474 u_int status;
1475 u_int lqistat1;
1476 u_int lqostat0;
1477 u_int scbid;
1478 u_int busfreetime;
1479
1480 ahd_update_modes(ahd);
1481 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1482
1483 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1484 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1485 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1486 lqistat1 = ahd_inb(ahd, LQISTAT1);
1487 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1488 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1489 if ((status0 & (SELDI|SELDO)) != 0) {
1490 u_int simode0;
1491
1492 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1493 simode0 = ahd_inb(ahd, SIMODE0);
1494 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1495 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1496 }
1497 scbid = ahd_get_scbptr(ahd);
1498 scb = ahd_lookup_scb(ahd, scbid);
1499 if (scb != NULL
1500 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1501 scb = NULL;
1502
1503 /* Make sure the sequencer is in a safe location. */
1504 ahd_clear_critical_section(ahd);
1505
1506 if ((status0 & IOERR) != 0) {
1507 u_int now_lvd;
1508
1509 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1510 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1511 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1512 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1513 /*
1514 * A change in I/O mode is equivalent to a bus reset.
1515 */
1516 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1517 ahd_pause(ahd);
1518 ahd_setup_iocell_workaround(ahd);
1519 ahd_unpause(ahd);
1520 } else if ((status0 & OVERRUN) != 0) {
1521 kprintf("%s: SCSI offset overrun detected. Resetting bus.\n",
1522 ahd_name(ahd));
1523 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1524 } else if ((status & SCSIRSTI) != 0) {
1525 kprintf("%s: Someone reset channel A\n", ahd_name(ahd));
1526 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1527 } else if ((status & SCSIPERR) != 0) {
1528 ahd_handle_transmission_error(ahd);
1529 } else if (lqostat0 != 0) {
1530 kprintf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1531 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1532 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1533 ahd_outb(ahd, CLRLQOINT1, 0);
1534 }
1535 } else if ((status & SELTO) != 0) {
1536 u_int scbid;
1537
1538 /* Stop the selection */
1539 ahd_outb(ahd, SCSISEQ0, 0);
1540
1541 /* No more pending messages */
1542 ahd_clear_msg_state(ahd);
1543
1544 /* Clear interrupt state */
1545 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1546
1547 /*
1548 * Although the driver does not care about the
1549 * 'Selection in Progress' status bit, the busy
1550 * LED does. SELINGO is only cleared by a successful
1551 * selection, so we must manually clear it to insure
1552 * the LED turns off just in case no future successful
1553 * selections occur (e.g. no devices on the bus).
1554 */
1555 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1556
1557 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1558 scb = ahd_lookup_scb(ahd, scbid);
1559 if (scb == NULL) {
1560 kprintf("%s: ahd_intr - referenced scb not "
1561 "valid during SELTO scb(0x%x)\n",
1562 ahd_name(ahd), scbid);
1563 ahd_dump_card_state(ahd);
1564 } else {
1565 struct ahd_devinfo devinfo;
1566 #ifdef AHD_DEBUG
1567 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1568 ahd_print_path(ahd, scb);
1569 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1570 scbid);
1571 }
1572 #endif
1573 /*
1574 * Force a renegotiation with this target just in
1575 * case the cable was pulled and will later be
1576 * re-attached. The target may forget its negotiation
1577 * settings with us should it attempt to reselect
1578 * during the interruption. The target will not issue
1579 * a unit attention in this case, so we must always
1580 * renegotiate.
1581 */
1582 ahd_scb_devinfo(ahd, &devinfo, scb);
1583 ahd_force_renegotiation(ahd, &devinfo);
1584 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1585 ahd_freeze_devq(ahd, scb);
1586 }
1587 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1588 ahd_iocell_first_selection(ahd);
1589 ahd_unpause(ahd);
1590 } else if ((status0 & (SELDI|SELDO)) != 0) {
1591 ahd_iocell_first_selection(ahd);
1592 ahd_unpause(ahd);
1593 } else if (status3 != 0) {
1594 kprintf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1595 ahd_name(ahd), status3);
1596 ahd_outb(ahd, CLRSINT3, status3);
1597 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1598 ahd_handle_lqiphase_error(ahd, lqistat1);
1599 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1600 /*
1601 * This status can be delayed during some
1602 * streaming operations. The SCSIPHASE
1603 * handler has already dealt with this case
1604 * so just clear the error.
1605 */
1606 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1607 } else if ((status & BUSFREE) != 0) {
1608 u_int lqostat1;
1609 int restart;
1610 int clear_fifo;
1611 int packetized;
1612 u_int mode;
1613
1614 /*
1615 * Clear our selection hardware as soon as possible.
1616 * We may have an entry in the waiting Q for this target,
1617 * that is affected by this busfree and we don't want to
1618 * go about selecting the target while we handle the event.
1619 */
1620 ahd_outb(ahd, SCSISEQ0, 0);
1621
1622 /*
1623 * Determine what we were up to at the time of
1624 * the busfree.
1625 */
1626 mode = AHD_MODE_SCSI;
1627 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1628 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1629 switch (busfreetime) {
1630 case BUSFREE_DFF0:
1631 case BUSFREE_DFF1:
1632 {
1633 u_int scbid;
1634 struct scb *scb;
1635
1636 mode = busfreetime == BUSFREE_DFF0
1637 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1638 ahd_set_modes(ahd, mode, mode);
1639 scbid = ahd_get_scbptr(ahd);
1640 scb = ahd_lookup_scb(ahd, scbid);
1641 if (scb == NULL) {
1642 kprintf("%s: Invalid SCB %d in DFF%d "
1643 "during unexpected busfree\n",
1644 ahd_name(ahd), scbid, mode);
1645 packetized = 0;
1646 } else
1647 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1648 clear_fifo = 1;
1649 break;
1650 }
1651 case BUSFREE_LQO:
1652 clear_fifo = 0;
1653 packetized = 1;
1654 break;
1655 default:
1656 clear_fifo = 0;
1657 packetized = (lqostat1 & LQOBUSFREE) != 0;
1658 if (!packetized
1659 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE)
1660 packetized = 1;
1661 break;
1662 }
1663
1664 #ifdef AHD_DEBUG
1665 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1666 kprintf("Saw Busfree. Busfreetime = 0x%x.\n",
1667 busfreetime);
1668 #endif
1669 /*
1670 * Busfrees that occur in non-packetized phases are
1671 * handled by the nonpkt_busfree handler.
1672 */
1673 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1674 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1675 } else {
1676 packetized = 0;
1677 restart = ahd_handle_nonpkt_busfree(ahd);
1678 }
1679 /*
1680 * Clear the busfree interrupt status. The setting of
1681 * the interrupt is a pulse, so in a perfect world, we
1682 * would not need to muck with the ENBUSFREE logic. This
1683 * would ensure that if the bus moves on to another
1684 * connection, busfree protection is still in force. If
1685 * BUSFREEREV is broken, however, we must manually clear
1686 * the ENBUSFREE if the busfree occurred during a non-pack
1687 * connection so that we don't get false positives during
1688 * future, packetized, connections.
1689 */
1690 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1691 if (packetized == 0
1692 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1693 ahd_outb(ahd, SIMODE1,
1694 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1695
1696 if (clear_fifo)
1697 ahd_clear_fifo(ahd, mode);
1698
1699 ahd_clear_msg_state(ahd);
1700 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1701 if (restart) {
1702 ahd_restart(ahd);
1703 } else {
1704 ahd_unpause(ahd);
1705 }
1706 } else {
1707 kprintf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1708 ahd_name(ahd), status);
1709 ahd_dump_card_state(ahd);
1710 ahd_clear_intstat(ahd);
1711 ahd_unpause(ahd);
1712 }
1713 }
1714
1715 static void
1716 ahd_handle_transmission_error(struct ahd_softc *ahd)
1717 {
1718 struct scb *scb;
1719 u_int scbid;
1720 u_int lqistat1;
1721 u_int lqistat2;
1722 u_int msg_out;
1723 u_int curphase;
1724 u_int lastphase;
1725 u_int perrdiag;
1726 u_int cur_col;
1727 int silent;
1728
1729 scb = NULL;
1730 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1731 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1732 lqistat2 = ahd_inb(ahd, LQISTAT2);
1733 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1734 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1735 u_int lqistate;
1736
1737 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1738 lqistate = ahd_inb(ahd, LQISTATE);
1739 if ((lqistate >= 0x1E && lqistate <= 0x24)
1740 || (lqistate == 0x29)) {
1741 #ifdef AHD_DEBUG
1742 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1743 kprintf("%s: NLQCRC found via LQISTATE\n",
1744 ahd_name(ahd));
1745 }
1746 #endif
1747 lqistat1 |= LQICRCI_NLQ;
1748 }
1749 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1750 }
1751
1752 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1753 lastphase = ahd_inb(ahd, LASTPHASE);
1754 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1755 perrdiag = ahd_inb(ahd, PERRDIAG);
1756 msg_out = MSG_INITIATOR_DET_ERR;
1757 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1758
1759 /*
1760 * Try to find the SCB associated with this error.
1761 */
1762 silent = FALSE;
1763 if (lqistat1 == 0
1764 || (lqistat1 & LQICRCI_NLQ) != 0) {
1765 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1766 ahd_set_active_fifo(ahd);
1767 scbid = ahd_get_scbptr(ahd);
1768 scb = ahd_lookup_scb(ahd, scbid);
1769 if (scb != NULL && SCB_IS_SILENT(scb))
1770 silent = TRUE;
1771 }
1772
1773 cur_col = 0;
1774 if (silent == FALSE) {
1775 kprintf("%s: Transmission error detected\n", ahd_name(ahd));
1776 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1777 ahd_lastphase_print(lastphase, &cur_col, 50);
1778 ahd_scsisigi_print(curphase, &cur_col, 50);
1779 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1780 kprintf("\n");
1781 ahd_dump_card_state(ahd);
1782 }
1783
1784 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1785 if (silent == FALSE) {
1786 kprintf("%s: Gross protocol error during incoming "
1787 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1788 ahd_name(ahd), lqistat1);
1789 }
1790 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1791 return;
1792 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1793 /*
1794 * A CRC error has been detected on an incoming LQ.
1795 * The bus is currently hung on the last ACK.
1796 * Hit LQIRETRY to release the last ack, and
1797 * wait for the sequencer to determine that ATNO
1798 * is asserted while in message out to take us
1799 * to our host message loop. No NONPACKREQ or
1800 * LQIPHASE type errors will occur in this
1801 * scenario. After this first LQIRETRY, the LQI
1802 * manager will be in ISELO where it will
1803 * happily sit until another packet phase begins.
1804 * Unexpected bus free detection is enabled
1805 * through any phases that occur after we release
1806 * this last ack until the LQI manager sees a
1807 * packet phase. This implies we may have to
1808 * ignore a perfectly valid "unexected busfree"
1809 * after our "initiator detected error" message is
1810 * sent. A busfree is the expected response after
1811 * we tell the target that it's L_Q was corrupted.
1812 * (SPI4R09 10.7.3.3.3)
1813 */
1814 ahd_outb(ahd, LQCTL2, LQIRETRY);
1815 kprintf("LQIRetry for LQICRCI_LQ to release ACK\n");
1816 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1817 /*
1818 * We detected a CRC error in a NON-LQ packet.
1819 * The hardware has varying behavior in this situation
1820 * depending on whether this packet was part of a
1821 * stream or not.
1822 *
1823 * PKT by PKT mode:
1824 * The hardware has already acked the complete packet.
1825 * If the target honors our outstanding ATN condition,
1826 * we should be (or soon will be) in MSGOUT phase.
1827 * This will trigger the LQIPHASE_LQ status bit as the
1828 * hardware was expecting another LQ. Unexpected
1829 * busfree detection is enabled. Once LQIPHASE_LQ is
1830 * true (first entry into host message loop is much
1831 * the same), we must clear LQIPHASE_LQ and hit
1832 * LQIRETRY so the hardware is ready to handle
1833 * a future LQ. NONPACKREQ will not be asserted again
1834 * once we hit LQIRETRY until another packet is
1835 * processed. The target may either go busfree
1836 * or start another packet in response to our message.
1837 *
1838 * Read Streaming P0 asserted:
1839 * If we raise ATN and the target completes the entire
1840 * stream (P0 asserted during the last packet), the
1841 * hardware will ack all data and return to the ISTART
1842 * state. When the target reponds to our ATN condition,
1843 * LQIPHASE_LQ will be asserted. We should respond to
1844 * this with an LQIRETRY to prepare for any future
1845 * packets. NONPACKREQ will not be asserted again
1846 * once we hit LQIRETRY until another packet is
1847 * processed. The target may either go busfree or
1848 * start another packet in response to our message.
1849 * Busfree detection is enabled.
1850 *
1851 * Read Streaming P0 not asserted:
1852 * If we raise ATN and the target transitions to
1853 * MSGOUT in or after a packet where P0 is not
1854 * asserted, the hardware will assert LQIPHASE_NLQ.
1855 * We should respond to the LQIPHASE_NLQ with an
1856 * LQIRETRY. Should the target stay in a non-pkt
1857 * phase after we send our message, the hardware
1858 * will assert LQIPHASE_LQ. Recovery is then just as
1859 * listed above for the read streaming with P0 asserted.
1860 * Busfree detection is enabled.
1861 */
1862 if (silent == FALSE)
1863 kprintf("LQICRC_NLQ\n");
1864 if (scb == NULL) {
1865 kprintf("%s: No SCB valid for LQICRC_NLQ. "
1866 "Resetting bus\n", ahd_name(ahd));
1867 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1868 return;
1869 }
1870 } else if ((lqistat1 & LQIBADLQI) != 0) {
1871 kprintf("Need to handle BADLQI!\n");
1872 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1873 return;
1874 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1875 if ((curphase & ~P_DATAIN_DT) != 0) {
1876 /* Ack the byte. So we can continue. */
1877 if (silent == FALSE)
1878 kprintf("Acking %s to clear perror\n",
1879 ahd_lookup_phase_entry(curphase)->phasemsg);
1880 ahd_inb(ahd, SCSIDAT);
1881 }
1882
1883 if (curphase == P_MESGIN)
1884 msg_out = MSG_PARITY_ERROR;
1885 }
1886
1887 /*
1888 * We've set the hardware to assert ATN if we
1889 * get a parity error on "in" phases, so all we
1890 * need to do is stuff the message buffer with
1891 * the appropriate message. "In" phases have set
1892 * mesg_out to something other than MSG_NOP.
1893 */
1894 ahd->send_msg_perror = msg_out;
1895 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1896 scb->flags |= SCB_TRANSMISSION_ERROR;
1897 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1898 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1899 ahd_unpause(ahd);
1900 }
1901
1902 static void
1903 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1904 {
1905 /*
1906 * Clear the sources of the interrupts.
1907 */
1908 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1909 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1910
1911 /*
1912 * If the "illegal" phase changes were in response
1913 * to our ATN to flag a CRC error, AND we ended up
1914 * on packet boundaries, clear the error, restart the
1915 * LQI manager as appropriate, and go on our merry
1916 * way toward sending the message. Otherwise, reset
1917 * the bus to clear the error.
1918 */
1919 ahd_set_active_fifo(ahd);
1920 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1921 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
1922 if ((lqistat1 & LQIPHASE_LQ) != 0) {
1923 kprintf("LQIRETRY for LQIPHASE_LQ\n");
1924 ahd_outb(ahd, LQCTL2, LQIRETRY);
1925 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
1926 kprintf("LQIRETRY for LQIPHASE_NLQ\n");
1927 ahd_outb(ahd, LQCTL2, LQIRETRY);
1928 } else
1929 panic("ahd_handle_lqiphase_error: No phase errors\n");
1930 ahd_dump_card_state(ahd);
1931 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1932 ahd_unpause(ahd);
1933 } else {
1934 kprintf("Reseting Channel for LQI Phase error\n");
1935 ahd_dump_card_state(ahd);
1936 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1937 }
1938 }
1939
1940 /*
1941 * Packetized unexpected or expected busfree.
1942 * Entered in mode based on busfreetime.
1943 */
1944 static int
1945 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
1946 {
1947 u_int lqostat1;
1948
1949 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
1950 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
1951 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1952 if ((lqostat1 & LQOBUSFREE) != 0) {
1953 struct scb *scb;
1954 u_int scbid;
1955 u_int saved_scbptr;
1956 u_int waiting_h;
1957 u_int waiting_t;
1958 u_int next;
1959
1960 if ((busfreetime & BUSFREE_LQO) == 0)
1961 kprintf("%s: Warning, BUSFREE time is 0x%x. "
1962 "Expected BUSFREE_LQO.\n",
1963 ahd_name(ahd), busfreetime);
1964 /*
1965 * The LQO manager detected an unexpected busfree
1966 * either:
1967 *
1968 * 1) During an outgoing LQ.
1969 * 2) After an outgoing LQ but before the first
1970 * REQ of the command packet.
1971 * 3) During an outgoing command packet.
1972 *
1973 * In all cases, CURRSCB is pointing to the
1974 * SCB that encountered the failure. Clean
1975 * up the queue, clear SELDO and LQOBUSFREE,
1976 * and allow the sequencer to restart the select
1977 * out at its lesure.
1978 */
1979 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1980 scbid = ahd_inw(ahd, CURRSCB);
1981 scb = ahd_lookup_scb(ahd, scbid);
1982 if (scb == NULL)
1983 panic("SCB not valid during LQOBUSFREE");
1984 /*
1985 * Clear the status.
1986 */
1987 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
1988 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1989 ahd_outb(ahd, CLRLQOINT1, 0);
1990 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1991 ahd_flush_device_writes(ahd);
1992 ahd_outb(ahd, CLRSINT0, CLRSELDO);
1993
1994 /*
1995 * Return the LQO manager to its idle loop. It will
1996 * not do this automatically if the busfree occurs
1997 * after the first REQ of either the LQ or command
1998 * packet or between the LQ and command packet.
1999 */
2000 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2001
2002 /*
2003 * Update the waiting for selection queue so
2004 * we restart on the correct SCB.
2005 */
2006 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2007 saved_scbptr = ahd_get_scbptr(ahd);
2008 if (waiting_h != scbid) {
2009
2010 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2011 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2012 if (waiting_t == waiting_h) {
2013 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2014 next = SCB_LIST_NULL;
2015 } else {
2016 ahd_set_scbptr(ahd, waiting_h);
2017 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2018 }
2019 ahd_set_scbptr(ahd, scbid);
2020 ahd_outw(ahd, SCB_NEXT2, next);
2021 }
2022 ahd_set_scbptr(ahd, saved_scbptr);
2023 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2024 if (SCB_IS_SILENT(scb) == FALSE) {
2025 ahd_print_path(ahd, scb);
2026 kprintf("Probable outgoing LQ CRC error. "
2027 "Retrying command\n");
2028 }
2029 scb->crc_retry_count++;
2030 } else {
2031 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY);
2032 ahd_freeze_scb(scb);
2033 ahd_freeze_devq(ahd, scb);
2034 }
2035 /* Return unpausing the sequencer. */
2036 return (0);
2037 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2038 /*
2039 * Ignore what are really parity errors that
2040 * occur on the last REQ of a free running
2041 * clock prior to going busfree. Some drives
2042 * do not properly active negate just before
2043 * going busfree resulting in a parity glitch.
2044 */
2045 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2046 #ifdef AHD_DEBUG
2047 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2048 kprintf("%s: Parity on last REQ detected "
2049 "during busfree phase.\n",
2050 ahd_name(ahd));
2051 #endif
2052 /* Return unpausing the sequencer. */
2053 return (0);
2054 }
2055 if (ahd->src_mode != AHD_MODE_SCSI) {
2056 u_int scbid;
2057 struct scb *scb;
2058
2059 scbid = ahd_get_scbptr(ahd);
2060 scb = ahd_lookup_scb(ahd, scbid);
2061 ahd_print_path(ahd, scb);
2062 kprintf("Unexpected PKT busfree condition\n");
2063 ahd_dump_card_state(ahd);
2064 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2065 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2066 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2067
2068 /* Return restarting the sequencer. */
2069 return (1);
2070 }
2071 kprintf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2072 ahd_dump_card_state(ahd);
2073 /* Restart the sequencer. */
2074 return (1);
2075 }
2076
2077 /*
2078 * Non-packetized unexpected or expected busfree.
2079 */
2080 static int
2081 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2082 {
2083 struct ahd_devinfo devinfo;
2084 struct scb *scb;
2085 u_int lastphase;
2086 u_int saved_scsiid;
2087 u_int saved_lun;
2088 u_int target;
2089 u_int initiator_role_id;
2090 u_int scbid;
2091 u_int ppr_busfree;
2092 int printerror;
2093
2094 /*
2095 * Look at what phase we were last in. If its message out,
2096 * chances are pretty good that the busfree was in response
2097 * to one of our abort requests.
2098 */
2099 lastphase = ahd_inb(ahd, LASTPHASE);
2100 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2101 saved_lun = ahd_inb(ahd, SAVED_LUN);
2102 target = SCSIID_TARGET(ahd, saved_scsiid);
2103 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2104 ahd_compile_devinfo(&devinfo, initiator_role_id,
2105 target, saved_lun, 'A', ROLE_INITIATOR);
2106 printerror = 1;
2107
2108 scbid = ahd_get_scbptr(ahd);
2109 scb = ahd_lookup_scb(ahd, scbid);
2110 if (scb != NULL
2111 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2112 scb = NULL;
2113
2114 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2115 if (lastphase == P_MESGOUT) {
2116 u_int tag;
2117
2118 tag = SCB_LIST_NULL;
2119 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2120 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2121 int found;
2122 int sent_msg;
2123
2124 if (scb == NULL) {
2125 ahd_print_devinfo(ahd, &devinfo);
2126 kprintf("Abort for unidentified "
2127 "connection completed.\n");
2128 /* restart the sequencer. */
2129 return (1);
2130 }
2131 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2132 ahd_print_path(ahd, scb);
2133 kprintf("SCB %d - Abort%s Completed.\n",
2134 SCB_GET_TAG(scb),
2135 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2136
2137 if (sent_msg == MSG_ABORT_TAG)
2138 tag = SCB_GET_TAG(scb);
2139
2140 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2141 /*
2142 * This abort is in response to an
2143 * unexpected switch to command phase
2144 * for a packetized connection. Since
2145 * the identify message was never sent,
2146 * "saved lun" is 0. We really want to
2147 * abort only the SCB that encountered
2148 * this error, which could have a different
2149 * lun. The SCB will be retried so the OS
2150 * will see the UA after renegotiating to
2151 * packetized.
2152 */
2153 tag = SCB_GET_TAG(scb);
2154 saved_lun = scb->hscb->lun;
2155 }
2156 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2157 tag, ROLE_INITIATOR,
2158 CAM_REQ_ABORTED);
2159 kprintf("found == 0x%x\n", found);
2160 printerror = 0;
2161 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2162 MSG_BUS_DEV_RESET, TRUE)) {
2163 #if defined(__DragonFly__) || defined(__FreeBSD__)
2164 /*
2165 * Don't mark the user's request for this BDR
2166 * as completing with CAM_BDR_SENT. CAM3
2167 * specifies CAM_REQ_CMP.
2168 */
2169 if (scb != NULL
2170 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2171 && ahd_match_scb(ahd, scb, target, 'A',
2172 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2173 ROLE_INITIATOR))
2174 ahd_set_transaction_status(scb, CAM_REQ_CMP);
2175 #endif
2176 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2177 CAM_BDR_SENT, "Bus Device Reset",
2178 /*verbose_level*/0);
2179 printerror = 0;
2180 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2181 && ppr_busfree == 0) {
2182 struct ahd_initiator_tinfo *tinfo;
2183 struct ahd_tmode_tstate *tstate;
2184
2185 /*
2186 * PPR Rejected. Try non-ppr negotiation
2187 * and retry command.
2188 */
2189 #ifdef AHD_DEBUG
2190 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2191 kprintf("PPR negotiation rejected busfree.\n");
2192 #endif
2193 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2194 devinfo.our_scsiid,
2195 devinfo.target, &tstate);
2196 tinfo->curr.transport_version = 2;
2197 tinfo->goal.transport_version = 2;
2198 tinfo->goal.ppr_options = 0;
2199 ahd_qinfifo_requeue_tail(ahd, scb);
2200 printerror = 0;
2201 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2202 && ppr_busfree == 0) {
2203 /*
2204 * Negotiation Rejected. Go-narrow and
2205 * retry command.
2206 */
2207 #ifdef AHD_DEBUG
2208 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2209 kprintf("WDTR negotiation rejected busfree.\n");
2210 #endif
2211 ahd_set_width(ahd, &devinfo,
2212 MSG_EXT_WDTR_BUS_8_BIT,
2213 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2214 /*paused*/TRUE);
2215 ahd_qinfifo_requeue_tail(ahd, scb);
2216 printerror = 0;
2217 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2218 && ppr_busfree == 0) {
2219 /*
2220 * Negotiation Rejected. Go-async and
2221 * retry command.
2222 */
2223 #ifdef AHD_DEBUG
2224 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2225 kprintf("SDTR negotiation rejected busfree.\n");
2226 #endif
2227 ahd_set_syncrate(ahd, &devinfo,
2228 /*period*/0, /*offset*/0,
2229 /*ppr_options*/0,
2230 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2231 /*paused*/TRUE);
2232 ahd_qinfifo_requeue_tail(ahd, scb);
2233 printerror = 0;
2234 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2235 && ahd_sent_msg(ahd, AHDMSG_1B,
2236 MSG_INITIATOR_DET_ERR, TRUE)) {
2237
2238 #ifdef AHD_DEBUG
2239 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2240 kprintf("Expected IDE Busfree\n");
2241 #endif
2242 printerror = 0;
2243 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2244 && ahd_sent_msg(ahd, AHDMSG_1B,
2245 MSG_MESSAGE_REJECT, TRUE)) {
2246
2247 #ifdef AHD_DEBUG
2248 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2249 kprintf("Expected QAS Reject Busfree\n");
2250 #endif
2251 printerror = 0;
2252 }
2253 }
2254
2255 /*
2256 * The busfree required flag is honored at the end of
2257 * the message phases. We check it last in case we
2258 * had to send some other message that caused a busfree.
2259 */
2260 if (printerror != 0
2261 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2262 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2263
2264 ahd_freeze_devq(ahd, scb);
2265 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
2266 ahd_freeze_scb(scb);
2267 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2268 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2269 SCB_GET_CHANNEL(ahd, scb),
2270 SCB_GET_LUN(scb), SCB_LIST_NULL,
2271 ROLE_INITIATOR, CAM_REQ_ABORTED);
2272 } else {
2273 #ifdef AHD_DEBUG
2274 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2275 kprintf("PPR Negotiation Busfree.\n");
2276 #endif
2277 ahd_done(ahd, scb);
2278 }
2279 printerror = 0;
2280 }
2281 if (printerror != 0) {
2282 int aborted;
2283
2284 aborted = 0;
2285 if (scb != NULL) {
2286 u_int tag;
2287
2288 if ((scb->hscb->control & TAG_ENB) != 0)
2289 tag = SCB_GET_TAG(scb);
2290 else
2291 tag = SCB_LIST_NULL;
2292 ahd_print_path(ahd, scb);
2293 aborted = ahd_abort_scbs(ahd, target, 'A',
2294 SCB_GET_LUN(scb), tag,
2295 ROLE_INITIATOR,
2296 CAM_UNEXP_BUSFREE);
2297 } else {
2298 /*
2299 * We had not fully identified this connection,
2300 * so we cannot abort anything.
2301 */
2302 kprintf("%s: ", ahd_name(ahd));
2303 }
2304 if (lastphase != P_BUSFREE)
2305 ahd_force_renegotiation(ahd, &devinfo);
2306 kprintf("Unexpected busfree %s, %d SCBs aborted, "
2307 "PRGMCNT == 0x%x\n",
2308 ahd_lookup_phase_entry(lastphase)->phasemsg,
2309 aborted,
2310 ahd_inb(ahd, PRGMCNT)
2311 | (ahd_inb(ahd, PRGMCNT+1) << 8));
2312 ahd_dump_card_state(ahd);
2313 }
2314 /* Always restart the sequencer. */
2315 return (1);
2316 }
2317
2318 static void
2319 ahd_handle_proto_violation(struct ahd_softc *ahd)
2320 {
2321 struct ahd_devinfo devinfo;
2322 struct scb *scb;
2323 u_int scbid;
2324 u_int seq_flags;
2325 u_int curphase;
2326 u_int lastphase;
2327 int found;
2328
2329 ahd_fetch_devinfo(ahd, &devinfo);
2330 scbid = ahd_get_scbptr(ahd);
2331 scb = ahd_lookup_scb(ahd, scbid);
2332 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2333 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2334 lastphase = ahd_inb(ahd, LASTPHASE);
2335 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2336
2337 /*
2338 * The reconnecting target either did not send an
2339 * identify message, or did, but we didn't find an SCB
2340 * to match.
2341 */
2342 ahd_print_devinfo(ahd, &devinfo);
2343 kprintf("Target did not send an IDENTIFY message. "
2344 "LASTPHASE = 0x%x.\n", lastphase);
2345 scb = NULL;
2346 } else if (scb == NULL) {
2347 /*
2348 * We don't seem to have an SCB active for this
2349 * transaction. Print an error and reset the bus.
2350 */
2351 ahd_print_devinfo(ahd, &devinfo);
2352 kprintf("No SCB found during protocol violation\n");
2353 goto proto_violation_reset;
2354 } else {
2355 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2356 if ((seq_flags & NO_CDB_SENT) != 0) {
2357 ahd_print_path(ahd, scb);
2358 kprintf("No or incomplete CDB sent to device.\n");
2359 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2360 & STATUS_RCVD) == 0) {
2361 /*
2362 * The target never bothered to provide status to
2363 * us prior to completing the command. Since we don't
2364 * know the disposition of this command, we must attempt
2365 * to abort it. Assert ATN and prepare to send an abort
2366 * message.
2367 */
2368 ahd_print_path(ahd, scb);
2369 kprintf("Completed command without status.\n");
2370 } else {
2371 ahd_print_path(ahd, scb);
2372 kprintf("Unknown protocol violation.\n");
2373 ahd_dump_card_state(ahd);
2374 }
2375 }
2376 if ((lastphase & ~P_DATAIN_DT) == 0
2377 || lastphase == P_COMMAND) {
2378 proto_violation_reset:
2379 /*
2380 * Target either went directly to data
2381 * phase or didn't respond to our ATN.
2382 * The only safe thing to do is to blow
2383 * it away with a bus reset.
2384 */
2385 found = ahd_reset_channel(ahd, 'A', TRUE);
2386 kprintf("%s: Issued Channel %c Bus Reset. "
2387 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2388 } else {
2389 /*
2390 * Leave the selection hardware off in case
2391 * this abort attempt will affect yet to
2392 * be sent commands.
2393 */
2394 ahd_outb(ahd, SCSISEQ0,
2395 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2396 ahd_assert_atn(ahd);
2397 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2398 if (scb == NULL) {
2399 ahd_print_devinfo(ahd, &devinfo);
2400 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2401 ahd->msgout_len = 1;
2402 ahd->msgout_index = 0;
2403 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2404 } else {
2405 ahd_print_path(ahd, scb);
2406 scb->flags |= SCB_ABORT;
2407 }
2408 kprintf("Protocol violation %s. Attempting to abort.\n",
2409 ahd_lookup_phase_entry(curphase)->phasemsg);
2410 }
2411 }
2412
2413 /*
2414 * Force renegotiation to occur the next time we initiate
2415 * a command to the current device.
2416 */
2417 static void
2418 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2419 {
2420 struct ahd_initiator_tinfo *targ_info;
2421 struct ahd_tmode_tstate *tstate;
2422
2423 #ifdef AHD_DEBUG
2424 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2425 ahd_print_devinfo(ahd, devinfo);
2426 kprintf("Forcing renegotiation\n");
2427 }
2428 #endif
2429 targ_info = ahd_fetch_transinfo(ahd,
2430 devinfo->channel,
2431 devinfo->our_scsiid,
2432 devinfo->target,
2433 &tstate);
2434 ahd_update_neg_request(ahd, devinfo, tstate,
2435 targ_info, AHD_NEG_IF_NON_ASYNC);
2436 }
2437
2438 #define AHD_MAX_STEPS 2000
2439 void
2440 ahd_clear_critical_section(struct ahd_softc *ahd)
2441 {
2442 ahd_mode_state saved_modes;
2443 int stepping;
2444 int steps;
2445 int first_instr;
2446 u_int simode0;
2447 u_int simode1;
2448 u_int simode3;
2449 u_int lqimode0;
2450 u_int lqimode1;
2451 u_int lqomode0;
2452 u_int lqomode1;
2453
2454 if (ahd->num_critical_sections == 0)
2455 return;
2456
2457 stepping = FALSE;
2458 steps = 0;
2459 first_instr = 0;
2460 simode0 = 0;
2461 simode1 = 0;
2462 simode3 = 0;
2463 lqimode0 = 0;
2464 lqimode1 = 0;
2465 lqomode0 = 0;
2466 lqomode1 = 0;
2467 saved_modes = ahd_save_modes(ahd);
2468 for (;;) {
2469 struct cs *cs;
2470 u_int seqaddr;
2471 u_int i;
2472
2473 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2474 seqaddr = ahd_inb(ahd, CURADDR)
2475 | (ahd_inb(ahd, CURADDR+1) << 8);
2476
2477 cs = ahd->critical_sections;
2478 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2479
2480 if (cs->begin < seqaddr && cs->end >= seqaddr)
2481 break;
2482 }
2483
2484 if (i == ahd->num_critical_sections)
2485 break;
2486
2487 if (steps > AHD_MAX_STEPS) {
2488 kprintf("%s: Infinite loop in critical section\n"
2489 "%s: First Instruction 0x%x now 0x%x\n",
2490 ahd_name(ahd), ahd_name(ahd), first_instr,
2491 seqaddr);
2492 ahd_dump_card_state(ahd);
2493 panic("critical section loop");
2494 }
2495
2496 steps++;
2497 #ifdef AHD_DEBUG
2498 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2499 kprintf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2500 seqaddr);
2501 #endif
2502 if (stepping == FALSE) {
2503
2504 first_instr = seqaddr;
2505 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2506 simode0 = ahd_inb(ahd, SIMODE0);
2507 simode3 = ahd_inb(ahd, SIMODE3);
2508 lqimode0 = ahd_inb(ahd, LQIMODE0);
2509 lqimode1 = ahd_inb(ahd, LQIMODE1);
2510 lqomode0 = ahd_inb(ahd, LQOMODE0);
2511 lqomode1 = ahd_inb(ahd, LQOMODE1);
2512 ahd_outb(ahd, SIMODE0, 0);
2513 ahd_outb(ahd, SIMODE3, 0);
2514 ahd_outb(ahd, LQIMODE0, 0);
2515 ahd_outb(ahd, LQIMODE1, 0);
2516 ahd_outb(ahd, LQOMODE0, 0);
2517 ahd_outb(ahd, LQOMODE1, 0);
2518 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2519 simode1 = ahd_inb(ahd, SIMODE1);
2520 /*
2521 * We don't clear ENBUSFREE. Unfortunately
2522 * we cannot re-enable busfree detection within
2523 * the current connection, so we must leave it
2524 * on while single stepping.
2525 */
2526 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2527 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2528 stepping = TRUE;
2529 }
2530 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2531 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2532 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2533 ahd_outb(ahd, HCNTRL, ahd->unpause);
2534 while (!ahd_is_paused(ahd))
2535 ahd_delay(200);
2536 ahd_update_modes(ahd);
2537 }
2538 if (stepping) {
2539 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2540 ahd_outb(ahd, SIMODE0, simode0);
2541 ahd_outb(ahd, SIMODE3, simode3);
2542 ahd_outb(ahd, LQIMODE0, lqimode0);
2543 ahd_outb(ahd, LQIMODE1, lqimode1);
2544 ahd_outb(ahd, LQOMODE0, lqomode0);
2545 ahd_outb(ahd, LQOMODE1, lqomode1);
2546 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2547 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2548 ahd_outb(ahd, SIMODE1, simode1);
2549 /*
2550 * SCSIINT seems to glitch occassionally when
2551 * the interrupt masks are restored. Clear SCSIINT
2552 * one more time so that only persistent errors
2553 * are seen as a real interrupt.
2554 */
2555 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2556 }
2557 ahd_restore_modes(ahd, saved_modes);
2558 }
2559
2560 /*
2561 * Clear any pending interrupt status.
2562 */
2563 void
2564 ahd_clear_intstat(struct ahd_softc *ahd)
2565 {
2566 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2567 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2568 /* Clear any interrupt conditions this may have caused */
2569 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2570 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2571 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2572 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2573 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2574 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2575 |CLRLQOATNPKT|CLRLQOTCRC);
2576 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2577 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2578 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2579 ahd_outb(ahd, CLRLQOINT0, 0);
2580 ahd_outb(ahd, CLRLQOINT1, 0);
2581 }
2582 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2583 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2584 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2585 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2586 |CLRIOERR|CLROVERRUN);
2587 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2588 }
2589
2590 /**************************** Debugging Routines ******************************/
2591 #ifdef AHD_DEBUG
2592 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2593 #endif
2594 void
2595 ahd_print_scb(struct scb *scb)
2596 {
2597 struct hardware_scb *hscb;
2598 int i;
2599
2600 hscb = scb->hscb;
2601 kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2602 (void *)scb,
2603 hscb->control,
2604 hscb->scsiid,
2605 hscb->lun,
2606 hscb->cdb_len);
2607 kprintf("Shared Data: ");
2608 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2609 kprintf("%#02x", hscb->shared_data.idata.cdb[i]);
2610 kprintf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2611 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2612 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2613 ahd_le32toh(hscb->datacnt),
2614 ahd_le32toh(hscb->sgptr),
2615 SCB_GET_TAG(scb));
2616 ahd_dump_sglist(scb);
2617 }
2618
2619 void
2620 ahd_dump_sglist(struct scb *scb)
2621 {
2622 int i;
2623
2624 if (scb->sg_count > 0) {
2625 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2626 struct ahd_dma64_seg *sg_list;
2627
2628 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2629 for (i = 0; i < scb->sg_count; i++) {
2630 uint64_t addr;
2631 uint32_t len;
2632
2633 addr = ahd_le64toh(sg_list[i].addr);
2634 len = ahd_le32toh(sg_list[i].len);
2635 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2636 i,
2637 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2638 (uint32_t)(addr & 0xFFFFFFFF),
2639 sg_list[i].len & AHD_SG_LEN_MASK,
2640 (sg_list[i].len & AHD_DMA_LAST_SEG)
2641 ? " Last" : "");
2642 }
2643 } else {
2644 struct ahd_dma_seg *sg_list;
2645
2646 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2647 for (i = 0; i < scb->sg_count; i++) {
2648 uint32_t len;
2649
2650 len = ahd_le32toh(sg_list[i].len);
2651 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2652 i,
2653 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2654 ahd_le32toh(sg_list[i].addr),
2655 len & AHD_SG_LEN_MASK,
2656 len & AHD_DMA_LAST_SEG ? " Last" : "");
2657 }
2658 }
2659 }
2660 }
2661
2662 /************************* Transfer Negotiation *******************************/
2663 /*
2664 * Allocate per target mode instance (ID we respond to as a target)
2665 * transfer negotiation data structures.
2666 */
2667 static struct ahd_tmode_tstate *
2668 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2669 {
2670 struct ahd_tmode_tstate *master_tstate;
2671 struct ahd_tmode_tstate *tstate;
2672 int i;
2673
2674 master_tstate = ahd->enabled_targets[ahd->our_id];
2675 if (ahd->enabled_targets[scsi_id] != NULL
2676 && ahd->enabled_targets[scsi_id] != master_tstate)
2677 panic("%s: ahd_alloc_tstate - Target already allocated",
2678 ahd_name(ahd));
2679 tstate = kmalloc(sizeof(*tstate), M_DEVBUF, M_INTWAIT);
2680
2681 /*
2682 * If we have allocated a master tstate, copy user settings from
2683 * the master tstate (taken from SRAM or the EEPROM) for this
2684 * channel, but reset our current and goal settings to async/narrow
2685 * until an initiator talks to us.
2686 */
2687 if (master_tstate != NULL) {
2688 memcpy(tstate, master_tstate, sizeof(*tstate));
2689 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2690 for (i = 0; i < 16; i++) {
2691 memset(&tstate->transinfo[i].curr, 0,
2692 sizeof(tstate->transinfo[i].curr));
2693 memset(&tstate->transinfo[i].goal, 0,
2694 sizeof(tstate->transinfo[i].goal));
2695 }
2696 } else
2697 memset(tstate, 0, sizeof(*tstate));
2698 ahd->enabled_targets[scsi_id] = tstate;
2699 return (tstate);
2700 }
2701
2702 #ifdef AHD_TARGET_MODE
2703 /*
2704 * Free per target mode instance (ID we respond to as a target)
2705 * transfer negotiation data structures.
2706 */
2707 static void
2708 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2709 {
2710 struct ahd_tmode_tstate *tstate;
2711
2712 /*
2713 * Don't clean up our "master" tstate.
2714 * It has our default user settings.
2715 */
2716 if (scsi_id == ahd->our_id
2717 && force == FALSE)
2718 return;
2719
2720 tstate = ahd->enabled_targets[scsi_id];
2721 if (tstate != NULL)
2722 kfree(tstate, M_DEVBUF);
2723 ahd->enabled_targets[scsi_id] = NULL;
2724 }
2725 #endif
2726
2727 /*
2728 * Called when we have an active connection to a target on the bus,
2729 * this function finds the nearest period to the input period limited
2730 * by the capabilities of the bus connectivity of and sync settings for
2731 * the target.
2732 */
2733 void
2734 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2735 struct ahd_initiator_tinfo *tinfo,
2736 u_int *period, u_int *ppr_options, role_t role)
2737 {
2738 struct ahd_transinfo *transinfo;
2739 u_int maxsync;
2740
2741 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2742 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2743 maxsync = AHD_SYNCRATE_PACED;
2744 } else {
2745 maxsync = AHD_SYNCRATE_ULTRA;
2746 /* Can't do DT related options on an SE bus */
2747 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2748 }
2749 /*
2750 * Never allow a value higher than our current goal
2751 * period otherwise we may allow a target initiated
2752 * negotiation to go above the limit as set by the
2753 * user. In the case of an initiator initiated
2754 * sync negotiation, we limit based on the user
2755 * setting. This allows the system to still accept
2756 * incoming negotiations even if target initiated
2757 * negotiation is not performed.
2758 */
2759 if (role == ROLE_TARGET)
2760 transinfo = &tinfo->user;
2761 else
2762 transinfo = &tinfo->goal;
2763 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2764 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2765 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2766 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2767 }
2768 if (transinfo->period == 0) {
2769 *period = 0;
2770 *ppr_options = 0;
2771 } else {
2772 *period = MAX(*period, transinfo->period);
2773 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2774 }
2775 }
2776
2777 /*
2778 * Look up the valid period to SCSIRATE conversion in our table.
2779 * Return the period and offset that should be sent to the target
2780 * if this was the beginning of an SDTR.
2781 */
2782 void
2783 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2784 u_int *ppr_options, u_int maxsync)
2785 {
2786 if (*period < maxsync)
2787 *period = maxsync;
2788
2789 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2790 && *period > AHD_SYNCRATE_MIN_DT)
2791 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2792
2793 if (*period > AHD_SYNCRATE_MIN)
2794 *period = 0;
2795
2796 /* Honor PPR option conformance rules. */
2797 if (*period > AHD_SYNCRATE_PACED)
2798 *ppr_options &= ~MSG_EXT_PPR_RTI;
2799
2800 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2801 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2802
2803 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2804 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2805
2806 /* Skip all PACED only entries if IU is not available */
2807 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2808 && *period < AHD_SYNCRATE_DT)
2809 *period = AHD_SYNCRATE_DT;
2810
2811 /* Skip all DT only entries if DT is not available */
2812 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2813 && *period < AHD_SYNCRATE_ULTRA2)
2814 *period = AHD_SYNCRATE_ULTRA2;
2815 }
2816
2817 /*
2818 * Truncate the given synchronous offset to a value the
2819 * current adapter type and syncrate are capable of.
2820 */
2821 void
2822 ahd_validate_offset(struct ahd_softc *ahd,
2823 struct ahd_initiator_tinfo *tinfo,
2824 u_int period, u_int *offset, int wide,
2825 role_t role)
2826 {
2827 u_int maxoffset;
2828
2829 /* Limit offset to what we can do */
2830 if (period == 0)
2831 maxoffset = 0;
2832 else if (period <= AHD_SYNCRATE_PACED) {
2833 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2834 maxoffset = MAX_OFFSET_PACED_BUG;
2835 else
2836 maxoffset = MAX_OFFSET_PACED;
2837 } else
2838 maxoffset = MAX_OFFSET_NON_PACED;
2839 *offset = MIN(*offset, maxoffset);
2840 if (tinfo != NULL) {
2841 if (role == ROLE_TARGET)
2842 *offset = MIN(*offset, tinfo->user.offset);
2843 else
2844 *offset = MIN(*offset, tinfo->goal.offset);
2845 }
2846 }
2847
2848 /*
2849 * Truncate the given transfer width parameter to a value the
2850 * current adapter type is capable of.
2851 */
2852 void
2853 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2854 u_int *bus_width, role_t role)
2855 {
2856 switch (*bus_width) {
2857 default:
2858 if (ahd->features & AHD_WIDE) {
2859 /* Respond Wide */
2860 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2861 break;
2862 }
2863 /* FALLTHROUGH */
2864 case MSG_EXT_WDTR_BUS_8_BIT:
2865 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2866 break;
2867 }
2868 if (tinfo != NULL) {
2869 if (role == ROLE_TARGET)
2870 *bus_width = MIN(tinfo->user.width, *bus_width);
2871 else
2872 *bus_width = MIN(tinfo->goal.width, *bus_width);
2873 }
2874 }
2875
2876 /*
2877 * Update the bitmask of targets for which the controller should
2878 * negotiate with at the next convenient oportunity. This currently
2879 * means the next time we send the initial identify messages for
2880 * a new transaction.
2881 */
2882 int
2883 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2884 struct ahd_tmode_tstate *tstate,
2885 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
2886 {
2887 u_int auto_negotiate_orig;
2888
2889 auto_negotiate_orig = tstate->auto_negotiate;
2890 if (neg_type == AHD_NEG_ALWAYS) {
2891 /*
2892 * Force our "current" settings to be
2893 * unknown so that unless a bus reset
2894 * occurs the need to renegotiate is
2895 * recorded persistently.
2896 */
2897 if ((ahd->features & AHD_WIDE) != 0)
2898 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
2899 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
2900 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
2901 }
2902 if (tinfo->curr.period != tinfo->goal.period
2903 || tinfo->curr.width != tinfo->goal.width
2904 || tinfo->curr.offset != tinfo->goal.offset
2905 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2906 || (neg_type == AHD_NEG_IF_NON_ASYNC
2907 && (tinfo->goal.offset != 0
2908 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2909 || tinfo->goal.ppr_options != 0)))
2910 tstate->auto_negotiate |= devinfo->target_mask;
2911 else
2912 tstate->auto_negotiate &= ~devinfo->target_mask;
2913
2914 return (auto_negotiate_orig != tstate->auto_negotiate);
2915 }
2916
2917 /*
2918 * Update the user/goal/curr tables of synchronous negotiation
2919 * parameters as well as, in the case of a current or active update,
2920 * any data structures on the host controller. In the case of an
2921 * active update, the specified target is currently talking to us on
2922 * the bus, so the transfer parameter update must take effect
2923 * immediately.
2924 */
2925 void
2926 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2927 u_int period, u_int offset, u_int ppr_options,
2928 u_int type, int paused)
2929 {
2930 struct ahd_initiator_tinfo *tinfo;
2931 struct ahd_tmode_tstate *tstate;
2932 u_int old_period;
2933 u_int old_offset;
2934 u_int old_ppr;
2935 int active;
2936 int update_needed;
2937
2938 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
2939 update_needed = 0;
2940
2941 if (period == 0 || offset == 0) {
2942 period = 0;
2943 offset = 0;
2944 }
2945
2946 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
2947 devinfo->target, &tstate);
2948
2949 if ((type & AHD_TRANS_USER) != 0) {
2950 tinfo->user.period = period;
2951 tinfo->user.offset = offset;
2952 tinfo->user.ppr_options = ppr_options;
2953 }
2954
2955 if ((type & AHD_TRANS_GOAL) != 0) {
2956 tinfo->goal.period = period;
2957 tinfo->goal.offset = offset;
2958 tinfo->goal.ppr_options = ppr_options;
2959 }
2960
2961 old_period = tinfo->curr.period;
2962 old_offset = tinfo->curr.offset;
2963 old_ppr = tinfo->curr.ppr_options;
2964
2965 if ((type & AHD_TRANS_CUR) != 0
2966 && (old_period != period
2967 || old_offset != offset
2968 || old_ppr != ppr_options)) {
2969
2970 update_needed++;
2971
2972 tinfo->curr.period = period;
2973 tinfo->curr.offset = offset;
2974 tinfo->curr.ppr_options = ppr_options;
2975
2976 ahd_send_async(ahd, devinfo->channel, devinfo->target,
2977 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2978 if (bootverbose) {
2979 if (offset != 0) {
2980 int options;
2981
2982 kprintf("%s: target %d synchronous with "
2983 "period = 0x%x, offset = 0x%x",
2984 ahd_name(ahd), devinfo->target,
2985 period, offset);
2986 options = 0;
2987 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
2988 kprintf("(RDSTRM");
2989 options++;
2990 }
2991 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
2992 kprintf("%s", options ? "|DT" : "(DT");
2993 options++;
2994 }
2995 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
2996 kprintf("%s", options ? "|IU" : "(IU");
2997 options++;
2998 }
2999 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3000 kprintf("%s", options ? "|RTI" : "(RTI");
3001 options++;
3002 }
3003 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3004 kprintf("%s", options ? "|QAS" : "(QAS");
3005 options++;
3006 }
3007 if (options != 0)
3008 kprintf(")\n");
3009 else
3010 kprintf("\n");
3011 } else {
3012 kprintf("%s: target %d using "
3013 "asynchronous transfers%s\n",
3014 ahd_name(ahd), devinfo->target,
3015 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3016 ? "(QAS)" : "");
3017 }
3018 }
3019 }
3020 /*
3021 * Always refresh the neg-table to handle the case of the
3022 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3023 * We will always renegotiate in that case if this is a
3024 * packetized request. Also manage the busfree expected flag
3025 * from this common routine so that we catch changes due to
3026 * WDTR or SDTR messages.
3027 */
3028 if ((type & AHD_TRANS_CUR) != 0) {
3029 if (!paused)
3030 ahd_pause(ahd);
3031 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3032 if (!paused)
3033 ahd_unpause(ahd);
3034 if (ahd->msg_type != MSG_TYPE_NONE) {
3035 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3036 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3037 #ifdef AHD_DEBUG
3038 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3039 ahd_print_devinfo(ahd, devinfo);
3040 kprintf("Expecting IU Change busfree\n");
3041 }
3042 #endif
3043 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3044 | MSG_FLAG_IU_REQ_CHANGED;
3045 }
3046 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3047 #ifdef AHD_DEBUG
3048 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3049 kprintf("PPR with IU_REQ outstanding\n");
3050 #endif
3051 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3052 }
3053 }
3054 }
3055
3056 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3057 tinfo, AHD_NEG_TO_GOAL);
3058
3059 if (update_needed && active)
3060 ahd_update_pending_scbs(ahd);
3061 }
3062
3063 /*
3064 * Update the user/goal/curr tables of wide negotiation
3065 * parameters as well as, in the case of a current or active update,
3066 * any data structures on the host controller. In the case of an
3067 * active update, the specified target is currently talking to us on
3068 * the bus, so the transfer parameter update must take effect
3069 * immediately.
3070 */
3071 void
3072 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3073 u_int width, u_int type, int paused)
3074 {
3075 struct ahd_initiator_tinfo *tinfo;
3076 struct ahd_tmode_tstate *tstate;
3077 u_int oldwidth;
3078 int active;
3079 int update_needed;
3080
3081 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3082 update_needed = 0;
3083 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3084 devinfo->target, &tstate);
3085
3086 if ((type & AHD_TRANS_USER) != 0)
3087 tinfo->user.width = width;
3088
3089 if ((type & AHD_TRANS_GOAL) != 0)
3090 tinfo->goal.width = width;
3091
3092 oldwidth = tinfo->curr.width;
3093 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3094
3095 update_needed++;
3096
3097 tinfo->curr.width = width;
3098 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3099 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3100 if (bootverbose) {
3101 kprintf("%s: target %d using %dbit transfers\n",
3102 ahd_name(ahd), devinfo->target,
3103 8 * (0x01 << width));
3104 }
3105 }
3106
3107 if ((type & AHD_TRANS_CUR) != 0) {
3108 if (!paused)
3109 ahd_pause(ahd);
3110 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3111 if (!paused)
3112 ahd_unpause(ahd);
3113 }
3114
3115 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3116 tinfo, AHD_NEG_TO_GOAL);
3117 if (update_needed && active)
3118 ahd_update_pending_scbs(ahd);
3119
3120 }
3121
3122 /*
3123 * Update the current state of tagged queuing for a given target.
3124 */
3125 void
3126 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3127 ahd_queue_alg alg)
3128 {
3129 ahd_platform_set_tags(ahd, devinfo, alg);
3130 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3131 devinfo->lun, AC_TRANSFER_NEG, &alg);
3132 }
3133
3134 static void
3135 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3136 struct ahd_transinfo *tinfo)
3137 {
3138 ahd_mode_state saved_modes;
3139 u_int period;
3140 u_int ppr_opts;
3141 u_int con_opts;
3142 u_int offset;
3143 u_int saved_negoaddr;
3144 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3145
3146 saved_modes = ahd_save_modes(ahd);
3147 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3148
3149 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3150 ahd_outb(ahd, NEGOADDR, devinfo->target);
3151 period = tinfo->period;
3152 offset = tinfo->offset;
3153 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3154 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3155 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3156 con_opts = 0;
3157 if (period == 0)
3158 period = AHD_SYNCRATE_ASYNC;
3159 if (period == AHD_SYNCRATE_160) {
3160
3161 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3162 /*
3163 * When the SPI4 spec was finalized, PACE transfers
3164 * was not made a configurable option in the PPR
3165 * message. Instead it is assumed to be enabled for
3166 * any syncrate faster than 80MHz. Nevertheless,
3167 * Harpoon2A4 allows this to be configurable.
3168 *
3169 * Harpoon2A4 also assumes at most 2 data bytes per
3170 * negotiated REQ/ACK offset. Paced transfers take
3171 * 4, so we must adjust our offset.
3172 */
3173 ppr_opts |= PPROPT_PACE;
3174 offset *= 2;
3175
3176 /*
3177 * Harpoon2A assumed that there would be a
3178 * fallback rate between 160MHz and 80Mhz,
3179 * so 7 is used as the period factor rather
3180 * than 8 for 160MHz.
3181 */
3182 period = AHD_SYNCRATE_REVA_160;
3183 }
3184 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3185 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3186 ~AHD_PRECOMP_MASK;
3187 } else {
3188 /*
3189 * Precomp should be disabled for non-paced transfers.
3190 */
3191 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3192
3193 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3194 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) {
3195 /*
3196 * Slow down our CRC interval to be
3197 * compatible with devices that can't
3198 * handle a CRC at full speed.
3199 */
3200 con_opts |= ENSLOWCRC;
3201 }
3202 }
3203
3204 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3205 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3206 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3207 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3208
3209 ahd_outb(ahd, NEGPERIOD, period);
3210 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3211 ahd_outb(ahd, NEGOFFSET, offset);
3212
3213 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3214 con_opts |= WIDEXFER;
3215
3216 /*
3217 * During packetized transfers, the target will
3218 * give us the oportunity to send command packets
3219 * without us asserting attention.
3220 */
3221 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3222 con_opts |= ENAUTOATNO;
3223 ahd_outb(ahd, NEGCONOPTS, con_opts);
3224 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3225 ahd_restore_modes(ahd, saved_modes);
3226 }
3227
3228 /*
3229 * When the transfer settings for a connection change, setup for
3230 * negotiation in pending SCBs to effect the change as quickly as
3231 * possible. We also cancel any negotiations that are scheduled
3232 * for inflight SCBs that have not been started yet.
3233 */
3234 static void
3235 ahd_update_pending_scbs(struct ahd_softc *ahd)
3236 {
3237 struct scb *pending_scb;
3238 int pending_scb_count;
3239 u_int scb_tag;
3240 int paused;
3241 u_int saved_scbptr;
3242 ahd_mode_state saved_modes;
3243
3244 /*
3245 * Traverse the pending SCB list and ensure that all of the
3246 * SCBs there have the proper settings. We can only safely
3247 * clear the negotiation required flag (setting requires the
3248 * execution queue to be modified) and this is only possible
3249 * if we are not already attempting to select out for this
3250 * SCB. For this reason, all callers only call this routine
3251 * if we are changing the negotiation settings for the currently
3252 * active transaction on the bus.
3253 */
3254 pending_scb_count = 0;
3255 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3256 struct ahd_devinfo devinfo;
3257 struct hardware_scb *pending_hscb;
3258 struct ahd_initiator_tinfo *tinfo;
3259 struct ahd_tmode_tstate *tstate;
3260
3261 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3262 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3263 devinfo.our_scsiid,
3264 devinfo.target, &tstate);
3265 pending_hscb = pending_scb->hscb;
3266 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3267 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3268 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3269 pending_hscb->control &= ~MK_MESSAGE;
3270 }
3271 ahd_sync_scb(ahd, pending_scb,
3272 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3273 pending_scb_count++;
3274 }
3275
3276 if (pending_scb_count == 0)
3277 return;
3278
3279 if (ahd_is_paused(ahd)) {
3280 paused = 1;
3281 } else {
3282 paused = 0;
3283 ahd_pause(ahd);
3284 }
3285
3286 /*
3287 * Force the sequencer to reinitialize the selection for
3288 * the command at the head of the execution queue if it
3289 * has already been setup. The negotiation changes may
3290 * effect whether we select-out with ATN.
3291 */
3292 saved_modes = ahd_save_modes(ahd);
3293 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3294 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3295 saved_scbptr = ahd_get_scbptr(ahd);
3296 /* Ensure that the hscbs down on the card match the new information */
3297 for (scb_tag = 0; scb_tag < ahd->scb_data.maxhscbs; scb_tag++) {
3298 struct hardware_scb *pending_hscb;
3299 u_int control;
3300
3301 pending_scb = ahd_lookup_scb(ahd, scb_tag);
3302 if (pending_scb == NULL)
3303 continue;
3304 ahd_set_scbptr(ahd, scb_tag);
3305 pending_hscb = pending_scb->hscb;
3306 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3307 control &= ~MK_MESSAGE;
3308 control |= pending_hscb->control & MK_MESSAGE;
3309 ahd_outb(ahd, SCB_CONTROL, control);
3310 }
3311 ahd_set_scbptr(ahd, saved_scbptr);
3312 ahd_restore_modes(ahd, saved_modes);
3313
3314 if (paused == 0)
3315 ahd_unpause(ahd);
3316 }
3317
3318 /**************************** Pathing Information *****************************/
3319 static void
3320 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3321 {
3322 ahd_mode_state saved_modes;
3323 u_int saved_scsiid;
3324 role_t role;
3325 int our_id;
3326
3327 saved_modes = ahd_save_modes(ahd);
3328 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3329
3330 if (ahd_inb(ahd, SSTAT0) & TARGET)
3331 role = ROLE_TARGET;
3332 else
3333 role = ROLE_INITIATOR;
3334
3335 if (role == ROLE_TARGET
3336 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3337 /* We were selected, so pull our id from TARGIDIN */
3338 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3339 } else if (role == ROLE_TARGET)
3340 our_id = ahd_inb(ahd, TOWNID);
3341 else
3342 our_id = ahd_inb(ahd, IOWNID);
3343
3344 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3345 ahd_compile_devinfo(devinfo,
3346 our_id,
3347 SCSIID_TARGET(ahd, saved_scsiid),
3348 ahd_inb(ahd, SAVED_LUN),
3349 SCSIID_CHANNEL(ahd, saved_scsiid),
3350 role);
3351 ahd_restore_modes(ahd, saved_modes);
3352 }
3353
3354 void
3355 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3356 {
3357 kprintf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3358 devinfo->target, devinfo->lun);
3359 }
3360
3361 struct ahd_phase_table_entry*
3362 ahd_lookup_phase_entry(int phase)
3363 {
3364 struct ahd_phase_table_entry *entry;
3365 struct ahd_phase_table_entry *last_entry;
3366
3367 /*
3368 * num_phases doesn't include the default entry which
3369 * will be returned if the phase doesn't match.
3370 */
3371 last_entry = &ahd_phase_table[num_phases];
3372 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3373 if (phase == entry->phase)
3374 break;
3375 }
3376 return (entry);
3377 }
3378
3379 void
3380 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3381 u_int lun, char channel, role_t role)
3382 {
3383 devinfo->our_scsiid = our_id;
3384 devinfo->target = target;
3385 devinfo->lun = lun;
3386 devinfo->target_offset = target;
3387 devinfo->channel = channel;
3388 devinfo->role = role;
3389 if (channel == 'B')
3390 devinfo->target_offset += 8;
3391 devinfo->target_mask = (0x01 << devinfo->target_offset);
3392 }
3393
3394 static void
3395 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3396 struct scb *scb)
3397 {
3398 role_t role;
3399 int our_id;
3400
3401 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3402 role = ROLE_INITIATOR;
3403 if ((scb->hscb->control & TARGET_SCB) != 0)
3404 role = ROLE_TARGET;
3405 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3406 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3407 }
3408
3409
3410 /************************ Message Phase Processing ****************************/
3411 /*
3412 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3413 * or enters the initial message out phase, we are interrupted. Fill our
3414 * outgoing message buffer with the appropriate message and beging handing
3415 * the message phase(s) manually.
3416 */
3417 static void
3418 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3419 struct scb *scb)
3420 {
3421 /*
3422 * To facilitate adding multiple messages together,
3423 * each routine should increment the index and len
3424 * variables instead of setting them explicitly.
3425 */
3426 ahd->msgout_index = 0;
3427 ahd->msgout_len = 0;
3428
3429 if (ahd_currently_packetized(ahd))
3430 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3431
3432 if (ahd->send_msg_perror
3433 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3434 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3435 ahd->msgout_len++;
3436 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3437 #ifdef AHD_DEBUG
3438 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3439 kprintf("Setting up for Parity Error delivery\n");
3440 #endif
3441 return;
3442 } else if (scb == NULL) {
3443 kprintf("%s: WARNING. No pending message for "
3444 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3445 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3446 ahd->msgout_len++;
3447 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3448 return;
3449 }
3450
3451 if ((scb->flags & SCB_DEVICE_RESET) == 0
3452 && (scb->flags & SCB_PACKETIZED) == 0
3453 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3454 u_int identify_msg;
3455
3456 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3457 if ((scb->hscb->control & DISCENB) != 0)
3458 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3459 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3460 ahd->msgout_len++;
3461
3462 if ((scb->hscb->control & TAG_ENB) != 0) {
3463 ahd->msgout_buf[ahd->msgout_index++] =
3464 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3465 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3466 ahd->msgout_len += 2;
3467 }
3468 }
3469
3470 if (scb->flags & SCB_DEVICE_RESET) {
3471 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3472 ahd->msgout_len++;
3473 ahd_print_path(ahd, scb);
3474 kprintf("Bus Device Reset Message Sent\n");
3475 /*
3476 * Clear our selection hardware in advance of
3477 * the busfree. We may have an entry in the waiting
3478 * Q for this target, and we don't want to go about
3479 * selecting while we handle the busfree and blow it
3480 * away.
3481 */
3482 ahd_outb(ahd, SCSISEQ0, 0);
3483 } else if ((scb->flags & SCB_ABORT) != 0) {
3484
3485 if ((scb->hscb->control & TAG_ENB) != 0) {
3486 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3487 } else {
3488 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3489 }
3490 ahd->msgout_len++;
3491 ahd_print_path(ahd, scb);
3492 kprintf("Abort%s Message Sent\n",
3493 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3494 /*
3495 * Clear our selection hardware in advance of
3496 * the busfree. We may have an entry in the waiting
3497 * Q for this target, and we don't want to go about
3498 * selecting while we handle the busfree and blow it
3499 * away.
3500 */
3501 ahd_outb(ahd, SCSISEQ0, 0);
3502 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3503 ahd_build_transfer_msg(ahd, devinfo);
3504 /*
3505 * Clear our selection hardware in advance of potential
3506 * PPR IU status change busfree. We may have an entry in
3507 * the waiting Q for this target, and we don't want to go
3508 * about selecting while we handle the busfree and blow
3509 * it away.
3510 */
3511 ahd_outb(ahd, SCSISEQ0, 0);
3512 } else {
3513 kprintf("ahd_intr: AWAITING_MSG for an SCB that "
3514 "does not have a waiting message\n");
3515 kprintf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3516 devinfo->target_mask);
3517 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3518 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3519 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3520 scb->flags);
3521 }
3522
3523 /*
3524 * Clear the MK_MESSAGE flag from the SCB so we aren't
3525 * asked to send this message again.
3526 */
3527 ahd_outb(ahd, SCB_CONTROL,
3528 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3529 scb->hscb->control &= ~MK_MESSAGE;
3530 ahd->msgout_index = 0;
3531 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3532 }
3533
3534 /*
3535 * Build an appropriate transfer negotiation message for the
3536 * currently active target.
3537 */
3538 static void
3539 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3540 {
3541 /*
3542 * We need to initiate transfer negotiations.
3543 * If our current and goal settings are identical,
3544 * we want to renegotiate due to a check condition.
3545 */
3546 struct ahd_initiator_tinfo *tinfo;
3547 struct ahd_tmode_tstate *tstate;
3548 int dowide;
3549 int dosync;
3550 int doppr;
3551 u_int period;
3552 u_int ppr_options;
3553 u_int offset;
3554
3555 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3556 devinfo->target, &tstate);
3557 /*
3558 * Filter our period based on the current connection.
3559 * If we can't perform DT transfers on this segment (not in LVD
3560 * mode for instance), then our decision to issue a PPR message
3561 * may change.
3562 */
3563 period = tinfo->goal.period;
3564 offset = tinfo->goal.offset;
3565 ppr_options = tinfo->goal.ppr_options;
3566 /* Target initiated PPR is not allowed in the SCSI spec */
3567 if (devinfo->role == ROLE_TARGET)
3568 ppr_options = 0;
3569 ahd_devlimited_syncrate(ahd, tinfo, &period,
3570 &ppr_options, devinfo->role);
3571 dowide = tinfo->curr.width != tinfo->goal.width;
3572 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3573 /*
3574 * Only use PPR if we have options that need it, even if the device
3575 * claims to support it. There might be an expander in the way
3576 * that doesn't.
3577 */
3578 doppr = ppr_options != 0;
3579
3580 if (!dowide && !dosync && !doppr) {
3581 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3582 dosync = tinfo->goal.offset != 0;
3583 }
3584
3585 if (!dowide && !dosync && !doppr) {
3586 /*
3587 * Force async with a WDTR message if we have a wide bus,
3588 * or just issue an SDTR with a 0 offset.
3589 */
3590 if ((ahd->features & AHD_WIDE) != 0)
3591 dowide = 1;
3592 else
3593 dosync = 1;
3594
3595 if (bootverbose) {
3596 ahd_print_devinfo(ahd, devinfo);
3597 kprintf("Ensuring async\n");
3598 }
3599 }
3600 /* Target initiated PPR is not allowed in the SCSI spec */
3601 if (devinfo->role == ROLE_TARGET)
3602 doppr = 0;
3603
3604 /*
3605 * Both the PPR message and SDTR message require the
3606 * goal syncrate to be limited to what the target device
3607 * is capable of handling (based on whether an LVD->SE
3608 * expander is on the bus), so combine these two cases.
3609 * Regardless, guarantee that if we are using WDTR and SDTR
3610 * messages that WDTR comes first.
3611 */
3612 if (doppr || (dosync && !dowide)) {
3613
3614 offset = tinfo->goal.offset;
3615 ahd_validate_offset(ahd, tinfo, period, &offset,
3616 doppr ? tinfo->goal.width
3617 : tinfo->curr.width,
3618 devinfo->role);
3619 if (doppr) {
3620 ahd_construct_ppr(ahd, devinfo, period, offset,
3621 tinfo->goal.width, ppr_options);
3622 } else {
3623 ahd_construct_sdtr(ahd, devinfo, period, offset);
3624 }
3625 } else {
3626 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3627 }
3628 }
3629
3630 /*
3631 * Build a synchronous negotiation message in our message
3632 * buffer based on the input parameters.
3633 */
3634 static void
3635 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3636 u_int period, u_int offset)
3637 {
3638 if (offset == 0)
3639 period = AHD_ASYNC_XFER_PERIOD;
3640 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3641 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3642 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3643 ahd->msgout_buf[ahd->msgout_index++] = period;
3644 ahd->msgout_buf[ahd->msgout_index++] = offset;
3645 ahd->msgout_len += 5;
3646 if (bootverbose) {
3647 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3648 ahd_name(ahd), devinfo->channel, devinfo->target,
3649 devinfo->lun, period, offset);
3650 }
3651 }
3652
3653 /*
3654 * Build a wide negotiateion message in our message
3655 * buffer based on the input parameters.
3656 */
3657 static void
3658 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3659 u_int bus_width)
3660 {
3661 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3662 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3663 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3664 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3665 ahd->msgout_len += 4;
3666 if (bootverbose) {
3667 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
3668 ahd_name(ahd), devinfo->channel, devinfo->target,
3669 devinfo->lun, bus_width);
3670 }
3671 }
3672
3673 /*
3674 * Build a parallel protocol request message in our message
3675 * buffer based on the input parameters.
3676 */
3677 static void
3678 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3679 u_int period, u_int offset, u_int bus_width,
3680 u_int ppr_options)
3681 {
3682 /*
3683 * Always request precompensation from
3684 * the other target if we are running
3685 * at paced syncrates.
3686 */
3687 if (period <= AHD_SYNCRATE_PACED)
3688 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3689 if (offset == 0)
3690 period = AHD_ASYNC_XFER_PERIOD;
3691 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3692 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3693 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3694 ahd->msgout_buf[ahd->msgout_index++] = period;
3695 ahd->msgout_buf[ahd->msgout_index++] = 0;
3696 ahd->msgout_buf[ahd->msgout_index++] = offset;
3697 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3698 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3699 ahd->msgout_len += 8;
3700 if (bootverbose) {
3701 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3702 "offset %x, ppr_options %x\n", ahd_name(ahd),
3703 devinfo->channel, devinfo->target, devinfo->lun,
3704 bus_width, period, offset, ppr_options);
3705 }
3706 }
3707
3708 /*
3709 * Clear any active message state.
3710 */
3711 static void
3712 ahd_clear_msg_state(struct ahd_softc *ahd)
3713 {
3714 ahd_mode_state saved_modes;
3715
3716 saved_modes = ahd_save_modes(ahd);
3717 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3718 ahd->send_msg_perror = 0;
3719 ahd->msg_flags = MSG_FLAG_NONE;
3720 ahd->msgout_len = 0;
3721 ahd->msgin_index = 0;
3722 ahd->msg_type = MSG_TYPE_NONE;
3723 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3724 /*
3725 * The target didn't care to respond to our
3726 * message request, so clear ATN.
3727 */
3728 ahd_outb(ahd, CLRSINT1, CLRATNO);
3729 }
3730 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3731 ahd_outb(ahd, SEQ_FLAGS2,
3732 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3733 ahd_restore_modes(ahd, saved_modes);
3734 }
3735
3736 /*
3737 * Manual message loop handler.
3738 */
3739 static void
3740 ahd_handle_message_phase(struct ahd_softc *ahd)
3741 {
3742 struct ahd_devinfo devinfo;
3743 u_int bus_phase;
3744 int end_session;
3745
3746 ahd_fetch_devinfo(ahd, &devinfo);
3747 end_session = FALSE;
3748 bus_phase = ahd_inb(ahd, LASTPHASE);
3749
3750 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3751 kprintf("LQIRETRY for LQIPHASE_OUTPKT\n");
3752 ahd_outb(ahd, LQCTL2, LQIRETRY);
3753 }
3754 reswitch:
3755 switch (ahd->msg_type) {
3756 case MSG_TYPE_INITIATOR_MSGOUT:
3757 {
3758 int lastbyte;
3759 int phasemis;
3760 int msgdone;
3761
3762 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3763 panic("HOST_MSG_LOOP interrupt with no active message");
3764
3765 #ifdef AHD_DEBUG
3766 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3767 ahd_print_devinfo(ahd, &devinfo);
3768 kprintf("INITIATOR_MSG_OUT");
3769 }
3770 #endif
3771 phasemis = bus_phase != P_MESGOUT;
3772 if (phasemis) {
3773 #ifdef AHD_DEBUG
3774 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3775 kprintf(" PHASEMIS %s\n",
3776 ahd_lookup_phase_entry(bus_phase)
3777 ->phasemsg);
3778 }
3779 #endif
3780 if (bus_phase == P_MESGIN) {
3781 /*
3782 * Change gears and see if
3783 * this messages is of interest to
3784 * us or should be passed back to
3785 * the sequencer.
3786 */
3787 ahd_outb(ahd, CLRSINT1, CLRATNO);
3788 ahd->send_msg_perror = 0;
3789 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3790 ahd->msgin_index = 0;
3791 goto reswitch;
3792 }
3793 end_session = TRUE;
3794 break;
3795 }
3796
3797 if (ahd->send_msg_perror) {
3798 ahd_outb(ahd, CLRSINT1, CLRATNO);
3799 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3800 #ifdef AHD_DEBUG
3801 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3802 kprintf(" byte 0x%x\n", ahd->send_msg_perror);
3803 #endif
3804 /*
3805 * If we are notifying the target of a CRC error
3806 * during packetized operations, the target is
3807 * within its rights to acknowledge our message
3808 * with a busfree.
3809 */
3810 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3811 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3812 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3813
3814 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3815 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3816 break;
3817 }
3818
3819 msgdone = ahd->msgout_index == ahd->msgout_len;
3820 if (msgdone) {
3821 /*
3822 * The target has requested a retry.
3823 * Re-assert ATN, reset our message index to
3824 * 0, and try again.
3825 */
3826 ahd->msgout_index = 0;
3827 ahd_assert_atn(ahd);
3828 }
3829
3830 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3831 if (lastbyte) {
3832 /* Last byte is signified by dropping ATN */
3833 ahd_outb(ahd, CLRSINT1, CLRATNO);
3834 }
3835
3836 /*
3837 * Clear our interrupt status and present
3838 * the next byte on the bus.
3839 */
3840 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3841 #ifdef AHD_DEBUG
3842 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3843 kprintf(" byte 0x%x\n",
3844 ahd->msgout_buf[ahd->msgout_index]);
3845 #endif
3846 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3847 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3848 break;
3849 }
3850 case MSG_TYPE_INITIATOR_MSGIN:
3851 {
3852 int phasemis;
3853 int message_done;
3854
3855 #ifdef AHD_DEBUG
3856 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3857 ahd_print_devinfo(ahd, &devinfo);
3858 kprintf("INITIATOR_MSG_IN");
3859 }
3860 #endif
3861 phasemis = bus_phase != P_MESGIN;
3862 if (phasemis) {
3863 #ifdef AHD_DEBUG
3864 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3865 kprintf(" PHASEMIS %s\n",
3866 ahd_lookup_phase_entry(bus_phase)
3867 ->phasemsg);
3868 }
3869 #endif
3870 ahd->msgin_index = 0;
3871 if (bus_phase == P_MESGOUT
3872 && (ahd->send_msg_perror != 0
3873 || (ahd->msgout_len != 0
3874 && ahd->msgout_index == 0))) {
3875 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3876 goto reswitch;
3877 }
3878 end_session = TRUE;
3879 break;
3880 }
3881
3882 /* Pull the byte in without acking it */
3883 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
3884 #ifdef AHD_DEBUG
3885 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3886 kprintf(" byte 0x%x\n",
3887 ahd->msgin_buf[ahd->msgin_index]);
3888 #endif
3889
3890 message_done = ahd_parse_msg(ahd, &devinfo);
3891
3892 if (message_done) {
3893 /*
3894 * Clear our incoming message buffer in case there
3895 * is another message following this one.
3896 */
3897 ahd->msgin_index = 0;
3898
3899 /*
3900 * If this message illicited a response,
3901 * assert ATN so the target takes us to the
3902 * message out phase.
3903 */
3904 if (ahd->msgout_len != 0) {
3905 #ifdef AHD_DEBUG
3906 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3907 ahd_print_devinfo(ahd, &devinfo);
3908 kprintf("Asserting ATN for response\n");
3909 }
3910 #endif
3911 ahd_assert_atn(ahd);
3912 }
3913 } else
3914 ahd->msgin_index++;
3915
3916 if (message_done == MSGLOOP_TERMINATED) {
3917 end_session = TRUE;
3918 } else {
3919 /* Ack the byte */
3920 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3921 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
3922 }
3923 break;
3924 }
3925 case MSG_TYPE_TARGET_MSGIN:
3926 {
3927 int msgdone;
3928 int msgout_request;
3929
3930 /*
3931 * By default, the message loop will continue.
3932 */
3933 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
3934
3935 if (ahd->msgout_len == 0)
3936 panic("Target MSGIN with no active message");
3937
3938 /*
3939 * If we interrupted a mesgout session, the initiator
3940 * will not know this until our first REQ. So, we
3941 * only honor mesgout requests after we've sent our
3942 * first byte.
3943 */
3944 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
3945 && ahd->msgout_index > 0)
3946 msgout_request = TRUE;
3947 else
3948 msgout_request = FALSE;
3949
3950 if (msgout_request) {
3951
3952 /*
3953 * Change gears and see if
3954 * this messages is of interest to
3955 * us or should be passed back to
3956 * the sequencer.
3957 */
3958 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
3959 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
3960 ahd->msgin_index = 0;
3961 /* Dummy read to REQ for first byte */
3962 ahd_inb(ahd, SCSIDAT);
3963 ahd_outb(ahd, SXFRCTL0,
3964 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
3965 break;
3966 }
3967
3968 msgdone = ahd->msgout_index == ahd->msgout_len;
3969 if (msgdone) {
3970 ahd_outb(ahd, SXFRCTL0,
3971 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
3972 end_session = TRUE;
3973 break;
3974 }
3975
3976 /*
3977 * Present the next byte on the bus.
3978 */
3979 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
3980 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
3981 break;
3982 }
3983 case MSG_TYPE_TARGET_MSGOUT:
3984 {
3985 int lastbyte;
3986 int msgdone;
3987
3988 /*
3989 * By default, the message loop will continue.
3990 */
3991 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
3992
3993 /*
3994 * The initiator signals that this is
3995 * the last byte by dropping ATN.
3996 */
3997 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
3998
3999 /*
4000 * Read the latched byte, but turn off SPIOEN first
4001 * so that we don't inadvertently cause a REQ for the
4002 * next byte.
4003 */
4004 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4005 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4006 msgdone = ahd_parse_msg(ahd, &devinfo);
4007 if (msgdone == MSGLOOP_TERMINATED) {
4008 /*
4009 * The message is *really* done in that it caused
4010 * us to go to bus free. The sequencer has already
4011 * been reset at this point, so pull the ejection
4012 * handle.
4013 */
4014 return;
4015 }
4016
4017 ahd->msgin_index++;
4018
4019 /*
4020 * XXX Read spec about initiator dropping ATN too soon
4021 * and use msgdone to detect it.
4022 */
4023 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4024 ahd->msgin_index = 0;
4025
4026 /*
4027 * If this message illicited a response, transition
4028 * to the Message in phase and send it.
4029 */
4030 if (ahd->msgout_len != 0) {
4031 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4032 ahd_outb(ahd, SXFRCTL0,
4033 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4034 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4035 ahd->msgin_index = 0;
4036 break;
4037 }
4038 }
4039
4040 if (lastbyte)
4041 end_session = TRUE;
4042 else {
4043 /* Ask for the next byte. */
4044 ahd_outb(ahd, SXFRCTL0,
4045 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4046 }
4047
4048 break;
4049 }
4050 default:
4051 panic("Unknown REQINIT message type");
4052 }
4053
4054 if (end_session) {
4055 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4056 kprintf("%s: Returning to Idle Loop\n",
4057 ahd_name(ahd));
4058 ahd_clear_msg_state(ahd);
4059
4060 /*
4061 * Perform the equivalent of a clear_target_state.
4062 */
4063 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4064 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4065 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4066 } else {
4067 ahd_clear_msg_state(ahd);
4068 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4069 }
4070 }
4071 }
4072
4073 /*
4074 * See if we sent a particular extended message to the target.
4075 * If "full" is true, return true only if the target saw the full
4076 * message. If "full" is false, return true if the target saw at
4077 * least the first byte of the message.
4078 */
4079 static int
4080 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4081 {
4082 int found;
4083 u_int index;
4084
4085 found = FALSE;
4086 index = 0;
4087
4088 while (index < ahd->msgout_len) {
4089 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4090 u_int end_index;
4091
4092 end_index = index + 1 + ahd->msgout_buf[index + 1];
4093 if (ahd->msgout_buf[index+2] == msgval
4094 && type == AHDMSG_EXT) {
4095
4096 if (full) {
4097 if (ahd->msgout_index > end_index)
4098 found = TRUE;
4099 } else if (ahd->msgout_index > index)
4100 found = TRUE;
4101 }
4102 index = end_index;
4103 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4104 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4105
4106 /* Skip tag type and tag id or residue param*/
4107 index += 2;
4108 } else {
4109 /* Single byte message */
4110 if (type == AHDMSG_1B
4111 && ahd->msgout_index > index
4112 && (ahd->msgout_buf[index] == msgval
4113 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4114 && msgval == MSG_IDENTIFYFLAG)))
4115 found = TRUE;
4116 index++;
4117 }
4118
4119 if (found)
4120 break;
4121 }
4122 return (found);
4123 }
4124
4125 /*
4126 * Wait for a complete incoming message, parse it, and respond accordingly.
4127 */
4128 static int
4129 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4130 {
4131 struct ahd_initiator_tinfo *tinfo;
4132 struct ahd_tmode_tstate *tstate;
4133 int reject;
4134 int done;
4135 int response;
4136
4137 done = MSGLOOP_IN_PROG;
4138 response = FALSE;
4139 reject = FALSE;
4140 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4141 devinfo->target, &tstate);
4142
4143 /*
4144 * Parse as much of the message as is available,
4145 * rejecting it if we don't support it. When
4146 * the entire message is available and has been
4147 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4148 * that we have parsed an entire message.
4149 *
4150 * In the case of extended messages, we accept the length
4151 * byte outright and perform more checking once we know the
4152 * extended message type.
4153 */
4154 switch (ahd->msgin_buf[0]) {
4155 case MSG_DISCONNECT:
4156 case MSG_SAVEDATAPOINTER:
4157 case MSG_CMDCOMPLETE:
4158 case MSG_RESTOREPOINTERS:
4159 case MSG_IGN_WIDE_RESIDUE:
4160 /*
4161 * End our message loop as these are messages
4162 * the sequencer handles on its own.
4163 */
4164 done = MSGLOOP_TERMINATED;
4165 break;
4166 case MSG_MESSAGE_REJECT:
4167 response = ahd_handle_msg_reject(ahd, devinfo);
4168 /* FALLTHROUGH */
4169 case MSG_NOOP:
4170 done = MSGLOOP_MSGCOMPLETE;
4171 break;
4172 case MSG_EXTENDED:
4173 {
4174 /* Wait for enough of the message to begin validation */
4175 if (ahd->msgin_index < 2)
4176 break;
4177 switch (ahd->msgin_buf[2]) {
4178 case MSG_EXT_SDTR:
4179 {
4180 u_int period;
4181 u_int ppr_options;
4182 u_int offset;
4183 u_int saved_offset;
4184
4185 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4186 reject = TRUE;
4187 break;
4188 }
4189
4190 /*
4191 * Wait until we have both args before validating
4192 * and acting on this message.
4193 *
4194 * Add one to MSG_EXT_SDTR_LEN to account for
4195 * the extended message preamble.
4196 */
4197 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4198 break;
4199
4200 period = ahd->msgin_buf[3];
4201 ppr_options = 0;
4202 saved_offset = offset = ahd->msgin_buf[4];
4203 ahd_devlimited_syncrate(ahd, tinfo, &period,
4204 &ppr_options, devinfo->role);
4205 ahd_validate_offset(ahd, tinfo, period, &offset,
4206 tinfo->curr.width, devinfo->role);
4207 if (bootverbose) {
4208 kprintf("(%s:%c:%d:%d): Received "
4209 "SDTR period %x, offset %x\n\t"
4210 "Filtered to period %x, offset %x\n",
4211 ahd_name(ahd), devinfo->channel,
4212 devinfo->target, devinfo->lun,
4213 ahd->msgin_buf[3], saved_offset,
4214 period, offset);
4215 }
4216 ahd_set_syncrate(ahd, devinfo, period,
4217 offset, ppr_options,
4218 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4219 /*paused*/TRUE);
4220
4221 /*
4222 * See if we initiated Sync Negotiation
4223 * and didn't have to fall down to async
4224 * transfers.
4225 */
4226 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4227 /* We started it */
4228 if (saved_offset != offset) {
4229 /* Went too low - force async */
4230 reject = TRUE;
4231 }
4232 } else {
4233 /*
4234 * Send our own SDTR in reply
4235 */
4236 if (bootverbose
4237 && devinfo->role == ROLE_INITIATOR) {
4238 kprintf("(%s:%c:%d:%d): Target "
4239 "Initiated SDTR\n",
4240 ahd_name(ahd), devinfo->channel,
4241 devinfo->target, devinfo->lun);
4242 }
4243 ahd->msgout_index = 0;
4244 ahd->msgout_len = 0;
4245 ahd_construct_sdtr(ahd, devinfo,
4246 period, offset);
4247 ahd->msgout_index = 0;
4248 response = TRUE;
4249 }
4250 done = MSGLOOP_MSGCOMPLETE;
4251 break;
4252 }
4253 case MSG_EXT_WDTR:
4254 {
4255 u_int bus_width;
4256 u_int saved_width;
4257 u_int sending_reply;
4258
4259 sending_reply = FALSE;
4260 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4261 reject = TRUE;
4262 break;
4263 }
4264
4265 /*
4266 * Wait until we have our arg before validating
4267 * and acting on this message.
4268 *
4269 * Add one to MSG_EXT_WDTR_LEN to account for
4270 * the extended message preamble.
4271 */
4272 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4273 break;
4274
4275 bus_width = ahd->msgin_buf[3];
4276 saved_width = bus_width;
4277 ahd_validate_width(ahd, tinfo, &bus_width,
4278 devinfo->role);
4279 if (bootverbose) {
4280 kprintf("(%s:%c:%d:%d): Received WDTR "
4281 "%x filtered to %x\n",
4282 ahd_name(ahd), devinfo->channel,
4283 devinfo->target, devinfo->lun,
4284 saved_width, bus_width);
4285 }
4286
4287 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4288 /*
4289 * Don't send a WDTR back to the
4290 * target, since we asked first.
4291 * If the width went higher than our
4292 * request, reject it.
4293 */
4294 if (saved_width > bus_width) {
4295 reject = TRUE;
4296 kprintf("(%s:%c:%d:%d): requested %dBit "
4297 "transfers. Rejecting...\n",
4298 ahd_name(ahd), devinfo->channel,
4299 devinfo->target, devinfo->lun,
4300 8 * (0x01 << bus_width));
4301 bus_width = 0;
4302 }
4303 } else {
4304 /*
4305 * Send our own WDTR in reply
4306 */
4307 if (bootverbose
4308 && devinfo->role == ROLE_INITIATOR) {
4309 kprintf("(%s:%c:%d:%d): Target "
4310 "Initiated WDTR\n",
4311 ahd_name(ahd), devinfo->channel,
4312 devinfo->target, devinfo->lun);
4313 }
4314 ahd->msgout_index = 0;
4315 ahd->msgout_len = 0;
4316 ahd_construct_wdtr(ahd, devinfo, bus_width);
4317 ahd->msgout_index = 0;
4318 response = TRUE;
4319 sending_reply = TRUE;
4320 }
4321 /*
4322 * After a wide message, we are async, but
4323 * some devices don't seem to honor this portion
4324 * of the spec. Force a renegotiation of the
4325 * sync component of our transfer agreement even
4326 * if our goal is async. By updating our width
4327 * after forcing the negotiation, we avoid
4328 * renegotiating for width.
4329 */
4330 ahd_update_neg_request(ahd, devinfo, tstate,
4331 tinfo, AHD_NEG_ALWAYS);
4332 ahd_set_width(ahd, devinfo, bus_width,
4333 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4334 /*paused*/TRUE);
4335 if (sending_reply == FALSE && reject == FALSE) {
4336
4337 /*
4338 * We will always have an SDTR to send.
4339 */
4340 ahd->msgout_index = 0;
4341 ahd->msgout_len = 0;
4342 ahd_build_transfer_msg(ahd, devinfo);
4343 ahd->msgout_index = 0;
4344 response = TRUE;
4345 }
4346 done = MSGLOOP_MSGCOMPLETE;
4347 break;
4348 }
4349 case MSG_EXT_PPR:
4350 {
4351 u_int period;
4352 u_int offset;
4353 u_int bus_width;
4354 u_int ppr_options;
4355 u_int saved_width;
4356 u_int saved_offset;
4357 u_int saved_ppr_options;
4358
4359 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4360 reject = TRUE;
4361 break;
4362 }
4363
4364 /*
4365 * Wait until we have all args before validating
4366 * and acting on this message.
4367 *
4368 * Add one to MSG_EXT_PPR_LEN to account for
4369 * the extended message preamble.
4370 */
4371 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4372 break;
4373
4374 period = ahd->msgin_buf[3];
4375 offset = ahd->msgin_buf[5];
4376 bus_width = ahd->msgin_buf[6];
4377 saved_width = bus_width;
4378 ppr_options = ahd->msgin_buf[7];
4379 /*
4380 * According to the spec, a DT only
4381 * period factor with no DT option
4382 * set implies async.
4383 */
4384 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4385 && period <= 9)
4386 offset = 0;
4387 saved_ppr_options = ppr_options;
4388 saved_offset = offset;
4389
4390 /*
4391 * Transfer options are only available if we
4392 * are negotiating wide.
4393 */
4394 if (bus_width == 0)
4395 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4396
4397 ahd_validate_width(ahd, tinfo, &bus_width,
4398 devinfo->role);
4399 ahd_devlimited_syncrate(ahd, tinfo, &period,
4400 &ppr_options, devinfo->role);
4401 ahd_validate_offset(ahd, tinfo, period, &offset,
4402 bus_width, devinfo->role);
4403
4404 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4405 /*
4406 * If we are unable to do any of the
4407 * requested options (we went too low),
4408 * then we'll have to reject the message.
4409 */
4410 if (saved_width > bus_width
4411 || saved_offset != offset
4412 || saved_ppr_options != ppr_options) {
4413 reject = TRUE;
4414 period = 0;
4415 offset = 0;
4416 bus_width = 0;
4417 ppr_options = 0;
4418 }
4419 } else {
4420 if (devinfo->role != ROLE_TARGET)
4421 kprintf("(%s:%c:%d:%d): Target "
4422 "Initiated PPR\n",
4423 ahd_name(ahd), devinfo->channel,
4424 devinfo->target, devinfo->lun);
4425 else
4426 kprintf("(%s:%c:%d:%d): Initiator "
4427 "Initiated PPR\n",
4428 ahd_name(ahd), devinfo->channel,
4429 devinfo->target, devinfo->lun);
4430 ahd->msgout_index = 0;
4431 ahd->msgout_len = 0;
4432 ahd_construct_ppr(ahd, devinfo, period, offset,
4433 bus_width, ppr_options);
4434 ahd->msgout_index = 0;
4435 response = TRUE;
4436 }
4437 if (bootverbose) {
4438 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
4439 "period %x, offset %x,options %x\n"
4440 "\tFiltered to width %x, period %x, "
4441 "offset %x, options %x\n",
4442 ahd_name(ahd), devinfo->channel,
4443 devinfo->target, devinfo->lun,
4444 saved_width, ahd->msgin_buf[3],
4445 saved_offset, saved_ppr_options,
4446 bus_width, period, offset, ppr_options);
4447 }
4448 ahd_set_width(ahd, devinfo, bus_width,
4449 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4450 /*paused*/TRUE);
4451 ahd_set_syncrate(ahd, devinfo, period,
4452 offset, ppr_options,
4453 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4454 /*paused*/TRUE);
4455
4456 done = MSGLOOP_MSGCOMPLETE;
4457 break;
4458 }
4459 default:
4460 /* Unknown extended message. Reject it. */
4461 reject = TRUE;
4462 break;
4463 }
4464 break;
4465 }
4466 #ifdef AHD_TARGET_MODE
4467 case MSG_BUS_DEV_RESET:
4468 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4469 CAM_BDR_SENT,
4470 "Bus Device Reset Received",
4471 /*verbose_level*/0);
4472 ahd_restart(ahd);
4473 done = MSGLOOP_TERMINATED;
4474 break;
4475 case MSG_ABORT_TAG:
4476 case MSG_ABORT:
4477 case MSG_CLEAR_QUEUE:
4478 {
4479 int tag;
4480
4481 /* Target mode messages */
4482 if (devinfo->role != ROLE_TARGET) {
4483 reject = TRUE;
4484 break;
4485 }
4486 tag = SCB_LIST_NULL;
4487 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4488 tag = ahd_inb(ahd, INITIATOR_TAG);
4489 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4490 devinfo->lun, tag, ROLE_TARGET,
4491 CAM_REQ_ABORTED);
4492
4493 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4494 if (tstate != NULL) {
4495 struct ahd_tmode_lstate* lstate;
4496
4497 lstate = tstate->enabled_luns[devinfo->lun];
4498 if (lstate != NULL) {
4499 ahd_queue_lstate_event(ahd, lstate,
4500 devinfo->our_scsiid,
4501 ahd->msgin_buf[0],
4502 /*arg*/tag);
4503 ahd_send_lstate_events(ahd, lstate);
4504 }
4505 }
4506 ahd_restart(ahd);
4507 done = MSGLOOP_TERMINATED;
4508 break;
4509 }
4510 #endif
4511 case MSG_QAS_REQUEST:
4512 #ifdef AHD_DEBUG
4513 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4514 kprintf("%s: QAS request. SCSISIGI == 0x%x\n",
4515 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4516 #endif
4517 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4518 /* FALLTHROUGH */
4519 case MSG_TERM_IO_PROC:
4520 default:
4521 reject = TRUE;
4522 break;
4523 }
4524
4525 if (reject) {
4526 /*
4527 * Setup to reject the message.
4528 */
4529 ahd->msgout_index = 0;
4530 ahd->msgout_len = 1;
4531 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4532 done = MSGLOOP_MSGCOMPLETE;
4533 response = TRUE;
4534 }
4535
4536 if (done != MSGLOOP_IN_PROG && !response)
4537 /* Clear the outgoing message buffer */
4538 ahd->msgout_len = 0;
4539
4540 return (done);
4541 }
4542
4543 /*
4544 * Process a message reject message.
4545 */
4546 static int
4547 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4548 {
4549 /*
4550 * What we care about here is if we had an
4551 * outstanding SDTR or WDTR message for this
4552 * target. If we did, this is a signal that
4553 * the target is refusing negotiation.
4554 */
4555 struct scb *scb;
4556 struct ahd_initiator_tinfo *tinfo;
4557 struct ahd_tmode_tstate *tstate;
4558 u_int scb_index;
4559 u_int last_msg;
4560 int response = 0;
4561
4562 scb_index = ahd_get_scbptr(ahd);
4563 scb = ahd_lookup_scb(ahd, scb_index);
4564 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4565 devinfo->our_scsiid,
4566 devinfo->target, &tstate);
4567 /* Might be necessary */
4568 last_msg = ahd_inb(ahd, LAST_MSG);
4569
4570 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4571 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4572 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4573 /*
4574 * Target may not like our SPI-4 PPR Options.
4575 * Attempt to negotiate 80MHz which will turn
4576 * off these options.
4577 */
4578 if (bootverbose) {
4579 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4580 "Trying simple U160 PPR\n",
4581 ahd_name(ahd), devinfo->channel,
4582 devinfo->target, devinfo->lun);
4583 }
4584 tinfo->goal.period = AHD_SYNCRATE_DT;
4585 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4586 | MSG_EXT_PPR_QAS_REQ
4587 | MSG_EXT_PPR_DT_REQ;
4588 } else {
4589 /*
4590 * Target does not support the PPR message.
4591 * Attempt to negotiate SPI-2 style.
4592 */
4593 if (bootverbose) {
4594 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4595 "Trying WDTR/SDTR\n",
4596 ahd_name(ahd), devinfo->channel,
4597 devinfo->target, devinfo->lun);
4598 }
4599 tinfo->goal.ppr_options = 0;
4600 tinfo->curr.transport_version = 2;
4601 tinfo->goal.transport_version = 2;
4602 }
4603 ahd->msgout_index = 0;
4604 ahd->msgout_len = 0;
4605 ahd_build_transfer_msg(ahd, devinfo);
4606 ahd->msgout_index = 0;
4607 response = 1;
4608 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4609
4610 /* note 8bit xfers */
4611 kprintf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4612 "8bit transfers\n", ahd_name(ahd),
4613 devinfo->channel, devinfo->target, devinfo->lun);
4614 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4615 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4616 /*paused*/TRUE);
4617 /*
4618 * No need to clear the sync rate. If the target
4619 * did not accept the command, our syncrate is
4620 * unaffected. If the target started the negotiation,
4621 * but rejected our response, we already cleared the
4622 * sync rate before sending our WDTR.
4623 */
4624 if (tinfo->goal.offset != tinfo->curr.offset) {
4625
4626 /* Start the sync negotiation */
4627 ahd->msgout_index = 0;
4628 ahd->msgout_len = 0;
4629 ahd_build_transfer_msg(ahd, devinfo);
4630 ahd->msgout_index = 0;
4631 response = 1;
4632 }
4633 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4634 /* note asynch xfers and clear flag */
4635 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4636 /*offset*/0, /*ppr_options*/0,
4637 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4638 /*paused*/TRUE);
4639 kprintf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4640 "Using asynchronous transfers\n",
4641 ahd_name(ahd), devinfo->channel,
4642 devinfo->target, devinfo->lun);
4643 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4644 int tag_type;
4645 int mask;
4646
4647 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4648
4649 if (tag_type == MSG_SIMPLE_TASK) {
4650 kprintf("(%s:%c:%d:%d): refuses tagged commands. "
4651 "Performing non-tagged I/O\n", ahd_name(ahd),
4652 devinfo->channel, devinfo->target, devinfo->lun);
4653 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4654 mask = ~0x23;
4655 } else {
4656 kprintf("(%s:%c:%d:%d): refuses %s tagged commands. "
4657 "Performing simple queue tagged I/O only\n",
4658 ahd_name(ahd), devinfo->channel, devinfo->target,
4659 devinfo->lun, tag_type == MSG_ORDERED_TASK
4660 ? "ordered" : "head of queue");
4661 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4662 mask = ~0x03;
4663 }
4664
4665 /*
4666 * Resend the identify for this CCB as the target
4667 * may believe that the selection is invalid otherwise.
4668 */
4669 ahd_outb(ahd, SCB_CONTROL,
4670 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4671 scb->hscb->control &= mask;
4672 ahd_set_transaction_tag(scb, /*enabled*/FALSE,
4673 /*type*/MSG_SIMPLE_TASK);
4674 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4675 ahd_assert_atn(ahd);
4676 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4677 SCB_GET_TAG(scb));
4678
4679 /*
4680 * Requeue all tagged commands for this target
4681 * currently in our posession so they can be
4682 * converted to untagged commands.
4683 */
4684 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4685 SCB_GET_CHANNEL(ahd, scb),
4686 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4687 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4688 SEARCH_COMPLETE);
4689 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4690 /*
4691 * Most likely the device believes that we had
4692 * previously negotiated packetized.
4693 */
4694 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4695 | MSG_FLAG_IU_REQ_CHANGED;
4696
4697 ahd_force_renegotiation(ahd, devinfo);
4698 ahd->msgout_index = 0;
4699 ahd->msgout_len = 0;
4700 ahd_build_transfer_msg(ahd, devinfo);
4701 ahd->msgout_index = 0;
4702 response = 1;
4703 } else {
4704 /*
4705 * Otherwise, we ignore it.
4706 */
4707 kprintf("%s:%c:%d: Message reject for %x -- ignored\n",
4708 ahd_name(ahd), devinfo->channel, devinfo->target,
4709 last_msg);
4710 }
4711 return (response);
4712 }
4713
4714 /*
4715 * Process an ingnore wide residue message.
4716 */
4717 static void
4718 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4719 {
4720 u_int scb_index;
4721 struct scb *scb;
4722
4723 scb_index = ahd_get_scbptr(ahd);
4724 scb = ahd_lookup_scb(ahd, scb_index);
4725 /*
4726 * XXX Actually check data direction in the sequencer?
4727 * Perhaps add datadir to some spare bits in the hscb?
4728 */
4729 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4730 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) {
4731 /*
4732 * Ignore the message if we haven't
4733 * seen an appropriate data phase yet.
4734 */
4735 } else {
4736 /*
4737 * If the residual occurred on the last
4738 * transfer and the transfer request was
4739 * expected to end on an odd count, do
4740 * nothing. Otherwise, subtract a byte
4741 * and update the residual count accordingly.
4742 */
4743 uint32_t sgptr;
4744
4745 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4746 if ((sgptr & SG_LIST_NULL) != 0
4747 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4748 & SCB_XFERLEN_ODD) != 0) {
4749 /*
4750 * If the residual occurred on the last
4751 * transfer and the transfer request was
4752 * expected to end on an odd count, do
4753 * nothing.
4754 */
4755 } else {
4756 uint32_t data_cnt;
4757 uint64_t data_addr;
4758 uint32_t sglen;
4759
4760 /* Pull in the rest of the sgptr */
4761 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4762 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4763 if ((sgptr & SG_LIST_NULL) != 0) {
4764 /*
4765 * The residual data count is not updated
4766 * for the command run to completion case.
4767 * Explicitly zero the count.
4768 */
4769 data_cnt &= ~AHD_SG_LEN_MASK;
4770 }
4771 data_addr = ahd_inq(ahd, SHADDR);
4772 data_cnt += 1;
4773 data_addr -= 1;
4774 sgptr &= SG_PTR_MASK;
4775 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4776 struct ahd_dma64_seg *sg;
4777
4778 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4779
4780 /*
4781 * The residual sg ptr points to the next S/G
4782 * to load so we must go back one.
4783 */
4784 sg--;
4785 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4786 if (sg != scb->sg_list
4787 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4788
4789 sg--;
4790 sglen = ahd_le32toh(sg->len);
4791 /*
4792 * Preserve High Address and SG_LIST
4793 * bits while setting the count to 1.
4794 */
4795 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4796 data_addr = ahd_le64toh(sg->addr)
4797 + (sglen & AHD_SG_LEN_MASK)
4798 - 1;
4799
4800 /*
4801 * Increment sg so it points to the
4802 * "next" sg.
4803 */
4804 sg++;
4805 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4806 sg);
4807 }
4808 } else {
4809 struct ahd_dma_seg *sg;
4810
4811 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4812
4813 /*
4814 * The residual sg ptr points to the next S/G
4815 * to load so we must go back one.
4816 */
4817 sg--;
4818 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4819 if (sg != scb->sg_list
4820 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4821
4822 sg--;
4823 sglen = ahd_le32toh(sg->len);
4824 /*
4825 * Preserve High Address and SG_LIST
4826 * bits while setting the count to 1.
4827 */
4828 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4829 data_addr = ahd_le32toh(sg->addr)
4830 + (sglen & AHD_SG_LEN_MASK)
4831 - 1;
4832
4833 /*
4834 * Increment sg so it points to the
4835 * "next" sg.
4836 */
4837 sg++;
4838 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4839 sg);
4840 }
4841 }
4842 /*
4843 * Toggle the "oddness" of the transfer length
4844 * to handle this mid-transfer ignore wide
4845 * residue. This ensures that the oddness is
4846 * correct for subsequent data transfers.
4847 */
4848 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4849 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4850 ^ SCB_XFERLEN_ODD);
4851
4852 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4853 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4854 /*
4855 * The FIFO's pointers will be updated if/when the
4856 * sequencer re-enters a data phase.
4857 */
4858 }
4859 }
4860 }
4861
4862
4863 /*
4864 * Reinitialize the data pointers for the active transfer
4865 * based on its current residual.
4866 */
4867 static void
4868 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4869 {
4870 struct scb *scb;
4871 ahd_mode_state saved_modes;
4872 u_int scb_index;
4873 u_int wait;
4874 uint32_t sgptr;
4875 uint32_t resid;
4876 uint64_t dataptr;
4877
4878 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
4879 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
4880
4881 scb_index = ahd_get_scbptr(ahd);
4882 scb = ahd_lookup_scb(ahd, scb_index);
4883
4884 /*
4885 * Release and reacquire the FIFO so we
4886 * have a clean slate.
4887 */
4888 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
4889 wait = 1000;
4890 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
4891 ahd_delay(100);
4892 if (wait == 0) {
4893 ahd_print_path(ahd, scb);
4894 kprintf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
4895 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
4896 }
4897 saved_modes = ahd_save_modes(ahd);
4898 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
4899 ahd_outb(ahd, DFFSTAT,
4900 ahd_inb(ahd, DFFSTAT)
4901 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
4902
4903 /*
4904 * Determine initial values for data_addr and data_cnt
4905 * for resuming the data phase.
4906 */
4907 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24)
4908 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16)
4909 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8)
4910 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4911 sgptr &= SG_PTR_MASK;
4912
4913 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
4914 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
4915 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
4916
4917 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4918 struct ahd_dma64_seg *sg;
4919
4920 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4921
4922 /* The residual sg_ptr always points to the next sg */
4923 sg--;
4924
4925 dataptr = ahd_le64toh(sg->addr)
4926 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
4927 - resid;
4928 ahd_outb(ahd, HADDR + 7, dataptr >> 56);
4929 ahd_outb(ahd, HADDR + 6, dataptr >> 48);
4930 ahd_outb(ahd, HADDR + 5, dataptr >> 40);
4931 ahd_outb(ahd, HADDR + 4, dataptr >> 32);
4932 } else {
4933 struct ahd_dma_seg *sg;
4934
4935 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4936
4937 /* The residual sg_ptr always points to the next sg */
4938 sg--;
4939
4940 dataptr = ahd_le32toh(sg->addr)
4941 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
4942 - resid;
4943 ahd_outb(ahd, HADDR + 4,
4944 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
4945 }
4946 ahd_outb(ahd, HADDR + 3, dataptr >> 24);
4947 ahd_outb(ahd, HADDR + 2, dataptr >> 16);
4948 ahd_outb(ahd, HADDR + 1, dataptr >> 8);
4949 ahd_outb(ahd, HADDR, dataptr);
4950 ahd_outb(ahd, HCNT + 2, resid >> 16);
4951 ahd_outb(ahd, HCNT + 1, resid >> 8);
4952 ahd_outb(ahd, HCNT, resid);
4953 }
4954
4955 /*
4956 * Handle the effects of issuing a bus device reset message.
4957 */
4958 static void
4959 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
4960 u_int lun, cam_status status, char *message,
4961 int verbose_level)
4962 {
4963 #ifdef AHD_TARGET_MODE
4964 struct ahd_tmode_tstate* tstate;
4965 #endif
4966 int found;
4967
4968 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4969 lun, SCB_LIST_NULL, devinfo->role,
4970 status);
4971
4972 #ifdef AHD_TARGET_MODE
4973 /*
4974 * Send an immediate notify ccb to all target mord peripheral
4975 * drivers affected by this action.
4976 */
4977 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4978 if (tstate != NULL) {
4979 u_int cur_lun;
4980 u_int max_lun;
4981
4982 if (lun != CAM_LUN_WILDCARD) {
4983 cur_lun = 0;
4984 max_lun = AHD_NUM_LUNS - 1;
4985 } else {
4986 cur_lun = lun;
4987 max_lun = lun;
4988 }
4989 for (cur_lun <= max_lun; cur_lun++) {
4990 struct ahd_tmode_lstate* lstate;
4991
4992 lstate = tstate->enabled_luns[cur_lun];
4993 if (lstate == NULL)
4994 continue;
4995
4996 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
4997 MSG_BUS_DEV_RESET, /*arg*/0);
4998 ahd_send_lstate_events(ahd, lstate);
4999 }
5000 }
5001 #endif
5002
5003 /*
5004 * Go back to async/narrow transfers and renegotiate.
5005 */
5006 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5007 AHD_TRANS_CUR, /*paused*/TRUE);
5008 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5009 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE);
5010
5011 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5012 lun, AC_SENT_BDR, NULL);
5013
5014 if (message != NULL
5015 && (verbose_level <= bootverbose))
5016 kprintf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5017 message, devinfo->channel, devinfo->target, found);
5018 }
5019
5020 #ifdef AHD_TARGET_MODE
5021 static void
5022 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5023 struct scb *scb)
5024 {
5025
5026 /*
5027 * To facilitate adding multiple messages together,
5028 * each routine should increment the index and len
5029 * variables instead of setting them explicitly.
5030 */
5031 ahd->msgout_index = 0;
5032 ahd->msgout_len = 0;
5033
5034 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5035 ahd_build_transfer_msg(ahd, devinfo);
5036 else
5037 panic("ahd_intr: AWAITING target message with no message");
5038
5039 ahd->msgout_index = 0;
5040 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5041 }
5042 #endif
5043 /**************************** Initialization **********************************/
5044 static u_int
5045 ahd_sglist_size(struct ahd_softc *ahd)
5046 {
5047 bus_size_t list_size;
5048
5049 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5050 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5051 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5052 return (list_size);
5053 }
5054
5055 /*
5056 * Calculate the optimum S/G List allocation size. S/G elements used
5057 * for a given transaction must be physically contiguous. Assume the
5058 * OS will allocate full pages to us, so it doesn't make sense to request
5059 * less than a page.
5060 */
5061 static u_int
5062 ahd_sglist_allocsize(struct ahd_softc *ahd)
5063 {
5064 bus_size_t sg_list_increment;
5065 bus_size_t sg_list_size;
5066 bus_size_t max_list_size;
5067 bus_size_t best_list_size;
5068
5069 /* Start out with the minimum required for AHD_NSEG. */
5070 sg_list_increment = ahd_sglist_size(ahd);
5071 sg_list_size = sg_list_increment;
5072
5073 /* Get us as close as possible to a page in size. */
5074 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5075 sg_list_size += sg_list_increment;
5076
5077 /*
5078 * Try to reduce the amount of wastage by allocating
5079 * multiple pages.
5080 */
5081 best_list_size = sg_list_size;
5082 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5083 if (max_list_size < 4 * PAGE_SIZE)
5084 max_list_size = 4 * PAGE_SIZE;
5085 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5086 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5087 while ((sg_list_size + sg_list_increment) <= max_list_size
5088 && (sg_list_size % PAGE_SIZE) != 0) {
5089 bus_size_t new_mod;
5090 bus_size_t best_mod;
5091
5092 sg_list_size += sg_list_increment;
5093 new_mod = sg_list_size % PAGE_SIZE;
5094 best_mod = best_list_size % PAGE_SIZE;
5095 if (new_mod > best_mod || new_mod == 0) {
5096 best_list_size = sg_list_size;
5097 }
5098 }
5099 return (best_list_size);
5100 }
5101
5102 /*
5103 * Allocate a controller structure for a new device
5104 * and perform initial initializion.
5105 */
5106 struct ahd_softc *
5107 ahd_alloc(void *platform_arg, char *name)
5108 {
5109 struct ahd_softc *ahd;
5110
5111 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5112 ahd = kmalloc(sizeof(*ahd), M_DEVBUF, M_INTWAIT);
5113 #else
5114 ahd = device_get_softc((device_t)platform_arg);
5115 #endif
5116 memset(ahd, 0, sizeof(*ahd));
5117 ahd->seep_config = kmalloc(sizeof(*ahd->seep_config),M_DEVBUF,M_INTWAIT);
5118 LIST_INIT(&ahd->pending_scbs);
5119 /* We don't know our unit number until the OSM sets it */
5120 ahd->name = name;
5121 ahd->unit = -1;
5122 ahd->description = NULL;
5123 ahd->bus_description = NULL;
5124 ahd->channel = 'A';
5125 ahd->chip = AHD_NONE;
5126 ahd->features = AHD_FENONE;
5127 ahd->bugs = AHD_BUGNONE;
5128 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5129 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5130 ahd_timer_init(&ahd->reset_timer);
5131 ahd_timer_init(&ahd->stat_timer);
5132 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5133 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5134 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5135 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5136 ahd->int_coalescing_stop_threshold =
5137 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5138
5139 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5140 ahd_free(ahd);
5141 ahd = NULL;
5142 }
5143 #ifdef AHD_DEBUG
5144 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5145 kprintf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5146 ahd_name(ahd), (u_int)sizeof(struct scb),
5147 (u_int)sizeof(struct hardware_scb));
5148 }
5149 #endif
5150 return (ahd);
5151 }
5152
5153 int
5154 ahd_softc_init(struct ahd_softc *ahd)
5155 {
5156
5157 ahd->unpause = 0;
5158 ahd->pause = PAUSE;
5159 return (0);
5160 }
5161
5162 void
5163 ahd_softc_insert(struct ahd_softc *ahd)
5164 {
5165 struct ahd_softc *list_ahd;
5166
5167 #if AHD_PCI_CONFIG > 0
5168 /*
5169 * Second Function PCI devices need to inherit some
5170 * settings from function 0.
5171 */
5172 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5173 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5174 ahd_dev_softc_t list_pci;
5175 ahd_dev_softc_t pci;
5176
5177 list_pci = list_ahd->dev_softc;
5178 pci = ahd->dev_softc;
5179 if (ahd_get_pci_slot(list_pci) == ahd_get_pci_slot(pci)
5180 && ahd_get_pci_bus(list_pci) == ahd_get_pci_bus(pci)) {
5181 struct ahd_softc *master;
5182 struct ahd_softc *slave;
5183
5184 if (ahd_get_pci_function(list_pci) == 0) {
5185 master = list_ahd;
5186 slave = ahd;
5187 } else {
5188 master = ahd;
5189 slave = list_ahd;
5190 }
5191 slave->flags &= ~AHD_BIOS_ENABLED;
5192 slave->flags |=
5193 master->flags & AHD_BIOS_ENABLED;
5194 break;
5195 }
5196 }
5197 }
5198 #endif
5199
5200 /*
5201 * Insertion sort into our list of softcs.
5202 */
5203 list_ahd = TAILQ_FIRST(&ahd_tailq);
5204 while (list_ahd != NULL
5205 && ahd_softc_comp(ahd, list_ahd) <= 0)
5206 list_ahd = TAILQ_NEXT(list_ahd, links);
5207 if (list_ahd != NULL)
5208 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5209 else
5210 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5211 ahd->init_level++;
5212 }
5213
5214 /*
5215 * Verify that the passed in softc pointer is for a
5216 * controller that is still configured.
5217 */
5218 struct ahd_softc *
5219 ahd_find_softc(struct ahd_softc *ahd)
5220 {
5221 struct ahd_softc *list_ahd;
5222
5223 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5224 if (list_ahd == ahd)
5225 return (ahd);
5226 }
5227 return (NULL);
5228 }
5229
5230 void
5231 ahd_set_unit(struct ahd_softc *ahd, int unit)
5232 {
5233 ahd->unit = unit;
5234 }
5235
5236 void
5237 ahd_set_name(struct ahd_softc *ahd, char *name)
5238 {
5239 if (ahd->name != NULL)
5240 kfree(ahd->name, M_DEVBUF);
5241 ahd->name = name;
5242 }
5243
5244 void
5245 ahd_free(struct ahd_softc *ahd)
5246 {
5247 int i;
5248
5249 switch (ahd->init_level) {
5250 default:
5251 case 5:
5252 ahd_shutdown(ahd);
5253 TAILQ_REMOVE(&ahd_tailq, ahd, links);
5254 /* FALLTHROUGH */
5255 case 4:
5256 ahd_dmamap_unload(ahd, ahd->shared_data_dmat,
5257 ahd->shared_data_dmamap);
5258 /* FALLTHROUGH */
5259 case 3:
5260 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5261 ahd->shared_data_dmamap);
5262 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat,
5263 ahd->shared_data_dmamap);
5264 /* FALLTHROUGH */
5265 case 2:
5266 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5267 case 1:
5268 #ifndef __linux__
5269 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat);
5270 #endif
5271 break;
5272 case 0:
5273 break;
5274 }
5275
5276 #ifndef __linux__
5277 ahd_dma_tag_destroy(ahd, ahd->parent_dmat);
5278 #endif
5279 ahd_platform_free(ahd);
5280 ahd_fini_scbdata(ahd);
5281 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5282 struct ahd_tmode_tstate *tstate;
5283
5284 tstate = ahd->enabled_targets[i];
5285 if (tstate != NULL) {
5286 #if AHD_TARGET_MODE
5287 int j;
5288
5289 for (j = 0; j < AHD_NUM_LUNS; j++) {
5290 struct ahd_tmode_lstate *lstate;
5291
5292 lstate = tstate->enabled_luns[j];
5293 if (lstate != NULL) {
5294 xpt_free_path(lstate->path);
5295 kfree(lstate, M_DEVBUF);
5296 }
5297 }
5298 #endif
5299 kfree(tstate, M_DEVBUF);
5300 }
5301 }
5302 #if AHD_TARGET_MODE
5303 if (ahd->black_hole != NULL) {
5304 xpt_free_path(ahd->black_hole->path);
5305 kfree(ahd->black_hole, M_DEVBUF);
5306 }
5307 #endif
5308 if (ahd->name != NULL)
5309 kfree(ahd->name, M_DEVBUF);
5310 if (ahd->seep_config != NULL)
5311 kfree(ahd->seep_config, M_DEVBUF);
5312 if (ahd->saved_stack != NULL)
5313 kfree(ahd->saved_stack, M_DEVBUF);
5314 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5315 kfree(ahd, M_DEVBUF);
5316 #endif
5317 return;
5318 }
5319
5320 void
5321 ahd_shutdown(void *arg)
5322 {
5323 struct ahd_softc *ahd;
5324
5325 ahd = (struct ahd_softc *)arg;
5326
5327 /*
5328 * Stop periodic timer callbacks.
5329 */
5330 ahd_timer_stop(&ahd->reset_timer);
5331 ahd_timer_stop(&ahd->stat_timer);
5332
5333 /* This will reset most registers to 0, but not all */
5334 ahd_reset(ahd, /*reinit*/FALSE);
5335 }
5336
5337 /*
5338 * Reset the controller and record some information about it
5339 * that is only available just after a reset. If "reinit" is
5340 * non-zero, this reset occured after initial configuration
5341 * and the caller requests that the chip be fully reinitialized
5342 * to a runable state. Chip interrupts are *not* enabled after
5343 * a reinitialization. The caller must enable interrupts via
5344 * ahd_intr_enable().
5345 */
5346 int
5347 ahd_reset(struct ahd_softc *ahd, int reinit)
5348 {
5349 u_int sxfrctl1;
5350 int wait;
5351 uint32_t cmd;
5352
5353 /*
5354 * Preserve the value of the SXFRCTL1 register for all channels.
5355 * It contains settings that affect termination and we don't want
5356 * to disturb the integrity of the bus.
5357 */
5358 ahd_pause(ahd);
5359 ahd_update_modes(ahd);
5360 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5361 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5362
5363 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5364 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5365 uint32_t mod_cmd;
5366
5367 /*
5368 * A4 Razor #632
5369 * During the assertion of CHIPRST, the chip
5370 * does not disable its parity logic prior to
5371 * the start of the reset. This may cause a
5372 * parity error to be detected and thus a
5373 * spurious SERR or PERR assertion. Disble
5374 * PERR and SERR responses during the CHIPRST.
5375 */
5376 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5377 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5378 mod_cmd, /*bytes*/2);
5379 }
5380 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5381
5382 /*
5383 * Ensure that the reset has finished. We delay 1000us
5384 * prior to reading the register to make sure the chip
5385 * has sufficiently completed its reset to handle register
5386 * accesses.
5387 */
5388 wait = 1000;
5389 do {
5390 ahd_delay(1000);
5391 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5392
5393 if (wait == 0) {
5394 kprintf("%s: WARNING - Failed chip reset! "
5395 "Trying to initialize anyway.\n", ahd_name(ahd));
5396 }
5397 ahd_outb(ahd, HCNTRL, ahd->pause);
5398
5399 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5400 /*
5401 * Clear any latched PCI error status and restore
5402 * previous SERR and PERR response enables.
5403 */
5404 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5405 0xFF, /*bytes*/1);
5406 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5407 cmd, /*bytes*/2);
5408 }
5409
5410 /*
5411 * Mode should be SCSI after a chip reset, but lets
5412 * set it just to be safe. We touch the MODE_PTR
5413 * register directly so as to bypass the lazy update
5414 * code in ahd_set_modes().
5415 */
5416 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5417 ahd_outb(ahd, MODE_PTR,
5418 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5419
5420 /*
5421 * Restore SXFRCTL1.
5422 *
5423 * We must always initialize STPWEN to 1 before we
5424 * restore the saved values. STPWEN is initialized
5425 * to a tri-state condition which can only be cleared
5426 * by turning it on.
5427 */
5428 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5429 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5430
5431 /* Determine chip configuration */
5432 ahd->features &= ~AHD_WIDE;
5433 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5434 ahd->features |= AHD_WIDE;
5435
5436 /*
5437 * If a recovery action has forced a chip reset,
5438 * re-initialize the chip to our liking.
5439 */
5440 if (reinit != 0)
5441 ahd_chip_init(ahd);
5442
5443 return (0);
5444 }
5445
5446 /*
5447 * Determine the number of SCBs available on the controller
5448 */
5449 int
5450 ahd_probe_scbs(struct ahd_softc *ahd) {
5451 int i;
5452
5453 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5454 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5455 for (i = 0; i < AHD_SCB_MAX; i++) {
5456 int j;
5457
5458 ahd_set_scbptr(ahd, i);
5459 ahd_outw(ahd, SCB_BASE, i);
5460 for (j = 2; j < 64; j++)
5461 ahd_outb(ahd, SCB_BASE+j, 0);
5462 /* Start out life as unallocated (needing an abort) */
5463 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5464 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5465 break;
5466 ahd_set_scbptr(ahd, 0);
5467 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5468 break;
5469 }
5470 return (i);
5471 }
5472
5473 static void
5474 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5475 {
5476 bus_addr_t *baddr;
5477
5478 baddr = (bus_addr_t *)arg;
5479 *baddr = segs->ds_addr;
5480 }
5481
5482 static void
5483 ahd_initialize_hscbs(struct ahd_softc *ahd)
5484 {
5485 int i;
5486
5487 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5488 ahd_set_scbptr(ahd, i);
5489
5490 /* Clear the control byte. */
5491 ahd_outb(ahd, SCB_CONTROL, 0);
5492
5493 /* Set the next pointer */
5494 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5495 }
5496 }
5497
5498 static int
5499 ahd_init_scbdata(struct ahd_softc *ahd)
5500 {
5501 struct scb_data *scb_data;
5502 int i;
5503
5504 scb_data = &ahd->scb_data;
5505 TAILQ_INIT(&scb_data->free_scbs);
5506 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5507 LIST_INIT(&scb_data->free_scb_lists[i]);
5508 LIST_INIT(&scb_data->any_dev_free_scb_list);
5509 SLIST_INIT(&scb_data->hscb_maps);
5510 SLIST_INIT(&scb_data->sg_maps);
5511 SLIST_INIT(&scb_data->sense_maps);
5512
5513 /* Determine the number of hardware SCBs and initialize them */
5514 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5515 if (scb_data->maxhscbs == 0) {
5516 kprintf("%s: No SCB space found\n", ahd_name(ahd));
5517 return (ENXIO);
5518 }
5519
5520 ahd_initialize_hscbs(ahd);
5521
5522 /*
5523 * Create our DMA tags. These tags define the kinds of device
5524 * accessible memory allocations and memory mappings we will
5525 * need to perform during normal operation.
5526 *
5527 * Unless we need to further restrict the allocation, we rely
5528 * on the restrictions of the parent dmat, hence the common
5529 * use of MAXADDR and MAXSIZE.
5530 */
5531
5532 /* DMA tag for our hardware scb structures */
5533 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5534 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5535 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5536 /*highaddr*/BUS_SPACE_MAXADDR,
5537 /*filter*/NULL, /*filterarg*/NULL,
5538 PAGE_SIZE, /*nsegments*/1,
5539 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5540 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5541 goto error_exit;
5542 }
5543
5544 scb_data->init_level++;
5545
5546 /* DMA tag for our S/G structures. */
5547 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5548 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5549 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5550 /*highaddr*/BUS_SPACE_MAXADDR,
5551 /*filter*/NULL, /*filterarg*/NULL,
5552 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5553 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5554 /*flags*/0, &scb_data->sg_dmat) != 0) {
5555 goto error_exit;
5556 }
5557 #ifdef AHD_DEBUG
5558 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5559 kprintf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5560 ahd_sglist_allocsize(ahd));
5561 #endif
5562
5563 scb_data->init_level++;
5564
5565 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5566 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5567 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5568 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5569 /*highaddr*/BUS_SPACE_MAXADDR,
5570 /*filter*/NULL, /*filterarg*/NULL,
5571 PAGE_SIZE, /*nsegments*/1,
5572 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5573 /*flags*/0, &scb_data->sense_dmat) != 0) {
5574 goto error_exit;
5575 }
5576
5577 scb_data->init_level++;
5578
5579 /* Perform initial CCB allocation */
5580 ahd_alloc_scbs(ahd);
5581
5582 if (scb_data->numscbs == 0) {
5583 kprintf("%s: ahd_init_scbdata - "
5584 "Unable to allocate initial scbs\n",
5585 ahd_name(ahd));
5586 goto error_exit;
5587 }
5588
5589 /*
5590 * Note that we were successful
5591 */
5592 return (0);
5593
5594 error_exit:
5595
5596 return (ENOMEM);
5597 }
5598
5599 static struct scb *
5600 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5601 {
5602 struct scb *scb;
5603
5604 /*
5605 * Look on the pending list.
5606 */
5607 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5608 if (SCB_GET_TAG(scb) == tag)
5609 return (scb);
5610 }
5611
5612 /*
5613 * Then on all of the collision free lists.
5614 */
5615 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5616 struct scb *list_scb;
5617
5618 list_scb = scb;
5619 do {
5620 if (SCB_GET_TAG(list_scb) == tag)
5621 return (list_scb);
5622 list_scb = LIST_NEXT(list_scb, collision_links);
5623 } while (list_scb);
5624 }
5625
5626 /*
5627 * And finally on the generic free list.
5628 */
5629 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5630 if (SCB_GET_TAG(scb) == tag)
5631 return (scb);
5632 }
5633
5634 return (NULL);
5635 }
5636
5637 static void
5638 ahd_fini_scbdata(struct ahd_softc *ahd)
5639 {
5640 struct scb_data *scb_data;
5641
5642 scb_data = &ahd->scb_data;
5643 if (scb_data == NULL)
5644 return;
5645
5646 switch (scb_data->init_level) {
5647 default:
5648 case 7:
5649 {
5650 struct map_node *sns_map;
5651
5652 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5653 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5654 ahd_dmamap_unload(ahd, scb_data->sense_dmat,
5655 sns_map->dmamap);
5656 ahd_dmamem_free(ahd, scb_data->sense_dmat,
5657 sns_map->vaddr, sns_map->dmamap);
5658 kfree(sns_map, M_DEVBUF);
5659 }
5660 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat);
5661 /* FALLTHROUGH */
5662 }
5663 case 6:
5664 {
5665 struct map_node *sg_map;
5666
5667 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5668 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5669 ahd_dmamap_unload(ahd, scb_data->sg_dmat,
5670 sg_map->dmamap);
5671 ahd_dmamem_free(ahd, scb_data->sg_dmat,
5672 sg_map->vaddr, sg_map->dmamap);
5673 kfree(sg_map, M_DEVBUF);
5674 }
5675 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat);
5676 /* FALLTHROUGH */
5677 }
5678 case 5:
5679 {
5680 struct map_node *hscb_map;
5681
5682 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5683 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5684 ahd_dmamap_unload(ahd, scb_data->hscb_dmat,
5685 hscb_map->dmamap);
5686 ahd_dmamem_free(ahd, scb_data->hscb_dmat,
5687 hscb_map->vaddr, hscb_map->dmamap);
5688 kfree(hscb_map, M_DEVBUF);
5689 }
5690 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5691 /* FALLTHROUGH */
5692 }
5693 case 4:
5694 case 3:
5695 case 2:
5696 case 1:
5697 case 0:
5698 break;
5699 }
5700 }
5701
5702 /*
5703 * DSP filter Bypass must be enabled until the first selection
5704 * after a change in bus mode (Razor #491 and #493).
5705 */
5706 static void
5707 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5708 {
5709 ahd_mode_state saved_modes;
5710
5711 saved_modes = ahd_save_modes(ahd);
5712 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5713 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5714 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5715 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5716 #ifdef AHD_DEBUG
5717 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5718 kprintf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5719 #endif
5720 ahd_restore_modes(ahd, saved_modes);
5721 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5722 }
5723
5724 static void
5725 ahd_iocell_first_selection(struct ahd_softc *ahd)
5726 {
5727 ahd_mode_state saved_modes;
5728 u_int sblkctl;
5729
5730 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5731 return;
5732 saved_modes = ahd_save_modes(ahd);
5733 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5734 sblkctl = ahd_inb(ahd, SBLKCTL);
5735 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5736 #ifdef AHD_DEBUG
5737 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5738 kprintf("%s: iocell first selection\n", ahd_name(ahd));
5739 #endif
5740 if ((sblkctl & ENAB40) != 0) {
5741 ahd_outb(ahd, DSPDATACTL,
5742 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5743 #ifdef AHD_DEBUG
5744 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5745 kprintf("%s: BYPASS now disabled\n", ahd_name(ahd));
5746 #endif
5747 }
5748 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5749 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5750 ahd_restore_modes(ahd, saved_modes);
5751 ahd->flags |= AHD_HAD_FIRST_SEL;
5752 }
5753
5754 /*************************** SCB Management ***********************************/
5755 static void
5756 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5757 {
5758 struct scb_list *free_list;
5759 struct scb_tailq *free_tailq;
5760 struct scb *first_scb;
5761
5762 scb->flags |= SCB_ON_COL_LIST;
5763 AHD_SET_SCB_COL_IDX(scb, col_idx);
5764 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5765 free_tailq = &ahd->scb_data.free_scbs;
5766 first_scb = LIST_FIRST(free_list);
5767 if (first_scb != NULL) {
5768 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5769 } else {
5770 LIST_INSERT_HEAD(free_list, scb, collision_links);
5771 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5772 }
5773 }
5774
5775 static void
5776 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5777 {
5778 struct scb_list *free_list;
5779 struct scb_tailq *free_tailq;
5780 struct scb *first_scb;
5781 u_int col_idx;
5782
5783 scb->flags &= ~SCB_ON_COL_LIST;
5784 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5785 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5786 free_tailq = &ahd->scb_data.free_scbs;
5787 first_scb = LIST_FIRST(free_list);
5788 if (first_scb == scb) {
5789 struct scb *next_scb;
5790
5791 /*
5792 * Maintain order in the collision free
5793 * lists for fairness if this device has
5794 * other colliding tags active.
5795 */
5796 next_scb = LIST_NEXT(scb, collision_links);
5797 if (next_scb != NULL) {
5798 TAILQ_INSERT_AFTER(free_tailq, scb,
5799 next_scb, links.tqe);
5800 }
5801 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5802 }
5803 LIST_REMOVE(scb, collision_links);
5804 }
5805
5806 /*
5807 * Get a free scb. If there are none, see if we can allocate a new SCB.
5808 */
5809 struct scb *
5810 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5811 {
5812 struct scb *scb;
5813 int tries;
5814
5815 tries = 0;
5816 look_again:
5817 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5818 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5819 ahd_rem_col_list(ahd, scb);
5820 goto found;
5821 }
5822 }
5823 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5824
5825 if (tries++ != 0)
5826 return (NULL);
5827 ahd_alloc_scbs(ahd);
5828 goto look_again;
5829 }
5830 LIST_REMOVE(scb, links.le);
5831 if (col_idx != AHD_NEVER_COL_IDX
5832 && (scb->col_scb != NULL)
5833 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5834 LIST_REMOVE(scb->col_scb, links.le);
5835 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5836 }
5837 found:
5838 scb->flags |= SCB_ACTIVE;
5839 return (scb);
5840 }
5841
5842 /*
5843 * Return an SCB resource to the free list.
5844 */
5845 void
5846 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5847 {
5848
5849 /* Clean up for the next user */
5850 scb->flags = SCB_FLAG_NONE;
5851 scb->hscb->control = 0;
5852 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5853
5854 if (scb->col_scb == NULL) {
5855
5856 /*
5857 * No collision possible. Just free normally.
5858 */
5859 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5860 scb, links.le);
5861 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5862
5863 /*
5864 * The SCB we might have collided with is on
5865 * a free collision list. Put both SCBs on
5866 * the generic list.
5867 */
5868 ahd_rem_col_list(ahd, scb->col_scb);
5869 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5870 scb, links.le);
5871 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5872 scb->col_scb, links.le);
5873 } else if ((scb->col_scb->flags
5874 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
5875 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
5876
5877 /*
5878 * The SCB we might collide with on the next allocation
5879 * is still active in a non-packetized, tagged, context.
5880 * Put us on the SCB collision list.
5881 */
5882 ahd_add_col_list(ahd, scb,
5883 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
5884 } else {
5885 /*
5886 * The SCB we might collide with on the next allocation
5887 * is either active in a packetized context, or free.
5888 * Since we can't collide, put this SCB on the generic
5889 * free list.
5890 */
5891 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5892 scb, links.le);
5893 }
5894
5895 ahd_platform_scb_free(ahd, scb);
5896 }
5897
5898 void
5899 ahd_alloc_scbs(struct ahd_softc *ahd)
5900 {
5901 struct scb_data *scb_data;
5902 struct scb *next_scb;
5903 struct hardware_scb *hscb;
5904 struct map_node *hscb_map;
5905 struct map_node *sg_map;
5906 struct map_node *sense_map;
5907 uint8_t *segs;
5908 uint8_t *sense_data;
5909 bus_addr_t hscb_busaddr;
5910 bus_addr_t sg_busaddr;
5911 bus_addr_t sense_busaddr;
5912 int newcount;
5913 int i;
5914
5915 scb_data = &ahd->scb_data;
5916 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
5917 /* Can't allocate any more */
5918 return;
5919
5920 if (scb_data->scbs_left != 0) {
5921 int offset;
5922
5923 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
5924 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
5925 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
5926 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb));
5927 } else {
5928 hscb_map = kmalloc(sizeof(*hscb_map), M_DEVBUF, M_INTWAIT);
5929
5930 /* Allocate the next batch of hardware SCBs */
5931 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat,
5932 (void **)&hscb_map->vaddr,
5933 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
5934 kfree(hscb_map, M_DEVBUF);
5935 return;
5936 }
5937
5938 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
5939
5940 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
5941 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
5942 &hscb_map->physaddr, /*flags*/0);
5943
5944 hscb = (struct hardware_scb *)hscb_map->vaddr;
5945 hscb_busaddr = hscb_map->physaddr;
5946 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
5947 }
5948
5949 if (scb_data->sgs_left != 0) {
5950 int offset;
5951
5952 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
5953 - scb_data->sgs_left) * ahd_sglist_size(ahd);
5954 sg_map = SLIST_FIRST(&scb_data->sg_maps);
5955 segs = sg_map->vaddr + offset;
5956 sg_busaddr = sg_map->physaddr + offset;
5957 } else {
5958 sg_map = kmalloc(sizeof(*sg_map), M_DEVBUF, M_INTWAIT);
5959
5960 /* Allocate the next batch of S/G lists */
5961 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat,
5962 (void **)&sg_map->vaddr,
5963 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
5964 kfree(sg_map, M_DEVBUF);
5965 return;
5966 }
5967
5968 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
5969
5970 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
5971 sg_map->vaddr, ahd_sglist_allocsize(ahd),
5972 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0);
5973
5974 segs = sg_map->vaddr;
5975 sg_busaddr = sg_map->physaddr;
5976 scb_data->sgs_left =
5977 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
5978 #ifdef AHD_DEBUG
5979 if (ahd_debug & AHD_SHOW_MEMORY)
5980 kprintf("Mapped SG data\n");
5981 #endif
5982 }
5983
5984 if (scb_data->sense_left != 0) {
5985 int offset;
5986
5987 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
5988 sense_map = SLIST_FIRST(&scb_data->sense_maps);
5989 sense_data = sense_map->vaddr + offset;
5990 sense_busaddr = sense_map->physaddr + offset;
5991 } else {
5992 sense_map = kmalloc(sizeof(*sense_map), M_DEVBUF, M_INTWAIT);
5993
5994 /* Allocate the next batch of sense buffers */
5995 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat,
5996 (void **)&sense_map->vaddr,
5997 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
5998 kfree(sense_map, M_DEVBUF);
5999 return;
6000 }
6001
6002 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6003
6004 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6005 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6006 &sense_map->physaddr, /*flags*/0);
6007
6008 sense_data = sense_map->vaddr;
6009 sense_busaddr = sense_map->physaddr;
6010 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6011 #ifdef AHD_DEBUG
6012 if (ahd_debug & AHD_SHOW_MEMORY)
6013 kprintf("Mapped sense data\n");
6014 #endif
6015 }
6016
6017 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6018 newcount = MIN(newcount, scb_data->sgs_left);
6019 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6020 scb_data->sense_left -= newcount;
6021 scb_data->scbs_left -= newcount;
6022 scb_data->sgs_left -= newcount;
6023 for (i = 0; i < newcount; i++) {
6024 u_int col_tag;
6025
6026 struct scb_platform_data *pdata;
6027 #ifndef __linux__
6028 int error;
6029 #endif
6030 next_scb = kmalloc(sizeof(*next_scb), M_DEVBUF, M_INTWAIT);
6031 pdata = kmalloc(sizeof(*pdata), M_DEVBUF, M_INTWAIT);
6032 next_scb->platform_data = pdata;
6033 next_scb->hscb_map = hscb_map;
6034 next_scb->sg_map = sg_map;
6035 next_scb->sense_map = sense_map;
6036 next_scb->sg_list = segs;
6037 next_scb->sense_data = sense_data;
6038 next_scb->sense_busaddr = sense_busaddr;
6039 memset(hscb, 0, sizeof(*hscb));
6040 next_scb->hscb = hscb;
6041 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr);
6042
6043 /*
6044 * The sequencer always starts with the second entry.
6045 * The first entry is embedded in the scb.
6046 */
6047 next_scb->sg_list_busaddr = sg_busaddr;
6048 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6049 next_scb->sg_list_busaddr
6050 += sizeof(struct ahd_dma64_seg);
6051 else
6052 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6053 next_scb->ahd_softc = ahd;
6054 next_scb->flags = SCB_FLAG_NONE;
6055 #ifndef __linux__
6056 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6057 &next_scb->dmamap);
6058 if (error != 0) {
6059 kfree(next_scb, M_DEVBUF);
6060 kfree(pdata, M_DEVBUF);
6061 break;
6062 }
6063 #endif
6064 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs);
6065 col_tag = scb_data->numscbs ^ 0x100;
6066 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6067 if (next_scb->col_scb != NULL)
6068 next_scb->col_scb->col_scb = next_scb;
6069 ahd_free_scb(ahd, next_scb);
6070 hscb++;
6071 hscb_busaddr += sizeof(*hscb);
6072 segs += ahd_sglist_size(ahd);
6073 sg_busaddr += ahd_sglist_size(ahd);
6074 sense_data += AHD_SENSE_BUFSIZE;
6075 sense_busaddr += AHD_SENSE_BUFSIZE;
6076 scb_data->numscbs++;
6077 }
6078 }
6079
6080 void
6081 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6082 {
6083 const char *speed;
6084 const char *type;
6085 int len;
6086
6087 len = ksprintf(buf, "%s: ",
6088 ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6089 buf += len;
6090
6091 speed = "Ultra320 ";
6092 if ((ahd->features & AHD_WIDE) != 0) {
6093 type = "Wide ";
6094 } else {
6095 type = "Single ";
6096 }
6097 len = ksprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6098 speed, type, ahd->channel, ahd->our_id);
6099 buf += len;
6100
6101 ksprintf(buf, "%s, %d SCBs", ahd->bus_description,
6102 ahd->scb_data.maxhscbs);
6103 }
6104
6105 static const char *channel_strings[] = {
6106 "Primary Low",
6107 "Primary High",
6108 "Secondary Low",
6109 "Secondary High"
6110 };
6111
6112 static const char *termstat_strings[] = {
6113 "Terminated Correctly",
6114 "Over Terminated",
6115 "Under Terminated",
6116 "Not Configured"
6117 };
6118
6119 /*
6120 * Start the board, ready for normal operation
6121 */
6122 int
6123 ahd_init(struct ahd_softc *ahd)
6124 {
6125 uint8_t *base_vaddr;
6126 uint8_t *next_vaddr;
6127 bus_addr_t next_baddr;
6128 size_t driver_data_size;
6129 int i;
6130 int error;
6131 u_int warn_user;
6132 uint8_t current_sensing;
6133 uint8_t fstat;
6134
6135 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6136
6137 ahd->stack_size = ahd_probe_stack_size(ahd);
6138 ahd->saved_stack = kmalloc(ahd->stack_size * sizeof(uint16_t),
6139 M_DEVBUF, M_WAITOK);
6140
6141 /*
6142 * Verify that the compiler hasn't over-agressively
6143 * padded important structures.
6144 */
6145 if (sizeof(struct hardware_scb) != 64)
6146 panic("Hardware SCB size is incorrect");
6147
6148 #ifdef AHD_DEBUG
6149 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6150 ahd->flags |= AHD_SEQUENCER_DEBUG;
6151 #endif
6152
6153 /*
6154 * Default to allowing initiator operations.
6155 */
6156 ahd->flags |= AHD_INITIATORROLE;
6157
6158 /*
6159 * Only allow target mode features if this unit has them enabled.
6160 */
6161 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6162 ahd->features &= ~AHD_TARGETMODE;
6163
6164 #ifndef __linux__
6165 /* DMA tag for mapping buffers into device visible space. */
6166 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6167 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6168 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6169 ? (bus_addr_t)0x7FFFFFFFFFULL
6170 : BUS_SPACE_MAXADDR_32BIT,
6171 /*highaddr*/BUS_SPACE_MAXADDR,
6172 /*filter*/NULL, /*filterarg*/NULL,
6173 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6174 /*nsegments*/AHD_NSEG,
6175 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6176 /*flags*/BUS_DMA_ALLOCNOW,
6177 &ahd->buffer_dmat) != 0) {
6178 return (ENOMEM);
6179 }
6180 #endif
6181
6182 ahd->init_level++;
6183
6184 /*
6185 * DMA tag for our command fifos and other data in system memory
6186 * the card's sequencer must be able to access. For initiator
6187 * roles, we need to allocate space for the qoutfifo. When providing
6188 * for the target mode role, we must additionally provide space for
6189 * the incoming target command fifo.
6190 */
6191 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t)
6192 + sizeof(struct hardware_scb);
6193 if ((ahd->features & AHD_TARGETMODE) != 0)
6194 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6195 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6196 driver_data_size += PKT_OVERRUN_BUFSIZE;
6197 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6198 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6199 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6200 /*highaddr*/BUS_SPACE_MAXADDR,
6201 /*filter*/NULL, /*filterarg*/NULL,
6202 driver_data_size,
6203 /*nsegments*/1,
6204 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6205 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6206 return (ENOMEM);
6207 }
6208
6209 ahd->init_level++;
6210
6211 /* Allocation of driver data */
6212 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat,
6213 (void **)&base_vaddr,
6214 BUS_DMA_NOWAIT, &ahd->shared_data_dmamap) != 0) {
6215 return (ENOMEM);
6216 }
6217
6218 ahd->init_level++;
6219
6220 /* And permanently map it in */
6221 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap,
6222 base_vaddr, driver_data_size, ahd_dmamap_cb,
6223 &ahd->shared_data_busaddr, /*flags*/0);
6224 ahd->qoutfifo = (uint16_t *)base_vaddr;
6225 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6226 next_baddr = ahd->shared_data_busaddr + AHD_QOUT_SIZE*sizeof(uint16_t);
6227 if ((ahd->features & AHD_TARGETMODE) != 0) {
6228 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6229 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6230 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6231 }
6232
6233 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6234 ahd->overrun_buf = next_vaddr;
6235 next_vaddr += PKT_OVERRUN_BUFSIZE;
6236 next_baddr += PKT_OVERRUN_BUFSIZE;
6237 }
6238
6239 /*
6240 * We need one SCB to serve as the "next SCB". Since the
6241 * tag identifier in this SCB will never be used, there is
6242 * no point in using a valid HSCB tag from an SCB pulled from
6243 * the standard free pool. So, we allocate this "sentinel"
6244 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6245 */
6246 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6247 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr);
6248
6249 ahd->init_level++;
6250
6251 /* Allocate SCB data now that buffer_dmat is initialized */
6252 if (ahd_init_scbdata(ahd) != 0)
6253 return (ENOMEM);
6254
6255 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6256 ahd->flags &= ~AHD_RESET_BUS_A;
6257
6258 /*
6259 * Before committing these settings to the chip, give
6260 * the OSM one last chance to modify our configuration.
6261 */
6262 ahd_platform_init(ahd);
6263
6264 /* Bring up the chip. */
6265 ahd_chip_init(ahd);
6266
6267 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6268
6269 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6270 goto init_done;
6271
6272 /*
6273 * Verify termination based on current draw and
6274 * warn user if the bus is over/under terminated.
6275 */
6276 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6277 CURSENSE_ENB);
6278 if (error != 0) {
6279 kprintf("%s: current sensing timeout 1\n", ahd_name(ahd));
6280 goto init_done;
6281 }
6282 for (i = 20, fstat = FLX_FSTAT_BUSY;
6283 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6284 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6285 if (error != 0) {
6286 kprintf("%s: current sensing timeout 2\n",
6287 ahd_name(ahd));
6288 goto init_done;
6289 }
6290 }
6291 if (i == 0) {
6292 kprintf("%s: Timedout during current-sensing test\n",
6293 ahd_name(ahd));
6294 goto init_done;
6295 }
6296
6297 /* Latch Current Sensing status. */
6298 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, &current_sensing);
6299 if (error != 0) {
6300 kprintf("%s: current sensing timeout 3\n", ahd_name(ahd));
6301 goto init_done;
6302 }
6303
6304 /* Diable current sensing. */
6305 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6306
6307 #ifdef AHD_DEBUG
6308 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6309 kprintf("%s: current_sensing == 0x%x\n",
6310 ahd_name(ahd), current_sensing);
6311 }
6312 #endif
6313 warn_user = 0;
6314 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6315 u_int term_stat;
6316
6317 term_stat = (current_sensing & FLX_CSTAT_MASK);
6318 switch (term_stat) {
6319 case FLX_CSTAT_OVER:
6320 case FLX_CSTAT_UNDER:
6321 warn_user++;
6322 case FLX_CSTAT_INVALID:
6323 case FLX_CSTAT_OKAY:
6324 if (warn_user == 0 && bootverbose == 0)
6325 break;
6326 kprintf("%s: %s Channel %s\n", ahd_name(ahd),
6327 channel_strings[i], termstat_strings[term_stat]);
6328 break;
6329 }
6330 }
6331 if (warn_user) {
6332 kprintf("%s: WARNING. Termination is not configured correctly.\n"
6333 "%s: WARNING. SCSI bus operations may FAIL.\n",
6334 ahd_name(ahd), ahd_name(ahd));
6335 }
6336 init_done:
6337 ahd_restart(ahd);
6338 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
6339 ahd_stat_timer, ahd);
6340 return (0);
6341 }
6342
6343 /*
6344 * (Re)initialize chip state after a chip reset.
6345 */
6346 static void
6347 ahd_chip_init(struct ahd_softc *ahd)
6348 {
6349 uint32_t busaddr;
6350 u_int sxfrctl1;
6351 u_int scsiseq_template;
6352 u_int wait;
6353 u_int i;
6354 u_int target;
6355
6356 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6357 /*
6358 * Take the LED out of diagnostic mode
6359 */
6360 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6361
6362 /*
6363 * Return HS_MAILBOX to its default value.
6364 */
6365 ahd->hs_mailbox = 0;
6366 ahd_outb(ahd, HS_MAILBOX, 0);
6367
6368 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6369 ahd_outb(ahd, IOWNID, ahd->our_id);
6370 ahd_outb(ahd, TOWNID, ahd->our_id);
6371 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6372 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6373 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6374 && (ahd->seltime != STIMESEL_MIN)) {
6375 /*
6376 * The selection timer duration is twice as long
6377 * as it should be. Halve it by adding "1" to
6378 * the user specified setting.
6379 */
6380 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6381 } else {
6382 sxfrctl1 |= ahd->seltime;
6383 }
6384
6385 ahd_outb(ahd, SXFRCTL0, DFON);
6386 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6387 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6388
6389 /*
6390 * Now that termination is set, wait for up
6391 * to 500ms for our transceivers to settle. If
6392 * the adapter does not have a cable attached,
6393 * the transceivers may never settle, so don't
6394 * complain if we fail here.
6395 */
6396 for (wait = 10000;
6397 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6398 wait--)
6399 ahd_delay(100);
6400
6401 /* Clear any false bus resets due to the transceivers settling */
6402 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6403 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6404
6405 /* Initialize mode specific S/G state. */
6406 for (i = 0; i < 2; i++) {
6407 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6408 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6409 ahd_outb(ahd, SG_STATE, 0);
6410 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6411 ahd_outb(ahd, SEQIMODE,
6412 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6413 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6414 }
6415
6416 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6417 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6418 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6419 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6420 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6421 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6422 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6423 } else {
6424 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6425 }
6426 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6427 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6428 /*
6429 * Do not issue a target abort when a split completion
6430 * error occurs. Let our PCIX interrupt handler deal
6431 * with it instead. H2A4 Razor #625
6432 */
6433 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6434
6435 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6436 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6437
6438 /*
6439 * Tweak IOCELL settings.
6440 */
6441 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6442 for (i = 0; i < NUMDSPS; i++) {
6443 ahd_outb(ahd, DSPSELECT, i);
6444 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6445 }
6446 #ifdef AHD_DEBUG
6447 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6448 kprintf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6449 WRTBIASCTL_HP_DEFAULT);
6450 #endif
6451 }
6452 ahd_setup_iocell_workaround(ahd);
6453
6454 /*
6455 * Enable LQI Manager interrupts.
6456 */
6457 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6458 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6459 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6460 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6461 /*
6462 * An interrupt from LQOBUSFREE is made redundant by the
6463 * BUSFREE interrupt. We choose to have the sequencer catch
6464 * LQOPHCHGINPKT errors manually for the command phase at the
6465 * start of a packetized selection case.
6466 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT);
6467 */
6468 ahd_outb(ahd, LQOMODE1, 0);
6469
6470 /*
6471 * Setup sequencer interrupt handlers.
6472 */
6473 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6474 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6475
6476 /*
6477 * Setup SCB Offset registers.
6478 */
6479 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6480 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6481 pkt_long_lun));
6482 } else {
6483 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6484 }
6485 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6486 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6487 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6488 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6489 shared_data.idata.cdb));
6490 ahd_outb(ahd, QNEXTPTR,
6491 offsetof(struct hardware_scb, next_hscb_busaddr));
6492 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6493 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6494 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6495 ahd_outb(ahd, LUNLEN,
6496 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6497 } else {
6498 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6499 }
6500 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6501 ahd_outb(ahd, MAXCMD, 0xFF);
6502 ahd_outb(ahd, SCBAUTOPTR,
6503 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6504
6505 /* We haven't been enabled for target mode yet. */
6506 ahd_outb(ahd, MULTARGID, 0);
6507 ahd_outb(ahd, MULTARGID + 1, 0);
6508
6509 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6510 /* Initialize the negotiation table. */
6511 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6512 /*
6513 * Clear the spare bytes in the neg table to avoid
6514 * spurious parity errors.
6515 */
6516 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6517 ahd_outb(ahd, NEGOADDR, target);
6518 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6519 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6520 ahd_outb(ahd, ANNEXDAT, 0);
6521 }
6522 }
6523 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6524 struct ahd_devinfo devinfo;
6525 struct ahd_initiator_tinfo *tinfo;
6526 struct ahd_tmode_tstate *tstate;
6527
6528 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6529 target, &tstate);
6530 ahd_compile_devinfo(&devinfo, ahd->our_id,
6531 target, CAM_LUN_WILDCARD,
6532 'A', ROLE_INITIATOR);
6533 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6534 }
6535
6536 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6537 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6538
6539 #if NEEDS_MORE_TESTING
6540 /*
6541 * Always enable abort on incoming L_Qs if this feature is
6542 * supported. We use this to catch invalid SCB references.
6543 */
6544 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6545 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6546 else
6547 #endif
6548 ahd_outb(ahd, LQCTL1, 0);
6549
6550 /* All of our queues are empty */
6551 ahd->qoutfifonext = 0;
6552 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE;
6553 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8);
6554 for (i = 0; i < AHD_QOUT_SIZE; i++)
6555 ahd->qoutfifo[i] = 0;
6556 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6557
6558 ahd->qinfifonext = 0;
6559 for (i = 0; i < AHD_QIN_SIZE; i++)
6560 ahd->qinfifo[i] = SCB_LIST_NULL;
6561
6562 if ((ahd->features & AHD_TARGETMODE) != 0) {
6563 /* All target command blocks start out invalid. */
6564 for (i = 0; i < AHD_TMODE_CMDS; i++)
6565 ahd->targetcmds[i].cmd_valid = 0;
6566 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6567 ahd->tqinfifonext = 1;
6568 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6569 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6570 }
6571
6572 /* Initialize Scratch Ram. */
6573 ahd_outb(ahd, SEQ_FLAGS, 0);
6574 ahd_outb(ahd, SEQ_FLAGS2, 0);
6575
6576 /* We don't have any waiting selections */
6577 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6578 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6579 for (i = 0; i < AHD_NUM_TARGETS; i++)
6580 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6581
6582 /*
6583 * Nobody is waiting to be DMAed into the QOUTFIFO.
6584 */
6585 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6586 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6587 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6588
6589 /*
6590 * The Freeze Count is 0.
6591 */
6592 ahd_outw(ahd, QFREEZE_COUNT, 0);
6593
6594 /*
6595 * Tell the sequencer where it can find our arrays in memory.
6596 */
6597 busaddr = ahd->shared_data_busaddr;
6598 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF);
6599 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF);
6600 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF);
6601 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF);
6602 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF);
6603 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF);
6604 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF);
6605 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF);
6606
6607 /*
6608 * Setup the allowed SCSI Sequences based on operational mode.
6609 * If we are a target, we'll enable select in operations once
6610 * we've had a lun enabled.
6611 */
6612 scsiseq_template = ENAUTOATNP;
6613 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6614 scsiseq_template |= ENRSELI;
6615 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6616
6617 /* There are no busy SCBs yet. */
6618 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6619 int lun;
6620
6621 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6622 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6623 }
6624
6625 /*
6626 * Initialize the group code to command length table.
6627 * Vendor Unique codes are set to 0 so we only capture
6628 * the first byte of the cdb. These can be overridden
6629 * when target mode is enabled.
6630 */
6631 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6632 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6633 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6634 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6635 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6636 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6637 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6638 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6639
6640 /* Tell the sequencer of our initial queue positions */
6641 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6642 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6643 ahd->qinfifonext = 0;
6644 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6645 ahd_set_hescb_qoff(ahd, 0);
6646 ahd_set_snscb_qoff(ahd, 0);
6647 ahd_set_sescb_qoff(ahd, 0);
6648 ahd_set_sdscb_qoff(ahd, 0);
6649
6650 /*
6651 * Tell the sequencer which SCB will be the next one it receives.
6652 */
6653 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6654 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
6655 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
6656 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
6657 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
6658
6659 /*
6660 * Default to coalescing disabled.
6661 */
6662 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6663 ahd_outw(ahd, CMDS_PENDING, 0);
6664 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6665 ahd->int_coalescing_maxcmds,
6666 ahd->int_coalescing_mincmds);
6667 ahd_enable_coalescing(ahd, FALSE);
6668
6669 ahd_loadseq(ahd);
6670 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6671 }
6672
6673 /*
6674 * Setup default device and controller settings.
6675 * This should only be called if our probe has
6676 * determined that no configuration data is available.
6677 */
6678 int
6679 ahd_default_config(struct ahd_softc *ahd)
6680 {
6681 int targ;
6682
6683 ahd->our_id = 7;
6684
6685 /*
6686 * Allocate a tstate to house information for our
6687 * initiator presence on the bus as well as the user
6688 * data for any target mode initiator.
6689 */
6690 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6691 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6692 "Failing attach\n", ahd_name(ahd));
6693 return (ENOMEM);
6694 }
6695
6696 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6697 struct ahd_devinfo devinfo;
6698 struct ahd_initiator_tinfo *tinfo;
6699 struct ahd_tmode_tstate *tstate;
6700 uint16_t target_mask;
6701
6702 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6703 targ, &tstate);
6704 /*
6705 * We support SPC2 and SPI4.
6706 */
6707 tinfo->user.protocol_version = 4;
6708 tinfo->user.transport_version = 4;
6709
6710 target_mask = 0x01 << targ;
6711 ahd->user_discenable |= target_mask;
6712 tstate->discenable |= target_mask;
6713 ahd->user_tagenable |= target_mask;
6714 #ifdef AHD_FORCE_160
6715 tinfo->user.period = AHD_SYNCRATE_DT;
6716 #else
6717 tinfo->user.period = AHD_SYNCRATE_160;
6718 #endif
6719 tinfo->user.offset = MAX_OFFSET;
6720 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6721 | MSG_EXT_PPR_WR_FLOW
6722 | MSG_EXT_PPR_HOLD_MCS
6723 | MSG_EXT_PPR_IU_REQ
6724 | MSG_EXT_PPR_QAS_REQ
6725 | MSG_EXT_PPR_DT_REQ;
6726 if ((ahd->features & AHD_RTI) != 0)
6727 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6728
6729 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6730
6731 /*
6732 * Start out Async/Narrow/Untagged and with
6733 * conservative protocol support.
6734 */
6735 tinfo->goal.protocol_version = 2;
6736 tinfo->goal.transport_version = 2;
6737 tinfo->curr.protocol_version = 2;
6738 tinfo->curr.transport_version = 2;
6739 ahd_compile_devinfo(&devinfo, ahd->our_id,
6740 targ, CAM_LUN_WILDCARD,
6741 'A', ROLE_INITIATOR);
6742 tstate->tagenable &= ~target_mask;
6743 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6744 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6745 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6746 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6747 /*paused*/TRUE);
6748 }
6749 return (0);
6750 }
6751
6752 /*
6753 * Parse device configuration information.
6754 */
6755 int
6756 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6757 {
6758 int targ;
6759 int max_targ;
6760
6761 max_targ = sc->max_targets & CFMAXTARG;
6762 ahd->our_id = sc->brtime_id & CFSCSIID;
6763
6764 /*
6765 * Allocate a tstate to house information for our
6766 * initiator presence on the bus as well as the user
6767 * data for any target mode initiator.
6768 */
6769 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6770 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6771 "Failing attach\n", ahd_name(ahd));
6772 return (ENOMEM);
6773 }
6774
6775 for (targ = 0; targ < max_targ; targ++) {
6776 struct ahd_devinfo devinfo;
6777 struct ahd_initiator_tinfo *tinfo;
6778 struct ahd_transinfo *user_tinfo;
6779 struct ahd_tmode_tstate *tstate;
6780 uint16_t target_mask;
6781
6782 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6783 targ, &tstate);
6784 user_tinfo = &tinfo->user;
6785
6786 /*
6787 * We support SPC2 and SPI4.
6788 */
6789 tinfo->user.protocol_version = 4;
6790 tinfo->user.transport_version = 4;
6791
6792 target_mask = 0x01 << targ;
6793 ahd->user_discenable &= ~target_mask;
6794 tstate->discenable &= ~target_mask;
6795 ahd->user_tagenable &= ~target_mask;
6796 if (sc->device_flags[targ] & CFDISC) {
6797 tstate->discenable |= target_mask;
6798 ahd->user_discenable |= target_mask;
6799 ahd->user_tagenable |= target_mask;
6800 } else {
6801 /*
6802 * Cannot be packetized without disconnection.
6803 */
6804 sc->device_flags[targ] &= ~CFPACKETIZED;
6805 }
6806
6807 user_tinfo->ppr_options = 0;
6808 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6809 if (user_tinfo->period < CFXFER_ASYNC) {
6810 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6811 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6812 user_tinfo->offset = MAX_OFFSET;
6813 } else {
6814 user_tinfo->offset = 0;
6815 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6816 }
6817 #ifdef AHD_FORCE_160
6818 if (user_tinfo->period <= AHD_SYNCRATE_160)
6819 user_tinfo->period = AHD_SYNCRATE_DT;
6820 #endif
6821
6822 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6823 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6824 | MSG_EXT_PPR_WR_FLOW
6825 | MSG_EXT_PPR_HOLD_MCS
6826 | MSG_EXT_PPR_IU_REQ;
6827 if ((ahd->features & AHD_RTI) != 0)
6828 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6829 }
6830
6831 if ((sc->device_flags[targ] & CFQAS) != 0)
6832 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6833
6834 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6835 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6836 else
6837 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6838 #ifdef AHD_DEBUG
6839 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6840 kprintf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6841 user_tinfo->period, user_tinfo->offset,
6842 user_tinfo->ppr_options);
6843 #endif
6844 /*
6845 * Start out Async/Narrow/Untagged and with
6846 * conservative protocol support.
6847 */
6848 tstate->tagenable &= ~target_mask;
6849 tinfo->goal.protocol_version = 2;
6850 tinfo->goal.transport_version = 2;
6851 tinfo->curr.protocol_version = 2;
6852 tinfo->curr.transport_version = 2;
6853 ahd_compile_devinfo(&devinfo, ahd->our_id,
6854 targ, CAM_LUN_WILDCARD,
6855 'A', ROLE_INITIATOR);
6856 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6857 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6858 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6859 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6860 /*paused*/TRUE);
6861 }
6862
6863 ahd->flags &= ~AHD_SPCHK_ENB_A;
6864 if (sc->bios_control & CFSPARITY)
6865 ahd->flags |= AHD_SPCHK_ENB_A;
6866
6867 ahd->flags &= ~AHD_RESET_BUS_A;
6868 if (sc->bios_control & CFRESETB)
6869 ahd->flags |= AHD_RESET_BUS_A;
6870
6871 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
6872 if (sc->bios_control & CFEXTEND)
6873 ahd->flags |= AHD_EXTENDED_TRANS_A;
6874
6875 ahd->flags &= ~AHD_BIOS_ENABLED;
6876 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
6877 ahd->flags |= AHD_BIOS_ENABLED;
6878
6879 ahd->flags &= ~AHD_STPWLEVEL_A;
6880 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
6881 ahd->flags |= AHD_STPWLEVEL_A;
6882
6883 return (0);
6884 }
6885
6886 /*
6887 * Parse device configuration information.
6888 */
6889 int
6890 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
6891 {
6892 int error;
6893
6894 error = ahd_verify_vpd_cksum(vpd);
6895 if (error == 0)
6896 return (EINVAL);
6897 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
6898 ahd->flags |= AHD_BOOT_CHANNEL;
6899 return (0);
6900 }
6901
6902 void
6903 ahd_intr_enable(struct ahd_softc *ahd, int enable)
6904 {
6905 u_int hcntrl;
6906
6907 hcntrl = ahd_inb(ahd, HCNTRL);
6908 hcntrl &= ~INTEN;
6909 ahd->pause &= ~INTEN;
6910 ahd->unpause &= ~INTEN;
6911 if (enable) {
6912 hcntrl |= INTEN;
6913 ahd->pause |= INTEN;
6914 ahd->unpause |= INTEN;
6915 }
6916 ahd_outb(ahd, HCNTRL, hcntrl);
6917 }
6918
6919 void
6920 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
6921 u_int mincmds)
6922 {
6923 if (timer > AHD_TIMER_MAX_US)
6924 timer = AHD_TIMER_MAX_US;
6925 ahd->int_coalescing_timer = timer;
6926
6927 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
6928 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
6929 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
6930 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
6931 ahd->int_coalescing_maxcmds = maxcmds;
6932 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
6933 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
6934 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
6935 }
6936
6937 void
6938 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
6939 {
6940
6941 ahd->hs_mailbox &= ~ENINT_COALESCE;
6942 if (enable)
6943 ahd->hs_mailbox |= ENINT_COALESCE;
6944 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
6945 ahd_flush_device_writes(ahd);
6946 ahd_run_qoutfifo(ahd);
6947 }
6948
6949 /*
6950 * Ensure that the card is paused in a location
6951 * outside of all critical sections and that all
6952 * pending work is completed prior to returning.
6953 * This routine should only be called from outside
6954 * an interrupt context.
6955 */
6956 void
6957 ahd_pause_and_flushwork(struct ahd_softc *ahd)
6958 {
6959 u_int intstat;
6960 u_int maxloops;
6961 u_int qfreeze_cnt;
6962
6963 maxloops = 1000;
6964 ahd->flags |= AHD_ALL_INTERRUPTS;
6965 ahd_pause(ahd);
6966 /*
6967 * Increment the QFreeze Count so that the sequencer
6968 * will not start new selections. We do this only
6969 * until we are safely paused without further selections
6970 * pending.
6971 */
6972 ahd_outw(ahd, QFREEZE_COUNT, ahd_inw(ahd, QFREEZE_COUNT) + 1);
6973 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
6974 do {
6975 struct scb *waiting_scb;
6976
6977 ahd_unpause(ahd);
6978 ahd_intr(ahd);
6979 ahd_pause(ahd);
6980 ahd_clear_critical_section(ahd);
6981 intstat = ahd_inb(ahd, INTSTAT);
6982 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6983 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
6984 ahd_outb(ahd, SCSISEQ0,
6985 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
6986 /*
6987 * In the non-packetized case, the sequencer (for Rev A),
6988 * relies on ENSELO remaining set after SELDO. The hardware
6989 * auto-clears ENSELO in the packetized case.
6990 */
6991 waiting_scb = ahd_lookup_scb(ahd,
6992 ahd_inw(ahd, WAITING_TID_HEAD));
6993 if (waiting_scb != NULL
6994 && (waiting_scb->flags & SCB_PACKETIZED) == 0
6995 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)
6996 ahd_outb(ahd, SCSISEQ0,
6997 ahd_inb(ahd, SCSISEQ0) | ENSELO);
6998 } while (--maxloops
6999 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7000 && ((intstat & INT_PEND) != 0
7001 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7002 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7003
7004 if (maxloops == 0) {
7005 kprintf("Infinite interrupt loop, INTSTAT = %x",
7006 ahd_inb(ahd, INTSTAT));
7007 }
7008 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT);
7009 if (qfreeze_cnt == 0) {
7010 kprintf("%s: ahd_pause_and_flushwork with 0 qfreeze count!\n",
7011 ahd_name(ahd));
7012 } else {
7013 qfreeze_cnt--;
7014 }
7015 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt);
7016 if (qfreeze_cnt == 0)
7017 ahd_outb(ahd, SEQ_FLAGS2,
7018 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN);
7019
7020 ahd_flush_qoutfifo(ahd);
7021
7022 ahd_platform_flushwork(ahd);
7023 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7024 }
7025
7026 int
7027 ahd_suspend(struct ahd_softc *ahd)
7028 {
7029
7030 ahd_pause_and_flushwork(ahd);
7031
7032 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7033 ahd_unpause(ahd);
7034 return (EBUSY);
7035 }
7036 ahd_shutdown(ahd);
7037 return (0);
7038 }
7039
7040 int
7041 ahd_resume(struct ahd_softc *ahd)
7042 {
7043
7044 ahd_reset(ahd, /*reinit*/TRUE);
7045 ahd_intr_enable(ahd, TRUE);
7046 ahd_restart(ahd);
7047 return (0);
7048 }
7049
7050 /************************** Busy Target Table *********************************/
7051 /*
7052 * Set SCBPTR to the SCB that contains the busy
7053 * table entry for TCL. Return the offset into
7054 * the SCB that contains the entry for TCL.
7055 * saved_scbid is dereferenced and set to the
7056 * scbid that should be restored once manipualtion
7057 * of the TCL entry is complete.
7058 */
7059 static __inline u_int
7060 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7061 {
7062 /*
7063 * Index to the SCB that contains the busy entry.
7064 */
7065 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7066 *saved_scbid = ahd_get_scbptr(ahd);
7067 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7068 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7069
7070 /*
7071 * And now calculate the SCB offset to the entry.
7072 * Each entry is 2 bytes wide, hence the
7073 * multiplication by 2.
7074 */
7075 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7076 }
7077
7078 /*
7079 * Return the untagged transaction id for a given target/channel lun.
7080 */
7081 u_int
7082 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7083 {
7084 u_int scbid;
7085 u_int scb_offset;
7086 u_int saved_scbptr;
7087
7088 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7089 scbid = ahd_inw_scbram(ahd, scb_offset);
7090 ahd_set_scbptr(ahd, saved_scbptr);
7091 return (scbid);
7092 }
7093
7094 void
7095 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7096 {
7097 u_int scb_offset;
7098 u_int saved_scbptr;
7099
7100 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7101 ahd_outw(ahd, scb_offset, scbid);
7102 ahd_set_scbptr(ahd, saved_scbptr);
7103 }
7104
7105 /************************** SCB and SCB queue management **********************/
7106 int
7107 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7108 char channel, int lun, u_int tag, role_t role)
7109 {
7110 int targ = SCB_GET_TARGET(ahd, scb);
7111 char chan = SCB_GET_CHANNEL(ahd, scb);
7112 int slun = SCB_GET_LUN(scb);
7113 int match;
7114
7115 match = ((chan == channel) || (channel == ALL_CHANNELS));
7116 if (match != 0)
7117 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7118 if (match != 0)
7119 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7120 if (match != 0) {
7121 #if AHD_TARGET_MODE
7122 int group;
7123
7124 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7125 if (role == ROLE_INITIATOR) {
7126 match = (group != XPT_FC_GROUP_TMODE)
7127 && ((tag == SCB_GET_TAG(scb))
7128 || (tag == SCB_LIST_NULL));
7129 } else if (role == ROLE_TARGET) {
7130 match = (group == XPT_FC_GROUP_TMODE)
7131 && ((tag == scb->io_ctx->csio.tag_id)
7132 || (tag == SCB_LIST_NULL));
7133 }
7134 #else /* !AHD_TARGET_MODE */
7135 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7136 #endif /* AHD_TARGET_MODE */
7137 }
7138
7139 return match;
7140 }
7141
7142 void
7143 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7144 {
7145 int target;
7146 char channel;
7147 int lun;
7148
7149 target = SCB_GET_TARGET(ahd, scb);
7150 lun = SCB_GET_LUN(scb);
7151 channel = SCB_GET_CHANNEL(ahd, scb);
7152
7153 ahd_search_qinfifo(ahd, target, channel, lun,
7154 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7155 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7156
7157 ahd_platform_freeze_devq(ahd, scb);
7158 }
7159
7160 void
7161 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7162 {
7163 struct scb *prev_scb;
7164 ahd_mode_state saved_modes;
7165
7166 saved_modes = ahd_save_modes(ahd);
7167 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7168 prev_scb = NULL;
7169 if (ahd_qinfifo_count(ahd) != 0) {
7170 u_int prev_tag;
7171 u_int prev_pos;
7172
7173 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7174 prev_tag = ahd->qinfifo[prev_pos];
7175 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7176 }
7177 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7178 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7179 ahd_restore_modes(ahd, saved_modes);
7180 }
7181
7182 static void
7183 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7184 struct scb *scb)
7185 {
7186 if (prev_scb == NULL) {
7187 uint32_t busaddr;
7188
7189 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr);
7190 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
7191 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
7192 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
7193 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
7194 } else {
7195 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7196 ahd_sync_scb(ahd, prev_scb,
7197 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7198 }
7199 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7200 ahd->qinfifonext++;
7201 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7202 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7203 }
7204
7205 static int
7206 ahd_qinfifo_count(struct ahd_softc *ahd)
7207 {
7208 u_int qinpos;
7209 u_int wrap_qinpos;
7210 u_int wrap_qinfifonext;
7211
7212 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7213 qinpos = ahd_get_snscb_qoff(ahd);
7214 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7215 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7216 if (wrap_qinfifonext >= wrap_qinpos)
7217 return (wrap_qinfifonext - wrap_qinpos);
7218 else
7219 return (wrap_qinfifonext
7220 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7221 }
7222
7223 void
7224 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7225 {
7226 struct scb *scb;
7227 ahd_mode_state saved_modes;
7228 u_int pending_cmds;
7229
7230 saved_modes = ahd_save_modes(ahd);
7231 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7232
7233 /*
7234 * Don't count any commands as outstanding that the
7235 * sequencer has already marked for completion.
7236 */
7237 ahd_flush_qoutfifo(ahd);
7238
7239 pending_cmds = 0;
7240 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7241 pending_cmds++;
7242 }
7243 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7244 ahd_restore_modes(ahd, saved_modes);
7245 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7246 }
7247
7248 int
7249 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7250 int lun, u_int tag, role_t role, uint32_t status,
7251 ahd_search_action action)
7252 {
7253 struct scb *scb;
7254 struct scb *prev_scb;
7255 ahd_mode_state saved_modes;
7256 u_int qinstart;
7257 u_int qinpos;
7258 u_int qintail;
7259 u_int tid_next;
7260 u_int tid_prev;
7261 u_int scbid;
7262 u_int savedscbptr;
7263 uint32_t busaddr;
7264 int found;
7265 int targets;
7266
7267 /* Must be in CCHAN mode */
7268 saved_modes = ahd_save_modes(ahd);
7269 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7270
7271 /*
7272 * Halt any pending SCB DMA. The sequencer will reinitiate
7273 * this dma if the qinfifo is not empty once we unpause.
7274 */
7275 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7276 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7277 ahd_outb(ahd, CCSCBCTL,
7278 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7279 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7280 ;
7281 }
7282 /* Determine sequencer's position in the qinfifo. */
7283 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7284 qinstart = ahd_get_snscb_qoff(ahd);
7285 qinpos = AHD_QIN_WRAP(qinstart);
7286 found = 0;
7287 prev_scb = NULL;
7288
7289 if (action == SEARCH_PRINT) {
7290 kprintf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7291 qinstart, ahd->qinfifonext);
7292 }
7293
7294 /*
7295 * Start with an empty queue. Entries that are not chosen
7296 * for removal will be re-added to the queue as we go.
7297 */
7298 ahd->qinfifonext = qinstart;
7299 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7300 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF);
7301 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF);
7302 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF);
7303 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF);
7304
7305 while (qinpos != qintail) {
7306 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7307 if (scb == NULL) {
7308 kprintf("qinpos = %d, SCB index = %d\n",
7309 qinpos, ahd->qinfifo[qinpos]);
7310 panic("Loop 1\n");
7311 }
7312
7313 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7314 /*
7315 * We found an scb that needs to be acted on.
7316 */
7317 found++;
7318 switch (action) {
7319 case SEARCH_COMPLETE:
7320 {
7321 cam_status ostat;
7322 cam_status cstat;
7323
7324 ostat = ahd_get_transaction_status(scb);
7325 if (ostat == CAM_REQ_INPROG)
7326 ahd_set_transaction_status(scb,
7327 status);
7328 cstat = ahd_get_transaction_status(scb);
7329 if (cstat != CAM_REQ_CMP)
7330 ahd_freeze_scb(scb);
7331 if ((scb->flags & SCB_ACTIVE) == 0)
7332 kprintf("Inactive SCB in qinfifo\n");
7333 ahd_done(ahd, scb);
7334
7335 /* FALLTHROUGH */
7336 }
7337 case SEARCH_REMOVE:
7338 break;
7339 case SEARCH_PRINT:
7340 kprintf(" 0x%x", ahd->qinfifo[qinpos]);
7341 /* FALLTHROUGH */
7342 case SEARCH_COUNT:
7343 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7344 prev_scb = scb;
7345 break;
7346 }
7347 } else {
7348 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7349 prev_scb = scb;
7350 }
7351 qinpos = AHD_QIN_WRAP(qinpos+1);
7352 }
7353
7354 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7355
7356 if (action == SEARCH_PRINT)
7357 kprintf("\nWAITING_TID_QUEUES:\n");
7358
7359 /*
7360 * Search waiting for selection lists. We traverse the
7361 * list of "their ids" waiting for selection and, if
7362 * appropriate, traverse the SCBs of each "their id"
7363 * looking for matches.
7364 */
7365 savedscbptr = ahd_get_scbptr(ahd);
7366 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7367 tid_prev = SCB_LIST_NULL;
7368 targets = 0;
7369 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7370 u_int tid_head;
7371
7372 /*
7373 * We limit based on the number of SCBs since
7374 * MK_MESSAGE SCBs are not in the per-tid lists.
7375 */
7376 targets++;
7377 if (targets > AHD_SCB_MAX) {
7378 panic("TID LIST LOOP");
7379 }
7380 if (scbid >= ahd->scb_data.numscbs) {
7381 kprintf("%s: Waiting TID List inconsistency. "
7382 "SCB index == 0x%x, yet numscbs == 0x%x.",
7383 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7384 ahd_dump_card_state(ahd);
7385 panic("for safety");
7386 }
7387 scb = ahd_lookup_scb(ahd, scbid);
7388 if (scb == NULL) {
7389 kprintf("%s: SCB = 0x%x Not Active!\n",
7390 ahd_name(ahd), scbid);
7391 panic("Waiting TID List traversal\n");
7392 }
7393 ahd_set_scbptr(ahd, scbid);
7394 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7395 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7396 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7397 tid_prev = scbid;
7398 continue;
7399 }
7400
7401 /*
7402 * We found a list of scbs that needs to be searched.
7403 */
7404 if (action == SEARCH_PRINT)
7405 kprintf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7406 tid_head = scbid;
7407 found += ahd_search_scb_list(ahd, target, channel,
7408 lun, tag, role, status,
7409 action, &tid_head,
7410 SCB_GET_TARGET(ahd, scb));
7411 if (tid_head != scbid)
7412 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7413 if (!SCBID_IS_NULL(tid_head))
7414 tid_prev = tid_head;
7415 if (action == SEARCH_PRINT)
7416 kprintf(")\n");
7417 }
7418 ahd_set_scbptr(ahd, savedscbptr);
7419 ahd_restore_modes(ahd, saved_modes);
7420 return (found);
7421 }
7422
7423 static int
7424 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7425 int lun, u_int tag, role_t role, uint32_t status,
7426 ahd_search_action action, u_int *list_head, u_int tid)
7427 {
7428 struct scb *scb;
7429 u_int scbid;
7430 u_int next;
7431 u_int prev;
7432 int found;
7433
7434 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7435 found = 0;
7436 prev = SCB_LIST_NULL;
7437 next = *list_head;
7438 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7439 if (scbid >= ahd->scb_data.numscbs) {
7440 kprintf("%s:SCB List inconsistency. "
7441 "SCB == 0x%x, yet numscbs == 0x%x.",
7442 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7443 ahd_dump_card_state(ahd);
7444 panic("for safety");
7445 }
7446 scb = ahd_lookup_scb(ahd, scbid);
7447 if (scb == NULL) {
7448 kprintf("%s: SCB = %d Not Active!\n",
7449 ahd_name(ahd), scbid);
7450 panic("Waiting List traversal\n");
7451 }
7452 ahd_set_scbptr(ahd, scbid);
7453 next = ahd_inw_scbram(ahd, SCB_NEXT);
7454 if (ahd_match_scb(ahd, scb, target, channel,
7455 lun, SCB_LIST_NULL, role) == 0) {
7456 prev = scbid;
7457 continue;
7458 }
7459 found++;
7460 switch (action) {
7461 case SEARCH_COMPLETE:
7462 {
7463 cam_status ostat;
7464 cam_status cstat;
7465
7466 ostat = ahd_get_transaction_status(scb);
7467 if (ostat == CAM_REQ_INPROG)
7468 ahd_set_transaction_status(scb, status);
7469 cstat = ahd_get_transaction_status(scb);
7470 if (cstat != CAM_REQ_CMP)
7471 ahd_freeze_scb(scb);
7472 if ((scb->flags & SCB_ACTIVE) == 0)
7473 kprintf("Inactive SCB in Waiting List\n");
7474 ahd_done(ahd, scb);
7475 /* FALLTHROUGH */
7476 }
7477 case SEARCH_REMOVE:
7478 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7479 if (prev == SCB_LIST_NULL)
7480 *list_head = next;
7481 break;
7482 case SEARCH_PRINT:
7483 kprintf("0x%x ", scbid);
7484 case SEARCH_COUNT:
7485 prev = scbid;
7486 break;
7487 }
7488 if (found > AHD_SCB_MAX)
7489 panic("SCB LIST LOOP");
7490 }
7491 if (action == SEARCH_COMPLETE
7492 || action == SEARCH_REMOVE)
7493 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7494 return (found);
7495 }
7496
7497 static void
7498 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7499 u_int tid_cur, u_int tid_next)
7500 {
7501 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7502
7503 if (SCBID_IS_NULL(tid_cur)) {
7504
7505 /* Bypass current TID list */
7506 if (SCBID_IS_NULL(tid_prev)) {
7507 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7508 } else {
7509 ahd_set_scbptr(ahd, tid_prev);
7510 ahd_outw(ahd, SCB_NEXT2, tid_next);
7511 }
7512 if (SCBID_IS_NULL(tid_next))
7513 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7514 } else {
7515
7516 /* Stitch through tid_cur */
7517 if (SCBID_IS_NULL(tid_prev)) {
7518 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7519 } else {
7520 ahd_set_scbptr(ahd, tid_prev);
7521 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7522 }
7523 ahd_set_scbptr(ahd, tid_cur);
7524 ahd_outw(ahd, SCB_NEXT2, tid_next);
7525
7526 if (SCBID_IS_NULL(tid_next))
7527 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7528 }
7529 }
7530
7531 /*
7532 * Manipulate the waiting for selection list and return the
7533 * scb that follows the one that we remove.
7534 */
7535 static u_int
7536 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7537 u_int prev, u_int next, u_int tid)
7538 {
7539 u_int tail_offset;
7540
7541 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7542 if (!SCBID_IS_NULL(prev)) {
7543 ahd_set_scbptr(ahd, prev);
7544 ahd_outw(ahd, SCB_NEXT, next);
7545 }
7546
7547 /*
7548 * SCBs that had MK_MESSAGE set in them will not
7549 * be queued to the per-target lists, so don't
7550 * blindly clear the tail pointer.
7551 */
7552 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7553 if (SCBID_IS_NULL(next)
7554 && ahd_inw(ahd, tail_offset) == scbid)
7555 ahd_outw(ahd, tail_offset, prev);
7556 ahd_add_scb_to_free_list(ahd, scbid);
7557 return (next);
7558 }
7559
7560 /*
7561 * Add the SCB as selected by SCBPTR onto the on chip list of
7562 * free hardware SCBs. This list is empty/unused if we are not
7563 * performing SCB paging.
7564 */
7565 static void
7566 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7567 {
7568 /* XXX Need some other mechanism to designate "free". */
7569 /*
7570 * Invalidate the tag so that our abort
7571 * routines don't think it's active.
7572 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7573 */
7574 }
7575
7576 /******************************** Error Handling ******************************/
7577 /*
7578 * Abort all SCBs that match the given description (target/channel/lun/tag),
7579 * setting their status to the passed in status if the status has not already
7580 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7581 * is paused before it is called.
7582 */
7583 int
7584 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7585 int lun, u_int tag, role_t role, uint32_t status)
7586 {
7587 struct scb *scbp;
7588 struct scb *scbp_next;
7589 u_int i, j;
7590 u_int maxtarget;
7591 u_int minlun;
7592 u_int maxlun;
7593 int found;
7594 ahd_mode_state saved_modes;
7595
7596 /* restore this when we're done */
7597 saved_modes = ahd_save_modes(ahd);
7598 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7599
7600 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7601 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7602
7603 /*
7604 * Clean out the busy target table for any untagged commands.
7605 */
7606 i = 0;
7607 maxtarget = 16;
7608 if (target != CAM_TARGET_WILDCARD) {
7609 i = target;
7610 if (channel == 'B')
7611 i += 8;
7612 maxtarget = i + 1;
7613 }
7614
7615 if (lun == CAM_LUN_WILDCARD) {
7616 minlun = 0;
7617 maxlun = AHD_NUM_LUNS_NONPKT;
7618 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7619 minlun = maxlun = 0;
7620 } else {
7621 minlun = lun;
7622 maxlun = lun + 1;
7623 }
7624
7625 if (role != ROLE_TARGET) {
7626 for (;i < maxtarget; i++) {
7627 for (j = minlun;j < maxlun; j++) {
7628 u_int scbid;
7629 u_int tcl;
7630
7631 tcl = BUILD_TCL_RAW(i, 'A', j);
7632 scbid = ahd_find_busy_tcl(ahd, tcl);
7633 scbp = ahd_lookup_scb(ahd, scbid);
7634 if (scbp == NULL
7635 || ahd_match_scb(ahd, scbp, target, channel,
7636 lun, tag, role) == 0)
7637 continue;
7638 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7639 }
7640 }
7641 }
7642
7643 /*
7644 * Don't abort commands that have already completed,
7645 * but haven't quite made it up to the host yet.
7646 */
7647 ahd_flush_qoutfifo(ahd);
7648
7649 /*
7650 * Go through the pending CCB list and look for
7651 * commands for this target that are still active.
7652 * These are other tagged commands that were
7653 * disconnected when the reset occurred.
7654 */
7655 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7656 while (scbp_next != NULL) {
7657 scbp = scbp_next;
7658 scbp_next = LIST_NEXT(scbp, pending_links);
7659 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7660 cam_status ostat;
7661
7662 ostat = ahd_get_transaction_status(scbp);
7663 if (ostat == CAM_REQ_INPROG)
7664 ahd_set_transaction_status(scbp, status);
7665 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP)
7666 ahd_freeze_scb(scbp);
7667 if ((scbp->flags & SCB_ACTIVE) == 0)
7668 kprintf("Inactive SCB on pending list\n");
7669 ahd_done(ahd, scbp);
7670 found++;
7671 }
7672 }
7673 ahd_restore_modes(ahd, saved_modes);
7674 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7675 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7676 return found;
7677 }
7678
7679 static void
7680 ahd_reset_current_bus(struct ahd_softc *ahd)
7681 {
7682 uint8_t scsiseq;
7683
7684 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7685 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7686 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7687 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7688 ahd_flush_device_writes(ahd);
7689 ahd_delay(AHD_BUSRESET_DELAY);
7690 /* Turn off the bus reset */
7691 ahd_outb(ahd, SCSISEQ0, scsiseq);
7692 ahd_flush_device_writes(ahd);
7693 ahd_delay(AHD_BUSRESET_DELAY);
7694 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7695 /*
7696 * 2A Razor #474
7697 * Certain chip state is not cleared for
7698 * SCSI bus resets that we initiate, so
7699 * we must reset the chip.
7700 */
7701 ahd_reset(ahd, /*reinit*/TRUE);
7702 ahd_intr_enable(ahd, /*enable*/TRUE);
7703 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7704 }
7705
7706 ahd_clear_intstat(ahd);
7707 }
7708
7709 int
7710 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7711 {
7712 struct ahd_devinfo devinfo;
7713 u_int initiator;
7714 u_int target;
7715 u_int max_scsiid;
7716 int found;
7717 u_int fifo;
7718 u_int next_fifo;
7719
7720 ahd->pending_device = NULL;
7721
7722 ahd_compile_devinfo(&devinfo,
7723 CAM_TARGET_WILDCARD,
7724 CAM_TARGET_WILDCARD,
7725 CAM_LUN_WILDCARD,
7726 channel, ROLE_UNKNOWN);
7727 ahd_pause(ahd);
7728
7729 /* Make sure the sequencer is in a safe location. */
7730 ahd_clear_critical_section(ahd);
7731
7732 #if AHD_TARGET_MODE
7733 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7734 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7735 }
7736 #endif
7737 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7738
7739 /*
7740 * Disable selections so no automatic hardware
7741 * functions will modify chip state.
7742 */
7743 ahd_outb(ahd, SCSISEQ0, 0);
7744 ahd_outb(ahd, SCSISEQ1, 0);
7745
7746 /*
7747 * Safely shut down our DMA engines. Always start with
7748 * the FIFO that is not currently active (if any are
7749 * actively connected).
7750 */
7751 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7752 if (next_fifo > CURRFIFO_1)
7753 /* If disconneced, arbitrarily start with FIFO1. */
7754 next_fifo = fifo = 0;
7755 do {
7756 next_fifo ^= CURRFIFO_1;
7757 ahd_set_modes(ahd, next_fifo, next_fifo);
7758 ahd_outb(ahd, DFCNTRL,
7759 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7760 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7761 ahd_delay(10);
7762 /*
7763 * Set CURRFIFO to the now inactive channel.
7764 */
7765 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7766 ahd_outb(ahd, DFFSTAT, next_fifo);
7767 } while (next_fifo != fifo);
7768
7769 /*
7770 * Reset the bus if we are initiating this reset
7771 */
7772 ahd_clear_msg_state(ahd);
7773 ahd_outb(ahd, SIMODE1,
7774 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE));
7775
7776 if (initiate_reset)
7777 ahd_reset_current_bus(ahd);
7778
7779 ahd_clear_intstat(ahd);
7780
7781 /*
7782 * Clean up all the state information for the
7783 * pending transactions on this bus.
7784 */
7785 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7786 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7787 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7788
7789 /*
7790 * Cleanup anything left in the FIFOs.
7791 */
7792 ahd_clear_fifo(ahd, 0);
7793 ahd_clear_fifo(ahd, 1);
7794
7795 /*
7796 * Revert to async/narrow transfers until we renegotiate.
7797 */
7798 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7799 for (target = 0; target <= max_scsiid; target++) {
7800
7801 if (ahd->enabled_targets[target] == NULL)
7802 continue;
7803 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7804 struct ahd_devinfo devinfo;
7805
7806 ahd_compile_devinfo(&devinfo, target, initiator,
7807 CAM_LUN_WILDCARD,
7808 'A', ROLE_UNKNOWN);
7809 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7810 AHD_TRANS_CUR, /*paused*/TRUE);
7811 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7812 /*offset*/0, /*ppr_options*/0,
7813 AHD_TRANS_CUR, /*paused*/TRUE);
7814 }
7815 }
7816
7817 #ifdef AHD_TARGET_MODE
7818 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7819
7820 /*
7821 * Send an immediate notify ccb to all target more peripheral
7822 * drivers affected by this action.
7823 */
7824 for (target = 0; target <= max_scsiid; target++) {
7825 struct ahd_tmode_tstate* tstate;
7826 u_int lun;
7827
7828 tstate = ahd->enabled_targets[target];
7829 if (tstate == NULL)
7830 continue;
7831 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
7832 struct ahd_tmode_lstate* lstate;
7833
7834 lstate = tstate->enabled_luns[lun];
7835 if (lstate == NULL)
7836 continue;
7837
7838 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
7839 EVENT_TYPE_BUS_RESET, /*arg*/0);
7840 ahd_send_lstate_events(ahd, lstate);
7841 }
7842 }
7843 #endif
7844 /* Notify the XPT that a bus reset occurred */
7845 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
7846 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
7847 ahd_restart(ahd);
7848 /*
7849 * Freeze the SIMQ until our poller can determine that
7850 * the bus reset has really gone away. We set the initial
7851 * timer to 0 to have the check performed as soon as possible
7852 * from the timer context.
7853 */
7854 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
7855 ahd->flags |= AHD_RESET_POLL_ACTIVE;
7856 ahd_freeze_simq(ahd);
7857 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
7858 }
7859 return (found);
7860 }
7861
7862
7863 #define AHD_RESET_POLL_US 1000
7864 static void
7865 ahd_reset_poll(void *arg)
7866 {
7867 struct ahd_softc *ahd;
7868 u_int scsiseq1;
7869
7870 ahd = ahd_find_softc((struct ahd_softc *)arg);
7871 if (ahd == NULL) {
7872 kprintf("ahd_reset_poll: Instance %p no longer exists\n", arg);
7873 return;
7874 }
7875 ahd_lock();
7876 ahd_pause(ahd);
7877 ahd_update_modes(ahd);
7878 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7879 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
7880 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
7881 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US,
7882 ahd_reset_poll, ahd);
7883 ahd_unpause(ahd);
7884 ahd_unlock();
7885 return;
7886 }
7887
7888 /* Reset is now low. Complete chip reinitialization. */
7889 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
7890 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
7891 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
7892 ahd_unpause(ahd);
7893 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
7894 ahd_unlock();
7895 ahd_release_simq(ahd);
7896 }
7897
7898 /**************************** Statistics Processing ***************************/
7899 static void
7900 ahd_stat_timer(void *arg)
7901 {
7902 struct ahd_softc *ahd;
7903 int enint_coal;
7904
7905 ahd = ahd_find_softc((struct ahd_softc *)arg);
7906 if (ahd == NULL) {
7907 kprintf("ahd_stat_timer: Instance %p no longer exists\n", arg);
7908 return;
7909 }
7910 ahd_lock();
7911
7912 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
7913 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
7914 enint_coal |= ENINT_COALESCE;
7915 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
7916 enint_coal &= ~ENINT_COALESCE;
7917
7918 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
7919 ahd_enable_coalescing(ahd, enint_coal);
7920 #ifdef AHD_DEBUG
7921 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
7922 kprintf("%s: Interrupt coalescing "
7923 "now %sabled. Cmds %d\n",
7924 ahd_name(ahd),
7925 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
7926 ahd->cmdcmplt_total);
7927 #endif
7928 }
7929
7930 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
7931 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
7932 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
7933 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
7934 ahd_stat_timer, ahd);
7935 ahd_unlock();
7936 }
7937
7938 /****************************** Status Processing *****************************/
7939 void
7940 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
7941 {
7942 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
7943 ahd_handle_scsi_status(ahd, scb);
7944 } else {
7945 ahd_calc_residual(ahd, scb);
7946 ahd_done(ahd, scb);
7947 }
7948 }
7949
7950 void
7951 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
7952 {
7953 struct hardware_scb *hscb;
7954 u_int qfreeze_cnt;
7955
7956 /*
7957 * The sequencer freezes its select-out queue
7958 * anytime a SCSI status error occurs. We must
7959 * handle the error and decrement the QFREEZE count
7960 * to allow the sequencer to continue.
7961 */
7962 hscb = scb->hscb;
7963
7964 /* Freeze the queue until the client sees the error. */
7965 ahd_freeze_devq(ahd, scb);
7966 ahd_freeze_scb(scb);
7967 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT);
7968 if (qfreeze_cnt == 0) {
7969 kprintf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd));
7970 } else {
7971 qfreeze_cnt--;
7972 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt);
7973 }
7974 if (qfreeze_cnt == 0)
7975 ahd_outb(ahd, SEQ_FLAGS2,
7976 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN);
7977
7978 /* Don't want to clobber the original sense code */
7979 if ((scb->flags & SCB_SENSE) != 0) {
7980 /*
7981 * Clear the SCB_SENSE Flag and perform
7982 * a normal command completion.
7983 */
7984 scb->flags &= ~SCB_SENSE;
7985 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
7986 ahd_done(ahd, scb);
7987 return;
7988 }
7989 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
7990 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
7991 switch (hscb->shared_data.istatus.scsi_status) {
7992 case STATUS_PKT_SENSE:
7993 {
7994 struct scsi_status_iu_header *siu;
7995
7996 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
7997 siu = (struct scsi_status_iu_header *)scb->sense_data;
7998 ahd_set_scsi_status(scb, siu->status);
7999 #ifdef AHD_DEBUG
8000 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8001 ahd_print_path(ahd, scb);
8002 kprintf("SCB 0x%x Received PKT Status of 0x%x\n",
8003 SCB_GET_TAG(scb), siu->status);
8004 kprintf("\tflags = 0x%x, sense len = 0x%x, "
8005 "pktfail = 0x%x\n",
8006 siu->flags, scsi_4btoul(siu->sense_length),
8007 scsi_4btoul(siu->pkt_failures_length));
8008 }
8009 #endif
8010 if ((siu->flags & SIU_RSPVALID) != 0) {
8011 ahd_print_path(ahd, scb);
8012 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8013 kprintf("Unable to parse pkt_failures\n");
8014 } else {
8015
8016 switch (SIU_PKTFAIL_CODE(siu)) {
8017 case SIU_PFC_NONE:
8018 kprintf("No packet failure found\n");
8019 break;
8020 case SIU_PFC_CIU_FIELDS_INVALID:
8021 kprintf("Invalid Command IU Field\n");
8022 break;
8023 case SIU_PFC_TMF_NOT_SUPPORTED:
8024 kprintf("TMF not supportd\n");
8025 break;
8026 case SIU_PFC_TMF_FAILED:
8027 kprintf("TMF failed\n");
8028 break;
8029 case SIU_PFC_INVALID_TYPE_CODE:
8030 kprintf("Invalid L_Q Type code\n");
8031 break;
8032 case SIU_PFC_ILLEGAL_REQUEST:
8033 kprintf("Illegal request\n");
8034 default:
8035 break;
8036 }
8037 }
8038 if (siu->status == SCSI_STATUS_OK)
8039 ahd_set_transaction_status(scb,
8040 CAM_REQ_CMP_ERR);
8041 }
8042 if ((siu->flags & SIU_SNSVALID) != 0) {
8043 scb->flags |= SCB_PKT_SENSE;
8044 #ifdef AHD_DEBUG
8045 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8046 kprintf("Sense data available\n");
8047 #endif
8048 }
8049 ahd_done(ahd, scb);
8050 break;
8051 }
8052 case SCSI_STATUS_CMD_TERMINATED:
8053 case SCSI_STATUS_CHECK_COND:
8054 {
8055 struct ahd_devinfo devinfo;
8056 struct ahd_dma_seg *sg;
8057 struct scsi_sense *sc;
8058 struct ahd_initiator_tinfo *targ_info;
8059 struct ahd_tmode_tstate *tstate;
8060 struct ahd_transinfo *tinfo;
8061 #ifdef AHD_DEBUG
8062 if (ahd_debug & AHD_SHOW_SENSE) {
8063 ahd_print_path(ahd, scb);
8064 kprintf("SCB %d: requests Check Status\n",
8065 SCB_GET_TAG(scb));
8066 }
8067 #endif
8068
8069 if (ahd_perform_autosense(scb) == 0)
8070 break;
8071
8072 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8073 SCB_GET_TARGET(ahd, scb),
8074 SCB_GET_LUN(scb),
8075 SCB_GET_CHANNEL(ahd, scb),
8076 ROLE_INITIATOR);
8077 targ_info = ahd_fetch_transinfo(ahd,
8078 devinfo.channel,
8079 devinfo.our_scsiid,
8080 devinfo.target,
8081 &tstate);
8082 tinfo = &targ_info->curr;
8083 sg = scb->sg_list;
8084 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8085 /*
8086 * Save off the residual if there is one.
8087 */
8088 ahd_update_residual(ahd, scb);
8089 #ifdef AHD_DEBUG
8090 if (ahd_debug & AHD_SHOW_SENSE) {
8091 ahd_print_path(ahd, scb);
8092 kprintf("Sending Sense\n");
8093 }
8094 #endif
8095 scb->sg_count = 0;
8096 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8097 ahd_get_sense_bufsize(ahd, scb),
8098 /*last*/TRUE);
8099 sc->opcode = REQUEST_SENSE;
8100 sc->byte2 = 0;
8101 if (tinfo->protocol_version <= SCSI_REV_2
8102 && SCB_GET_LUN(scb) < 8)
8103 sc->byte2 = SCB_GET_LUN(scb) << 5;
8104 sc->unused[0] = 0;
8105 sc->unused[1] = 0;
8106 sc->length = ahd_get_sense_bufsize(ahd, scb);
8107 sc->control = 0;
8108
8109 /*
8110 * We can't allow the target to disconnect.
8111 * This will be an untagged transaction and
8112 * having the target disconnect will make this
8113 * transaction indestinguishable from outstanding
8114 * tagged transactions.
8115 */
8116 hscb->control = 0;
8117
8118 /*
8119 * This request sense could be because the
8120 * the device lost power or in some other
8121 * way has lost our transfer negotiations.
8122 * Renegotiate if appropriate. Unit attention
8123 * errors will be reported before any data
8124 * phases occur.
8125 */
8126 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) {
8127 ahd_update_neg_request(ahd, &devinfo,
8128 tstate, targ_info,
8129 AHD_NEG_IF_NON_ASYNC);
8130 }
8131 if (tstate->auto_negotiate & devinfo.target_mask) {
8132 hscb->control |= MK_MESSAGE;
8133 scb->flags &=
8134 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8135 scb->flags |= SCB_AUTO_NEGOTIATE;
8136 }
8137 hscb->cdb_len = sizeof(*sc);
8138 ahd_setup_data_scb(ahd, scb);
8139 scb->flags |= SCB_SENSE;
8140 ahd_queue_scb(ahd, scb);
8141 /*
8142 * Ensure we have enough time to actually
8143 * retrieve the sense.
8144 */
8145 ahd_scb_timer_reset(scb, 5 * 1000000);
8146 break;
8147 }
8148 case SCSI_STATUS_OK:
8149 kprintf("%s: Interrupted for staus of 0???\n",
8150 ahd_name(ahd));
8151 /* FALLTHROUGH */
8152 default:
8153 ahd_done(ahd, scb);
8154 break;
8155 }
8156 }
8157
8158 /*
8159 * Calculate the residual for a just completed SCB.
8160 */
8161 void
8162 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8163 {
8164 struct hardware_scb *hscb;
8165 struct initiator_status *spkt;
8166 uint32_t sgptr;
8167 uint32_t resid_sgptr;
8168 uint32_t resid;
8169
8170 /*
8171 * 5 cases.
8172 * 1) No residual.
8173 * SG_STATUS_VALID clear in sgptr.
8174 * 2) Transferless command
8175 * 3) Never performed any transfers.
8176 * sgptr has SG_FULL_RESID set.
8177 * 4) No residual but target did not
8178 * save data pointers after the
8179 * last transfer, so sgptr was
8180 * never updated.
8181 * 5) We have a partial residual.
8182 * Use residual_sgptr to determine
8183 * where we are.
8184 */
8185
8186 hscb = scb->hscb;
8187 sgptr = ahd_le32toh(hscb->sgptr);
8188 if ((sgptr & SG_STATUS_VALID) == 0)
8189 /* Case 1 */
8190 return;
8191 sgptr &= ~SG_STATUS_VALID;
8192
8193 if ((sgptr & SG_LIST_NULL) != 0)
8194 /* Case 2 */
8195 return;
8196
8197 /*
8198 * Residual fields are the same in both
8199 * target and initiator status packets,
8200 * so we can always use the initiator fields
8201 * regardless of the role for this SCB.
8202 */
8203 spkt = &hscb->shared_data.istatus;
8204 resid_sgptr = ahd_le32toh(spkt->residual_sgptr);
8205 if ((sgptr & SG_FULL_RESID) != 0) {
8206 /* Case 3 */
8207 resid = ahd_get_transfer_length(scb);
8208 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8209 /* Case 4 */
8210 return;
8211 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8212 ahd_print_path(ahd, scb);
8213 kprintf("data overrun detected Tag == 0x%x.\n",
8214 SCB_GET_TAG(scb));
8215 ahd_freeze_devq(ahd, scb);
8216 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8217 ahd_freeze_scb(scb);
8218 return;
8219 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8220 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8221 /* NOTREACHED */
8222 } else {
8223 struct ahd_dma_seg *sg;
8224
8225 /*
8226 * Remainder of the SG where the transfer
8227 * stopped.
8228 */
8229 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8230 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8231
8232 /* The residual sg_ptr always points to the next sg */
8233 sg--;
8234
8235 /*
8236 * Add up the contents of all residual
8237 * SG segments that are after the SG where
8238 * the transfer stopped.
8239 */
8240 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8241 sg++;
8242 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
8243 }
8244 }
8245 if ((scb->flags & SCB_SENSE) == 0)
8246 ahd_set_residual(scb, resid);
8247 else
8248 ahd_set_sense_residual(scb, resid);
8249
8250 #ifdef AHD_DEBUG
8251 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8252 ahd_print_path(ahd, scb);
8253 kprintf("Handled %sResidual of %d bytes\n",
8254 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8255 }
8256 #endif
8257 }
8258
8259 /******************************* Target Mode **********************************/
8260 #ifdef AHD_TARGET_MODE
8261 /*
8262 * Add a target mode event to this lun's queue
8263 */
8264 static void
8265 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8266 u_int initiator_id, u_int event_type, u_int event_arg)
8267 {
8268 struct ahd_tmode_event *event;
8269 int pending;
8270
8271 xpt_freeze_devq(lstate->path, /*count*/1);
8272 if (lstate->event_w_idx >= lstate->event_r_idx)
8273 pending = lstate->event_w_idx - lstate->event_r_idx;
8274 else
8275 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8276 - (lstate->event_r_idx - lstate->event_w_idx);
8277
8278 if (event_type == EVENT_TYPE_BUS_RESET
8279 || event_type == MSG_BUS_DEV_RESET) {
8280 /*
8281 * Any earlier events are irrelevant, so reset our buffer.
8282 * This has the effect of allowing us to deal with reset
8283 * floods (an external device holding down the reset line)
8284 * without losing the event that is really interesting.
8285 */
8286 lstate->event_r_idx = 0;
8287 lstate->event_w_idx = 0;
8288 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8289 }
8290
8291 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8292 xpt_print_path(lstate->path);
8293 kprintf("immediate event %x:%x lost\n",
8294 lstate->event_buffer[lstate->event_r_idx].event_type,
8295 lstate->event_buffer[lstate->event_r_idx].event_arg);
8296 lstate->event_r_idx++;
8297 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8298 lstate->event_r_idx = 0;
8299 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8300 }
8301
8302 event = &lstate->event_buffer[lstate->event_w_idx];
8303 event->initiator_id = initiator_id;
8304 event->event_type = event_type;
8305 event->event_arg = event_arg;
8306 lstate->event_w_idx++;
8307 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8308 lstate->event_w_idx = 0;
8309 }
8310
8311 /*
8312 * Send any target mode events queued up waiting
8313 * for immediate notify resources.
8314 */
8315 void
8316 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8317 {
8318 struct ccb_hdr *ccbh;
8319 struct ccb_immed_notify *inot;
8320
8321 while (lstate->event_r_idx != lstate->event_w_idx
8322 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8323 struct ahd_tmode_event *event;
8324
8325 event = &lstate->event_buffer[lstate->event_r_idx];
8326 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8327 inot = (struct ccb_immed_notify *)ccbh;
8328 switch (event->event_type) {
8329 case EVENT_TYPE_BUS_RESET:
8330 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8331 break;
8332 default:
8333 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8334 inot->message_args[0] = event->event_type;
8335 inot->message_args[1] = event->event_arg;
8336 break;
8337 }
8338 inot->initiator_id = event->initiator_id;
8339 inot->sense_len = 0;
8340 xpt_done((union ccb *)inot);
8341 lstate->event_r_idx++;
8342 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8343 lstate->event_r_idx = 0;
8344 }
8345 }
8346 #endif
8347
8348 /******************** Sequencer Program Patching/Download *********************/
8349
8350 #ifdef AHD_DUMP_SEQ
8351 void
8352 ahd_dumpseq(struct ahd_softc* ahd)
8353 {
8354 int i;
8355 int max_prog;
8356
8357 max_prog = 2048;
8358
8359 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8360 ahd_outb(ahd, PRGMCNT, 0);
8361 ahd_outb(ahd, PRGMCNT+1, 0);
8362 for (i = 0; i < max_prog; i++) {
8363 uint8_t ins_bytes[4];
8364
8365 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8366 kprintf("0x%08x\n", ins_bytes[0] << 24
8367 | ins_bytes[1] << 16
8368 | ins_bytes[2] << 8
8369 | ins_bytes[3]);
8370 }
8371 }
8372 #endif
8373
8374 static void
8375 ahd_loadseq(struct ahd_softc *ahd)
8376 {
8377 struct cs cs_table[num_critical_sections];
8378 u_int begin_set[num_critical_sections];
8379 u_int end_set[num_critical_sections];
8380 struct patch *cur_patch;
8381 u_int cs_count;
8382 u_int cur_cs;
8383 u_int i;
8384 int downloaded;
8385 u_int skip_addr;
8386 u_int sg_prefetch_cnt;
8387 u_int sg_prefetch_cnt_limit;
8388 u_int sg_prefetch_align;
8389 u_int sg_size;
8390 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8391
8392 if (bootverbose)
8393 kprintf("%s: Downloading Sequencer Program...",
8394 ahd_name(ahd));
8395
8396 #if DOWNLOAD_CONST_COUNT != 7
8397 #error "Download Const Mismatch"
8398 #endif
8399 /*
8400 * Start out with 0 critical sections
8401 * that apply to this firmware load.
8402 */
8403 cs_count = 0;
8404 cur_cs = 0;
8405 memset(begin_set, 0, sizeof(begin_set));
8406 memset(end_set, 0, sizeof(end_set));
8407
8408 /*
8409 * Setup downloadable constant table.
8410 *
8411 * The computation for the S/G prefetch variables is
8412 * a bit complicated. We would like to always fetch
8413 * in terms of cachelined sized increments. However,
8414 * if the cacheline is not an even multiple of the
8415 * SG element size or is larger than our SG RAM, using
8416 * just the cache size might leave us with only a portion
8417 * of an SG element at the tail of a prefetch. If the
8418 * cacheline is larger than our S/G prefetch buffer less
8419 * the size of an SG element, we may round down to a cacheline
8420 * that doesn't contain any or all of the S/G of interest
8421 * within the bounds of our S/G ram. Provide variables to
8422 * the sequencer that will allow it to handle these edge
8423 * cases.
8424 */
8425 /* Start by aligning to the nearest cacheline. */
8426 sg_prefetch_align = ahd->pci_cachesize;
8427 if (sg_prefetch_align == 0)
8428 sg_prefetch_align = 8;
8429 /* Round down to the nearest power of 2. */
8430 while (powerof2(sg_prefetch_align) == 0)
8431 sg_prefetch_align--;
8432 /*
8433 * If the cacheline boundary is greater than half our prefetch RAM
8434 * we risk not being able to fetch even a single complete S/G
8435 * segment if we align to that boundary.
8436 */
8437 if (sg_prefetch_align > CCSGADDR_MAX/2)
8438 sg_prefetch_align = CCSGADDR_MAX/2;
8439 /* Start by fetching a single cacheline. */
8440 sg_prefetch_cnt = sg_prefetch_align;
8441 /*
8442 * Increment the prefetch count by cachelines until
8443 * at least one S/G element will fit.
8444 */
8445 sg_size = sizeof(struct ahd_dma_seg);
8446 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8447 sg_size = sizeof(struct ahd_dma64_seg);
8448 while (sg_prefetch_cnt < sg_size)
8449 sg_prefetch_cnt += sg_prefetch_align;
8450 /*
8451 * If the cacheline is not an even multiple of
8452 * the S/G size, we may only get a partial S/G when
8453 * we align. Add a cacheline if this is the case.
8454 */
8455 if ((sg_prefetch_align % sg_size) != 0
8456 && (sg_prefetch_cnt < CCSGADDR_MAX))
8457 sg_prefetch_cnt += sg_prefetch_align;
8458 /*
8459 * Lastly, compute a value that the sequencer can use
8460 * to determine if the remainder of the CCSGRAM buffer
8461 * has a full S/G element in it.
8462 */
8463 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8464 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8465 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8466 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8467 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8468 download_consts[SG_SIZEOF] = sg_size;
8469 download_consts[PKT_OVERRUN_BUFOFFSET] =
8470 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8471 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8472 cur_patch = patches;
8473 downloaded = 0;
8474 skip_addr = 0;
8475 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8476 ahd_outb(ahd, PRGMCNT, 0);
8477 ahd_outb(ahd, PRGMCNT+1, 0);
8478
8479 for (i = 0; i < sizeof(seqprog)/4; i++) {
8480 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8481 /*
8482 * Don't download this instruction as it
8483 * is in a patch that was removed.
8484 */
8485 continue;
8486 }
8487 /*
8488 * Move through the CS table until we find a CS
8489 * that might apply to this instruction.
8490 */
8491 for (; cur_cs < num_critical_sections; cur_cs++) {
8492 if (critical_sections[cur_cs].end <= i) {
8493 if (begin_set[cs_count] == TRUE
8494 && end_set[cs_count] == FALSE) {
8495 cs_table[cs_count].end = downloaded;
8496 end_set[cs_count] = TRUE;
8497 cs_count++;
8498 }
8499 continue;
8500 }
8501 if (critical_sections[cur_cs].begin <= i
8502 && begin_set[cs_count] == FALSE) {
8503 cs_table[cs_count].begin = downloaded;
8504 begin_set[cs_count] = TRUE;
8505 }
8506 break;
8507 }
8508 ahd_download_instr(ahd, i, download_consts);
8509 downloaded++;
8510 }
8511
8512 ahd->num_critical_sections = cs_count;
8513 if (cs_count != 0) {
8514 cs_count *= sizeof(struct cs);
8515 ahd->critical_sections = kmalloc(cs_count, M_DEVBUF, M_INTWAIT);
8516 memcpy(ahd->critical_sections, cs_table, cs_count);
8517 }
8518 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8519
8520 if (bootverbose) {
8521 kprintf(" %d instructions downloaded\n", downloaded);
8522 kprintf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8523 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8524 }
8525 }
8526
8527 static int
8528 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8529 u_int start_instr, u_int *skip_addr)
8530 {
8531 struct patch *cur_patch;
8532 struct patch *last_patch;
8533 u_int num_patches;
8534
8535 num_patches = sizeof(patches)/sizeof(struct patch);
8536 last_patch = &patches[num_patches];
8537 cur_patch = *start_patch;
8538
8539 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8540
8541 if (cur_patch->patch_func(ahd) == 0) {
8542
8543 /* Start rejecting code */
8544 *skip_addr = start_instr + cur_patch->skip_instr;
8545 cur_patch += cur_patch->skip_patch;
8546 } else {
8547 /* Accepted this patch. Advance to the next
8548 * one and wait for our intruction pointer to
8549 * hit this point.
8550 */
8551 cur_patch++;
8552 }
8553 }
8554
8555 *start_patch = cur_patch;
8556 if (start_instr < *skip_addr)
8557 /* Still skipping */
8558 return (0);
8559
8560 return (1);
8561 }
8562
8563 static u_int
8564 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8565 {
8566 struct patch *cur_patch;
8567 int address_offset;
8568 u_int skip_addr;
8569 u_int i;
8570
8571 address_offset = 0;
8572 cur_patch = patches;
8573 skip_addr = 0;
8574
8575 for (i = 0; i < address;) {
8576
8577 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8578
8579 if (skip_addr > i) {
8580 int end_addr;
8581
8582 end_addr = MIN(address, skip_addr);
8583 address_offset += end_addr - i;
8584 i = skip_addr;
8585 } else {
8586 i++;
8587 }
8588 }
8589 return (address - address_offset);
8590 }
8591
8592 static void
8593 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8594 {
8595 union ins_formats instr;
8596 struct ins_format1 *fmt1_ins;
8597 struct ins_format3 *fmt3_ins;
8598 u_int opcode;
8599
8600 /*
8601 * The firmware is always compiled into a little endian format.
8602 */
8603 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8604
8605 fmt1_ins = &instr.format1;
8606 fmt3_ins = NULL;
8607
8608 /* Pull the opcode */
8609 opcode = instr.format1.opcode;
8610 switch (opcode) {
8611 case AIC_OP_JMP:
8612 case AIC_OP_JC:
8613 case AIC_OP_JNC:
8614 case AIC_OP_CALL:
8615 case AIC_OP_JNE:
8616 case AIC_OP_JNZ:
8617 case AIC_OP_JE:
8618 case AIC_OP_JZ:
8619 {
8620 fmt3_ins = &instr.format3;
8621 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8622 /* FALLTHROUGH */
8623 }
8624 case AIC_OP_OR:
8625 case AIC_OP_AND:
8626 case AIC_OP_XOR:
8627 case AIC_OP_ADD:
8628 case AIC_OP_ADC:
8629 case AIC_OP_BMOV:
8630 if (fmt1_ins->parity != 0) {
8631 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8632 }
8633 fmt1_ins->parity = 0;
8634 /* FALLTHROUGH */
8635 case AIC_OP_ROL:
8636 {
8637 int i, count;
8638
8639 /* Calculate odd parity for the instruction */
8640 for (i = 0, count = 0; i < 31; i++) {
8641 uint32_t mask;
8642
8643 mask = 0x01 << i;
8644 if ((instr.integer & mask) != 0)
8645 count++;
8646 }
8647 if ((count & 0x01) == 0)
8648 instr.format1.parity = 1;
8649
8650 /* The sequencer is a little endian cpu */
8651 instr.integer = ahd_htole32(instr.integer);
8652 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8653 break;
8654 }
8655 default:
8656 panic("Unknown opcode encountered in seq program");
8657 break;
8658 }
8659 }
8660
8661 static int
8662 ahd_probe_stack_size(struct ahd_softc *ahd)
8663 {
8664 int last_probe;
8665
8666 last_probe = 0;
8667 while (1) {
8668 int i;
8669
8670 /*
8671 * We avoid using 0 as a pattern to avoid
8672 * confusion if the stack implementation
8673 * "back-fills" with zeros when "poping'
8674 * entries.
8675 */
8676 for (i = 1; i <= last_probe+1; i++) {
8677 ahd_outb(ahd, STACK, i & 0xFF);
8678 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8679 }
8680
8681 /* Verify */
8682 for (i = last_probe+1; i > 0; i--) {
8683 u_int stack_entry;
8684
8685 stack_entry = ahd_inb(ahd, STACK)
8686 |(ahd_inb(ahd, STACK) << 8);
8687 if (stack_entry != i)
8688 goto sized;
8689 }
8690 last_probe++;
8691 }
8692 sized:
8693 return (last_probe);
8694 }
8695
8696 void
8697 ahd_dump_all_cards_state(void)
8698 {
8699 struct ahd_softc *list_ahd;
8700
8701 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8702 ahd_dump_card_state(list_ahd);
8703 }
8704 }
8705
8706 int
8707 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8708 const char *name, u_int address, u_int value,
8709 u_int *cur_column, u_int wrap_point)
8710 {
8711 int printed;
8712 u_int printed_mask;
8713
8714 if (cur_column != NULL && *cur_column >= wrap_point) {
8715 kprintf("\n");
8716 *cur_column = 0;
8717 }
8718 printed = kprintf("%s[0x%x]", name, value);
8719 if (table == NULL) {
8720 printed += kprintf(" ");
8721 *cur_column += printed;
8722 return (printed);
8723 }
8724 printed_mask = 0;
8725 while (printed_mask != 0xFF) {
8726 int entry;
8727
8728 for (entry = 0; entry < num_entries; entry++) {
8729 if (((value & table[entry].mask)
8730 != table[entry].value)
8731 || ((printed_mask & table[entry].mask)
8732 == table[entry].mask))
8733 continue;
8734
8735 printed += kprintf("%s%s",
8736 printed_mask == 0 ? ":(" : "|",
8737 table[entry].name);
8738 printed_mask |= table[entry].mask;
8739
8740 break;
8741 }
8742 if (entry >= num_entries)
8743 break;
8744 }
8745 if (printed_mask != 0)
8746 printed += kprintf(") ");
8747 else
8748 printed += kprintf(" ");
8749 if (cur_column != NULL)
8750 *cur_column += printed;
8751 return (printed);
8752 }
8753
8754 void
8755 ahd_dump_card_state(struct ahd_softc *ahd)
8756 {
8757 struct scb *scb;
8758 ahd_mode_state saved_modes;
8759 u_int dffstat;
8760 int paused;
8761 u_int scb_index;
8762 u_int saved_scb_index;
8763 u_int cur_col;
8764 int i;
8765
8766 if (ahd_is_paused(ahd)) {
8767 paused = 1;
8768 } else {
8769 paused = 0;
8770 ahd_pause(ahd);
8771 }
8772 saved_modes = ahd_save_modes(ahd);
8773 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8774 kprintf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8775 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8776 ahd_name(ahd),
8777 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8),
8778 ahd_build_mode_state(ahd, ahd->saved_src_mode,
8779 ahd->saved_dst_mode));
8780 if (paused)
8781 kprintf("Card was paused\n");
8782
8783 if (ahd_check_cmdcmpltqueues(ahd))
8784 kprintf("Completions are pending\n");
8785
8786 /*
8787 * Mode independent registers.
8788 */
8789 cur_col = 0;
8790 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8791 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8792 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8793 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8794 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8795 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8796 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8797 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8798 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8799 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8800 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8801 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8802 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8803 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8804 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8805 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
8806 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
8807 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
8808 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
8809 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
8810 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
8811 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
8812 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
8813 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
8814 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
8815 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
8816 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
8817 kprintf("\n");
8818 kprintf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8819 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8820 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
8821 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
8822 ahd_inw(ahd, NEXTSCB));
8823 cur_col = 0;
8824 /* QINFIFO */
8825 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
8826 CAM_LUN_WILDCARD, SCB_LIST_NULL,
8827 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
8828 saved_scb_index = ahd_get_scbptr(ahd);
8829 kprintf("Pending list:");
8830 i = 0;
8831 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
8832 if (i++ > AHD_SCB_MAX)
8833 break;
8834 cur_col = kprintf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
8835 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
8836 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
8837 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
8838 &cur_col, 60);
8839 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
8840 &cur_col, 60);
8841 }
8842 kprintf("\nTotal %d\n", i);
8843
8844 kprintf("Kernel Free SCB list: ");
8845 i = 0;
8846 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
8847 struct scb *list_scb;
8848
8849 list_scb = scb;
8850 do {
8851 kprintf("%d ", SCB_GET_TAG(list_scb));
8852 list_scb = LIST_NEXT(list_scb, collision_links);
8853 } while (list_scb && i++ < AHD_SCB_MAX);
8854 }
8855
8856 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
8857 if (i++ > AHD_SCB_MAX)
8858 break;
8859 kprintf("%d ", SCB_GET_TAG(scb));
8860 }
8861 kprintf("\n");
8862
8863 kprintf("Sequencer Complete DMA-inprog list: ");
8864 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
8865 i = 0;
8866 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8867 ahd_set_scbptr(ahd, scb_index);
8868 kprintf("%d ", scb_index);
8869 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8870 }
8871 kprintf("\n");
8872
8873 kprintf("Sequencer Complete list: ");
8874 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
8875 i = 0;
8876 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8877 ahd_set_scbptr(ahd, scb_index);
8878 kprintf("%d ", scb_index);
8879 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8880 }
8881 kprintf("\n");
8882
8883
8884 kprintf("Sequencer DMA-Up and Complete list: ");
8885 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
8886 i = 0;
8887 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8888 ahd_set_scbptr(ahd, scb_index);
8889 kprintf("%d ", scb_index);
8890 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
8891 }
8892 kprintf("\n");
8893 ahd_set_scbptr(ahd, saved_scb_index);
8894 dffstat = ahd_inb(ahd, DFFSTAT);
8895 for (i = 0; i < 2; i++) {
8896 #ifdef AHD_DEBUG
8897 struct scb *fifo_scb;
8898 #endif
8899 u_int fifo_scbptr;
8900
8901 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
8902 fifo_scbptr = ahd_get_scbptr(ahd);
8903 kprintf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
8904 ahd_name(ahd), i,
8905 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
8906 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
8907 cur_col = 0;
8908 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
8909 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
8910 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
8911 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
8912 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
8913 &cur_col, 50);
8914 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
8915 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
8916 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
8917 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
8918 if (cur_col > 50) {
8919 kprintf("\n");
8920 cur_col = 0;
8921 }
8922 cur_col += kprintf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
8923 ahd_inl(ahd, SHADDR+4),
8924 ahd_inl(ahd, SHADDR),
8925 (ahd_inb(ahd, SHCNT)
8926 | (ahd_inb(ahd, SHCNT + 1) << 8)
8927 | (ahd_inb(ahd, SHCNT + 2) << 16)));
8928 if (cur_col > 50) {
8929 kprintf("\n");
8930 cur_col = 0;
8931 }
8932 cur_col += kprintf("HADDR = 0x%x%x, HCNT = 0x%x ",
8933 ahd_inl(ahd, HADDR+4),
8934 ahd_inl(ahd, HADDR),
8935 (ahd_inb(ahd, HCNT)
8936 | (ahd_inb(ahd, HCNT + 1) << 8)
8937 | (ahd_inb(ahd, HCNT + 2) << 16)));
8938 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
8939 #ifdef AHD_DEBUG
8940 if ((ahd_debug & AHD_SHOW_SG) != 0) {
8941 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
8942 if (fifo_scb != NULL)
8943 ahd_dump_sglist(fifo_scb);
8944 }
8945 #endif
8946 }
8947 kprintf("\nLQIN: ");
8948 for (i = 0; i < 20; i++)
8949 kprintf("0x%x ", ahd_inb(ahd, LQIN + i));
8950 kprintf("\n");
8951 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
8952 kprintf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
8953 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
8954 ahd_inb(ahd, OPTIONMODE));
8955 kprintf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
8956 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
8957 ahd_inb(ahd, MAXCMDCNT));
8958 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
8959 kprintf("\n");
8960 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
8961 cur_col = 0;
8962 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
8963 kprintf("\n");
8964 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
8965 kprintf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
8966 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
8967 ahd_inw(ahd, DINDEX));
8968 kprintf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
8969 ahd_name(ahd), ahd_get_scbptr(ahd),
8970 ahd_inw_scbram(ahd, SCB_NEXT),
8971 ahd_inw_scbram(ahd, SCB_NEXT2));
8972 kprintf("CDB %x %x %x %x %x %x\n",
8973 ahd_inb_scbram(ahd, SCB_CDB_STORE),
8974 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
8975 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
8976 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
8977 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
8978 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
8979 kprintf("STACK:");
8980 for (i = 0; i < ahd->stack_size; i++) {
8981 ahd->saved_stack[i] =
8982 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
8983 kprintf(" 0x%x", ahd->saved_stack[i]);
8984 }
8985 for (i = ahd->stack_size-1; i >= 0; i--) {
8986 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
8987 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
8988 }
8989 kprintf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
8990 ahd_platform_dump_card_state(ahd);
8991 ahd_restore_modes(ahd, saved_modes);
8992 if (paused == 0)
8993 ahd_unpause(ahd);
8994 }
8995
8996 void
8997 ahd_dump_scbs(struct ahd_softc *ahd)
8998 {
8999 ahd_mode_state saved_modes;
9000 u_int saved_scb_index;
9001 int i;
9002
9003 saved_modes = ahd_save_modes(ahd);
9004 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9005 saved_scb_index = ahd_get_scbptr(ahd);
9006 for (i = 0; i < AHD_SCB_MAX; i++) {
9007 ahd_set_scbptr(ahd, i);
9008 kprintf("%3d", i);
9009 kprintf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9010 ahd_inb_scbram(ahd, SCB_CONTROL),
9011 ahd_inb_scbram(ahd, SCB_SCSIID),
9012 ahd_inw_scbram(ahd, SCB_NEXT),
9013 ahd_inw_scbram(ahd, SCB_NEXT2),
9014 ahd_inl_scbram(ahd, SCB_SGPTR),
9015 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9016 }
9017 kprintf("\n");
9018 ahd_set_scbptr(ahd, saved_scb_index);
9019 ahd_restore_modes(ahd, saved_modes);
9020 }
9021
9022 /**************************** Flexport Logic **********************************/
9023 /*
9024 * Read count 16bit words from 16bit word address start_addr from the
9025 * SEEPROM attached to the controller, into buf, using the controller's
9026 * SEEPROM reading state machine. Optionally treat the data as a byte
9027 * stream in terms of byte order.
9028 */
9029 int
9030 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9031 u_int start_addr, u_int count, int bytestream)
9032 {
9033 u_int cur_addr;
9034 u_int end_addr;
9035 int error;
9036
9037 /*
9038 * If we never make it through the loop even once,
9039 * we were passed invalid arguments.
9040 */
9041 error = EINVAL;
9042 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9043 end_addr = start_addr + count;
9044 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9045
9046 ahd_outb(ahd, SEEADR, cur_addr);
9047 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9048
9049 error = ahd_wait_seeprom(ahd);
9050 if (error)
9051 break;
9052 if (bytestream != 0) {
9053 uint8_t *bytestream_ptr;
9054
9055 bytestream_ptr = (uint8_t *)buf;
9056 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9057 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9058 } else {
9059 /*
9060 * ahd_inw() already handles machine byte order.
9061 */
9062 *buf = ahd_inw(ahd, SEEDAT);
9063 }
9064 buf++;
9065 }
9066 return (error);
9067 }
9068
9069 /*
9070 * Write count 16bit words from buf, into SEEPROM attache to the
9071 * controller starting at 16bit word address start_addr, using the
9072 * controller's SEEPROM writing state machine.
9073 */
9074 int
9075 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9076 u_int start_addr, u_int count)
9077 {
9078 u_int cur_addr;
9079 u_int end_addr;
9080 int error;
9081 int retval;
9082
9083 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9084 error = ENOENT;
9085
9086 /* Place the chip into write-enable mode */
9087 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9088 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9089 error = ahd_wait_seeprom(ahd);
9090 if (error)
9091 return (error);
9092
9093 /*
9094 * Write the data. If we don't get throught the loop at
9095 * least once, the arguments were invalid.
9096 */
9097 retval = EINVAL;
9098 end_addr = start_addr + count;
9099 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9100 ahd_outw(ahd, SEEDAT, *buf++);
9101 ahd_outb(ahd, SEEADR, cur_addr);
9102 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9103
9104 retval = ahd_wait_seeprom(ahd);
9105 if (retval)
9106 break;
9107 }
9108
9109 /*
9110 * Disable writes.
9111 */
9112 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9113 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9114 error = ahd_wait_seeprom(ahd);
9115 if (error)
9116 return (error);
9117 return (retval);
9118 }
9119
9120 /*
9121 * Wait ~100us for the serial eeprom to satisfy our request.
9122 */
9123 int
9124 ahd_wait_seeprom(struct ahd_softc *ahd)
9125 {
9126 int cnt;
9127
9128 cnt = 20;
9129 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9130 ahd_delay(5);
9131
9132 if (cnt == 0)
9133 return (ETIMEDOUT);
9134 return (0);
9135 }
9136
9137 /*
9138 * Validate the two checksums in the per_channel
9139 * vital product data struct.
9140 */
9141 int
9142 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9143 {
9144 int i;
9145 int maxaddr;
9146 uint32_t checksum;
9147 uint8_t *vpdarray;
9148
9149 vpdarray = (uint8_t *)vpd;
9150 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9151 checksum = 0;
9152 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9153 checksum = checksum + vpdarray[i];
9154 if (checksum == 0
9155 || (-checksum & 0xFF) != vpd->vpd_checksum)
9156 return (0);
9157
9158 checksum = 0;
9159 maxaddr = offsetof(struct vpd_config, checksum);
9160 for (i = offsetof(struct vpd_config, default_target_flags);
9161 i < maxaddr; i++)
9162 checksum = checksum + vpdarray[i];
9163 if (checksum == 0
9164 || (-checksum & 0xFF) != vpd->checksum)
9165 return (0);
9166 return (1);
9167 }
9168
9169 int
9170 ahd_verify_cksum(struct seeprom_config *sc)
9171 {
9172 int i;
9173 int maxaddr;
9174 uint32_t checksum;
9175 uint16_t *scarray;
9176
9177 maxaddr = (sizeof(*sc)/2) - 1;
9178 checksum = 0;
9179 scarray = (uint16_t *)sc;
9180
9181 for (i = 0; i < maxaddr; i++)
9182 checksum = checksum + scarray[i];
9183 if (checksum == 0
9184 || (checksum & 0xFFFF) != sc->checksum) {
9185 return (0);
9186 } else {
9187 return (1);
9188 }
9189 }
9190
9191 int
9192 ahd_acquire_seeprom(struct ahd_softc *ahd)
9193 {
9194 /*
9195 * We should be able to determine the SEEPROM type
9196 * from the flexport logic, but unfortunately not
9197 * all implementations have this logic and there is
9198 * no programatic method for determining if the logic
9199 * is present.
9200 */
9201 return (1);
9202 #if 0
9203 uint8_t seetype;
9204 int error;
9205
9206 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9207 if (error != 0
9208 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9209 return (0);
9210 return (1);
9211 #endif
9212 }
9213
9214 void
9215 ahd_release_seeprom(struct ahd_softc *ahd)
9216 {
9217 /* Currently a no-op */
9218 }
9219
9220 int
9221 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9222 {
9223 int error;
9224
9225 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9226 if (addr > 7)
9227 panic("ahd_write_flexport: address out of range");
9228 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9229 error = ahd_wait_flexport(ahd);
9230 if (error != 0)
9231 return (error);
9232 ahd_outb(ahd, BRDDAT, value);
9233 ahd_flush_device_writes(ahd);
9234 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9235 ahd_flush_device_writes(ahd);
9236 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9237 ahd_flush_device_writes(ahd);
9238 ahd_outb(ahd, BRDCTL, 0);
9239 ahd_flush_device_writes(ahd);
9240 return (0);
9241 }
9242
9243 int
9244 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9245 {
9246 int error;
9247
9248 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9249 if (addr > 7)
9250 panic("ahd_read_flexport: address out of range");
9251 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9252 error = ahd_wait_flexport(ahd);
9253 if (error != 0)
9254 return (error);
9255 *value = ahd_inb(ahd, BRDDAT);
9256 ahd_outb(ahd, BRDCTL, 0);
9257 ahd_flush_device_writes(ahd);
9258 return (0);
9259 }
9260
9261 /*
9262 * Wait at most 2 seconds for flexport arbitration to succeed.
9263 */
9264 int
9265 ahd_wait_flexport(struct ahd_softc *ahd)
9266 {
9267 int cnt;
9268
9269 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9270 cnt = 1000000 * 2 / 5;
9271 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9272 ahd_delay(5);
9273
9274 if (cnt == 0)
9275 return (ETIMEDOUT);
9276 return (0);
9277 }
9278
9279 /************************* Target Mode ****************************************/
9280 #ifdef AHD_TARGET_MODE
9281 cam_status
9282 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9283 struct ahd_tmode_tstate **tstate,
9284 struct ahd_tmode_lstate **lstate,
9285 int notfound_failure)
9286 {
9287
9288 if ((ahd->features & AHD_TARGETMODE) == 0)
9289 return (CAM_REQ_INVALID);
9290
9291 /*
9292 * Handle the 'black hole' device that sucks up
9293 * requests to unattached luns on enabled targets.
9294 */
9295 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9296 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9297 *tstate = NULL;
9298 *lstate = ahd->black_hole;
9299 } else {
9300 u_int max_id;
9301
9302 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9303 if (ccb->ccb_h.target_id > max_id)
9304 return (CAM_TID_INVALID);
9305
9306 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9307 return (CAM_LUN_INVALID);
9308
9309 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9310 *lstate = NULL;
9311 if (*tstate != NULL)
9312 *lstate =
9313 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9314 }
9315
9316 if (notfound_failure != 0 && *lstate == NULL)
9317 return (CAM_PATH_INVALID);
9318
9319 return (CAM_REQ_CMP);
9320 }
9321
9322 void
9323 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9324 {
9325 #if NOT_YET
9326 struct ahd_tmode_tstate *tstate;
9327 struct ahd_tmode_lstate *lstate;
9328 struct ccb_en_lun *cel;
9329 cam_status status;
9330 u_int target;
9331 u_int lun;
9332 u_int target_mask;
9333 u_long s;
9334 char channel;
9335
9336 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9337 /*notfound_failure*/FALSE);
9338
9339 if (status != CAM_REQ_CMP) {
9340 ccb->ccb_h.status = status;
9341 return;
9342 }
9343
9344 if ((ahd->features & AHD_MULTIROLE) != 0) {
9345 u_int our_id;
9346
9347 our_id = ahd->our_id;
9348 if (ccb->ccb_h.target_id != our_id) {
9349 if ((ahd->features & AHD_MULTI_TID) != 0
9350 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9351 /*
9352 * Only allow additional targets if
9353 * the initiator role is disabled.
9354 * The hardware cannot handle a re-select-in
9355 * on the initiator id during a re-select-out
9356 * on a different target id.
9357 */
9358 status = CAM_TID_INVALID;
9359 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9360 || ahd->enabled_luns > 0) {
9361 /*
9362 * Only allow our target id to change
9363 * if the initiator role is not configured
9364 * and there are no enabled luns which
9365 * are attached to the currently registered
9366 * scsi id.
9367 */
9368 status = CAM_TID_INVALID;
9369 }
9370 }
9371 }
9372
9373 if (status != CAM_REQ_CMP) {
9374 ccb->ccb_h.status = status;
9375 return;
9376 }
9377
9378 /*
9379 * We now have an id that is valid.
9380 * If we aren't in target mode, switch modes.
9381 */
9382 if ((ahd->flags & AHD_TARGETROLE) == 0
9383 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9384 u_long s;
9385
9386 kprintf("Configuring Target Mode\n");
9387 ahd_lock();
9388 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9389 ccb->ccb_h.status = CAM_BUSY;
9390 ahd_unlock();
9391 return;
9392 }
9393 ahd->flags |= AHD_TARGETROLE;
9394 if ((ahd->features & AHD_MULTIROLE) == 0)
9395 ahd->flags &= ~AHD_INITIATORROLE;
9396 ahd_pause(ahd);
9397 ahd_loadseq(ahd);
9398 ahd_restart(ahd);
9399 ahd_unlock();
9400 }
9401 cel = &ccb->cel;
9402 target = ccb->ccb_h.target_id;
9403 lun = ccb->ccb_h.target_lun;
9404 channel = SIM_CHANNEL(ahd, sim);
9405 target_mask = 0x01 << target;
9406 if (channel == 'B')
9407 target_mask <<= 8;
9408
9409 if (cel->enable != 0) {
9410 u_int scsiseq1;
9411
9412 /* Are we already enabled?? */
9413 if (lstate != NULL) {
9414 xpt_print_path(ccb->ccb_h.path);
9415 kprintf("Lun already enabled\n");
9416 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9417 return;
9418 }
9419
9420 if (cel->grp6_len != 0
9421 || cel->grp7_len != 0) {
9422 /*
9423 * Don't (yet?) support vendor
9424 * specific commands.
9425 */
9426 ccb->ccb_h.status = CAM_REQ_INVALID;
9427 kprintf("Non-zero Group Codes\n");
9428 return;
9429 }
9430
9431 /*
9432 * Seems to be okay.
9433 * Setup our data structures.
9434 */
9435 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9436 tstate = ahd_alloc_tstate(ahd, target, channel);
9437 if (tstate == NULL) {
9438 xpt_print_path(ccb->ccb_h.path);
9439 kprintf("Couldn't allocate tstate\n");
9440 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9441 return;
9442 }
9443 }
9444 lstate = kmalloc(sizeof(*lstate), M_DEVBUF, M_INTWAIT | M_ZERO);
9445 status = xpt_create_path(&lstate->path, /*periph*/NULL,
9446 xpt_path_path_id(ccb->ccb_h.path),
9447 xpt_path_target_id(ccb->ccb_h.path),
9448 xpt_path_lun_id(ccb->ccb_h.path));
9449 if (status != CAM_REQ_CMP) {
9450 kfree(lstate, M_DEVBUF);
9451 xpt_print_path(ccb->ccb_h.path);
9452 kprintf("Couldn't allocate path\n");
9453 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9454 return;
9455 }
9456 SLIST_INIT(&lstate->accept_tios);
9457 SLIST_INIT(&lstate->immed_notifies);
9458 ahd_lock();
9459 ahd_pause(ahd);
9460 if (target != CAM_TARGET_WILDCARD) {
9461 tstate->enabled_luns[lun] = lstate;
9462 ahd->enabled_luns++;
9463
9464 if ((ahd->features & AHD_MULTI_TID) != 0) {
9465 u_int targid_mask;
9466
9467 targid_mask = ahd_inb(ahd, TARGID)
9468 | (ahd_inb(ahd, TARGID + 1) << 8);
9469
9470 targid_mask |= target_mask;
9471 ahd_outb(ahd, TARGID, targid_mask);
9472 ahd_outb(ahd, TARGID+1, (targid_mask >> 8));
9473
9474 ahd_update_scsiid(ahd, targid_mask);
9475 } else {
9476 u_int our_id;
9477 char channel;
9478
9479 channel = SIM_CHANNEL(ahd, sim);
9480 our_id = SIM_SCSI_ID(ahd, sim);
9481
9482 /*
9483 * This can only happen if selections
9484 * are not enabled
9485 */
9486 if (target != our_id) {
9487 u_int sblkctl;
9488 char cur_channel;
9489 int swap;
9490
9491 sblkctl = ahd_inb(ahd, SBLKCTL);
9492 cur_channel = (sblkctl & SELBUSB)
9493 ? 'B' : 'A';
9494 if ((ahd->features & AHD_TWIN) == 0)
9495 cur_channel = 'A';
9496 swap = cur_channel != channel;
9497 ahd->our_id = target;
9498
9499 if (swap)
9500 ahd_outb(ahd, SBLKCTL,
9501 sblkctl ^ SELBUSB);
9502
9503 ahd_outb(ahd, SCSIID, target);
9504
9505 if (swap)
9506 ahd_outb(ahd, SBLKCTL, sblkctl);
9507 }
9508 }
9509 } else
9510 ahd->black_hole = lstate;
9511 /* Allow select-in operations */
9512 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
9513 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9514 scsiseq1 |= ENSELI;
9515 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9516 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9517 scsiseq1 |= ENSELI;
9518 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9519 }
9520 ahd_unpause(ahd);
9521 ahd_unlock();
9522 ccb->ccb_h.status = CAM_REQ_CMP;
9523 xpt_print_path(ccb->ccb_h.path);
9524 kprintf("Lun now enabled for target mode\n");
9525 } else {
9526 struct scb *scb;
9527 int i, empty;
9528
9529 if (lstate == NULL) {
9530 ccb->ccb_h.status = CAM_LUN_INVALID;
9531 return;
9532 }
9533
9534 ahd_lock();
9535
9536 ccb->ccb_h.status = CAM_REQ_CMP;
9537 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9538 struct ccb_hdr *ccbh;
9539
9540 ccbh = &scb->io_ctx->ccb_h;
9541 if (ccbh->func_code == XPT_CONT_TARGET_IO
9542 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
9543 kprintf("CTIO pending\n");
9544 ccb->ccb_h.status = CAM_REQ_INVALID;
9545 ahd_unlock();
9546 return;
9547 }
9548 }
9549
9550 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
9551 kprintf("ATIOs pending\n");
9552 ccb->ccb_h.status = CAM_REQ_INVALID;
9553 }
9554
9555 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
9556 kprintf("INOTs pending\n");
9557 ccb->ccb_h.status = CAM_REQ_INVALID;
9558 }
9559
9560 if (ccb->ccb_h.status != CAM_REQ_CMP) {
9561 ahd_unlock();
9562 return;
9563 }
9564
9565 xpt_print_path(ccb->ccb_h.path);
9566 kprintf("Target mode disabled\n");
9567 xpt_free_path(lstate->path);
9568 kfree(lstate, M_DEVBUF);
9569
9570 ahd_pause(ahd);
9571 /* Can we clean up the target too? */
9572 if (target != CAM_TARGET_WILDCARD) {
9573 tstate->enabled_luns[lun] = NULL;
9574 ahd->enabled_luns--;
9575 for (empty = 1, i = 0; i < 8; i++)
9576 if (tstate->enabled_luns[i] != NULL) {
9577 empty = 0;
9578 break;
9579 }
9580
9581 if (empty) {
9582 ahd_free_tstate(ahd, target, channel,
9583 /*force*/FALSE);
9584 if (ahd->features & AHD_MULTI_TID) {
9585 u_int targid_mask;
9586
9587 targid_mask = ahd_inb(ahd, TARGID)
9588 | (ahd_inb(ahd, TARGID + 1)
9589 << 8);
9590
9591 targid_mask &= ~target_mask;
9592 ahd_outb(ahd, TARGID, targid_mask);
9593 ahd_outb(ahd, TARGID+1,
9594 (targid_mask >> 8));
9595 ahd_update_scsiid(ahd, targid_mask);
9596 }
9597 }
9598 } else {
9599
9600 ahd->black_hole = NULL;
9601
9602 /*
9603 * We can't allow selections without
9604 * our black hole device.
9605 */
9606 empty = TRUE;
9607 }
9608 if (ahd->enabled_luns == 0) {
9609 /* Disallow select-in */
9610 u_int scsiseq1;
9611
9612 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9613 scsiseq1 &= ~ENSELI;
9614 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9615 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9616 scsiseq1 &= ~ENSELI;
9617 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9618
9619 if ((ahd->features & AHD_MULTIROLE) == 0) {
9620 kprintf("Configuring Initiator Mode\n");
9621 ahd->flags &= ~AHD_TARGETROLE;
9622 ahd->flags |= AHD_INITIATORROLE;
9623 ahd_pause(ahd);
9624 ahd_loadseq(ahd);
9625 ahd_restart(ahd);
9626 /*
9627 * Unpaused. The extra unpause
9628 * that follows is harmless.
9629 */
9630 }
9631 }
9632 ahd_unpause(ahd);
9633 ahd_unlock();
9634 }
9635 #endif
9636 }
9637
9638 static void
9639 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
9640 {
9641 #if NOT_YET
9642 u_int scsiid_mask;
9643 u_int scsiid;
9644
9645 if ((ahd->features & AHD_MULTI_TID) == 0)
9646 panic("ahd_update_scsiid called on non-multitid unit\n");
9647
9648 /*
9649 * Since we will rely on the TARGID mask
9650 * for selection enables, ensure that OID
9651 * in SCSIID is not set to some other ID
9652 * that we don't want to allow selections on.
9653 */
9654 if ((ahd->features & AHD_ULTRA2) != 0)
9655 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
9656 else
9657 scsiid = ahd_inb(ahd, SCSIID);
9658 scsiid_mask = 0x1 << (scsiid & OID);
9659 if ((targid_mask & scsiid_mask) == 0) {
9660 u_int our_id;
9661
9662 /* ffs counts from 1 */
9663 our_id = ffs(targid_mask);
9664 if (our_id == 0)
9665 our_id = ahd->our_id;
9666 else
9667 our_id--;
9668 scsiid &= TID;
9669 scsiid |= our_id;
9670 }
9671 if ((ahd->features & AHD_ULTRA2) != 0)
9672 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
9673 else
9674 ahd_outb(ahd, SCSIID, scsiid);
9675 #endif
9676 }
9677
9678 void
9679 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
9680 {
9681 struct target_cmd *cmd;
9682
9683 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
9684 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
9685
9686 /*
9687 * Only advance through the queue if we
9688 * have the resources to process the command.
9689 */
9690 if (ahd_handle_target_cmd(ahd, cmd) != 0)
9691 break;
9692
9693 cmd->cmd_valid = 0;
9694 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
9695 ahd->shared_data_dmamap,
9696 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
9697 sizeof(struct target_cmd),
9698 BUS_DMASYNC_PREREAD);
9699 ahd->tqinfifonext++;
9700
9701 /*
9702 * Lazily update our position in the target mode incoming
9703 * command queue as seen by the sequencer.
9704 */
9705 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
9706 u_int hs_mailbox;
9707
9708 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
9709 hs_mailbox &= ~HOST_TQINPOS;
9710 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
9711 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
9712 }
9713 }
9714 }
9715
9716 static int
9717 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
9718 {
9719 struct ahd_tmode_tstate *tstate;
9720 struct ahd_tmode_lstate *lstate;
9721 struct ccb_accept_tio *atio;
9722 uint8_t *byte;
9723 int initiator;
9724 int target;
9725 int lun;
9726
9727 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
9728 target = SCSIID_OUR_ID(cmd->scsiid);
9729 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
9730
9731 byte = cmd->bytes;
9732 tstate = ahd->enabled_targets[target];
9733 lstate = NULL;
9734 if (tstate != NULL)
9735 lstate = tstate->enabled_luns[lun];
9736
9737 /*
9738 * Commands for disabled luns go to the black hole driver.
9739 */
9740 if (lstate == NULL)
9741 lstate = ahd->black_hole;
9742
9743 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
9744 if (atio == NULL) {
9745 ahd->flags |= AHD_TQINFIFO_BLOCKED;
9746 /*
9747 * Wait for more ATIOs from the peripheral driver for this lun.
9748 */
9749 return (1);
9750 } else
9751 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
9752 #ifdef AHD_DEBUG
9753 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9754 kprintf("Incoming command from %d for %d:%d%s\n",
9755 initiator, target, lun,
9756 lstate == ahd->black_hole ? "(Black Holed)" : "");
9757 #endif
9758 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
9759
9760 if (lstate == ahd->black_hole) {
9761 /* Fill in the wildcards */
9762 atio->ccb_h.target_id = target;
9763 atio->ccb_h.target_lun = lun;
9764 }
9765
9766 /*
9767 * Package it up and send it off to
9768 * whomever has this lun enabled.
9769 */
9770 atio->sense_len = 0;
9771 atio->init_id = initiator;
9772 if (byte[0] != 0xFF) {
9773 /* Tag was included */
9774 atio->tag_action = *byte++;
9775 atio->tag_id = *byte++;
9776 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
9777 } else {
9778 atio->ccb_h.flags = 0;
9779 }
9780 byte++;
9781
9782 /* Okay. Now determine the cdb size based on the command code */
9783 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
9784 case 0:
9785 atio->cdb_len = 6;
9786 break;
9787 case 1:
9788 case 2:
9789 atio->cdb_len = 10;
9790 break;
9791 case 4:
9792 atio->cdb_len = 16;
9793 break;
9794 case 5:
9795 atio->cdb_len = 12;
9796 break;
9797 case 3:
9798 default:
9799 /* Only copy the opcode. */
9800 atio->cdb_len = 1;
9801 kprintf("Reserved or VU command code type encountered\n");
9802 break;
9803 }
9804
9805 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
9806
9807 atio->ccb_h.status |= CAM_CDB_RECVD;
9808
9809 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
9810 /*
9811 * We weren't allowed to disconnect.
9812 * We're hanging on the bus until a
9813 * continue target I/O comes in response
9814 * to this accept tio.
9815 */
9816 #ifdef AHD_DEBUG
9817 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9818 kprintf("Received Immediate Command %d:%d:%d - %p\n",
9819 initiator, target, lun, ahd->pending_device);
9820 #endif
9821 ahd->pending_device = lstate;
9822 ahd_freeze_ccb((union ccb *)atio);
9823 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
9824 }
9825 xpt_done((union ccb*)atio);
9826 return (0);
9827 }
9828
9829 #endif
A repo for keeping AMD64 port code before merging with the master