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Add WIP support for Broadcom wireless chips:
[dragonfly/port-amd64.git] / sys / dev / netif / bwi / if_bwi.c
blob08a17cecfce6907922a78d840fbe4ae675c6b9dc
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.1 2007/09/08 06:15:54 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/bus.h>
41 #include <sys/malloc.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48
49 #include <net/ethernet.h>
50 #include <net/if.h>
51 #include <net/bpf.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
56
57 #include <netproto/802_11/ieee80211_var.h>
58
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pcidevs.h>
62
63 #include "bitops.h"
64 #include "if_bwireg.h"
65 #include "if_bwivar.h"
66 #include "bwimac.h"
67 #include "bwirf.h"
68
69 struct bwi_clock_freq {
70 u_int clkfreq_min;
71 u_int clkfreq_max;
72 };
73
74 struct bwi_myaddr_bssid {
75 uint8_t myaddr[IEEE80211_ADDR_LEN];
76 uint8_t bssid[IEEE80211_ADDR_LEN];
77 } __packed;
78
79 static int bwi_probe(device_t);
80 static int bwi_attach(device_t);
81 static int bwi_detach(device_t);
82 static int bwi_shutdown(device_t);
83
84 static void bwi_init(void *);
85 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
86 static void bwi_start(struct ifnet *);
87 static void bwi_watchdog(struct ifnet *);
88 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
89 static void bwi_updateslot(struct ifnet *);
90 static int bwi_media_change(struct ifnet *);
91
92 static void bwi_next_scan(void *);
93 static void bwi_calibrate(void *);
94
95 static int bwi_stop(struct bwi_softc *);
96 static int bwi_newbuf(struct bwi_softc *, int, int);
97 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
98 struct ieee80211_node *);
99
100 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
101 bus_addr_t, int, int);
102 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
103
104 static int bwi_init_tx_ring32(struct bwi_softc *, int);
105 static int bwi_init_rx_ring32(struct bwi_softc *);
106 static int bwi_init_txstats32(struct bwi_softc *);
107 static void bwi_free_tx_ring32(struct bwi_softc *, int);
108 static void bwi_free_rx_ring32(struct bwi_softc *);
109 static void bwi_free_txstats32(struct bwi_softc *);
110 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
111 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
112 int, bus_addr_t, int);
113 static void bwi_rxeof32(struct bwi_softc *);
114 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
115 static void bwi_txeof_status32(struct bwi_softc *);
116
117 static int bwi_init_tx_ring64(struct bwi_softc *, int);
118 static int bwi_init_rx_ring64(struct bwi_softc *);
119 static int bwi_init_txstats64(struct bwi_softc *);
120 static void bwi_free_tx_ring64(struct bwi_softc *, int);
121 static void bwi_free_rx_ring64(struct bwi_softc *);
122 static void bwi_free_txstats64(struct bwi_softc *);
123 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
124 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
125 int, bus_addr_t, int);
126 static void bwi_rxeof64(struct bwi_softc *);
127 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
128 static void bwi_txeof_status64(struct bwi_softc *);
129
130 static void bwi_intr(void *);
131 static void bwi_rxeof(struct bwi_softc *, int);
132 static void _bwi_txeof(struct bwi_softc *, uint16_t);
133 static void bwi_txeof(struct bwi_softc *);
134 static void bwi_txeof_status(struct bwi_softc *, int);
135 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
136 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
137
138 static int bwi_dma_alloc(struct bwi_softc *);
139 static void bwi_dma_free(struct bwi_softc *);
140 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
141 struct bwi_ring_data *, bus_size_t,
142 uint32_t);
143 static int bwi_dma_mbuf_create(struct bwi_softc *);
144 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
145 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
146 static void bwi_dma_txstats_free(struct bwi_softc *);
147 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
148 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
149 bus_size_t, int);
150
151 static void bwi_power_on(struct bwi_softc *, int);
152 static int bwi_power_off(struct bwi_softc *, int);
153 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
154 static int bwi_set_clock_delay(struct bwi_softc *);
155 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
156 static int bwi_get_pwron_delay(struct bwi_softc *sc);
157 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
158 const uint8_t *);
159 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
160 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
161
162 static void bwi_get_card_flags(struct bwi_softc *);
163 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
164
165 static int bwi_bus_attach(struct bwi_softc *);
166 static int bwi_bbp_attach(struct bwi_softc *);
167 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
168 static void bwi_bbp_power_off(struct bwi_softc *);
169
170 static const char *bwi_regwin_name(const struct bwi_regwin *);
171 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
172 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
173 static int bwi_regwin_select(struct bwi_softc *, int);
174
175 static const struct bwi_dev {
176 uint16_t vid;
177 uint16_t did;
178 const char *desc;
179 } bwi_devices[] = {
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
181 "Broadcom BCM4301 802.11 Wireless Lan" },
182
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
184 "Broadcom BCM4307 802.11 Wireless Lan" },
185
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
187 "Broadcom BCM4311 802.11 Wireless Lan" },
188
189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
190 "Broadcom BCM4312 802.11 Wireless Lan" },
191
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
193 "Broadcom BCM4306 802.11 Wireless Lan" },
194
195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
196 "Broadcom BCM4306 802.11 Wireless Lan" },
197
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
199 "Broadcom BCM4306 802.11 Wireless Lan" },
200
201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
202 "Broadcom BCM4309 802.11 Wireless Lan" },
203
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
205 "Broadcom BCM4318 802.11 Wireless Lan" },
206
207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
208 "Broadcom BCM4319 802.11 Wireless Lan" }
209 };
210
211 static device_method_t bwi_methods[] = {
212 DEVMETHOD(device_probe, bwi_probe),
213 DEVMETHOD(device_attach, bwi_attach),
214 DEVMETHOD(device_detach, bwi_detach),
215 DEVMETHOD(device_shutdown, bwi_shutdown),
216 #if 0
217 DEVMETHOD(device_suspend, bwi_suspend),
218 DEVMETHOD(device_resume, bwi_resume),
219 #endif
220 { 0, 0 }
221 };
222
223 static driver_t bwi_driver = {
224 "bwi",
225 bwi_methods,
226 sizeof(struct bwi_softc)
227 };
228
229 static devclass_t bwi_devclass;
230
231 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
232 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
233
234 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
235 #if 0
236 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
237 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
238 #endif
239 MODULE_DEPEND(bwi, pci, 1, 1, 1);
240 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
241
242 static const struct {
243 uint16_t did_min;
244 uint16_t did_max;
245 uint16_t bbp_id;
246 } bwi_bbpid_map[] = {
247 { 0x4301, 0x4301, 0x4301 },
248 { 0x4305, 0x4307, 0x4307 },
249 { 0x4403, 0x4403, 0x4402 },
250 { 0x4610, 0x4615, 0x4610 },
251 { 0x4710, 0x4715, 0x4710 },
252 { 0x4720, 0x4725, 0x4309 }
253 };
254
255 static const struct {
256 uint16_t bbp_id;
257 int nregwin;
258 } bwi_regwin_count[] = {
259 { 0x4301, 5 },
260 { 0x4306, 6 },
261 { 0x4307, 5 },
262 { 0x4310, 8 },
263 { 0x4401, 3 },
264 { 0x4402, 3 },
265 { 0x4610, 9 },
266 { 0x4704, 9 },
267 { 0x4710, 9 },
268 { 0x5365, 7 }
269 };
270
271 #define CLKSRC(src) \
272 [BWI_CLKSRC_ ## src] = { \
273 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
274 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
275 }
276
277 static const struct {
278 u_int freq_min;
279 u_int freq_max;
280 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
281 CLKSRC(LP_OSC),
282 CLKSRC(CS_OSC),
283 CLKSRC(PCI)
284 };
285
286 #undef CLKSRC
287
288 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
289
290 static const struct ieee80211_rateset bwi_rateset_11b =
291 { 4, { 2, 4, 11, 22 } };
292 static const struct ieee80211_rateset bwi_rateset_11g =
293 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
294
295 uint16_t
296 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
297 {
298 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
299 }
300
301 static __inline void
302 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
303 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
304 int tx)
305 {
306 struct bwi_desc32 *desc = &desc_array[desc_idx];
307 uint32_t ctrl, addr, addr_hi, addr_lo;
308
309 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
310 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
311
312 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
313 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
314
315 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
316 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
317 if (desc_idx == ndesc - 1)
318 ctrl |= BWI_DESC32_C_EOR;
319 if (tx) {
320 /* XXX */
321 ctrl |= BWI_DESC32_C_FRAME_START |
322 BWI_DESC32_C_FRAME_END |
323 BWI_DESC32_C_INTR;
324 }
325
326 desc->addr = htole32(addr);
327 desc->ctrl = htole32(ctrl);
328 }
329
330 static int
331 bwi_probe(device_t dev)
332 {
333 const struct bwi_dev *b;
334 uint16_t did, vid;
335
336 did = pci_get_device(dev);
337 vid = pci_get_vendor(dev);
338
339 for (b = bwi_devices; b->desc != NULL; ++b) {
340 if (b->did == did && b->vid == vid) {
341 device_set_desc(dev, b->desc);
342 return 0;
343 }
344 }
345 return ENXIO;
346 }
347
348 static int
349 bwi_attach(device_t dev)
350 {
351 struct bwi_softc *sc = device_get_softc(dev);
352 struct ieee80211com *ic = &sc->sc_ic;
353 struct ifnet *ifp = &ic->ic_if;
354 struct bwi_mac *mac;
355 struct bwi_phy *phy;
356 int i, error;
357
358 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
359 sc->sc_dev = dev;
360
361 callout_init(&sc->sc_scan_ch);
362 callout_init(&sc->sc_calib_ch);
363
364 #ifndef BURN_BRIDGES
365 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
366 uint32_t irq, mem;
367
368 /* XXX Save more PCIR */
369 irq = pci_read_config(dev, PCIR_INTLINE, 4);
370 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
371
372 device_printf(dev, "chip is in D%d power mode "
373 "-- setting to D0\n", pci_get_powerstate(dev));
374
375 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
376
377 pci_write_config(dev, PCIR_INTLINE, irq, 4);
378 pci_write_config(dev, BWI_PCIR_BAR, irq, 4);
379 }
380 #endif /* !BURN_BRIDGE */
381
382 pci_enable_busmaster(dev);
383
384 /* Get more PCI information */
385 sc->sc_pci_revid = pci_get_revid(dev);
386 sc->sc_pci_subvid = pci_get_subvendor(dev);
387 sc->sc_pci_subdid = pci_get_subdevice(dev);
388
389 /*
390 * Allocate IO memory
391 */
392 sc->sc_mem_rid = BWI_PCIR_BAR;
393 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
394 &sc->sc_mem_rid, RF_ACTIVE);
395 if (sc->sc_mem_res == NULL) {
396 device_printf(dev, "can't allocate IO memory\n");
397 return ENXIO;
398 }
399 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
400 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
401
402 /*
403 * Allocate IRQ
404 */
405 sc->sc_irq_rid = 0;
406 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
407 &sc->sc_irq_rid,
408 RF_SHAREABLE | RF_ACTIVE);
409 if (sc->sc_irq_res == NULL) {
410 device_printf(dev, "can't allocate irq\n");
411 error = ENXIO;
412 goto fail;
413 }
414
415 bwi_power_on(sc, 1);
416
417 error = bwi_bbp_attach(sc);
418 if (error)
419 goto fail;
420
421 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
422 if (error)
423 goto fail;
424
425 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
426 error = bwi_set_clock_delay(sc);
427 if (error)
428 goto fail;
429
430 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
431 if (error)
432 goto fail;
433
434 error = bwi_get_pwron_delay(sc);
435 if (error)
436 goto fail;
437 }
438
439 error = bwi_bus_attach(sc);
440 if (error)
441 goto fail;
442
443 bwi_get_card_flags(sc);
444
445 /* TODO: LED */
446
447 for (i = 0; i < sc->sc_nmac; ++i) {
448 struct bwi_regwin *old;
449
450 mac = &sc->sc_mac[i];
451 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
452 if (error)
453 goto fail;
454
455 error = bwi_mac_lateattach(mac);
456 if (error)
457 goto fail;
458
459 error = bwi_regwin_switch(sc, old, NULL);
460 if (error)
461 goto fail;
462 }
463
464 /*
465 * XXX First MAC is known to exist
466 * TODO2
467 */
468 mac = &sc->sc_mac[0];
469 phy = &mac->mac_phy;
470
471 bwi_bbp_power_off(sc);
472
473 error = bwi_dma_alloc(sc);
474 if (error)
475 goto fail;
476
477 ifp->if_softc = sc;
478 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
479 ifp->if_init = bwi_init;
480 ifp->if_ioctl = bwi_ioctl;
481 ifp->if_start = bwi_start;
482 ifp->if_watchdog = bwi_watchdog;
483 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
484 ifq_set_ready(&ifp->if_snd);
485
486 /* Get locale */
487 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
488 BWI_SPROM_CARD_INFO_LOCALE);
489 DPRINTF(sc, "locale: %d\n", sc->sc_locale);
490
491 /*
492 * Setup ratesets, phytype, channels and get MAC address
493 */
494 if (phy->phy_mode == IEEE80211_MODE_11B ||
495 phy->phy_mode == IEEE80211_MODE_11G) {
496 uint16_t chan_flags;
497
498 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
499
500 if (phy->phy_mode == IEEE80211_MODE_11B) {
501 chan_flags = IEEE80211_CHAN_B;
502 ic->ic_phytype = IEEE80211_T_DS;
503 } else {
504 chan_flags = IEEE80211_CHAN_CCK |
505 IEEE80211_CHAN_OFDM |
506 IEEE80211_CHAN_DYN |
507 IEEE80211_CHAN_2GHZ;
508 ic->ic_phytype = IEEE80211_T_OFDM;
509 ic->ic_sup_rates[IEEE80211_MODE_11G] =
510 bwi_rateset_11g;
511 }
512
513 /* XXX depend on locale */
514 for (i = 1; i <= 14; ++i) {
515 ic->ic_channels[i].ic_freq =
516 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
517 ic->ic_channels[i].ic_flags = chan_flags;
518 }
519
520 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
521 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
522 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
523 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
524 device_printf(dev, "invalid MAC address: "
525 "%6D\n", ic->ic_myaddr, ":");
526 }
527 }
528 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
529 /* TODO:11A */
530 error = ENXIO;
531 goto fail;
532 } else {
533 panic("unknown phymode %d\n", phy->phy_mode);
534 }
535
536 sc->sc_fw_version = BWI_FW_VERSION3;
537 sc->sc_dwell_time = 200;
538
539 ic->ic_caps = IEEE80211_C_SHSLOT |
540 IEEE80211_C_SHPREAMBLE |
541 IEEE80211_C_WPA |
542 IEEE80211_C_MONITOR;
543 ic->ic_state = IEEE80211_S_INIT;
544 ic->ic_opmode = IEEE80211_M_STA;
545
546 ic->ic_updateslot = bwi_updateslot;
547
548 ieee80211_ifattach(ic);
549
550 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
551 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
552
553 sc->sc_newstate = ic->ic_newstate;
554 ic->ic_newstate = bwi_newstate;
555
556 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
557
558 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
559 &sc->sc_irq_handle, ifp->if_serializer);
560 if (error) {
561 ieee80211_ifdetach(ic);
562 goto fail;
563 }
564
565 if (bootverbose)
566 ieee80211_announce(ic);
567
568 return 0;
569 fail:
570 bwi_detach(dev);
571 return error;
572 }
573
574 static int
575 bwi_detach(device_t dev)
576 {
577 struct bwi_softc *sc = device_get_softc(dev);
578
579 if (device_is_attached(dev)) {
580 struct ifnet *ifp = &sc->sc_ic.ic_if;
581 int i;
582
583 lwkt_serialize_enter(ifp->if_serializer);
584 bwi_stop(sc);
585 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
586 lwkt_serialize_exit(ifp->if_serializer);
587
588 ieee80211_ifdetach(&sc->sc_ic);
589
590 for (i = 0; i < sc->sc_nmac; ++i)
591 bwi_mac_detach(&sc->sc_mac[i]);
592 }
593
594 if (sc->sc_irq_res != NULL) {
595 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
596 sc->sc_irq_res);
597 }
598
599 if (sc->sc_mem_res != NULL) {
600 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
601 sc->sc_mem_res);
602 }
603
604 bwi_dma_free(sc);
605
606 return 0;
607 }
608
609 static int
610 bwi_shutdown(device_t dev)
611 {
612 struct bwi_softc *sc = device_get_softc(dev);
613 struct ifnet *ifp = &sc->sc_ic.ic_if;
614
615 lwkt_serialize_enter(ifp->if_serializer);
616 bwi_stop(sc);
617 lwkt_serialize_exit(ifp->if_serializer);
618 return 0;
619 }
620
621 static void
622 bwi_power_on(struct bwi_softc *sc, int with_pll)
623 {
624 uint32_t gpio_in, gpio_out, gpio_en;
625 uint16_t status;
626
627 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
628 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
629 goto back;
630
631 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
632 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
633
634 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
635 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
636 if (with_pll) {
637 /* Turn off PLL first */
638 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
639 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
640 }
641
642 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
643 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
644 DELAY(1000);
645
646 if (with_pll) {
647 /* Turn on PLL */
648 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
649 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
650 DELAY(5000);
651 }
652
653 back:
654 /* Clear "Signaled Target Abort" */
655 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
656 status &= ~PCIM_STATUS_STABORT;
657 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
658 }
659
660 static int
661 bwi_power_off(struct bwi_softc *sc, int with_pll)
662 {
663 uint32_t gpio_out, gpio_en;
664
665 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
666 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
667 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
668
669 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
670 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
671 if (with_pll) {
672 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
673 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
674 }
675
676 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
677 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
678 return 0;
679 }
680
681 int
682 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
683 struct bwi_regwin **old_rw)
684 {
685 int error;
686
687 if (old_rw != NULL)
688 *old_rw = NULL;
689
690 if (!BWI_REGWIN_EXIST(rw))
691 return EINVAL;
692
693 if (sc->sc_cur_regwin != rw) {
694 error = bwi_regwin_select(sc, rw->rw_id);
695 if (error) {
696 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
697 rw->rw_id);
698 return error;
699 }
700 }
701
702 if (old_rw != NULL)
703 *old_rw = sc->sc_cur_regwin;
704 sc->sc_cur_regwin = rw;
705 return 0;
706 }
707
708 static int
709 bwi_regwin_select(struct bwi_softc *sc, int id)
710 {
711 uint32_t win = BWI_PCIM_REGWIN(id);
712 int i;
713
714 #define RETRY_MAX 50
715 for (i = 0; i < RETRY_MAX; ++i) {
716 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
717 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
718 return 0;
719 DELAY(10);
720 }
721 #undef RETRY_MAX
722
723 return ENXIO;
724 }
725
726 static void
727 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
728 {
729 uint32_t val;
730
731 val = CSR_READ_4(sc, BWI_ID_HI);
732 *type = BWI_ID_HI_REGWIN_TYPE(val);
733 *rev = BWI_ID_HI_REGWIN_REV(val);
734
735 DPRINTF(sc, "regwin: type 0x%03x, rev %d, vendor 0x%04x\n",
736 *type, *rev, __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
737 }
738
739 static int
740 bwi_bbp_attach(struct bwi_softc *sc)
741 {
742 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
743 uint16_t bbp_id, rw_type;
744 uint8_t rw_rev;
745 uint32_t info;
746 int error, nregwin, i;
747
748 /*
749 * Get 0th regwin information
750 * NOTE: 0th regwin should exist
751 */
752 error = bwi_regwin_select(sc, 0);
753 if (error) {
754 device_printf(sc->sc_dev, "can't select regwin 0\n");
755 return error;
756 }
757 bwi_regwin_info(sc, &rw_type, &rw_rev);
758
759 /*
760 * Find out BBP id
761 */
762 bbp_id = 0;
763 info = 0;
764 if (rw_type == BWI_REGWIN_T_COM) {
765 info = CSR_READ_4(sc, BWI_INFO);
766 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
767
768 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
769
770 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
771 } else {
772 uint16_t did = pci_get_device(sc->sc_dev);
773 uint8_t revid = pci_get_revid(sc->sc_dev);
774
775 for (i = 0; i < N(bwi_bbpid_map); ++i) {
776 if (did >= bwi_bbpid_map[i].did_min &&
777 did <= bwi_bbpid_map[i].did_max) {
778 bbp_id = bwi_bbpid_map[i].bbp_id;
779 break;
780 }
781 }
782 if (bbp_id == 0) {
783 device_printf(sc->sc_dev, "no BBP id for device id "
784 "0x%04x\n", did);
785 return ENXIO;
786 }
787
788 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
789 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
790 }
791
792 /*
793 * Find out number of regwins
794 */
795 nregwin = 0;
796 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
797 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
798 } else {
799 for (i = 0; i < N(bwi_regwin_count); ++i) {
800 if (bwi_regwin_count[i].bbp_id == bbp_id) {
801 nregwin = bwi_regwin_count[i].nregwin;
802 break;
803 }
804 }
805 if (nregwin == 0) {
806 device_printf(sc->sc_dev, "no number of win for "
807 "BBP id 0x%04x\n", bbp_id);
808 return ENXIO;
809 }
810 }
811
812 /* Record BBP id/rev for later using */
813 sc->sc_bbp_id = bbp_id;
814 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
815 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
816 device_printf(sc->sc_dev, "BBP id 0x%04x, BBP rev 0x%x, BBP pkg %d\n",
817 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
818
819 DPRINTF(sc, "nregwin %d, cap 0x%08x\n", nregwin, sc->sc_cap);
820
821 /*
822 * Create rest of the regwins
823 */
824
825 /* Don't re-create common regwin, if it is already created */
826 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
827
828 for (; i < nregwin; ++i) {
829 /*
830 * Get regwin information
831 */
832 error = bwi_regwin_select(sc, i);
833 if (error) {
834 device_printf(sc->sc_dev,
835 "can't select regwin %d\n", i);
836 return error;
837 }
838 bwi_regwin_info(sc, &rw_type, &rw_rev);
839
840 /*
841 * Try attach:
842 * 1) Bus (PCI/PCIE) regwin
843 * 2) MAC regwin
844 * Ignore rest types of regwin
845 */
846 if (rw_type == BWI_REGWIN_T_BUSPCI ||
847 rw_type == BWI_REGWIN_T_BUSPCIE) {
848 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
849 device_printf(sc->sc_dev,
850 "bus regwin already exists\n");
851 } else {
852 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
853 rw_type, rw_rev);
854 }
855 } else if (rw_type == BWI_REGWIN_T_MAC) {
856 /* XXX ignore return value */
857 bwi_mac_attach(sc, i, rw_rev);
858 }
859 }
860
861 /* At least one MAC shold exist */
862 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
863 device_printf(sc->sc_dev, "no MAC was found\n");
864 return ENXIO;
865 }
866 KKASSERT(sc->sc_nmac > 0);
867
868 /* Bus regwin must exist */
869 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
870 device_printf(sc->sc_dev, "no bus regwin was found\n");
871 return ENXIO;
872 }
873
874 /* Start with first MAC */
875 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
876 if (error)
877 return error;
878
879 return 0;
880 #undef N
881 }
882
883 int
884 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
885 {
886 struct bwi_regwin *old, *bus;
887 uint32_t val;
888 int error;
889
890 bus = &sc->sc_bus_regwin;
891 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
892
893 /*
894 * Tell bus to generate requested interrupts
895 */
896 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
897 /*
898 * NOTE: Read BWI_FLAGS from MAC regwin
899 */
900 val = CSR_READ_4(sc, BWI_FLAGS);
901
902 error = bwi_regwin_switch(sc, bus, &old);
903 if (error)
904 return error;
905
906 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
907 } else {
908 uint32_t mac_mask;
909
910 mac_mask = 1 << mac->mac_id;
911
912 error = bwi_regwin_switch(sc, bus, &old);
913 if (error)
914 return error;
915
916 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
917 val |= mac_mask << 8;
918 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
919 }
920
921 if (sc->sc_flags & BWI_F_BUS_INITED)
922 goto back;
923
924 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
925 /*
926 * Enable prefetch and burst
927 */
928 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
929 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
930
931 if (bus->rw_rev < 5) {
932 struct bwi_regwin *com = &sc->sc_com_regwin;
933
934 /*
935 * Configure timeouts for bus operation
936 */
937
938 /*
939 * Set service timeout and request timeout
940 */
941 CSR_SETBITS_4(sc, BWI_CONF_LO,
942 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
943 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
944
945 /*
946 * If there is common regwin, we switch to that regwin
947 * and switch back to bus regwin once we have done.
948 */
949 if (BWI_REGWIN_EXIST(com)) {
950 error = bwi_regwin_switch(sc, com, NULL);
951 if (error)
952 return error;
953 }
954
955 /* Let bus know what we have changed */
956 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
957 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
958 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
959 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
960
961 if (BWI_REGWIN_EXIST(com)) {
962 error = bwi_regwin_switch(sc, bus, NULL);
963 if (error)
964 return error;
965 }
966 } else if (bus->rw_rev >= 11) {
967 /*
968 * Enable memory read multiple
969 */
970 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
971 }
972 } else {
973 /* TODO:PCIE */
974 }
975
976 sc->sc_flags |= BWI_F_BUS_INITED;
977 back:
978 return bwi_regwin_switch(sc, old, NULL);
979 }
980
981 static void
982 bwi_get_card_flags(struct bwi_softc *sc)
983 {
984 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
985 if (sc->sc_card_flags == 0xffff)
986 sc->sc_card_flags = 0;
987
988 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
989 sc->sc_pci_subdid == 0x4e && /* XXX */
990 sc->sc_pci_revid > 0x40)
991 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
992
993 DPRINTF(sc, "card flags 0x%04x\n", sc->sc_card_flags);
994 }
995
996 static void
997 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
998 {
999 int i;
1000
1001 for (i = 0; i < 3; ++i) {
1002 *((uint16_t *)eaddr + i) =
1003 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1004 }
1005 }
1006
1007 static void
1008 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1009 {
1010 struct bwi_regwin *com;
1011 uint32_t val;
1012 u_int div;
1013 int src;
1014
1015 bzero(freq, sizeof(*freq));
1016 com = &sc->sc_com_regwin;
1017
1018 KKASSERT(BWI_REGWIN_EXIST(com));
1019 KKASSERT(sc->sc_cur_regwin == com);
1020 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1021
1022 /*
1023 * Calculate clock frequency
1024 */
1025 src = -1;
1026 div = 0;
1027 if (com->rw_rev < 6) {
1028 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1029 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1030 src = BWI_CLKSRC_PCI;
1031 div = 64;
1032 } else {
1033 src = BWI_CLKSRC_CS_OSC;
1034 div = 32;
1035 }
1036 } else if (com->rw_rev < 10) {
1037 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1038
1039 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1040 if (src == BWI_CLKSRC_LP_OSC) {
1041 div = 1;
1042 } else {
1043 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1044
1045 /* Unknown source */
1046 if (src >= BWI_CLKSRC_MAX)
1047 src = BWI_CLKSRC_CS_OSC;
1048 }
1049 } else {
1050 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1051
1052 src = BWI_CLKSRC_CS_OSC;
1053 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1054 }
1055
1056 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1057 KKASSERT(div != 0);
1058
1059 DPRINTF(sc, "clksrc %s\n",
1060 src == BWI_CLKSRC_PCI ? "PCI" :
1061 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1062
1063 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1064 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1065
1066 DPRINTF(sc, "clkfreq min %u, max %u\n",
1067 freq->clkfreq_min, freq->clkfreq_max);
1068 }
1069
1070 static int
1071 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1072 {
1073 struct bwi_regwin *old, *com;
1074 uint32_t clk_ctrl, clk_src;
1075 int error, pwr_off = 0;
1076
1077 com = &sc->sc_com_regwin;
1078 if (!BWI_REGWIN_EXIST(com))
1079 return 0;
1080
1081 if (com->rw_rev >= 10 || com->rw_rev < 6)
1082 return 0;
1083
1084 /*
1085 * For common regwin whose rev is [6, 10), the chip
1086 * must be capable to change clock mode.
1087 */
1088 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1089 return 0;
1090
1091 error = bwi_regwin_switch(sc, com, &old);
1092 if (error)
1093 return error;
1094
1095 if (clk_mode == BWI_CLOCK_MODE_FAST)
1096 bwi_power_on(sc, 0); /* Don't turn on PLL */
1097
1098 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1099 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1100
1101 switch (clk_mode) {
1102 case BWI_CLOCK_MODE_FAST:
1103 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1104 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1105 break;
1106 case BWI_CLOCK_MODE_SLOW:
1107 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1108 break;
1109 case BWI_CLOCK_MODE_DYN:
1110 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1111 BWI_CLOCK_CTRL_IGNPLL |
1112 BWI_CLOCK_CTRL_NODYN);
1113 if (clk_src != BWI_CLKSRC_CS_OSC) {
1114 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1115 pwr_off = 1;
1116 }
1117 break;
1118 }
1119 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1120
1121 if (pwr_off)
1122 bwi_power_off(sc, 0); /* Leave PLL as it is */
1123
1124 return bwi_regwin_switch(sc, old, NULL);
1125 }
1126
1127 static int
1128 bwi_set_clock_delay(struct bwi_softc *sc)
1129 {
1130 struct bwi_regwin *old, *com;
1131 int error;
1132
1133 com = &sc->sc_com_regwin;
1134 if (!BWI_REGWIN_EXIST(com))
1135 return 0;
1136
1137 error = bwi_regwin_switch(sc, com, &old);
1138 if (error)
1139 return error;
1140
1141 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1142 if (sc->sc_bbp_rev == 0)
1143 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1144 else if (sc->sc_bbp_rev == 1)
1145 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1146 }
1147
1148 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1149 if (com->rw_rev >= 10) {
1150 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1151 } else {
1152 struct bwi_clock_freq freq;
1153
1154 bwi_get_clock_freq(sc, &freq);
1155 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1156 howmany(freq.clkfreq_max * 150, 1000000));
1157 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1158 howmany(freq.clkfreq_max * 15, 1000000));
1159 }
1160 }
1161
1162 return bwi_regwin_switch(sc, old, NULL);
1163 }
1164
1165 static void
1166 bwi_init(void *xsc)
1167 {
1168 struct bwi_softc *sc = xsc;
1169 struct ieee80211com *ic = &sc->sc_ic;
1170 struct ifnet *ifp = &ic->ic_if;
1171 struct bwi_mac *mac;
1172 int error;
1173
1174 ASSERT_SERIALIZED(ifp->if_serializer);
1175
1176 DPRINTF(sc, "%s\n", __func__);
1177
1178 error = bwi_stop(sc);
1179 if (error) {
1180 if_printf(ifp, "can't stop\n");
1181 return;
1182 }
1183
1184 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1185
1186 /* TODO: 2 MAC */
1187
1188 mac = &sc->sc_mac[0];
1189 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1190 if (error)
1191 goto back;
1192
1193 error = bwi_mac_init(mac);
1194 if (error)
1195 goto back;
1196
1197 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1198
1199 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1200
1201 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1202 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1203
1204 bwi_mac_reset_hwkeys(mac);
1205
1206 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1207 int i;
1208
1209 #define NRETRY 1000
1210 /*
1211 * Drain any possible pending TX status
1212 */
1213 for (i = 0; i < NRETRY; ++i) {
1214 if ((CSR_READ_4(sc, BWI_TXSTATUS_0) &
1215 BWI_TXSTATUS_0_MORE) == 0)
1216 break;
1217 CSR_READ_4(sc, BWI_TXSTATUS_1);
1218 }
1219 if (i == NRETRY)
1220 if_printf(ifp, "can't drain TX status\n");
1221 #undef NRETRY
1222 }
1223
1224 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1225 bwi_mac_updateslot(mac, 1);
1226
1227 /* Start MAC */
1228 error = bwi_mac_start(mac);
1229 if (error)
1230 goto back;
1231
1232 /* Enable intrs */
1233 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1234
1235 ifp->if_flags |= IFF_RUNNING;
1236 ifp->if_flags &= ~IFF_OACTIVE;
1237
1238 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1239 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1240 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1241 } else {
1242 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1243 }
1244 back:
1245 if (error)
1246 bwi_stop(sc);
1247 }
1248
1249 static int
1250 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1251 {
1252 struct bwi_softc *sc = ifp->if_softc;
1253 int error = 0;
1254
1255 ASSERT_SERIALIZED(ifp->if_serializer);
1256
1257 switch (cmd) {
1258 case SIOCSIFFLAGS:
1259 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1260 (IFF_UP | IFF_RUNNING)) {
1261 struct bwi_mac *mac;
1262 int promisc = -1;
1263
1264 KKASSERT(sc->sc_cur_regwin->rw_type ==
1265 BWI_REGWIN_T_MAC);
1266 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1267
1268 if ((ifp->if_flags & IFF_PROMISC) &&
1269 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1270 promisc = 1;
1271 sc->sc_flags |= BWI_F_PROMISC;
1272 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1273 (sc->sc_flags & BWI_F_PROMISC)) {
1274 promisc = 0;
1275 sc->sc_flags &= ~BWI_F_PROMISC;
1276 }
1277
1278 if (promisc >= 0)
1279 bwi_mac_set_promisc(mac, promisc);
1280 }
1281
1282 if (ifp->if_flags & IFF_UP) {
1283 if ((ifp->if_flags & IFF_RUNNING) == 0)
1284 bwi_init(sc);
1285 } else {
1286 if (ifp->if_flags & IFF_RUNNING)
1287 bwi_stop(sc);
1288 }
1289 break;
1290 default:
1291 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1292 break;
1293 }
1294
1295 if (error == ENETRESET) {
1296 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1297 (IFF_UP | IFF_RUNNING))
1298 bwi_init(sc);
1299 error = 0;
1300 }
1301 return error;
1302 }
1303
1304 static void
1305 bwi_start(struct ifnet *ifp)
1306 {
1307 struct bwi_softc *sc = ifp->if_softc;
1308 struct ieee80211com *ic = &sc->sc_ic;
1309 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1310 int trans, idx;
1311
1312 ASSERT_SERIALIZED(ifp->if_serializer);
1313
1314 if ((ifp->if_flags & IFF_OACTIVE) ||
1315 (ifp->if_flags & IFF_RUNNING) == 0)
1316 return;
1317
1318 trans = 0;
1319 idx = tbd->tbd_idx;
1320
1321 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1322 struct ieee80211_frame *wh;
1323 struct ieee80211_node *ni;
1324 struct mbuf *m;
1325 int mgt_pkt = 0;
1326
1327 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1328 IF_DEQUEUE(&ic->ic_mgtq, m);
1329
1330 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1331 m->m_pkthdr.rcvif = NULL;
1332
1333 mgt_pkt = 1;
1334 } else if (!ifq_is_empty(&ifp->if_snd)) {
1335 struct ether_header *eh;
1336
1337 if (ic->ic_state != IEEE80211_S_RUN)
1338 break;
1339
1340 m = ifq_dequeue(&ifp->if_snd, NULL);
1341 if (m == NULL)
1342 break;
1343
1344 if (m->m_len < sizeof(*eh)) {
1345 m = m_pullup(m, sizeof(*eh));
1346 if (m == NULL) {
1347 ifp->if_oerrors++;
1348 continue;
1349 }
1350 }
1351 eh = mtod(m, struct ether_header *);
1352
1353 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1354 if (ni == NULL) {
1355 m_freem(m);
1356 ifp->if_oerrors++;
1357 continue;
1358 }
1359
1360 /* TODO: PS */
1361
1362 BPF_MTAP(ifp, m);
1363
1364 m = ieee80211_encap(ic, m, ni);
1365 if (m == NULL) {
1366 ieee80211_free_node(ni);
1367 ifp->if_oerrors++;
1368 continue;
1369 }
1370 } else {
1371 break;
1372 }
1373
1374 if (ic->ic_rawbpf != NULL)
1375 bpf_mtap(ic->ic_rawbpf, m);
1376
1377 wh = mtod(m, struct ieee80211_frame *);
1378 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1379 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1380 ieee80211_free_node(ni);
1381 m_freem(m);
1382 ifp->if_oerrors++;
1383 continue;
1384 }
1385 }
1386 wh = NULL; /* Catch any invalid use */
1387
1388 if (mgt_pkt) {
1389 ieee80211_free_node(ni);
1390 ni = NULL;
1391 }
1392
1393 if (bwi_encap(sc, idx, m, ni) != 0) {
1394 /* 'm' is freed in bwi_encap() if we reach here */
1395 if (ni != NULL)
1396 ieee80211_free_node(ni);
1397 ifp->if_oerrors++;
1398 continue;
1399 }
1400
1401 trans = 1;
1402 tbd->tbd_used++;
1403 idx = (idx + 1) % BWI_TX_NDESC;
1404
1405 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1406 ifp->if_flags |= IFF_OACTIVE;
1407 break;
1408 }
1409 }
1410 tbd->tbd_idx = idx;
1411
1412 if (trans)
1413 sc->sc_tx_timer = 5;
1414 ifp->if_timer = 1;
1415 }
1416
1417 static void
1418 bwi_watchdog(struct ifnet *ifp)
1419 {
1420 struct bwi_softc *sc = ifp->if_softc;
1421
1422 ASSERT_SERIALIZED(ifp->if_serializer);
1423
1424 ifp->if_timer = 0;
1425
1426 if ((ifp->if_flags & IFF_RUNNING) == 0)
1427 return;
1428
1429 if (sc->sc_tx_timer) {
1430 if (--sc->sc_tx_timer == 0) {
1431 if_printf(ifp, "watchdog timeout\n");
1432 ifp->if_oerrors++;
1433 /* TODO */
1434 } else {
1435 ifp->if_timer = 1;
1436 }
1437 }
1438 ieee80211_watchdog(&sc->sc_ic);
1439 }
1440
1441 static int
1442 bwi_stop(struct bwi_softc *sc)
1443 {
1444 struct ieee80211com *ic = &sc->sc_ic;
1445 struct ifnet *ifp = &ic->ic_if;
1446 struct bwi_mac *mac;
1447 int i, error, pwr_off = 0;
1448
1449 ASSERT_SERIALIZED(ifp->if_serializer);
1450
1451 DPRINTF(sc, "%s\n", __func__);
1452
1453 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1454
1455 if (ifp->if_flags & IFF_RUNNING) {
1456 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1457 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1458
1459 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1460 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1461 bwi_mac_stop(mac);
1462 }
1463
1464 for (i = 0; i < sc->sc_nmac; ++i) {
1465 struct bwi_regwin *old_rw;
1466
1467 mac = &sc->sc_mac[i];
1468 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1469 continue;
1470
1471 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1472 if (error)
1473 continue;
1474
1475 bwi_mac_shutdown(mac);
1476 pwr_off = 1;
1477
1478 bwi_regwin_switch(sc, old_rw, NULL);
1479 }
1480
1481 if (pwr_off)
1482 bwi_bbp_power_off(sc);
1483
1484 sc->sc_tx_timer = 0;
1485 ifp->if_timer = 0;
1486 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1487 return 0;
1488 }
1489
1490 static void
1491 bwi_intr(void *xsc)
1492 {
1493 struct bwi_softc *sc = xsc;
1494 struct ifnet *ifp = &sc->sc_ic.ic_if;
1495 uint32_t intr_status;
1496 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1497 int i, txrx_error;
1498
1499 ASSERT_SERIALIZED(ifp->if_serializer);
1500
1501 if ((ifp->if_flags & IFF_RUNNING) == 0)
1502 return;
1503
1504 /*
1505 * Get interrupt status
1506 */
1507 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1508 if (intr_status == 0xffffffff) /* Not for us */
1509 return;
1510
1511 #if 0
1512 if_printf(ifp, "intr status 0x%08x\n", intr_status);
1513 #endif
1514
1515 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1516 if (intr_status == 0) /* Nothing is interesting */
1517 return;
1518
1519 txrx_error = 0;
1520 #if 0
1521 if_printf(ifp, "TX/RX intr");
1522 #endif
1523 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1524 uint32_t mask;
1525
1526 if (BWI_TXRX_IS_RX(i))
1527 mask = BWI_TXRX_RX_INTRS;
1528 else
1529 mask = BWI_TXRX_TX_INTRS;
1530
1531 txrx_intr_status[i] =
1532 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1533
1534 #if 0
1535 kprintf(", %d 0x%08x", i, txrx_intr_status[i]);
1536 #endif
1537
1538 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1539 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1540 i, txrx_intr_status[i]);
1541 txrx_error = 1;
1542 }
1543 }
1544 #if 0
1545 kprintf("\n");
1546 #endif
1547
1548 /*
1549 * Acknowledge interrupt
1550 */
1551 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1552
1553 for (i = 0; i < BWI_TXRX_NRING; ++i)
1554 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1555
1556 /* Disable all interrupts */
1557 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1558
1559 if (intr_status & BWI_INTR_PHY_TXERR)
1560 if_printf(ifp, "intr PHY TX error\n");
1561
1562 if (txrx_error) {
1563 /* TODO: reset device */
1564 }
1565
1566 if (intr_status & BWI_INTR_TBTT) {
1567 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1568 bwi_mac_config_ps((struct bwi_mac *)sc->sc_cur_regwin);
1569 }
1570
1571 if (intr_status & BWI_INTR_EO_ATIM)
1572 if_printf(ifp, "EO_ATIM\n");
1573
1574 if (intr_status & BWI_INTR_PMQ) {
1575 for (;;) {
1576 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1577 break;
1578 }
1579 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1580 }
1581
1582 if (intr_status & BWI_INTR_NOISE)
1583 if_printf(ifp, "intr noise\n");
1584
1585 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1586 sc->sc_rxeof(sc);
1587
1588 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX)
1589 sc->sc_txeof_status(sc);
1590
1591 if (intr_status & BWI_INTR_TX_DONE)
1592 bwi_txeof(sc);
1593
1594 /* TODO:LED */
1595
1596 /* Re-enable interrupts */
1597 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1598 }
1599
1600 static int
1601 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1602 {
1603 struct bwi_softc *sc = ic->ic_if.if_softc;
1604 struct ifnet *ifp = &ic->ic_if;
1605 int error;
1606
1607 ASSERT_SERIALIZED(ifp->if_serializer);
1608
1609 callout_stop(&sc->sc_scan_ch);
1610 callout_stop(&sc->sc_calib_ch);
1611
1612 if (nstate == IEEE80211_S_INIT)
1613 goto back;
1614
1615 error = bwi_set_chan(sc, ic->ic_curchan);
1616 if (error) {
1617 if_printf(ifp, "can't set channel to %u\n",
1618 ieee80211_chan2ieee(ic, ic->ic_curchan));
1619 return error;
1620 }
1621
1622 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1623 /* Nothing to do */
1624 } else if (nstate == IEEE80211_S_RUN) {
1625 struct bwi_mac *mac;
1626
1627 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1628
1629 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1630 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1631
1632 /* Initial TX power calibration */
1633 bwi_mac_calibrate_txpower(mac);
1634 } else {
1635 bwi_set_bssid(sc, bwi_zero_addr);
1636 }
1637
1638 back:
1639 error = sc->sc_newstate(ic, nstate, arg);
1640
1641 if (nstate == IEEE80211_S_SCAN) {
1642 callout_reset(&sc->sc_scan_ch,
1643 (sc->sc_dwell_time * hz) / 1000,
1644 bwi_next_scan, sc);
1645 } else if (nstate == IEEE80211_S_RUN) {
1646 /* XXX 15 seconds */
1647 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
1648 }
1649 return error;
1650 }
1651
1652 static int
1653 bwi_media_change(struct ifnet *ifp)
1654 {
1655 int error;
1656
1657 ASSERT_SERIALIZED(ifp->if_serializer);
1658
1659 error = ieee80211_media_change(ifp);
1660 if (error != ENETRESET)
1661 return error;
1662
1663 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1664 bwi_init(ifp->if_softc);
1665 return 0;
1666 }
1667
1668 static int
1669 bwi_dma_alloc(struct bwi_softc *sc)
1670 {
1671 int error, i, has_txstats;
1672 bus_addr_t lowaddr = 0;
1673 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1674 uint32_t txrx_ctrl_step = 0;
1675
1676 has_txstats = 0;
1677 for (i = 0; i < sc->sc_nmac; ++i) {
1678 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1679 has_txstats = 1;
1680 break;
1681 }
1682 }
1683
1684 switch (sc->sc_bus_space) {
1685 case BWI_BUS_SPACE_30BIT:
1686 case BWI_BUS_SPACE_32BIT:
1687 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1688 lowaddr = BWI_BUS_SPACE_MAXADDR;
1689 else
1690 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1691 desc_sz = sizeof(struct bwi_desc32);
1692 txrx_ctrl_step = 0x20;
1693
1694 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1695 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1696 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1697 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1698 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1699 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1700 sc->sc_rxeof = bwi_rxeof32;
1701 sc->sc_start_tx = bwi_start_tx32;
1702 if (has_txstats) {
1703 sc->sc_init_txstats = bwi_init_txstats32;
1704 sc->sc_free_txstats = bwi_free_txstats32;
1705 sc->sc_txeof_status = bwi_txeof_status32;
1706 }
1707 break;
1708
1709 case BWI_BUS_SPACE_64BIT:
1710 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1711 desc_sz = sizeof(struct bwi_desc64);
1712 txrx_ctrl_step = 0x40;
1713
1714 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1715 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1716 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1717 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1718 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1719 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1720 sc->sc_rxeof = bwi_rxeof64;
1721 sc->sc_start_tx = bwi_start_tx64;
1722 if (has_txstats) {
1723 sc->sc_init_txstats = bwi_init_txstats64;
1724 sc->sc_free_txstats = bwi_free_txstats64;
1725 sc->sc_txeof_status = bwi_txeof_status64;
1726 }
1727 break;
1728 }
1729
1730 KKASSERT(lowaddr != 0);
1731 KKASSERT(desc_sz != 0);
1732 KKASSERT(txrx_ctrl_step != 0);
1733
1734 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1735 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1736
1737 /*
1738 * Create top level DMA tag
1739 */
1740 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
1741 lowaddr, BUS_SPACE_MAXADDR,
1742 NULL, NULL,
1743 MAXBSIZE,
1744 BUS_SPACE_UNRESTRICTED,
1745 BUS_SPACE_MAXSIZE_32BIT,
1746 0, &sc->sc_parent_dtag);
1747 if (error) {
1748 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1749 return error;
1750 }
1751
1752 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1753
1754 /*
1755 * Create TX ring DMA stuffs
1756 */
1757 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1758 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1759 NULL, NULL,
1760 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
1761 0, &sc->sc_txring_dtag);
1762 if (error) {
1763 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1764 return error;
1765 }
1766
1767 for (i = 0; i < BWI_TX_NRING; ++i) {
1768 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1769 &sc->sc_tx_rdata[i], tx_ring_sz,
1770 TXRX_CTRL(i));
1771 if (error) {
1772 device_printf(sc->sc_dev, "%dth TX ring "
1773 "DMA alloc failed\n", i);
1774 return error;
1775 }
1776 }
1777
1778 /*
1779 * Create RX ring DMA stuffs
1780 */
1781 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1782 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1783 NULL, NULL,
1784 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
1785 0, &sc->sc_rxring_dtag);
1786 if (error) {
1787 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1788 return error;
1789 }
1790
1791 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1792 rx_ring_sz, TXRX_CTRL(0));
1793 if (error) {
1794 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1795 return error;
1796 }
1797
1798 if (has_txstats) {
1799 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1800 if (error) {
1801 device_printf(sc->sc_dev,
1802 "TX stats DMA alloc failed\n");
1803 return error;
1804 }
1805 }
1806
1807 #undef TXRX_CTRL
1808
1809 return bwi_dma_mbuf_create(sc);
1810 }
1811
1812 static void
1813 bwi_dma_free(struct bwi_softc *sc)
1814 {
1815 if (sc->sc_txring_dtag != NULL) {
1816 int i;
1817
1818 for (i = 0; i < BWI_TX_NRING; ++i) {
1819 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
1820
1821 if (rd->rdata_desc != NULL) {
1822 bus_dmamap_unload(sc->sc_txring_dtag,
1823 rd->rdata_dmap);
1824 bus_dmamem_free(sc->sc_txring_dtag,
1825 rd->rdata_desc,
1826 rd->rdata_dmap);
1827 }
1828 }
1829 bus_dma_tag_destroy(sc->sc_txring_dtag);
1830 }
1831
1832 if (sc->sc_rxring_dtag != NULL) {
1833 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
1834
1835 if (rd->rdata_desc != NULL) {
1836 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
1837 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
1838 rd->rdata_dmap);
1839 }
1840 bus_dma_tag_destroy(sc->sc_rxring_dtag);
1841 }
1842
1843 bwi_dma_txstats_free(sc);
1844 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
1845
1846 if (sc->sc_parent_dtag != NULL)
1847 bus_dma_tag_destroy(sc->sc_parent_dtag);
1848 }
1849
1850 static int
1851 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
1852 struct bwi_ring_data *rd, bus_size_t size,
1853 uint32_t txrx_ctrl)
1854 {
1855 int error;
1856
1857 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
1858 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1859 &rd->rdata_dmap);
1860 if (error) {
1861 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
1862 return error;
1863 }
1864
1865 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
1866 bwi_dma_ring_addr, &rd->rdata_paddr,
1867 BUS_DMA_WAITOK);
1868 if (error) {
1869 device_printf(sc->sc_dev, "can't load DMA mem\n");
1870 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
1871 rd->rdata_desc = NULL;
1872 return error;
1873 }
1874
1875 rd->rdata_txrx_ctrl = txrx_ctrl;
1876 return 0;
1877 }
1878
1879 static int
1880 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
1881 bus_size_t desc_sz)
1882 {
1883 struct bwi_txstats_data *st;
1884 bus_size_t dma_size;
1885 int error;
1886
1887 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
1888 sc->sc_txstats = st;
1889
1890 /*
1891 * Create TX stats descriptor DMA stuffs
1892 */
1893 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
1894
1895 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
1896 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1897 NULL, NULL,
1898 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
1899 0, &st->stats_ring_dtag);
1900 if (error) {
1901 device_printf(sc->sc_dev, "can't create txstats ring "
1902 "DMA tag\n");
1903 return error;
1904 }
1905
1906 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
1907 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1908 &st->stats_ring_dmap);
1909 if (error) {
1910 device_printf(sc->sc_dev, "can't allocate txstats ring "
1911 "DMA mem\n");
1912 bus_dma_tag_destroy(st->stats_ring_dtag);
1913 st->stats_ring_dtag = NULL;
1914 return error;
1915 }
1916
1917 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
1918 st->stats_ring, dma_size,
1919 bwi_dma_ring_addr, &st->stats_ring_paddr,
1920 BUS_DMA_WAITOK);
1921 if (error) {
1922 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
1923 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
1924 st->stats_ring_dmap);
1925 bus_dma_tag_destroy(st->stats_ring_dtag);
1926 st->stats_ring_dtag = NULL;
1927 return error;
1928 }
1929
1930 /*
1931 * Create TX stats DMA stuffs
1932 */
1933 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
1934 BWI_ALIGN);
1935
1936 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
1937 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1938 NULL, NULL,
1939 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
1940 0, &st->stats_dtag);
1941 if (error) {
1942 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
1943 return error;
1944 }
1945
1946 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
1947 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1948 &st->stats_dmap);
1949 if (error) {
1950 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
1951 bus_dma_tag_destroy(st->stats_dtag);
1952 st->stats_dtag = NULL;
1953 return error;
1954 }
1955
1956 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
1957 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
1958 BUS_DMA_WAITOK);
1959 if (error) {
1960 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
1961 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
1962 bus_dma_tag_destroy(st->stats_dtag);
1963 st->stats_dtag = NULL;
1964 return error;
1965 }
1966
1967 st->stats_ctrl_base = ctrl_base;
1968 return 0;
1969 }
1970
1971 static void
1972 bwi_dma_txstats_free(struct bwi_softc *sc)
1973 {
1974 struct bwi_txstats_data *st;
1975
1976 if (sc->sc_txstats == NULL)
1977 return;
1978 st = sc->sc_txstats;
1979
1980 if (st->stats_ring_dtag != NULL) {
1981 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
1982 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
1983 st->stats_ring_dmap);
1984 bus_dma_tag_destroy(st->stats_ring_dtag);
1985 }
1986
1987 if (st->stats_dtag != NULL) {
1988 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
1989 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
1990 bus_dma_tag_destroy(st->stats_dtag);
1991 }
1992
1993 kfree(st, M_DEVBUF);
1994 }
1995
1996 static void
1997 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
1998 {
1999 KASSERT(nseg == 1, ("too many segments\n"));
2000 *((bus_addr_t *)arg) = seg->ds_addr;
2001 }
2002
2003 static int
2004 bwi_dma_mbuf_create(struct bwi_softc *sc)
2005 {
2006 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2007 int i, j, k, ntx, error;
2008
2009 /*
2010 * Create TX/RX mbuf DMA tag
2011 */
2012 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2013 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2014 NULL, NULL, MCLBYTES, 1,
2015 BUS_SPACE_MAXSIZE_32BIT,
2016 0, &sc->sc_buf_dtag);
2017 if (error) {
2018 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2019 return error;
2020 }
2021
2022 ntx = 0;
2023
2024 /*
2025 * Create TX mbuf DMA map
2026 */
2027 for (i = 0; i < BWI_TX_NRING; ++i) {
2028 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2029
2030 for (j = 0; j < BWI_TX_NDESC; ++j) {
2031 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2032 &tbd->tbd_buf[j].tb_dmap);
2033 if (error) {
2034 device_printf(sc->sc_dev, "can't create "
2035 "%dth tbd, %dth DMA map\n", i, j);
2036
2037 ntx = i;
2038 for (k = 0; k < j; ++k) {
2039 bus_dmamap_destroy(sc->sc_buf_dtag,
2040 tbd->tbd_buf[k].tb_dmap);
2041 }
2042 goto fail;
2043 }
2044 }
2045 }
2046 ntx = BWI_TX_NRING;
2047
2048 /*
2049 * Create RX mbuf DMA map and a spare DMA map
2050 */
2051 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2052 &rbd->rbd_tmp_dmap);
2053 if (error) {
2054 device_printf(sc->sc_dev,
2055 "can't create spare RX buf DMA map\n");
2056 goto fail;
2057 }
2058
2059 for (j = 0; j < BWI_RX_NDESC; ++j) {
2060 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2061 &rbd->rbd_buf[j].rb_dmap);
2062 if (error) {
2063 device_printf(sc->sc_dev, "can't create %dth "
2064 "RX buf DMA map\n", j);
2065
2066 for (k = 0; k < j; ++k) {
2067 bus_dmamap_destroy(sc->sc_buf_dtag,
2068 rbd->rbd_buf[j].rb_dmap);
2069 }
2070 bus_dmamap_destroy(sc->sc_buf_dtag,
2071 rbd->rbd_tmp_dmap);
2072 goto fail;
2073 }
2074 }
2075
2076 return 0;
2077 fail:
2078 bwi_dma_mbuf_destroy(sc, ntx, 0);
2079 return error;
2080 }
2081
2082 static void
2083 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2084 {
2085 int i, j;
2086
2087 if (sc->sc_buf_dtag == NULL)
2088 return;
2089
2090 for (i = 0; i < ntx; ++i) {
2091 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2092
2093 for (j = 0; j < BWI_TX_NDESC; ++j) {
2094 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2095
2096 if (tb->tb_mbuf != NULL) {
2097 bus_dmamap_unload(sc->sc_buf_dtag,
2098 tb->tb_dmap);
2099 m_freem(tb->tb_mbuf);
2100 }
2101 if (tb->tb_ni != NULL)
2102 ieee80211_free_node(tb->tb_ni);
2103 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2104 }
2105 }
2106
2107 if (nrx) {
2108 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2109
2110 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2111 for (j = 0; j < BWI_RX_NDESC; ++j) {
2112 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2113
2114 if (rb->rb_mbuf != NULL) {
2115 bus_dmamap_unload(sc->sc_buf_dtag,
2116 rb->rb_dmap);
2117 m_freem(rb->rb_mbuf);
2118 }
2119 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2120 }
2121 }
2122
2123 bus_dma_tag_destroy(sc->sc_buf_dtag);
2124 sc->sc_buf_dtag = NULL;
2125 }
2126
2127 static void
2128 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2129 {
2130 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2131 }
2132
2133 static void
2134 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2135 {
2136 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2137 }
2138
2139 static int
2140 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2141 {
2142 struct bwi_ring_data *rd;
2143 struct bwi_txbuf_data *tbd;
2144 uint32_t val, addr_hi, addr_lo;
2145
2146 KKASSERT(ring_idx < BWI_TX_NRING);
2147 rd = &sc->sc_tx_rdata[ring_idx];
2148 tbd = &sc->sc_tx_bdata[ring_idx];
2149
2150 tbd->tbd_idx = 0;
2151 tbd->tbd_used = 0;
2152
2153 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2154 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2155 BUS_DMASYNC_PREWRITE);
2156
2157 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2158 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2159
2160 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2161 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2162 BWI_TXRX32_RINGINFO_FUNC_MASK);
2163 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2164
2165 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2166 BWI_TXRX32_CTRL_ENABLE;
2167 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2168
2169 return 0;
2170 }
2171
2172 static void
2173 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2174 bus_addr_t paddr, int hdr_size, int ndesc)
2175 {
2176 uint32_t val, addr_hi, addr_lo;
2177
2178 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2179 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2180
2181 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2182 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2183 BWI_TXRX32_RINGINFO_FUNC_MASK);
2184 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2185
2186 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2187 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2188 BWI_TXRX32_CTRL_ENABLE;
2189 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2190
2191 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2192 (ndesc - 1) * sizeof(struct bwi_desc32));
2193 }
2194
2195 static int
2196 bwi_init_rx_ring32(struct bwi_softc *sc)
2197 {
2198 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2199 int i, error;
2200
2201 sc->sc_rx_bdata.rbd_idx = 0;
2202
2203 for (i = 0; i < BWI_RX_NDESC; ++i) {
2204 error = bwi_newbuf(sc, i, 1);
2205 if (error) {
2206 if_printf(&sc->sc_ic.ic_if,
2207 "can't allocate %dth RX buffer\n", i);
2208 return error;
2209 }
2210 }
2211 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2212 BUS_DMASYNC_PREWRITE);
2213
2214 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2215 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2216 return 0;
2217 }
2218
2219 static int
2220 bwi_init_txstats32(struct bwi_softc *sc)
2221 {
2222 struct bwi_txstats_data *st = sc->sc_txstats;
2223 bus_addr_t stats_paddr;
2224 int i;
2225
2226 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2227 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2228
2229 st->stats_idx = 0;
2230
2231 stats_paddr = st->stats_paddr;
2232 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2233 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2234 stats_paddr, sizeof(struct bwi_txstats), 0);
2235 stats_paddr += sizeof(struct bwi_txstats);
2236 }
2237 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2238 BUS_DMASYNC_PREWRITE);
2239
2240 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2241 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2242 return 0;
2243 }
2244
2245 static void
2246 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2247 int buf_len)
2248 {
2249 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2250
2251 KKASSERT(buf_idx < BWI_RX_NDESC);
2252 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2253 paddr, buf_len, 0);
2254 }
2255
2256 static void
2257 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2258 int buf_idx, bus_addr_t paddr, int buf_len)
2259 {
2260 KKASSERT(buf_idx < BWI_TX_NDESC);
2261 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2262 paddr, buf_len, 1);
2263 }
2264
2265 static int
2266 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2267 {
2268 /* TODO:64 */
2269 return EOPNOTSUPP;
2270 }
2271
2272 static int
2273 bwi_init_rx_ring64(struct bwi_softc *sc)
2274 {
2275 /* TODO:64 */
2276 return EOPNOTSUPP;
2277 }
2278
2279 static int
2280 bwi_init_txstats64(struct bwi_softc *sc)
2281 {
2282 /* TODO:64 */
2283 return EOPNOTSUPP;
2284 }
2285
2286 static void
2287 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2288 int buf_len)
2289 {
2290 /* TODO:64 */
2291 }
2292
2293 static void
2294 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2295 int buf_idx, bus_addr_t paddr, int buf_len)
2296 {
2297 /* TODO:64 */
2298 }
2299
2300 static void
2301 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2302 bus_size_t mapsz __unused, int error)
2303 {
2304 if (!error) {
2305 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2306 *((bus_addr_t *)arg) = seg->ds_addr;
2307 }
2308 }
2309
2310 static int
2311 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2312 {
2313 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2314 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2315 struct bwi_rxbuf_hdr *hdr;
2316 bus_dmamap_t map;
2317 bus_addr_t paddr;
2318 struct mbuf *m;
2319 int error;
2320
2321 KKASSERT(buf_idx < BWI_RX_NDESC);
2322
2323 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2324 if (m == NULL) {
2325 error = ENOBUFS;
2326
2327 /*
2328 * If the NIC is up and running, we need to:
2329 * - Clear RX buffer's header.
2330 * - Restore RX descriptor settings.
2331 */
2332 if (init)
2333 return error;
2334 else
2335 goto back;
2336 }
2337 m->m_len = m->m_pkthdr.len = MCLBYTES;
2338
2339 /*
2340 * Try to load RX buf into temporary DMA map
2341 */
2342 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2343 bwi_dma_buf_addr, &paddr,
2344 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2345 if (error) {
2346 m_freem(m);
2347
2348 /*
2349 * See the comment above
2350 */
2351 if (init)
2352 return error;
2353 else
2354 goto back;
2355 }
2356
2357 if (!init)
2358 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2359 rxbuf->rb_mbuf = m;
2360 rxbuf->rb_paddr = paddr;
2361
2362 /*
2363 * Swap RX buf's DMA map with the loaded temporary one
2364 */
2365 map = rxbuf->rb_dmap;
2366 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2367 rbd->rbd_tmp_dmap = map;
2368
2369 back:
2370 /*
2371 * Clear RX buf header
2372 */
2373 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2374 bzero(hdr, sizeof(*hdr));
2375 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2376
2377 /*
2378 * Setup RX buf descriptor
2379 */
2380 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2381 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2382 return error;
2383 }
2384
2385 static void
2386 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2387 const uint8_t *addr)
2388 {
2389 int i;
2390
2391 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2392 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2393
2394 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2395 uint16_t addr_val;
2396
2397 addr_val = (uint16_t)addr[i * 2] |
2398 (((uint16_t)addr[(i * 2) + 1]) << 8);
2399 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2400 }
2401 }
2402
2403 static int
2404 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2405 {
2406 struct ieee80211com *ic = &sc->sc_ic;
2407 struct ifnet *ifp = &ic->ic_if;
2408 struct bwi_mac *mac;
2409 u_int chan;
2410
2411 ASSERT_SERIALIZED(ifp->if_serializer);
2412
2413 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2414 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2415
2416 chan = ieee80211_chan2ieee(ic, c);
2417
2418 bwi_rf_set_chan(mac, chan, 0);
2419
2420 /* TODO: radio tap */
2421
2422 return 0;
2423 }
2424
2425 static void
2426 bwi_next_scan(void *xsc)
2427 {
2428 struct bwi_softc *sc = xsc;
2429 struct ieee80211com *ic = &sc->sc_ic;
2430 struct ifnet *ifp = &ic->ic_if;
2431
2432 lwkt_serialize_enter(ifp->if_serializer);
2433
2434 if (ic->ic_state == IEEE80211_S_SCAN)
2435 ieee80211_next_scan(ic);
2436
2437 lwkt_serialize_exit(ifp->if_serializer);
2438 }
2439
2440 static void
2441 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2442 {
2443 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2444 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2445 struct ieee80211com *ic = &sc->sc_ic;
2446 struct ifnet *ifp = &ic->ic_if;
2447 int idx;
2448
2449 idx = rbd->rbd_idx;
2450 while (idx != end_idx) {
2451 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2452 struct bwi_rxbuf_hdr *hdr;
2453 struct ieee80211_frame_min *wh;
2454 struct ieee80211_node *ni;
2455 struct mbuf *m;
2456 uint8_t plcp_signal;
2457 uint16_t flags2;
2458 int buflen, wh_ofs, hdr_extra;
2459
2460 m = rb->rb_mbuf;
2461 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2462 BUS_DMASYNC_POSTREAD);
2463
2464 if (bwi_newbuf(sc, idx, 0)) {
2465 ifp->if_ierrors++;
2466 goto next;
2467 }
2468
2469 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2470 flags2 = le16toh(hdr->rxh_flags2);
2471
2472 hdr_extra = 0;
2473 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2474 hdr_extra = 2;
2475 wh_ofs = hdr_extra + 6;
2476
2477 buflen = le16toh(hdr->rxh_buflen);
2478 if (buflen <= wh_ofs) {
2479 if_printf(ifp, "zero length data, hdr_extra %d\n",
2480 hdr_extra);
2481 ifp->if_ierrors++;
2482 m_freem(m);
2483 goto next;
2484 }
2485
2486 plcp_signal = *((uint8_t *)(hdr + 1) + hdr_extra);
2487
2488 m->m_pkthdr.rcvif = ifp;
2489 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2490 m_adj(m, sizeof(*hdr) + wh_ofs);
2491
2492 /* TODO: radio tap */
2493
2494 m_adj(m, -IEEE80211_CRC_LEN);
2495
2496 wh = mtod(m, struct ieee80211_frame_min *);
2497 ni = ieee80211_find_rxnode(ic, wh);
2498
2499 ieee80211_input(ic, m, ni, hdr->rxh_rssi,
2500 le16toh(hdr->rxh_tsf));
2501
2502 ieee80211_free_node(ni);
2503 next:
2504 idx = (idx + 1) % BWI_RX_NDESC;
2505 }
2506
2507 rbd->rbd_idx = idx;
2508 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2509 BUS_DMASYNC_PREWRITE);
2510 }
2511
2512 static void
2513 bwi_rxeof32(struct bwi_softc *sc)
2514 {
2515 uint32_t val, rx_ctrl;
2516 int end_idx;
2517
2518 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2519
2520 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2521 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2522 sizeof(struct bwi_desc32);
2523
2524 bwi_rxeof(sc, end_idx);
2525
2526 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2527 end_idx * sizeof(struct bwi_desc32));
2528 }
2529
2530 static void
2531 bwi_rxeof64(struct bwi_softc *sc)
2532 {
2533 /* TODO:64 */
2534 }
2535
2536 static void
2537 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2538 {
2539 int i;
2540
2541 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2542
2543 #define NRETRY 10
2544
2545 for (i = 0; i < NRETRY; ++i) {
2546 uint32_t status;
2547
2548 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2549 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2550 BWI_RX32_STATUS_STATE_DISABLED)
2551 break;
2552
2553 DELAY(1000);
2554 }
2555 if (i == NRETRY)
2556 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2557
2558 #undef NRETRY
2559
2560 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2561 }
2562
2563 static void
2564 bwi_free_txstats32(struct bwi_softc *sc)
2565 {
2566 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2567 }
2568
2569 static void
2570 bwi_free_rx_ring32(struct bwi_softc *sc)
2571 {
2572 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2573 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2574 int i;
2575
2576 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2577
2578 for (i = 0; i < BWI_RX_NDESC; ++i) {
2579 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2580
2581 if (rb->rb_mbuf != NULL) {
2582 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2583 m_freem(rb->rb_mbuf);
2584 rb->rb_mbuf = NULL;
2585 }
2586 }
2587 }
2588
2589 static void
2590 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2591 {
2592 struct bwi_ring_data *rd;
2593 struct bwi_txbuf_data *tbd;
2594 struct ifnet *ifp = &sc->sc_ic.ic_if;
2595 uint32_t state, val;
2596 int i;
2597
2598 KKASSERT(ring_idx < BWI_TX_NRING);
2599 rd = &sc->sc_tx_rdata[ring_idx];
2600 tbd = &sc->sc_tx_bdata[ring_idx];
2601
2602 #define NRETRY 10
2603
2604 for (i = 0; i < NRETRY; ++i) {
2605 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2606 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2607 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2608 state == BWI_TX32_STATUS_STATE_IDLE ||
2609 state == BWI_TX32_STATUS_STATE_STOPPED)
2610 break;
2611
2612 DELAY(1000);
2613 }
2614 if (i == NRETRY) {
2615 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2616 ring_idx);
2617 }
2618
2619 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2620 for (i = 0; i < NRETRY; ++i) {
2621 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2622 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2623 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2624 break;
2625
2626 DELAY(1000);
2627 }
2628 if (i == NRETRY)
2629 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2630
2631 #undef NRETRY
2632
2633 DELAY(1000);
2634
2635 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2636
2637 for (i = 0; i < BWI_TX_NDESC; ++i) {
2638 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2639
2640 if (tb->tb_mbuf != NULL) {
2641 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2642 m_freem(tb->tb_mbuf);
2643 tb->tb_mbuf = NULL;
2644 }
2645 if (tb->tb_ni != NULL) {
2646 ieee80211_free_node(tb->tb_ni);
2647 tb->tb_ni = NULL;
2648 }
2649 }
2650 }
2651
2652 static void
2653 bwi_free_txstats64(struct bwi_softc *sc)
2654 {
2655 /* TODO:64 */
2656 }
2657
2658 static void
2659 bwi_free_rx_ring64(struct bwi_softc *sc)
2660 {
2661 /* TODO:64 */
2662 }
2663
2664 static void
2665 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2666 {
2667 /* TODO:64 */
2668 }
2669
2670 /* XXX does not belong here */
2671 uint8_t
2672 bwi_rate2plcp(uint8_t rate)
2673 {
2674 rate &= IEEE80211_RATE_VAL;
2675
2676 switch (rate) {
2677 case 2: return 0xa;
2678 case 4: return 0x14;
2679 case 11: return 0x37;
2680 case 22: return 0x6e;
2681 case 44: return 0xdc;
2682
2683 case 12: return 0xb;
2684 case 18: return 0xf;
2685 case 24: return 0xa;
2686 case 36: return 0xe;
2687 case 48: return 0x9;
2688 case 72: return 0xd;
2689 case 96: return 0x8;
2690 case 108: return 0xc;
2691
2692 default:
2693 panic("unsupported rate %u\n", rate);
2694 }
2695 }
2696
2697 static __inline void
2698 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2699 {
2700 /* XXX does not belong here */
2701 #define IEEE80211_OFDM_PLCP_SIG_MASK __BITS(3, 0)
2702 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2703
2704 uint32_t plcp;
2705
2706 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_SIG_MASK) |
2707 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2708 *plcp0 = htole32(plcp);
2709 }
2710
2711 /* XXX does not belong here */
2712 struct ieee80211_ds_plcp_hdr {
2713 uint8_t i_signal;
2714 uint8_t i_service;
2715 uint16_t i_length;
2716 uint16_t i_crc;
2717 } __packed;
2718
2719 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
2720 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
2721 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
2722 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
2723 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
2724
2725 static __inline void
2726 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2727 uint8_t rate)
2728 {
2729 int len, service, pkt_bitlen;
2730
2731 pkt_bitlen = pkt_len * NBBY;
2732 len = howmany(pkt_bitlen * 2, rate);
2733
2734 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
2735 if (rate == (11 * 2)) {
2736 int pkt_bitlen1;
2737
2738 /*
2739 * PLCP service field needs to be adjusted,
2740 * if TX rate is 11Mbytes/s
2741 */
2742 pkt_bitlen1 = len * 11;
2743 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2744 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
2745 }
2746
2747 plcp->i_signal = bwi_rate2plcp(rate);
2748 plcp->i_service = service;
2749 plcp->i_length = htole16(len);
2750 /* NOTE: do NOT touch i_crc */
2751 }
2752
2753 static __inline void
2754 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
2755 {
2756 enum ieee80211_modtype modtype;
2757
2758 /*
2759 * Assume caller has zeroed 'plcp'
2760 */
2761
2762 modtype = ieee80211_rate2modtype(rate);
2763 if (modtype == IEEE80211_MODTYPE_OFDM)
2764 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2765 else if (modtype == IEEE80211_MODTYPE_DS)
2766 bwi_ds_plcp_header(plcp, pkt_len, rate);
2767 else
2768 panic("unsupport modulation type %u\n", modtype);
2769 }
2770
2771 static int
2772 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2773 struct ieee80211_node *ni)
2774 {
2775 struct ieee80211com *ic = &sc->sc_ic;
2776 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2777 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2778 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2779 struct bwi_mac *mac;
2780 struct bwi_txbuf_hdr *hdr;
2781 struct ieee80211_frame *wh;
2782 uint8_t rate, rate_fb;
2783 uint32_t mac_ctrl;
2784 uint16_t phy_ctrl;
2785 bus_addr_t paddr;
2786 int pkt_len, error;
2787 #if 0
2788 const uint8_t *p;
2789 int i;
2790 #endif
2791
2792 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2793 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2794
2795 wh = mtod(m, struct ieee80211_frame *);
2796
2797 /* Get 802.11 frame len before prepending TX header */
2798 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2799
2800 /*
2801 * Find TX rate
2802 */
2803 bzero(tb->tb_rate_idx, sizeof(tb->tb_rate_idx));
2804 if (ni != NULL) {
2805 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
2806 int idx;
2807
2808 rate = IEEE80211_RS_RATE(&ni->ni_rates,
2809 ic->ic_fixed_rate);
2810
2811 if (ic->ic_fixed_rate >= 1)
2812 idx = ic->ic_fixed_rate - 1;
2813 else
2814 idx = 0;
2815 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
2816 } else {
2817 /* TODO: TX rate control */
2818 rate = rate_fb = (1 * 2);
2819 }
2820 } else {
2821 /* Fixed at 1Mbytes/s for mgt frames */
2822 rate = rate_fb = (1 * 2);
2823 }
2824
2825 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
2826 rate = rate_fb = ic->ic_mcast_rate;
2827
2828 if (rate == 0 || rate_fb == 0) {
2829 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
2830 rate, rate_fb);
2831 rate = rate_fb = (1 * 2); /* Force 1Mbytes/s */
2832 }
2833
2834 /* TODO: radio tap */
2835
2836 /*
2837 * Setup the embedded TX header
2838 */
2839 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
2840 if (m == NULL) {
2841 if_printf(&ic->ic_if, "prepend TX header failed\n");
2842 return ENOBUFS;
2843 }
2844 hdr = mtod(m, struct bwi_txbuf_hdr *);
2845
2846 bzero(hdr, sizeof(*hdr));
2847
2848 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
2849 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
2850
2851 if (ni != NULL && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2852 uint16_t dur;
2853 uint8_t ack_rate;
2854
2855 ack_rate = ieee80211_ack_rate(ni, rate_fb);
2856 dur = ieee80211_txtime(ni,
2857 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
2858 ack_rate, ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
2859
2860 hdr->txh_fb_duration = htole16(dur);
2861 }
2862
2863 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
2864 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
2865
2866 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
2867 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
2868
2869 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
2870 BWI_TXH_PHY_C_ANTMODE_MASK);
2871 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
2872 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
2873 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
2874 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
2875
2876 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
2877 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
2878 mac_ctrl |= BWI_TXH_MAC_C_ACK;
2879 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
2880 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
2881
2882 hdr->txh_mac_ctrl = htole32(mac_ctrl);
2883 hdr->txh_phy_ctrl = htole16(phy_ctrl);
2884
2885 /* Catch any further usage */
2886 hdr = NULL;
2887 wh = NULL;
2888
2889 /* DMA load */
2890 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
2891 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2892 if (error && error != EFBIG) {
2893 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
2894 goto back;
2895 }
2896
2897 if (error) { /* error == EFBIG */
2898 struct mbuf *m_new;
2899
2900 m_new = m_defrag(m, MB_DONTWAIT);
2901 if (m_new == NULL) {
2902 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
2903 error = ENOBUFS;
2904 goto back;
2905 } else {
2906 m = m_new;
2907 }
2908
2909 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
2910 bwi_dma_buf_addr, &paddr,
2911 BUS_DMA_NOWAIT);
2912 if (error) {
2913 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
2914 error);
2915 goto back;
2916 }
2917 }
2918 error = 0;
2919
2920 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
2921
2922 tb->tb_mbuf = m;
2923 tb->tb_ni = ni;
2924
2925 #if 0
2926 p = mtod(m, const uint8_t *);
2927 for (i = 0; i < m->m_pkthdr.len; ++i) {
2928 if (i != 0 && i % 8 == 0)
2929 kprintf("\n");
2930 kprintf("%02x ", p[i]);
2931 }
2932 kprintf("\n");
2933
2934 if_printf(&ic->ic_if, "idx %d, pkt_len %d, buflen %d\n",
2935 idx, pkt_len, m->m_pkthdr.len);
2936 #endif
2937
2938 /* Setup TX descriptor */
2939 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
2940 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2941 BUS_DMASYNC_PREWRITE);
2942
2943 /* Kick start */
2944 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
2945
2946 back:
2947 if (error)
2948 m_freem(m);
2949 return error;
2950 }
2951
2952 static void
2953 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
2954 {
2955 idx = (idx + 1) % BWI_TX_NDESC;
2956 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
2957 idx * sizeof(struct bwi_desc32));
2958 }
2959
2960 static void
2961 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
2962 {
2963 /* TODO:64 */
2964 }
2965
2966 static void
2967 bwi_txeof_status32(struct bwi_softc *sc)
2968 {
2969 struct ifnet *ifp = &sc->sc_ic.ic_if;
2970 uint32_t val, ctrl_base;
2971 int end_idx;
2972
2973 ctrl_base = sc->sc_txstats->stats_ctrl_base;
2974
2975 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
2976 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2977 sizeof(struct bwi_desc32);
2978
2979 bwi_txeof_status(sc, end_idx);
2980
2981 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2982 end_idx * sizeof(struct bwi_desc32));
2983
2984 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2985 ifp->if_start(ifp);
2986 }
2987
2988 static void
2989 bwi_txeof_status64(struct bwi_softc *sc)
2990 {
2991 /* TODO:64 */
2992 }
2993
2994 static void
2995 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id)
2996 {
2997 struct ifnet *ifp = &sc->sc_ic.ic_if;
2998 struct bwi_txbuf_data *tbd;
2999 struct bwi_txbuf *tb;
3000 int ring_idx, buf_idx;
3001
3002 if (tx_id == 0) {
3003 if_printf(ifp, "zero tx id\n");
3004 return;
3005 }
3006
3007 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3008 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3009
3010 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3011 KKASSERT(buf_idx < BWI_TX_NDESC);
3012 #if 0
3013 if_printf(ifp, "txeof idx %d\n", buf_idx);
3014 #endif
3015
3016 tbd = &sc->sc_tx_bdata[ring_idx];
3017 KKASSERT(tbd->tbd_used > 0);
3018 tbd->tbd_used--;
3019
3020 tb = &tbd->tbd_buf[buf_idx];
3021
3022 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3023 m_freem(tb->tb_mbuf);
3024 tb->tb_mbuf = NULL;
3025
3026 if (tb->tb_ni != NULL) {
3027 ieee80211_free_node(tb->tb_ni);
3028 tb->tb_ni = NULL;
3029 }
3030
3031 if (tbd->tbd_used == 0)
3032 sc->sc_tx_timer = 0;
3033
3034 ifp->if_flags &= ~IFF_OACTIVE;
3035 }
3036
3037 static void
3038 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3039 {
3040 struct bwi_txstats_data *st = sc->sc_txstats;
3041 int idx;
3042
3043 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3044
3045 idx = st->stats_idx;
3046 while (idx != end_idx) {
3047 _bwi_txeof(sc, le16toh(st->stats[idx].txs_id));
3048 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3049 }
3050 st->stats_idx = idx;
3051 }
3052
3053 static void
3054 bwi_txeof(struct bwi_softc *sc)
3055 {
3056 struct ifnet *ifp = &sc->sc_ic.ic_if;
3057
3058 for (;;) {
3059 uint32_t tx_status0, tx_status1;
3060 uint16_t tx_id, tx_info;
3061
3062 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS_0);
3063 if (tx_status0 == 0)
3064 break;
3065 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS_1);
3066
3067 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS_0_TXID_MASK);
3068 tx_info = BWI_TXSTATUS_0_INFO(tx_status0);
3069
3070 if (tx_info & 0x30) /* XXX */
3071 continue;
3072
3073 _bwi_txeof(sc, tx_id);
3074 }
3075
3076 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3077 ifp->if_start(ifp);
3078 }
3079
3080 static int
3081 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3082 {
3083 bwi_power_on(sc, 1);
3084 return bwi_set_clock_mode(sc, clk_mode);
3085 }
3086
3087 static void
3088 bwi_bbp_power_off(struct bwi_softc *sc)
3089 {
3090 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3091 bwi_power_off(sc, 1);
3092 }
3093
3094 static int
3095 bwi_get_pwron_delay(struct bwi_softc *sc)
3096 {
3097 struct bwi_regwin *com, *old;
3098 struct bwi_clock_freq freq;
3099 uint32_t val;
3100 int error;
3101
3102 com = &sc->sc_com_regwin;
3103 KKASSERT(BWI_REGWIN_EXIST(com));
3104
3105 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3106 return 0;
3107
3108 error = bwi_regwin_switch(sc, com, &old);
3109 if (error)
3110 return error;
3111
3112 bwi_get_clock_freq(sc, &freq);
3113
3114 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3115 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3116 DPRINTF(sc, "power on delay %u\n", sc->sc_pwron_delay);
3117
3118 return bwi_regwin_switch(sc, old, NULL);
3119 }
3120
3121 static int
3122 bwi_bus_attach(struct bwi_softc *sc)
3123 {
3124 struct bwi_regwin *bus, *old;
3125 int error;
3126
3127 bus = &sc->sc_bus_regwin;
3128
3129 error = bwi_regwin_switch(sc, bus, &old);
3130 if (error)
3131 return error;
3132
3133 if (!bwi_regwin_is_enabled(sc, bus))
3134 bwi_regwin_enable(sc, bus, 0);
3135
3136 /* Disable interripts */
3137 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3138
3139 return bwi_regwin_switch(sc, old, NULL);
3140 }
3141
3142 static const char *
3143 bwi_regwin_name(const struct bwi_regwin *rw)
3144 {
3145 switch (rw->rw_type) {
3146 case BWI_REGWIN_T_COM:
3147 return "COM";
3148 case BWI_REGWIN_T_BUSPCI:
3149 return "PCI";
3150 case BWI_REGWIN_T_MAC:
3151 return "MAC";
3152 case BWI_REGWIN_T_BUSPCIE:
3153 return "PCIE";
3154 }
3155 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3156 return NULL;
3157 }
3158
3159 static uint32_t
3160 bwi_regwin_disable_bits(struct bwi_softc *sc)
3161 {
3162 uint32_t busrev;
3163
3164 /* XXX cache this */
3165 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3166 DPRINTF(sc, "bus rev %u\n", busrev);
3167
3168 if (busrev == BWI_BUSREV_0)
3169 return BWI_STATE_LO_DISABLE1;
3170 else if (busrev == BWI_BUSREV_1)
3171 return BWI_STATE_LO_DISABLE2;
3172 else
3173 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3174 }
3175
3176 int
3177 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3178 {
3179 uint32_t val, disable_bits;
3180
3181 disable_bits = bwi_regwin_disable_bits(sc);
3182 val = CSR_READ_4(sc, BWI_STATE_LO);
3183
3184 if ((val & (BWI_STATE_LO_CLOCK |
3185 BWI_STATE_LO_RESET |
3186 disable_bits)) == BWI_STATE_LO_CLOCK) {
3187 DPRINTF(sc, "%s is enabled\n", bwi_regwin_name(rw));
3188 return 1;
3189 } else {
3190 DPRINTF(sc, "%s is disabled\n", bwi_regwin_name(rw));
3191 return 0;
3192 }
3193 }
3194
3195 void
3196 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3197 {
3198 uint32_t state_lo, disable_bits;
3199 int i;
3200
3201 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3202
3203 /*
3204 * If current regwin is in 'reset' state, it was already disabled.
3205 */
3206 if (state_lo & BWI_STATE_LO_RESET) {
3207 DPRINTF(sc, "%s was already disabled\n", bwi_regwin_name(rw));
3208 return;
3209 }
3210
3211 disable_bits = bwi_regwin_disable_bits(sc);
3212
3213 /*
3214 * Disable normal clock
3215 */
3216 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3217 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3218
3219 /*
3220 * Wait until normal clock is disabled
3221 */
3222 #define NRETRY 1000
3223 for (i = 0; i < NRETRY; ++i) {
3224 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3225 if (state_lo & disable_bits)
3226 break;
3227 DELAY(10);
3228 }
3229 if (i == NRETRY) {
3230 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3231 bwi_regwin_name(rw));
3232 }
3233
3234 for (i = 0; i < NRETRY; ++i) {
3235 uint32_t state_hi;
3236
3237 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3238 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3239 break;
3240 DELAY(10);
3241 }
3242 if (i == NRETRY) {
3243 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3244 bwi_regwin_name(rw));
3245 }
3246 #undef NRETRY
3247
3248 /*
3249 * Reset and disable regwin with gated clock
3250 */
3251 state_lo = BWI_STATE_LO_RESET | disable_bits |
3252 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3253 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3254 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3255
3256 /* Flush pending bus write */
3257 CSR_READ_4(sc, BWI_STATE_LO);
3258 DELAY(1);
3259
3260 /* Reset and disable regwin */
3261 state_lo = BWI_STATE_LO_RESET | disable_bits |
3262 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3263 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3264
3265 /* Flush pending bus write */
3266 CSR_READ_4(sc, BWI_STATE_LO);
3267 DELAY(1);
3268 }
3269
3270 void
3271 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3272 {
3273 uint32_t state_lo, state_hi, imstate;
3274
3275 bwi_regwin_disable(sc, rw, flags);
3276
3277 /* Reset regwin with gated clock */
3278 state_lo = BWI_STATE_LO_RESET |
3279 BWI_STATE_LO_CLOCK |
3280 BWI_STATE_LO_GATED_CLOCK |
3281 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3282 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3283
3284 /* Flush pending bus write */
3285 CSR_READ_4(sc, BWI_STATE_LO);
3286 DELAY(1);
3287
3288 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3289 if (state_hi & BWI_STATE_HI_SERROR)
3290 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3291
3292 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3293 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3294 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3295 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3296 }
3297
3298 /* Enable regwin with gated clock */
3299 state_lo = BWI_STATE_LO_CLOCK |
3300 BWI_STATE_LO_GATED_CLOCK |
3301 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3302 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3303
3304 /* Flush pending bus write */
3305 CSR_READ_4(sc, BWI_STATE_LO);
3306 DELAY(1);
3307
3308 /* Enable regwin with normal clock */
3309 state_lo = BWI_STATE_LO_CLOCK |
3310 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3311 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3312
3313 /* Flush pending bus write */
3314 CSR_READ_4(sc, BWI_STATE_LO);
3315 DELAY(1);
3316 }
3317
3318 static void
3319 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3320 {
3321 struct ieee80211com *ic = &sc->sc_ic;
3322 struct bwi_mac *mac;
3323 struct bwi_myaddr_bssid buf;
3324 const uint8_t *p;
3325 uint32_t val;
3326 int n, i;
3327
3328 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3329 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3330
3331 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3332
3333 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3334 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3335
3336 n = sizeof(buf) / sizeof(val);
3337 p = (const uint8_t *)&buf;
3338 for (i = 0; i < n; ++i) {
3339 int j;
3340
3341 val = 0;
3342 for (j = 0; j < sizeof(val); ++j)
3343 val |= ((uint32_t)(*p++)) << (j * 8);
3344
3345 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3346 }
3347 }
3348
3349 static void
3350 bwi_updateslot(struct ifnet *ifp)
3351 {
3352 struct bwi_softc *sc = ifp->if_softc;
3353 struct ieee80211com *ic = &sc->sc_ic;
3354 struct bwi_mac *mac;
3355
3356 if ((ifp->if_flags & IFF_RUNNING) == 0)
3357 return;
3358
3359 ASSERT_SERIALIZED(ifp->if_serializer);
3360
3361 DPRINTF(sc, "%s\n", __func__);
3362
3363 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3364 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3365
3366 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3367 }
3368
3369 static void
3370 bwi_calibrate(void *xsc)
3371 {
3372 struct bwi_softc *sc = xsc;
3373 struct ieee80211com *ic = &sc->sc_ic;
3374 struct ifnet *ifp = &ic->ic_if;
3375
3376 lwkt_serialize_enter(ifp->if_serializer);
3377
3378 if (ic->ic_state == IEEE80211_S_RUN) {
3379 struct bwi_mac *mac;
3380
3381 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3382 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3383
3384 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3385 bwi_mac_calibrate_txpower(mac);
3386
3387 /* XXX 15 seconds */
3388 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3389 }
3390
3391 lwkt_serialize_exit(ifp->if_serializer);
3392 }
A repo for keeping AMD64 port code before merging with the master