2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.c,v 1.111 2007/04/19 18:53:52 scottl Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.c,v 1.26 2007/07/19 00:23:04 pavalos Exp $
46 #include "aic7xxx_osm.h"
47 #include "aic7xxx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 /****************************** Softc Data ************************************/
51 struct ahc_softc_tailq ahc_tailq
= TAILQ_HEAD_INITIALIZER(ahc_tailq
);
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names
[] =
71 static const u_int num_chip_names
= NUM_ELEMENTS(ahc_chip_names
);
74 * Hardware error codes.
76 struct ahc_hard_error_entry
{
81 static struct ahc_hard_error_entry ahc_hard_errors
[] = {
82 { ILLHADDR
, "Illegal Host Access" },
83 { ILLSADDR
, "Illegal Sequencer Address referenced" },
84 { ILLOPCODE
, "Illegal Opcode in sequencer program" },
85 { SQPARERR
, "Sequencer Parity Error" },
86 { DPARERR
, "Data-path Parity Error" },
87 { MPARERR
, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT
, "PCI Error detected" },
89 { CIOPARERR
, "CIOBUS Parity Error" },
91 static const u_int num_errors
= NUM_ELEMENTS(ahc_hard_errors
);
93 static struct ahc_phase_table_entry ahc_phase_table
[] =
95 { P_DATAOUT
, MSG_NOOP
, "in Data-out phase" },
96 { P_DATAIN
, MSG_INITIATOR_DET_ERR
, "in Data-in phase" },
97 { P_DATAOUT_DT
, MSG_NOOP
, "in DT Data-out phase" },
98 { P_DATAIN_DT
, MSG_INITIATOR_DET_ERR
, "in DT Data-in phase" },
99 { P_COMMAND
, MSG_NOOP
, "in Command phase" },
100 { P_MESGOUT
, MSG_NOOP
, "in Message-out phase" },
101 { P_STATUS
, MSG_INITIATOR_DET_ERR
, "in Status phase" },
102 { P_MESGIN
, MSG_PARITY_ERROR
, "in Message-in phase" },
103 { P_BUSFREE
, MSG_NOOP
, "while idle" },
104 { 0, MSG_NOOP
, "in unknown phase" }
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
111 static const u_int num_phases
= NUM_ELEMENTS(ahc_phase_table
) - 1;
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
118 static struct ahc_syncrate ahc_syncrates
[] =
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL
}
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc
*ahc
,
143 struct ahc_devinfo
*devinfo
);
144 static struct ahc_tmode_tstate
*
145 ahc_alloc_tstate(struct ahc_softc
*ahc
,
146 u_int scsi_id
, char channel
);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc
*ahc
,
149 u_int scsi_id
, char channel
, int force
);
151 static struct ahc_syncrate
*
152 ahc_devlimited_syncrate(struct ahc_softc
*ahc
,
153 struct ahc_initiator_tinfo
*,
157 static void ahc_update_pending_scbs(struct ahc_softc
*ahc
);
158 static void ahc_fetch_devinfo(struct ahc_softc
*ahc
,
159 struct ahc_devinfo
*devinfo
);
160 static void ahc_scb_devinfo(struct ahc_softc
*ahc
,
161 struct ahc_devinfo
*devinfo
,
163 static void ahc_assert_atn(struct ahc_softc
*ahc
);
164 static void ahc_setup_initiator_msgout(struct ahc_softc
*ahc
,
165 struct ahc_devinfo
*devinfo
,
167 static void ahc_build_transfer_msg(struct ahc_softc
*ahc
,
168 struct ahc_devinfo
*devinfo
);
169 static void ahc_construct_sdtr(struct ahc_softc
*ahc
,
170 struct ahc_devinfo
*devinfo
,
171 u_int period
, u_int offset
);
172 static void ahc_construct_wdtr(struct ahc_softc
*ahc
,
173 struct ahc_devinfo
*devinfo
,
175 static void ahc_construct_ppr(struct ahc_softc
*ahc
,
176 struct ahc_devinfo
*devinfo
,
177 u_int period
, u_int offset
,
178 u_int bus_width
, u_int ppr_options
);
179 static void ahc_clear_msg_state(struct ahc_softc
*ahc
);
180 static void ahc_handle_proto_violation(struct ahc_softc
*ahc
);
181 static void ahc_handle_message_phase(struct ahc_softc
*ahc
);
187 static int ahc_sent_msg(struct ahc_softc
*ahc
, ahc_msgtype type
,
188 u_int msgval
, int full
);
189 static int ahc_parse_msg(struct ahc_softc
*ahc
,
190 struct ahc_devinfo
*devinfo
);
191 static int ahc_handle_msg_reject(struct ahc_softc
*ahc
,
192 struct ahc_devinfo
*devinfo
);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc
*ahc
,
194 struct ahc_devinfo
*devinfo
);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc
*ahc
);
196 static void ahc_handle_devreset(struct ahc_softc
*ahc
,
197 struct ahc_devinfo
*devinfo
,
198 cam_status status
, char *message
,
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc
*ahc
,
202 struct ahc_devinfo
*devinfo
,
206 static bus_dmamap_callback_t ahc_dmamap_cb
;
207 static void ahc_build_free_scb_list(struct ahc_softc
*ahc
);
208 static int ahc_init_scbdata(struct ahc_softc
*ahc
);
209 static void ahc_fini_scbdata(struct ahc_softc
*ahc
);
210 static void ahc_qinfifo_requeue(struct ahc_softc
*ahc
,
211 struct scb
*prev_scb
,
213 static int ahc_qinfifo_count(struct ahc_softc
*ahc
);
214 static u_int
ahc_rem_scb_from_disc_list(struct ahc_softc
*ahc
,
215 u_int prev
, u_int scbptr
);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc
*ahc
);
217 static u_int
ahc_rem_wscb(struct ahc_softc
*ahc
,
218 u_int scbpos
, u_int prev
);
219 static void ahc_reset_current_bus(struct ahc_softc
*ahc
);
221 static void ahc_dumpseq(struct ahc_softc
*ahc
);
223 static int ahc_loadseq(struct ahc_softc
*ahc
);
224 static int ahc_check_patch(struct ahc_softc
*ahc
,
225 struct patch
**start_patch
,
226 u_int start_instr
, u_int
*skip_addr
);
227 static void ahc_download_instr(struct ahc_softc
*ahc
,
228 u_int instrptr
, uint8_t *dconsts
);
229 static int ahc_other_scb_timeout(struct ahc_softc
*ahc
,
231 struct scb
*other_scb
);
232 #ifdef AHC_TARGET_MODE
233 static void ahc_queue_lstate_event(struct ahc_softc
*ahc
,
234 struct ahc_tmode_lstate
*lstate
,
238 static void ahc_update_scsiid(struct ahc_softc
*ahc
,
240 static int ahc_handle_target_cmd(struct ahc_softc
*ahc
,
241 struct target_cmd
*cmd
);
243 /************************* Sequencer Execution Control ************************/
245 * Restart the sequencer program from address zero
248 ahc_restart(struct ahc_softc
*ahc
)
253 /* No more pending messages. */
254 ahc_clear_msg_state(ahc
);
256 ahc_outb(ahc
, SCSISIGO
, 0); /* De-assert BSY */
257 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
); /* No message to send */
258 ahc_outb(ahc
, SXFRCTL1
, ahc_inb(ahc
, SXFRCTL1
) & ~BITBUCKET
);
259 ahc_outb(ahc
, LASTPHASE
, P_BUSFREE
);
260 ahc_outb(ahc
, SAVED_SCSIID
, 0xFF);
261 ahc_outb(ahc
, SAVED_LUN
, 0xFF);
264 * Ensure that the sequencer's idea of TQINPOS
265 * matches our own. The sequencer increments TQINPOS
266 * only after it sees a DMA complete and a reset could
267 * occur before the increment leaving the kernel to believe
268 * the command arrived but the sequencer to not.
270 ahc_outb(ahc
, TQINPOS
, ahc
->tqinfifonext
);
272 /* Always allow reselection */
273 ahc_outb(ahc
, SCSISEQ
,
274 ahc_inb(ahc
, SCSISEQ_TEMPLATE
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
275 if ((ahc
->features
& AHC_CMD_CHAN
) != 0) {
276 /* Ensure that no DMA operations are in progress */
277 ahc_outb(ahc
, CCSCBCNT
, 0);
278 ahc_outb(ahc
, CCSGCTL
, 0);
279 ahc_outb(ahc
, CCSCBCTL
, 0);
282 * If we were in the process of DMA'ing SCB data into
283 * an SCB, replace that SCB on the free list. This prevents
286 if ((ahc_inb(ahc
, SEQ_FLAGS2
) & SCB_DMA
) != 0) {
287 ahc_add_curscb_to_free_list(ahc
);
288 ahc_outb(ahc
, SEQ_FLAGS2
,
289 ahc_inb(ahc
, SEQ_FLAGS2
) & ~SCB_DMA
);
293 * Clear any pending sequencer interrupt. It is no
294 * longer relevant since we're resetting the Program
297 ahc_outb(ahc
, CLRINT
, CLRSEQINT
);
299 ahc_outb(ahc
, MWI_RESIDUAL
, 0);
300 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
);
301 ahc_outb(ahc
, SEQADDR0
, 0);
302 ahc_outb(ahc
, SEQADDR1
, 0);
307 /************************* Input/Output Queues ********************************/
309 ahc_run_qoutfifo(struct ahc_softc
*ahc
)
314 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_POSTREAD
);
315 while (ahc
->qoutfifo
[ahc
->qoutfifonext
] != SCB_LIST_NULL
) {
317 scb_index
= ahc
->qoutfifo
[ahc
->qoutfifonext
];
318 if ((ahc
->qoutfifonext
& 0x03) == 0x03) {
322 * Clear 32bits of QOUTFIFO at a time
323 * so that we don't clobber an incoming
324 * byte DMA to the array on architectures
325 * that only support 32bit load and store
328 modnext
= ahc
->qoutfifonext
& ~0x3;
329 *((uint32_t *)(&ahc
->qoutfifo
[modnext
])) = 0xFFFFFFFFUL
;
330 aic_dmamap_sync(ahc
, ahc
->shared_data_dmat
,
331 ahc
->shared_data_dmamap
,
332 /*offset*/modnext
, /*len*/4,
333 BUS_DMASYNC_PREREAD
);
337 scb
= ahc_lookup_scb(ahc
, scb_index
);
339 kprintf("%s: WARNING no command for scb %d "
340 "(cmdcmplt)\nQOUTPOS = %d\n",
341 ahc_name(ahc
), scb_index
,
342 (ahc
->qoutfifonext
- 1) & 0xFF);
347 * Save off the residual
350 ahc_update_residual(ahc
, scb
);
356 ahc_run_untagged_queues(struct ahc_softc
*ahc
)
360 for (i
= 0; i
< 16; i
++)
361 ahc_run_untagged_queue(ahc
, &ahc
->untagged_queues
[i
]);
365 ahc_run_untagged_queue(struct ahc_softc
*ahc
, struct scb_tailq
*queue
)
369 if (ahc
->untagged_queue_lock
!= 0)
372 if ((scb
= TAILQ_FIRST(queue
)) != NULL
373 && (scb
->flags
& SCB_ACTIVE
) == 0) {
374 scb
->flags
|= SCB_ACTIVE
;
376 * Timers are disabled while recovery is in progress.
378 aic_scb_timer_start(scb
);
379 ahc_queue_scb(ahc
, scb
);
383 /************************* Interrupt Handling *********************************/
385 ahc_handle_brkadrint(struct ahc_softc
*ahc
)
388 * We upset the sequencer :-(
389 * Lookup the error message
394 error
= ahc_inb(ahc
, ERROR
);
395 for (i
= 0; error
!= 1 && i
< num_errors
; i
++)
397 kprintf("%s: brkadrint, %s at seqaddr = 0x%x\n",
398 ahc_name(ahc
), ahc_hard_errors
[i
].errmesg
,
399 ahc_inb(ahc
, SEQADDR0
) |
400 (ahc_inb(ahc
, SEQADDR1
) << 8));
402 ahc_dump_card_state(ahc
);
404 /* Tell everyone that this HBA is no longer available */
405 ahc_abort_scbs(ahc
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
406 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, ROLE_UNKNOWN
,
409 /* Disable all interrupt sources by resetting the controller */
414 ahc_handle_seqint(struct ahc_softc
*ahc
, u_int intstat
)
417 struct ahc_devinfo devinfo
;
419 ahc_fetch_devinfo(ahc
, &devinfo
);
422 * Clear the upper byte that holds SEQINT status
423 * codes and clear the SEQINT bit. We will unpause
424 * the sequencer, if appropriate, after servicing
427 ahc_outb(ahc
, CLRINT
, CLRSEQINT
);
428 switch (intstat
& SEQINT_MASK
) {
432 struct hardware_scb
*hscb
;
435 * Set the default return value to 0 (don't
436 * send sense). The sense code will change
439 ahc_outb(ahc
, RETURN_1
, 0);
442 * The sequencer will notify us when a command
443 * has an error that would be of interest to
444 * the kernel. This allows us to leave the sequencer
445 * running in the common case of command completes
446 * without error. The sequencer will already have
447 * dma'd the SCB back up to us, so we can reference
448 * the in kernel copy directly.
450 scb_index
= ahc_inb(ahc
, SCB_TAG
);
451 scb
= ahc_lookup_scb(ahc
, scb_index
);
453 ahc_print_devinfo(ahc
, &devinfo
);
454 kprintf("ahc_intr - referenced scb "
455 "not valid during seqint 0x%x scb(%d)\n",
457 ahc_dump_card_state(ahc
);
464 /* Don't want to clobber the original sense code */
465 if ((scb
->flags
& SCB_SENSE
) != 0) {
467 * Clear the SCB_SENSE Flag and have
468 * the sequencer do a normal command
471 scb
->flags
&= ~SCB_SENSE
;
472 aic_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
475 aic_set_transaction_status(scb
, CAM_SCSI_STATUS_ERROR
);
476 /* Freeze the queue until the client sees the error. */
477 ahc_freeze_devq(ahc
, scb
);
479 aic_set_scsi_status(scb
, hscb
->shared_data
.status
.scsi_status
);
480 switch (hscb
->shared_data
.status
.scsi_status
) {
482 kprintf("%s: Interrupted for staus of 0???\n",
485 case SCSI_STATUS_CMD_TERMINATED
:
486 case SCSI_STATUS_CHECK_COND
:
488 struct ahc_dma_seg
*sg
;
489 struct scsi_sense
*sc
;
490 struct ahc_initiator_tinfo
*targ_info
;
491 struct ahc_tmode_tstate
*tstate
;
492 struct ahc_transinfo
*tinfo
;
494 if (ahc_debug
& AHC_SHOW_SENSE
) {
495 ahc_print_path(ahc
, scb
);
496 kprintf("SCB %d: requests Check Status\n",
501 if (aic_perform_autosense(scb
) == 0)
504 targ_info
= ahc_fetch_transinfo(ahc
,
509 tinfo
= &targ_info
->curr
;
511 sc
= (struct scsi_sense
*)(&hscb
->shared_data
.cdb
);
513 * Save off the residual if there is one.
515 ahc_update_residual(ahc
, scb
);
517 if (ahc_debug
& AHC_SHOW_SENSE
) {
518 ahc_print_path(ahc
, scb
);
519 kprintf("Sending Sense\n");
522 sg
->addr
= ahc_get_sense_bufaddr(ahc
, scb
);
523 sg
->len
= aic_get_sense_bufsize(ahc
, scb
);
524 sg
->len
|= AHC_DMA_LAST_SEG
;
526 /* Fixup byte order */
527 sg
->addr
= aic_htole32(sg
->addr
);
528 sg
->len
= aic_htole32(sg
->len
);
530 sc
->opcode
= REQUEST_SENSE
;
532 if (tinfo
->protocol_version
<= SCSI_REV_2
533 && SCB_GET_LUN(scb
) < 8)
534 sc
->byte2
= SCB_GET_LUN(scb
) << 5;
537 sc
->length
= sg
->len
;
541 * We can't allow the target to disconnect.
542 * This will be an untagged transaction and
543 * having the target disconnect will make this
544 * transaction indestinguishable from outstanding
545 * tagged transactions.
550 * This request sense could be because the
551 * the device lost power or in some other
552 * way has lost our transfer negotiations.
553 * Renegotiate if appropriate. Unit attention
554 * errors will be reported before any data
557 if (aic_get_residual(scb
)
558 == aic_get_transfer_length(scb
)) {
559 ahc_update_neg_request(ahc
, &devinfo
,
561 AHC_NEG_IF_NON_ASYNC
);
563 if (tstate
->auto_negotiate
& devinfo
.target_mask
) {
564 hscb
->control
|= MK_MESSAGE
;
565 scb
->flags
&= ~SCB_NEGOTIATE
;
566 scb
->flags
|= SCB_AUTO_NEGOTIATE
;
568 hscb
->cdb_len
= sizeof(*sc
);
569 hscb
->dataptr
= sg
->addr
;
570 hscb
->datacnt
= sg
->len
;
571 hscb
->sgptr
= scb
->sg_list_phys
| SG_FULL_RESID
;
572 hscb
->sgptr
= aic_htole32(hscb
->sgptr
);
574 scb
->flags
|= SCB_SENSE
;
575 ahc_qinfifo_requeue_tail(ahc
, scb
);
576 ahc_outb(ahc
, RETURN_1
, SEND_SENSE
);
578 * Ensure we have enough time to actually
579 * retrieve the sense, but only schedule
580 * the timer if we are not in recovery or
581 * this is a recovery SCB that is allowed
582 * to have an active timer.
584 if (ahc
->scb_data
->recovery_scbs
== 0
585 || (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
586 aic_scb_timer_reset(scb
, 5 * 1000);
596 /* Ensure we don't leave the selection hardware on */
597 ahc_outb(ahc
, SCSISEQ
,
598 ahc_inb(ahc
, SCSISEQ
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
600 kprintf("%s:%c:%d: no active SCB for reconnecting "
601 "target - issuing BUS DEVICE RESET\n",
602 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
);
603 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
604 "ARG_1 == 0x%x ACCUM = 0x%x\n",
605 ahc_inb(ahc
, SAVED_SCSIID
), ahc_inb(ahc
, SAVED_LUN
),
606 ahc_inb(ahc
, ARG_1
), ahc_inb(ahc
, ACCUM
));
607 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
609 ahc_inb(ahc
, SEQ_FLAGS
), ahc_inb(ahc
, SCBPTR
),
610 ahc_index_busy_tcl(ahc
,
611 BUILD_TCL(ahc_inb(ahc
, SAVED_SCSIID
),
612 ahc_inb(ahc
, SAVED_LUN
))),
613 ahc_inb(ahc
, SINDEX
));
614 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
615 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
616 ahc_inb(ahc
, SCSIID
), ahc_inb(ahc
, SCB_SCSIID
),
617 ahc_inb(ahc
, SCB_LUN
), ahc_inb(ahc
, SCB_TAG
),
618 ahc_inb(ahc
, SCB_CONTROL
));
619 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
620 ahc_inb(ahc
, SCSIBUSL
), ahc_inb(ahc
, SCSISIGI
));
621 kprintf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc
, SXFRCTL0
));
622 kprintf("SEQCTL == 0x%x\n", ahc_inb(ahc
, SEQCTL
));
623 ahc_dump_card_state(ahc
);
624 ahc
->msgout_buf
[0] = MSG_BUS_DEV_RESET
;
626 ahc
->msgout_index
= 0;
627 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
628 ahc_outb(ahc
, MSG_OUT
, HOST_MSG
);
634 u_int rejbyte
= ahc_inb(ahc
, ACCUM
);
635 kprintf("%s:%c:%d: Warning - unknown message received from "
636 "target (0x%x). Rejecting\n",
637 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
, rejbyte
);
640 case PROTO_VIOLATION
:
642 ahc_handle_proto_violation(ahc
);
646 ahc_handle_ign_wide_residue(ahc
, &devinfo
);
649 ahc_reinitialize_dataptrs(ahc
);
655 lastphase
= ahc_inb(ahc
, LASTPHASE
);
656 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
657 "lastphase = 0x%x. Attempting to continue\n",
658 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
659 lastphase
, ahc_inb(ahc
, SCSISIGI
));
666 lastphase
= ahc_inb(ahc
, LASTPHASE
);
667 kprintf("%s:%c:%d: Missed busfree. "
668 "Lastphase = 0x%x, Curphase = 0x%x\n",
669 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
670 lastphase
, ahc_inb(ahc
, SCSISIGI
));
677 * The sequencer has encountered a message phase
678 * that requires host assistance for completion.
679 * While handling the message phase(s), we will be
680 * notified by the sequencer after each byte is
681 * transfered so we can track bus phase changes.
683 * If this is the first time we've seen a HOST_MSG_LOOP
684 * interrupt, initialize the state of the host message
687 if (ahc
->msg_type
== MSG_TYPE_NONE
) {
692 bus_phase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
693 if (bus_phase
!= P_MESGIN
694 && bus_phase
!= P_MESGOUT
) {
695 kprintf("ahc_intr: HOST_MSG_LOOP bad "
699 * Probably transitioned to bus free before
700 * we got here. Just punt the message.
702 ahc_clear_intstat(ahc
);
707 scb_index
= ahc_inb(ahc
, SCB_TAG
);
708 scb
= ahc_lookup_scb(ahc
, scb_index
);
709 if (devinfo
.role
== ROLE_INITIATOR
) {
711 panic("HOST_MSG_LOOP with "
712 "invalid SCB %x\n", scb_index
);
714 if (bus_phase
== P_MESGOUT
)
715 ahc_setup_initiator_msgout(ahc
,
720 MSG_TYPE_INITIATOR_MSGIN
;
721 ahc
->msgin_index
= 0;
724 #ifdef AHC_TARGET_MODE
726 if (bus_phase
== P_MESGOUT
) {
728 MSG_TYPE_TARGET_MSGOUT
;
729 ahc
->msgin_index
= 0;
732 ahc_setup_target_msgin(ahc
,
739 ahc_handle_message_phase(ahc
);
745 * If we've cleared the parity error interrupt
746 * but the sequencer still believes that SCSIPERR
747 * is true, it must be that the parity error is
748 * for the currently presented byte on the bus,
749 * and we are not in a phase (data-in) where we will
750 * eventually ack this byte. Ack the byte and
751 * throw it away in the hope that the target will
752 * take us to message out to deliver the appropriate
755 if ((intstat
& SCSIINT
) == 0
756 && (ahc_inb(ahc
, SSTAT1
) & SCSIPERR
) != 0) {
758 if ((ahc
->features
& AHC_DT
) == 0) {
762 * The hardware will only let you ack bytes
763 * if the expected phase in SCSISIGO matches
764 * the current phase. Make sure this is
765 * currently the case.
767 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
768 ahc_outb(ahc
, LASTPHASE
, curphase
);
769 ahc_outb(ahc
, SCSISIGO
, curphase
);
771 if ((ahc_inb(ahc
, SCSISIGI
) & (CDI
|MSGI
)) == 0) {
775 * In a data phase. Faster to bitbucket
776 * the data than to individually ack each
777 * byte. This is also the only strategy
778 * that will work with AUTOACK enabled.
780 ahc_outb(ahc
, SXFRCTL1
,
781 ahc_inb(ahc
, SXFRCTL1
) | BITBUCKET
);
783 while (--wait
!= 0) {
784 if ((ahc_inb(ahc
, SCSISIGI
)
789 ahc_outb(ahc
, SXFRCTL1
,
790 ahc_inb(ahc
, SXFRCTL1
) & ~BITBUCKET
);
795 ahc_print_devinfo(ahc
, &devinfo
);
796 kprintf("Unable to clear parity error. "
798 scb_index
= ahc_inb(ahc
, SCB_TAG
);
799 scb
= ahc_lookup_scb(ahc
, scb_index
);
801 aic_set_transaction_status(scb
,
803 ahc_reset_channel(ahc
, devinfo
.channel
,
807 ahc_inb(ahc
, SCSIDATL
);
815 * When the sequencer detects an overrun, it
816 * places the controller in "BITBUCKET" mode
817 * and allows the target to complete its transfer.
818 * Unfortunately, none of the counters get updated
819 * when the controller is in this mode, so we have
820 * no way of knowing how large the overrun was.
822 u_int scbindex
= ahc_inb(ahc
, SCB_TAG
);
823 u_int lastphase
= ahc_inb(ahc
, LASTPHASE
);
826 scb
= ahc_lookup_scb(ahc
, scbindex
);
827 for (i
= 0; i
< num_phases
; i
++) {
828 if (lastphase
== ahc_phase_table
[i
].phase
)
831 ahc_print_path(ahc
, scb
);
832 kprintf("data overrun detected %s."
834 ahc_phase_table
[i
].phasemsg
,
836 ahc_print_path(ahc
, scb
);
837 kprintf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
838 ahc_inb(ahc
, SEQ_FLAGS
) & DPHASE
? "Have" : "Haven't",
839 aic_get_transfer_length(scb
), scb
->sg_count
);
840 if (scb
->sg_count
> 0) {
841 for (i
= 0; i
< scb
->sg_count
; i
++) {
843 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
845 (aic_le32toh(scb
->sg_list
[i
].len
) >> 24
846 & SG_HIGH_ADDR_BITS
),
847 aic_le32toh(scb
->sg_list
[i
].addr
),
848 aic_le32toh(scb
->sg_list
[i
].len
)
853 * Set this and it will take effect when the
854 * target does a command complete.
856 ahc_freeze_devq(ahc
, scb
);
857 if ((scb
->flags
& SCB_SENSE
) == 0) {
858 aic_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
860 scb
->flags
&= ~SCB_SENSE
;
861 aic_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
865 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
867 * Clear the channel in case we return
868 * to data phase later.
870 ahc_outb(ahc
, SXFRCTL0
,
871 ahc_inb(ahc
, SXFRCTL0
) | CLRSTCNT
|CLRCHN
);
872 ahc_outb(ahc
, SXFRCTL0
,
873 ahc_inb(ahc
, SXFRCTL0
) | CLRSTCNT
|CLRCHN
);
875 if ((ahc
->flags
& AHC_39BIT_ADDRESSING
) != 0) {
878 /* Ensure HHADDR is 0 for future DMA operations. */
879 dscommand1
= ahc_inb(ahc
, DSCOMMAND1
);
880 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
| HADDLDSEL0
);
881 ahc_outb(ahc
, HADDR
, 0);
882 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
);
890 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
891 ahc_name(ahc
), devinfo
.channel
, devinfo
.target
,
893 scbindex
= ahc_inb(ahc
, SCB_TAG
);
894 scb
= ahc_lookup_scb(ahc
, scbindex
);
896 && (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
898 * Ensure that we didn't put a second instance of this
899 * SCB into the QINFIFO.
901 ahc_search_qinfifo(ahc
, SCB_GET_TARGET(ahc
, scb
),
902 SCB_GET_CHANNEL(ahc
, scb
),
903 SCB_GET_LUN(scb
), scb
->hscb
->tag
,
904 ROLE_INITIATOR
, /*status*/0,
910 kprintf("%s: No free or disconnected SCBs\n", ahc_name(ahc
));
911 ahc_dump_card_state(ahc
);
919 scbptr
= ahc_inb(ahc
, SCBPTR
);
920 kprintf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
921 scbptr
, ahc_inb(ahc
, ARG_1
),
922 ahc
->scb_data
->hscbs
[scbptr
].tag
);
923 ahc_dump_card_state(ahc
);
929 kprintf("%s: BTT calculation out of range\n", ahc_name(ahc
));
930 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
931 "ARG_1 == 0x%x ACCUM = 0x%x\n",
932 ahc_inb(ahc
, SAVED_SCSIID
), ahc_inb(ahc
, SAVED_LUN
),
933 ahc_inb(ahc
, ARG_1
), ahc_inb(ahc
, ACCUM
));
934 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
935 "SINDEX == 0x%x\n, A == 0x%x\n",
936 ahc_inb(ahc
, SEQ_FLAGS
), ahc_inb(ahc
, SCBPTR
),
937 ahc_index_busy_tcl(ahc
,
938 BUILD_TCL(ahc_inb(ahc
, SAVED_SCSIID
),
939 ahc_inb(ahc
, SAVED_LUN
))),
940 ahc_inb(ahc
, SINDEX
),
941 ahc_inb(ahc
, ACCUM
));
942 kprintf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
943 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
944 ahc_inb(ahc
, SCSIID
), ahc_inb(ahc
, SCB_SCSIID
),
945 ahc_inb(ahc
, SCB_LUN
), ahc_inb(ahc
, SCB_TAG
),
946 ahc_inb(ahc
, SCB_CONTROL
));
947 kprintf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
948 ahc_inb(ahc
, SCSIBUSL
), ahc_inb(ahc
, SCSISIGI
));
949 ahc_dump_card_state(ahc
);
954 kprintf("ahc_intr: seqint, "
955 "intstat == 0x%x, scsisigi = 0x%x\n",
956 intstat
, ahc_inb(ahc
, SCSISIGI
));
961 * The sequencer is paused immediately on
962 * a SEQINT, so we should restart it when
969 ahc_handle_scsiint(struct ahc_softc
*ahc
, u_int intstat
)
978 if ((ahc
->features
& AHC_TWIN
) != 0
979 && ((ahc_inb(ahc
, SBLKCTL
) & SELBUSB
) != 0))
983 intr_channel
= cur_channel
;
985 if ((ahc
->features
& AHC_ULTRA2
) != 0)
986 status0
= ahc_inb(ahc
, SSTAT0
) & IOERR
;
989 status
= ahc_inb(ahc
, SSTAT1
) & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
990 if (status
== 0 && status0
== 0) {
991 if ((ahc
->features
& AHC_TWIN
) != 0) {
992 /* Try the other channel */
993 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) ^ SELBUSB
);
994 status
= ahc_inb(ahc
, SSTAT1
)
995 & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
996 intr_channel
= (cur_channel
== 'A') ? 'B' : 'A';
999 kprintf("%s: Spurious SCSI interrupt\n", ahc_name(ahc
));
1000 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1006 /* Make sure the sequencer is in a safe location. */
1007 ahc_clear_critical_section(ahc
);
1009 scb_index
= ahc_inb(ahc
, SCB_TAG
);
1010 scb
= ahc_lookup_scb(ahc
, scb_index
);
1012 && (ahc_inb(ahc
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
1015 if ((ahc
->features
& AHC_ULTRA2
) != 0
1016 && (status0
& IOERR
) != 0) {
1019 now_lvd
= ahc_inb(ahc
, SBLKCTL
) & ENAB40
;
1020 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1021 ahc_name(ahc
), now_lvd
? "LVD" : "SE");
1022 ahc_outb(ahc
, CLRSINT0
, CLRIOERR
);
1024 * When transitioning to SE mode, the reset line
1025 * glitches, triggering an arbitration bug in some
1026 * Ultra2 controllers. This bug is cleared when we
1027 * assert the reset line. Since a reset glitch has
1028 * already occurred with this transition and a
1029 * transceiver state change is handled just like
1030 * a bus reset anyway, asserting the reset line
1031 * ourselves is safe.
1033 ahc_reset_channel(ahc
, intr_channel
,
1034 /*Initiate Reset*/now_lvd
== 0);
1035 } else if ((status
& SCSIRSTI
) != 0) {
1036 kprintf("%s: Someone reset channel %c\n",
1037 ahc_name(ahc
), intr_channel
);
1038 if (intr_channel
!= cur_channel
)
1039 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) ^ SELBUSB
);
1040 ahc_reset_channel(ahc
, intr_channel
, /*Initiate Reset*/FALSE
);
1041 } else if ((status
& SCSIPERR
) != 0) {
1043 * Determine the bus phase and queue an appropriate message.
1044 * SCSIPERR is latched true as soon as a parity error
1045 * occurs. If the sequencer acked the transfer that
1046 * caused the parity error and the currently presented
1047 * transfer on the bus has correct parity, SCSIPERR will
1048 * be cleared by CLRSCSIPERR. Use this to determine if
1049 * we should look at the last phase the sequencer recorded,
1050 * or the current phase presented on the bus.
1052 struct ahc_devinfo devinfo
;
1062 lastphase
= ahc_inb(ahc
, LASTPHASE
);
1063 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
1064 sstat2
= ahc_inb(ahc
, SSTAT2
);
1065 ahc_outb(ahc
, CLRSINT1
, CLRSCSIPERR
);
1067 * For all phases save DATA, the sequencer won't
1068 * automatically ack a byte that has a parity error
1069 * in it. So the only way that the current phase
1070 * could be 'data-in' is if the parity error is for
1071 * an already acked byte in the data phase. During
1072 * synchronous data-in transfers, we may actually
1073 * ack bytes before latching the current phase in
1074 * LASTPHASE, leading to the discrepancy between
1075 * curphase and lastphase.
1077 if ((ahc_inb(ahc
, SSTAT1
) & SCSIPERR
) != 0
1078 || curphase
== P_DATAIN
|| curphase
== P_DATAIN_DT
)
1079 errorphase
= curphase
;
1081 errorphase
= lastphase
;
1083 for (i
= 0; i
< num_phases
; i
++) {
1084 if (errorphase
== ahc_phase_table
[i
].phase
)
1087 mesg_out
= ahc_phase_table
[i
].mesg_out
;
1090 if (SCB_IS_SILENT(scb
))
1093 ahc_print_path(ahc
, scb
);
1094 scb
->flags
|= SCB_TRANSMISSION_ERROR
;
1096 kprintf("%s:%c:%d: ", ahc_name(ahc
), intr_channel
,
1097 SCSIID_TARGET(ahc
, ahc_inb(ahc
, SAVED_SCSIID
)));
1098 scsirate
= ahc_inb(ahc
, SCSIRATE
);
1099 if (silent
== FALSE
) {
1100 kprintf("parity error detected %s. "
1101 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1102 ahc_phase_table
[i
].phasemsg
,
1103 ahc_inw(ahc
, SEQADDR0
),
1105 if ((ahc
->features
& AHC_DT
) != 0) {
1106 if ((sstat2
& CRCVALERR
) != 0)
1107 kprintf("\tCRC Value Mismatch\n");
1108 if ((sstat2
& CRCENDERR
) != 0)
1109 kprintf("\tNo terminal CRC packet "
1111 if ((sstat2
& CRCREQERR
) != 0)
1112 kprintf("\tIllegal CRC packet "
1114 if ((sstat2
& DUAL_EDGE_ERR
) != 0)
1115 kprintf("\tUnexpected %sDT Data Phase\n",
1116 (scsirate
& SINGLE_EDGE
)
1121 if ((ahc
->features
& AHC_DT
) != 0
1122 && (sstat2
& DUAL_EDGE_ERR
) != 0) {
1124 * This error applies regardless of
1125 * data direction, so ignore the value
1126 * in the phase table.
1128 mesg_out
= MSG_INITIATOR_DET_ERR
;
1132 * We've set the hardware to assert ATN if we
1133 * get a parity error on "in" phases, so all we
1134 * need to do is stuff the message buffer with
1135 * the appropriate message. "In" phases have set
1136 * mesg_out to something other than MSG_NOP.
1138 if (mesg_out
!= MSG_NOOP
) {
1139 if (ahc
->msg_type
!= MSG_TYPE_NONE
)
1140 ahc
->send_msg_perror
= TRUE
;
1142 ahc_outb(ahc
, MSG_OUT
, mesg_out
);
1145 * Force a renegotiation with this target just in
1146 * case we are out of sync for some external reason
1147 * unknown (or unreported) by the target.
1149 ahc_fetch_devinfo(ahc
, &devinfo
);
1150 ahc_force_renegotiation(ahc
, &devinfo
);
1152 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1154 } else if ((status
& SELTO
) != 0) {
1157 /* Stop the selection */
1158 ahc_outb(ahc
, SCSISEQ
, 0);
1160 /* No more pending messages */
1161 ahc_clear_msg_state(ahc
);
1163 /* Clear interrupt state */
1164 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENBUSFREE
);
1165 ahc_outb(ahc
, CLRSINT1
, CLRSELTIMEO
|CLRBUSFREE
|CLRSCSIPERR
);
1168 * Although the driver does not care about the
1169 * 'Selection in Progress' status bit, the busy
1170 * LED does. SELINGO is only cleared by a successful
1171 * selection, so we must manually clear it to insure
1172 * the LED turns off just in case no future successful
1173 * selections occur (e.g. no devices on the bus).
1175 ahc_outb(ahc
, CLRSINT0
, CLRSELINGO
);
1177 scbptr
= ahc_inb(ahc
, WAITING_SCBH
);
1178 ahc_outb(ahc
, SCBPTR
, scbptr
);
1179 scb_index
= ahc_inb(ahc
, SCB_TAG
);
1181 scb
= ahc_lookup_scb(ahc
, scb_index
);
1183 kprintf("%s: ahc_intr - referenced scb not "
1184 "valid during SELTO scb(%d, %d)\n",
1185 ahc_name(ahc
), scbptr
, scb_index
);
1186 ahc_dump_card_state(ahc
);
1188 struct ahc_devinfo devinfo
;
1190 if ((ahc_debug
& AHC_SHOW_SELTO
) != 0) {
1191 ahc_print_path(ahc
, scb
);
1192 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1196 ahc_scb_devinfo(ahc
, &devinfo
, scb
);
1197 aic_set_transaction_status(scb
, CAM_SEL_TIMEOUT
);
1198 ahc_freeze_devq(ahc
, scb
);
1201 * Cancel any pending transactions on the device
1202 * now that it seems to be missing. This will
1203 * also revert us to async/narrow transfers until
1204 * we can renegotiate with the device.
1206 ahc_handle_devreset(ahc
, &devinfo
,
1208 "Selection Timeout",
1209 /*verbose_level*/1);
1211 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1213 } else if ((status
& BUSFREE
) != 0
1214 && (ahc_inb(ahc
, SIMODE1
) & ENBUSFREE
) != 0) {
1215 struct ahc_devinfo devinfo
;
1220 u_int initiator_role_id
;
1225 * Clear our selection hardware as soon as possible.
1226 * We may have an entry in the waiting Q for this target,
1227 * that is affected by this busfree and we don't want to
1228 * go about selecting the target while we handle the event.
1230 ahc_outb(ahc
, SCSISEQ
,
1231 ahc_inb(ahc
, SCSISEQ
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
1234 * Disable busfree interrupts and clear the busfree
1235 * interrupt status. We do this here so that several
1236 * bus transactions occur prior to clearing the SCSIINT
1237 * latch. It can take a bit for the clearing to take effect.
1239 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENBUSFREE
);
1240 ahc_outb(ahc
, CLRSINT1
, CLRBUSFREE
|CLRSCSIPERR
);
1243 * Look at what phase we were last in.
1244 * If its message out, chances are pretty good
1245 * that the busfree was in response to one of
1246 * our abort requests.
1248 lastphase
= ahc_inb(ahc
, LASTPHASE
);
1249 saved_scsiid
= ahc_inb(ahc
, SAVED_SCSIID
);
1250 saved_lun
= ahc_inb(ahc
, SAVED_LUN
);
1251 target
= SCSIID_TARGET(ahc
, saved_scsiid
);
1252 initiator_role_id
= SCSIID_OUR_ID(saved_scsiid
);
1253 channel
= SCSIID_CHANNEL(ahc
, saved_scsiid
);
1254 ahc_compile_devinfo(&devinfo
, initiator_role_id
,
1255 target
, saved_lun
, channel
, ROLE_INITIATOR
);
1258 if (lastphase
== P_MESGOUT
) {
1261 tag
= SCB_LIST_NULL
;
1262 if (ahc_sent_msg(ahc
, AHCMSG_1B
, MSG_ABORT_TAG
, TRUE
)
1263 || ahc_sent_msg(ahc
, AHCMSG_1B
, MSG_ABORT
, TRUE
)) {
1264 if (ahc
->msgout_buf
[ahc
->msgout_index
- 1]
1266 tag
= scb
->hscb
->tag
;
1267 ahc_print_path(ahc
, scb
);
1268 kprintf("SCB %d - Abort%s Completed.\n",
1269 scb
->hscb
->tag
, tag
== SCB_LIST_NULL
?
1271 ahc_abort_scbs(ahc
, target
, channel
,
1276 } else if (ahc_sent_msg(ahc
, AHCMSG_1B
,
1277 MSG_BUS_DEV_RESET
, TRUE
)) {
1278 #if defined(__DragonFly__) || defined(__FreeBSD__)
1280 * Don't mark the user's request for this BDR
1281 * as completing with CAM_BDR_SENT. CAM3
1282 * specifies CAM_REQ_CMP.
1285 && scb
->io_ctx
->ccb_h
.func_code
== XPT_RESET_DEV
1286 && ahc_match_scb(ahc
, scb
, target
, channel
,
1290 aic_set_transaction_status(scb
, CAM_REQ_CMP
);
1293 ahc_compile_devinfo(&devinfo
,
1299 ahc_handle_devreset(ahc
, &devinfo
,
1302 /*verbose_level*/0);
1304 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1305 MSG_EXT_PPR
, FALSE
)) {
1306 struct ahc_initiator_tinfo
*tinfo
;
1307 struct ahc_tmode_tstate
*tstate
;
1310 * PPR Rejected. Try non-ppr negotiation
1311 * and retry command.
1313 tinfo
= ahc_fetch_transinfo(ahc
,
1318 tinfo
->curr
.transport_version
= 2;
1319 tinfo
->goal
.transport_version
= 2;
1320 tinfo
->goal
.ppr_options
= 0;
1321 ahc_qinfifo_requeue_tail(ahc
, scb
);
1323 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1324 MSG_EXT_WDTR
, FALSE
)) {
1326 * Negotiation Rejected. Go-narrow and
1329 ahc_set_width(ahc
, &devinfo
,
1330 MSG_EXT_WDTR_BUS_8_BIT
,
1331 AHC_TRANS_CUR
|AHC_TRANS_GOAL
,
1333 ahc_qinfifo_requeue_tail(ahc
, scb
);
1335 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
,
1336 MSG_EXT_SDTR
, FALSE
)) {
1338 * Negotiation Rejected. Go-async and
1341 ahc_set_syncrate(ahc
, &devinfo
,
1343 /*period*/0, /*offset*/0,
1345 AHC_TRANS_CUR
|AHC_TRANS_GOAL
,
1347 ahc_qinfifo_requeue_tail(ahc
, scb
);
1351 if (printerror
!= 0) {
1357 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
1358 tag
= scb
->hscb
->tag
;
1360 tag
= SCB_LIST_NULL
;
1361 ahc_print_path(ahc
, scb
);
1362 ahc_abort_scbs(ahc
, target
, channel
,
1363 SCB_GET_LUN(scb
), tag
,
1368 * We had not fully identified this connection,
1369 * so we cannot abort anything.
1371 kprintf("%s: ", ahc_name(ahc
));
1373 for (i
= 0; i
< num_phases
; i
++) {
1374 if (lastphase
== ahc_phase_table
[i
].phase
)
1377 if (lastphase
!= P_BUSFREE
) {
1379 * Renegotiate with this device at the
1380 * next oportunity just in case this busfree
1381 * is due to a negotiation mismatch with the
1384 ahc_force_renegotiation(ahc
, &devinfo
);
1386 kprintf("Unexpected busfree %s\n"
1387 "SEQADDR == 0x%x\n",
1388 ahc_phase_table
[i
].phasemsg
,
1389 ahc_inb(ahc
, SEQADDR0
)
1390 | (ahc_inb(ahc
, SEQADDR1
) << 8));
1392 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1395 kprintf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1396 ahc_name(ahc
), status
);
1397 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1402 * Force renegotiation to occur the next time we initiate
1403 * a command to the current device.
1406 ahc_force_renegotiation(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
1408 struct ahc_initiator_tinfo
*targ_info
;
1409 struct ahc_tmode_tstate
*tstate
;
1411 targ_info
= ahc_fetch_transinfo(ahc
,
1413 devinfo
->our_scsiid
,
1416 ahc_update_neg_request(ahc
, devinfo
, tstate
,
1417 targ_info
, AHC_NEG_IF_NON_ASYNC
);
1420 #define AHC_MAX_STEPS 2000
1422 ahc_clear_critical_section(struct ahc_softc
*ahc
)
1429 if (ahc
->num_critical_sections
== 0)
1441 seqaddr
= ahc_inb(ahc
, SEQADDR0
)
1442 | (ahc_inb(ahc
, SEQADDR1
) << 8);
1445 * Seqaddr represents the next instruction to execute,
1446 * so we are really executing the instruction just
1449 cs
= ahc
->critical_sections
;
1450 for (i
= 0; i
< ahc
->num_critical_sections
; i
++, cs
++) {
1452 if (cs
->begin
< seqaddr
&& cs
->end
>= seqaddr
)
1456 if (i
== ahc
->num_critical_sections
)
1459 if (steps
> AHC_MAX_STEPS
) {
1460 kprintf("%s: Infinite loop in critical section\n",
1462 ahc_dump_card_state(ahc
);
1463 panic("critical section loop");
1467 if (stepping
== FALSE
) {
1470 * Disable all interrupt sources so that the
1471 * sequencer will not be stuck by a pausing
1472 * interrupt condition while we attempt to
1473 * leave a critical section.
1475 simode0
= ahc_inb(ahc
, SIMODE0
);
1476 ahc_outb(ahc
, SIMODE0
, 0);
1477 simode1
= ahc_inb(ahc
, SIMODE1
);
1478 if ((ahc
->features
& AHC_DT
) != 0)
1480 * On DT class controllers, we
1481 * use the enhanced busfree logic.
1482 * Unfortunately we cannot re-enable
1483 * busfree detection within the
1484 * current connection, so we must
1485 * leave it on while single stepping.
1487 ahc_outb(ahc
, SIMODE1
, simode1
& ENBUSFREE
);
1489 ahc_outb(ahc
, SIMODE1
, 0);
1490 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1491 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
| STEP
);
1494 if ((ahc
->features
& AHC_DT
) != 0) {
1495 ahc_outb(ahc
, CLRSINT1
, CLRBUSFREE
);
1496 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1498 ahc_outb(ahc
, HCNTRL
, ahc
->unpause
);
1499 while (!ahc_is_paused(ahc
))
1503 ahc_outb(ahc
, SIMODE0
, simode0
);
1504 ahc_outb(ahc
, SIMODE1
, simode1
);
1505 ahc_outb(ahc
, SEQCTL
, ahc
->seqctl
);
1510 * Clear any pending interrupt status.
1513 ahc_clear_intstat(struct ahc_softc
*ahc
)
1515 /* Clear any interrupt conditions this may have caused */
1516 ahc_outb(ahc
, CLRSINT1
, CLRSELTIMEO
|CLRATNO
|CLRSCSIRSTI
1517 |CLRBUSFREE
|CLRSCSIPERR
|CLRPHASECHG
|
1519 ahc_flush_device_writes(ahc
);
1520 ahc_outb(ahc
, CLRSINT0
, CLRSELDO
|CLRSELDI
|CLRSELINGO
);
1521 ahc_flush_device_writes(ahc
);
1522 ahc_outb(ahc
, CLRINT
, CLRSCSIINT
);
1523 ahc_flush_device_writes(ahc
);
1526 /**************************** Debugging Routines ******************************/
1528 uint32_t ahc_debug
= AHC_DEBUG_OPTS
;
1532 ahc_print_scb(struct scb
*scb
)
1536 struct hardware_scb
*hscb
= scb
->hscb
;
1538 kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1544 kprintf("Shared Data: ");
1545 for (i
= 0; i
< sizeof(hscb
->shared_data
.cdb
); i
++)
1546 kprintf("%#02x", hscb
->shared_data
.cdb
[i
]);
1547 kprintf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1548 aic_le32toh(hscb
->dataptr
),
1549 aic_le32toh(hscb
->datacnt
),
1550 aic_le32toh(hscb
->sgptr
),
1552 if (scb
->sg_count
> 0) {
1553 for (i
= 0; i
< scb
->sg_count
; i
++) {
1554 kprintf("sg[%d] - Addr 0x%x%x : Length %d\n",
1556 (aic_le32toh(scb
->sg_list
[i
].len
) >> 24
1557 & SG_HIGH_ADDR_BITS
),
1558 aic_le32toh(scb
->sg_list
[i
].addr
),
1559 aic_le32toh(scb
->sg_list
[i
].len
));
1564 /************************* Transfer Negotiation *******************************/
1566 * Allocate per target mode instance (ID we respond to as a target)
1567 * transfer negotiation data structures.
1569 static struct ahc_tmode_tstate
*
1570 ahc_alloc_tstate(struct ahc_softc
*ahc
, u_int scsi_id
, char channel
)
1572 struct ahc_tmode_tstate
*master_tstate
;
1573 struct ahc_tmode_tstate
*tstate
;
1576 master_tstate
= ahc
->enabled_targets
[ahc
->our_id
];
1577 if (channel
== 'B') {
1579 master_tstate
= ahc
->enabled_targets
[ahc
->our_id_b
+ 8];
1581 if (ahc
->enabled_targets
[scsi_id
] != NULL
1582 && ahc
->enabled_targets
[scsi_id
] != master_tstate
)
1583 panic("%s: ahc_alloc_tstate - Target already allocated",
1585 tstate
= kmalloc(sizeof(*tstate
), M_DEVBUF
, M_INTWAIT
);
1588 * If we have allocated a master tstate, copy user settings from
1589 * the master tstate (taken from SRAM or the EEPROM) for this
1590 * channel, but reset our current and goal settings to async/narrow
1591 * until an initiator talks to us.
1593 if (master_tstate
!= NULL
) {
1594 memcpy(tstate
, master_tstate
, sizeof(*tstate
));
1595 memset(tstate
->enabled_luns
, 0, sizeof(tstate
->enabled_luns
));
1596 tstate
->ultraenb
= 0;
1597 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++) {
1598 memset(&tstate
->transinfo
[i
].curr
, 0,
1599 sizeof(tstate
->transinfo
[i
].curr
));
1600 memset(&tstate
->transinfo
[i
].goal
, 0,
1601 sizeof(tstate
->transinfo
[i
].goal
));
1604 memset(tstate
, 0, sizeof(*tstate
));
1605 ahc
->enabled_targets
[scsi_id
] = tstate
;
1609 #ifdef AHC_TARGET_MODE
1611 * Free per target mode instance (ID we respond to as a target)
1612 * transfer negotiation data structures.
1615 ahc_free_tstate(struct ahc_softc
*ahc
, u_int scsi_id
, char channel
, int force
)
1617 struct ahc_tmode_tstate
*tstate
;
1620 * Don't clean up our "master" tstate.
1621 * It has our default user settings.
1623 if (((channel
== 'B' && scsi_id
== ahc
->our_id_b
)
1624 || (channel
== 'A' && scsi_id
== ahc
->our_id
))
1630 tstate
= ahc
->enabled_targets
[scsi_id
];
1632 kfree(tstate
, M_DEVBUF
);
1633 ahc
->enabled_targets
[scsi_id
] = NULL
;
1638 * Called when we have an active connection to a target on the bus,
1639 * this function finds the nearest syncrate to the input period limited
1640 * by the capabilities of the bus connectivity of and sync settings for
1643 struct ahc_syncrate
*
1644 ahc_devlimited_syncrate(struct ahc_softc
*ahc
,
1645 struct ahc_initiator_tinfo
*tinfo
,
1646 u_int
*period
, u_int
*ppr_options
, role_t role
)
1648 struct ahc_transinfo
*transinfo
;
1651 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1652 if ((ahc_inb(ahc
, SBLKCTL
) & ENAB40
) != 0
1653 && (ahc_inb(ahc
, SSTAT2
) & EXP_ACTIVE
) == 0) {
1654 maxsync
= AHC_SYNCRATE_DT
;
1656 maxsync
= AHC_SYNCRATE_ULTRA
;
1657 /* Can't do DT on an SE bus */
1658 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1660 } else if ((ahc
->features
& AHC_ULTRA
) != 0) {
1661 maxsync
= AHC_SYNCRATE_ULTRA
;
1663 maxsync
= AHC_SYNCRATE_FAST
;
1666 * Never allow a value higher than our current goal
1667 * period otherwise we may allow a target initiated
1668 * negotiation to go above the limit as set by the
1669 * user. In the case of an initiator initiated
1670 * sync negotiation, we limit based on the user
1671 * setting. This allows the system to still accept
1672 * incoming negotiations even if target initiated
1673 * negotiation is not performed.
1675 if (role
== ROLE_TARGET
)
1676 transinfo
= &tinfo
->user
;
1678 transinfo
= &tinfo
->goal
;
1679 *ppr_options
&= transinfo
->ppr_options
;
1680 if (transinfo
->width
== MSG_EXT_WDTR_BUS_8_BIT
) {
1681 maxsync
= MAX(maxsync
, AHC_SYNCRATE_ULTRA2
);
1682 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1684 if (transinfo
->period
== 0) {
1689 *period
= MAX(*period
, transinfo
->period
);
1690 return (ahc_find_syncrate(ahc
, period
, ppr_options
, maxsync
));
1694 * Look up the valid period to SCSIRATE conversion in our table.
1695 * Return the period and offset that should be sent to the target
1696 * if this was the beginning of an SDTR.
1698 struct ahc_syncrate
*
1699 ahc_find_syncrate(struct ahc_softc
*ahc
, u_int
*period
,
1700 u_int
*ppr_options
, u_int maxsync
)
1702 struct ahc_syncrate
*syncrate
;
1704 if ((ahc
->features
& AHC_DT
) == 0)
1705 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1707 /* Skip all DT only entries if DT is not available */
1708 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
1709 && maxsync
< AHC_SYNCRATE_ULTRA2
)
1710 maxsync
= AHC_SYNCRATE_ULTRA2
;
1712 for (syncrate
= &ahc_syncrates
[maxsync
];
1713 syncrate
->rate
!= NULL
;
1717 * The Ultra2 table doesn't go as low
1718 * as for the Fast/Ultra cards.
1720 if ((ahc
->features
& AHC_ULTRA2
) != 0
1721 && (syncrate
->sxfr_u2
== 0))
1724 if (*period
<= syncrate
->period
) {
1726 * When responding to a target that requests
1727 * sync, the requested rate may fall between
1728 * two rates that we can output, but still be
1729 * a rate that we can receive. Because of this,
1730 * we want to respond to the target with
1731 * the same rate that it sent to us even
1732 * if the period we use to send data to it
1733 * is lower. Only lower the response period
1736 if (syncrate
== &ahc_syncrates
[maxsync
])
1737 *period
= syncrate
->period
;
1740 * At some speeds, we only support
1743 if ((syncrate
->sxfr_u2
& ST_SXFR
) != 0)
1744 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1750 || (syncrate
->rate
== NULL
)
1751 || ((ahc
->features
& AHC_ULTRA2
) != 0
1752 && (syncrate
->sxfr_u2
== 0))) {
1753 /* Use asynchronous transfers. */
1756 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
1762 * Convert from an entry in our syncrate table to the SCSI equivalent
1763 * sync "period" factor.
1766 ahc_find_period(struct ahc_softc
*ahc
, u_int scsirate
, u_int maxsync
)
1768 struct ahc_syncrate
*syncrate
;
1770 if ((ahc
->features
& AHC_ULTRA2
) != 0)
1771 scsirate
&= SXFR_ULTRA2
;
1775 syncrate
= &ahc_syncrates
[maxsync
];
1776 while (syncrate
->rate
!= NULL
) {
1778 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1779 if (syncrate
->sxfr_u2
== 0)
1781 else if (scsirate
== (syncrate
->sxfr_u2
& SXFR_ULTRA2
))
1782 return (syncrate
->period
);
1783 } else if (scsirate
== (syncrate
->sxfr
& SXFR
)) {
1784 return (syncrate
->period
);
1788 return (0); /* async */
1792 * Truncate the given synchronous offset to a value the
1793 * current adapter type and syncrate are capable of.
1796 ahc_validate_offset(struct ahc_softc
*ahc
,
1797 struct ahc_initiator_tinfo
*tinfo
,
1798 struct ahc_syncrate
*syncrate
,
1799 u_int
*offset
, int wide
, role_t role
)
1803 /* Limit offset to what we can do */
1804 if (syncrate
== NULL
) {
1806 } else if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1807 maxoffset
= MAX_OFFSET_ULTRA2
;
1810 maxoffset
= MAX_OFFSET_16BIT
;
1812 maxoffset
= MAX_OFFSET_8BIT
;
1814 *offset
= MIN(*offset
, maxoffset
);
1815 if (tinfo
!= NULL
) {
1816 if (role
== ROLE_TARGET
)
1817 *offset
= MIN(*offset
, tinfo
->user
.offset
);
1819 *offset
= MIN(*offset
, tinfo
->goal
.offset
);
1824 * Truncate the given transfer width parameter to a value the
1825 * current adapter type is capable of.
1828 ahc_validate_width(struct ahc_softc
*ahc
, struct ahc_initiator_tinfo
*tinfo
,
1829 u_int
*bus_width
, role_t role
)
1831 switch (*bus_width
) {
1833 if (ahc
->features
& AHC_WIDE
) {
1835 *bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
1839 case MSG_EXT_WDTR_BUS_8_BIT
:
1840 *bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
1843 if (tinfo
!= NULL
) {
1844 if (role
== ROLE_TARGET
)
1845 *bus_width
= MIN(tinfo
->user
.width
, *bus_width
);
1847 *bus_width
= MIN(tinfo
->goal
.width
, *bus_width
);
1852 * Update the bitmask of targets for which the controller should
1853 * negotiate with at the next convenient oportunity. This currently
1854 * means the next time we send the initial identify messages for
1855 * a new transaction.
1858 ahc_update_neg_request(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
1859 struct ahc_tmode_tstate
*tstate
,
1860 struct ahc_initiator_tinfo
*tinfo
, ahc_neg_type neg_type
)
1862 u_int auto_negotiate_orig
;
1864 auto_negotiate_orig
= tstate
->auto_negotiate
;
1865 if (neg_type
== AHC_NEG_ALWAYS
) {
1867 * Force our "current" settings to be
1868 * unknown so that unless a bus reset
1869 * occurs the need to renegotiate is
1870 * recorded persistently.
1872 if ((ahc
->features
& AHC_WIDE
) != 0)
1873 tinfo
->curr
.width
= AHC_WIDTH_UNKNOWN
;
1874 tinfo
->curr
.period
= AHC_PERIOD_UNKNOWN
;
1875 tinfo
->curr
.offset
= AHC_OFFSET_UNKNOWN
;
1877 if (tinfo
->curr
.period
!= tinfo
->goal
.period
1878 || tinfo
->curr
.width
!= tinfo
->goal
.width
1879 || tinfo
->curr
.offset
!= tinfo
->goal
.offset
1880 || tinfo
->curr
.ppr_options
!= tinfo
->goal
.ppr_options
1881 || (neg_type
== AHC_NEG_IF_NON_ASYNC
1882 && (tinfo
->goal
.offset
!= 0
1883 || tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
1884 || tinfo
->goal
.ppr_options
!= 0)))
1885 tstate
->auto_negotiate
|= devinfo
->target_mask
;
1887 tstate
->auto_negotiate
&= ~devinfo
->target_mask
;
1889 return (auto_negotiate_orig
!= tstate
->auto_negotiate
);
1893 * Update the user/goal/curr tables of synchronous negotiation
1894 * parameters as well as, in the case of a current or active update,
1895 * any data structures on the host controller. In the case of an
1896 * active update, the specified target is currently talking to us on
1897 * the bus, so the transfer parameter update must take effect
1901 ahc_set_syncrate(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
1902 struct ahc_syncrate
*syncrate
, u_int period
,
1903 u_int offset
, u_int ppr_options
, u_int type
, int paused
)
1905 struct ahc_initiator_tinfo
*tinfo
;
1906 struct ahc_tmode_tstate
*tstate
;
1913 active
= (type
& AHC_TRANS_ACTIVE
) == AHC_TRANS_ACTIVE
;
1916 if (syncrate
== NULL
) {
1921 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
1922 devinfo
->target
, &tstate
);
1924 if ((type
& AHC_TRANS_USER
) != 0) {
1925 tinfo
->user
.period
= period
;
1926 tinfo
->user
.offset
= offset
;
1927 tinfo
->user
.ppr_options
= ppr_options
;
1930 if ((type
& AHC_TRANS_GOAL
) != 0) {
1931 tinfo
->goal
.period
= period
;
1932 tinfo
->goal
.offset
= offset
;
1933 tinfo
->goal
.ppr_options
= ppr_options
;
1936 old_period
= tinfo
->curr
.period
;
1937 old_offset
= tinfo
->curr
.offset
;
1938 old_ppr
= tinfo
->curr
.ppr_options
;
1940 if ((type
& AHC_TRANS_CUR
) != 0
1941 && (old_period
!= period
1942 || old_offset
!= offset
1943 || old_ppr
!= ppr_options
)) {
1947 scsirate
= tinfo
->scsirate
;
1948 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
1950 scsirate
&= ~(SXFR_ULTRA2
|SINGLE_EDGE
|ENABLE_CRC
);
1951 if (syncrate
!= NULL
) {
1952 scsirate
|= syncrate
->sxfr_u2
;
1953 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0)
1954 scsirate
|= ENABLE_CRC
;
1956 scsirate
|= SINGLE_EDGE
;
1960 scsirate
&= ~(SXFR
|SOFS
);
1962 * Ensure Ultra mode is set properly for
1965 tstate
->ultraenb
&= ~devinfo
->target_mask
;
1966 if (syncrate
!= NULL
) {
1967 if (syncrate
->sxfr
& ULTRA_SXFR
) {
1969 devinfo
->target_mask
;
1971 scsirate
|= syncrate
->sxfr
& SXFR
;
1972 scsirate
|= offset
& SOFS
;
1977 sxfrctl0
= ahc_inb(ahc
, SXFRCTL0
);
1978 sxfrctl0
&= ~FAST20
;
1979 if (tstate
->ultraenb
& devinfo
->target_mask
)
1981 ahc_outb(ahc
, SXFRCTL0
, sxfrctl0
);
1985 ahc_outb(ahc
, SCSIRATE
, scsirate
);
1986 if ((ahc
->features
& AHC_ULTRA2
) != 0)
1987 ahc_outb(ahc
, SCSIOFFSET
, offset
);
1990 tinfo
->scsirate
= scsirate
;
1991 tinfo
->curr
.period
= period
;
1992 tinfo
->curr
.offset
= offset
;
1993 tinfo
->curr
.ppr_options
= ppr_options
;
1995 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
1996 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
1999 kprintf("%s: target %d synchronous at %sMHz%s, "
2000 "offset = 0x%x\n", ahc_name(ahc
),
2001 devinfo
->target
, syncrate
->rate
,
2002 (ppr_options
& MSG_EXT_PPR_DT_REQ
)
2003 ? " DT" : "", offset
);
2005 kprintf("%s: target %d using "
2006 "asynchronous transfers\n",
2007 ahc_name(ahc
), devinfo
->target
);
2012 update_needed
+= ahc_update_neg_request(ahc
, devinfo
, tstate
,
2013 tinfo
, AHC_NEG_TO_GOAL
);
2016 ahc_update_pending_scbs(ahc
);
2020 * Update the user/goal/curr tables of wide negotiation
2021 * parameters as well as, in the case of a current or active update,
2022 * any data structures on the host controller. In the case of an
2023 * active update, the specified target is currently talking to us on
2024 * the bus, so the transfer parameter update must take effect
2028 ahc_set_width(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2029 u_int width
, u_int type
, int paused
)
2031 struct ahc_initiator_tinfo
*tinfo
;
2032 struct ahc_tmode_tstate
*tstate
;
2037 active
= (type
& AHC_TRANS_ACTIVE
) == AHC_TRANS_ACTIVE
;
2039 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
2040 devinfo
->target
, &tstate
);
2042 if ((type
& AHC_TRANS_USER
) != 0)
2043 tinfo
->user
.width
= width
;
2045 if ((type
& AHC_TRANS_GOAL
) != 0)
2046 tinfo
->goal
.width
= width
;
2048 oldwidth
= tinfo
->curr
.width
;
2049 if ((type
& AHC_TRANS_CUR
) != 0 && oldwidth
!= width
) {
2053 scsirate
= tinfo
->scsirate
;
2054 scsirate
&= ~WIDEXFER
;
2055 if (width
== MSG_EXT_WDTR_BUS_16_BIT
)
2056 scsirate
|= WIDEXFER
;
2058 tinfo
->scsirate
= scsirate
;
2061 ahc_outb(ahc
, SCSIRATE
, scsirate
);
2063 tinfo
->curr
.width
= width
;
2065 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
2066 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
2068 kprintf("%s: target %d using %dbit transfers\n",
2069 ahc_name(ahc
), devinfo
->target
,
2070 8 * (0x01 << width
));
2074 update_needed
+= ahc_update_neg_request(ahc
, devinfo
, tstate
,
2075 tinfo
, AHC_NEG_TO_GOAL
);
2077 ahc_update_pending_scbs(ahc
);
2081 * Update the current state of tagged queuing for a given target.
2084 ahc_set_tags(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2087 ahc_platform_set_tags(ahc
, devinfo
, alg
);
2088 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
2089 devinfo
->lun
, AC_TRANSFER_NEG
, &alg
);
2093 * When the transfer settings for a connection change, update any
2094 * in-transit SCBs to contain the new data so the hardware will
2095 * be set correctly during future (re)selections.
2098 ahc_update_pending_scbs(struct ahc_softc
*ahc
)
2100 struct scb
*pending_scb
;
2101 int pending_scb_count
;
2107 * Traverse the pending SCB list and ensure that all of the
2108 * SCBs there have the proper settings.
2110 pending_scb_count
= 0;
2111 LIST_FOREACH(pending_scb
, &ahc
->pending_scbs
, pending_links
) {
2112 struct ahc_devinfo devinfo
;
2113 struct hardware_scb
*pending_hscb
;
2114 struct ahc_initiator_tinfo
*tinfo
;
2115 struct ahc_tmode_tstate
*tstate
;
2117 ahc_scb_devinfo(ahc
, &devinfo
, pending_scb
);
2118 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
.channel
,
2120 devinfo
.target
, &tstate
);
2121 pending_hscb
= pending_scb
->hscb
;
2122 pending_hscb
->control
&= ~ULTRAENB
;
2123 if ((tstate
->ultraenb
& devinfo
.target_mask
) != 0)
2124 pending_hscb
->control
|= ULTRAENB
;
2125 pending_hscb
->scsirate
= tinfo
->scsirate
;
2126 pending_hscb
->scsioffset
= tinfo
->curr
.offset
;
2127 if ((tstate
->auto_negotiate
& devinfo
.target_mask
) == 0
2128 && (pending_scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0) {
2129 pending_scb
->flags
&= ~SCB_AUTO_NEGOTIATE
;
2130 pending_hscb
->control
&= ~MK_MESSAGE
;
2132 ahc_sync_scb(ahc
, pending_scb
,
2133 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
2134 pending_scb_count
++;
2137 if (pending_scb_count
== 0)
2140 if (ahc_is_paused(ahc
)) {
2147 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
2148 /* Ensure that the hscbs down on the card match the new information */
2149 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
2150 struct hardware_scb
*pending_hscb
;
2154 ahc_outb(ahc
, SCBPTR
, i
);
2155 scb_tag
= ahc_inb(ahc
, SCB_TAG
);
2156 pending_scb
= ahc_lookup_scb(ahc
, scb_tag
);
2157 if (pending_scb
== NULL
)
2160 pending_hscb
= pending_scb
->hscb
;
2161 control
= ahc_inb(ahc
, SCB_CONTROL
);
2162 control
&= ~(ULTRAENB
|MK_MESSAGE
);
2163 control
|= pending_hscb
->control
& (ULTRAENB
|MK_MESSAGE
);
2164 ahc_outb(ahc
, SCB_CONTROL
, control
);
2165 ahc_outb(ahc
, SCB_SCSIRATE
, pending_hscb
->scsirate
);
2166 ahc_outb(ahc
, SCB_SCSIOFFSET
, pending_hscb
->scsioffset
);
2168 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
2174 /**************************** Pathing Information *****************************/
2176 ahc_fetch_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2182 if (ahc_inb(ahc
, SSTAT0
) & TARGET
)
2185 role
= ROLE_INITIATOR
;
2187 if (role
== ROLE_TARGET
2188 && (ahc
->features
& AHC_MULTI_TID
) != 0
2189 && (ahc_inb(ahc
, SEQ_FLAGS
)
2190 & (CMDPHASE_PENDING
|TARG_CMD_PENDING
|NO_DISCONNECT
)) != 0) {
2191 /* We were selected, so pull our id from TARGIDIN */
2192 our_id
= ahc_inb(ahc
, TARGIDIN
) & OID
;
2193 } else if ((ahc
->features
& AHC_ULTRA2
) != 0)
2194 our_id
= ahc_inb(ahc
, SCSIID_ULTRA2
) & OID
;
2196 our_id
= ahc_inb(ahc
, SCSIID
) & OID
;
2198 saved_scsiid
= ahc_inb(ahc
, SAVED_SCSIID
);
2199 ahc_compile_devinfo(devinfo
,
2201 SCSIID_TARGET(ahc
, saved_scsiid
),
2202 ahc_inb(ahc
, SAVED_LUN
),
2203 SCSIID_CHANNEL(ahc
, saved_scsiid
),
2207 struct ahc_phase_table_entry
*
2208 ahc_lookup_phase_entry(int phase
)
2210 struct ahc_phase_table_entry
*entry
;
2211 struct ahc_phase_table_entry
*last_entry
;
2214 * num_phases doesn't include the default entry which
2215 * will be returned if the phase doesn't match.
2217 last_entry
= &ahc_phase_table
[num_phases
];
2218 for (entry
= ahc_phase_table
; entry
< last_entry
; entry
++) {
2219 if (phase
== entry
->phase
)
2226 ahc_compile_devinfo(struct ahc_devinfo
*devinfo
, u_int our_id
, u_int target
,
2227 u_int lun
, char channel
, role_t role
)
2229 devinfo
->our_scsiid
= our_id
;
2230 devinfo
->target
= target
;
2232 devinfo
->target_offset
= target
;
2233 devinfo
->channel
= channel
;
2234 devinfo
->role
= role
;
2236 devinfo
->target_offset
+= 8;
2237 devinfo
->target_mask
= (0x01 << devinfo
->target_offset
);
2241 ahc_print_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2243 kprintf("%s:%c:%d:%d: ", ahc_name(ahc
), devinfo
->channel
,
2244 devinfo
->target
, devinfo
->lun
);
2248 ahc_scb_devinfo(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2254 our_id
= SCSIID_OUR_ID(scb
->hscb
->scsiid
);
2255 role
= ROLE_INITIATOR
;
2256 if ((scb
->flags
& SCB_TARGET_SCB
) != 0)
2258 ahc_compile_devinfo(devinfo
, our_id
, SCB_GET_TARGET(ahc
, scb
),
2259 SCB_GET_LUN(scb
), SCB_GET_CHANNEL(ahc
, scb
), role
);
2263 /************************ Message Phase Processing ****************************/
2265 ahc_assert_atn(struct ahc_softc
*ahc
)
2270 if ((ahc
->features
& AHC_DT
) == 0)
2271 scsisigo
|= ahc_inb(ahc
, SCSISIGI
);
2272 ahc_outb(ahc
, SCSISIGO
, scsisigo
);
2276 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2277 * or enters the initial message out phase, we are interrupted. Fill our
2278 * outgoing message buffer with the appropriate message and beging handing
2279 * the message phase(s) manually.
2282 ahc_setup_initiator_msgout(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2286 * To facilitate adding multiple messages together,
2287 * each routine should increment the index and len
2288 * variables instead of setting them explicitly.
2290 ahc
->msgout_index
= 0;
2291 ahc
->msgout_len
= 0;
2293 if ((scb
->flags
& SCB_DEVICE_RESET
) == 0
2294 && ahc_inb(ahc
, MSG_OUT
) == MSG_IDENTIFYFLAG
) {
2297 identify_msg
= MSG_IDENTIFYFLAG
| SCB_GET_LUN(scb
);
2298 if ((scb
->hscb
->control
& DISCENB
) != 0)
2299 identify_msg
|= MSG_IDENTIFY_DISCFLAG
;
2300 ahc
->msgout_buf
[ahc
->msgout_index
++] = identify_msg
;
2303 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
2304 ahc
->msgout_buf
[ahc
->msgout_index
++] =
2305 scb
->hscb
->control
& (TAG_ENB
|SCB_TAG_TYPE
);
2306 ahc
->msgout_buf
[ahc
->msgout_index
++] = scb
->hscb
->tag
;
2307 ahc
->msgout_len
+= 2;
2311 if (scb
->flags
& SCB_DEVICE_RESET
) {
2312 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_BUS_DEV_RESET
;
2314 ahc_print_path(ahc
, scb
);
2315 kprintf("Bus Device Reset Message Sent\n");
2317 * Clear our selection hardware in advance of
2318 * the busfree. We may have an entry in the waiting
2319 * Q for this target, and we don't want to go about
2320 * selecting while we handle the busfree and blow it
2323 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
2324 } else if ((scb
->flags
& SCB_ABORT
) != 0) {
2325 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
2326 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_ABORT_TAG
;
2328 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_ABORT
;
2330 ahc_print_path(ahc
, scb
);
2331 kprintf("Abort%s Message Sent\n",
2332 (scb
->hscb
->control
& TAG_ENB
) != 0 ? " Tag" : "");
2334 * Clear our selection hardware in advance of
2335 * the busfree. We may have an entry in the waiting
2336 * Q for this target, and we don't want to go about
2337 * selecting while we handle the busfree and blow it
2340 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
2341 } else if ((scb
->flags
& (SCB_AUTO_NEGOTIATE
|SCB_NEGOTIATE
)) != 0) {
2342 ahc_build_transfer_msg(ahc
, devinfo
);
2344 kprintf("ahc_intr: AWAITING_MSG for an SCB that "
2345 "does not have a waiting message\n");
2346 kprintf("SCSIID = %x, target_mask = %x\n", scb
->hscb
->scsiid
,
2347 devinfo
->target_mask
);
2348 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2349 "SCB flags = %x", scb
->hscb
->tag
, scb
->hscb
->control
,
2350 ahc_inb(ahc
, MSG_OUT
), scb
->flags
);
2354 * Clear the MK_MESSAGE flag from the SCB so we aren't
2355 * asked to send this message again.
2357 ahc_outb(ahc
, SCB_CONTROL
, ahc_inb(ahc
, SCB_CONTROL
) & ~MK_MESSAGE
);
2358 scb
->hscb
->control
&= ~MK_MESSAGE
;
2359 ahc
->msgout_index
= 0;
2360 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2364 * Build an appropriate transfer negotiation message for the
2365 * currently active target.
2368 ahc_build_transfer_msg(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
2371 * We need to initiate transfer negotiations.
2372 * If our current and goal settings are identical,
2373 * we want to renegotiate due to a check condition.
2375 struct ahc_initiator_tinfo
*tinfo
;
2376 struct ahc_tmode_tstate
*tstate
;
2377 struct ahc_syncrate
*rate
;
2385 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
2386 devinfo
->target
, &tstate
);
2388 * Filter our period based on the current connection.
2389 * If we can't perform DT transfers on this segment (not in LVD
2390 * mode for instance), then our decision to issue a PPR message
2393 period
= tinfo
->goal
.period
;
2394 offset
= tinfo
->goal
.offset
;
2395 ppr_options
= tinfo
->goal
.ppr_options
;
2396 /* Target initiated PPR is not allowed in the SCSI spec */
2397 if (devinfo
->role
== ROLE_TARGET
)
2399 rate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
2400 &ppr_options
, devinfo
->role
);
2401 dowide
= tinfo
->curr
.width
!= tinfo
->goal
.width
;
2402 dosync
= tinfo
->curr
.offset
!= offset
|| tinfo
->curr
.period
!= period
;
2404 * Only use PPR if we have options that need it, even if the device
2405 * claims to support it. There might be an expander in the way
2408 doppr
= ppr_options
!= 0;
2410 if (!dowide
&& !dosync
&& !doppr
) {
2411 dowide
= tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
;
2412 dosync
= tinfo
->goal
.offset
!= 0;
2415 if (!dowide
&& !dosync
&& !doppr
) {
2417 * Force async with a WDTR message if we have a wide bus,
2418 * or just issue an SDTR with a 0 offset.
2420 if ((ahc
->features
& AHC_WIDE
) != 0)
2426 ahc_print_devinfo(ahc
, devinfo
);
2427 kprintf("Ensuring async\n");
2431 /* Target initiated PPR is not allowed in the SCSI spec */
2432 if (devinfo
->role
== ROLE_TARGET
)
2436 * Both the PPR message and SDTR message require the
2437 * goal syncrate to be limited to what the target device
2438 * is capable of handling (based on whether an LVD->SE
2439 * expander is on the bus), so combine these two cases.
2440 * Regardless, guarantee that if we are using WDTR and SDTR
2441 * messages that WDTR comes first.
2443 if (doppr
|| (dosync
&& !dowide
)) {
2445 offset
= tinfo
->goal
.offset
;
2446 ahc_validate_offset(ahc
, tinfo
, rate
, &offset
,
2447 doppr
? tinfo
->goal
.width
2448 : tinfo
->curr
.width
,
2451 ahc_construct_ppr(ahc
, devinfo
, period
, offset
,
2452 tinfo
->goal
.width
, ppr_options
);
2454 ahc_construct_sdtr(ahc
, devinfo
, period
, offset
);
2457 ahc_construct_wdtr(ahc
, devinfo
, tinfo
->goal
.width
);
2462 * Build a synchronous negotiation message in our message
2463 * buffer based on the input parameters.
2466 ahc_construct_sdtr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2467 u_int period
, u_int offset
)
2470 period
= AHC_ASYNC_XFER_PERIOD
;
2471 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2472 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_SDTR_LEN
;
2473 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_SDTR
;
2474 ahc
->msgout_buf
[ahc
->msgout_index
++] = period
;
2475 ahc
->msgout_buf
[ahc
->msgout_index
++] = offset
;
2476 ahc
->msgout_len
+= 5;
2478 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2479 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
2480 devinfo
->lun
, period
, offset
);
2485 * Build a wide negotiation message in our message
2486 * buffer based on the input parameters.
2489 ahc_construct_wdtr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2492 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2493 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_WDTR_LEN
;
2494 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_WDTR
;
2495 ahc
->msgout_buf
[ahc
->msgout_index
++] = bus_width
;
2496 ahc
->msgout_len
+= 4;
2498 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
2499 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
2500 devinfo
->lun
, bus_width
);
2505 * Build a parallel protocol request message in our message
2506 * buffer based on the input parameters.
2509 ahc_construct_ppr(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
2510 u_int period
, u_int offset
, u_int bus_width
,
2514 period
= AHC_ASYNC_XFER_PERIOD
;
2515 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXTENDED
;
2516 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_PPR_LEN
;
2517 ahc
->msgout_buf
[ahc
->msgout_index
++] = MSG_EXT_PPR
;
2518 ahc
->msgout_buf
[ahc
->msgout_index
++] = period
;
2519 ahc
->msgout_buf
[ahc
->msgout_index
++] = 0;
2520 ahc
->msgout_buf
[ahc
->msgout_index
++] = offset
;
2521 ahc
->msgout_buf
[ahc
->msgout_index
++] = bus_width
;
2522 ahc
->msgout_buf
[ahc
->msgout_index
++] = ppr_options
;
2523 ahc
->msgout_len
+= 8;
2525 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2526 "offset %x, ppr_options %x\n", ahc_name(ahc
),
2527 devinfo
->channel
, devinfo
->target
, devinfo
->lun
,
2528 bus_width
, period
, offset
, ppr_options
);
2533 * Clear any active message state.
2536 ahc_clear_msg_state(struct ahc_softc
*ahc
)
2538 ahc
->msgout_len
= 0;
2539 ahc
->msgin_index
= 0;
2540 ahc
->msg_type
= MSG_TYPE_NONE
;
2541 if ((ahc_inb(ahc
, SCSISIGI
) & ATNI
) != 0) {
2543 * The target didn't care to respond to our
2544 * message request, so clear ATN.
2546 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2548 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
);
2549 ahc_outb(ahc
, SEQ_FLAGS2
,
2550 ahc_inb(ahc
, SEQ_FLAGS2
) & ~TARGET_MSG_PENDING
);
2554 ahc_handle_proto_violation(struct ahc_softc
*ahc
)
2556 struct ahc_devinfo devinfo
;
2564 ahc_fetch_devinfo(ahc
, &devinfo
);
2565 scbid
= ahc_inb(ahc
, SCB_TAG
);
2566 scb
= ahc_lookup_scb(ahc
, scbid
);
2567 seq_flags
= ahc_inb(ahc
, SEQ_FLAGS
);
2568 curphase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
2569 lastphase
= ahc_inb(ahc
, LASTPHASE
);
2570 if ((seq_flags
& NOT_IDENTIFIED
) != 0) {
2573 * The reconnecting target either did not send an
2574 * identify message, or did, but we didn't find an SCB
2577 ahc_print_devinfo(ahc
, &devinfo
);
2578 kprintf("Target did not send an IDENTIFY message. "
2579 "LASTPHASE = 0x%x.\n", lastphase
);
2581 } else if (scb
== NULL
) {
2583 * We don't seem to have an SCB active for this
2584 * transaction. Print an error and reset the bus.
2586 ahc_print_devinfo(ahc
, &devinfo
);
2587 kprintf("No SCB found during protocol violation\n");
2588 goto proto_violation_reset
;
2590 aic_set_transaction_status(scb
, CAM_SEQUENCE_FAIL
);
2591 if ((seq_flags
& NO_CDB_SENT
) != 0) {
2592 ahc_print_path(ahc
, scb
);
2593 kprintf("No or incomplete CDB sent to device.\n");
2594 } else if ((ahc_inb(ahc
, SCB_CONTROL
) & STATUS_RCVD
) == 0) {
2596 * The target never bothered to provide status to
2597 * us prior to completing the command. Since we don't
2598 * know the disposition of this command, we must attempt
2599 * to abort it. Assert ATN and prepare to send an abort
2602 ahc_print_path(ahc
, scb
);
2603 kprintf("Completed command without status.\n");
2605 ahc_print_path(ahc
, scb
);
2606 kprintf("Unknown protocol violation.\n");
2607 ahc_dump_card_state(ahc
);
2610 if ((lastphase
& ~P_DATAIN_DT
) == 0
2611 || lastphase
== P_COMMAND
) {
2612 proto_violation_reset
:
2614 * Target either went directly to data/command
2615 * phase or didn't respond to our ATN.
2616 * The only safe thing to do is to blow
2617 * it away with a bus reset.
2619 found
= ahc_reset_channel(ahc
, 'A', TRUE
);
2620 kprintf("%s: Issued Channel %c Bus Reset. "
2621 "%d SCBs aborted\n", ahc_name(ahc
), 'A', found
);
2624 * Leave the selection hardware off in case
2625 * this abort attempt will affect yet to
2628 ahc_outb(ahc
, SCSISEQ
,
2629 ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
);
2630 ahc_assert_atn(ahc
);
2631 ahc_outb(ahc
, MSG_OUT
, HOST_MSG
);
2633 ahc_print_devinfo(ahc
, &devinfo
);
2634 ahc
->msgout_buf
[0] = MSG_ABORT_TASK
;
2635 ahc
->msgout_len
= 1;
2636 ahc
->msgout_index
= 0;
2637 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2639 ahc_print_path(ahc
, scb
);
2640 scb
->flags
|= SCB_ABORT
;
2642 kprintf("Protocol violation %s. Attempting to abort.\n",
2643 ahc_lookup_phase_entry(curphase
)->phasemsg
);
2648 * Manual message loop handler.
2651 ahc_handle_message_phase(struct ahc_softc
*ahc
)
2653 struct ahc_devinfo devinfo
;
2657 ahc_fetch_devinfo(ahc
, &devinfo
);
2658 end_session
= FALSE
;
2659 bus_phase
= ahc_inb(ahc
, SCSISIGI
) & PHASE_MASK
;
2662 switch (ahc
->msg_type
) {
2663 case MSG_TYPE_INITIATOR_MSGOUT
:
2669 if (ahc
->msgout_len
== 0)
2670 panic("HOST_MSG_LOOP interrupt with no active message");
2673 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2674 ahc_print_devinfo(ahc
, &devinfo
);
2675 kprintf("INITIATOR_MSG_OUT");
2678 phasemis
= bus_phase
!= P_MESGOUT
;
2681 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2682 kprintf(" PHASEMIS %s\n",
2683 ahc_lookup_phase_entry(bus_phase
)
2687 if (bus_phase
== P_MESGIN
) {
2689 * Change gears and see if
2690 * this messages is of interest to
2691 * us or should be passed back to
2694 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2695 ahc
->send_msg_perror
= FALSE
;
2696 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGIN
;
2697 ahc
->msgin_index
= 0;
2704 if (ahc
->send_msg_perror
) {
2705 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2706 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2708 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2709 kprintf(" byte 0x%x\n", ahc
->send_msg_perror
);
2711 ahc_outb(ahc
, SCSIDATL
, MSG_PARITY_ERROR
);
2715 msgdone
= ahc
->msgout_index
== ahc
->msgout_len
;
2718 * The target has requested a retry.
2719 * Re-assert ATN, reset our message index to
2722 ahc
->msgout_index
= 0;
2723 ahc_assert_atn(ahc
);
2726 lastbyte
= ahc
->msgout_index
== (ahc
->msgout_len
- 1);
2728 /* Last byte is signified by dropping ATN */
2729 ahc_outb(ahc
, CLRSINT1
, CLRATNO
);
2733 * Clear our interrupt status and present
2734 * the next byte on the bus.
2736 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2738 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2739 kprintf(" byte 0x%x\n",
2740 ahc
->msgout_buf
[ahc
->msgout_index
]);
2742 ahc_outb(ahc
, SCSIDATL
, ahc
->msgout_buf
[ahc
->msgout_index
++]);
2745 case MSG_TYPE_INITIATOR_MSGIN
:
2751 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2752 ahc_print_devinfo(ahc
, &devinfo
);
2753 kprintf("INITIATOR_MSG_IN");
2756 phasemis
= bus_phase
!= P_MESGIN
;
2759 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2760 kprintf(" PHASEMIS %s\n",
2761 ahc_lookup_phase_entry(bus_phase
)
2765 ahc
->msgin_index
= 0;
2766 if (bus_phase
== P_MESGOUT
2767 && (ahc
->send_msg_perror
== TRUE
2768 || (ahc
->msgout_len
!= 0
2769 && ahc
->msgout_index
== 0))) {
2770 ahc
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2777 /* Pull the byte in without acking it */
2778 ahc
->msgin_buf
[ahc
->msgin_index
] = ahc_inb(ahc
, SCSIBUSL
);
2780 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2781 kprintf(" byte 0x%x\n",
2782 ahc
->msgin_buf
[ahc
->msgin_index
]);
2785 message_done
= ahc_parse_msg(ahc
, &devinfo
);
2789 * Clear our incoming message buffer in case there
2790 * is another message following this one.
2792 ahc
->msgin_index
= 0;
2795 * If this message illicited a response,
2796 * assert ATN so the target takes us to the
2797 * message out phase.
2799 if (ahc
->msgout_len
!= 0) {
2801 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2802 ahc_print_devinfo(ahc
, &devinfo
);
2803 kprintf("Asserting ATN for response\n");
2806 ahc_assert_atn(ahc
);
2811 if (message_done
== MSGLOOP_TERMINATED
) {
2815 ahc_outb(ahc
, CLRSINT1
, CLRREQINIT
);
2816 ahc_inb(ahc
, SCSIDATL
);
2820 case MSG_TYPE_TARGET_MSGIN
:
2824 if (ahc
->msgout_len
== 0)
2825 panic("Target MSGIN with no active message");
2828 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2829 ahc_print_devinfo(ahc
, &devinfo
);
2830 kprintf("TARGET_MSG_IN");
2835 * If we interrupted a mesgout session, the initiator
2836 * will not know this until our first REQ. So, we
2837 * only honor mesgout requests after we've sent our
2840 if ((ahc_inb(ahc
, SCSISIGI
) & ATNI
) != 0
2841 && ahc
->msgout_index
> 0) {
2844 * Change gears and see if this messages is
2845 * of interest to us or should be passed back
2849 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2850 kprintf(" Honoring ATN Request.\n");
2852 ahc
->msg_type
= MSG_TYPE_TARGET_MSGOUT
;
2855 * Disable SCSI Programmed I/O during the
2856 * phase change so as to avoid phantom REQs.
2858 ahc_outb(ahc
, SXFRCTL0
,
2859 ahc_inb(ahc
, SXFRCTL0
) & ~SPIOEN
);
2862 * Since SPIORDY asserts when ACK is asserted
2863 * for P_MSGOUT, and SPIORDY's assertion triggered
2864 * our entry into this routine, wait for ACK to
2865 * *de-assert* before changing phases.
2867 while ((ahc_inb(ahc
, SCSISIGI
) & ACKI
) != 0)
2870 ahc_outb(ahc
, SCSISIGO
, P_MESGOUT
| BSYO
);
2873 * All phase line changes require a bus
2874 * settle delay before REQ is asserted.
2875 * [SCSI SPI4 10.7.1]
2877 ahc_flush_device_writes(ahc
);
2878 aic_delay(AHC_BUSSETTLE_DELAY
);
2880 ahc
->msgin_index
= 0;
2881 /* Enable SCSI Programmed I/O to REQ for first byte */
2882 ahc_outb(ahc
, SXFRCTL0
,
2883 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2887 msgdone
= ahc
->msgout_index
== ahc
->msgout_len
;
2889 ahc_outb(ahc
, SXFRCTL0
,
2890 ahc_inb(ahc
, SXFRCTL0
) & ~SPIOEN
);
2896 * Present the next byte on the bus.
2899 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2900 kprintf(" byte 0x%x\n",
2901 ahc
->msgout_buf
[ahc
->msgout_index
]);
2903 ahc_outb(ahc
, SXFRCTL0
, ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2904 ahc_outb(ahc
, SCSIDATL
, ahc
->msgout_buf
[ahc
->msgout_index
++]);
2907 case MSG_TYPE_TARGET_MSGOUT
:
2913 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2914 ahc_print_devinfo(ahc
, &devinfo
);
2915 kprintf("TARGET_MSG_OUT");
2919 * The initiator signals that this is
2920 * the last byte by dropping ATN.
2922 lastbyte
= (ahc_inb(ahc
, SCSISIGI
) & ATNI
) == 0;
2925 * Read the latched byte, but turn off SPIOEN first
2926 * so that we don't inadvertently cause a REQ for the
2929 ahc_outb(ahc
, SXFRCTL0
, ahc_inb(ahc
, SXFRCTL0
) & ~SPIOEN
);
2930 ahc
->msgin_buf
[ahc
->msgin_index
] = ahc_inb(ahc
, SCSIDATL
);
2933 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0)
2934 kprintf(" byte 0x%x\n",
2935 ahc
->msgin_buf
[ahc
->msgin_index
]);
2938 msgdone
= ahc_parse_msg(ahc
, &devinfo
);
2939 if (msgdone
== MSGLOOP_TERMINATED
) {
2941 * The message is *really* done in that it caused
2942 * us to go to bus free. The sequencer has already
2943 * been reset at this point, so pull the ejection
2952 * XXX Read spec about initiator dropping ATN too soon
2953 * and use msgdone to detect it.
2955 if (msgdone
== MSGLOOP_MSGCOMPLETE
) {
2956 ahc
->msgin_index
= 0;
2959 * If this message illicited a response, transition
2960 * to the Message in phase and send it.
2962 if (ahc
->msgout_len
!= 0) {
2964 if ((ahc_debug
& AHC_SHOW_MESSAGES
) != 0) {
2965 ahc_print_devinfo(ahc
, &devinfo
);
2966 kprintf(" preparing response.\n");
2969 ahc_outb(ahc
, SCSISIGO
, P_MESGIN
| BSYO
);
2972 * All phase line changes require a bus
2973 * settle delay before REQ is asserted.
2974 * [SCSI SPI4 10.7.1] When transitioning
2975 * from an OUT to an IN phase, we must
2976 * also wait a data release delay to allow
2977 * the initiator time to release the data
2978 * lines. [SCSI SPI4 10.12]
2980 ahc_flush_device_writes(ahc
);
2981 aic_delay(AHC_BUSSETTLE_DELAY
2982 + AHC_DATARELEASE_DELAY
);
2985 * Enable SCSI Programmed I/O. This will
2986 * immediately cause SPIORDY to assert,
2987 * and the sequencer will call our message
2990 ahc_outb(ahc
, SXFRCTL0
,
2991 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
2992 ahc
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
2993 ahc
->msgin_index
= 0;
3001 /* Ask for the next byte. */
3002 ahc_outb(ahc
, SXFRCTL0
,
3003 ahc_inb(ahc
, SXFRCTL0
) | SPIOEN
);
3009 panic("Unknown REQINIT message type");
3013 ahc_clear_msg_state(ahc
);
3014 ahc_outb(ahc
, RETURN_1
, EXIT_MSG_LOOP
);
3016 ahc_outb(ahc
, RETURN_1
, CONT_MSG_LOOP
);
3020 * See if we sent a particular extended message to the target.
3021 * If "full" is true, return true only if the target saw the full
3022 * message. If "full" is false, return true if the target saw at
3023 * least the first byte of the message.
3026 ahc_sent_msg(struct ahc_softc
*ahc
, ahc_msgtype type
, u_int msgval
, int full
)
3034 while (index
< ahc
->msgout_len
) {
3035 if (ahc
->msgout_buf
[index
] == MSG_EXTENDED
) {
3038 end_index
= index
+ 1 + ahc
->msgout_buf
[index
+ 1];
3039 if (ahc
->msgout_buf
[index
+2] == msgval
3040 && type
== AHCMSG_EXT
) {
3043 if (ahc
->msgout_index
> end_index
)
3045 } else if (ahc
->msgout_index
> index
)
3049 } else if (ahc
->msgout_buf
[index
] >= MSG_SIMPLE_TASK
3050 && ahc
->msgout_buf
[index
] <= MSG_IGN_WIDE_RESIDUE
) {
3052 /* Skip tag type and tag id or residue param*/
3055 /* Single byte message */
3056 if (type
== AHCMSG_1B
3057 && ahc
->msgout_buf
[index
] == msgval
3058 && ahc
->msgout_index
> index
)
3070 * Wait for a complete incoming message, parse it, and respond accordingly.
3073 ahc_parse_msg(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
3075 struct ahc_initiator_tinfo
*tinfo
;
3076 struct ahc_tmode_tstate
*tstate
;
3080 u_int targ_scsirate
;
3082 done
= MSGLOOP_IN_PROG
;
3085 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
, devinfo
->our_scsiid
,
3086 devinfo
->target
, &tstate
);
3087 targ_scsirate
= tinfo
->scsirate
;
3090 * Parse as much of the message as is available,
3091 * rejecting it if we don't support it. When
3092 * the entire message is available and has been
3093 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3094 * that we have parsed an entire message.
3096 * In the case of extended messages, we accept the length
3097 * byte outright and perform more checking once we know the
3098 * extended message type.
3100 switch (ahc
->msgin_buf
[0]) {
3101 case MSG_DISCONNECT
:
3102 case MSG_SAVEDATAPOINTER
:
3103 case MSG_CMDCOMPLETE
:
3104 case MSG_RESTOREPOINTERS
:
3105 case MSG_IGN_WIDE_RESIDUE
:
3107 * End our message loop as these are messages
3108 * the sequencer handles on its own.
3110 done
= MSGLOOP_TERMINATED
;
3112 case MSG_MESSAGE_REJECT
:
3113 response
= ahc_handle_msg_reject(ahc
, devinfo
);
3116 done
= MSGLOOP_MSGCOMPLETE
;
3120 /* Wait for enough of the message to begin validation */
3121 if (ahc
->msgin_index
< 2)
3123 switch (ahc
->msgin_buf
[2]) {
3126 struct ahc_syncrate
*syncrate
;
3132 if (ahc
->msgin_buf
[1] != MSG_EXT_SDTR_LEN
) {
3138 * Wait until we have both args before validating
3139 * and acting on this message.
3141 * Add one to MSG_EXT_SDTR_LEN to account for
3142 * the extended message preamble.
3144 if (ahc
->msgin_index
< (MSG_EXT_SDTR_LEN
+ 1))
3147 period
= ahc
->msgin_buf
[3];
3149 saved_offset
= offset
= ahc
->msgin_buf
[4];
3150 syncrate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
3153 ahc_validate_offset(ahc
, tinfo
, syncrate
, &offset
,
3154 targ_scsirate
& WIDEXFER
,
3157 kprintf("(%s:%c:%d:%d): Received "
3158 "SDTR period %x, offset %x\n\t"
3159 "Filtered to period %x, offset %x\n",
3160 ahc_name(ahc
), devinfo
->channel
,
3161 devinfo
->target
, devinfo
->lun
,
3162 ahc
->msgin_buf
[3], saved_offset
,
3165 ahc_set_syncrate(ahc
, devinfo
,
3167 offset
, ppr_options
,
3168 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3172 * See if we initiated Sync Negotiation
3173 * and didn't have to fall down to async
3176 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_SDTR
, TRUE
)) {
3178 if (saved_offset
!= offset
) {
3179 /* Went too low - force async */
3184 * Send our own SDTR in reply
3187 && devinfo
->role
== ROLE_INITIATOR
) {
3188 kprintf("(%s:%c:%d:%d): Target "
3190 ahc_name(ahc
), devinfo
->channel
,
3191 devinfo
->target
, devinfo
->lun
);
3193 ahc
->msgout_index
= 0;
3194 ahc
->msgout_len
= 0;
3195 ahc_construct_sdtr(ahc
, devinfo
,
3197 ahc
->msgout_index
= 0;
3200 done
= MSGLOOP_MSGCOMPLETE
;
3207 u_int sending_reply
;
3209 sending_reply
= FALSE
;
3210 if (ahc
->msgin_buf
[1] != MSG_EXT_WDTR_LEN
) {
3216 * Wait until we have our arg before validating
3217 * and acting on this message.
3219 * Add one to MSG_EXT_WDTR_LEN to account for
3220 * the extended message preamble.
3222 if (ahc
->msgin_index
< (MSG_EXT_WDTR_LEN
+ 1))
3225 bus_width
= ahc
->msgin_buf
[3];
3226 saved_width
= bus_width
;
3227 ahc_validate_width(ahc
, tinfo
, &bus_width
,
3230 kprintf("(%s:%c:%d:%d): Received WDTR "
3231 "%x filtered to %x\n",
3232 ahc_name(ahc
), devinfo
->channel
,
3233 devinfo
->target
, devinfo
->lun
,
3234 saved_width
, bus_width
);
3237 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_WDTR
, TRUE
)) {
3239 * Don't send a WDTR back to the
3240 * target, since we asked first.
3241 * If the width went higher than our
3242 * request, reject it.
3244 if (saved_width
> bus_width
) {
3246 kprintf("(%s:%c:%d:%d): requested %dBit "
3247 "transfers. Rejecting...\n",
3248 ahc_name(ahc
), devinfo
->channel
,
3249 devinfo
->target
, devinfo
->lun
,
3250 8 * (0x01 << bus_width
));
3255 * Send our own WDTR in reply
3258 && devinfo
->role
== ROLE_INITIATOR
) {
3259 kprintf("(%s:%c:%d:%d): Target "
3261 ahc_name(ahc
), devinfo
->channel
,
3262 devinfo
->target
, devinfo
->lun
);
3264 ahc
->msgout_index
= 0;
3265 ahc
->msgout_len
= 0;
3266 ahc_construct_wdtr(ahc
, devinfo
, bus_width
);
3267 ahc
->msgout_index
= 0;
3269 sending_reply
= TRUE
;
3272 * After a wide message, we are async, but
3273 * some devices don't seem to honor this portion
3274 * of the spec. Force a renegotiation of the
3275 * sync component of our transfer agreement even
3276 * if our goal is async. By updating our width
3277 * after forcing the negotiation, we avoid
3278 * renegotiating for width.
3280 ahc_update_neg_request(ahc
, devinfo
, tstate
,
3281 tinfo
, AHC_NEG_ALWAYS
);
3282 ahc_set_width(ahc
, devinfo
, bus_width
,
3283 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3285 if (sending_reply
== FALSE
&& reject
== FALSE
) {
3288 * We will always have an SDTR to send.
3290 ahc
->msgout_index
= 0;
3291 ahc
->msgout_len
= 0;
3292 ahc_build_transfer_msg(ahc
, devinfo
);
3293 ahc
->msgout_index
= 0;
3296 done
= MSGLOOP_MSGCOMPLETE
;
3301 struct ahc_syncrate
*syncrate
;
3308 u_int saved_ppr_options
;
3310 if (ahc
->msgin_buf
[1] != MSG_EXT_PPR_LEN
) {
3316 * Wait until we have all args before validating
3317 * and acting on this message.
3319 * Add one to MSG_EXT_PPR_LEN to account for
3320 * the extended message preamble.
3322 if (ahc
->msgin_index
< (MSG_EXT_PPR_LEN
+ 1))
3325 period
= ahc
->msgin_buf
[3];
3326 offset
= ahc
->msgin_buf
[5];
3327 bus_width
= ahc
->msgin_buf
[6];
3328 saved_width
= bus_width
;
3329 ppr_options
= ahc
->msgin_buf
[7];
3331 * According to the spec, a DT only
3332 * period factor with no DT option
3333 * set implies async.
3335 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
3338 saved_ppr_options
= ppr_options
;
3339 saved_offset
= offset
;
3342 * Mask out any options we don't support
3343 * on any controller. Transfer options are
3344 * only available if we are negotiating wide.
3346 ppr_options
&= MSG_EXT_PPR_DT_REQ
;
3350 ahc_validate_width(ahc
, tinfo
, &bus_width
,
3352 syncrate
= ahc_devlimited_syncrate(ahc
, tinfo
, &period
,
3355 ahc_validate_offset(ahc
, tinfo
, syncrate
,
3359 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_PPR
, TRUE
)) {
3361 * If we are unable to do any of the
3362 * requested options (we went too low),
3363 * then we'll have to reject the message.
3365 if (saved_width
> bus_width
3366 || saved_offset
!= offset
3367 || saved_ppr_options
!= ppr_options
) {
3376 if (devinfo
->role
!= ROLE_TARGET
)
3377 kprintf("(%s:%c:%d:%d): Target "
3379 ahc_name(ahc
), devinfo
->channel
,
3380 devinfo
->target
, devinfo
->lun
);
3382 kprintf("(%s:%c:%d:%d): Initiator "
3384 ahc_name(ahc
), devinfo
->channel
,
3385 devinfo
->target
, devinfo
->lun
);
3386 ahc
->msgout_index
= 0;
3387 ahc
->msgout_len
= 0;
3388 ahc_construct_ppr(ahc
, devinfo
, period
, offset
,
3389 bus_width
, ppr_options
);
3390 ahc
->msgout_index
= 0;
3394 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
3395 "period %x, offset %x,options %x\n"
3396 "\tFiltered to width %x, period %x, "
3397 "offset %x, options %x\n",
3398 ahc_name(ahc
), devinfo
->channel
,
3399 devinfo
->target
, devinfo
->lun
,
3400 saved_width
, ahc
->msgin_buf
[3],
3401 saved_offset
, saved_ppr_options
,
3402 bus_width
, period
, offset
, ppr_options
);
3404 ahc_set_width(ahc
, devinfo
, bus_width
,
3405 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3407 ahc_set_syncrate(ahc
, devinfo
,
3409 offset
, ppr_options
,
3410 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3412 done
= MSGLOOP_MSGCOMPLETE
;
3416 /* Unknown extended message. Reject it. */
3422 #ifdef AHC_TARGET_MODE
3423 case MSG_BUS_DEV_RESET
:
3424 ahc_handle_devreset(ahc
, devinfo
,
3426 "Bus Device Reset Received",
3427 /*verbose_level*/0);
3429 done
= MSGLOOP_TERMINATED
;
3433 case MSG_CLEAR_QUEUE
:
3437 /* Target mode messages */
3438 if (devinfo
->role
!= ROLE_TARGET
) {
3442 tag
= SCB_LIST_NULL
;
3443 if (ahc
->msgin_buf
[0] == MSG_ABORT_TAG
)
3444 tag
= ahc_inb(ahc
, INITIATOR_TAG
);
3445 ahc_abort_scbs(ahc
, devinfo
->target
, devinfo
->channel
,
3446 devinfo
->lun
, tag
, ROLE_TARGET
,
3449 tstate
= ahc
->enabled_targets
[devinfo
->our_scsiid
];
3450 if (tstate
!= NULL
) {
3451 struct ahc_tmode_lstate
* lstate
;
3453 lstate
= tstate
->enabled_luns
[devinfo
->lun
];
3454 if (lstate
!= NULL
) {
3455 ahc_queue_lstate_event(ahc
, lstate
,
3456 devinfo
->our_scsiid
,
3459 ahc_send_lstate_events(ahc
, lstate
);
3463 done
= MSGLOOP_TERMINATED
;
3467 case MSG_TERM_IO_PROC
:
3475 * Setup to reject the message.
3477 ahc
->msgout_index
= 0;
3478 ahc
->msgout_len
= 1;
3479 ahc
->msgout_buf
[0] = MSG_MESSAGE_REJECT
;
3480 done
= MSGLOOP_MSGCOMPLETE
;
3484 if (done
!= MSGLOOP_IN_PROG
&& !response
)
3485 /* Clear the outgoing message buffer */
3486 ahc
->msgout_len
= 0;
3492 * Process a message reject message.
3495 ahc_handle_msg_reject(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
3498 * What we care about here is if we had an
3499 * outstanding SDTR or WDTR message for this
3500 * target. If we did, this is a signal that
3501 * the target is refusing negotiation.
3504 struct ahc_initiator_tinfo
*tinfo
;
3505 struct ahc_tmode_tstate
*tstate
;
3510 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3511 scb
= ahc_lookup_scb(ahc
, scb_index
);
3512 tinfo
= ahc_fetch_transinfo(ahc
, devinfo
->channel
,
3513 devinfo
->our_scsiid
,
3514 devinfo
->target
, &tstate
);
3515 /* Might be necessary */
3516 last_msg
= ahc_inb(ahc
, LAST_MSG
);
3518 if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_PPR
, /*full*/FALSE
)) {
3520 * Target does not support the PPR message.
3521 * Attempt to negotiate SPI-2 style.
3524 kprintf("(%s:%c:%d:%d): PPR Rejected. "
3525 "Trying WDTR/SDTR\n",
3526 ahc_name(ahc
), devinfo
->channel
,
3527 devinfo
->target
, devinfo
->lun
);
3529 tinfo
->goal
.ppr_options
= 0;
3530 tinfo
->curr
.transport_version
= 2;
3531 tinfo
->goal
.transport_version
= 2;
3532 ahc
->msgout_index
= 0;
3533 ahc
->msgout_len
= 0;
3534 ahc_build_transfer_msg(ahc
, devinfo
);
3535 ahc
->msgout_index
= 0;
3537 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_WDTR
, /*full*/FALSE
)) {
3539 /* note 8bit xfers */
3540 kprintf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3541 "8bit transfers\n", ahc_name(ahc
),
3542 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
3543 ahc_set_width(ahc
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
3544 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3547 * No need to clear the sync rate. If the target
3548 * did not accept the command, our syncrate is
3549 * unaffected. If the target started the negotiation,
3550 * but rejected our response, we already cleared the
3551 * sync rate before sending our WDTR.
3553 if (tinfo
->goal
.offset
!= tinfo
->curr
.offset
) {
3555 /* Start the sync negotiation */
3556 ahc
->msgout_index
= 0;
3557 ahc
->msgout_len
= 0;
3558 ahc_build_transfer_msg(ahc
, devinfo
);
3559 ahc
->msgout_index
= 0;
3562 } else if (ahc_sent_msg(ahc
, AHCMSG_EXT
, MSG_EXT_SDTR
, /*full*/FALSE
)) {
3563 /* note asynch xfers and clear flag */
3564 ahc_set_syncrate(ahc
, devinfo
, /*syncrate*/NULL
, /*period*/0,
3565 /*offset*/0, /*ppr_options*/0,
3566 AHC_TRANS_ACTIVE
|AHC_TRANS_GOAL
,
3568 kprintf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3569 "Using asynchronous transfers\n",
3570 ahc_name(ahc
), devinfo
->channel
,
3571 devinfo
->target
, devinfo
->lun
);
3572 } else if ((scb
->hscb
->control
& MSG_SIMPLE_TASK
) != 0) {
3576 tag_type
= (scb
->hscb
->control
& MSG_SIMPLE_TASK
);
3578 if (tag_type
== MSG_SIMPLE_TASK
) {
3579 kprintf("(%s:%c:%d:%d): refuses tagged commands. "
3580 "Performing non-tagged I/O\n", ahc_name(ahc
),
3581 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
3582 ahc_set_tags(ahc
, devinfo
, AHC_QUEUE_NONE
);
3585 kprintf("(%s:%c:%d:%d): refuses %s tagged commands. "
3586 "Performing simple queue tagged I/O only\n",
3587 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
3588 devinfo
->lun
, tag_type
== MSG_ORDERED_TASK
3589 ? "ordered" : "head of queue");
3590 ahc_set_tags(ahc
, devinfo
, AHC_QUEUE_BASIC
);
3595 * Resend the identify for this CCB as the target
3596 * may believe that the selection is invalid otherwise.
3598 ahc_outb(ahc
, SCB_CONTROL
,
3599 ahc_inb(ahc
, SCB_CONTROL
) & mask
);
3600 scb
->hscb
->control
&= mask
;
3601 aic_set_transaction_tag(scb
, /*enabled*/FALSE
,
3602 /*type*/MSG_SIMPLE_TASK
);
3603 ahc_outb(ahc
, MSG_OUT
, MSG_IDENTIFYFLAG
);
3604 ahc_assert_atn(ahc
);
3607 * This transaction is now at the head of
3608 * the untagged queue for this target.
3610 if ((ahc
->flags
& AHC_SCB_BTT
) == 0) {
3611 struct scb_tailq
*untagged_q
;
3614 &(ahc
->untagged_queues
[devinfo
->target_offset
]);
3615 TAILQ_INSERT_HEAD(untagged_q
, scb
, links
.tqe
);
3616 scb
->flags
|= SCB_UNTAGGEDQ
;
3618 ahc_busy_tcl(ahc
, BUILD_TCL(scb
->hscb
->scsiid
, devinfo
->lun
),
3622 * Requeue all tagged commands for this target
3623 * currently in our posession so they can be
3624 * converted to untagged commands.
3626 ahc_search_qinfifo(ahc
, SCB_GET_TARGET(ahc
, scb
),
3627 SCB_GET_CHANNEL(ahc
, scb
),
3628 SCB_GET_LUN(scb
), /*tag*/SCB_LIST_NULL
,
3629 ROLE_INITIATOR
, CAM_REQUEUE_REQ
,
3633 * Otherwise, we ignore it.
3635 kprintf("%s:%c:%d: Message reject for %x -- ignored\n",
3636 ahc_name(ahc
), devinfo
->channel
, devinfo
->target
,
3643 * Process an ingnore wide residue message.
3646 ahc_handle_ign_wide_residue(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
)
3651 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3652 scb
= ahc_lookup_scb(ahc
, scb_index
);
3654 * XXX Actually check data direction in the sequencer?
3655 * Perhaps add datadir to some spare bits in the hscb?
3657 if ((ahc_inb(ahc
, SEQ_FLAGS
) & DPHASE
) == 0
3658 || aic_get_transfer_dir(scb
) != CAM_DIR_IN
) {
3660 * Ignore the message if we haven't
3661 * seen an appropriate data phase yet.
3665 * If the residual occurred on the last
3666 * transfer and the transfer request was
3667 * expected to end on an odd count, do
3668 * nothing. Otherwise, subtract a byte
3669 * and update the residual count accordingly.
3673 sgptr
= ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
);
3674 if ((sgptr
& SG_LIST_NULL
) != 0
3675 && (ahc_inb(ahc
, SCB_LUN
) & SCB_XFERLEN_ODD
) != 0) {
3677 * If the residual occurred on the last
3678 * transfer and the transfer request was
3679 * expected to end on an odd count, do
3683 struct ahc_dma_seg
*sg
;
3688 /* Pull in all of the sgptr */
3689 sgptr
= ahc_inl(ahc
, SCB_RESIDUAL_SGPTR
);
3690 data_cnt
= ahc_inl(ahc
, SCB_RESIDUAL_DATACNT
);
3692 if ((sgptr
& SG_LIST_NULL
) != 0) {
3694 * The residual data count is not updated
3695 * for the command run to completion case.
3696 * Explicitly zero the count.
3698 data_cnt
&= ~AHC_SG_LEN_MASK
;
3701 data_addr
= ahc_inl(ahc
, SHADDR
);
3705 sgptr
&= SG_PTR_MASK
;
3707 sg
= ahc_sg_bus_to_virt(scb
, sgptr
);
3710 * The residual sg ptr points to the next S/G
3711 * to load so we must go back one.
3714 sglen
= aic_le32toh(sg
->len
) & AHC_SG_LEN_MASK
;
3715 if (sg
!= scb
->sg_list
3716 && sglen
< (data_cnt
& AHC_SG_LEN_MASK
)) {
3719 sglen
= aic_le32toh(sg
->len
);
3721 * Preserve High Address and SG_LIST bits
3722 * while setting the count to 1.
3724 data_cnt
= 1 | (sglen
& (~AHC_SG_LEN_MASK
));
3725 data_addr
= aic_le32toh(sg
->addr
)
3726 + (sglen
& AHC_SG_LEN_MASK
) - 1;
3729 * Increment sg so it points to the
3733 sgptr
= ahc_sg_virt_to_bus(scb
, sg
);
3735 ahc_outl(ahc
, SCB_RESIDUAL_SGPTR
, sgptr
);
3736 ahc_outl(ahc
, SCB_RESIDUAL_DATACNT
, data_cnt
);
3738 * Toggle the "oddness" of the transfer length
3739 * to handle this mid-transfer ignore wide
3740 * residue. This ensures that the oddness is
3741 * correct for subsequent data transfers.
3743 ahc_outb(ahc
, SCB_LUN
,
3744 ahc_inb(ahc
, SCB_LUN
) ^ SCB_XFERLEN_ODD
);
3751 * Reinitialize the data pointers for the active transfer
3752 * based on its current residual.
3755 ahc_reinitialize_dataptrs(struct ahc_softc
*ahc
)
3758 struct ahc_dma_seg
*sg
;
3764 scb_index
= ahc_inb(ahc
, SCB_TAG
);
3765 scb
= ahc_lookup_scb(ahc
, scb_index
);
3766 sgptr
= (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 3) << 24)
3767 | (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 2) << 16)
3768 | (ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
+ 1) << 8)
3769 | ahc_inb(ahc
, SCB_RESIDUAL_SGPTR
);
3771 sgptr
&= SG_PTR_MASK
;
3772 sg
= ahc_sg_bus_to_virt(scb
, sgptr
);
3774 /* The residual sg_ptr always points to the next sg */
3777 resid
= (ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
+ 2) << 16)
3778 | (ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
+ 1) << 8)
3779 | ahc_inb(ahc
, SCB_RESIDUAL_DATACNT
);
3781 dataptr
= aic_le32toh(sg
->addr
)
3782 + (aic_le32toh(sg
->len
) & AHC_SG_LEN_MASK
)
3784 if ((ahc
->flags
& AHC_39BIT_ADDRESSING
) != 0) {
3787 dscommand1
= ahc_inb(ahc
, DSCOMMAND1
);
3788 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
| HADDLDSEL0
);
3789 ahc_outb(ahc
, HADDR
,
3790 (aic_le32toh(sg
->len
) >> 24) & SG_HIGH_ADDR_BITS
);
3791 ahc_outb(ahc
, DSCOMMAND1
, dscommand1
);
3793 ahc_outb(ahc
, HADDR
+ 3, dataptr
>> 24);
3794 ahc_outb(ahc
, HADDR
+ 2, dataptr
>> 16);
3795 ahc_outb(ahc
, HADDR
+ 1, dataptr
>> 8);
3796 ahc_outb(ahc
, HADDR
, dataptr
);
3797 ahc_outb(ahc
, HCNT
+ 2, resid
>> 16);
3798 ahc_outb(ahc
, HCNT
+ 1, resid
>> 8);
3799 ahc_outb(ahc
, HCNT
, resid
);
3800 if ((ahc
->features
& AHC_ULTRA2
) == 0) {
3801 ahc_outb(ahc
, STCNT
+ 2, resid
>> 16);
3802 ahc_outb(ahc
, STCNT
+ 1, resid
>> 8);
3803 ahc_outb(ahc
, STCNT
, resid
);
3808 * Handle the effects of issuing a bus device reset message.
3811 ahc_handle_devreset(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
3812 cam_status status
, char *message
, int verbose_level
)
3814 #ifdef AHC_TARGET_MODE
3815 struct ahc_tmode_tstate
* tstate
;
3820 found
= ahc_abort_scbs(ahc
, devinfo
->target
, devinfo
->channel
,
3821 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, devinfo
->role
,
3824 #ifdef AHC_TARGET_MODE
3826 * Send an immediate notify ccb to all target mord peripheral
3827 * drivers affected by this action.
3829 tstate
= ahc
->enabled_targets
[devinfo
->our_scsiid
];
3830 if (tstate
!= NULL
) {
3831 for (lun
= 0; lun
< AHC_NUM_LUNS
; lun
++) {
3832 struct ahc_tmode_lstate
* lstate
;
3834 lstate
= tstate
->enabled_luns
[lun
];
3838 ahc_queue_lstate_event(ahc
, lstate
, devinfo
->our_scsiid
,
3839 MSG_BUS_DEV_RESET
, /*arg*/0);
3840 ahc_send_lstate_events(ahc
, lstate
);
3846 * Go back to async/narrow transfers and renegotiate.
3848 ahc_set_width(ahc
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
3849 AHC_TRANS_CUR
, /*paused*/TRUE
);
3850 ahc_set_syncrate(ahc
, devinfo
, /*syncrate*/NULL
,
3851 /*period*/0, /*offset*/0, /*ppr_options*/0,
3852 AHC_TRANS_CUR
, /*paused*/TRUE
);
3854 if (status
!= CAM_SEL_TIMEOUT
)
3855 ahc_send_async(ahc
, devinfo
->channel
, devinfo
->target
,
3856 CAM_LUN_WILDCARD
, AC_SENT_BDR
, NULL
);
3859 && (verbose_level
<= bootverbose
))
3860 kprintf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc
),
3861 message
, devinfo
->channel
, devinfo
->target
, found
);
3864 #ifdef AHC_TARGET_MODE
3866 ahc_setup_target_msgin(struct ahc_softc
*ahc
, struct ahc_devinfo
*devinfo
,
3871 * To facilitate adding multiple messages together,
3872 * each routine should increment the index and len
3873 * variables instead of setting them explicitly.
3875 ahc
->msgout_index
= 0;
3876 ahc
->msgout_len
= 0;
3878 if (scb
!= NULL
&& (scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0)
3879 ahc_build_transfer_msg(ahc
, devinfo
);
3881 panic("ahc_intr: AWAITING target message with no message");
3883 ahc
->msgout_index
= 0;
3884 ahc
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
3887 /**************************** Initialization **********************************/
3889 * Allocate a controller structure for a new device
3890 * and perform initial initializion.
3893 ahc_alloc(void *platform_arg
, char *name
)
3895 struct ahc_softc
*ahc
;
3898 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
3899 ahc
= kmalloc(sizeof(*ahc
), M_DEVBUF
, M_WAITOK
);
3901 ahc
= device_get_softc((device_t
)platform_arg
);
3903 memset(ahc
, 0, sizeof(*ahc
));
3904 ahc
->seep_config
= kmalloc(sizeof(*ahc
->seep_config
),
3905 M_DEVBUF
, M_WAITOK
);
3906 LIST_INIT(&ahc
->pending_scbs
);
3907 LIST_INIT(&ahc
->timedout_scbs
);
3908 /* We don't know our unit number until the OSM sets it */
3911 ahc
->description
= NULL
;
3913 ahc
->channel_b
= 'B';
3914 ahc
->chip
= AHC_NONE
;
3915 ahc
->features
= AHC_FENONE
;
3916 ahc
->bugs
= AHC_BUGNONE
;
3917 ahc
->flags
= AHC_FNONE
;
3919 * Default to all error reporting enabled with the
3920 * sequencer operating at its fastest speed.
3921 * The bus attach code may modify this.
3923 ahc
->seqctl
= FASTMODE
;
3925 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++)
3926 TAILQ_INIT(&ahc
->untagged_queues
[i
]);
3927 if (ahc_platform_alloc(ahc
, platform_arg
) != 0) {
3935 ahc_softc_init(struct ahc_softc
*ahc
)
3938 /* The IRQMS bit is only valid on VL and EISA chips */
3939 if ((ahc
->chip
& AHC_PCI
) == 0)
3940 ahc
->unpause
= ahc_inb(ahc
, HCNTRL
) & IRQMS
;
3943 ahc
->pause
= ahc
->unpause
| PAUSE
;
3944 /* XXX The shared scb data stuff should be deprecated */
3945 if (ahc
->scb_data
== NULL
) {
3946 ahc
->scb_data
= kmalloc(sizeof(*ahc
->scb_data
),
3947 M_DEVBUF
, M_WAITOK
| M_ZERO
);
3954 ahc_softc_insert(struct ahc_softc
*ahc
)
3956 struct ahc_softc
*list_ahc
;
3958 #if AIC_PCI_CONFIG > 0
3960 * Second Function PCI devices need to inherit some
3961 * settings from function 0.
3963 if ((ahc
->chip
& AHC_BUS_MASK
) == AHC_PCI
3964 && (ahc
->features
& AHC_MULTI_FUNC
) != 0) {
3965 TAILQ_FOREACH(list_ahc
, &ahc_tailq
, links
) {
3966 aic_dev_softc_t list_pci
;
3967 aic_dev_softc_t pci
;
3969 list_pci
= list_ahc
->dev_softc
;
3970 pci
= ahc
->dev_softc
;
3971 if (aic_get_pci_slot(list_pci
) == aic_get_pci_slot(pci
)
3972 && aic_get_pci_bus(list_pci
) == aic_get_pci_bus(pci
)) {
3973 struct ahc_softc
*master
;
3974 struct ahc_softc
*slave
;
3976 if (aic_get_pci_function(list_pci
) == 0) {
3983 slave
->flags
&= ~AHC_BIOS_ENABLED
;
3985 master
->flags
& AHC_BIOS_ENABLED
;
3986 slave
->flags
&= ~AHC_PRIMARY_CHANNEL
;
3988 master
->flags
& AHC_PRIMARY_CHANNEL
;
3996 * Insertion sort into our list of softcs.
3998 list_ahc
= TAILQ_FIRST(&ahc_tailq
);
3999 while (list_ahc
!= NULL
4000 && ahc_softc_comp(ahc
, list_ahc
) <= 0)
4001 list_ahc
= TAILQ_NEXT(list_ahc
, links
);
4002 if (list_ahc
!= NULL
)
4003 TAILQ_INSERT_BEFORE(list_ahc
, ahc
, links
);
4005 TAILQ_INSERT_TAIL(&ahc_tailq
, ahc
, links
);
4010 * Verify that the passed in softc pointer is for a
4011 * controller that is still configured.
4014 ahc_find_softc(struct ahc_softc
*ahc
)
4016 struct ahc_softc
*list_ahc
;
4018 TAILQ_FOREACH(list_ahc
, &ahc_tailq
, links
) {
4019 if (list_ahc
== ahc
)
4026 ahc_set_unit(struct ahc_softc
*ahc
, int unit
)
4032 ahc_set_name(struct ahc_softc
*ahc
, char *name
)
4034 if (ahc
->name
!= NULL
)
4035 kfree(ahc
->name
, M_DEVBUF
);
4040 ahc_free(struct ahc_softc
*ahc
)
4044 ahc_terminate_recovery_thread(ahc
);
4045 switch (ahc
->init_level
) {
4051 aic_dmamap_unload(ahc
, ahc
->shared_data_dmat
,
4052 ahc
->shared_data_dmamap
);
4055 aic_dmamem_free(ahc
, ahc
->shared_data_dmat
, ahc
->qoutfifo
,
4056 ahc
->shared_data_dmamap
);
4057 aic_dmamap_destroy(ahc
, ahc
->shared_data_dmat
,
4058 ahc
->shared_data_dmamap
);
4061 aic_dma_tag_destroy(ahc
, ahc
->shared_data_dmat
);
4064 aic_dma_tag_destroy(ahc
, ahc
->buffer_dmat
);
4072 aic_dma_tag_destroy(ahc
, ahc
->parent_dmat
);
4074 ahc_platform_free(ahc
);
4075 ahc_fini_scbdata(ahc
);
4076 for (i
= 0; i
< AHC_NUM_TARGETS
; i
++) {
4077 struct ahc_tmode_tstate
*tstate
;
4079 tstate
= ahc
->enabled_targets
[i
];
4080 if (tstate
!= NULL
) {
4081 #ifdef AHC_TARGET_MODE
4084 for (j
= 0; j
< AHC_NUM_LUNS
; j
++) {
4085 struct ahc_tmode_lstate
*lstate
;
4087 lstate
= tstate
->enabled_luns
[j
];
4088 if (lstate
!= NULL
) {
4089 xpt_free_path(lstate
->path
);
4090 kfree(lstate
, M_DEVBUF
);
4094 kfree(tstate
, M_DEVBUF
);
4097 #ifdef AHC_TARGET_MODE
4098 if (ahc
->black_hole
!= NULL
) {
4099 xpt_free_path(ahc
->black_hole
->path
);
4100 kfree(ahc
->black_hole
, M_DEVBUF
);
4103 if (ahc
->name
!= NULL
)
4104 kfree(ahc
->name
, M_DEVBUF
);
4105 if (ahc
->seep_config
!= NULL
)
4106 kfree(ahc
->seep_config
, M_DEVBUF
);
4107 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
4108 kfree(ahc
, M_DEVBUF
);
4114 ahc_shutdown(void *arg
)
4116 struct ahc_softc
*ahc
;
4119 ahc
= (struct ahc_softc
*)arg
;
4121 /* This will reset most registers to 0, but not all */
4122 ahc_reset(ahc
, /*reinit*/FALSE
);
4123 ahc_outb(ahc
, SCSISEQ
, 0);
4124 ahc_outb(ahc
, SXFRCTL0
, 0);
4125 ahc_outb(ahc
, DSPCISTATUS
, 0);
4127 for (i
= TARG_SCSIRATE
; i
< SCSICONF
; i
++)
4128 ahc_outb(ahc
, i
, 0);
4132 * Reset the controller and record some information about it
4133 * that is only available just after a reset. If "reinit" is
4134 * non-zero, this reset occured after initial configuration
4135 * and the caller requests that the chip be fully reinitialized
4136 * to a runable state. Chip interrupts are *not* enabled after
4137 * a reinitialization. The caller must enable interrupts via
4138 * ahc_intr_enable().
4141 ahc_reset(struct ahc_softc
*ahc
, int reinit
)
4144 u_int sxfrctl1_a
, sxfrctl1_b
;
4149 * Preserve the value of the SXFRCTL1 register for all channels.
4150 * It contains settings that affect termination and we don't want
4151 * to disturb the integrity of the bus.
4155 if ((ahc
->chip
& AHC_CHIPID_MASK
) == AHC_AIC7770
) {
4159 * Save channel B's settings in case this chip
4160 * is setup for TWIN channel operation.
4162 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
4163 ahc_outb(ahc
, SBLKCTL
, sblkctl
| SELBUSB
);
4164 sxfrctl1_b
= ahc_inb(ahc
, SXFRCTL1
);
4165 ahc_outb(ahc
, SBLKCTL
, sblkctl
& ~SELBUSB
);
4167 sxfrctl1_a
= ahc_inb(ahc
, SXFRCTL1
);
4169 ahc_outb(ahc
, HCNTRL
, CHIPRST
| ahc
->pause
);
4172 * Ensure that the reset has finished. We delay 1000us
4173 * prior to reading the register to make sure the chip
4174 * has sufficiently completed its reset to handle register
4180 } while (--wait
&& !(ahc_inb(ahc
, HCNTRL
) & CHIPRSTACK
));
4183 kprintf("%s: WARNING - Failed chip reset! "
4184 "Trying to initialize anyway.\n", ahc_name(ahc
));
4186 ahc_outb(ahc
, HCNTRL
, ahc
->pause
);
4188 /* Determine channel configuration */
4189 sblkctl
= ahc_inb(ahc
, SBLKCTL
) & (SELBUSB
|SELWIDE
);
4190 /* No Twin Channel PCI cards */
4191 if ((ahc
->chip
& AHC_PCI
) != 0)
4192 sblkctl
&= ~SELBUSB
;
4195 /* Single Narrow Channel */
4199 ahc
->features
|= AHC_WIDE
;
4203 ahc
->features
|= AHC_TWIN
;
4206 kprintf(" Unsupported adapter type. Ignoring\n");
4213 * We must always initialize STPWEN to 1 before we
4214 * restore the saved values. STPWEN is initialized
4215 * to a tri-state condition which can only be cleared
4218 if ((ahc
->features
& AHC_TWIN
) != 0) {
4221 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
4222 ahc_outb(ahc
, SBLKCTL
, sblkctl
| SELBUSB
);
4223 ahc_outb(ahc
, SXFRCTL1
, sxfrctl1_b
);
4224 ahc_outb(ahc
, SBLKCTL
, sblkctl
& ~SELBUSB
);
4226 ahc_outb(ahc
, SXFRCTL1
, sxfrctl1_a
);
4231 * If a recovery action has forced a chip reset,
4232 * re-initialize the chip to our liking.
4234 error
= ahc
->bus_chip_init(ahc
);
4244 * Determine the number of SCBs available on the controller
4247 ahc_probe_scbs(struct ahc_softc
*ahc
) {
4250 for (i
= 0; i
< AHC_SCB_MAX
; i
++) {
4252 ahc_outb(ahc
, SCBPTR
, i
);
4253 ahc_outb(ahc
, SCB_BASE
, i
);
4254 if (ahc_inb(ahc
, SCB_BASE
) != i
)
4256 ahc_outb(ahc
, SCBPTR
, 0);
4257 if (ahc_inb(ahc
, SCB_BASE
) != 0)
4264 ahc_dmamap_cb(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
4268 baddr
= (bus_addr_t
*)arg
;
4269 *baddr
= segs
->ds_addr
;
4273 ahc_build_free_scb_list(struct ahc_softc
*ahc
)
4279 if ((ahc
->flags
& AHC_LSCBS_ENABLED
) != 0)
4282 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
4285 ahc_outb(ahc
, SCBPTR
, i
);
4288 * Touch all SCB bytes to avoid parity errors
4289 * should one of our debugging routines read
4290 * an otherwise uninitiatlized byte.
4292 for (j
= 0; j
< scbsize
; j
++)
4293 ahc_outb(ahc
, SCB_BASE
+j
, 0xFF);
4295 /* Clear the control byte. */
4296 ahc_outb(ahc
, SCB_CONTROL
, 0);
4298 /* Set the next pointer */
4299 if ((ahc
->flags
& AHC_PAGESCBS
) != 0)
4300 ahc_outb(ahc
, SCB_NEXT
, i
+1);
4302 ahc_outb(ahc
, SCB_NEXT
, SCB_LIST_NULL
);
4304 /* Make the tag number, SCSIID, and lun invalid */
4305 ahc_outb(ahc
, SCB_TAG
, SCB_LIST_NULL
);
4306 ahc_outb(ahc
, SCB_SCSIID
, 0xFF);
4307 ahc_outb(ahc
, SCB_LUN
, 0xFF);
4310 if ((ahc
->flags
& AHC_PAGESCBS
) != 0) {
4311 /* SCB 0 heads the free list. */
4312 ahc_outb(ahc
, FREE_SCBH
, 0);
4315 ahc_outb(ahc
, FREE_SCBH
, SCB_LIST_NULL
);
4318 /* Make sure that the last SCB terminates the free list */
4319 ahc_outb(ahc
, SCBPTR
, i
-1);
4320 ahc_outb(ahc
, SCB_NEXT
, SCB_LIST_NULL
);
4324 ahc_init_scbdata(struct ahc_softc
*ahc
)
4326 struct scb_data
*scb_data
;
4328 scb_data
= ahc
->scb_data
;
4329 SLIST_INIT(&scb_data
->free_scbs
);
4330 SLIST_INIT(&scb_data
->sg_maps
);
4332 /* Allocate SCB resources */
4333 scb_data
->scbarray
= kmalloc(sizeof(struct scb
) * AHC_SCB_MAX_ALLOC
,
4334 M_DEVBUF
, M_INTWAIT
| M_ZERO
);
4336 /* Determine the number of hardware SCBs and initialize them */
4338 scb_data
->maxhscbs
= ahc_probe_scbs(ahc
);
4339 if (ahc
->scb_data
->maxhscbs
== 0) {
4340 kprintf("%s: No SCB space found\n", ahc_name(ahc
));
4345 * Create our DMA tags. These tags define the kinds of device
4346 * accessible memory allocations and memory mappings we will
4347 * need to perform during normal operation.
4349 * Unless we need to further restrict the allocation, we rely
4350 * on the restrictions of the parent dmat, hence the common
4351 * use of MAXADDR and MAXSIZE.
4354 /* DMA tag for our hardware scb structures */
4355 if (aic_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4356 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4357 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4358 /*highaddr*/BUS_SPACE_MAXADDR
,
4359 /*filter*/NULL
, /*filterarg*/NULL
,
4360 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
),
4362 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4363 /*flags*/0, &scb_data
->hscb_dmat
) != 0) {
4367 scb_data
->init_level
++;
4369 /* Allocation for our hscbs */
4370 if (aic_dmamem_alloc(ahc
, scb_data
->hscb_dmat
,
4371 (void **)&scb_data
->hscbs
,
4372 BUS_DMA_NOWAIT
, &scb_data
->hscb_dmamap
) != 0) {
4376 scb_data
->init_level
++;
4378 /* And permanently map them */
4379 aic_dmamap_load(ahc
, scb_data
->hscb_dmat
, scb_data
->hscb_dmamap
,
4381 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
),
4382 ahc_dmamap_cb
, &scb_data
->hscb_busaddr
, /*flags*/0);
4384 scb_data
->init_level
++;
4386 /* DMA tag for our sense buffers */
4387 if (aic_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4388 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4389 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4390 /*highaddr*/BUS_SPACE_MAXADDR
,
4391 /*filter*/NULL
, /*filterarg*/NULL
,
4392 AHC_SCB_MAX_ALLOC
* sizeof(struct scsi_sense_data
),
4394 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4395 /*flags*/0, &scb_data
->sense_dmat
) != 0) {
4399 scb_data
->init_level
++;
4402 if (aic_dmamem_alloc(ahc
, scb_data
->sense_dmat
,
4403 (void **)&scb_data
->sense
,
4404 BUS_DMA_NOWAIT
, &scb_data
->sense_dmamap
) != 0) {
4408 scb_data
->init_level
++;
4410 /* And permanently map them */
4411 aic_dmamap_load(ahc
, scb_data
->sense_dmat
, scb_data
->sense_dmamap
,
4413 AHC_SCB_MAX_ALLOC
* sizeof(struct scsi_sense_data
),
4414 ahc_dmamap_cb
, &scb_data
->sense_busaddr
, /*flags*/0);
4416 scb_data
->init_level
++;
4418 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4419 if (aic_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/8,
4420 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4421 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4422 /*highaddr*/BUS_SPACE_MAXADDR
,
4423 /*filter*/NULL
, /*filterarg*/NULL
,
4424 PAGE_SIZE
, /*nsegments*/1,
4425 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4426 /*flags*/0, &scb_data
->sg_dmat
) != 0) {
4430 scb_data
->init_level
++;
4432 /* Perform initial CCB allocation */
4433 memset(scb_data
->hscbs
, 0,
4434 AHC_SCB_MAX_ALLOC
* sizeof(struct hardware_scb
));
4435 while (ahc_alloc_scbs(ahc
) != 0)
4438 if (scb_data
->numscbs
== 0) {
4439 kprintf("%s: ahc_init_scbdata - "
4440 "Unable to allocate initial scbs\n",
4446 * Reserve the next queued SCB.
4448 ahc
->next_queued_scb
= ahc_get_scb(ahc
);
4451 * Note that we were successful
4461 ahc_fini_scbdata(struct ahc_softc
*ahc
)
4463 struct scb_data
*scb_data
;
4465 scb_data
= ahc
->scb_data
;
4466 if (scb_data
== NULL
)
4469 switch (scb_data
->init_level
) {
4473 struct sg_map_node
*sg_map
;
4475 while ((sg_map
= SLIST_FIRST(&scb_data
->sg_maps
))!= NULL
) {
4476 SLIST_REMOVE_HEAD(&scb_data
->sg_maps
, links
);
4477 aic_dmamap_unload(ahc
, scb_data
->sg_dmat
,
4479 aic_dmamem_free(ahc
, scb_data
->sg_dmat
,
4482 kfree(sg_map
, M_DEVBUF
);
4484 aic_dma_tag_destroy(ahc
, scb_data
->sg_dmat
);
4487 aic_dmamap_unload(ahc
, scb_data
->sense_dmat
,
4488 scb_data
->sense_dmamap
);
4490 aic_dmamem_free(ahc
, scb_data
->sense_dmat
, scb_data
->sense
,
4491 scb_data
->sense_dmamap
);
4492 aic_dmamap_destroy(ahc
, scb_data
->sense_dmat
,
4493 scb_data
->sense_dmamap
);
4495 aic_dma_tag_destroy(ahc
, scb_data
->sense_dmat
);
4497 aic_dmamap_unload(ahc
, scb_data
->hscb_dmat
,
4498 scb_data
->hscb_dmamap
);
4500 aic_dmamem_free(ahc
, scb_data
->hscb_dmat
, scb_data
->hscbs
,
4501 scb_data
->hscb_dmamap
);
4502 aic_dmamap_destroy(ahc
, scb_data
->hscb_dmat
,
4503 scb_data
->hscb_dmamap
);
4505 aic_dma_tag_destroy(ahc
, scb_data
->hscb_dmat
);
4510 if (scb_data
->scbarray
!= NULL
)
4511 kfree(scb_data
->scbarray
, M_DEVBUF
);
4515 ahc_alloc_scbs(struct ahc_softc
*ahc
)
4517 struct scb_data
*scb_data
;
4518 struct scb
*next_scb
;
4519 struct sg_map_node
*sg_map
;
4520 bus_addr_t physaddr
;
4521 struct ahc_dma_seg
*segs
;
4525 scb_data
= ahc
->scb_data
;
4526 if (scb_data
->numscbs
>= AHC_SCB_MAX_ALLOC
)
4527 /* Can't allocate any more */
4530 next_scb
= &scb_data
->scbarray
[scb_data
->numscbs
];
4532 sg_map
= kmalloc(sizeof(*sg_map
), M_DEVBUF
, M_INTWAIT
);
4534 /* Allocate S/G space for the next batch of SCBS */
4535 if (aic_dmamem_alloc(ahc
, scb_data
->sg_dmat
,
4536 (void **)&sg_map
->sg_vaddr
,
4537 BUS_DMA_NOWAIT
, &sg_map
->sg_dmamap
) != 0) {
4538 kfree(sg_map
, M_DEVBUF
);
4542 SLIST_INSERT_HEAD(&scb_data
->sg_maps
, sg_map
, links
);
4544 aic_dmamap_load(ahc
, scb_data
->sg_dmat
, sg_map
->sg_dmamap
,
4545 sg_map
->sg_vaddr
, PAGE_SIZE
, ahc_dmamap_cb
,
4546 &sg_map
->sg_physaddr
, /*flags*/0);
4548 segs
= sg_map
->sg_vaddr
;
4549 physaddr
= sg_map
->sg_physaddr
;
4551 newcount
= (PAGE_SIZE
/ (AHC_NSEG
* sizeof(struct ahc_dma_seg
)));
4552 newcount
= MIN(newcount
, (AHC_SCB_MAX_ALLOC
- scb_data
->numscbs
));
4553 for (i
= 0; i
< newcount
; i
++) {
4554 struct scb_platform_data
*pdata
;
4558 pdata
= kmalloc(sizeof(*pdata
), M_DEVBUF
, M_INTWAIT
);
4559 next_scb
->platform_data
= pdata
;
4560 next_scb
->sg_map
= sg_map
;
4561 next_scb
->sg_list
= segs
;
4563 * The sequencer always starts with the second entry.
4564 * The first entry is embedded in the scb.
4566 next_scb
->sg_list_phys
= physaddr
+ sizeof(struct ahc_dma_seg
);
4567 next_scb
->ahc_softc
= ahc
;
4568 next_scb
->flags
= SCB_FLAG_NONE
;
4570 error
= aic_dmamap_create(ahc
, ahc
->buffer_dmat
, /*flags*/0,
4575 next_scb
->hscb
= &scb_data
->hscbs
[scb_data
->numscbs
];
4576 next_scb
->hscb
->tag
= ahc
->scb_data
->numscbs
;
4577 SLIST_INSERT_HEAD(&ahc
->scb_data
->free_scbs
,
4578 next_scb
, links
.sle
);
4580 physaddr
+= (AHC_NSEG
* sizeof(struct ahc_dma_seg
));
4582 ahc
->scb_data
->numscbs
++;
4588 ahc_controller_info(struct ahc_softc
*ahc
, char *buf
)
4592 len
= ksprintf(buf
, "%s: ",
4593 ahc_chip_names
[ahc
->chip
& AHC_CHIPID_MASK
]);
4595 if ((ahc
->features
& AHC_TWIN
) != 0) {
4596 len
= ksprintf(buf
, "Twin Channel, A SCSI Id=%d, "
4597 "B SCSI Id=%d, primary %c, ",
4598 ahc
->our_id
, ahc
->our_id_b
,
4599 (ahc
->flags
& AHC_PRIMARY_CHANNEL
) + 'A');
4605 if ((ahc
->features
& AHC_ULTRA
) != 0) {
4607 } else if ((ahc
->features
& AHC_DT
) != 0) {
4608 speed
= "Ultra160 ";
4609 } else if ((ahc
->features
& AHC_ULTRA2
) != 0) {
4612 if ((ahc
->features
& AHC_WIDE
) != 0) {
4617 len
= ksprintf(buf
, "%s%s Channel %c, SCSI Id=%d, ",
4618 speed
, type
, ahc
->channel
, ahc
->our_id
);
4622 if ((ahc
->flags
& AHC_PAGESCBS
) != 0)
4623 ksprintf(buf
, "%d/%d SCBs",
4624 ahc
->scb_data
->maxhscbs
, AHC_MAX_QUEUE
);
4626 ksprintf(buf
, "%d SCBs", ahc
->scb_data
->maxhscbs
);
4630 ahc_chip_init(struct ahc_softc
*ahc
)
4636 u_int scsiseq_template
;
4639 ahc_outb(ahc
, SEQ_FLAGS
, 0);
4640 ahc_outb(ahc
, SEQ_FLAGS2
, 0);
4642 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4643 if (ahc
->features
& AHC_TWIN
) {
4646 * Setup Channel B first.
4648 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) | SELBUSB
);
4649 term
= (ahc
->flags
& AHC_TERM_ENB_B
) != 0 ? STPWEN
: 0;
4650 ahc_outb(ahc
, SCSIID
, ahc
->our_id_b
);
4651 scsi_conf
= ahc_inb(ahc
, SCSICONF
+ 1);
4652 ahc_outb(ahc
, SXFRCTL1
, (scsi_conf
& (ENSPCHK
|STIMESEL
))
4653 |term
|ahc
->seltime_b
|ENSTIMER
|ACTNEGEN
);
4654 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4655 ahc_outb(ahc
, SIMODE0
, ahc_inb(ahc
, SIMODE0
)|ENIOERR
);
4656 ahc_outb(ahc
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
4657 ahc_outb(ahc
, SXFRCTL0
, DFON
|SPIOEN
);
4659 /* Select Channel A */
4660 ahc_outb(ahc
, SBLKCTL
, ahc_inb(ahc
, SBLKCTL
) & ~SELBUSB
);
4662 term
= (ahc
->flags
& AHC_TERM_ENB_A
) != 0 ? STPWEN
: 0;
4663 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4664 ahc_outb(ahc
, SCSIID_ULTRA2
, ahc
->our_id
);
4666 ahc_outb(ahc
, SCSIID
, ahc
->our_id
);
4667 scsi_conf
= ahc_inb(ahc
, SCSICONF
);
4668 ahc_outb(ahc
, SXFRCTL1
, (scsi_conf
& (ENSPCHK
|STIMESEL
))
4670 |ENSTIMER
|ACTNEGEN
);
4671 if ((ahc
->features
& AHC_ULTRA2
) != 0)
4672 ahc_outb(ahc
, SIMODE0
, ahc_inb(ahc
, SIMODE0
)|ENIOERR
);
4673 ahc_outb(ahc
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
4674 ahc_outb(ahc
, SXFRCTL0
, DFON
|SPIOEN
);
4676 /* There are no untagged SCBs active yet. */
4677 for (i
= 0; i
< 16; i
++) {
4678 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, 0));
4679 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
4683 * The SCB based BTT allows an entry per
4684 * target and lun pair.
4686 for (lun
= 1; lun
< AHC_NUM_LUNS
; lun
++)
4687 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, lun
));
4691 /* All of our queues are empty */
4692 for (i
= 0; i
< 256; i
++)
4693 ahc
->qoutfifo
[i
] = SCB_LIST_NULL
;
4694 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_PREREAD
);
4696 for (i
= 0; i
< 256; i
++)
4697 ahc
->qinfifo
[i
] = SCB_LIST_NULL
;
4699 if ((ahc
->features
& AHC_MULTI_TID
) != 0) {
4700 ahc_outb(ahc
, TARGID
, 0);
4701 ahc_outb(ahc
, TARGID
+ 1, 0);
4705 * Tell the sequencer where it can find our arrays in memory.
4707 physaddr
= ahc
->scb_data
->hscb_busaddr
;
4708 ahc_outb(ahc
, HSCB_ADDR
, physaddr
& 0xFF);
4709 ahc_outb(ahc
, HSCB_ADDR
+ 1, (physaddr
>> 8) & 0xFF);
4710 ahc_outb(ahc
, HSCB_ADDR
+ 2, (physaddr
>> 16) & 0xFF);
4711 ahc_outb(ahc
, HSCB_ADDR
+ 3, (physaddr
>> 24) & 0xFF);
4713 physaddr
= ahc
->shared_data_busaddr
;
4714 ahc_outb(ahc
, SHARED_DATA_ADDR
, physaddr
& 0xFF);
4715 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 1, (physaddr
>> 8) & 0xFF);
4716 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 2, (physaddr
>> 16) & 0xFF);
4717 ahc_outb(ahc
, SHARED_DATA_ADDR
+ 3, (physaddr
>> 24) & 0xFF);
4720 * Initialize the group code to command length table.
4721 * This overrides the values in TARG_SCSIRATE, so only
4722 * setup the table after we have processed that information.
4724 ahc_outb(ahc
, CMDSIZE_TABLE
, 5);
4725 ahc_outb(ahc
, CMDSIZE_TABLE
+ 1, 9);
4726 ahc_outb(ahc
, CMDSIZE_TABLE
+ 2, 9);
4727 ahc_outb(ahc
, CMDSIZE_TABLE
+ 3, 0);
4728 ahc_outb(ahc
, CMDSIZE_TABLE
+ 4, 15);
4729 ahc_outb(ahc
, CMDSIZE_TABLE
+ 5, 11);
4730 ahc_outb(ahc
, CMDSIZE_TABLE
+ 6, 0);
4731 ahc_outb(ahc
, CMDSIZE_TABLE
+ 7, 0);
4733 if ((ahc
->features
& AHC_HS_MAILBOX
) != 0)
4734 ahc_outb(ahc
, HS_MAILBOX
, 0);
4736 /* Tell the sequencer of our initial queue positions */
4737 if ((ahc
->features
& AHC_TARGETMODE
) != 0) {
4738 ahc
->tqinfifonext
= 1;
4739 ahc_outb(ahc
, KERNEL_TQINPOS
, ahc
->tqinfifonext
- 1);
4740 ahc_outb(ahc
, TQINPOS
, ahc
->tqinfifonext
);
4742 ahc
->qinfifonext
= 0;
4743 ahc
->qoutfifonext
= 0;
4744 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
4745 ahc_outb(ahc
, QOFF_CTLSTA
, SCB_QSIZE_256
);
4746 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
4747 ahc_outb(ahc
, SNSCB_QOFF
, ahc
->qinfifonext
);
4748 ahc_outb(ahc
, SDSCB_QOFF
, 0);
4750 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
4751 ahc_outb(ahc
, QINPOS
, ahc
->qinfifonext
);
4752 ahc_outb(ahc
, QOUTPOS
, ahc
->qoutfifonext
);
4755 /* We don't have any waiting selections */
4756 ahc_outb(ahc
, WAITING_SCBH
, SCB_LIST_NULL
);
4758 /* Our disconnection list is empty too */
4759 ahc_outb(ahc
, DISCONNECTED_SCBH
, SCB_LIST_NULL
);
4761 /* Message out buffer starts empty */
4762 ahc_outb(ahc
, MSG_OUT
, MSG_NOOP
);
4765 * Setup the allowed SCSI Sequences based on operational mode.
4766 * If we are a target, we'll enalbe select in operations once
4767 * we've had a lun enabled.
4769 scsiseq_template
= ENSELO
|ENAUTOATNO
|ENAUTOATNP
;
4770 if ((ahc
->flags
& AHC_INITIATORROLE
) != 0)
4771 scsiseq_template
|= ENRSELI
;
4772 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq_template
);
4774 /* Initialize our list of free SCBs. */
4775 ahc_build_free_scb_list(ahc
);
4778 * Tell the sequencer which SCB will be the next one it receives.
4780 ahc_outb(ahc
, NEXT_QUEUED_SCB
, ahc
->next_queued_scb
->hscb
->tag
);
4783 * Load the Sequencer program and Enable the adapter
4787 kprintf("%s: Downloading Sequencer Program...",
4790 error
= ahc_loadseq(ahc
);
4794 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
4798 * Wait for up to 500ms for our transceivers
4799 * to settle. If the adapter does not have
4800 * a cable attached, the transceivers may
4801 * never settle, so don't complain if we
4805 (ahc_inb(ahc
, SBLKCTL
) & (ENAB40
|ENAB20
)) == 0 && wait
;
4814 * Start the board, ready for normal operation
4817 ahc_init(struct ahc_softc
*ahc
)
4826 size_t driver_data_size
;
4829 if ((ahc_debug
& AHC_DEBUG_SEQUENCER
) != 0)
4830 ahc
->flags
|= AHC_SEQUENCER_DEBUG
;
4833 #ifdef AHC_PRINT_SRAM
4834 kprintf("Scratch Ram:");
4835 for (i
= 0x20; i
< 0x5f; i
++) {
4836 if (((i
% 8) == 0) && (i
!= 0)) {
4839 kprintf (" 0x%x", ahc_inb(ahc
, i
));
4841 if ((ahc
->features
& AHC_MORE_SRAM
) != 0) {
4842 for (i
= 0x70; i
< 0x7f; i
++) {
4843 if (((i
% 8) == 0) && (i
!= 0)) {
4846 kprintf (" 0x%x", ahc_inb(ahc
, i
));
4851 * Reading uninitialized scratch ram may
4852 * generate parity errors.
4854 ahc_outb(ahc
, CLRINT
, CLRPARERR
);
4855 ahc_outb(ahc
, CLRINT
, CLRBRKADRINT
);
4860 * Assume we have a board at this stage and it has been reset.
4862 if ((ahc
->flags
& AHC_USEDEFAULTS
) != 0)
4863 ahc
->our_id
= ahc
->our_id_b
= 7;
4866 * Default to allowing initiator operations.
4868 ahc
->flags
|= AHC_INITIATORROLE
;
4871 * Only allow target mode features if this unit has them enabled.
4873 if ((AHC_TMODE_ENABLE
& (0x1 << ahc
->unit
)) == 0)
4874 ahc
->features
&= ~AHC_TARGETMODE
;
4877 /* DMA tag for mapping buffers into device visible space. */
4878 if (aic_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4879 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4880 /*lowaddr*/ahc
->flags
& AHC_39BIT_ADDRESSING
4881 ? (bus_addr_t
)0x7FFFFFFFFFULL
4882 : BUS_SPACE_MAXADDR_32BIT
,
4883 /*highaddr*/BUS_SPACE_MAXADDR
,
4884 /*filter*/NULL
, /*filterarg*/NULL
,
4885 /*maxsize*/(AHC_NSEG
- 1) * PAGE_SIZE
,
4886 /*nsegments*/AHC_NSEG
,
4887 /*maxsegsz*/AHC_MAXTRANSFER_SIZE
,
4888 /*flags*/BUS_DMA_ALLOCNOW
,
4889 &ahc
->buffer_dmat
) != 0) {
4897 * DMA tag for our command fifos and other data in system memory
4898 * the card's sequencer must be able to access. For initiator
4899 * roles, we need to allocate space for the qinfifo and qoutfifo.
4900 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4901 * When providing for the target mode role, we must additionally
4902 * provide space for the incoming target command fifo and an extra
4903 * byte to deal with a dma bug in some chip versions.
4905 driver_data_size
= 2 * 256 * sizeof(uint8_t);
4906 if ((ahc
->features
& AHC_TARGETMODE
) != 0)
4907 driver_data_size
+= AHC_TMODE_CMDS
* sizeof(struct target_cmd
)
4908 + /*DMA WideOdd Bug Buffer*/1;
4909 if (aic_dma_tag_create(ahc
, ahc
->parent_dmat
, /*alignment*/1,
4910 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
4911 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
4912 /*highaddr*/BUS_SPACE_MAXADDR
,
4913 /*filter*/NULL
, /*filterarg*/NULL
,
4916 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
4917 /*flags*/0, &ahc
->shared_data_dmat
) != 0) {
4923 /* Allocation of driver data */
4924 if (aic_dmamem_alloc(ahc
, ahc
->shared_data_dmat
,
4925 (void **)&ahc
->qoutfifo
,
4926 BUS_DMA_NOWAIT
, &ahc
->shared_data_dmamap
) != 0) {
4932 /* And permanently map it in */
4933 aic_dmamap_load(ahc
, ahc
->shared_data_dmat
, ahc
->shared_data_dmamap
,
4934 ahc
->qoutfifo
, driver_data_size
, ahc_dmamap_cb
,
4935 &ahc
->shared_data_busaddr
, /*flags*/0);
4937 if ((ahc
->features
& AHC_TARGETMODE
) != 0) {
4938 ahc
->targetcmds
= (struct target_cmd
*)ahc
->qoutfifo
;
4939 ahc
->qoutfifo
= (uint8_t *)&ahc
->targetcmds
[AHC_TMODE_CMDS
];
4940 ahc
->dma_bug_buf
= ahc
->shared_data_busaddr
4941 + driver_data_size
- 1;
4942 /* All target command blocks start out invalid. */
4943 for (i
= 0; i
< AHC_TMODE_CMDS
; i
++)
4944 ahc
->targetcmds
[i
].cmd_valid
= 0;
4945 ahc_sync_tqinfifo(ahc
, BUS_DMASYNC_PREREAD
);
4946 ahc
->qoutfifo
= (uint8_t *)&ahc
->targetcmds
[256];
4948 ahc
->qinfifo
= &ahc
->qoutfifo
[256];
4952 /* Allocate SCB data now that buffer_dmat is initialized */
4953 if (ahc
->scb_data
->maxhscbs
== 0)
4954 if (ahc_init_scbdata(ahc
) != 0)
4958 * Allocate a tstate to house information for our
4959 * initiator presence on the bus as well as the user
4960 * data for any target mode initiator.
4962 if (ahc_alloc_tstate(ahc
, ahc
->our_id
, 'A') == NULL
) {
4963 kprintf("%s: unable to allocate ahc_tmode_tstate. "
4964 "Failing attach\n", ahc_name(ahc
));
4968 if ((ahc
->features
& AHC_TWIN
) != 0) {
4969 if (ahc_alloc_tstate(ahc
, ahc
->our_id_b
, 'B') == NULL
) {
4970 kprintf("%s: unable to allocate ahc_tmode_tstate. "
4971 "Failing attach\n", ahc_name(ahc
));
4977 * Fire up a recovery thread for this controller.
4979 error
= ahc_spawn_recovery_thread(ahc
);
4983 if (ahc
->scb_data
->maxhscbs
< AHC_SCB_MAX_ALLOC
) {
4984 ahc
->flags
|= AHC_PAGESCBS
;
4986 ahc
->flags
&= ~AHC_PAGESCBS
;
4990 if (ahc_debug
& AHC_SHOW_MISC
) {
4991 kprintf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4992 "ahc_dma %u bytes\n",
4994 (u_int
)sizeof(struct hardware_scb
),
4995 (u_int
)sizeof(struct scb
),
4996 (u_int
)sizeof(struct ahc_dma_seg
));
4998 #endif /* AHC_DEBUG */
5001 * Look at the information that board initialization or
5002 * the board bios has left us.
5004 if (ahc
->features
& AHC_TWIN
) {
5005 scsi_conf
= ahc_inb(ahc
, SCSICONF
+ 1);
5006 if ((scsi_conf
& RESET_SCSI
) != 0
5007 && (ahc
->flags
& AHC_INITIATORROLE
) != 0)
5008 ahc
->flags
|= AHC_RESET_BUS_B
;
5011 scsi_conf
= ahc_inb(ahc
, SCSICONF
);
5012 if ((scsi_conf
& RESET_SCSI
) != 0
5013 && (ahc
->flags
& AHC_INITIATORROLE
) != 0)
5014 ahc
->flags
|= AHC_RESET_BUS_A
;
5017 tagenable
= ALL_TARGETS_MASK
;
5019 /* Grab the disconnection disable table and invert it for our needs */
5020 if ((ahc
->flags
& AHC_USEDEFAULTS
) != 0) {
5021 kprintf("%s: Host Adapter Bios disabled. Using default SCSI "
5022 "device parameters\n", ahc_name(ahc
));
5023 ahc
->flags
|= AHC_EXTENDED_TRANS_A
|AHC_EXTENDED_TRANS_B
|
5024 AHC_TERM_ENB_A
|AHC_TERM_ENB_B
;
5025 discenable
= ALL_TARGETS_MASK
;
5026 if ((ahc
->features
& AHC_ULTRA
) != 0)
5027 ultraenb
= ALL_TARGETS_MASK
;
5029 discenable
= ~((ahc_inb(ahc
, DISC_DSB
+ 1) << 8)
5030 | ahc_inb(ahc
, DISC_DSB
));
5031 if ((ahc
->features
& (AHC_ULTRA
|AHC_ULTRA2
)) != 0)
5032 ultraenb
= (ahc_inb(ahc
, ULTRA_ENB
+ 1) << 8)
5033 | ahc_inb(ahc
, ULTRA_ENB
);
5036 if ((ahc
->features
& (AHC_WIDE
|AHC_TWIN
)) == 0)
5039 for (i
= 0; i
<= max_targ
; i
++) {
5040 struct ahc_initiator_tinfo
*tinfo
;
5041 struct ahc_tmode_tstate
*tstate
;
5047 our_id
= ahc
->our_id
;
5049 if (i
> 7 && (ahc
->features
& AHC_TWIN
) != 0) {
5051 our_id
= ahc
->our_id_b
;
5054 tinfo
= ahc_fetch_transinfo(ahc
, channel
, our_id
,
5055 target_id
, &tstate
);
5056 /* Default to async narrow across the board */
5057 memset(tinfo
, 0, sizeof(*tinfo
));
5058 if (ahc
->flags
& AHC_USEDEFAULTS
) {
5059 if ((ahc
->features
& AHC_WIDE
) != 0)
5060 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
5063 * These will be truncated when we determine the
5064 * connection type we have with the target.
5066 tinfo
->user
.period
= ahc_syncrates
->period
;
5067 tinfo
->user
.offset
= MAX_OFFSET
;
5072 /* Take the settings leftover in scratch RAM. */
5073 scsirate
= ahc_inb(ahc
, TARG_SCSIRATE
+ i
);
5075 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
5079 if ((scsirate
& SOFS
) == 0x0F) {
5081 * Haven't negotiated yet,
5082 * so the format is different.
5084 scsirate
= (scsirate
& SXFR
) >> 4
5087 | (scsirate
& WIDEXFER
);
5088 offset
= MAX_OFFSET_ULTRA2
;
5090 offset
= ahc_inb(ahc
, TARG_OFFSET
+ i
);
5091 if ((scsirate
& ~WIDEXFER
) == 0 && offset
!= 0)
5092 /* Set to the lowest sync rate, 5MHz */
5094 maxsync
= AHC_SYNCRATE_ULTRA2
;
5095 if ((ahc
->features
& AHC_DT
) != 0)
5096 maxsync
= AHC_SYNCRATE_DT
;
5097 tinfo
->user
.period
=
5098 ahc_find_period(ahc
, scsirate
, maxsync
);
5100 tinfo
->user
.period
= 0;
5102 tinfo
->user
.offset
= MAX_OFFSET
;
5103 if ((scsirate
& SXFR_ULTRA2
) <= 8/*10MHz*/
5104 && (ahc
->features
& AHC_DT
) != 0)
5105 tinfo
->user
.ppr_options
=
5107 } else if ((scsirate
& SOFS
) != 0) {
5108 if ((scsirate
& SXFR
) == 0x40
5109 && (ultraenb
& mask
) != 0) {
5110 /* Treat 10MHz as a non-ultra speed */
5114 tinfo
->user
.period
=
5115 ahc_find_period(ahc
, scsirate
,
5117 ? AHC_SYNCRATE_ULTRA
5118 : AHC_SYNCRATE_FAST
);
5119 if (tinfo
->user
.period
!= 0)
5120 tinfo
->user
.offset
= MAX_OFFSET
;
5122 if (tinfo
->user
.period
== 0)
5123 tinfo
->user
.offset
= 0;
5124 if ((scsirate
& WIDEXFER
) != 0
5125 && (ahc
->features
& AHC_WIDE
) != 0)
5126 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
5127 tinfo
->user
.protocol_version
= 4;
5128 if ((ahc
->features
& AHC_DT
) != 0)
5129 tinfo
->user
.transport_version
= 3;
5131 tinfo
->user
.transport_version
= 2;
5132 tinfo
->goal
.protocol_version
= 2;
5133 tinfo
->goal
.transport_version
= 2;
5134 tinfo
->curr
.protocol_version
= 2;
5135 tinfo
->curr
.transport_version
= 2;
5137 tstate
->ultraenb
= 0;
5139 ahc
->user_discenable
= discenable
;
5140 ahc
->user_tagenable
= tagenable
;
5142 return (ahc
->bus_chip_init(ahc
));
5146 ahc_intr_enable(struct ahc_softc
*ahc
, int enable
)
5150 hcntrl
= ahc_inb(ahc
, HCNTRL
);
5152 ahc
->pause
&= ~INTEN
;
5153 ahc
->unpause
&= ~INTEN
;
5156 ahc
->pause
|= INTEN
;
5157 ahc
->unpause
|= INTEN
;
5159 ahc_outb(ahc
, HCNTRL
, hcntrl
);
5163 * Ensure that the card is paused in a location
5164 * outside of all critical sections and that all
5165 * pending work is completed prior to returning.
5166 * This routine should only be called from outside
5167 * an interrupt context.
5170 ahc_pause_and_flushwork(struct ahc_softc
*ahc
)
5177 ahc
->flags
|= AHC_ALL_INTERRUPTS
;
5183 * Give the sequencer some time to service
5184 * any active selections.
5191 ahc_outb(ahc
, SCSISEQ
, ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
);
5192 intstat
= ahc_inb(ahc
, INTSTAT
);
5193 if ((intstat
& INT_PEND
) == 0) {
5194 ahc_clear_critical_section(ahc
);
5195 intstat
= ahc_inb(ahc
, INTSTAT
);
5198 && (intstat
!= 0xFF || (ahc
->features
& AHC_REMOVABLE
) == 0)
5199 && ((intstat
& INT_PEND
) != 0
5200 || (ahc_inb(ahc
, SSTAT0
) & (SELDO
|SELINGO
)) != 0));
5201 if (maxloops
== 0) {
5202 kprintf("Infinite interrupt loop, INTSTAT = %x",
5203 ahc_inb(ahc
, INTSTAT
));
5205 ahc_platform_flushwork(ahc
);
5206 ahc
->flags
&= ~AHC_ALL_INTERRUPTS
;
5210 ahc_suspend(struct ahc_softc
*ahc
)
5213 ahc_pause_and_flushwork(ahc
);
5215 if (LIST_FIRST(&ahc
->pending_scbs
) != NULL
) {
5220 #ifdef AHC_TARGET_MODE
5222 * XXX What about ATIOs that have not yet been serviced?
5223 * Perhaps we should just refuse to be suspended if we
5224 * are acting in a target role.
5226 if (ahc
->pending_device
!= NULL
) {
5236 ahc_resume(struct ahc_softc
*ahc
)
5239 ahc_reset(ahc
, /*reinit*/TRUE
);
5240 ahc_intr_enable(ahc
, TRUE
);
5245 /************************** Busy Target Table *********************************/
5247 * Return the untagged transaction id for a given target/channel lun.
5248 * Optionally, clear the entry.
5251 ahc_index_busy_tcl(struct ahc_softc
*ahc
, u_int tcl
)
5254 u_int target_offset
;
5256 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5259 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5260 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5261 scbid
= ahc_inb(ahc
, SCB_64_BTT
+ TCL_TARGET_OFFSET(tcl
));
5262 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5264 target_offset
= TCL_TARGET_OFFSET(tcl
);
5265 scbid
= ahc_inb(ahc
, BUSY_TARGETS
+ target_offset
);
5272 ahc_unbusy_tcl(struct ahc_softc
*ahc
, u_int tcl
)
5274 u_int target_offset
;
5276 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5279 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5280 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5281 ahc_outb(ahc
, SCB_64_BTT
+TCL_TARGET_OFFSET(tcl
), SCB_LIST_NULL
);
5282 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5284 target_offset
= TCL_TARGET_OFFSET(tcl
);
5285 ahc_outb(ahc
, BUSY_TARGETS
+ target_offset
, SCB_LIST_NULL
);
5290 ahc_busy_tcl(struct ahc_softc
*ahc
, u_int tcl
, u_int scbid
)
5292 u_int target_offset
;
5294 if ((ahc
->flags
& AHC_SCB_BTT
) != 0) {
5297 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
5298 ahc_outb(ahc
, SCBPTR
, TCL_LUN(tcl
));
5299 ahc_outb(ahc
, SCB_64_BTT
+ TCL_TARGET_OFFSET(tcl
), scbid
);
5300 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
5302 target_offset
= TCL_TARGET_OFFSET(tcl
);
5303 ahc_outb(ahc
, BUSY_TARGETS
+ target_offset
, scbid
);
5307 /************************** SCB and SCB queue management **********************/
5309 ahc_match_scb(struct ahc_softc
*ahc
, struct scb
*scb
, int target
,
5310 char channel
, int lun
, u_int tag
, role_t role
)
5312 int targ
= SCB_GET_TARGET(ahc
, scb
);
5313 char chan
= SCB_GET_CHANNEL(ahc
, scb
);
5314 int slun
= SCB_GET_LUN(scb
);
5317 match
= ((chan
== channel
) || (channel
== ALL_CHANNELS
));
5319 match
= ((targ
== target
) || (target
== CAM_TARGET_WILDCARD
));
5321 match
= ((lun
== slun
) || (lun
== CAM_LUN_WILDCARD
));
5323 #ifdef AHC_TARGET_MODE
5326 group
= XPT_FC_GROUP(scb
->io_ctx
->ccb_h
.func_code
);
5327 if (role
== ROLE_INITIATOR
) {
5328 match
= (group
!= XPT_FC_GROUP_TMODE
)
5329 && ((tag
== scb
->hscb
->tag
)
5330 || (tag
== SCB_LIST_NULL
));
5331 } else if (role
== ROLE_TARGET
) {
5332 match
= (group
== XPT_FC_GROUP_TMODE
)
5333 && ((tag
== scb
->io_ctx
->csio
.tag_id
)
5334 || (tag
== SCB_LIST_NULL
));
5336 #else /* !AHC_TARGET_MODE */
5337 match
= ((tag
== scb
->hscb
->tag
) || (tag
== SCB_LIST_NULL
));
5338 #endif /* AHC_TARGET_MODE */
5345 ahc_freeze_devq(struct ahc_softc
*ahc
, struct scb
*scb
)
5351 target
= SCB_GET_TARGET(ahc
, scb
);
5352 lun
= SCB_GET_LUN(scb
);
5353 channel
= SCB_GET_CHANNEL(ahc
, scb
);
5355 ahc_search_qinfifo(ahc
, target
, channel
, lun
,
5356 /*tag*/SCB_LIST_NULL
, ROLE_UNKNOWN
,
5357 CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
5359 ahc_platform_freeze_devq(ahc
, scb
);
5363 ahc_qinfifo_requeue_tail(struct ahc_softc
*ahc
, struct scb
*scb
)
5365 struct scb
*prev_scb
;
5368 if (ahc_qinfifo_count(ahc
) != 0) {
5372 prev_pos
= ahc
->qinfifonext
- 1;
5373 prev_tag
= ahc
->qinfifo
[prev_pos
];
5374 prev_scb
= ahc_lookup_scb(ahc
, prev_tag
);
5376 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5377 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5378 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
5380 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
5385 ahc_qinfifo_requeue(struct ahc_softc
*ahc
, struct scb
*prev_scb
,
5388 if (prev_scb
== NULL
) {
5389 ahc_outb(ahc
, NEXT_QUEUED_SCB
, scb
->hscb
->tag
);
5391 prev_scb
->hscb
->next
= scb
->hscb
->tag
;
5392 ahc_sync_scb(ahc
, prev_scb
,
5393 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
5395 ahc
->qinfifo
[ahc
->qinfifonext
++] = scb
->hscb
->tag
;
5396 scb
->hscb
->next
= ahc
->next_queued_scb
->hscb
->tag
;
5397 ahc_sync_scb(ahc
, scb
, BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
5401 ahc_qinfifo_count(struct ahc_softc
*ahc
)
5406 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5407 qinpos
= ahc_inb(ahc
, SNSCB_QOFF
);
5408 ahc_outb(ahc
, SNSCB_QOFF
, qinpos
);
5410 qinpos
= ahc_inb(ahc
, QINPOS
);
5411 diff
= ahc
->qinfifonext
- qinpos
;
5416 ahc_search_qinfifo(struct ahc_softc
*ahc
, int target
, char channel
,
5417 int lun
, u_int tag
, role_t role
, uint32_t status
,
5418 ahc_search_action action
)
5421 struct scb
*prev_scb
;
5431 qintail
= ahc
->qinfifonext
;
5432 have_qregs
= (ahc
->features
& AHC_QUEUE_REGS
) != 0;
5434 qinstart
= ahc_inb(ahc
, SNSCB_QOFF
);
5435 ahc_outb(ahc
, SNSCB_QOFF
, qinstart
);
5437 qinstart
= ahc_inb(ahc
, QINPOS
);
5442 if (action
== SEARCH_COMPLETE
) {
5444 * Don't attempt to run any queued untagged transactions
5445 * until we are done with the abort process.
5447 ahc_freeze_untagged_queues(ahc
);
5451 * Start with an empty queue. Entries that are not chosen
5452 * for removal will be re-added to the queue as we go.
5454 ahc
->qinfifonext
= qinpos
;
5455 ahc_outb(ahc
, NEXT_QUEUED_SCB
, ahc
->next_queued_scb
->hscb
->tag
);
5457 while (qinpos
!= qintail
) {
5458 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qinpos
]);
5460 kprintf("qinpos = %d, SCB index = %d\n",
5461 qinpos
, ahc
->qinfifo
[qinpos
]);
5465 if (ahc_match_scb(ahc
, scb
, target
, channel
, lun
, tag
, role
)) {
5467 * We found an scb that needs to be acted on.
5471 case SEARCH_COMPLETE
:
5476 ostat
= aic_get_transaction_status(scb
);
5477 if (ostat
== CAM_REQ_INPROG
)
5478 aic_set_transaction_status(scb
, status
);
5479 cstat
= aic_get_transaction_status(scb
);
5480 if (cstat
!= CAM_REQ_CMP
)
5481 aic_freeze_scb(scb
);
5482 if ((scb
->flags
& SCB_ACTIVE
) == 0)
5483 kprintf("Inactive SCB in qinfifo\n");
5491 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5496 ahc_qinfifo_requeue(ahc
, prev_scb
, scb
);
5502 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
5503 ahc_outb(ahc
, HNSCB_QOFF
, ahc
->qinfifonext
);
5505 ahc_outb(ahc
, KERNEL_QINPOS
, ahc
->qinfifonext
);
5508 if (action
!= SEARCH_COUNT
5510 && (qinstart
!= ahc
->qinfifonext
)) {
5512 * The sequencer may be in the process of dmaing
5513 * down the SCB at the beginning of the queue.
5514 * This could be problematic if either the first,
5515 * or the second SCB is removed from the queue
5516 * (the first SCB includes a pointer to the "next"
5517 * SCB to dma). If we have removed any entries, swap
5518 * the first element in the queue with the next HSCB
5519 * so the sequencer will notice that NEXT_QUEUED_SCB
5520 * has changed during its dma attempt and will retry
5523 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qinstart
]);
5526 kprintf("found = %d, qinstart = %d, qinfifionext = %d\n",
5527 found
, qinstart
, ahc
->qinfifonext
);
5528 panic("First/Second Qinfifo fixup\n");
5531 * ahc_swap_with_next_hscb forces our next pointer to
5532 * point to the reserved SCB for future commands. Save
5533 * and restore our original next pointer to maintain
5536 next
= scb
->hscb
->next
;
5537 ahc
->scb_data
->scbindex
[scb
->hscb
->tag
] = NULL
;
5538 ahc_swap_with_next_hscb(ahc
, scb
);
5539 scb
->hscb
->next
= next
;
5540 ahc
->qinfifo
[qinstart
] = scb
->hscb
->tag
;
5542 /* Tell the card about the new head of the qinfifo. */
5543 ahc_outb(ahc
, NEXT_QUEUED_SCB
, scb
->hscb
->tag
);
5545 /* Fixup the tail "next" pointer. */
5546 qintail
= ahc
->qinfifonext
- 1;
5547 scb
= ahc_lookup_scb(ahc
, ahc
->qinfifo
[qintail
]);
5548 scb
->hscb
->next
= ahc
->next_queued_scb
->hscb
->tag
;
5552 * Search waiting for selection list.
5554 curscbptr
= ahc_inb(ahc
, SCBPTR
);
5555 next
= ahc_inb(ahc
, WAITING_SCBH
); /* Start at head of list. */
5556 prev
= SCB_LIST_NULL
;
5558 while (next
!= SCB_LIST_NULL
) {
5561 ahc_outb(ahc
, SCBPTR
, next
);
5562 scb_index
= ahc_inb(ahc
, SCB_TAG
);
5563 if (scb_index
>= ahc
->scb_data
->numscbs
) {
5564 kprintf("Waiting List inconsistency. "
5565 "SCB index == %d, yet numscbs == %d.",
5566 scb_index
, ahc
->scb_data
->numscbs
);
5567 ahc_dump_card_state(ahc
);
5568 panic("for safety");
5570 scb
= ahc_lookup_scb(ahc
, scb_index
);
5572 kprintf("scb_index = %d, next = %d\n",
5574 panic("Waiting List traversal\n");
5576 if (ahc_match_scb(ahc
, scb
, target
, channel
,
5577 lun
, SCB_LIST_NULL
, role
)) {
5579 * We found an scb that needs to be acted on.
5583 case SEARCH_COMPLETE
:
5588 ostat
= aic_get_transaction_status(scb
);
5589 if (ostat
== CAM_REQ_INPROG
)
5590 aic_set_transaction_status(scb
,
5592 cstat
= aic_get_transaction_status(scb
);
5593 if (cstat
!= CAM_REQ_CMP
)
5594 aic_freeze_scb(scb
);
5595 if ((scb
->flags
& SCB_ACTIVE
) == 0)
5596 kprintf("Inactive SCB in Wait List\n");
5601 next
= ahc_rem_wscb(ahc
, next
, prev
);
5605 next
= ahc_inb(ahc
, SCB_NEXT
);
5611 next
= ahc_inb(ahc
, SCB_NEXT
);
5614 ahc_outb(ahc
, SCBPTR
, curscbptr
);
5616 found
+= ahc_search_untagged_queues(ahc
, /*aic_io_ctx_t*/NULL
, target
,
5617 channel
, lun
, status
, action
);
5619 if (action
== SEARCH_COMPLETE
)
5620 ahc_release_untagged_queues(ahc
);
5625 ahc_search_untagged_queues(struct ahc_softc
*ahc
, aic_io_ctx_t ctx
,
5626 int target
, char channel
, int lun
, uint32_t status
,
5627 ahc_search_action action
)
5634 if (action
== SEARCH_COMPLETE
) {
5636 * Don't attempt to run any queued untagged transactions
5637 * until we are done with the abort process.
5639 ahc_freeze_untagged_queues(ahc
);
5644 if ((ahc
->flags
& AHC_SCB_BTT
) == 0) {
5647 if (target
!= CAM_TARGET_WILDCARD
) {
5658 for (; i
< maxtarget
; i
++) {
5659 struct scb_tailq
*untagged_q
;
5660 struct scb
*next_scb
;
5662 untagged_q
= &(ahc
->untagged_queues
[i
]);
5663 next_scb
= TAILQ_FIRST(untagged_q
);
5664 while (next_scb
!= NULL
) {
5667 next_scb
= TAILQ_NEXT(scb
, links
.tqe
);
5670 * The head of the list may be the currently
5671 * active untagged command for a device.
5672 * We're only searching for commands that
5673 * have not been started. A transaction
5674 * marked active but still in the qinfifo
5675 * is removed by the qinfifo scanning code
5678 if ((scb
->flags
& SCB_ACTIVE
) != 0)
5681 if (ahc_match_scb(ahc
, scb
, target
, channel
, lun
,
5682 SCB_LIST_NULL
, ROLE_INITIATOR
) == 0
5683 || (ctx
!= NULL
&& ctx
!= scb
->io_ctx
))
5687 * We found an scb that needs to be acted on.
5691 case SEARCH_COMPLETE
:
5696 ostat
= aic_get_transaction_status(scb
);
5697 if (ostat
== CAM_REQ_INPROG
)
5698 aic_set_transaction_status(scb
, status
);
5699 cstat
= aic_get_transaction_status(scb
);
5700 if (cstat
!= CAM_REQ_CMP
)
5701 aic_freeze_scb(scb
);
5706 scb
->flags
&= ~SCB_UNTAGGEDQ
;
5707 TAILQ_REMOVE(untagged_q
, scb
, links
.tqe
);
5715 if (action
== SEARCH_COMPLETE
)
5716 ahc_release_untagged_queues(ahc
);
5721 ahc_search_disc_list(struct ahc_softc
*ahc
, int target
, char channel
,
5722 int lun
, u_int tag
, int stop_on_first
, int remove
,
5732 next
= ahc_inb(ahc
, DISCONNECTED_SCBH
);
5733 prev
= SCB_LIST_NULL
;
5736 /* restore this when we're done */
5737 active_scb
= ahc_inb(ahc
, SCBPTR
);
5739 /* Silence compiler */
5740 active_scb
= SCB_LIST_NULL
;
5742 while (next
!= SCB_LIST_NULL
) {
5745 ahc_outb(ahc
, SCBPTR
, next
);
5746 scb_index
= ahc_inb(ahc
, SCB_TAG
);
5747 if (scb_index
>= ahc
->scb_data
->numscbs
) {
5748 kprintf("Disconnected List inconsistency. "
5749 "SCB index == %d, yet numscbs == %d.",
5750 scb_index
, ahc
->scb_data
->numscbs
);
5751 ahc_dump_card_state(ahc
);
5752 panic("for safety");
5756 panic("Disconnected List Loop. "
5757 "cur SCBPTR == %x, prev SCBPTR == %x.",
5760 scbp
= ahc_lookup_scb(ahc
, scb_index
);
5761 if (ahc_match_scb(ahc
, scbp
, target
, channel
, lun
,
5762 tag
, ROLE_INITIATOR
)) {
5766 ahc_rem_scb_from_disc_list(ahc
, prev
, next
);
5769 next
= ahc_inb(ahc
, SCB_NEXT
);
5775 next
= ahc_inb(ahc
, SCB_NEXT
);
5779 ahc_outb(ahc
, SCBPTR
, active_scb
);
5784 * Remove an SCB from the on chip list of disconnected transactions.
5785 * This is empty/unused if we are not performing SCB paging.
5788 ahc_rem_scb_from_disc_list(struct ahc_softc
*ahc
, u_int prev
, u_int scbptr
)
5792 ahc_outb(ahc
, SCBPTR
, scbptr
);
5793 next
= ahc_inb(ahc
, SCB_NEXT
);
5795 ahc_outb(ahc
, SCB_CONTROL
, 0);
5797 ahc_add_curscb_to_free_list(ahc
);
5799 if (prev
!= SCB_LIST_NULL
) {
5800 ahc_outb(ahc
, SCBPTR
, prev
);
5801 ahc_outb(ahc
, SCB_NEXT
, next
);
5803 ahc_outb(ahc
, DISCONNECTED_SCBH
, next
);
5809 * Add the SCB as selected by SCBPTR onto the on chip list of
5810 * free hardware SCBs. This list is empty/unused if we are not
5811 * performing SCB paging.
5814 ahc_add_curscb_to_free_list(struct ahc_softc
*ahc
)
5817 * Invalidate the tag so that our abort
5818 * routines don't think it's active.
5820 ahc_outb(ahc
, SCB_TAG
, SCB_LIST_NULL
);
5822 if ((ahc
->flags
& AHC_PAGESCBS
) != 0) {
5823 ahc_outb(ahc
, SCB_NEXT
, ahc_inb(ahc
, FREE_SCBH
));
5824 ahc_outb(ahc
, FREE_SCBH
, ahc_inb(ahc
, SCBPTR
));
5829 * Manipulate the waiting for selection list and return the
5830 * scb that follows the one that we remove.
5833 ahc_rem_wscb(struct ahc_softc
*ahc
, u_int scbpos
, u_int prev
)
5838 * Select the SCB we want to abort and
5839 * pull the next pointer out of it.
5841 curscb
= ahc_inb(ahc
, SCBPTR
);
5842 ahc_outb(ahc
, SCBPTR
, scbpos
);
5843 next
= ahc_inb(ahc
, SCB_NEXT
);
5845 /* Clear the necessary fields */
5846 ahc_outb(ahc
, SCB_CONTROL
, 0);
5848 ahc_add_curscb_to_free_list(ahc
);
5850 /* update the waiting list */
5851 if (prev
== SCB_LIST_NULL
) {
5852 /* First in the list */
5853 ahc_outb(ahc
, WAITING_SCBH
, next
);
5856 * Ensure we aren't attempting to perform
5857 * selection for this entry.
5859 ahc_outb(ahc
, SCSISEQ
, (ahc_inb(ahc
, SCSISEQ
) & ~ENSELO
));
5862 * Select the scb that pointed to us
5863 * and update its next pointer.
5865 ahc_outb(ahc
, SCBPTR
, prev
);
5866 ahc_outb(ahc
, SCB_NEXT
, next
);
5870 * Point us back at the original scb position.
5872 ahc_outb(ahc
, SCBPTR
, curscb
);
5876 /******************************** Error Handling ******************************/
5878 * Abort all SCBs that match the given description (target/channel/lun/tag),
5879 * setting their status to the passed in status if the status has not already
5880 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5881 * is paused before it is called.
5884 ahc_abort_scbs(struct ahc_softc
*ahc
, int target
, char channel
,
5885 int lun
, u_int tag
, role_t role
, uint32_t status
)
5888 struct scb
*scbp_next
;
5898 * Don't attempt to run any queued untagged transactions
5899 * until we are done with the abort process.
5901 ahc_freeze_untagged_queues(ahc
);
5903 /* restore this when we're done */
5904 active_scb
= ahc_inb(ahc
, SCBPTR
);
5906 found
= ahc_search_qinfifo(ahc
, target
, channel
, lun
, SCB_LIST_NULL
,
5907 role
, CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
5910 * Clean out the busy target table for any untagged commands.
5914 if (target
!= CAM_TARGET_WILDCARD
) {
5921 if (lun
== CAM_LUN_WILDCARD
) {
5924 * Unless we are using an SCB based
5925 * busy targets table, there is only
5926 * one table entry for all luns of
5931 if ((ahc
->flags
& AHC_SCB_BTT
) != 0)
5932 maxlun
= AHC_NUM_LUNS
;
5938 if (role
!= ROLE_TARGET
) {
5939 for (;i
< maxtarget
; i
++) {
5940 for (j
= minlun
;j
< maxlun
; j
++) {
5944 tcl
= BUILD_TCL(i
<< 4, j
);
5945 scbid
= ahc_index_busy_tcl(ahc
, tcl
);
5946 scbp
= ahc_lookup_scb(ahc
, scbid
);
5948 || ahc_match_scb(ahc
, scbp
, target
, channel
,
5949 lun
, tag
, role
) == 0)
5951 ahc_unbusy_tcl(ahc
, BUILD_TCL(i
<< 4, j
));
5956 * Go through the disconnected list and remove any entries we
5957 * have queued for completion, 0'ing their control byte too.
5958 * We save the active SCB and restore it ourselves, so there
5959 * is no reason for this search to restore it too.
5961 ahc_search_disc_list(ahc
, target
, channel
, lun
, tag
,
5962 /*stop_on_first*/FALSE
, /*remove*/TRUE
,
5963 /*save_state*/FALSE
);
5967 * Go through the hardware SCB array looking for commands that
5968 * were active but not on any list. In some cases, these remnants
5969 * might not still have mappings in the scbindex array (e.g. unexpected
5970 * bus free with the same scb queued for an abort). Don't hold this
5973 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
5976 ahc_outb(ahc
, SCBPTR
, i
);
5977 scbid
= ahc_inb(ahc
, SCB_TAG
);
5978 scbp
= ahc_lookup_scb(ahc
, scbid
);
5979 if ((scbp
== NULL
&& scbid
!= SCB_LIST_NULL
)
5981 && ahc_match_scb(ahc
, scbp
, target
, channel
, lun
, tag
, role
)))
5982 ahc_add_curscb_to_free_list(ahc
);
5986 * Go through the pending CCB list and look for
5987 * commands for this target that are still active.
5988 * These are other tagged commands that were
5989 * disconnected when the reset occurred.
5991 scbp_next
= LIST_FIRST(&ahc
->pending_scbs
);
5992 while (scbp_next
!= NULL
) {
5994 scbp_next
= LIST_NEXT(scbp
, pending_links
);
5995 if (ahc_match_scb(ahc
, scbp
, target
, channel
, lun
, tag
, role
)) {
5998 ostat
= aic_get_transaction_status(scbp
);
5999 if (ostat
== CAM_REQ_INPROG
)
6000 aic_set_transaction_status(scbp
, status
);
6001 if (aic_get_transaction_status(scbp
) != CAM_REQ_CMP
)
6002 aic_freeze_scb(scbp
);
6003 if ((scbp
->flags
& SCB_ACTIVE
) == 0)
6004 kprintf("Inactive SCB on pending list\n");
6005 ahc_done(ahc
, scbp
);
6009 ahc_outb(ahc
, SCBPTR
, active_scb
);
6010 ahc_platform_abort_scbs(ahc
, target
, channel
, lun
, tag
, role
, status
);
6011 ahc_release_untagged_queues(ahc
);
6016 ahc_reset_current_bus(struct ahc_softc
*ahc
)
6020 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) & ~ENSCSIRST
);
6021 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
6022 ahc_outb(ahc
, SCSISEQ
, scsiseq
| SCSIRSTO
);
6023 ahc_flush_device_writes(ahc
);
6024 aic_delay(AHC_BUSRESET_DELAY
);
6025 /* Turn off the bus reset */
6026 ahc_outb(ahc
, SCSISEQ
, scsiseq
& ~SCSIRSTO
);
6028 ahc_clear_intstat(ahc
);
6030 /* Re-enable reset interrupts */
6031 ahc_outb(ahc
, SIMODE1
, ahc_inb(ahc
, SIMODE1
) | ENSCSIRST
);
6035 ahc_reset_channel(struct ahc_softc
*ahc
, char channel
, int initiate_reset
)
6037 struct ahc_devinfo devinfo
;
6038 u_int initiator
, target
, max_scsiid
;
6046 ahc
->pending_device
= NULL
;
6048 ahc_compile_devinfo(&devinfo
,
6049 CAM_TARGET_WILDCARD
,
6050 CAM_TARGET_WILDCARD
,
6052 channel
, ROLE_UNKNOWN
);
6055 /* Make sure the sequencer is in a safe location. */
6056 ahc_clear_critical_section(ahc
);
6059 * Run our command complete fifos to ensure that we perform
6060 * completion processing on any commands that 'completed'
6061 * before the reset occurred.
6063 ahc_run_qoutfifo(ahc
);
6064 #ifdef AHC_TARGET_MODE
6066 * XXX - In Twin mode, the tqinfifo may have commands
6067 * for an unaffected channel in it. However, if
6068 * we have run out of ATIO resources to drain that
6069 * queue, we may not get them all out here. Further,
6070 * the blocked transactions for the reset channel
6071 * should just be killed off, irrespecitve of whether
6072 * we are blocked on ATIO resources. Write a routine
6073 * to compact the tqinfifo appropriately.
6075 if ((ahc
->flags
& AHC_TARGETROLE
) != 0) {
6076 ahc_run_tqinfifo(ahc
, /*paused*/TRUE
);
6081 * Reset the bus if we are initiating this reset
6083 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
6085 if ((ahc
->features
& AHC_TWIN
) != 0
6086 && ((sblkctl
& SELBUSB
) != 0))
6088 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
6089 if (cur_channel
!= channel
) {
6090 /* Case 1: Command for another bus is active
6091 * Stealthily reset the other bus without
6092 * upsetting the current bus.
6094 ahc_outb(ahc
, SBLKCTL
, sblkctl
^ SELBUSB
);
6095 simode1
= ahc_inb(ahc
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
);
6096 #ifdef AHC_TARGET_MODE
6098 * Bus resets clear ENSELI, so we cannot
6099 * defer re-enabling bus reset interrupts
6100 * if we are in target mode.
6102 if ((ahc
->flags
& AHC_TARGETROLE
) != 0)
6103 simode1
|= ENSCSIRST
;
6105 ahc_outb(ahc
, SIMODE1
, simode1
);
6107 ahc_reset_current_bus(ahc
);
6108 ahc_clear_intstat(ahc
);
6109 ahc_outb(ahc
, SCSISEQ
, scsiseq
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
6110 ahc_outb(ahc
, SBLKCTL
, sblkctl
);
6111 restart_needed
= FALSE
;
6113 /* Case 2: A command from this bus is active or we're idle */
6114 simode1
= ahc_inb(ahc
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
);
6115 #ifdef AHC_TARGET_MODE
6117 * Bus resets clear ENSELI, so we cannot
6118 * defer re-enabling bus reset interrupts
6119 * if we are in target mode.
6121 if ((ahc
->flags
& AHC_TARGETROLE
) != 0)
6122 simode1
|= ENSCSIRST
;
6124 ahc_outb(ahc
, SIMODE1
, simode1
);
6126 ahc_reset_current_bus(ahc
);
6127 ahc_clear_intstat(ahc
);
6128 ahc_outb(ahc
, SCSISEQ
, scsiseq
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
6129 restart_needed
= TRUE
;
6133 * Clean up all the state information for the
6134 * pending transactions on this bus.
6136 found
= ahc_abort_scbs(ahc
, CAM_TARGET_WILDCARD
, channel
,
6137 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
6138 ROLE_UNKNOWN
, CAM_SCSI_BUS_RESET
);
6140 max_scsiid
= (ahc
->features
& AHC_WIDE
) ? 15 : 7;
6142 #ifdef AHC_TARGET_MODE
6144 * Send an immediate notify ccb to all target more peripheral
6145 * drivers affected by this action.
6147 for (target
= 0; target
<= max_scsiid
; target
++) {
6148 struct ahc_tmode_tstate
* tstate
;
6151 tstate
= ahc
->enabled_targets
[target
];
6154 for (lun
= 0; lun
< AHC_NUM_LUNS
; lun
++) {
6155 struct ahc_tmode_lstate
* lstate
;
6157 lstate
= tstate
->enabled_luns
[lun
];
6161 ahc_queue_lstate_event(ahc
, lstate
, CAM_TARGET_WILDCARD
,
6162 EVENT_TYPE_BUS_RESET
, /*arg*/0);
6163 ahc_send_lstate_events(ahc
, lstate
);
6167 /* Notify the XPT that a bus reset occurred */
6168 ahc_send_async(ahc
, devinfo
.channel
, CAM_TARGET_WILDCARD
,
6169 CAM_LUN_WILDCARD
, AC_BUS_RESET
, NULL
);
6172 * Revert to async/narrow transfers until we renegotiate.
6174 for (target
= 0; target
<= max_scsiid
; target
++) {
6176 if (ahc
->enabled_targets
[target
] == NULL
)
6178 for (initiator
= 0; initiator
<= max_scsiid
; initiator
++) {
6179 struct ahc_devinfo devinfo
;
6181 ahc_compile_devinfo(&devinfo
, target
, initiator
,
6183 channel
, ROLE_UNKNOWN
);
6184 ahc_set_width(ahc
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6185 AHC_TRANS_CUR
, /*paused*/TRUE
);
6186 ahc_set_syncrate(ahc
, &devinfo
, /*syncrate*/NULL
,
6187 /*period*/0, /*offset*/0,
6188 /*ppr_options*/0, AHC_TRANS_CUR
,
6201 /***************************** Residual Processing ****************************/
6203 * Calculate the residual for a just completed SCB.
6206 ahc_calc_residual(struct ahc_softc
*ahc
, struct scb
*scb
)
6208 struct hardware_scb
*hscb
;
6209 struct status_pkt
*spkt
;
6211 uint32_t resid_sgptr
;
6217 * SG_RESID_VALID clear in sgptr.
6218 * 2) Transferless command
6219 * 3) Never performed any transfers.
6220 * sgptr has SG_FULL_RESID set.
6221 * 4) No residual but target did not
6222 * save data pointers after the
6223 * last transfer, so sgptr was
6225 * 5) We have a partial residual.
6226 * Use residual_sgptr to determine
6231 sgptr
= aic_le32toh(hscb
->sgptr
);
6232 if ((sgptr
& SG_RESID_VALID
) == 0)
6235 sgptr
&= ~SG_RESID_VALID
;
6237 if ((sgptr
& SG_LIST_NULL
) != 0)
6241 spkt
= &hscb
->shared_data
.status
;
6242 resid_sgptr
= aic_le32toh(spkt
->residual_sg_ptr
);
6243 if ((sgptr
& SG_FULL_RESID
) != 0) {
6245 resid
= aic_get_transfer_length(scb
);
6246 } else if ((resid_sgptr
& SG_LIST_NULL
) != 0) {
6249 } else if ((resid_sgptr
& ~SG_PTR_MASK
) != 0) {
6250 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr
);
6254 struct ahc_dma_seg
*sg
;
6257 * Remainder of the SG where the transfer
6260 resid
= aic_le32toh(spkt
->residual_datacnt
) & AHC_SG_LEN_MASK
;
6261 sg
= ahc_sg_bus_to_virt(scb
, resid_sgptr
& SG_PTR_MASK
);
6263 /* The residual sg_ptr always points to the next sg */
6267 * Add up the contents of all residual
6268 * SG segments that are after the SG where
6269 * the transfer stopped.
6271 while ((aic_le32toh(sg
->len
) & AHC_DMA_LAST_SEG
) == 0) {
6273 resid
+= aic_le32toh(sg
->len
) & AHC_SG_LEN_MASK
;
6276 if ((scb
->flags
& SCB_SENSE
) == 0)
6277 aic_set_residual(scb
, resid
);
6279 aic_set_sense_residual(scb
, resid
);
6282 if ((ahc_debug
& AHC_SHOW_MISC
) != 0) {
6283 ahc_print_path(ahc
, scb
);
6284 kprintf("Handled %sResidual of %d bytes\n",
6285 (scb
->flags
& SCB_SENSE
) ? "Sense " : "", resid
);
6290 /******************************* Target Mode **********************************/
6291 #ifdef AHC_TARGET_MODE
6293 * Add a target mode event to this lun's queue
6296 ahc_queue_lstate_event(struct ahc_softc
*ahc
, struct ahc_tmode_lstate
*lstate
,
6297 u_int initiator_id
, u_int event_type
, u_int event_arg
)
6299 struct ahc_tmode_event
*event
;
6302 xpt_freeze_devq(lstate
->path
, /*count*/1);
6303 if (lstate
->event_w_idx
>= lstate
->event_r_idx
)
6304 pending
= lstate
->event_w_idx
- lstate
->event_r_idx
;
6306 pending
= AHC_TMODE_EVENT_BUFFER_SIZE
+ 1
6307 - (lstate
->event_r_idx
- lstate
->event_w_idx
);
6309 if (event_type
== EVENT_TYPE_BUS_RESET
6310 || event_type
== MSG_BUS_DEV_RESET
) {
6312 * Any earlier events are irrelevant, so reset our buffer.
6313 * This has the effect of allowing us to deal with reset
6314 * floods (an external device holding down the reset line)
6315 * without losing the event that is really interesting.
6317 lstate
->event_r_idx
= 0;
6318 lstate
->event_w_idx
= 0;
6319 xpt_release_devq(lstate
->path
, pending
, /*runqueue*/FALSE
);
6322 if (pending
== AHC_TMODE_EVENT_BUFFER_SIZE
) {
6323 xpt_print_path(lstate
->path
);
6324 kprintf("immediate event %x:%x lost\n",
6325 lstate
->event_buffer
[lstate
->event_r_idx
].event_type
,
6326 lstate
->event_buffer
[lstate
->event_r_idx
].event_arg
);
6327 lstate
->event_r_idx
++;
6328 if (lstate
->event_r_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6329 lstate
->event_r_idx
= 0;
6330 xpt_release_devq(lstate
->path
, /*count*/1, /*runqueue*/FALSE
);
6333 event
= &lstate
->event_buffer
[lstate
->event_w_idx
];
6334 event
->initiator_id
= initiator_id
;
6335 event
->event_type
= event_type
;
6336 event
->event_arg
= event_arg
;
6337 lstate
->event_w_idx
++;
6338 if (lstate
->event_w_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6339 lstate
->event_w_idx
= 0;
6343 * Send any target mode events queued up waiting
6344 * for immediate notify resources.
6347 ahc_send_lstate_events(struct ahc_softc
*ahc
, struct ahc_tmode_lstate
*lstate
)
6349 struct ccb_hdr
*ccbh
;
6350 struct ccb_immed_notify
*inot
;
6352 while (lstate
->event_r_idx
!= lstate
->event_w_idx
6353 && (ccbh
= SLIST_FIRST(&lstate
->immed_notifies
)) != NULL
) {
6354 struct ahc_tmode_event
*event
;
6356 event
= &lstate
->event_buffer
[lstate
->event_r_idx
];
6357 SLIST_REMOVE_HEAD(&lstate
->immed_notifies
, sim_links
.sle
);
6358 inot
= (struct ccb_immed_notify
*)ccbh
;
6359 switch (event
->event_type
) {
6360 case EVENT_TYPE_BUS_RESET
:
6361 ccbh
->status
= CAM_SCSI_BUS_RESET
|CAM_DEV_QFRZN
;
6364 ccbh
->status
= CAM_MESSAGE_RECV
|CAM_DEV_QFRZN
;
6365 inot
->message_args
[0] = event
->event_type
;
6366 inot
->message_args
[1] = event
->event_arg
;
6369 inot
->initiator_id
= event
->initiator_id
;
6370 inot
->sense_len
= 0;
6371 xpt_done((union ccb
*)inot
);
6372 lstate
->event_r_idx
++;
6373 if (lstate
->event_r_idx
== AHC_TMODE_EVENT_BUFFER_SIZE
)
6374 lstate
->event_r_idx
= 0;
6379 /******************** Sequencer Program Patching/Download *********************/
6383 ahc_dumpseq(struct ahc_softc
* ahc
)
6387 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
6388 ahc_outb(ahc
, SEQADDR0
, 0);
6389 ahc_outb(ahc
, SEQADDR1
, 0);
6390 for (i
= 0; i
< ahc
->instruction_ram_size
; i
++) {
6391 uint8_t ins_bytes
[4];
6393 ahc_insb(ahc
, SEQRAM
, ins_bytes
, 4);
6394 kprintf("0x%08x\n", ins_bytes
[0] << 24
6395 | ins_bytes
[1] << 16
6403 ahc_loadseq(struct ahc_softc
*ahc
)
6405 struct cs cs_table
[num_critical_sections
];
6406 u_int begin_set
[num_critical_sections
];
6407 u_int end_set
[num_critical_sections
];
6408 struct patch
*cur_patch
;
6413 u_int sg_prefetch_cnt
;
6415 uint8_t download_consts
[7];
6418 * Start out with 0 critical sections
6419 * that apply to this firmware load.
6423 memset(begin_set
, 0, sizeof(begin_set
));
6424 memset(end_set
, 0, sizeof(end_set
));
6426 /* Setup downloadable constant table */
6427 download_consts
[QOUTFIFO_OFFSET
] = 0;
6428 if (ahc
->targetcmds
!= NULL
)
6429 download_consts
[QOUTFIFO_OFFSET
] += 32;
6430 download_consts
[QINFIFO_OFFSET
] = download_consts
[QOUTFIFO_OFFSET
] + 1;
6431 download_consts
[CACHESIZE_MASK
] = ahc
->pci_cachesize
- 1;
6432 download_consts
[INVERTED_CACHESIZE_MASK
] = ~(ahc
->pci_cachesize
- 1);
6433 sg_prefetch_cnt
= ahc
->pci_cachesize
;
6434 if (sg_prefetch_cnt
< (2 * sizeof(struct ahc_dma_seg
)))
6435 sg_prefetch_cnt
= 2 * sizeof(struct ahc_dma_seg
);
6436 download_consts
[SG_PREFETCH_CNT
] = sg_prefetch_cnt
;
6437 download_consts
[SG_PREFETCH_ALIGN_MASK
] = ~(sg_prefetch_cnt
- 1);
6438 download_consts
[SG_PREFETCH_ADDR_MASK
] = (sg_prefetch_cnt
- 1);
6440 cur_patch
= patches
;
6443 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
6444 ahc_outb(ahc
, SEQADDR0
, 0);
6445 ahc_outb(ahc
, SEQADDR1
, 0);
6447 for (i
= 0; i
< sizeof(seqprog
)/4; i
++) {
6448 if (ahc_check_patch(ahc
, &cur_patch
, i
, &skip_addr
) == 0) {
6450 * Don't download this instruction as it
6451 * is in a patch that was removed.
6456 if (downloaded
== ahc
->instruction_ram_size
) {
6458 * We're about to exceed the instruction
6459 * storage capacity for this chip. Fail
6462 kprintf("\n%s: Program too large for instruction memory "
6463 "size of %d!\n", ahc_name(ahc
),
6464 ahc
->instruction_ram_size
);
6469 * Move through the CS table until we find a CS
6470 * that might apply to this instruction.
6472 for (; cur_cs
< num_critical_sections
; cur_cs
++) {
6473 if (critical_sections
[cur_cs
].end
<= i
) {
6474 if (begin_set
[cs_count
] == TRUE
6475 && end_set
[cs_count
] == FALSE
) {
6476 cs_table
[cs_count
].end
= downloaded
;
6477 end_set
[cs_count
] = TRUE
;
6482 if (critical_sections
[cur_cs
].begin
<= i
6483 && begin_set
[cs_count
] == FALSE
) {
6484 cs_table
[cs_count
].begin
= downloaded
;
6485 begin_set
[cs_count
] = TRUE
;
6489 ahc_download_instr(ahc
, i
, download_consts
);
6493 ahc
->num_critical_sections
= cs_count
;
6494 if (cs_count
!= 0) {
6495 cs_count
*= sizeof(struct cs
);
6496 ahc
->critical_sections
= kmalloc(cs_count
, M_DEVBUF
, M_INTWAIT
);
6497 memcpy(ahc
->critical_sections
, cs_table
, cs_count
);
6499 ahc_outb(ahc
, SEQCTL
, PERRORDIS
|FAILDIS
|FASTMODE
);
6502 kprintf(" %d instructions downloaded\n", downloaded
);
6503 kprintf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6504 ahc_name(ahc
), ahc
->features
, ahc
->bugs
, ahc
->flags
);
6510 ahc_check_patch(struct ahc_softc
*ahc
, struct patch
**start_patch
,
6511 u_int start_instr
, u_int
*skip_addr
)
6513 struct patch
*cur_patch
;
6514 struct patch
*last_patch
;
6517 num_patches
= sizeof(patches
)/sizeof(struct patch
);
6518 last_patch
= &patches
[num_patches
];
6519 cur_patch
= *start_patch
;
6521 while (cur_patch
< last_patch
&& start_instr
== cur_patch
->begin
) {
6523 if (cur_patch
->patch_func(ahc
) == 0) {
6525 /* Start rejecting code */
6526 *skip_addr
= start_instr
+ cur_patch
->skip_instr
;
6527 cur_patch
+= cur_patch
->skip_patch
;
6529 /* Accepted this patch. Advance to the next
6530 * one and wait for our intruction pointer to
6537 *start_patch
= cur_patch
;
6538 if (start_instr
< *skip_addr
)
6539 /* Still skipping */
6546 ahc_download_instr(struct ahc_softc
*ahc
, u_int instrptr
, uint8_t *dconsts
)
6548 union ins_formats instr
;
6549 struct ins_format1
*fmt1_ins
;
6550 struct ins_format3
*fmt3_ins
;
6554 * The firmware is always compiled into a little endian format.
6556 instr
.integer
= aic_le32toh(*(uint32_t*)&seqprog
[instrptr
* 4]);
6558 fmt1_ins
= &instr
.format1
;
6561 /* Pull the opcode */
6562 opcode
= instr
.format1
.opcode
;
6573 struct patch
*cur_patch
;
6579 fmt3_ins
= &instr
.format3
;
6581 address
= fmt3_ins
->address
;
6582 cur_patch
= patches
;
6585 for (i
= 0; i
< address
;) {
6587 ahc_check_patch(ahc
, &cur_patch
, i
, &skip_addr
);
6589 if (skip_addr
> i
) {
6592 end_addr
= MIN(address
, skip_addr
);
6593 address_offset
+= end_addr
- i
;
6599 address
-= address_offset
;
6600 fmt3_ins
->address
= address
;
6609 if (fmt1_ins
->parity
!= 0) {
6610 fmt1_ins
->immediate
= dconsts
[fmt1_ins
->immediate
];
6612 fmt1_ins
->parity
= 0;
6613 if ((ahc
->features
& AHC_CMD_CHAN
) == 0
6614 && opcode
== AIC_OP_BMOV
) {
6616 * Block move was added at the same time
6617 * as the command channel. Verify that
6618 * this is only a move of a single element
6619 * and convert the BMOV to a MOV
6620 * (AND with an immediate of FF).
6622 if (fmt1_ins
->immediate
!= 1)
6623 panic("%s: BMOV not supported\n",
6625 fmt1_ins
->opcode
= AIC_OP_AND
;
6626 fmt1_ins
->immediate
= 0xff;
6630 if ((ahc
->features
& AHC_ULTRA2
) != 0) {
6633 /* Calculate odd parity for the instruction */
6634 for (i
= 0, count
= 0; i
< 31; i
++) {
6638 if ((instr
.integer
& mask
) != 0)
6641 if ((count
& 0x01) == 0)
6642 instr
.format1
.parity
= 1;
6644 /* Compress the instruction for older sequencers */
6645 if (fmt3_ins
!= NULL
) {
6648 | (fmt3_ins
->source
<< 8)
6649 | (fmt3_ins
->address
<< 16)
6650 | (fmt3_ins
->opcode
<< 25);
6654 | (fmt1_ins
->source
<< 8)
6655 | (fmt1_ins
->destination
<< 16)
6656 | (fmt1_ins
->ret
<< 24)
6657 | (fmt1_ins
->opcode
<< 25);
6660 /* The sequencer is a little endian cpu */
6661 instr
.integer
= aic_htole32(instr
.integer
);
6662 ahc_outsb(ahc
, SEQRAM
, instr
.bytes
, 4);
6665 panic("Unknown opcode encountered in seq program");
6671 ahc_print_register(ahc_reg_parse_entry_t
*table
, u_int num_entries
,
6672 const char *name
, u_int address
, u_int value
,
6673 u_int
*cur_column
, u_int wrap_point
)
6679 if (cur_column
== NULL
) {
6681 cur_column
= &dummy_column
;
6684 if (*cur_column
>= wrap_point
) {
6688 printed
= kprintf("%s[0x%x]", name
, value
);
6689 if (table
== NULL
) {
6690 printed
+= kprintf(" ");
6691 *cur_column
+= printed
;
6695 while (printed_mask
!= 0xFF) {
6698 for (entry
= 0; entry
< num_entries
; entry
++) {
6699 if (((value
& table
[entry
].mask
)
6700 != table
[entry
].value
)
6701 || ((printed_mask
& table
[entry
].mask
)
6702 == table
[entry
].mask
))
6705 printed
+= kprintf("%s%s",
6706 printed_mask
== 0 ? ":(" : "|",
6708 printed_mask
|= table
[entry
].mask
;
6712 if (entry
>= num_entries
)
6715 if (printed_mask
!= 0)
6716 printed
+= kprintf(") ");
6718 printed
+= kprintf(" ");
6719 if (cur_column
!= NULL
)
6720 *cur_column
+= printed
;
6725 ahc_dump_card_state(struct ahc_softc
*ahc
)
6728 struct scb_tailq
*untagged_q
;
6739 uint8_t saved_scbptr
;
6741 if (ahc_is_paused(ahc
)) {
6748 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
6749 last_phase
= ahc_inb(ahc
, LASTPHASE
);
6750 kprintf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6751 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6752 ahc_name(ahc
), ahc_lookup_phase_entry(last_phase
)->phasemsg
,
6753 ahc_inb(ahc
, SEQADDR0
) | (ahc_inb(ahc
, SEQADDR1
) << 8));
6755 kprintf("Card was paused\n");
6756 kprintf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6757 ahc_inb(ahc
, ACCUM
), ahc_inb(ahc
, SINDEX
), ahc_inb(ahc
, DINDEX
),
6758 ahc_inb(ahc
, ARG_2
));
6759 kprintf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc
, HCNT
),
6760 ahc_inb(ahc
, SCBPTR
));
6762 if ((ahc
->features
& AHC_DT
) != 0)
6763 ahc_scsiphase_print(ahc_inb(ahc
, SCSIPHASE
), &cur_col
, 50);
6764 ahc_scsisigi_print(ahc_inb(ahc
, SCSISIGI
), &cur_col
, 50);
6765 ahc_error_print(ahc_inb(ahc
, ERROR
), &cur_col
, 50);
6766 ahc_scsibusl_print(ahc_inb(ahc
, SCSIBUSL
), &cur_col
, 50);
6767 ahc_lastphase_print(ahc_inb(ahc
, LASTPHASE
), &cur_col
, 50);
6768 ahc_scsiseq_print(ahc_inb(ahc
, SCSISEQ
), &cur_col
, 50);
6769 ahc_sblkctl_print(ahc_inb(ahc
, SBLKCTL
), &cur_col
, 50);
6770 ahc_scsirate_print(ahc_inb(ahc
, SCSIRATE
), &cur_col
, 50);
6771 ahc_seqctl_print(ahc_inb(ahc
, SEQCTL
), &cur_col
, 50);
6772 ahc_seq_flags_print(ahc_inb(ahc
, SEQ_FLAGS
), &cur_col
, 50);
6773 ahc_sstat0_print(ahc_inb(ahc
, SSTAT0
), &cur_col
, 50);
6774 ahc_sstat1_print(ahc_inb(ahc
, SSTAT1
), &cur_col
, 50);
6775 ahc_sstat2_print(ahc_inb(ahc
, SSTAT2
), &cur_col
, 50);
6776 ahc_sstat3_print(ahc_inb(ahc
, SSTAT3
), &cur_col
, 50);
6777 ahc_simode0_print(ahc_inb(ahc
, SIMODE0
), &cur_col
, 50);
6778 ahc_simode1_print(ahc_inb(ahc
, SIMODE1
), &cur_col
, 50);
6779 ahc_sxfrctl0_print(ahc_inb(ahc
, SXFRCTL0
), &cur_col
, 50);
6780 ahc_dfcntrl_print(ahc_inb(ahc
, DFCNTRL
), &cur_col
, 50);
6781 ahc_dfstatus_print(ahc_inb(ahc
, DFSTATUS
), &cur_col
, 50);
6785 for (i
= 0; i
< STACK_SIZE
; i
++)
6786 kprintf(" 0x%x", ahc_inb(ahc
, STACK
)|(ahc_inb(ahc
, STACK
) << 8));
6787 kprintf("\nSCB count = %d\n", ahc
->scb_data
->numscbs
);
6788 kprintf("Kernel NEXTQSCB = %d\n", ahc
->next_queued_scb
->hscb
->tag
);
6789 kprintf("Card NEXTQSCB = %d\n", ahc_inb(ahc
, NEXT_QUEUED_SCB
));
6791 kprintf("QINFIFO entries: ");
6792 if ((ahc
->features
& AHC_QUEUE_REGS
) != 0) {
6793 qinpos
= ahc_inb(ahc
, SNSCB_QOFF
);
6794 ahc_outb(ahc
, SNSCB_QOFF
, qinpos
);
6796 qinpos
= ahc_inb(ahc
, QINPOS
);
6797 qintail
= ahc
->qinfifonext
;
6798 while (qinpos
!= qintail
) {
6799 kprintf("%d ", ahc
->qinfifo
[qinpos
]);
6804 kprintf("Waiting Queue entries: ");
6805 scb_index
= ahc_inb(ahc
, WAITING_SCBH
);
6807 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6808 ahc_outb(ahc
, SCBPTR
, scb_index
);
6809 kprintf("%d:%d ", scb_index
, ahc_inb(ahc
, SCB_TAG
));
6810 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6814 kprintf("Disconnected Queue entries: ");
6815 scb_index
= ahc_inb(ahc
, DISCONNECTED_SCBH
);
6817 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6818 ahc_outb(ahc
, SCBPTR
, scb_index
);
6819 kprintf("%d:%d ", scb_index
, ahc_inb(ahc
, SCB_TAG
));
6820 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6824 ahc_sync_qoutfifo(ahc
, BUS_DMASYNC_POSTREAD
);
6825 kprintf("QOUTFIFO entries: ");
6826 qoutpos
= ahc
->qoutfifonext
;
6828 while (ahc
->qoutfifo
[qoutpos
] != SCB_LIST_NULL
&& i
++ < 256) {
6829 kprintf("%d ", ahc
->qoutfifo
[qoutpos
]);
6834 kprintf("Sequencer Free SCB List: ");
6835 scb_index
= ahc_inb(ahc
, FREE_SCBH
);
6837 while (scb_index
!= SCB_LIST_NULL
&& i
++ < 256) {
6838 ahc_outb(ahc
, SCBPTR
, scb_index
);
6839 kprintf("%d ", scb_index
);
6840 scb_index
= ahc_inb(ahc
, SCB_NEXT
);
6844 kprintf("Sequencer SCB Info: ");
6845 for (i
= 0; i
< ahc
->scb_data
->maxhscbs
; i
++) {
6846 ahc_outb(ahc
, SCBPTR
, i
);
6847 cur_col
= kprintf("\n%3d ", i
);
6849 ahc_scb_control_print(ahc_inb(ahc
, SCB_CONTROL
), &cur_col
, 60);
6850 ahc_scb_scsiid_print(ahc_inb(ahc
, SCB_SCSIID
), &cur_col
, 60);
6851 ahc_scb_lun_print(ahc_inb(ahc
, SCB_LUN
), &cur_col
, 60);
6852 ahc_scb_tag_print(ahc_inb(ahc
, SCB_TAG
), &cur_col
, 60);
6856 kprintf("Pending list: ");
6858 LIST_FOREACH(scb
, &ahc
->pending_scbs
, pending_links
) {
6861 cur_col
= kprintf("\n%3d ", scb
->hscb
->tag
);
6862 ahc_scb_control_print(scb
->hscb
->control
, &cur_col
, 60);
6863 ahc_scb_scsiid_print(scb
->hscb
->scsiid
, &cur_col
, 60);
6864 ahc_scb_lun_print(scb
->hscb
->lun
, &cur_col
, 60);
6865 if ((ahc
->flags
& AHC_PAGESCBS
) == 0) {
6866 ahc_outb(ahc
, SCBPTR
, scb
->hscb
->tag
);
6868 ahc_scb_control_print(ahc_inb(ahc
, SCB_CONTROL
),
6870 ahc_scb_tag_print(ahc_inb(ahc
, SCB_TAG
), &cur_col
, 60);
6876 kprintf("Kernel Free SCB list: ");
6878 SLIST_FOREACH(scb
, &ahc
->scb_data
->free_scbs
, links
.sle
) {
6881 kprintf("%d ", scb
->hscb
->tag
);
6885 maxtarget
= (ahc
->features
& (AHC_WIDE
|AHC_TWIN
)) ? 15 : 7;
6886 for (target
= 0; target
<= maxtarget
; target
++) {
6887 untagged_q
= &ahc
->untagged_queues
[target
];
6888 if (TAILQ_FIRST(untagged_q
) == NULL
)
6890 kprintf("Untagged Q(%d): ", target
);
6892 TAILQ_FOREACH(scb
, untagged_q
, links
.tqe
) {
6895 kprintf("%d ", scb
->hscb
->tag
);
6900 ahc_platform_dump_card_state(ahc
);
6901 kprintf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6902 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
6907 /*************************** Timeout Handling *********************************/
6909 ahc_timeout(struct scb
*scb
)
6911 struct ahc_softc
*ahc
;
6913 ahc
= scb
->ahc_softc
;
6914 if ((scb
->flags
& SCB_ACTIVE
) != 0) {
6915 if ((scb
->flags
& SCB_TIMEDOUT
) == 0) {
6916 LIST_INSERT_HEAD(&ahc
->timedout_scbs
, scb
,
6918 scb
->flags
|= SCB_TIMEDOUT
;
6920 ahc_wakeup_recovery_thread(ahc
);
6925 * Re-schedule a timeout for the passed in SCB if we determine that some
6926 * other SCB is in the process of recovery or an SCB with a longer
6927 * timeout is still pending. Limit our search to just "other_scb"
6928 * if it is non-NULL.
6931 ahc_other_scb_timeout(struct ahc_softc
*ahc
, struct scb
*scb
,
6932 struct scb
*other_scb
)
6937 ahc_print_path(ahc
, scb
);
6938 kprintf("Other SCB Timeout%s",
6939 (scb
->flags
& SCB_OTHERTCL_TIMEOUT
) != 0
6940 ? " again\n" : "\n");
6942 newtimeout
= aic_get_timeout(scb
);
6943 scb
->flags
|= SCB_OTHERTCL_TIMEOUT
;
6945 if (other_scb
!= NULL
) {
6946 if ((other_scb
->flags
6947 & (SCB_OTHERTCL_TIMEOUT
|SCB_TIMEDOUT
)) == 0
6948 || (other_scb
->flags
& SCB_RECOVERY_SCB
) != 0) {
6950 newtimeout
= MAX(aic_get_timeout(other_scb
),
6954 LIST_FOREACH(other_scb
, &ahc
->pending_scbs
, pending_links
) {
6955 if ((other_scb
->flags
6956 & (SCB_OTHERTCL_TIMEOUT
|SCB_TIMEDOUT
)) == 0
6957 || (other_scb
->flags
& SCB_RECOVERY_SCB
) != 0) {
6960 MAX(aic_get_timeout(other_scb
),
6967 aic_scb_timer_reset(scb
, newtimeout
);
6969 ahc_print_path(ahc
, scb
);
6970 kprintf("No other SCB worth waiting for...\n");
6973 return (found
!= 0);
6977 * ahc_recover_commands determines if any of the commands that have currently
6978 * timedout are the root cause for this timeout. Innocent commands are given
6979 * a new timeout while we wait for the command executing on the bus to timeout.
6980 * This routine is invoked from a thread context so we are allowed to sleep.
6981 * Our lock is not held on entry.
6984 ahc_recover_commands(struct ahc_softc
*ahc
)
6994 * Pause the controller and manually flush any
6995 * commands that have just completed but that our
6996 * interrupt handler has yet to see.
6998 ahc_pause_and_flushwork(ahc
);
7000 if (LIST_EMPTY(&ahc
->timedout_scbs
) != 0) {
7002 * The timedout commands have already
7003 * completed. This typically means
7004 * that either the timeout value was on
7005 * the hairy edge of what the device
7006 * requires or - more likely - interrupts
7007 * are not happening.
7009 kprintf("%s: Timedout SCBs already complete. "
7010 "Interrupts may not be functioning.\n", ahc_name(ahc
));
7017 kprintf("%s: Recovery Initiated\n", ahc_name(ahc
));
7018 ahc_dump_card_state(ahc
);
7020 last_phase
= ahc_inb(ahc
, LASTPHASE
);
7021 while ((scb
= LIST_FIRST(&ahc
->timedout_scbs
)) != NULL
) {
7022 u_int active_scb_index
;
7029 target
= SCB_GET_TARGET(ahc
, scb
);
7030 channel
= SCB_GET_CHANNEL(ahc
, scb
);
7031 lun
= SCB_GET_LUN(scb
);
7033 ahc_print_path(ahc
, scb
);
7034 kprintf("SCB 0x%x - timed out\n", scb
->hscb
->tag
);
7035 if (scb
->sg_count
> 0) {
7036 for (i
= 0; i
< scb
->sg_count
; i
++) {
7037 kprintf("sg[%d] - Addr 0x%x : Length %d\n",
7039 scb
->sg_list
[i
].addr
,
7040 scb
->sg_list
[i
].len
& AHC_SG_LEN_MASK
);
7043 if (scb
->flags
& (SCB_DEVICE_RESET
|SCB_ABORT
)) {
7045 * Been down this road before.
7046 * Do a full bus reset.
7048 aic_set_transaction_status(scb
, CAM_CMD_TIMEOUT
);
7050 found
= ahc_reset_channel(ahc
, channel
,
7051 /*Initiate Reset*/TRUE
);
7052 kprintf("%s: Issued Channel %c Bus Reset. "
7053 "%d SCBs aborted\n", ahc_name(ahc
), channel
,
7059 * Remove the command from the timedout list in
7060 * preparation for requeing it.
7062 LIST_REMOVE(scb
, timedout_links
);
7063 scb
->flags
&= ~SCB_TIMEDOUT
;
7066 * If we are a target, transition to bus free and report
7069 * The target/initiator that is holding up the bus may not
7070 * be the same as the one that triggered this timeout
7071 * (different commands have different timeout lengths).
7072 * If the bus is idle and we are actiing as the initiator
7073 * for this request, queue a BDR message to the timed out
7074 * target. Otherwise, if the timed out transaction is
7076 * Initiator transaction:
7077 * Stuff the message buffer with a BDR message and assert
7078 * ATN in the hopes that the target will let go of the bus
7079 * and go to the mesgout phase. If this fails, we'll
7080 * get another timeout 2 seconds later which will attempt
7083 * Target transaction:
7084 * Transition to BUS FREE and report the error.
7085 * It's good to be the target!
7087 saved_scbptr
= ahc_inb(ahc
, SCBPTR
);
7088 active_scb_index
= ahc_inb(ahc
, SCB_TAG
);
7090 if ((ahc_inb(ahc
, SEQ_FLAGS
) & NOT_IDENTIFIED
) == 0
7091 && (active_scb_index
< ahc
->scb_data
->numscbs
)) {
7092 struct scb
*active_scb
;
7095 * If the active SCB is not us, assume that
7096 * the active SCB has a longer timeout than
7097 * the timedout SCB, and wait for the active
7100 active_scb
= ahc_lookup_scb(ahc
, active_scb_index
);
7101 if (active_scb
!= scb
) {
7102 if (ahc_other_scb_timeout(ahc
, scb
,
7109 if ((scb
->flags
& SCB_TARGET_SCB
) != 0) {
7112 * Send back any queued up transactions
7113 * and properly record the error condition.
7115 ahc_abort_scbs(ahc
, SCB_GET_TARGET(ahc
, scb
),
7116 SCB_GET_CHANNEL(ahc
, scb
),
7122 /* Will clear us from the bus */
7127 ahc_set_recoveryscb(ahc
, active_scb
);
7128 ahc_outb(ahc
, MSG_OUT
, HOST_MSG
);
7129 ahc_outb(ahc
, SCSISIGO
, last_phase
|ATNO
);
7130 ahc_print_path(ahc
, active_scb
);
7131 kprintf("BDR message in message buffer\n");
7132 active_scb
->flags
|= SCB_DEVICE_RESET
;
7133 aic_scb_timer_reset(scb
, 2 * 1000);
7134 } else if (last_phase
!= P_BUSFREE
7135 && (ahc_inb(ahc
, SSTAT1
) & REQINIT
) == 0) {
7137 * SCB is not identified, there
7138 * is no pending REQ, and the sequencer
7139 * has not seen a busfree. Looks like
7140 * a stuck connection waiting to
7141 * go busfree. Reset the bus.
7143 kprintf("%s: Connection stuck awaiting busfree or "
7144 "Identify Msg.\n", ahc_name(ahc
));
7149 if (last_phase
!= P_BUSFREE
7150 && (ahc_inb(ahc
, SSTAT0
) & TARGET
) != 0) {
7151 /* Hung target selection. Goto busfree */
7152 kprintf("%s: Hung target selection\n",
7158 /* XXX Shouldn't panic. Just punt instead? */
7159 if ((scb
->flags
& SCB_TARGET_SCB
) != 0)
7160 panic("Timed-out target SCB but bus idle");
7162 if (ahc_search_qinfifo(ahc
, target
, channel
, lun
,
7163 scb
->hscb
->tag
, ROLE_INITIATOR
,
7164 /*status*/0, SEARCH_COUNT
) > 0) {
7165 disconnected
= FALSE
;
7167 disconnected
= TRUE
;
7172 ahc_set_recoveryscb(ahc
, scb
);
7174 * Actually re-queue this SCB in an attempt
7175 * to select the device before it reconnects.
7176 * In either case (selection or reselection),
7177 * we will now issue a target reset to the
7180 * Set the MK_MESSAGE control bit indicating
7181 * that we desire to send a message. We
7182 * also set the disconnected flag since
7183 * in the paging case there is no guarantee
7184 * that our SCB control byte matches the
7185 * version on the card. We don't want the
7186 * sequencer to abort the command thinking
7187 * an unsolicited reselection occurred.
7189 scb
->hscb
->control
|= MK_MESSAGE
|DISCONNECTED
;
7190 scb
->flags
|= SCB_DEVICE_RESET
;
7193 * Remove any cached copy of this SCB in the
7194 * disconnected list in preparation for the
7195 * queuing of our abort SCB. We use the
7196 * same element in the SCB, SCB_NEXT, for
7197 * both the qinfifo and the disconnected list.
7199 ahc_search_disc_list(ahc
, target
, channel
,
7200 lun
, scb
->hscb
->tag
,
7201 /*stop_on_first*/TRUE
,
7203 /*save_state*/FALSE
);
7206 * In the non-paging case, the sequencer will
7207 * never re-reference the in-core SCB.
7208 * To make sure we are notified during
7209 * reslection, set the MK_MESSAGE flag in
7210 * the card's copy of the SCB.
7212 if ((ahc
->flags
& AHC_PAGESCBS
) == 0) {
7213 ahc_outb(ahc
, SCBPTR
, scb
->hscb
->tag
);
7214 ahc_outb(ahc
, SCB_CONTROL
,
7215 ahc_inb(ahc
, SCB_CONTROL
)
7220 * Clear out any entries in the QINFIFO first
7221 * so we are the next SCB for this target
7224 ahc_search_qinfifo(ahc
,
7225 SCB_GET_TARGET(ahc
, scb
),
7226 channel
, SCB_GET_LUN(scb
),
7231 ahc_print_path(ahc
, scb
);
7232 kprintf("Queuing a BDR SCB\n");
7233 ahc_qinfifo_requeue_tail(ahc
, scb
);
7234 ahc_outb(ahc
, SCBPTR
, saved_scbptr
);
7235 aic_scb_timer_reset(scb
, 2 * 1000);
7237 /* Go "immediatly" to the bus reset */
7238 /* This shouldn't happen */
7239 ahc_set_recoveryscb(ahc
, scb
);
7240 ahc_print_path(ahc
, scb
);
7241 kprintf("SCB %d: Immediate reset. "
7242 "Flags = 0x%x\n", scb
->hscb
->tag
,
7251 * Any remaining SCBs were not the "culprit", so remove
7252 * them from the timeout list. The timer for these commands
7253 * will be reset once the recovery SCB completes.
7255 while ((scb
= LIST_FIRST(&ahc
->timedout_scbs
)) != NULL
) {
7257 LIST_REMOVE(scb
, timedout_links
);
7258 scb
->flags
&= ~SCB_TIMEDOUT
;
7268 /************************* Target Mode ****************************************/
7269 #ifdef AHC_TARGET_MODE
7271 ahc_find_tmode_devs(struct ahc_softc
*ahc
, struct cam_sim
*sim
, union ccb
*ccb
,
7272 struct ahc_tmode_tstate
**tstate
,
7273 struct ahc_tmode_lstate
**lstate
,
7274 int notfound_failure
)
7277 if ((ahc
->features
& AHC_TARGETMODE
) == 0)
7278 return (CAM_REQ_INVALID
);
7281 * Handle the 'black hole' device that sucks up
7282 * requests to unattached luns on enabled targets.
7284 if (ccb
->ccb_h
.target_id
== CAM_TARGET_WILDCARD
7285 && ccb
->ccb_h
.target_lun
== CAM_LUN_WILDCARD
) {
7287 *lstate
= ahc
->black_hole
;
7291 max_id
= (ahc
->features
& AHC_WIDE
) ? 15 : 7;
7292 if (ccb
->ccb_h
.target_id
> max_id
)
7293 return (CAM_TID_INVALID
);
7295 if (ccb
->ccb_h
.target_lun
>= AHC_NUM_LUNS
)
7296 return (CAM_LUN_INVALID
);
7298 *tstate
= ahc
->enabled_targets
[ccb
->ccb_h
.target_id
];
7300 if (*tstate
!= NULL
)
7302 (*tstate
)->enabled_luns
[ccb
->ccb_h
.target_lun
];
7305 if (notfound_failure
!= 0 && *lstate
== NULL
)
7306 return (CAM_PATH_INVALID
);
7308 return (CAM_REQ_CMP
);
7312 ahc_handle_en_lun(struct ahc_softc
*ahc
, struct cam_sim
*sim
, union ccb
*ccb
)
7314 struct ahc_tmode_tstate
*tstate
;
7315 struct ahc_tmode_lstate
*lstate
;
7316 struct ccb_en_lun
*cel
;
7325 status
= ahc_find_tmode_devs(ahc
, sim
, ccb
, &tstate
, &lstate
,
7326 /*notfound_failure*/FALSE
);
7328 if (status
!= CAM_REQ_CMP
) {
7329 ccb
->ccb_h
.status
= status
;
7333 if (cam_sim_bus(sim
) == 0)
7334 our_id
= ahc
->our_id
;
7336 our_id
= ahc
->our_id_b
;
7338 if (ccb
->ccb_h
.target_id
!= our_id
) {
7340 * our_id represents our initiator ID, or
7341 * the ID of the first target to have an
7342 * enabled lun in target mode. There are
7343 * two cases that may preclude enabling a
7344 * target id other than our_id.
7346 * o our_id is for an active initiator role.
7347 * Since the hardware does not support
7348 * reselections to the initiator role at
7349 * anything other than our_id, and our_id
7350 * is used by the hardware to indicate the
7351 * ID to use for both select-out and
7352 * reselect-out operations, the only target
7353 * ID we can support in this mode is our_id.
7355 * o The MULTARGID feature is not available and
7356 * a previous target mode ID has been enabled.
7358 if ((ahc
->features
& AHC_MULTIROLE
) != 0) {
7360 if ((ahc
->features
& AHC_MULTI_TID
) != 0
7361 && (ahc
->flags
& AHC_INITIATORROLE
) != 0) {
7363 * Only allow additional targets if
7364 * the initiator role is disabled.
7365 * The hardware cannot handle a re-select-in
7366 * on the initiator id during a re-select-out
7367 * on a different target id.
7369 status
= CAM_TID_INVALID
;
7370 } else if ((ahc
->flags
& AHC_INITIATORROLE
) != 0
7371 || ahc
->enabled_luns
> 0) {
7373 * Only allow our target id to change
7374 * if the initiator role is not configured
7375 * and there are no enabled luns which
7376 * are attached to the currently registered
7379 status
= CAM_TID_INVALID
;
7381 } else if ((ahc
->features
& AHC_MULTI_TID
) == 0
7382 && ahc
->enabled_luns
> 0) {
7384 status
= CAM_TID_INVALID
;
7388 if (status
!= CAM_REQ_CMP
) {
7389 ccb
->ccb_h
.status
= status
;
7394 * We now have an id that is valid.
7395 * If we aren't in target mode, switch modes.
7397 if ((ahc
->flags
& AHC_TARGETROLE
) == 0
7398 && ccb
->ccb_h
.target_id
!= CAM_TARGET_WILDCARD
) {
7399 ahc_flag saved_flags
;
7401 kprintf("Configuring Target Mode\n");
7403 if (LIST_FIRST(&ahc
->pending_scbs
) != NULL
) {
7404 ccb
->ccb_h
.status
= CAM_BUSY
;
7408 saved_flags
= ahc
->flags
;
7409 ahc
->flags
|= AHC_TARGETROLE
;
7410 if ((ahc
->features
& AHC_MULTIROLE
) == 0)
7411 ahc
->flags
&= ~AHC_INITIATORROLE
;
7413 error
= ahc_loadseq(ahc
);
7416 * Restore original configuration and notify
7417 * the caller that we cannot support target mode.
7418 * Since the adapter started out in this
7419 * configuration, the firmware load will succeed,
7420 * so there is no point in checking ahc_loadseq's
7423 ahc
->flags
= saved_flags
;
7424 (void)ahc_loadseq(ahc
);
7427 ccb
->ccb_h
.status
= CAM_FUNC_NOTAVAIL
;
7434 target
= ccb
->ccb_h
.target_id
;
7435 lun
= ccb
->ccb_h
.target_lun
;
7436 channel
= SIM_CHANNEL(ahc
, sim
);
7437 target_mask
= 0x01 << target
;
7441 if (cel
->enable
!= 0) {
7444 /* Are we already enabled?? */
7445 if (lstate
!= NULL
) {
7446 xpt_print_path(ccb
->ccb_h
.path
);
7447 kprintf("Lun already enabled\n");
7448 ccb
->ccb_h
.status
= CAM_LUN_ALRDY_ENA
;
7452 if (cel
->grp6_len
!= 0
7453 || cel
->grp7_len
!= 0) {
7455 * Don't (yet?) support vendor
7456 * specific commands.
7458 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7459 kprintf("Non-zero Group Codes\n");
7465 * Setup our data structures.
7467 if (target
!= CAM_TARGET_WILDCARD
&& tstate
== NULL
) {
7468 tstate
= ahc_alloc_tstate(ahc
, target
, channel
);
7469 if (tstate
== NULL
) {
7470 xpt_print_path(ccb
->ccb_h
.path
);
7471 kprintf("Couldn't allocate tstate\n");
7472 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
7476 lstate
= kmalloc(sizeof(*lstate
), M_DEVBUF
, M_INTWAIT
| M_ZERO
);
7477 status
= xpt_create_path(&lstate
->path
, /*periph*/NULL
,
7478 xpt_path_path_id(ccb
->ccb_h
.path
),
7479 xpt_path_target_id(ccb
->ccb_h
.path
),
7480 xpt_path_lun_id(ccb
->ccb_h
.path
));
7481 if (status
!= CAM_REQ_CMP
) {
7482 kfree(lstate
, M_DEVBUF
);
7483 xpt_print_path(ccb
->ccb_h
.path
);
7484 kprintf("Couldn't allocate path\n");
7485 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
7488 SLIST_INIT(&lstate
->accept_tios
);
7489 SLIST_INIT(&lstate
->immed_notifies
);
7492 if (target
!= CAM_TARGET_WILDCARD
) {
7493 tstate
->enabled_luns
[lun
] = lstate
;
7494 ahc
->enabled_luns
++;
7496 if ((ahc
->features
& AHC_MULTI_TID
) != 0) {
7499 targid_mask
= ahc_inb(ahc
, TARGID
)
7500 | (ahc_inb(ahc
, TARGID
+ 1) << 8);
7502 targid_mask
|= target_mask
;
7503 ahc_outb(ahc
, TARGID
, targid_mask
);
7504 ahc_outb(ahc
, TARGID
+1, (targid_mask
>> 8));
7506 ahc_update_scsiid(ahc
, targid_mask
);
7511 channel
= SIM_CHANNEL(ahc
, sim
);
7512 our_id
= SIM_SCSI_ID(ahc
, sim
);
7515 * This can only happen if selections
7518 if (target
!= our_id
) {
7523 sblkctl
= ahc_inb(ahc
, SBLKCTL
);
7524 cur_channel
= (sblkctl
& SELBUSB
)
7526 if ((ahc
->features
& AHC_TWIN
) == 0)
7528 swap
= cur_channel
!= channel
;
7530 ahc
->our_id
= target
;
7532 ahc
->our_id_b
= target
;
7535 ahc_outb(ahc
, SBLKCTL
,
7538 ahc_outb(ahc
, SCSIID
, target
);
7541 ahc_outb(ahc
, SBLKCTL
, sblkctl
);
7545 ahc
->black_hole
= lstate
;
7546 /* Allow select-in operations */
7547 if (ahc
->black_hole
!= NULL
&& ahc
->enabled_luns
> 0) {
7548 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
7550 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq
);
7551 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
7553 ahc_outb(ahc
, SCSISEQ
, scsiseq
);
7557 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
7558 xpt_print_path(ccb
->ccb_h
.path
);
7559 kprintf("Lun now enabled for target mode\n");
7564 if (lstate
== NULL
) {
7565 ccb
->ccb_h
.status
= CAM_LUN_INVALID
;
7571 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
7572 LIST_FOREACH(scb
, &ahc
->pending_scbs
, pending_links
) {
7573 struct ccb_hdr
*ccbh
;
7575 ccbh
= &scb
->io_ctx
->ccb_h
;
7576 if (ccbh
->func_code
== XPT_CONT_TARGET_IO
7577 && !xpt_path_comp(ccbh
->path
, ccb
->ccb_h
.path
)){
7578 kprintf("CTIO pending\n");
7579 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7585 if (SLIST_FIRST(&lstate
->accept_tios
) != NULL
) {
7586 kprintf("ATIOs pending\n");
7587 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7590 if (SLIST_FIRST(&lstate
->immed_notifies
) != NULL
) {
7591 kprintf("INOTs pending\n");
7592 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
7595 if (ccb
->ccb_h
.status
!= CAM_REQ_CMP
) {
7600 xpt_print_path(ccb
->ccb_h
.path
);
7601 kprintf("Target mode disabled\n");
7602 xpt_free_path(lstate
->path
);
7603 kfree(lstate
, M_DEVBUF
);
7606 /* Can we clean up the target too? */
7607 if (target
!= CAM_TARGET_WILDCARD
) {
7608 tstate
->enabled_luns
[lun
] = NULL
;
7609 ahc
->enabled_luns
--;
7610 for (empty
= 1, i
= 0; i
< 8; i
++)
7611 if (tstate
->enabled_luns
[i
] != NULL
) {
7617 ahc_free_tstate(ahc
, target
, channel
,
7619 if (ahc
->features
& AHC_MULTI_TID
) {
7622 targid_mask
= ahc_inb(ahc
, TARGID
)
7623 | (ahc_inb(ahc
, TARGID
+ 1)
7626 targid_mask
&= ~target_mask
;
7627 ahc_outb(ahc
, TARGID
, targid_mask
);
7628 ahc_outb(ahc
, TARGID
+1,
7629 (targid_mask
>> 8));
7630 ahc_update_scsiid(ahc
, targid_mask
);
7635 ahc
->black_hole
= NULL
;
7638 * We can't allow selections without
7639 * our black hole device.
7643 if (ahc
->enabled_luns
== 0) {
7644 /* Disallow select-in */
7647 scsiseq
= ahc_inb(ahc
, SCSISEQ_TEMPLATE
);
7649 ahc_outb(ahc
, SCSISEQ_TEMPLATE
, scsiseq
);
7650 scsiseq
= ahc_inb(ahc
, SCSISEQ
);
7652 ahc_outb(ahc
, SCSISEQ
, scsiseq
);
7654 if ((ahc
->features
& AHC_MULTIROLE
) == 0) {
7655 kprintf("Configuring Initiator Mode\n");
7656 ahc
->flags
&= ~AHC_TARGETROLE
;
7657 ahc
->flags
|= AHC_INITIATORROLE
;
7659 * Returning to a configuration that
7660 * fit previously will always succeed.
7662 (void)ahc_loadseq(ahc
);
7665 * Unpaused. The extra unpause
7666 * that follows is harmless.
7676 ahc_update_scsiid(struct ahc_softc
*ahc
, u_int targid_mask
)
7681 if ((ahc
->features
& AHC_MULTI_TID
) == 0)
7682 panic("ahc_update_scsiid called on non-multitid unit\n");
7685 * Since we will rely on the TARGID mask
7686 * for selection enables, ensure that OID
7687 * in SCSIID is not set to some other ID
7688 * that we don't want to allow selections on.
7690 if ((ahc
->features
& AHC_ULTRA2
) != 0)
7691 scsiid
= ahc_inb(ahc
, SCSIID_ULTRA2
);
7693 scsiid
= ahc_inb(ahc
, SCSIID
);
7694 scsiid_mask
= 0x1 << (scsiid
& OID
);
7695 if ((targid_mask
& scsiid_mask
) == 0) {
7698 /* ffs counts from 1 */
7699 our_id
= ffs(targid_mask
);
7701 our_id
= ahc
->our_id
;
7707 if ((ahc
->features
& AHC_ULTRA2
) != 0)
7708 ahc_outb(ahc
, SCSIID_ULTRA2
, scsiid
);
7710 ahc_outb(ahc
, SCSIID
, scsiid
);
7714 ahc_run_tqinfifo(struct ahc_softc
*ahc
, int paused
)
7716 struct target_cmd
*cmd
;
7719 * If the card supports auto-access pause,
7720 * we can access the card directly regardless
7721 * of whether it is paused or not.
7723 if ((ahc
->features
& AHC_AUTOPAUSE
) != 0)
7726 ahc_sync_tqinfifo(ahc
, BUS_DMASYNC_POSTREAD
);
7727 while ((cmd
= &ahc
->targetcmds
[ahc
->tqinfifonext
])->cmd_valid
!= 0) {
7730 * Only advance through the queue if we
7731 * have the resources to process the command.
7733 if (ahc_handle_target_cmd(ahc
, cmd
) != 0)
7737 aic_dmamap_sync(ahc
, ahc
->shared_data_dmat
,
7738 ahc
->shared_data_dmamap
,
7739 ahc_targetcmd_offset(ahc
, ahc
->tqinfifonext
),
7740 sizeof(struct target_cmd
),
7741 BUS_DMASYNC_PREREAD
);
7742 ahc
->tqinfifonext
++;
7745 * Lazily update our position in the target mode incoming
7746 * command queue as seen by the sequencer.
7748 if ((ahc
->tqinfifonext
& (HOST_TQINPOS
- 1)) == 1) {
7749 if ((ahc
->features
& AHC_HS_MAILBOX
) != 0) {
7752 hs_mailbox
= ahc_inb(ahc
, HS_MAILBOX
);
7753 hs_mailbox
&= ~HOST_TQINPOS
;
7754 hs_mailbox
|= ahc
->tqinfifonext
& HOST_TQINPOS
;
7755 ahc_outb(ahc
, HS_MAILBOX
, hs_mailbox
);
7759 ahc_outb(ahc
, KERNEL_TQINPOS
,
7760 ahc
->tqinfifonext
& HOST_TQINPOS
);
7769 ahc_handle_target_cmd(struct ahc_softc
*ahc
, struct target_cmd
*cmd
)
7771 struct ahc_tmode_tstate
*tstate
;
7772 struct ahc_tmode_lstate
*lstate
;
7773 struct ccb_accept_tio
*atio
;
7779 initiator
= SCSIID_TARGET(ahc
, cmd
->scsiid
);
7780 target
= SCSIID_OUR_ID(cmd
->scsiid
);
7781 lun
= (cmd
->identify
& MSG_IDENTIFY_LUNMASK
);
7784 tstate
= ahc
->enabled_targets
[target
];
7787 lstate
= tstate
->enabled_luns
[lun
];
7790 * Commands for disabled luns go to the black hole driver.
7793 lstate
= ahc
->black_hole
;
7795 atio
= (struct ccb_accept_tio
*)SLIST_FIRST(&lstate
->accept_tios
);
7797 ahc
->flags
|= AHC_TQINFIFO_BLOCKED
;
7799 * Wait for more ATIOs from the peripheral driver for this lun.
7802 kprintf("%s: ATIOs exhausted\n", ahc_name(ahc
));
7805 ahc
->flags
&= ~AHC_TQINFIFO_BLOCKED
;
7807 if (ahc_debug
& AHC_SHOW_TQIN
) {
7808 kprintf("Incoming command from %d for %d:%d%s\n",
7809 initiator
, target
, lun
,
7810 lstate
== ahc
->black_hole
? "(Black Holed)" : "");
7813 SLIST_REMOVE_HEAD(&lstate
->accept_tios
, sim_links
.sle
);
7815 if (lstate
== ahc
->black_hole
) {
7816 /* Fill in the wildcards */
7817 atio
->ccb_h
.target_id
= target
;
7818 atio
->ccb_h
.target_lun
= lun
;
7822 * Package it up and send it off to
7823 * whomever has this lun enabled.
7825 atio
->sense_len
= 0;
7826 atio
->init_id
= initiator
;
7827 if (byte
[0] != 0xFF) {
7828 /* Tag was included */
7829 atio
->tag_action
= *byte
++;
7830 atio
->tag_id
= *byte
++;
7831 atio
->ccb_h
.flags
= CAM_TAG_ACTION_VALID
;
7833 atio
->ccb_h
.flags
= 0;
7837 /* Okay. Now determine the cdb size based on the command code */
7838 switch (*byte
>> CMD_GROUP_CODE_SHIFT
) {
7854 /* Only copy the opcode. */
7856 kprintf("Reserved or VU command code type encountered\n");
7860 memcpy(atio
->cdb_io
.cdb_bytes
, byte
, atio
->cdb_len
);
7862 atio
->ccb_h
.status
|= CAM_CDB_RECVD
;
7864 if ((cmd
->identify
& MSG_IDENTIFY_DISCFLAG
) == 0) {
7866 * We weren't allowed to disconnect.
7867 * We're hanging on the bus until a
7868 * continue target I/O comes in response
7869 * to this accept tio.
7872 if (ahc_debug
& AHC_SHOW_TQIN
) {
7873 kprintf("Received Immediate Command %d:%d:%d - %p\n",
7874 initiator
, target
, lun
, ahc
->pending_device
);
7877 ahc
->pending_device
= lstate
;
7878 aic_freeze_ccb((union ccb
*)atio
);
7879 atio
->ccb_h
.flags
|= CAM_DIS_DISCONNECT
;
7881 xpt_done((union ccb
*)atio
);