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Add a new csum flag to tell IP defragmenter that csum_data does _not_
[dragonfly/port-amd64.git] / sys / dev / netif / xl / if_xl.c
blobaf684154873a7563dbe7e5ca53773aa66987e155
1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.49 2007/08/14 13:30:35 sephe Exp $
34 */
35
36 /*
37 * 3Com 3c90x Etherlink XL PCI NIC driver
38 *
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
41 * the following:
42 *
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
72 *
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
76 */
77
78 /*
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
87 *
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
92 *
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
100 */
101
102 #include "opt_polling.h"
103
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/sockio.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/socket.h>
111 #include <sys/serialize.h>
112 #include <sys/bus.h>
113 #include <sys/rman.h>
114 #include <sys/thread2.h>
115
116 #include <net/if.h>
117 #include <net/ifq_var.h>
118 #include <net/if_arp.h>
119 #include <net/ethernet.h>
120 #include <net/if_dl.h>
121 #include <net/if_media.h>
122 #include <net/vlan/if_vlan_var.h>
123
124 #include <net/bpf.h>
125
126 #include "../mii_layer/mii.h"
127 #include "../mii_layer/miivar.h"
128
129 #include <bus/pci/pcireg.h>
130 #include <bus/pci/pcivar.h>
131
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
134
135 #include "if_xlreg.h"
136
137 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
138
139 /*
140 * Various supported device vendors/types and their names.
141 */
142 static struct xl_type xl_devs[] = {
143 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
144 "3Com 3c900-TPO Etherlink XL" },
145 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
146 "3Com 3c900-COMBO Etherlink XL" },
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
148 "3Com 3c905-TX Fast Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
150 "3Com 3c905-T4 Fast Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
152 "3Com 3c900B-TPO Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
154 "3Com 3c900B-COMBO Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
156 "3Com 3c900B-TPC Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
158 "3Com 3c900B-FL Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
160 "3Com 3c905B-TX Fast Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
162 "3Com 3c905B-T4 Fast Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
164 "3Com 3c905B-FX/SC Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
166 "3Com 3c905B-COMBO Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
168 "3Com 3c905C-TX Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
170 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
172 "3Com 3c980 Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
174 "3Com 3c980C Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
176 "3Com 3cSOHO100-TX OfficeConnect" },
177 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
178 "3Com 3c450-TX HomeConnect" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
180 "3Com 3c555 Fast Etherlink XL" },
181 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
182 "3Com 3c556 Fast Etherlink XL" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
184 "3Com 3c556B Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
186 "3Com 3c575TX Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
188 "3Com 3c575B Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
190 "3Com 3c575C Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
192 "3Com 3c656 Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
194 "3Com 3c656B Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
196 "3Com 3c656C Fast Etherlink XL" },
197 { 0, 0, NULL }
198 };
199
200 static int xl_probe (device_t);
201 static int xl_attach (device_t);
202 static int xl_detach (device_t);
203
204 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
205 static void xl_stats_update (void *);
206 static void xl_stats_update_serialized(void *);
207 static int xl_encap (struct xl_softc *, struct xl_chain *,
208 struct mbuf *);
209 static void xl_rxeof (struct xl_softc *, int);
210 static int xl_rx_resync (struct xl_softc *);
211 static void xl_txeof (struct xl_softc *);
212 static void xl_txeof_90xB (struct xl_softc *);
213 static void xl_txeoc (struct xl_softc *);
214 static void xl_intr (void *);
215 static void xl_start_body (struct ifnet *, int);
216 static void xl_start (struct ifnet *);
217 static void xl_start_90xB (struct ifnet *);
218 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
219 struct ucred *);
220 static void xl_init (void *);
221 static void xl_stop (struct xl_softc *);
222 static void xl_watchdog (struct ifnet *);
223 static void xl_shutdown (device_t);
224 static int xl_suspend (device_t);
225 static int xl_resume (device_t);
226 #ifdef DEVICE_POLLING
227 static void xl_poll (struct ifnet *, enum poll_cmd, int);
228 #endif
229 static void xl_enable_intrs (struct xl_softc *, uint16_t);
230
231 static int xl_ifmedia_upd (struct ifnet *);
232 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
233
234 static int xl_eeprom_wait (struct xl_softc *);
235 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
236 static void xl_mii_sync (struct xl_softc *);
237 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
238 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
239 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
240
241 static void xl_setcfg (struct xl_softc *);
242 static void xl_setmode (struct xl_softc *, int);
243 static void xl_setmulti (struct xl_softc *);
244 static void xl_setmulti_hash (struct xl_softc *);
245 static void xl_reset (struct xl_softc *);
246 static int xl_list_rx_init (struct xl_softc *);
247 static void xl_list_tx_init (struct xl_softc *);
248 static void xl_list_tx_init_90xB(struct xl_softc *);
249 static void xl_wait (struct xl_softc *);
250 static void xl_mediacheck (struct xl_softc *);
251 static void xl_choose_xcvr (struct xl_softc *, int);
252 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
253 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
254 int);
255 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
256 int);
257
258 static int xl_dma_alloc (device_t);
259 static void xl_dma_free (device_t);
260
261 #ifdef notdef
262 static void xl_testpacket (struct xl_softc *);
263 #endif
264
265 static int xl_miibus_readreg (device_t, int, int);
266 static int xl_miibus_writereg (device_t, int, int, int);
267 static void xl_miibus_statchg (device_t);
268 static void xl_miibus_mediainit (device_t);
269
270 static device_method_t xl_methods[] = {
271 /* Device interface */
272 DEVMETHOD(device_probe, xl_probe),
273 DEVMETHOD(device_attach, xl_attach),
274 DEVMETHOD(device_detach, xl_detach),
275 DEVMETHOD(device_shutdown, xl_shutdown),
276 DEVMETHOD(device_suspend, xl_suspend),
277 DEVMETHOD(device_resume, xl_resume),
278
279 /* bus interface */
280 DEVMETHOD(bus_print_child, bus_generic_print_child),
281 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
282
283 /* MII interface */
284 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
285 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
286 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
287 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
288
289 { 0, 0 }
290 };
291
292 static driver_t xl_driver = {
293 "xl",
294 xl_methods,
295 sizeof(struct xl_softc)
296 };
297
298 static devclass_t xl_devclass;
299
300 DECLARE_DUMMY_MODULE(if_xl);
301 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
302 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
303 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
304 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
305
306 static void
307 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
308 {
309 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
310 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
311 if (sc->xl_flags & XL_FLAG_FUNCREG)
312 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
313 }
314
315 static void
316 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
317 {
318 u_int32_t *paddr;
319
320 paddr = arg;
321 *paddr = segs->ds_addr;
322 }
323
324 static void
325 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
326 bus_size_t mapsize, int error)
327 {
328 u_int32_t *paddr;
329
330 if (error)
331 return;
332 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
333 paddr = arg;
334 *paddr = segs->ds_addr;
335 }
336
337 static void
338 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
339 bus_size_t mapsize, int error)
340 {
341 struct xl_list *l;
342 int i, total_len;
343
344 if (error)
345 return;
346
347 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
348
349 total_len = 0;
350 l = arg;
351 for (i = 0; i < nseg; i++) {
352 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
353 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
354 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
355 total_len += segs[i].ds_len;
356 }
357 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
358 XL_LAST_FRAG);
359 l->xl_status = htole32(total_len);
360 l->xl_next = 0;
361 }
362
363 /*
364 * Murphy's law says that it's possible the chip can wedge and
365 * the 'command in progress' bit may never clear. Hence, we wait
366 * only a finite amount of time to avoid getting caught in an
367 * infinite loop. Normally this delay routine would be a macro,
368 * but it isn't called during normal operation so we can afford
369 * to make it a function.
370 */
371 static void
372 xl_wait(struct xl_softc *sc)
373 {
374 int i;
375
376 for (i = 0; i < XL_TIMEOUT; i++) {
377 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
378 break;
379 }
380
381 if (i == XL_TIMEOUT)
382 if_printf(&sc->arpcom.ac_if, "command never completed!");
383
384 return;
385 }
386
387 /*
388 * MII access routines are provided for adapters with external
389 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
390 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
391 * Note: if you don't perform the MDIO operations just right,
392 * it's possible to end up with code that works correctly with
393 * some chips/CPUs/processor speeds/bus speeds/etc but not
394 * with others.
395 */
396 #define MII_SET(x) \
397 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
398 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
399
400 #define MII_CLR(x) \
401 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
402 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
403
404 /*
405 * Sync the PHYs by setting data bit and strobing the clock 32 times.
406 */
407 static void
408 xl_mii_sync(struct xl_softc *sc)
409 {
410 int i;
411
412 XL_SEL_WIN(4);
413 MII_SET(XL_MII_DIR|XL_MII_DATA);
414
415 for (i = 0; i < 32; i++) {
416 MII_SET(XL_MII_CLK);
417 MII_SET(XL_MII_DATA);
418 MII_SET(XL_MII_DATA);
419 MII_CLR(XL_MII_CLK);
420 MII_SET(XL_MII_DATA);
421 MII_SET(XL_MII_DATA);
422 }
423
424 return;
425 }
426
427 /*
428 * Clock a series of bits through the MII.
429 */
430 static void
431 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
432 {
433 int i;
434
435 XL_SEL_WIN(4);
436 MII_CLR(XL_MII_CLK);
437
438 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
439 if (bits & i) {
440 MII_SET(XL_MII_DATA);
441 } else {
442 MII_CLR(XL_MII_DATA);
443 }
444 MII_CLR(XL_MII_CLK);
445 MII_SET(XL_MII_CLK);
446 }
447 }
448
449 /*
450 * Read an PHY register through the MII.
451 */
452 static int
453 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
454 {
455 int i, ack;
456
457 /*
458 * Set up frame for RX.
459 */
460 frame->mii_stdelim = XL_MII_STARTDELIM;
461 frame->mii_opcode = XL_MII_READOP;
462 frame->mii_turnaround = 0;
463 frame->mii_data = 0;
464
465 /*
466 * Select register window 4.
467 */
468
469 XL_SEL_WIN(4);
470
471 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
472 /*
473 * Turn on data xmit.
474 */
475 MII_SET(XL_MII_DIR);
476
477 xl_mii_sync(sc);
478
479 /*
480 * Send command/address info.
481 */
482 xl_mii_send(sc, frame->mii_stdelim, 2);
483 xl_mii_send(sc, frame->mii_opcode, 2);
484 xl_mii_send(sc, frame->mii_phyaddr, 5);
485 xl_mii_send(sc, frame->mii_regaddr, 5);
486
487 /* Idle bit */
488 MII_CLR((XL_MII_CLK|XL_MII_DATA));
489 MII_SET(XL_MII_CLK);
490
491 /* Turn off xmit. */
492 MII_CLR(XL_MII_DIR);
493
494 /* Check for ack */
495 MII_CLR(XL_MII_CLK);
496 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
497 MII_SET(XL_MII_CLK);
498
499 /*
500 * Now try reading data bits. If the ack failed, we still
501 * need to clock through 16 cycles to keep the PHY(s) in sync.
502 */
503 if (ack) {
504 for(i = 0; i < 16; i++) {
505 MII_CLR(XL_MII_CLK);
506 MII_SET(XL_MII_CLK);
507 }
508 goto fail;
509 }
510
511 for (i = 0x8000; i; i >>= 1) {
512 MII_CLR(XL_MII_CLK);
513 if (!ack) {
514 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
515 frame->mii_data |= i;
516 }
517 MII_SET(XL_MII_CLK);
518 }
519
520 fail:
521
522 MII_CLR(XL_MII_CLK);
523 MII_SET(XL_MII_CLK);
524
525 if (ack)
526 return(1);
527 return(0);
528 }
529
530 /*
531 * Write to a PHY register through the MII.
532 */
533 static int
534 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
535 {
536 /*
537 * Set up frame for TX.
538 */
539
540 frame->mii_stdelim = XL_MII_STARTDELIM;
541 frame->mii_opcode = XL_MII_WRITEOP;
542 frame->mii_turnaround = XL_MII_TURNAROUND;
543
544 /*
545 * Select the window 4.
546 */
547 XL_SEL_WIN(4);
548
549 /*
550 * Turn on data output.
551 */
552 MII_SET(XL_MII_DIR);
553
554 xl_mii_sync(sc);
555
556 xl_mii_send(sc, frame->mii_stdelim, 2);
557 xl_mii_send(sc, frame->mii_opcode, 2);
558 xl_mii_send(sc, frame->mii_phyaddr, 5);
559 xl_mii_send(sc, frame->mii_regaddr, 5);
560 xl_mii_send(sc, frame->mii_turnaround, 2);
561 xl_mii_send(sc, frame->mii_data, 16);
562
563 /* Idle bit. */
564 MII_SET(XL_MII_CLK);
565 MII_CLR(XL_MII_CLK);
566
567 /*
568 * Turn off xmit.
569 */
570 MII_CLR(XL_MII_DIR);
571
572 return(0);
573 }
574
575 static int
576 xl_miibus_readreg(device_t dev, int phy, int reg)
577 {
578 struct xl_softc *sc;
579 struct xl_mii_frame frame;
580
581 sc = device_get_softc(dev);
582
583 /*
584 * Pretend that PHYs are only available at MII address 24.
585 * This is to guard against problems with certain 3Com ASIC
586 * revisions that incorrectly map the internal transceiver
587 * control registers at all MII addresses. This can cause
588 * the miibus code to attach the same PHY several times over.
589 */
590 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
591 return(0);
592
593 bzero((char *)&frame, sizeof(frame));
594
595 frame.mii_phyaddr = phy;
596 frame.mii_regaddr = reg;
597 xl_mii_readreg(sc, &frame);
598
599 return(frame.mii_data);
600 }
601
602 static int
603 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
604 {
605 struct xl_softc *sc;
606 struct xl_mii_frame frame;
607
608 sc = device_get_softc(dev);
609
610 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
611 return(0);
612
613 bzero((char *)&frame, sizeof(frame));
614
615 frame.mii_phyaddr = phy;
616 frame.mii_regaddr = reg;
617 frame.mii_data = data;
618
619 xl_mii_writereg(sc, &frame);
620
621 return(0);
622 }
623
624 static void
625 xl_miibus_statchg(device_t dev)
626 {
627 struct xl_softc *sc;
628 struct mii_data *mii;
629
630
631 sc = device_get_softc(dev);
632 mii = device_get_softc(sc->xl_miibus);
633
634 xl_setcfg(sc);
635
636 /* Set ASIC's duplex mode to match the PHY. */
637 XL_SEL_WIN(3);
638 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
639 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
640 else
641 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
642 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
643
644 return;
645 }
646
647 /*
648 * Special support for the 3c905B-COMBO. This card has 10/100 support
649 * plus BNC and AUI ports. This means we will have both an miibus attached
650 * plus some non-MII media settings. In order to allow this, we have to
651 * add the extra media to the miibus's ifmedia struct, but we can't do
652 * that during xl_attach() because the miibus hasn't been attached yet.
653 * So instead, we wait until the miibus probe/attach is done, at which
654 * point we will get a callback telling is that it's safe to add our
655 * extra media.
656 */
657 static void
658 xl_miibus_mediainit(device_t dev)
659 {
660 struct xl_softc *sc;
661 struct mii_data *mii;
662 struct ifmedia *ifm;
663
664 sc = device_get_softc(dev);
665 mii = device_get_softc(sc->xl_miibus);
666 ifm = &mii->mii_media;
667
668 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
669 /*
670 * Check for a 10baseFL board in disguise.
671 */
672 if (sc->xl_type == XL_TYPE_905B &&
673 sc->xl_media == XL_MEDIAOPT_10FL) {
674 if (bootverbose)
675 device_printf(dev, "found 10baseFL\n");
676 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
677 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
678 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
679 ifmedia_add(ifm,
680 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
681 } else {
682 if (bootverbose)
683 device_printf(dev, "found AUI\n");
684 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
685 }
686 }
687
688 if (sc->xl_media & XL_MEDIAOPT_BNC) {
689 if (bootverbose)
690 device_printf(dev, "found BNC\n");
691 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
692 }
693
694 return;
695 }
696
697 /*
698 * The EEPROM is slow: give it time to come ready after issuing
699 * it a command.
700 */
701 static int
702 xl_eeprom_wait(struct xl_softc *sc)
703 {
704 int i;
705
706 for (i = 0; i < 100; i++) {
707 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
708 DELAY(162);
709 else
710 break;
711 }
712
713 if (i == 100) {
714 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
715 return(1);
716 }
717
718 return(0);
719 }
720
721 /*
722 * Read a sequence of words from the EEPROM. Note that ethernet address
723 * data is stored in the EEPROM in network byte order.
724 */
725 static int
726 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
727 {
728 int err = 0, i;
729 u_int16_t word = 0, *ptr;
730 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
731 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
732 /* WARNING! DANGER!
733 * It's easy to accidentally overwrite the rom content!
734 * Note: the 3c575 uses 8bit EEPROM offsets.
735 */
736 XL_SEL_WIN(0);
737
738 if (xl_eeprom_wait(sc))
739 return(1);
740
741 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
742 off += 0x30;
743
744 for (i = 0; i < cnt; i++) {
745 if (sc->xl_flags & XL_FLAG_8BITROM)
746 CSR_WRITE_2(sc, XL_W0_EE_CMD,
747 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
748 else
749 CSR_WRITE_2(sc, XL_W0_EE_CMD,
750 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
751 err = xl_eeprom_wait(sc);
752 if (err)
753 break;
754 word = CSR_READ_2(sc, XL_W0_EE_DATA);
755 ptr = (u_int16_t *)(dest + (i * 2));
756 if (swap)
757 *ptr = ntohs(word);
758 else
759 *ptr = word;
760 }
761
762 return(err ? 1 : 0);
763 }
764
765 /*
766 * NICs older than the 3c905B have only one multicast option, which
767 * is to enable reception of all multicast frames.
768 */
769 static void
770 xl_setmulti(struct xl_softc *sc)
771 {
772 struct ifnet *ifp;
773 struct ifmultiaddr *ifma;
774 u_int8_t rxfilt;
775 int mcnt = 0;
776
777 ifp = &sc->arpcom.ac_if;
778
779 XL_SEL_WIN(5);
780 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
781
782 if (ifp->if_flags & IFF_ALLMULTI) {
783 rxfilt |= XL_RXFILTER_ALLMULTI;
784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
785 return;
786 }
787
788 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
789 mcnt++;
790
791 if (mcnt)
792 rxfilt |= XL_RXFILTER_ALLMULTI;
793 else
794 rxfilt &= ~XL_RXFILTER_ALLMULTI;
795
796 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
797
798 return;
799 }
800
801 /*
802 * 3c905B adapters have a hash filter that we can program.
803 */
804 static void
805 xl_setmulti_hash(struct xl_softc *sc)
806 {
807 struct ifnet *ifp;
808 int h = 0, i;
809 struct ifmultiaddr *ifma;
810 u_int8_t rxfilt;
811 int mcnt = 0;
812
813 ifp = &sc->arpcom.ac_if;
814
815 XL_SEL_WIN(5);
816 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
817
818 if (ifp->if_flags & IFF_ALLMULTI) {
819 rxfilt |= XL_RXFILTER_ALLMULTI;
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
821 return;
822 } else
823 rxfilt &= ~XL_RXFILTER_ALLMULTI;
824
825
826 /* first, zot all the existing hash bits */
827 for (i = 0; i < XL_HASHFILT_SIZE; i++)
828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
829
830 /* now program new ones */
831 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
832 if (ifma->ifma_addr->sa_family != AF_LINK)
833 continue;
834
835 /*
836 * Note: the 3c905B currently only supports a 64-bit
837 * hash table, which means we really only need 6 bits,
838 * but the manual indicates that future chip revisions
839 * will have a 256-bit hash table, hence the routine is
840 * set up to calculate 8 bits of position info in case
841 * we need it some day.
842 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
843 * have a 256 bit hash table. This means we have to use
844 * all 8 bits regardless. On older cards, the upper 2
845 * bits will be ignored. Grrrr....
846 */
847 h = ether_crc32_be(
848 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
849 ETHER_ADDR_LEN) & 0xff;
850 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
851 mcnt++;
852 }
853
854 if (mcnt)
855 rxfilt |= XL_RXFILTER_MULTIHASH;
856 else
857 rxfilt &= ~XL_RXFILTER_MULTIHASH;
858
859 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
860
861 return;
862 }
863
864 #ifdef notdef
865 static void
866 xl_testpacket(struct xl_softc *sc)
867 {
868 struct mbuf *m;
869 struct ifnet *ifp;
870
871 ifp = &sc->arpcom.ac_if;
872
873 MGETHDR(m, MB_DONTWAIT, MT_DATA);
874
875 if (m == NULL)
876 return;
877
878 bcopy(&sc->arpcom.ac_enaddr,
879 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
880 bcopy(&sc->arpcom.ac_enaddr,
881 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
882 mtod(m, struct ether_header *)->ether_type = htons(3);
883 mtod(m, unsigned char *)[14] = 0;
884 mtod(m, unsigned char *)[15] = 0;
885 mtod(m, unsigned char *)[16] = 0xE3;
886 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
887 IF_ENQUEUE(&ifp->if_snd, m);
888 xl_start(ifp);
889
890 return;
891 }
892 #endif
893
894 static void
895 xl_setcfg(struct xl_softc *sc)
896 {
897 u_int32_t icfg;
898
899 XL_SEL_WIN(3);
900 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
901 icfg &= ~XL_ICFG_CONNECTOR_MASK;
902 if (sc->xl_media & XL_MEDIAOPT_MII ||
903 sc->xl_media & XL_MEDIAOPT_BT4)
904 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
905 if (sc->xl_media & XL_MEDIAOPT_BTX)
906 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
907
908 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
910
911 return;
912 }
913
914 static void
915 xl_setmode(struct xl_softc *sc, int media)
916 {
917 struct ifnet *ifp = &sc->arpcom.ac_if;
918 u_int32_t icfg;
919 u_int16_t mediastat;
920
921 if_printf(ifp, "selecting ");
922
923 XL_SEL_WIN(4);
924 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
925 XL_SEL_WIN(3);
926 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
927
928 if (sc->xl_media & XL_MEDIAOPT_BT) {
929 if (IFM_SUBTYPE(media) == IFM_10_T) {
930 kprintf("10baseT transceiver, ");
931 sc->xl_xcvr = XL_XCVR_10BT;
932 icfg &= ~XL_ICFG_CONNECTOR_MASK;
933 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
934 mediastat |= XL_MEDIASTAT_LINKBEAT|
935 XL_MEDIASTAT_JABGUARD;
936 mediastat &= ~XL_MEDIASTAT_SQEENB;
937 }
938 }
939
940 if (sc->xl_media & XL_MEDIAOPT_BFX) {
941 if (IFM_SUBTYPE(media) == IFM_100_FX) {
942 kprintf("100baseFX port, ");
943 sc->xl_xcvr = XL_XCVR_100BFX;
944 icfg &= ~XL_ICFG_CONNECTOR_MASK;
945 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
946 mediastat |= XL_MEDIASTAT_LINKBEAT;
947 mediastat &= ~XL_MEDIASTAT_SQEENB;
948 }
949 }
950
951 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
952 if (IFM_SUBTYPE(media) == IFM_10_5) {
953 kprintf("AUI port, ");
954 sc->xl_xcvr = XL_XCVR_AUI;
955 icfg &= ~XL_ICFG_CONNECTOR_MASK;
956 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
957 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
958 XL_MEDIASTAT_JABGUARD);
959 mediastat |= ~XL_MEDIASTAT_SQEENB;
960 }
961 if (IFM_SUBTYPE(media) == IFM_10_FL) {
962 kprintf("10baseFL transceiver, ");
963 sc->xl_xcvr = XL_XCVR_AUI;
964 icfg &= ~XL_ICFG_CONNECTOR_MASK;
965 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
966 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
967 XL_MEDIASTAT_JABGUARD);
968 mediastat |= ~XL_MEDIASTAT_SQEENB;
969 }
970 }
971
972 if (sc->xl_media & XL_MEDIAOPT_BNC) {
973 if (IFM_SUBTYPE(media) == IFM_10_2) {
974 kprintf("BNC port, ");
975 sc->xl_xcvr = XL_XCVR_COAX;
976 icfg &= ~XL_ICFG_CONNECTOR_MASK;
977 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
978 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
979 XL_MEDIASTAT_JABGUARD|
980 XL_MEDIASTAT_SQEENB);
981 }
982 }
983
984 if ((media & IFM_GMASK) == IFM_FDX ||
985 IFM_SUBTYPE(media) == IFM_100_FX) {
986 kprintf("full duplex\n");
987 XL_SEL_WIN(3);
988 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
989 } else {
990 kprintf("half duplex\n");
991 XL_SEL_WIN(3);
992 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
993 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
994 }
995
996 if (IFM_SUBTYPE(media) == IFM_10_2)
997 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
998 else
999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1000 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1001 XL_SEL_WIN(4);
1002 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1003 DELAY(800);
1004 XL_SEL_WIN(7);
1005 }
1006
1007 static void
1008 xl_reset(struct xl_softc *sc)
1009 {
1010 int i;
1011
1012 XL_SEL_WIN(0);
1013 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1014 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1015 XL_RESETOPT_DISADVFD:0));
1016
1017 /*
1018 * If we're using memory mapped register mode, pause briefly
1019 * after issuing the reset command before trying to access any
1020 * other registers. With my 3c575C cardbus card, failing to do
1021 * this results in the system locking up while trying to poll
1022 * the command busy bit in the status register.
1023 */
1024 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1025 DELAY(100000);
1026
1027 for (i = 0; i < XL_TIMEOUT; i++) {
1028 DELAY(10);
1029 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1030 break;
1031 }
1032
1033 if (i == XL_TIMEOUT)
1034 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1035
1036 /* Reset TX and RX. */
1037 /* Note: the RX reset takes an absurd amount of time
1038 * on newer versions of the Tornado chips such as those
1039 * on the 3c905CX and newer 3c908C cards. We wait an
1040 * extra amount of time so that xl_wait() doesn't complain
1041 * and annoy the users.
1042 */
1043 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1044 DELAY(100000);
1045 xl_wait(sc);
1046 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1047 xl_wait(sc);
1048
1049 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1050 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1051 XL_SEL_WIN(2);
1052 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1053 XL_W2_RESET_OPTIONS)
1054 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1055 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1056 );
1057 }
1058
1059 /* Wait a little while for the chip to get its brains in order. */
1060 DELAY(100000);
1061 return;
1062 }
1063
1064 /*
1065 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1066 * IDs against our list and return a device name if we find a match.
1067 */
1068 static int
1069 xl_probe(device_t dev)
1070 {
1071 struct xl_type *t;
1072 uint16_t vid, did;
1073
1074 vid = pci_get_vendor(dev);
1075 did = pci_get_device(dev);
1076 for (t = xl_devs; t->xl_name != NULL; t++) {
1077 if (vid == t->xl_vid && did == t->xl_did) {
1078 device_set_desc(dev, t->xl_name);
1079 return(0);
1080 }
1081 }
1082 return(ENXIO);
1083 }
1084
1085 /*
1086 * This routine is a kludge to work around possible hardware faults
1087 * or manufacturing defects that can cause the media options register
1088 * (or reset options register, as it's called for the first generation
1089 * 3c90x adapters) to return an incorrect result. I have encountered
1090 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1091 * which doesn't have any of the 'mediaopt' bits set. This screws up
1092 * the attach routine pretty badly because it doesn't know what media
1093 * to look for. If we find ourselves in this predicament, this routine
1094 * will try to guess the media options values and warn the user of a
1095 * possible manufacturing defect with his adapter/system/whatever.
1096 */
1097 static void
1098 xl_mediacheck(struct xl_softc *sc)
1099 {
1100 struct ifnet *ifp = &sc->arpcom.ac_if;
1101
1102 /*
1103 * If some of the media options bits are set, assume they are
1104 * correct. If not, try to figure it out down below.
1105 * XXX I should check for 10baseFL, but I don't have an adapter
1106 * to test with.
1107 */
1108 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1109 /*
1110 * Check the XCVR value. If it's not in the normal range
1111 * of values, we need to fake it up here.
1112 */
1113 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1114 return;
1115 else {
1116 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1117 sc->xl_xcvr);
1118 if_printf(ifp,
1119 "choosing new default based on card type\n");
1120 }
1121 } else {
1122 if (sc->xl_type == XL_TYPE_905B &&
1123 sc->xl_media & XL_MEDIAOPT_10FL)
1124 return;
1125 if_printf(ifp, "WARNING: no media options bits set in "
1126 "the media options register!!\n");
1127 if_printf(ifp, "this could be a manufacturing defect in "
1128 "your adapter or system\n");
1129 if_printf(ifp, "attempting to guess media type; you "
1130 "should probably consult your vendor\n");
1131 }
1132
1133 xl_choose_xcvr(sc, 1);
1134 }
1135
1136 static void
1137 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1138 {
1139 struct ifnet *ifp = &sc->arpcom.ac_if;
1140 u_int16_t devid;
1141
1142 /*
1143 * Read the device ID from the EEPROM.
1144 * This is what's loaded into the PCI device ID register, so it has
1145 * to be correct otherwise we wouldn't have gotten this far.
1146 */
1147 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1148
1149 switch(devid) {
1150 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1151 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1152 sc->xl_media = XL_MEDIAOPT_BT;
1153 sc->xl_xcvr = XL_XCVR_10BT;
1154 if (verbose)
1155 if_printf(ifp, "guessing 10BaseT transceiver\n");
1156 break;
1157 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1158 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1159 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1160 sc->xl_xcvr = XL_XCVR_10BT;
1161 if (verbose)
1162 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1163 break;
1164 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1165 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1166 sc->xl_xcvr = XL_XCVR_10BT;
1167 if (verbose)
1168 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1169 break;
1170 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1171 sc->xl_media = XL_MEDIAOPT_10FL;
1172 sc->xl_xcvr = XL_XCVR_AUI;
1173 if (verbose)
1174 if_printf(ifp, "guessing 10baseFL\n");
1175 break;
1176 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1177 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1178 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1179 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1180 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1181 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1182 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1183 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1184 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1185 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1186 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1187 sc->xl_media = XL_MEDIAOPT_MII;
1188 sc->xl_xcvr = XL_XCVR_MII;
1189 if (verbose)
1190 if_printf(ifp, "guessing MII\n");
1191 break;
1192 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1193 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1194 sc->xl_media = XL_MEDIAOPT_BT4;
1195 sc->xl_xcvr = XL_XCVR_MII;
1196 if (verbose)
1197 if_printf(ifp, "guessing 100BaseT4/MII\n");
1198 break;
1199 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1200 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1201 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1202 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1203 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1204 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1205 sc->xl_media = XL_MEDIAOPT_BTX;
1206 sc->xl_xcvr = XL_XCVR_AUTO;
1207 if (verbose)
1208 if_printf(ifp, "guessing 10/100 internal\n");
1209 break;
1210 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1211 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1212 sc->xl_xcvr = XL_XCVR_AUTO;
1213 if (verbose)
1214 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1215 break;
1216 default:
1217 if_printf(ifp,
1218 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1219 sc->xl_media = XL_MEDIAOPT_BT;
1220 break;
1221 }
1222
1223 return;
1224 }
1225
1226 /*
1227 * Attach the interface. Allocate softc structures, do ifmedia
1228 * setup and ethernet/BPF attach.
1229 */
1230 static int
1231 xl_attach(device_t dev)
1232 {
1233 u_char eaddr[ETHER_ADDR_LEN];
1234 u_int16_t xcvr[2];
1235 struct xl_softc *sc;
1236 struct ifnet *ifp;
1237 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1238 int error = 0, rid, res;
1239 uint16_t did;
1240
1241 sc = device_get_softc(dev);
1242
1243 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1244
1245 did = pci_get_device(dev);
1246
1247 sc->xl_flags = 0;
1248 if (did == TC_DEVICEID_HURRICANE_555)
1249 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1250 if (did == TC_DEVICEID_HURRICANE_556 ||
1251 did == TC_DEVICEID_HURRICANE_556B)
1252 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1253 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1254 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1255 if (did == TC_DEVICEID_HURRICANE_555 ||
1256 did == TC_DEVICEID_HURRICANE_556)
1257 sc->xl_flags |= XL_FLAG_8BITROM;
1258 if (did == TC_DEVICEID_HURRICANE_556B)
1259 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1260 if (did == TC_DEVICEID_HURRICANE_575B ||
1261 did == TC_DEVICEID_HURRICANE_575C ||
1262 did == TC_DEVICEID_HURRICANE_656B ||
1263 did == TC_DEVICEID_TORNADO_656C)
1264 sc->xl_flags |= XL_FLAG_FUNCREG;
1265 if (did == TC_DEVICEID_HURRICANE_575A ||
1266 did == TC_DEVICEID_HURRICANE_575B ||
1267 did == TC_DEVICEID_HURRICANE_575C ||
1268 did == TC_DEVICEID_HURRICANE_656B ||
1269 did == TC_DEVICEID_TORNADO_656C)
1270 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1271 XL_FLAG_8BITROM;
1272 if (did == TC_DEVICEID_HURRICANE_656)
1273 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1274 if (did == TC_DEVICEID_HURRICANE_575B)
1275 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1276 if (did == TC_DEVICEID_HURRICANE_575C)
1277 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1278 if (did == TC_DEVICEID_TORNADO_656C)
1279 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1280 if (did == TC_DEVICEID_HURRICANE_656 ||
1281 did == TC_DEVICEID_HURRICANE_656B)
1282 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1283 XL_FLAG_INVERT_LED_PWR;
1284 if (did == TC_DEVICEID_TORNADO_10_100BT_920B)
1285 sc->xl_flags |= XL_FLAG_PHYOK;
1286 #ifndef BURN_BRIDGES
1287 /*
1288 * If this is a 3c905B, we have to check one extra thing.
1289 * The 905B supports power management and may be placed in
1290 * a low-power mode (D3 mode), typically by certain operating
1291 * systems which shall not be named. The PCI BIOS is supposed
1292 * to reset the NIC and bring it out of low-power mode, but
1293 * some do not. Consequently, we have to see if this chip
1294 * supports power management, and if so, make sure it's not
1295 * in low-power mode. If power management is available, the
1296 * capid byte will be 0x01.
1297 *
1298 * I _think_ that what actually happens is that the chip
1299 * loses its PCI configuration during the transition from
1300 * D3 back to D0; this means that it should be possible for
1301 * us to save the PCI iobase, membase and IRQ, put the chip
1302 * back in the D0 state, then restore the PCI config ourselves.
1303 */
1304
1305 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1306 u_int32_t iobase, membase, irq;
1307
1308 /* Save important PCI config data. */
1309 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1310 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1311 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1312
1313 /* Reset the power state. */
1314 device_printf(dev, "chip is in D%d power mode "
1315 "-- setting to D0\n", pci_get_powerstate(dev));
1316
1317 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1318
1319 /* Restore PCI config data. */
1320 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1321 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1322 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1323 }
1324 #endif
1325 /*
1326 * Map control/status registers.
1327 */
1328 pci_enable_busmaster(dev);
1329
1330 rid = XL_PCI_LOMEM;
1331 res = SYS_RES_MEMORY;
1332
1333 #if 0
1334 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1335 #endif
1336
1337 if (sc->xl_res != NULL) {
1338 sc->xl_flags |= XL_FLAG_USE_MMIO;
1339 if (bootverbose)
1340 device_printf(dev, "using memory mapped I/O\n");
1341 } else {
1342 rid = XL_PCI_LOIO;
1343 res = SYS_RES_IOPORT;
1344 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1345 if (sc->xl_res == NULL) {
1346 device_printf(dev, "couldn't map ports/memory\n");
1347 error = ENXIO;
1348 goto fail;
1349 }
1350 if (bootverbose)
1351 device_printf(dev, "using port I/O\n");
1352 }
1353
1354 sc->xl_btag = rman_get_bustag(sc->xl_res);
1355 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1356
1357 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1358 rid = XL_PCI_FUNCMEM;
1359 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1360 RF_ACTIVE);
1361
1362 if (sc->xl_fres == NULL) {
1363 device_printf(dev, "couldn't map funcreg memory\n");
1364 error = ENXIO;
1365 goto fail;
1366 }
1367
1368 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1369 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1370 }
1371
1372 /* Allocate interrupt */
1373 rid = 0;
1374 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1375 RF_SHAREABLE | RF_ACTIVE);
1376 if (sc->xl_irq == NULL) {
1377 device_printf(dev, "couldn't map interrupt\n");
1378 error = ENXIO;
1379 goto fail;
1380 }
1381
1382 ifp = &sc->arpcom.ac_if;
1383 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1384
1385 /* Reset the adapter. */
1386 xl_reset(sc);
1387
1388 /*
1389 * Get station address from the EEPROM.
1390 */
1391 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1392 device_printf(dev, "failed to read station address\n");
1393 error = ENXIO;
1394 goto fail;
1395 }
1396
1397 callout_init(&sc->xl_stat_timer);
1398
1399 error = xl_dma_alloc(dev);
1400 if (error)
1401 goto fail;
1402
1403 /*
1404 * Figure out the card type. 3c905B adapters have the
1405 * 'supportsNoTxLength' bit set in the capabilities
1406 * word in the EEPROM.
1407 * Note: my 3c575C cardbus card lies. It returns a value
1408 * of 0x1578 for its capabilities word, which is somewhat
1409 * nonsensical. Another way to distinguish a 3c90x chip
1410 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1411 * bit. This will only be set for 3c90x boomerage chips.
1412 */
1413 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1414 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1415 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1416 sc->xl_type = XL_TYPE_905B;
1417 else
1418 sc->xl_type = XL_TYPE_90X;
1419 if (bootverbose) {
1420 device_printf(dev, "type %s\n",
1421 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1422 }
1423
1424 ifp->if_softc = sc;
1425 ifp->if_mtu = ETHERMTU;
1426 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1427 ifp->if_ioctl = xl_ioctl;
1428 if (sc->xl_type == XL_TYPE_905B) {
1429 ifp->if_start = xl_start_90xB;
1430 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU;
1431 } else {
1432 ifp->if_start = xl_start;
1433 }
1434 ifp->if_watchdog = xl_watchdog;
1435 ifp->if_init = xl_init;
1436 #ifdef DEVICE_POLLING
1437 ifp->if_poll = xl_poll;
1438 #endif
1439 ifp->if_baudrate = 10000000;
1440 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1441 ifq_set_ready(&ifp->if_snd);
1442 /*
1443 * NOTE: Hardware checksum features disabled by default.
1444 * This seems to corrupt tx packet data one out of a
1445 * million packets or so and then generates a good checksum
1446 * so the receiver doesn't know the packet is bad
1447 */
1448 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1449 if (ifp->if_capenable & IFCAP_TXCSUM)
1450 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1451
1452 /*
1453 * Now we have to see what sort of media we have.
1454 * This includes probing for an MII interace and a
1455 * possible PHY.
1456 */
1457 XL_SEL_WIN(3);
1458 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1459 if (bootverbose)
1460 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1461
1462 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1463 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1464 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1465 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1466
1467 xl_mediacheck(sc);
1468
1469 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1470 || sc->xl_media & XL_MEDIAOPT_BT4) {
1471 if (bootverbose)
1472 if_printf(ifp, "found MII/AUTO\n");
1473 xl_setcfg(sc);
1474
1475 error = mii_phy_probe(dev, &sc->xl_miibus,
1476 xl_ifmedia_upd, xl_ifmedia_sts);
1477 if (error) {
1478 if_printf(ifp, "no PHY found!\n");
1479 goto fail;
1480 }
1481
1482 goto done;
1483 }
1484
1485 /*
1486 * Sanity check. If the user has selected "auto" and this isn't
1487 * a 10/100 card of some kind, we need to force the transceiver
1488 * type to something sane.
1489 */
1490 if (sc->xl_xcvr == XL_XCVR_AUTO)
1491 xl_choose_xcvr(sc, bootverbose);
1492
1493 /*
1494 * Do ifmedia setup.
1495 */
1496 if (sc->xl_media & XL_MEDIAOPT_BT) {
1497 if (bootverbose)
1498 if_printf(ifp, "found 10baseT\n");
1499 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1500 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1501 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1502 ifmedia_add(&sc->ifmedia,
1503 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1504 }
1505
1506 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1507 /*
1508 * Check for a 10baseFL board in disguise.
1509 */
1510 if (sc->xl_type == XL_TYPE_905B &&
1511 sc->xl_media == XL_MEDIAOPT_10FL) {
1512 if (bootverbose)
1513 if_printf(ifp, "found 10baseFL\n");
1514 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1516 0, NULL);
1517 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1518 ifmedia_add(&sc->ifmedia,
1519 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1520 } else {
1521 if (bootverbose)
1522 if_printf(ifp, "found AUI\n");
1523 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1524 }
1525 }
1526
1527 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1528 if (bootverbose)
1529 if_printf(ifp, "found BNC\n");
1530 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1531 }
1532
1533 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1534 if (bootverbose)
1535 if_printf(ifp, "found 100baseFX\n");
1536 ifp->if_baudrate = 100000000;
1537 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1538 }
1539
1540 /* Choose a default media. */
1541 switch(sc->xl_xcvr) {
1542 case XL_XCVR_10BT:
1543 media = IFM_ETHER|IFM_10_T;
1544 xl_setmode(sc, media);
1545 break;
1546 case XL_XCVR_AUI:
1547 if (sc->xl_type == XL_TYPE_905B &&
1548 sc->xl_media == XL_MEDIAOPT_10FL) {
1549 media = IFM_ETHER|IFM_10_FL;
1550 xl_setmode(sc, media);
1551 } else {
1552 media = IFM_ETHER|IFM_10_5;
1553 xl_setmode(sc, media);
1554 }
1555 break;
1556 case XL_XCVR_COAX:
1557 media = IFM_ETHER|IFM_10_2;
1558 xl_setmode(sc, media);
1559 break;
1560 case XL_XCVR_AUTO:
1561 case XL_XCVR_100BTX:
1562 case XL_XCVR_MII:
1563 /* Chosen by miibus */
1564 break;
1565 case XL_XCVR_100BFX:
1566 media = IFM_ETHER|IFM_100_FX;
1567 break;
1568 default:
1569 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1570 /*
1571 * This will probably be wrong, but it prevents
1572 * the ifmedia code from panicking.
1573 */
1574 media = IFM_ETHER|IFM_10_T;
1575 break;
1576 }
1577
1578 if (sc->xl_miibus == NULL)
1579 ifmedia_set(&sc->ifmedia, media);
1580
1581 done:
1582
1583 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1584 XL_SEL_WIN(0);
1585 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1586 }
1587
1588 /*
1589 * Call MI attach routine.
1590 */
1591 ether_ifattach(ifp, eaddr, NULL);
1592
1593 /*
1594 * Tell the upper layer(s) we support long frames.
1595 */
1596 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1597
1598 /* Hook interrupt last to avoid having to lock softc */
1599 error = bus_setup_intr(dev, sc->xl_irq, INTR_NETSAFE,
1600 xl_intr, sc, &sc->xl_intrhand,
1601 ifp->if_serializer);
1602 if (error) {
1603 if_printf(ifp, "couldn't set up irq\n");
1604 ether_ifdetach(ifp);
1605 goto fail;
1606 }
1607
1608 return 0;
1609
1610 fail:
1611 xl_detach(dev);
1612 return error;
1613 }
1614
1615 /*
1616 * Shutdown hardware and free up resources. This can be called any
1617 * time after the mutex has been initialized. It is called in both
1618 * the error case in attach and the normal detach case so it needs
1619 * to be careful about only freeing resources that have actually been
1620 * allocated.
1621 */
1622 static int
1623 xl_detach(device_t dev)
1624 {
1625 struct xl_softc *sc;
1626 struct ifnet *ifp;
1627 int rid, res;
1628
1629 sc = device_get_softc(dev);
1630 ifp = &sc->arpcom.ac_if;
1631
1632 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1633 rid = XL_PCI_LOMEM;
1634 res = SYS_RES_MEMORY;
1635 } else {
1636 rid = XL_PCI_LOIO;
1637 res = SYS_RES_IOPORT;
1638 }
1639
1640 if (device_is_attached(dev)) {
1641 lwkt_serialize_enter(ifp->if_serializer);
1642 xl_reset(sc);
1643 xl_stop(sc);
1644 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1645 lwkt_serialize_exit(ifp->if_serializer);
1646
1647 ether_ifdetach(ifp);
1648 }
1649
1650 if (sc->xl_miibus)
1651 device_delete_child(dev, sc->xl_miibus);
1652 bus_generic_detach(dev);
1653 ifmedia_removeall(&sc->ifmedia);
1654
1655 if (sc->xl_irq)
1656 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1657 if (sc->xl_fres != NULL)
1658 bus_release_resource(dev, SYS_RES_MEMORY,
1659 XL_PCI_FUNCMEM, sc->xl_fres);
1660 if (sc->xl_res)
1661 bus_release_resource(dev, res, rid, sc->xl_res);
1662
1663 xl_dma_free(dev);
1664
1665 return(0);
1666 }
1667
1668 static int
1669 xl_dma_alloc(device_t dev)
1670 {
1671 struct xl_softc *sc;
1672 struct xl_chain_data *cd;
1673 struct xl_list_data *ld;
1674 int i, error;
1675
1676 sc = device_get_softc(dev);
1677 cd = &sc->xl_cdata;
1678 ld = &sc->xl_ldata;
1679
1680 /*
1681 * Now allocate a tag for the DMA descriptor lists and a chunk
1682 * of DMA-able memory based on the tag. Also obtain the DMA
1683 * addresses of the RX and TX ring, which we'll need later.
1684 * All of our lists are allocated as a contiguous block
1685 * of memory.
1686 */
1687 error = bus_dma_tag_create(NULL, 8, 0,
1688 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1689 NULL, NULL,
1690 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ,
1691 0, &ld->xl_rx_tag);
1692 if (error) {
1693 device_printf(dev, "failed to allocate rx dma tag\n");
1694 return error;
1695 }
1696
1697 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list,
1698 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1699 &ld->xl_rx_dmamap);
1700 if (error) {
1701 device_printf(dev, "no memory for rx list buffers!\n");
1702 bus_dma_tag_destroy(ld->xl_rx_tag);
1703 ld->xl_rx_tag = NULL;
1704 return error;
1705 }
1706
1707 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap,
1708 ld->xl_rx_list, XL_RX_LIST_SZ,
1709 xl_dma_map_addr, &ld->xl_rx_dmaaddr,
1710 BUS_DMA_WAITOK);
1711 if (error) {
1712 device_printf(dev, "cannot get dma address of the rx ring!\n");
1713 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1714 ld->xl_rx_dmamap);
1715 bus_dma_tag_destroy(ld->xl_rx_tag);
1716 ld->xl_rx_tag = NULL;
1717 return error;
1718 }
1719
1720 error = bus_dma_tag_create(NULL, 8, 0,
1721 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1722 NULL, NULL,
1723 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ,
1724 0, &ld->xl_tx_tag);
1725 if (error) {
1726 device_printf(dev, "failed to allocate tx dma tag\n");
1727 return error;
1728 }
1729
1730 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list,
1731 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1732 &ld->xl_tx_dmamap);
1733 if (error) {
1734 device_printf(dev, "no memory for list buffers!\n");
1735 bus_dma_tag_destroy(ld->xl_tx_tag);
1736 ld->xl_tx_tag = NULL;
1737 return error;
1738 }
1739
1740 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap,
1741 ld->xl_tx_list, XL_TX_LIST_SZ,
1742 xl_dma_map_addr, &ld->xl_tx_dmaaddr,
1743 BUS_DMA_WAITOK);
1744 if (error) {
1745 device_printf(dev, "cannot get dma address of the tx ring!\n");
1746 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1747 ld->xl_tx_dmamap);
1748 bus_dma_tag_destroy(ld->xl_tx_tag);
1749 ld->xl_tx_tag = NULL;
1750 return error;
1751 }
1752
1753 /*
1754 * Allocate a DMA tag for the mapping of mbufs.
1755 */
1756 error = bus_dma_tag_create(NULL, 1, 0,
1757 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1758 NULL, NULL,
1759 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS,
1760 MCLBYTES, 0, &sc->xl_mtag);
1761 if (error) {
1762 device_printf(dev, "failed to allocate mbuf dma tag\n");
1763 return error;
1764 }
1765
1766 /*
1767 * Allocate a spare DMA map for the RX ring.
1768 */
1769 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1770 if (error) {
1771 device_printf(dev, "failed to create mbuf dma map\n");
1772 bus_dma_tag_destroy(sc->xl_mtag);
1773 sc->xl_mtag = NULL;
1774 return error;
1775 }
1776
1777 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1778 error = bus_dmamap_create(sc->xl_mtag, 0,
1779 &cd->xl_rx_chain[i].xl_map);
1780 if (error) {
1781 device_printf(dev, "failed to create %dth "
1782 "rx descriptor dma map!\n", i);
1783 return error;
1784 }
1785 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1786 }
1787
1788 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1789 error = bus_dmamap_create(sc->xl_mtag, 0,
1790 &cd->xl_tx_chain[i].xl_map);
1791 if (error) {
1792 device_printf(dev, "failed to create %dth "
1793 "tx descriptor dma map!\n", i);
1794 return error;
1795 }
1796 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1797 }
1798 return 0;
1799 }
1800
1801 static void
1802 xl_dma_free(device_t dev)
1803 {
1804 struct xl_softc *sc;
1805 struct xl_chain_data *cd;
1806 struct xl_list_data *ld;
1807 int i;
1808
1809 sc = device_get_softc(dev);
1810 cd = &sc->xl_cdata;
1811 ld = &sc->xl_ldata;
1812
1813 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1814 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1815 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1816 bus_dmamap_unload(sc->xl_mtag,
1817 cd->xl_rx_chain[i].xl_map);
1818 m_freem(cd->xl_rx_chain[i].xl_mbuf);
1819 }
1820 bus_dmamap_destroy(sc->xl_mtag,
1821 cd->xl_rx_chain[i].xl_map);
1822 }
1823 }
1824
1825 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1826 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1827 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1828 bus_dmamap_unload(sc->xl_mtag,
1829 cd->xl_tx_chain[i].xl_map);
1830 m_freem(cd->xl_tx_chain[i].xl_mbuf);
1831 }
1832 bus_dmamap_destroy(sc->xl_mtag,
1833 cd->xl_tx_chain[i].xl_map);
1834 }
1835 }
1836
1837 if (ld->xl_rx_tag) {
1838 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1839 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1840 ld->xl_rx_dmamap);
1841 bus_dma_tag_destroy(ld->xl_rx_tag);
1842 }
1843
1844 if (ld->xl_tx_tag) {
1845 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1846 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1847 ld->xl_tx_dmamap);
1848 bus_dma_tag_destroy(ld->xl_tx_tag);
1849 }
1850
1851 if (sc->xl_mtag) {
1852 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1853 bus_dma_tag_destroy(sc->xl_mtag);
1854 }
1855 }
1856
1857 /*
1858 * Initialize the transmit descriptors.
1859 */
1860 static void
1861 xl_list_tx_init(struct xl_softc *sc)
1862 {
1863 struct xl_chain_data *cd;
1864 struct xl_list_data *ld;
1865 int i;
1866
1867 cd = &sc->xl_cdata;
1868 ld = &sc->xl_ldata;
1869 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1870 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1871 i * sizeof(struct xl_list);
1872 if (i == (XL_TX_LIST_CNT - 1))
1873 cd->xl_tx_chain[i].xl_next = NULL;
1874 else
1875 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1876 }
1877
1878 cd->xl_tx_free = &cd->xl_tx_chain[0];
1879 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1880
1881 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1882 }
1883
1884 /*
1885 * Initialize the transmit descriptors.
1886 */
1887 static void
1888 xl_list_tx_init_90xB(struct xl_softc *sc)
1889 {
1890 struct xl_chain_data *cd;
1891 struct xl_list_data *ld;
1892 int i;
1893
1894 cd = &sc->xl_cdata;
1895 ld = &sc->xl_ldata;
1896 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1897 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1898 i * sizeof(struct xl_list);
1899 if (i == (XL_TX_LIST_CNT - 1))
1900 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1901 else
1902 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1903 if (i == 0) {
1904 cd->xl_tx_chain[i].xl_prev =
1905 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1906 } else {
1907 cd->xl_tx_chain[i].xl_prev =
1908 &cd->xl_tx_chain[i - 1];
1909 }
1910 }
1911
1912 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1913
1914 cd->xl_tx_prod = 1;
1915 cd->xl_tx_cons = 1;
1916 cd->xl_tx_cnt = 0;
1917
1918 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1919 }
1920
1921 /*
1922 * Initialize the RX descriptors and allocate mbufs for them. Note that
1923 * we arrange the descriptors in a closed ring, so that the last descriptor
1924 * points back to the first.
1925 */
1926 static int
1927 xl_list_rx_init(struct xl_softc *sc)
1928 {
1929 struct xl_chain_data *cd;
1930 struct xl_list_data *ld;
1931 int error, i, next;
1932 u_int32_t nextptr;
1933
1934 cd = &sc->xl_cdata;
1935 ld = &sc->xl_ldata;
1936
1937 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1938 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1939 if (error)
1940 return(error);
1941 if (i == (XL_RX_LIST_CNT - 1))
1942 next = 0;
1943 else
1944 next = i + 1;
1945 nextptr = ld->xl_rx_dmaaddr +
1946 next * sizeof(struct xl_list_onefrag);
1947 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1948 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1949 }
1950
1951 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1952 cd->xl_rx_head = &cd->xl_rx_chain[0];
1953
1954 return(0);
1955 }
1956
1957 /*
1958 * Initialize an RX descriptor and attach an MBUF cluster.
1959 * If we fail to do so, we need to leave the old mbuf and
1960 * the old DMA map untouched so that it can be reused.
1961 */
1962 static int
1963 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1964 {
1965 struct mbuf *m_new;
1966 bus_dmamap_t map;
1967 int error;
1968 u_int32_t baddr;
1969
1970 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1971 if (m_new == NULL)
1972 return(ENOBUFS);
1973
1974 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1975
1976 /* Force longword alignment for packet payload. */
1977 m_adj(m_new, ETHER_ALIGN);
1978
1979 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1980 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1981 if (error) {
1982 m_freem(m_new);
1983 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1984 error);
1985 return(error);
1986 }
1987
1988 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1989 map = c->xl_map;
1990 c->xl_map = sc->xl_tmpmap;
1991 sc->xl_tmpmap = map;
1992 c->xl_mbuf = m_new;
1993 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1994 c->xl_ptr->xl_status = 0;
1995 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
1996 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1997 return(0);
1998 }
1999
2000 static int
2001 xl_rx_resync(struct xl_softc *sc)
2002 {
2003 struct xl_chain_onefrag *pos;
2004 int i;
2005
2006 pos = sc->xl_cdata.xl_rx_head;
2007
2008 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2009 if (pos->xl_ptr->xl_status)
2010 break;
2011 pos = pos->xl_next;
2012 }
2013
2014 if (i == XL_RX_LIST_CNT)
2015 return(0);
2016
2017 sc->xl_cdata.xl_rx_head = pos;
2018
2019 return(EAGAIN);
2020 }
2021
2022 /*
2023 * A frame has been uploaded: pass the resulting mbuf chain up to
2024 * the higher level protocols.
2025 */
2026 static void
2027 xl_rxeof(struct xl_softc *sc, int count)
2028 {
2029 struct mbuf *m;
2030 struct ifnet *ifp;
2031 struct xl_chain_onefrag *cur_rx;
2032 int total_len = 0;
2033 u_int32_t rxstat;
2034
2035 ifp = &sc->arpcom.ac_if;
2036
2037 again:
2038
2039 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2040 BUS_DMASYNC_POSTREAD);
2041 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2042 #ifdef DEVICE_POLLING
2043 if (count >= 0 && count-- == 0)
2044 break;
2045 #endif
2046 cur_rx = sc->xl_cdata.xl_rx_head;
2047 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2048 total_len = rxstat & XL_RXSTAT_LENMASK;
2049
2050 /*
2051 * Since we have told the chip to allow large frames,
2052 * we need to trap giant frame errors in software. We allow
2053 * a little more than the normal frame size to account for
2054 * frames with VLAN tags.
2055 */
2056 if (total_len > XL_MAX_FRAMELEN)
2057 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2058
2059 /*
2060 * If an error occurs, update stats, clear the
2061 * status word and leave the mbuf cluster in place:
2062 * it should simply get re-used next time this descriptor
2063 * comes up in the ring.
2064 */
2065 if (rxstat & XL_RXSTAT_UP_ERROR) {
2066 ifp->if_ierrors++;
2067 cur_rx->xl_ptr->xl_status = 0;
2068 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2069 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2070 continue;
2071 }
2072
2073 /*
2074 * If the error bit was not set, the upload complete
2075 * bit should be set which means we have a valid packet.
2076 * If not, something truly strange has happened.
2077 */
2078 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2079 if_printf(ifp,
2080 "bad receive status -- packet dropped\n");
2081 ifp->if_ierrors++;
2082 cur_rx->xl_ptr->xl_status = 0;
2083 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2084 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2085 continue;
2086 }
2087
2088 /* No errors; receive the packet. */
2089 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2090 BUS_DMASYNC_POSTREAD);
2091 m = cur_rx->xl_mbuf;
2092
2093 /*
2094 * Try to conjure up a new mbuf cluster. If that
2095 * fails, it means we have an out of memory condition and
2096 * should leave the buffer in place and continue. This will
2097 * result in a lost packet, but there's little else we
2098 * can do in this situation.
2099 */
2100 if (xl_newbuf(sc, cur_rx)) {
2101 ifp->if_ierrors++;
2102 cur_rx->xl_ptr->xl_status = 0;
2103 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2104 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2105 continue;
2106 }
2107 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2108 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2109
2110 ifp->if_ipackets++;
2111 m->m_pkthdr.rcvif = ifp;
2112 m->m_pkthdr.len = m->m_len = total_len;
2113
2114 if (ifp->if_capenable & IFCAP_RXCSUM) {
2115 /* Do IP checksum checking. */
2116 if (rxstat & XL_RXSTAT_IPCKOK)
2117 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2118 if (!(rxstat & XL_RXSTAT_IPCKERR))
2119 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2120 if ((rxstat & XL_RXSTAT_TCPCOK &&
2121 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2122 (rxstat & XL_RXSTAT_UDPCKOK &&
2123 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2124 m->m_pkthdr.csum_flags |=
2125 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2126 CSUM_FRAG_NOT_CHECKED;
2127 m->m_pkthdr.csum_data = 0xffff;
2128 }
2129 }
2130
2131 ifp->if_input(ifp, m);
2132 }
2133
2134 if (sc->xl_type != XL_TYPE_905B) {
2135 /*
2136 * Handle the 'end of channel' condition. When the upload
2137 * engine hits the end of the RX ring, it will stall. This
2138 * is our cue to flush the RX ring, reload the uplist pointer
2139 * register and unstall the engine.
2140 * XXX This is actually a little goofy. With the ThunderLAN
2141 * chip, you get an interrupt when the receiver hits the end
2142 * of the receive ring, which tells you exactly when you
2143 * you need to reload the ring pointer. Here we have to
2144 * fake it. I'm mad at myself for not being clever enough
2145 * to avoid the use of a goto here.
2146 */
2147 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2148 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2149 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2150 xl_wait(sc);
2151 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2152 sc->xl_ldata.xl_rx_dmaaddr);
2153 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2154 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2155 goto again;
2156 }
2157 }
2158 }
2159
2160 /*
2161 * A frame was downloaded to the chip. It's safe for us to clean up
2162 * the list buffers.
2163 */
2164 static void
2165 xl_txeof(struct xl_softc *sc)
2166 {
2167 struct xl_chain *cur_tx;
2168 struct ifnet *ifp;
2169
2170 ifp = &sc->arpcom.ac_if;
2171
2172 /* Clear the timeout timer. */
2173 ifp->if_timer = 0;
2174
2175 /*
2176 * Go through our tx list and free mbufs for those
2177 * frames that have been uploaded. Note: the 3c905B
2178 * sets a special bit in the status word to let us
2179 * know that a frame has been downloaded, but the
2180 * original 3c900/3c905 adapters don't do that.
2181 * Consequently, we have to use a different test if
2182 * xl_type != XL_TYPE_905B.
2183 */
2184 while(sc->xl_cdata.xl_tx_head != NULL) {
2185 cur_tx = sc->xl_cdata.xl_tx_head;
2186
2187 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2188 break;
2189
2190 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2191 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2192 BUS_DMASYNC_POSTWRITE);
2193 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2194 m_freem(cur_tx->xl_mbuf);
2195 cur_tx->xl_mbuf = NULL;
2196 ifp->if_opackets++;
2197
2198 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2199 sc->xl_cdata.xl_tx_free = cur_tx;
2200 }
2201
2202 if (sc->xl_cdata.xl_tx_head == NULL) {
2203 ifp->if_flags &= ~IFF_OACTIVE;
2204 sc->xl_cdata.xl_tx_tail = NULL;
2205 } else {
2206 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2207 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2208 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2209 sc->xl_cdata.xl_tx_head->xl_phys);
2210 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2211 }
2212 }
2213
2214 return;
2215 }
2216
2217 static void
2218 xl_txeof_90xB(struct xl_softc *sc)
2219 {
2220 struct xl_chain *cur_tx = NULL;
2221 struct ifnet *ifp;
2222 int idx;
2223
2224 ifp = &sc->arpcom.ac_if;
2225
2226 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2227 BUS_DMASYNC_POSTREAD);
2228 idx = sc->xl_cdata.xl_tx_cons;
2229 while(idx != sc->xl_cdata.xl_tx_prod) {
2230
2231 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2232
2233 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2234 XL_TXSTAT_DL_COMPLETE))
2235 break;
2236
2237 if (cur_tx->xl_mbuf != NULL) {
2238 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2239 BUS_DMASYNC_POSTWRITE);
2240 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2241 m_freem(cur_tx->xl_mbuf);
2242 cur_tx->xl_mbuf = NULL;
2243 }
2244
2245 ifp->if_opackets++;
2246
2247 sc->xl_cdata.xl_tx_cnt--;
2248 XL_INC(idx, XL_TX_LIST_CNT);
2249 ifp->if_timer = 0;
2250 }
2251
2252 sc->xl_cdata.xl_tx_cons = idx;
2253
2254 if (cur_tx != NULL)
2255 ifp->if_flags &= ~IFF_OACTIVE;
2256
2257 return;
2258 }
2259
2260 /*
2261 * TX 'end of channel' interrupt handler. Actually, we should
2262 * only get a 'TX complete' interrupt if there's a transmit error,
2263 * so this is really TX error handler.
2264 */
2265 static void
2266 xl_txeoc(struct xl_softc *sc)
2267 {
2268 struct ifnet *ifp = &sc->arpcom.ac_if;
2269 u_int8_t txstat;
2270
2271 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2272 if (txstat & XL_TXSTATUS_UNDERRUN ||
2273 txstat & XL_TXSTATUS_JABBER ||
2274 txstat & XL_TXSTATUS_RECLAIM) {
2275 if_printf(ifp, "transmission error: %x\n", txstat);
2276 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2277 xl_wait(sc);
2278 if (sc->xl_type == XL_TYPE_905B) {
2279 if (sc->xl_cdata.xl_tx_cnt) {
2280 int i;
2281 struct xl_chain *c;
2282 i = sc->xl_cdata.xl_tx_cons;
2283 c = &sc->xl_cdata.xl_tx_chain[i];
2284 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2285 c->xl_phys);
2286 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2287 }
2288 } else {
2289 if (sc->xl_cdata.xl_tx_head != NULL)
2290 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2291 sc->xl_cdata.xl_tx_head->xl_phys);
2292 }
2293 /*
2294 * Remember to set this for the
2295 * first generation 3c90X chips.
2296 */
2297 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2298 if (txstat & XL_TXSTATUS_UNDERRUN &&
2299 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2300 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2301 if_printf(ifp, "tx underrun, increasing tx start"
2302 " threshold to %d bytes\n",
2303 sc->xl_tx_thresh);
2304 }
2305 CSR_WRITE_2(sc, XL_COMMAND,
2306 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2307 if (sc->xl_type == XL_TYPE_905B) {
2308 CSR_WRITE_2(sc, XL_COMMAND,
2309 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2310 }
2311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2313 } else {
2314 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2315 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2316 }
2317 /*
2318 * Write an arbitrary byte to the TX_STATUS register
2319 * to clear this interrupt/error and advance to the next.
2320 */
2321 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2322 }
2323
2324 return;
2325 }
2326
2327 #ifdef DEVICE_POLLING
2328
2329 static void
2330 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2331 {
2332 struct xl_softc *sc = ifp->if_softc;
2333
2334 switch (cmd) {
2335 case POLL_REGISTER:
2336 xl_enable_intrs(sc, 0);
2337 break;
2338 case POLL_DEREGISTER:
2339 xl_enable_intrs(sc, XL_INTRS);
2340 break;
2341 case POLL_ONLY:
2342 case POLL_AND_CHECK_STATUS:
2343 xl_rxeof(sc, count);
2344 if (sc->xl_type == XL_TYPE_905B)
2345 xl_txeof_90xB(sc);
2346 else
2347 xl_txeof(sc);
2348
2349 if (!ifq_is_empty(&ifp->if_snd)) {
2350 if (sc->xl_type == XL_TYPE_905B)
2351 xl_start_90xB(ifp);
2352 else
2353 xl_start_body(ifp, 0);
2354 }
2355
2356 if (cmd == POLL_AND_CHECK_STATUS) {
2357 uint16_t status;
2358
2359 /* XXX copy & pasted from xl_intr() */
2360 status = CSR_READ_2(sc, XL_STATUS);
2361 if ((status & XL_INTRS) && status != 0xFFFF) {
2362 CSR_WRITE_2(sc, XL_COMMAND,
2363 XL_CMD_INTR_ACK | (status & XL_INTRS));
2364
2365 if (status & XL_STAT_TX_COMPLETE) {
2366 ifp->if_oerrors++;
2367 xl_txeoc(sc);
2368 }
2369
2370 if (status & XL_STAT_ADFAIL) {
2371 xl_reset(sc);
2372 xl_init(sc);
2373 }
2374
2375 if (status & XL_STAT_STATSOFLOW) {
2376 sc->xl_stats_no_timeout = 1;
2377 xl_stats_update_serialized(sc);
2378 sc->xl_stats_no_timeout = 0;
2379 }
2380 }
2381 }
2382 break;
2383 }
2384 }
2385
2386 #endif /* DEVICE_POLLING */
2387
2388 static void
2389 xl_intr(void *arg)
2390 {
2391 struct xl_softc *sc;
2392 struct ifnet *ifp;
2393 u_int16_t status;
2394
2395 sc = arg;
2396 ifp = &sc->arpcom.ac_if;
2397
2398 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2399 status != 0xFFFF) {
2400
2401 CSR_WRITE_2(sc, XL_COMMAND,
2402 XL_CMD_INTR_ACK|(status & XL_INTRS));
2403
2404 if (status & XL_STAT_UP_COMPLETE) {
2405 int curpkts;
2406
2407 curpkts = ifp->if_ipackets;
2408 xl_rxeof(sc, -1);
2409 if (curpkts == ifp->if_ipackets) {
2410 while (xl_rx_resync(sc))
2411 xl_rxeof(sc, -1);
2412 }
2413 }
2414
2415 if (status & XL_STAT_DOWN_COMPLETE) {
2416 if (sc->xl_type == XL_TYPE_905B)
2417 xl_txeof_90xB(sc);
2418 else
2419 xl_txeof(sc);
2420 }
2421
2422 if (status & XL_STAT_TX_COMPLETE) {
2423 ifp->if_oerrors++;
2424 xl_txeoc(sc);
2425 }
2426
2427 if (status & XL_STAT_ADFAIL) {
2428 xl_reset(sc);
2429 xl_init(sc);
2430 }
2431
2432 if (status & XL_STAT_STATSOFLOW) {
2433 sc->xl_stats_no_timeout = 1;
2434 xl_stats_update_serialized(sc);
2435 sc->xl_stats_no_timeout = 0;
2436 }
2437 }
2438
2439 if (!ifq_is_empty(&ifp->if_snd))
2440 (*ifp->if_start)(ifp);
2441
2442 return;
2443 }
2444
2445 static void
2446 xl_stats_update(void *xsc)
2447 {
2448 struct xl_softc *sc = xsc;
2449
2450 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2451 xl_stats_update_serialized(xsc);
2452 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2453 }
2454
2455 static void
2456 xl_stats_update_serialized(void *xsc)
2457 {
2458 struct xl_softc *sc;
2459 struct ifnet *ifp;
2460 struct xl_stats xl_stats;
2461 u_int8_t *p;
2462 int i;
2463 struct mii_data *mii = NULL;
2464
2465 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2466
2467 sc = xsc;
2468 ifp = &sc->arpcom.ac_if;
2469 if (sc->xl_miibus != NULL)
2470 mii = device_get_softc(sc->xl_miibus);
2471
2472 p = (u_int8_t *)&xl_stats;
2473
2474 /* Read all the stats registers. */
2475 XL_SEL_WIN(6);
2476
2477 for (i = 0; i < 16; i++)
2478 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2479
2480 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2481
2482 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2483 xl_stats.xl_tx_single_collision +
2484 xl_stats.xl_tx_late_collision;
2485
2486 /*
2487 * Boomerang and cyclone chips have an extra stats counter
2488 * in window 4 (BadSSD). We have to read this too in order
2489 * to clear out all the stats registers and avoid a statsoflow
2490 * interrupt.
2491 */
2492 XL_SEL_WIN(4);
2493 CSR_READ_1(sc, XL_W4_BADSSD);
2494
2495 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2496 mii_tick(mii);
2497
2498 XL_SEL_WIN(7);
2499
2500 if (!sc->xl_stats_no_timeout)
2501 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2502
2503 return;
2504 }
2505
2506 /*
2507 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2508 * pointers to the fragment pointers.
2509 */
2510 static int
2511 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2512 {
2513 int error;
2514 u_int32_t status;
2515 struct ifnet *ifp;
2516
2517 ifp = &sc->arpcom.ac_if;
2518
2519 /*
2520 * Start packing the mbufs in this chain into
2521 * the fragment pointers. Stop when we run out
2522 * of fragments or hit the end of the mbuf chain.
2523 */
2524 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2525 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2526
2527 if (error && error != EFBIG) {
2528 m_freem(m_head);
2529 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2530 return(1);
2531 }
2532
2533 /*
2534 * Handle special case: we used up all 63 fragments,
2535 * but we have more mbufs left in the chain. Copy the
2536 * data into an mbuf cluster. Note that we don't
2537 * bother clearing the values in the other fragment
2538 * pointers/counters; it wouldn't gain us anything,
2539 * and would waste cycles.
2540 */
2541 if (error) {
2542 struct mbuf *m_new;
2543
2544 m_new = m_defrag(m_head, MB_DONTWAIT);
2545 if (m_new == NULL) {
2546 m_freem(m_head);
2547 return(1);
2548 } else {
2549 m_head = m_new;
2550 }
2551
2552 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2553 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2554 if (error) {
2555 m_freem(m_head);
2556 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2557 return(1);
2558 }
2559 }
2560
2561 if (sc->xl_type == XL_TYPE_905B) {
2562 status = XL_TXSTAT_RND_DEFEAT;
2563
2564 if (m_head->m_pkthdr.csum_flags) {
2565 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2566 status |= XL_TXSTAT_IPCKSUM;
2567 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2568 status |= XL_TXSTAT_TCPCKSUM;
2569 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2570 status |= XL_TXSTAT_UDPCKSUM;
2571 }
2572 c->xl_ptr->xl_status = htole32(status);
2573 }
2574
2575 c->xl_mbuf = m_head;
2576 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2577 return(0);
2578 }
2579
2580 static void
2581 xl_start(struct ifnet *ifp)
2582 {
2583 xl_start_body(ifp, 1);
2584 }
2585
2586 /*
2587 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2588 * to the mbuf data regions directly in the transmit lists. We also save a
2589 * copy of the pointers since the transmit list fragment pointers are
2590 * physical addresses.
2591 */
2592 static void
2593 xl_start_body(struct ifnet *ifp, int proc_rx)
2594 {
2595 struct xl_softc *sc;
2596 struct mbuf *m_head = NULL;
2597 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2598 struct xl_chain *prev_tx;
2599 u_int32_t status;
2600 int error;
2601
2602 sc = ifp->if_softc;
2603 /*
2604 * Check for an available queue slot. If there are none,
2605 * punt.
2606 */
2607 if (sc->xl_cdata.xl_tx_free == NULL) {
2608 xl_txeoc(sc);
2609 xl_txeof(sc);
2610 if (sc->xl_cdata.xl_tx_free == NULL) {
2611 ifp->if_flags |= IFF_OACTIVE;
2612 return;
2613 }
2614 }
2615
2616 start_tx = sc->xl_cdata.xl_tx_free;
2617
2618 while(sc->xl_cdata.xl_tx_free != NULL) {
2619 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2620 if (m_head == NULL)
2621 break;
2622
2623 /* Pick a descriptor off the free list. */
2624 prev_tx = cur_tx;
2625 cur_tx = sc->xl_cdata.xl_tx_free;
2626
2627 /* Pack the data into the descriptor. */
2628 error = xl_encap(sc, cur_tx, m_head);
2629 if (error) {
2630 cur_tx = prev_tx;
2631 continue;
2632 }
2633
2634 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2635 cur_tx->xl_next = NULL;
2636
2637 /* Chain it together. */
2638 if (prev != NULL) {
2639 prev->xl_next = cur_tx;
2640 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2641 }
2642 prev = cur_tx;
2643
2644 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2645 }
2646
2647 /*
2648 * If there are no packets queued, bail.
2649 */
2650 if (cur_tx == NULL)
2651 return;
2652
2653 /*
2654 * Place the request for the upload interrupt
2655 * in the last descriptor in the chain. This way, if
2656 * we're chaining several packets at once, we'll only
2657 * get an interupt once for the whole chain rather than
2658 * once for each packet.
2659 */
2660 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2661 XL_TXSTAT_DL_INTR);
2662
2663 /*
2664 * Queue the packets. If the TX channel is clear, update
2665 * the downlist pointer register.
2666 */
2667 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2668 xl_wait(sc);
2669
2670 if (sc->xl_cdata.xl_tx_head != NULL) {
2671 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2672 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2673 htole32(start_tx->xl_phys);
2674 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2675 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2676 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2677 sc->xl_cdata.xl_tx_tail = cur_tx;
2678 } else {
2679 sc->xl_cdata.xl_tx_head = start_tx;
2680 sc->xl_cdata.xl_tx_tail = cur_tx;
2681 }
2682 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2683 BUS_DMASYNC_PREWRITE);
2684
2685 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2686 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2687
2688 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2689
2690 XL_SEL_WIN(7);
2691
2692 /*
2693 * Set a timeout in case the chip goes out to lunch.
2694 */
2695 ifp->if_timer = 5;
2696
2697 if (proc_rx) {
2698 /*
2699 * XXX Under certain conditions, usually on slower machines
2700 * where interrupts may be dropped, it's possible for the
2701 * adapter to chew up all the buffers in the receive ring
2702 * and stall, without us being able to do anything about it.
2703 * To guard against this, we need to make a pass over the
2704 * RX queue to make sure there aren't any packets pending.
2705 * Doing it here means we can flush the receive ring at the
2706 * same time the chip is DMAing the transmit descriptors we
2707 * just gave it.
2708 *
2709 * 3Com goes to some lengths to emphasize the Parallel
2710 * Tasking (tm) nature of their chips in all their marketing
2711 * literature; we may as well take advantage of it. :)
2712 */
2713 xl_rxeof(sc, -1);
2714 }
2715 }
2716
2717 static void
2718 xl_start_90xB(struct ifnet *ifp)
2719 {
2720 struct xl_softc *sc;
2721 struct mbuf *m_head = NULL;
2722 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2723 struct xl_chain *prev_tx;
2724 int error, idx;
2725
2726 sc = ifp->if_softc;
2727
2728 if (ifp->if_flags & IFF_OACTIVE)
2729 return;
2730
2731 idx = sc->xl_cdata.xl_tx_prod;
2732 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2733
2734 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2735
2736 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2737 ifp->if_flags |= IFF_OACTIVE;
2738 break;
2739 }
2740
2741 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2742 if (m_head == NULL)
2743 break;
2744
2745 prev_tx = cur_tx;
2746 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2747
2748 /* Pack the data into the descriptor. */
2749 error = xl_encap(sc, cur_tx, m_head);
2750 if (error) {
2751 cur_tx = prev_tx;
2752 continue;
2753 }
2754
2755 /* Chain it together. */
2756 if (prev != NULL)
2757 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2758 prev = cur_tx;
2759
2760 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2761
2762 XL_INC(idx, XL_TX_LIST_CNT);
2763 sc->xl_cdata.xl_tx_cnt++;
2764 }
2765
2766 /*
2767 * If there are no packets queued, bail.
2768 */
2769 if (cur_tx == NULL)
2770 return;
2771
2772 /*
2773 * Place the request for the upload interrupt
2774 * in the last descriptor in the chain. This way, if
2775 * we're chaining several packets at once, we'll only
2776 * get an interupt once for the whole chain rather than
2777 * once for each packet.
2778 */
2779 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2780 XL_TXSTAT_DL_INTR);
2781
2782 /* Start transmission */
2783 sc->xl_cdata.xl_tx_prod = idx;
2784 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2785
2786 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2787 BUS_DMASYNC_PREWRITE);
2788
2789 /*
2790 * Set a timeout in case the chip goes out to lunch.
2791 */
2792 ifp->if_timer = 5;
2793 }
2794
2795 static void
2796 xl_init(void *xsc)
2797 {
2798 struct xl_softc *sc = xsc;
2799 struct ifnet *ifp = &sc->arpcom.ac_if;
2800 int error, i;
2801 u_int16_t rxfilt = 0;
2802 struct mii_data *mii = NULL;
2803
2804 /*
2805 * Cancel pending I/O and free all RX/TX buffers.
2806 */
2807 xl_stop(sc);
2808
2809 if (sc->xl_miibus == NULL) {
2810 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2811 xl_wait(sc);
2812 }
2813 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2814 xl_wait(sc);
2815 DELAY(10000);
2816
2817 if (sc->xl_miibus != NULL)
2818 mii = device_get_softc(sc->xl_miibus);
2819
2820 /* Init our MAC address */
2821 XL_SEL_WIN(2);
2822 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2823 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2824 sc->arpcom.ac_enaddr[i]);
2825 }
2826
2827 /* Clear the station mask. */
2828 for (i = 0; i < 3; i++)
2829 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2830 #ifdef notdef
2831 /* Reset TX and RX. */
2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2833 xl_wait(sc);
2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2835 xl_wait(sc);
2836 #endif
2837 /* Init circular RX list. */
2838 error = xl_list_rx_init(sc);
2839 if (error) {
2840 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2841 error);
2842 xl_stop(sc);
2843 return;
2844 }
2845
2846 /* Init TX descriptors. */
2847 if (sc->xl_type == XL_TYPE_905B)
2848 xl_list_tx_init_90xB(sc);
2849 else
2850 xl_list_tx_init(sc);
2851
2852 /*
2853 * Set the TX freethresh value.
2854 * Note that this has no effect on 3c905B "cyclone"
2855 * cards but is required for 3c900/3c905 "boomerang"
2856 * cards in order to enable the download engine.
2857 */
2858 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2859
2860 /* Set the TX start threshold for best performance. */
2861 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2862 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2863
2864 /*
2865 * If this is a 3c905B, also set the tx reclaim threshold.
2866 * This helps cut down on the number of tx reclaim errors
2867 * that could happen on a busy network. The chip multiplies
2868 * the register value by 16 to obtain the actual threshold
2869 * in bytes, so we divide by 16 when setting the value here.
2870 * The existing threshold value can be examined by reading
2871 * the register at offset 9 in window 5.
2872 */
2873 if (sc->xl_type == XL_TYPE_905B) {
2874 CSR_WRITE_2(sc, XL_COMMAND,
2875 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2876 }
2877
2878 /* Set RX filter bits. */
2879 XL_SEL_WIN(5);
2880 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2881
2882 /* Set the individual bit to receive frames for this host only. */
2883 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2884
2885 /* If we want promiscuous mode, set the allframes bit. */
2886 if (ifp->if_flags & IFF_PROMISC) {
2887 rxfilt |= XL_RXFILTER_ALLFRAMES;
2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2889 } else {
2890 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2892 }
2893
2894 /*
2895 * Set capture broadcast bit to capture broadcast frames.
2896 */
2897 if (ifp->if_flags & IFF_BROADCAST) {
2898 rxfilt |= XL_RXFILTER_BROADCAST;
2899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2900 } else {
2901 rxfilt &= ~XL_RXFILTER_BROADCAST;
2902 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2903 }
2904
2905 /*
2906 * Program the multicast filter, if necessary.
2907 */
2908 if (sc->xl_type == XL_TYPE_905B)
2909 xl_setmulti_hash(sc);
2910 else
2911 xl_setmulti(sc);
2912
2913 if (sc->xl_type == XL_TYPE_905B) {
2914 /* Set UP polling interval */
2915 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2916 }
2917
2918 /*
2919 * Load the address of the RX list. We have to
2920 * stall the upload engine before we can manipulate
2921 * the uplist pointer register, then unstall it when
2922 * we're finished. We also have to wait for the
2923 * stall command to complete before proceeding.
2924 * Note that we have to do this after any RX resets
2925 * have completed since the uplist register is cleared
2926 * by a reset.
2927 */
2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2929 xl_wait(sc);
2930 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2931 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2932 xl_wait(sc);
2933
2934 if (sc->xl_type == XL_TYPE_905B) {
2935 /* Set DN polling interval */
2936 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2937
2938 /* Load the address of the TX list */
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2940 xl_wait(sc);
2941 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2942 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2943 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2944 xl_wait(sc);
2945 }
2946
2947 /*
2948 * If the coax transceiver is on, make sure to enable
2949 * the DC-DC converter.
2950 */
2951 XL_SEL_WIN(3);
2952 if (sc->xl_xcvr == XL_XCVR_COAX)
2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2954 else
2955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2956
2957 /*
2958 * increase packet size to allow reception of 802.1q or ISL packets.
2959 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2960 * control register. For 3c90xB/C chips, use the RX packet size
2961 * register.
2962 */
2963
2964 if (sc->xl_type == XL_TYPE_905B) {
2965 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2966 } else {
2967 u_int8_t macctl;
2968 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2969 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2970 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2971 }
2972
2973 /* Clear out the stats counters. */
2974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2975 sc->xl_stats_no_timeout = 1;
2976 xl_stats_update_serialized(sc);
2977 sc->xl_stats_no_timeout = 0;
2978 XL_SEL_WIN(4);
2979 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2980 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2981
2982 /*
2983 * Enable interrupts.
2984 */
2985 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
2986 #ifdef DEVICE_POLLING
2987 /* Do not enable interrupt if polling(4) is enabled */
2988 if ((ifp->if_flags & IFF_POLLING) != 0)
2989 xl_enable_intrs(sc, 0);
2990 else
2991 #endif
2992 xl_enable_intrs(sc, XL_INTRS);
2993
2994 /* Set the RX early threshold */
2995 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2996 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2997
2998 /* Enable receiver and transmitter. */
2999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3000 xl_wait(sc);
3001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3002 xl_wait(sc);
3003
3004 if (mii != NULL)
3005 mii_mediachg(mii);
3006
3007 /* Select window 7 for normal operations. */
3008 XL_SEL_WIN(7);
3009
3010 ifp->if_flags |= IFF_RUNNING;
3011 ifp->if_flags &= ~IFF_OACTIVE;
3012
3013 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
3014 }
3015
3016 /*
3017 * Set media options.
3018 */
3019 static int
3020 xl_ifmedia_upd(struct ifnet *ifp)
3021 {
3022 struct xl_softc *sc;
3023 struct ifmedia *ifm = NULL;
3024 struct mii_data *mii = NULL;
3025
3026 sc = ifp->if_softc;
3027 if (sc->xl_miibus != NULL)
3028 mii = device_get_softc(sc->xl_miibus);
3029 if (mii == NULL)
3030 ifm = &sc->ifmedia;
3031 else
3032 ifm = &mii->mii_media;
3033
3034 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3035 case IFM_100_FX:
3036 case IFM_10_FL:
3037 case IFM_10_2:
3038 case IFM_10_5:
3039 xl_setmode(sc, ifm->ifm_media);
3040 return(0);
3041 break;
3042 default:
3043 break;
3044 }
3045
3046 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3047 || sc->xl_media & XL_MEDIAOPT_BT4) {
3048 xl_init(sc);
3049 } else {
3050 xl_setmode(sc, ifm->ifm_media);
3051 }
3052
3053 return(0);
3054 }
3055
3056 /*
3057 * Report current media status.
3058 */
3059 static void
3060 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3061 {
3062 struct xl_softc *sc;
3063 u_int32_t icfg;
3064 struct mii_data *mii = NULL;
3065
3066 sc = ifp->if_softc;
3067 if (sc->xl_miibus != NULL)
3068 mii = device_get_softc(sc->xl_miibus);
3069
3070 XL_SEL_WIN(3);
3071 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3072 icfg >>= XL_ICFG_CONNECTOR_BITS;
3073
3074 ifmr->ifm_active = IFM_ETHER;
3075
3076 switch(icfg) {
3077 case XL_XCVR_10BT:
3078 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3079 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3080 ifmr->ifm_active |= IFM_FDX;
3081 else
3082 ifmr->ifm_active |= IFM_HDX;
3083 break;
3084 case XL_XCVR_AUI:
3085 if (sc->xl_type == XL_TYPE_905B &&
3086 sc->xl_media == XL_MEDIAOPT_10FL) {
3087 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3088 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3089 ifmr->ifm_active |= IFM_FDX;
3090 else
3091 ifmr->ifm_active |= IFM_HDX;
3092 } else
3093 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3094 break;
3095 case XL_XCVR_COAX:
3096 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3097 break;
3098 /*
3099 * XXX MII and BTX/AUTO should be separate cases.
3100 */
3101
3102 case XL_XCVR_100BTX:
3103 case XL_XCVR_AUTO:
3104 case XL_XCVR_MII:
3105 if (mii != NULL) {
3106 mii_pollstat(mii);
3107 ifmr->ifm_active = mii->mii_media_active;
3108 ifmr->ifm_status = mii->mii_media_status;
3109 }
3110 break;
3111 case XL_XCVR_100BFX:
3112 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3113 break;
3114 default:
3115 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3116 break;
3117 }
3118
3119 return;
3120 }
3121
3122 static int
3123 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3124 {
3125 struct xl_softc *sc = ifp->if_softc;
3126 struct ifreq *ifr = (struct ifreq *) data;
3127 int error = 0;
3128 struct mii_data *mii = NULL;
3129 u_int8_t rxfilt;
3130
3131 switch(command) {
3132 case SIOCSIFFLAGS:
3133 XL_SEL_WIN(5);
3134 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3135 if (ifp->if_flags & IFF_UP) {
3136 if (ifp->if_flags & IFF_RUNNING &&
3137 ifp->if_flags & IFF_PROMISC &&
3138 !(sc->xl_if_flags & IFF_PROMISC)) {
3139 rxfilt |= XL_RXFILTER_ALLFRAMES;
3140 CSR_WRITE_2(sc, XL_COMMAND,
3141 XL_CMD_RX_SET_FILT|rxfilt);
3142 XL_SEL_WIN(7);
3143 } else if (ifp->if_flags & IFF_RUNNING &&
3144 !(ifp->if_flags & IFF_PROMISC) &&
3145 sc->xl_if_flags & IFF_PROMISC) {
3146 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3147 CSR_WRITE_2(sc, XL_COMMAND,
3148 XL_CMD_RX_SET_FILT|rxfilt);
3149 XL_SEL_WIN(7);
3150 } else
3151 xl_init(sc);
3152 } else {
3153 if (ifp->if_flags & IFF_RUNNING)
3154 xl_stop(sc);
3155 }
3156 sc->xl_if_flags = ifp->if_flags;
3157 error = 0;
3158 break;
3159 case SIOCADDMULTI:
3160 case SIOCDELMULTI:
3161 if (sc->xl_type == XL_TYPE_905B)
3162 xl_setmulti_hash(sc);
3163 else
3164 xl_setmulti(sc);
3165 error = 0;
3166 break;
3167 case SIOCGIFMEDIA:
3168 case SIOCSIFMEDIA:
3169 if (sc->xl_miibus != NULL)
3170 mii = device_get_softc(sc->xl_miibus);
3171 if (mii == NULL)
3172 error = ifmedia_ioctl(ifp, ifr,
3173 &sc->ifmedia, command);
3174 else
3175 error = ifmedia_ioctl(ifp, ifr,
3176 &mii->mii_media, command);
3177 break;
3178 case SIOCSIFCAP:
3179 ifp->if_capenable &= ~IFCAP_HWCSUM;
3180 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM);
3181 if (ifp->if_capenable & IFCAP_HWCSUM)
3182 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3183 else
3184 ifp->if_hwassist = 0;
3185 break;
3186 default:
3187 error = ether_ioctl(ifp, command, data);
3188 break;
3189 }
3190 return(error);
3191 }
3192
3193 static void
3194 xl_watchdog(struct ifnet *ifp)
3195 {
3196 struct xl_softc *sc;
3197 u_int16_t status = 0;
3198
3199 sc = ifp->if_softc;
3200
3201 ifp->if_oerrors++;
3202 XL_SEL_WIN(4);
3203 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3204 if_printf(ifp, "watchdog timeout\n");
3205
3206 if (status & XL_MEDIASTAT_CARRIER)
3207 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3208 xl_txeoc(sc);
3209 xl_txeof(sc);
3210 xl_rxeof(sc, -1);
3211 xl_reset(sc);
3212 xl_init(sc);
3213
3214 if (!ifq_is_empty(&ifp->if_snd))
3215 (*ifp->if_start)(ifp);
3216 }
3217
3218 /*
3219 * Stop the adapter and free any mbufs allocated to the
3220 * RX and TX lists.
3221 */
3222 static void
3223 xl_stop(struct xl_softc *sc)
3224 {
3225 int i;
3226 struct ifnet *ifp;
3227
3228 ifp = &sc->arpcom.ac_if;
3229 ifp->if_timer = 0;
3230
3231 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3233 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3235 xl_wait(sc);
3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3237 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3238 DELAY(800);
3239
3240 #ifdef foo
3241 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3242 xl_wait(sc);
3243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3244 xl_wait(sc);
3245 #endif
3246
3247 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3248 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3250 if (sc->xl_flags & XL_FLAG_FUNCREG)
3251 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3252
3253 /* Stop the stats updater. */
3254 callout_stop(&sc->xl_stat_timer);
3255
3256 /*
3257 * Free data in the RX lists.
3258 */
3259 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3260 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3261 bus_dmamap_unload(sc->xl_mtag,
3262 sc->xl_cdata.xl_rx_chain[i].xl_map);
3263 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3264 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3265 }
3266 }
3267 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3268
3269 /*
3270 * Free the TX list buffers.
3271 */
3272 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3273 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3274 bus_dmamap_unload(sc->xl_mtag,
3275 sc->xl_cdata.xl_tx_chain[i].xl_map);
3276 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3277 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3278 }
3279 }
3280 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3281
3282 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3283 }
3284
3285 /*
3286 * Stop all chip I/O so that the kernel's probe routines don't
3287 * get confused by errant DMAs when rebooting.
3288 */
3289 static void
3290 xl_shutdown(device_t dev)
3291 {
3292 struct xl_softc *sc = device_get_softc(dev);
3293
3294 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3295 xl_reset(sc);
3296 xl_stop(sc);
3297 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3298 }
3299
3300 static int
3301 xl_suspend(device_t dev)
3302 {
3303 struct xl_softc *sc = device_get_softc(dev);
3304
3305 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3306 xl_stop(sc);
3307 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3308
3309 return(0);
3310 }
3311
3312 static int
3313 xl_resume(device_t dev)
3314 {
3315 struct xl_softc *sc;
3316 struct ifnet *ifp;
3317
3318 sc = device_get_softc(dev);
3319 ifp = &sc->arpcom.ac_if;
3320
3321 lwkt_serialize_enter(ifp->if_serializer);
3322 xl_reset(sc);
3323 if (ifp->if_flags & IFF_UP)
3324 xl_init(sc);
3325 lwkt_serialize_exit(ifp->if_serializer);
3326
3327 return(0);
3328 }
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