sys/dev/netif/awi/am79c930reg.h

   1 /* $NetBSD: am79c930reg.h,v 1.3 2000/03/22 11:22:22 onoe Exp $ */
   2 /* $FreeBSD: src/sys/dev/awi/am79c930reg.h,v 1.1.2.1 2000/12/07 04:09:39 imp Exp $ */
   3 /* $DragonFly: src/sys/dev/netif/awi/am79c930reg.h,v 1.2 2003/06/17 04:28:22 dillon Exp $ */
   4
   5 /*-
   6  * Copyright (c) 1999 The NetBSD Foundation, Inc.
   7  * All rights reserved.
   8  *
   9  * This code is derived from software contributed to The NetBSD Foundation
  10  * by Bill Sommerfeld
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  * 3. All advertising materials mentioning features or use of this software
  21  *    must display the following acknowledgement:
  22  *        This product includes software developed by the NetBSD
  23  *        Foundation, Inc. and its contributors.
  24  * 4. Neither the name of The NetBSD Foundation nor the names of its
  25  *    contributors may be used to endorse or promote products derived
  26  *    from this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 /*
  42  * Device register definitions gleaned from from the AMD "Am79C930
  43  * PCnet(tm)-Mobile Single Chip Wireless LAN Media Access Controller"
  44  * data sheet, AMD Pub #20183, Rev B, amendment/0, issue date August 1997.
  45  *
  46  * As of 1999/10/23, this was available from AMD's web site in PDF
  47  * form.
  48  */
  49
  50
  51 /*
  52  * The 79c930 contains a bus interface unit, a media access
  53  * controller, and a tranceiver attachment interface.
  54  * The MAC contains an 80188 CPU core.
  55  * typical devices built around this chip typically add 32k or 64k of
  56  * memory for buffers.
  57  *
  58  * The 80188 runs firmware which handles most of the 802.11 gorp, and
  59  * communicates with the host using shared data structures in this
  60  * memory; the specifics of the shared memory layout are not covered
  61  * in this source file; see <dev/ic/am80211fw.h> for details of that layer.
  62  */
  63
  64 /*
  65  * Device Registers
  66  */
  67
  68 #define AM79C930_IO_BASE        0
  69 #define AM79C930_IO_SIZE        16
  70 #define AM79C930_IO_SIZE_BIG    40
  71 #define AM79C930_IO_ALIGN       0x40    /* am79c930 decodes lower 6bits */
  72
  73
  74 #define AM79C930_GCR    0       /* General Config Register */
  75
  76 #define AM79C930_GCR_SWRESET    0x80    /* software reset */
  77 #define AM79C930_GCR_CORESET    0x40    /* core reset */
  78 #define AM79C930_GCR_DISPWDN    0x20    /* disable powerdown */
  79 #define AM79C930_GCR_ECWAIT     0x10    /* embedded controller wait */
  80 #define AM79C930_GCR_ECINT      0x08    /* interrupt from embedded ctrlr */
  81 #define AM79C930_GCR_INT2EC     0x04    /* interrupt to embedded ctrlr */
  82 #define AM79C930_GCR_ENECINT    0x02    /* enable interrupts from e.c. */
  83 #define AM79C930_GCR_DAM        0x01    /* direct access mode (read only) */
  84
  85 #define AM79C930_GCR_BITS "\020\1DAM\2ENECINT\3INT2EC\4ECINT\5ECWAIT\6DISPWDN\7CORESET\010SWRESET"
  86
  87 #define AM79C930_BSS    1       /* Bank Switching Select register */
  88
  89 #define AM79C930_BSS_ECATR      0x80    /* E.C. ALE test read */
  90 #define AM79C930_BSS_FS         0x20    /* Flash Select */
  91 #define AM79C930_BSS_MBS        0x18    /* Memory Bank Select */
  92 #define AM79C930_BSS_EIOW       0x04    /* Expand I/O Window */
  93 #define AM79C930_BSS_TBS        0x03    /* TAI Bank Select */
  94
  95 #define AM79C930_LMA_LO 2       /* Local Memory Address register (low byte) */
  96
  97 #define AM79C930_LMA_HI 3       /* Local Memory Address register (high byte) */
  98
  99                                 /* set this bit to turn off ISAPnP version */
 100 #define AM79C930_LMA_HI_ISAPWRDWN       0x80
 101
 102 /*
 103  * mmm, inconsistancy in chip documentation:
 104  * According to page 79--80, all four of the following are equivalent
 105  * and address the single byte pointed at by BSS_{FS,MBS} | LMA_{HI,LO}
 106  * According to tables on p63 and p67, they're the LSB through MSB
 107  * of a 32-bit word.
 108  */
 109
 110 #define AM79C930_IODPA          4 /* I/O Data port A */
 111 #define AM79C930_IODPB          5 /* I/O Data port B */
 112 #define AM79C930_IODPC          6 /* I/O Data port C */
 113 #define AM79C930_IODPD          7 /* I/O Data port D */
 114
 115
 116 /*
 117  * Tranceiver Attachment Interface Registers (TIR space)
 118  * (omitted for now, since host access to them is for diagnostic
 119  * purposes only).
 120  */
 121
 122 /*
 123  * memory space goo.
 124  */
 125
 126 #define AM79C930_MEM_SIZE       0x8000           /* 32k */
 127 #define AM79C930_MEM_BASE       0x0              /* starting at 0 */