?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Explicitly initialize timedout_scb lists, use SCB_TAG for all access
[dragonfly/port-amd64.git] / sys / dev / disk / aic7xxx / aic79xx.c
blobd2561ba7c0587b1f02898059dd2cea624753d02f
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
41 *
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.35 2005/02/16 18:09:41 gibbs Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.c,v 1.25 2007/07/06 06:26:59 pavalos Exp $
44 */
45
46 #include "aic79xx_osm.h"
47 #include "aic79xx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
49
50 /******************************** Globals *************************************/
51 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
52 uint32_t ahd_attach_to_HostRAID_controllers = 1;
53
54 /***************************** Lookup Tables **********************************/
55 char *ahd_chip_names[] =
56 {
57 "NONE",
58 "aic7901",
59 "aic7902",
60 "aic7901A"
61 };
62 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
63
64 /*
65 * Hardware error codes.
66 */
67 struct ahd_hard_error_entry {
68 uint8_t error;
69 char *errmesg;
70 };
71
72 static struct ahd_hard_error_entry ahd_hard_errors[] = {
73 { DSCTMOUT, "Discard Timer has timed out" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" },
76 { DPARERR, "Data-path Parity Error" },
77 { MPARERR, "Scratch or SCB Memory Parity Error" },
78 { CIOPARERR, "CIOBUS Parity Error" },
79 };
80 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
81
82 static struct ahd_phase_table_entry ahd_phase_table[] =
83 {
84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
86 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
87 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
88 { P_COMMAND, MSG_NOOP, "in Command phase" },
89 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
90 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
91 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
92 { P_BUSFREE, MSG_NOOP, "while idle" },
93 { 0, MSG_NOOP, "in unknown phase" }
94 };
95
96 /*
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
99 */
100 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
101
102 /* Our Sequencer Program */
103 #include "aic79xx_seq.h"
104
105 /**************************** Function Declarations ***************************/
106 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
107 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
108 u_int lqistat1);
109 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
110 u_int busfreetime);
111 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
112 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
113 static void ahd_force_renegotiation(struct ahd_softc *ahd,
114 struct ahd_devinfo *devinfo);
115
116 static struct ahd_tmode_tstate*
117 ahd_alloc_tstate(struct ahd_softc *ahd,
118 u_int scsi_id, char channel);
119 #ifdef AHD_TARGET_MODE
120 static void ahd_free_tstate(struct ahd_softc *ahd,
121 u_int scsi_id, char channel, int force);
122 #endif
123 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
124 struct ahd_initiator_tinfo *,
125 u_int *period,
126 u_int *ppr_options,
127 role_t role);
128 static void ahd_update_neg_table(struct ahd_softc *ahd,
129 struct ahd_devinfo *devinfo,
130 struct ahd_transinfo *tinfo);
131 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
132 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
133 struct ahd_devinfo *devinfo);
134 static void ahd_scb_devinfo(struct ahd_softc *ahd,
135 struct ahd_devinfo *devinfo,
136 struct scb *scb);
137 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
138 struct ahd_devinfo *devinfo,
139 struct scb *scb);
140 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
141 struct ahd_devinfo *devinfo);
142 static void ahd_construct_sdtr(struct ahd_softc *ahd,
143 struct ahd_devinfo *devinfo,
144 u_int period, u_int offset);
145 static void ahd_construct_wdtr(struct ahd_softc *ahd,
146 struct ahd_devinfo *devinfo,
147 u_int bus_width);
148 static void ahd_construct_ppr(struct ahd_softc *ahd,
149 struct ahd_devinfo *devinfo,
150 u_int period, u_int offset,
151 u_int bus_width, u_int ppr_options);
152 static void ahd_clear_msg_state(struct ahd_softc *ahd);
153 static void ahd_handle_message_phase(struct ahd_softc *ahd);
154 typedef enum {
155 AHDMSG_1B,
156 AHDMSG_2B,
157 AHDMSG_EXT
158 } ahd_msgtype;
159 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
160 u_int msgval, int full);
161 static int ahd_parse_msg(struct ahd_softc *ahd,
162 struct ahd_devinfo *devinfo);
163 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
164 struct ahd_devinfo *devinfo);
165 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
166 struct ahd_devinfo *devinfo);
167 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
168 static void ahd_handle_devreset(struct ahd_softc *ahd,
169 struct ahd_devinfo *devinfo,
170 u_int lun, cam_status status,
171 char *message, int verbose_level);
172 #if AHD_TARGET_MODE
173 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
174 struct ahd_devinfo *devinfo,
175 struct scb *scb);
176 #endif
177
178 static u_int ahd_sglist_size(struct ahd_softc *ahd);
179 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
180 static bus_dmamap_callback_t
181 ahd_dmamap_cb;
182 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
183 static int ahd_init_scbdata(struct ahd_softc *ahd);
184 static void ahd_fini_scbdata(struct ahd_softc *ahd);
185 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
186 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
187 static void ahd_add_col_list(struct ahd_softc *ahd,
188 struct scb *scb, u_int col_idx);
189 static void ahd_rem_col_list(struct ahd_softc *ahd,
190 struct scb *scb);
191 static void ahd_chip_init(struct ahd_softc *ahd);
192 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
193 struct scb *prev_scb,
194 struct scb *scb);
195 static int ahd_qinfifo_count(struct ahd_softc *ahd);
196 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
197 char channel, int lun, u_int tag,
198 role_t role, uint32_t status,
199 ahd_search_action action,
200 u_int *list_head, u_int *list_tail,
201 u_int tid);
202 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
203 u_int tid_prev, u_int tid_cur,
204 u_int tid_next);
205 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
206 u_int scbid);
207 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
208 u_int prev, u_int next, u_int tid);
209 static void ahd_reset_current_bus(struct ahd_softc *ahd);
210 static ahd_callback_t ahd_reset_poll;
211 static ahd_callback_t ahd_stat_timer;
212 #ifdef AHD_DUMP_SEQ
213 static void ahd_dumpseq(struct ahd_softc *ahd);
214 #endif
215 static void ahd_loadseq(struct ahd_softc *ahd);
216 static int ahd_check_patch(struct ahd_softc *ahd,
217 struct patch **start_patch,
218 u_int start_instr, u_int *skip_addr);
219 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
220 u_int address);
221 static void ahd_download_instr(struct ahd_softc *ahd,
222 u_int instrptr, uint8_t *dconsts);
223 static int ahd_probe_stack_size(struct ahd_softc *ahd);
224 static int ahd_other_scb_timeout(struct ahd_softc *ahd,
225 struct scb *scb,
226 struct scb *other_scb);
227 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
228 struct scb *scb);
229 static void ahd_run_data_fifo(struct ahd_softc *ahd,
230 struct scb *scb);
231
232 #ifdef AHD_TARGET_MODE
233 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
234 struct ahd_tmode_lstate *lstate,
235 u_int initiator_id,
236 u_int event_type,
237 u_int event_arg);
238 static void ahd_update_scsiid(struct ahd_softc *ahd,
239 u_int targid_mask);
240 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
241 struct target_cmd *cmd);
242 #endif
243
244 /******************************** Private Inlines *****************************/
245 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
246 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
247 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
248
249 static __inline void
250 ahd_assert_atn(struct ahd_softc *ahd)
251 {
252 ahd_outb(ahd, SCSISIGO, ATNO);
253 }
254
255 /*
256 * Determine if the current connection has a packetized
257 * agreement. This does not necessarily mean that we
258 * are currently in a packetized transfer. We could
259 * just as easily be sending or receiving a message.
260 */
261 static __inline int
262 ahd_currently_packetized(struct ahd_softc *ahd)
263 {
264 ahd_mode_state saved_modes;
265 int packetized;
266
267 saved_modes = ahd_save_modes(ahd);
268 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
269 /*
270 * The packetized bit refers to the last
271 * connection, not the current one. Check
272 * for non-zero LQISTATE instead.
273 */
274 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
275 packetized = ahd_inb(ahd, LQISTATE) != 0;
276 } else {
277 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
278 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
279 }
280 ahd_restore_modes(ahd, saved_modes);
281 return (packetized);
282 }
283
284 static __inline int
285 ahd_set_active_fifo(struct ahd_softc *ahd)
286 {
287 u_int active_fifo;
288
289 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
290 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
291 switch (active_fifo) {
292 case 0:
293 case 1:
294 ahd_set_modes(ahd, active_fifo, active_fifo);
295 return (1);
296 default:
297 return (0);
298 }
299 }
300
301 /************************* Sequencer Execution Control ************************/
302 /*
303 * Restart the sequencer program from address zero
304 */
305 void
306 ahd_restart(struct ahd_softc *ahd)
307 {
308
309 ahd_pause(ahd);
310
311 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
312
313 /* No more pending messages */
314 ahd_clear_msg_state(ahd);
315 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
316 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
317 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
318 ahd_outb(ahd, SEQINTCTL, 0);
319 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
320 ahd_outb(ahd, SEQ_FLAGS, 0);
321 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
322 ahd_outb(ahd, SAVED_LUN, 0xFF);
323
324 /*
325 * Ensure that the sequencer's idea of TQINPOS
326 * matches our own. The sequencer increments TQINPOS
327 * only after it sees a DMA complete and a reset could
328 * occur before the increment leaving the kernel to believe
329 * the command arrived but the sequencer to not.
330 */
331 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
332
333 /* Always allow reselection */
334 ahd_outb(ahd, SCSISEQ1,
335 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
336 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
337
338 /*
339 * Clear any pending sequencer interrupt. It is no
340 * longer relevant since we're resetting the Program
341 * Counter.
342 */
343 ahd_outb(ahd, CLRINT, CLRSEQINT);
344
345 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
346 ahd_unpause(ahd);
347 }
348
349 void
350 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
351 {
352 ahd_mode_state saved_modes;
353
354 #ifdef AHD_DEBUG
355 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
356 kprintf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
357 #endif
358 saved_modes = ahd_save_modes(ahd);
359 ahd_set_modes(ahd, fifo, fifo);
360 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
361 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
362 ahd_outb(ahd, CCSGCTL, CCSGRESET);
363 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
364 ahd_outb(ahd, SG_STATE, 0);
365 ahd_restore_modes(ahd, saved_modes);
366 }
367
368 /************************* Input/Output Queues ********************************/
369 /*
370 * Flush and completed commands that are sitting in the command
371 * complete queues down on the chip but have yet to be dma'ed back up.
372 */
373 void
374 ahd_flush_qoutfifo(struct ahd_softc *ahd)
375 {
376 struct scb *scb;
377 ahd_mode_state saved_modes;
378 u_int saved_scbptr;
379 u_int ccscbctl;
380 u_int scbid;
381 u_int next_scbid;
382
383 saved_modes = ahd_save_modes(ahd);
384
385 /*
386 * Flush the good status FIFO for completed packetized commands.
387 */
388 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
389 saved_scbptr = ahd_get_scbptr(ahd);
390 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
391 u_int fifo_mode;
392 u_int i;
393
394 scbid = ahd_inw(ahd, GSFIFO);
395 scb = ahd_lookup_scb(ahd, scbid);
396 if (scb == NULL) {
397 kprintf("%s: Warning - GSFIFO SCB %d invalid\n",
398 ahd_name(ahd), scbid);
399 continue;
400 }
401 /*
402 * Determine if this transaction is still active in
403 * any FIFO. If it is, we must flush that FIFO to
404 * the host before completing the command.
405 */
406 fifo_mode = 0;
407 rescan_fifos:
408 for (i = 0; i < 2; i++) {
409 /* Toggle to the other mode. */
410 fifo_mode ^= 1;
411 ahd_set_modes(ahd, fifo_mode, fifo_mode);
412
413 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
414 continue;
415
416 ahd_run_data_fifo(ahd, scb);
417
418 /*
419 * Running this FIFO may cause a CFG4DATA for
420 * this same transaction to assert in the other
421 * FIFO or a new snapshot SAVEPTRS interrupt
422 * in this FIFO. Even running a FIFO may not
423 * clear the transaction if we are still waiting
424 * for data to drain to the host. We must loop
425 * until the transaction is not active in either
426 * FIFO just to be sure. Reset our loop counter
427 * so we will visit both FIFOs again before
428 * declaring this transaction finished. We
429 * also delay a bit so that status has a chance
430 * to change before we look at this FIFO again.
431 */
432 aic_delay(200);
433 goto rescan_fifos;
434 }
435 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
436 ahd_set_scbptr(ahd, scbid);
437 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
438 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
439 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
440 & SG_LIST_NULL) != 0)) {
441 u_int comp_head;
442
443 /*
444 * The transfer completed with a residual.
445 * Place this SCB on the complete DMA list
446 * so that we update our in-core copy of the
447 * SCB before completing the command.
448 */
449 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
450 ahd_outb(ahd, SCB_SGPTR,
451 ahd_inb_scbram(ahd, SCB_SGPTR)
452 | SG_STATUS_VALID);
453 ahd_outw(ahd, SCB_TAG, scbid);
454 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
455 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
456 if (SCBID_IS_NULL(comp_head)) {
457 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
458 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
459 } else {
460 u_int tail;
461
462 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
463 ahd_set_scbptr(ahd, tail);
464 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
465 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
466 ahd_set_scbptr(ahd, scbid);
467 }
468 } else
469 ahd_complete_scb(ahd, scb);
470 }
471 ahd_set_scbptr(ahd, saved_scbptr);
472
473 /*
474 * Setup for command channel portion of flush.
475 */
476 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
477
478 /*
479 * Wait for any inprogress DMA to complete and clear DMA state
480 * if this if for an SCB in the qinfifo.
481 */
482 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
483
484 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
485 if ((ccscbctl & ARRDONE) != 0)
486 break;
487 } else if ((ccscbctl & CCSCBDONE) != 0)
488 break;
489 aic_delay(200);
490 }
491 /*
492 * We leave the sequencer to cleanup in the case of DMA's to
493 * update the qoutfifo. In all other cases (DMA's to the
494 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
495 * we disable the DMA engine so that the sequencer will not
496 * attempt to handle the DMA completion.
497 */
498 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
499 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
500
501 /*
502 * Complete any SCBs that just finished
503 * being DMA'ed into the qoutfifo.
504 */
505 ahd_run_qoutfifo(ahd);
506
507 saved_scbptr = ahd_get_scbptr(ahd);
508 /*
509 * Manually update/complete any completed SCBs that are waiting to be
510 * DMA'ed back up to the host.
511 */
512 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
513 while (!SCBID_IS_NULL(scbid)) {
514 uint8_t *hscb_ptr;
515 u_int i;
516
517 ahd_set_scbptr(ahd, scbid);
518 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
519 scb = ahd_lookup_scb(ahd, scbid);
520 if (scb == NULL) {
521 kprintf("%s: Warning - DMA-up and complete "
522 "SCB %d invalid\n", ahd_name(ahd), scbid);
523 continue;
524 }
525 hscb_ptr = (uint8_t *)scb->hscb;
526 for (i = 0; i < sizeof(struct hardware_scb); i++)
527 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
528
529 ahd_complete_scb(ahd, scb);
530 scbid = next_scbid;
531 }
532 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
533 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
534
535 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
536 while (!SCBID_IS_NULL(scbid)) {
537
538 ahd_set_scbptr(ahd, scbid);
539 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
540 scb = ahd_lookup_scb(ahd, scbid);
541 if (scb == NULL) {
542 kprintf("%s: Warning - Complete Qfrz SCB %d invalid\n",
543 ahd_name(ahd), scbid);
544 continue;
545 }
546
547 ahd_complete_scb(ahd, scb);
548 scbid = next_scbid;
549 }
550 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
551
552 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
553 while (!SCBID_IS_NULL(scbid)) {
554
555 ahd_set_scbptr(ahd, scbid);
556 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
557 scb = ahd_lookup_scb(ahd, scbid);
558 if (scb == NULL) {
559 kprintf("%s: Warning - Complete SCB %d invalid\n",
560 ahd_name(ahd), scbid);
561 continue;
562 }
563
564 ahd_complete_scb(ahd, scb);
565 scbid = next_scbid;
566 }
567 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
568
569 /*
570 * Restore state.
571 */
572 ahd_set_scbptr(ahd, saved_scbptr);
573 ahd_restore_modes(ahd, saved_modes);
574 ahd->flags |= AHD_UPDATE_PEND_CMDS;
575 }
576
577 /*
578 * Determine if an SCB for a packetized transaction
579 * is active in a FIFO.
580 */
581 static int
582 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
583 {
584
585 /*
586 * The FIFO is only active for our transaction if
587 * the SCBPTR matches the SCB's ID and the firmware
588 * has installed a handler for the FIFO or we have
589 * a pending SAVEPTRS or CFG4DATA interrupt.
590 */
591 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
592 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
593 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
594 return (0);
595
596 return (1);
597 }
598
599 /*
600 * Run a data fifo to completion for a transaction we know
601 * has completed across the SCSI bus (good status has been
602 * received). We are already set to the correct FIFO mode
603 * on entry to this routine.
604 *
605 * This function attempts to operate exactly as the firmware
606 * would when running this FIFO. Care must be taken to update
607 * this routine any time the firmware's FIFO algorithm is
608 * changed.
609 */
610 static void
611 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
612 {
613 u_int seqintsrc;
614
615 seqintsrc = ahd_inb(ahd, SEQINTSRC);
616 if ((seqintsrc & CFG4DATA) != 0) {
617 uint32_t datacnt;
618 uint32_t sgptr;
619
620 /*
621 * Clear full residual flag.
622 */
623 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
624 ahd_outb(ahd, SCB_SGPTR, sgptr);
625
626 /*
627 * Load datacnt and address.
628 */
629 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
630 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
631 sgptr |= LAST_SEG;
632 ahd_outb(ahd, SG_STATE, 0);
633 } else
634 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
635 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
636 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
637 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
638 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
639
640 /*
641 * Initialize Residual Fields.
642 */
643 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
644 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
645
646 /*
647 * Mark the SCB as having a FIFO in use.
648 */
649 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
650 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
651
652 /*
653 * Install a "fake" handler for this FIFO.
654 */
655 ahd_outw(ahd, LONGJMP_ADDR, 0);
656
657 /*
658 * Notify the hardware that we have satisfied
659 * this sequencer interrupt.
660 */
661 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
662 } else if ((seqintsrc & SAVEPTRS) != 0) {
663 uint32_t sgptr;
664 uint32_t resid;
665
666 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
667 /*
668 * Snapshot Save Pointers. All that
669 * is necessary to clear the snapshot
670 * is a CLRCHN.
671 */
672 goto clrchn;
673 }
674
675 /*
676 * Disable S/G fetch so the DMA engine
677 * is available to future users.
678 */
679 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
680 ahd_outb(ahd, CCSGCTL, 0);
681 ahd_outb(ahd, SG_STATE, 0);
682
683 /*
684 * Flush the data FIFO. Strickly only
685 * necessary for Rev A parts.
686 */
687 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
688
689 /*
690 * Calculate residual.
691 */
692 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
693 resid = ahd_inl(ahd, SHCNT);
694 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
695 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
696 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
697 /*
698 * Must back up to the correct S/G element.
699 * Typically this just means resetting our
700 * low byte to the offset in the SG_CACHE,
701 * but if we wrapped, we have to correct
702 * the other bytes of the sgptr too.
703 */
704 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
705 && (sgptr & 0x80) == 0)
706 sgptr -= 0x100;
707 sgptr &= ~0xFF;
708 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
709 & SG_ADDR_MASK;
710 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
711 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
712 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
713 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
714 sgptr | SG_LIST_NULL);
715 }
716 /*
717 * Save Pointers.
718 */
719 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
720 ahd_outl(ahd, SCB_DATACNT, resid);
721 ahd_outl(ahd, SCB_SGPTR, sgptr);
722 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
723 ahd_outb(ahd, SEQIMODE,
724 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
725 /*
726 * If the data is to the SCSI bus, we are
727 * done, otherwise wait for FIFOEMP.
728 */
729 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
730 goto clrchn;
731 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
732 uint32_t sgptr;
733 uint64_t data_addr;
734 uint32_t data_len;
735 u_int dfcntrl;
736
737 /*
738 * Disable S/G fetch so the DMA engine
739 * is available to future users. We won't
740 * be using the DMA engine to load segments.
741 */
742 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
743 ahd_outb(ahd, CCSGCTL, 0);
744 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
745 }
746
747 /*
748 * Wait for the DMA engine to notice that the
749 * host transfer is enabled and that there is
750 * space in the S/G FIFO for new segments before
751 * loading more segments.
752 */
753 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
754 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
755
756 /*
757 * Determine the offset of the next S/G
758 * element to load.
759 */
760 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
761 sgptr &= SG_PTR_MASK;
762 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
763 struct ahd_dma64_seg *sg;
764
765 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
766 data_addr = sg->addr;
767 data_len = sg->len;
768 sgptr += sizeof(*sg);
769 } else {
770 struct ahd_dma_seg *sg;
771
772 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
773 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
774 data_addr <<= 8;
775 data_addr |= sg->addr;
776 data_len = sg->len;
777 sgptr += sizeof(*sg);
778 }
779
780 /*
781 * Update residual information.
782 */
783 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
784 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
785
786 /*
787 * Load the S/G.
788 */
789 if (data_len & AHD_DMA_LAST_SEG) {
790 sgptr |= LAST_SEG;
791 ahd_outb(ahd, SG_STATE, 0);
792 }
793 ahd_outq(ahd, HADDR, data_addr);
794 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
795 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
796
797 /*
798 * Advertise the segment to the hardware.
799 */
800 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
801 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
802 /*
803 * Use SCSIENWRDIS so that SCSIEN
804 * is never modified by this
805 * operation.
806 */
807 dfcntrl |= SCSIENWRDIS;
808 }
809 ahd_outb(ahd, DFCNTRL, dfcntrl);
810 }
811 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
812
813 /*
814 * Transfer completed to the end of SG list
815 * and has flushed to the host.
816 */
817 ahd_outb(ahd, SCB_SGPTR,
818 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
819 goto clrchn;
820 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
821 clrchn:
822 /*
823 * Clear any handler for this FIFO, decrement
824 * the FIFO use count for the SCB, and release
825 * the FIFO.
826 */
827 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
828 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
829 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
830 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
831 }
832 }
833
834 /*
835 * Look for entries in the QoutFIFO that have completed.
836 * The valid_tag completion field indicates the validity
837 * of the entry - the valid value toggles each time through
838 * the queue. We use the sg_status field in the completion
839 * entry to avoid referencing the hscb if the completion
840 * occurred with no errors and no residual. sg_status is
841 * a copy of the first byte (little endian) of the sgptr
842 * hscb field.
843 */
844 void
845 ahd_run_qoutfifo(struct ahd_softc *ahd)
846 {
847 struct ahd_completion *completion;
848 struct scb *scb;
849 u_int scb_index;
850
851 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
852 panic("ahd_run_qoutfifo recursion");
853 ahd->flags |= AHD_RUNNING_QOUTFIFO;
854 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
855 for (;;) {
856 completion = &ahd->qoutfifo[ahd->qoutfifonext];
857
858 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
859 break;
860
861 scb_index = aic_le16toh(completion->tag);
862 scb = ahd_lookup_scb(ahd, scb_index);
863 if (scb == NULL) {
864 kprintf("%s: WARNING no command for scb %d "
865 "(cmdcmplt)\nQOUTPOS = %d\n",
866 ahd_name(ahd), scb_index,
867 ahd->qoutfifonext);
868 ahd_dump_card_state(ahd);
869 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
870 ahd_handle_scb_status(ahd, scb);
871 } else {
872 ahd_done(ahd, scb);
873 }
874
875 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
876 if (ahd->qoutfifonext == 0)
877 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
878 }
879 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
880 }
881
882 /************************* Interrupt Handling *********************************/
883 void
884 ahd_handle_hwerrint(struct ahd_softc *ahd)
885 {
886 /*
887 * Some catastrophic hardware error has occurred.
888 * Print it for the user and disable the controller.
889 */
890 int i;
891 int error;
892
893 error = ahd_inb(ahd, ERROR);
894 for (i = 0; i < num_errors; i++) {
895 if ((error & ahd_hard_errors[i].error) != 0)
896 kprintf("%s: hwerrint, %s\n",
897 ahd_name(ahd), ahd_hard_errors[i].errmesg);
898 }
899
900 ahd_dump_card_state(ahd);
901 panic("BRKADRINT");
902
903 /* Tell everyone that this HBA is no longer available */
904 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
905 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
906 CAM_NO_HBA);
907
908 /* Tell the system that this controller has gone away. */
909 ahd_free(ahd);
910 }
911
912 void
913 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
914 {
915 u_int seqintcode;
916
917 /*
918 * Save the sequencer interrupt code and clear the SEQINT
919 * bit. We will unpause the sequencer, if appropriate,
920 * after servicing the request.
921 */
922 seqintcode = ahd_inb(ahd, SEQINTCODE);
923 ahd_outb(ahd, CLRINT, CLRSEQINT);
924 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
925 /*
926 * Unpause the sequencer and let it clear
927 * SEQINT by writing NO_SEQINT to it. This
928 * will cause the sequencer to be paused again,
929 * which is the expected state of this routine.
930 */
931 ahd_unpause(ahd);
932 while (!ahd_is_paused(ahd))
933 ;
934 ahd_outb(ahd, CLRINT, CLRSEQINT);
935 }
936 ahd_update_modes(ahd);
937 #ifdef AHD_DEBUG
938 if ((ahd_debug & AHD_SHOW_MISC) != 0)
939 kprintf("%s: Handle Seqint Called for code %d\n",
940 ahd_name(ahd), seqintcode);
941 #endif
942 switch (seqintcode) {
943 case ENTERING_NONPACK:
944 {
945 struct scb *scb;
946 u_int scbid;
947
948 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
949 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
950 scbid = ahd_get_scbptr(ahd);
951 scb = ahd_lookup_scb(ahd, scbid);
952 if (scb == NULL) {
953 /*
954 * Somehow need to know if this
955 * is from a selection or reselection.
956 * From that, we can determine target
957 * ID so we at least have an I_T nexus.
958 */
959 } else {
960 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
961 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
962 ahd_outb(ahd, SEQ_FLAGS, 0x0);
963 }
964 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
965 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
966 /*
967 * Phase change after read stream with
968 * CRC error with P0 asserted on last
969 * packet.
970 */
971 #ifdef AHD_DEBUG
972 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
973 kprintf("%s: Assuming LQIPHASE_NLQ with "
974 "P0 assertion\n", ahd_name(ahd));
975 #endif
976 }
977 #ifdef AHD_DEBUG
978 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
979 kprintf("%s: Entering NONPACK\n", ahd_name(ahd));
980 #endif
981 break;
982 }
983 case INVALID_SEQINT:
984 kprintf("%s: Invalid Sequencer interrupt occurred.\n",
985 ahd_name(ahd));
986 ahd_dump_card_state(ahd);
987 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
988 break;
989 case STATUS_OVERRUN:
990 {
991 struct scb *scb;
992 u_int scbid;
993
994 scbid = ahd_get_scbptr(ahd);
995 scb = ahd_lookup_scb(ahd, scbid);
996 if (scb != NULL)
997 ahd_print_path(ahd, scb);
998 else
999 kprintf("%s: ", ahd_name(ahd));
1000 kprintf("SCB %d Packetized Status Overrun", scbid);
1001 ahd_dump_card_state(ahd);
1002 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1003 break;
1004 }
1005 case CFG4ISTAT_INTR:
1006 {
1007 struct scb *scb;
1008 u_int scbid;
1009
1010 scbid = ahd_get_scbptr(ahd);
1011 scb = ahd_lookup_scb(ahd, scbid);
1012 if (scb == NULL) {
1013 ahd_dump_card_state(ahd);
1014 kprintf("CFG4ISTAT: Free SCB %d referenced", scbid);
1015 panic("For safety");
1016 }
1017 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1018 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1019 ahd_outb(ahd, HCNT + 2, 0);
1020 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1021 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1022 break;
1023 }
1024 case ILLEGAL_PHASE:
1025 {
1026 u_int bus_phase;
1027
1028 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1029 kprintf("%s: ILLEGAL_PHASE 0x%x\n",
1030 ahd_name(ahd), bus_phase);
1031
1032 switch (bus_phase) {
1033 case P_DATAOUT:
1034 case P_DATAIN:
1035 case P_DATAOUT_DT:
1036 case P_DATAIN_DT:
1037 case P_MESGOUT:
1038 case P_STATUS:
1039 case P_MESGIN:
1040 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1041 kprintf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1042 break;
1043 case P_COMMAND:
1044 {
1045 struct ahd_devinfo devinfo;
1046 struct scb *scb;
1047 struct ahd_initiator_tinfo *targ_info;
1048 struct ahd_tmode_tstate *tstate;
1049 struct ahd_transinfo *tinfo;
1050 u_int scbid;
1051
1052 /*
1053 * If a target takes us into the command phase
1054 * assume that it has been externally reset and
1055 * has thus lost our previous packetized negotiation
1056 * agreement. Since we have not sent an identify
1057 * message and may not have fully qualified the
1058 * connection, we change our command to TUR, assert
1059 * ATN and ABORT the task when we go to message in
1060 * phase. The OSM will see the REQUEUE_REQUEST
1061 * status and retry the command.
1062 */
1063 scbid = ahd_get_scbptr(ahd);
1064 scb = ahd_lookup_scb(ahd, scbid);
1065 if (scb == NULL) {
1066 kprintf("Invalid phase with no valid SCB. "
1067 "Resetting bus.\n");
1068 ahd_reset_channel(ahd, 'A',
1069 /*Initiate Reset*/TRUE);
1070 break;
1071 }
1072 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1073 SCB_GET_TARGET(ahd, scb),
1074 SCB_GET_LUN(scb),
1075 SCB_GET_CHANNEL(ahd, scb),
1076 ROLE_INITIATOR);
1077 targ_info = ahd_fetch_transinfo(ahd,
1078 devinfo.channel,
1079 devinfo.our_scsiid,
1080 devinfo.target,
1081 &tstate);
1082 tinfo = &targ_info->curr;
1083 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1084 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1085 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1086 /*offset*/0, /*ppr_options*/0,
1087 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1088 ahd_outb(ahd, SCB_CDB_STORE, 0);
1089 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1090 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1091 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1092 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1093 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1094 ahd_outb(ahd, SCB_CDB_LEN, 6);
1095 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1096 scb->hscb->control |= MK_MESSAGE;
1097 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1098 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1099 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1100 /*
1101 * The lun is 0, regardless of the SCB's lun
1102 * as we have not sent an identify message.
1103 */
1104 ahd_outb(ahd, SAVED_LUN, 0);
1105 ahd_outb(ahd, SEQ_FLAGS, 0);
1106 ahd_assert_atn(ahd);
1107 scb->flags &= ~SCB_PACKETIZED;
1108 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1109 ahd_freeze_devq(ahd, scb);
1110 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1111 aic_freeze_scb(scb);
1112
1113 /*
1114 * Allow the sequencer to continue with
1115 * non-pack processing.
1116 */
1117 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1118 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1119 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1120 ahd_outb(ahd, CLRLQOINT1, 0);
1121 }
1122 #ifdef AHD_DEBUG
1123 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1124 ahd_print_path(ahd, scb);
1125 kprintf("Unexpected command phase from "
1126 "packetized target\n");
1127 }
1128 #endif
1129 break;
1130 }
1131 }
1132 break;
1133 }
1134 case CFG4OVERRUN:
1135 {
1136 struct scb *scb;
1137 u_int scb_index;
1138
1139 #ifdef AHD_DEBUG
1140 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1141 kprintf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1142 ahd_inb(ahd, MODE_PTR));
1143 }
1144 #endif
1145 scb_index = ahd_get_scbptr(ahd);
1146 scb = ahd_lookup_scb(ahd, scb_index);
1147 if (scb == NULL) {
1148 /*
1149 * Attempt to transfer to an SCB that is
1150 * not outstanding.
1151 */
1152 ahd_assert_atn(ahd);
1153 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1154 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1155 ahd->msgout_len = 1;
1156 ahd->msgout_index = 0;
1157 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1158 /*
1159 * Clear status received flag to prevent any
1160 * attempt to complete this bogus SCB.
1161 */
1162 ahd_outb(ahd, SCB_CONTROL,
1163 ahd_inb_scbram(ahd, SCB_CONTROL)
1164 & ~STATUS_RCVD);
1165 }
1166 break;
1167 }
1168 case DUMP_CARD_STATE:
1169 {
1170 ahd_dump_card_state(ahd);
1171 break;
1172 }
1173 case PDATA_REINIT:
1174 {
1175 #ifdef AHD_DEBUG
1176 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1177 kprintf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1178 "SG_CACHE_SHADOW = 0x%x\n",
1179 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1180 ahd_inb(ahd, SG_CACHE_SHADOW));
1181 }
1182 #endif
1183 ahd_reinitialize_dataptrs(ahd);
1184 break;
1185 }
1186 case HOST_MSG_LOOP:
1187 {
1188 struct ahd_devinfo devinfo;
1189
1190 /*
1191 * The sequencer has encountered a message phase
1192 * that requires host assistance for completion.
1193 * While handling the message phase(s), we will be
1194 * notified by the sequencer after each byte is
1195 * transfered so we can track bus phase changes.
1196 *
1197 * If this is the first time we've seen a HOST_MSG_LOOP
1198 * interrupt, initialize the state of the host message
1199 * loop.
1200 */
1201 ahd_fetch_devinfo(ahd, &devinfo);
1202 if (ahd->msg_type == MSG_TYPE_NONE) {
1203 struct scb *scb;
1204 u_int scb_index;
1205 u_int bus_phase;
1206
1207 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1208 if (bus_phase != P_MESGIN
1209 && bus_phase != P_MESGOUT) {
1210 kprintf("ahd_intr: HOST_MSG_LOOP bad "
1211 "phase 0x%x\n", bus_phase);
1212 /*
1213 * Probably transitioned to bus free before
1214 * we got here. Just punt the message.
1215 */
1216 ahd_dump_card_state(ahd);
1217 ahd_clear_intstat(ahd);
1218 ahd_restart(ahd);
1219 return;
1220 }
1221
1222 scb_index = ahd_get_scbptr(ahd);
1223 scb = ahd_lookup_scb(ahd, scb_index);
1224 if (devinfo.role == ROLE_INITIATOR) {
1225 if (bus_phase == P_MESGOUT)
1226 ahd_setup_initiator_msgout(ahd,
1227 &devinfo,
1228 scb);
1229 else {
1230 ahd->msg_type =
1231 MSG_TYPE_INITIATOR_MSGIN;
1232 ahd->msgin_index = 0;
1233 }
1234 }
1235 #if AHD_TARGET_MODE
1236 else {
1237 if (bus_phase == P_MESGOUT) {
1238 ahd->msg_type =
1239 MSG_TYPE_TARGET_MSGOUT;
1240 ahd->msgin_index = 0;
1241 }
1242 else
1243 ahd_setup_target_msgin(ahd,
1244 &devinfo,
1245 scb);
1246 }
1247 #endif
1248 }
1249
1250 ahd_handle_message_phase(ahd);
1251 break;
1252 }
1253 case NO_MATCH:
1254 {
1255 /* Ensure we don't leave the selection hardware on */
1256 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1257 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1258
1259 kprintf("%s:%c:%d: no active SCB for reconnecting "
1260 "target - issuing BUS DEVICE RESET\n",
1261 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1262 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1263 "REG0 == 0x%x ACCUM = 0x%x\n",
1264 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1265 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1266 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1267 "SINDEX == 0x%x\n",
1268 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1269 ahd_find_busy_tcl(ahd,
1270 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1271 ahd_inb(ahd, SAVED_LUN))),
1272 ahd_inw(ahd, SINDEX));
1273 kprintf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1274 "SCB_CONTROL == 0x%x\n",
1275 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1276 ahd_inb_scbram(ahd, SCB_LUN),
1277 ahd_inb_scbram(ahd, SCB_CONTROL));
1278 kprintf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1279 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1280 kprintf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1281 kprintf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1282 ahd_dump_card_state(ahd);
1283 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1284 ahd->msgout_len = 1;
1285 ahd->msgout_index = 0;
1286 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1287 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1288 ahd_assert_atn(ahd);
1289 break;
1290 }
1291 case PROTO_VIOLATION:
1292 {
1293 ahd_handle_proto_violation(ahd);
1294 break;
1295 }
1296 case IGN_WIDE_RES:
1297 {
1298 struct ahd_devinfo devinfo;
1299
1300 ahd_fetch_devinfo(ahd, &devinfo);
1301 ahd_handle_ign_wide_residue(ahd, &devinfo);
1302 break;
1303 }
1304 case BAD_PHASE:
1305 {
1306 u_int lastphase;
1307
1308 lastphase = ahd_inb(ahd, LASTPHASE);
1309 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
1310 "lastphase = 0x%x. Attempting to continue\n",
1311 ahd_name(ahd), 'A',
1312 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1313 lastphase, ahd_inb(ahd, SCSISIGI));
1314 break;
1315 }
1316 case MISSED_BUSFREE:
1317 {
1318 u_int lastphase;
1319
1320 lastphase = ahd_inb(ahd, LASTPHASE);
1321 kprintf("%s:%c:%d: Missed busfree. "
1322 "Lastphase = 0x%x, Curphase = 0x%x\n",
1323 ahd_name(ahd), 'A',
1324 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1325 lastphase, ahd_inb(ahd, SCSISIGI));
1326 ahd_restart(ahd);
1327 return;
1328 }
1329 case DATA_OVERRUN:
1330 {
1331 /*
1332 * When the sequencer detects an overrun, it
1333 * places the controller in "BITBUCKET" mode
1334 * and allows the target to complete its transfer.
1335 * Unfortunately, none of the counters get updated
1336 * when the controller is in this mode, so we have
1337 * no way of knowing how large the overrun was.
1338 */
1339 struct scb *scb;
1340 u_int scbindex;
1341 #ifdef AHD_DEBUG
1342 u_int lastphase;
1343 #endif
1344
1345 scbindex = ahd_get_scbptr(ahd);
1346 scb = ahd_lookup_scb(ahd, scbindex);
1347 #ifdef AHD_DEBUG
1348 lastphase = ahd_inb(ahd, LASTPHASE);
1349 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1350 ahd_print_path(ahd, scb);
1351 kprintf("data overrun detected %s. Tag == 0x%x.\n",
1352 ahd_lookup_phase_entry(lastphase)->phasemsg,
1353 SCB_GET_TAG(scb));
1354 ahd_print_path(ahd, scb);
1355 kprintf("%s seen Data Phase. Length = %ld. "
1356 "NumSGs = %d.\n",
1357 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1358 ? "Have" : "Haven't",
1359 aic_get_transfer_length(scb), scb->sg_count);
1360 ahd_dump_sglist(scb);
1361 }
1362 #endif
1363
1364 /*
1365 * Set this and it will take effect when the
1366 * target does a command complete.
1367 */
1368 ahd_freeze_devq(ahd, scb);
1369 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1370 aic_freeze_scb(scb);
1371 break;
1372 }
1373 case MKMSG_FAILED:
1374 {
1375 struct ahd_devinfo devinfo;
1376 struct scb *scb;
1377 u_int scbid;
1378
1379 ahd_fetch_devinfo(ahd, &devinfo);
1380 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
1381 ahd_name(ahd), devinfo.channel, devinfo.target,
1382 devinfo.lun);
1383 scbid = ahd_get_scbptr(ahd);
1384 scb = ahd_lookup_scb(ahd, scbid);
1385 if (scb != NULL
1386 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1387 /*
1388 * Ensure that we didn't put a second instance of this
1389 * SCB into the QINFIFO.
1390 */
1391 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1392 SCB_GET_CHANNEL(ahd, scb),
1393 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1394 ROLE_INITIATOR, /*status*/0,
1395 SEARCH_REMOVE);
1396 ahd_outb(ahd, SCB_CONTROL,
1397 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1398 break;
1399 }
1400 case TASKMGMT_FUNC_COMPLETE:
1401 {
1402 u_int scbid;
1403 struct scb *scb;
1404
1405 scbid = ahd_get_scbptr(ahd);
1406 scb = ahd_lookup_scb(ahd, scbid);
1407 if (scb != NULL) {
1408 u_int lun;
1409 u_int tag;
1410 cam_status error;
1411
1412 ahd_print_path(ahd, scb);
1413 kprintf("Task Management Func 0x%x Complete\n",
1414 scb->hscb->task_management);
1415 lun = CAM_LUN_WILDCARD;
1416 tag = SCB_LIST_NULL;
1417
1418 switch (scb->hscb->task_management) {
1419 case SIU_TASKMGMT_ABORT_TASK:
1420 tag = SCB_GET_TAG(scb);
1421 case SIU_TASKMGMT_ABORT_TASK_SET:
1422 case SIU_TASKMGMT_CLEAR_TASK_SET:
1423 lun = scb->hscb->lun;
1424 error = CAM_REQ_ABORTED;
1425 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1426 'A', lun, tag, ROLE_INITIATOR,
1427 error);
1428 break;
1429 case SIU_TASKMGMT_LUN_RESET:
1430 lun = scb->hscb->lun;
1431 case SIU_TASKMGMT_TARGET_RESET:
1432 {
1433 struct ahd_devinfo devinfo;
1434
1435 ahd_scb_devinfo(ahd, &devinfo, scb);
1436 error = CAM_BDR_SENT;
1437 ahd_handle_devreset(ahd, &devinfo, lun,
1438 CAM_BDR_SENT,
1439 lun != CAM_LUN_WILDCARD
1440 ? "Lun Reset"
1441 : "Target Reset",
1442 /*verbose_level*/0);
1443 break;
1444 }
1445 default:
1446 panic("Unexpected TaskMgmt Func\n");
1447 break;
1448 }
1449 }
1450 break;
1451 }
1452 case TASKMGMT_CMD_CMPLT_OKAY:
1453 {
1454 u_int scbid;
1455 struct scb *scb;
1456
1457 /*
1458 * An ABORT TASK TMF failed to be delivered before
1459 * the targeted command completed normally.
1460 */
1461 scbid = ahd_get_scbptr(ahd);
1462 scb = ahd_lookup_scb(ahd, scbid);
1463 if (scb != NULL) {
1464 /*
1465 * Remove the second instance of this SCB from
1466 * the QINFIFO if it is still there.
1467 */
1468 ahd_print_path(ahd, scb);
1469 kprintf("SCB completes before TMF\n");
1470 /*
1471 * Handle losing the race. Wait until any
1472 * current selection completes. We will then
1473 * set the TMF back to zero in this SCB so that
1474 * the sequencer doesn't bother to issue another
1475 * sequencer interrupt for its completion.
1476 */
1477 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1478 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1479 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1480 ;
1481 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1482 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1483 SCB_GET_CHANNEL(ahd, scb),
1484 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1485 ROLE_INITIATOR, /*status*/0,
1486 SEARCH_REMOVE);
1487 }
1488 break;
1489 }
1490 case TRACEPOINT0:
1491 case TRACEPOINT1:
1492 case TRACEPOINT2:
1493 case TRACEPOINT3:
1494 kprintf("%s: Tracepoint %d\n", ahd_name(ahd),
1495 seqintcode - TRACEPOINT0);
1496 break;
1497 case NO_SEQINT:
1498 break;
1499 case SAW_HWERR:
1500 ahd_handle_hwerrint(ahd);
1501 break;
1502 default:
1503 kprintf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1504 seqintcode);
1505 break;
1506 }
1507 /*
1508 * The sequencer is paused immediately on
1509 * a SEQINT, so we should restart it when
1510 * we're done.
1511 */
1512 ahd_unpause(ahd);
1513 }
1514
1515 void
1516 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1517 {
1518 struct scb *scb;
1519 u_int status0;
1520 u_int status3;
1521 u_int status;
1522 u_int lqistat1;
1523 u_int lqostat0;
1524 u_int scbid;
1525 u_int busfreetime;
1526
1527 ahd_update_modes(ahd);
1528 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1529
1530 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1531 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1532 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1533 lqistat1 = ahd_inb(ahd, LQISTAT1);
1534 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1535 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1536 if ((status0 & (SELDI|SELDO)) != 0) {
1537 u_int simode0;
1538
1539 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1540 simode0 = ahd_inb(ahd, SIMODE0);
1541 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1542 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1543 }
1544 scbid = ahd_get_scbptr(ahd);
1545 scb = ahd_lookup_scb(ahd, scbid);
1546 if (scb != NULL
1547 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1548 scb = NULL;
1549
1550 if ((status0 & IOERR) != 0) {
1551 u_int now_lvd;
1552
1553 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1554 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1555 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1556 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1557 /*
1558 * A change in I/O mode is equivalent to a bus reset.
1559 */
1560 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1561 ahd_pause(ahd);
1562 ahd_setup_iocell_workaround(ahd);
1563 ahd_unpause(ahd);
1564 } else if ((status0 & OVERRUN) != 0) {
1565
1566 kprintf("%s: SCSI offset overrun detected. Resetting bus.\n",
1567 ahd_name(ahd));
1568 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1569 } else if ((status & SCSIRSTI) != 0) {
1570
1571 kprintf("%s: Someone reset channel A\n", ahd_name(ahd));
1572 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1573 } else if ((status & SCSIPERR) != 0) {
1574
1575 /* Make sure the sequencer is in a safe location. */
1576 ahd_clear_critical_section(ahd);
1577
1578 ahd_handle_transmission_error(ahd);
1579 } else if (lqostat0 != 0) {
1580
1581 kprintf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1582 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1583 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1584 ahd_outb(ahd, CLRLQOINT1, 0);
1585 } else if ((status & SELTO) != 0) {
1586 u_int scbid;
1587
1588 /* Stop the selection */
1589 ahd_outb(ahd, SCSISEQ0, 0);
1590
1591 /* Make sure the sequencer is in a safe location. */
1592 ahd_clear_critical_section(ahd);
1593
1594 /* No more pending messages */
1595 ahd_clear_msg_state(ahd);
1596
1597 /* Clear interrupt state */
1598 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1599
1600 /*
1601 * Although the driver does not care about the
1602 * 'Selection in Progress' status bit, the busy
1603 * LED does. SELINGO is only cleared by a successful
1604 * selection, so we must manually clear it to insure
1605 * the LED turns off just in case no future successful
1606 * selections occur (e.g. no devices on the bus).
1607 */
1608 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1609
1610 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1611 scb = ahd_lookup_scb(ahd, scbid);
1612 if (scb == NULL) {
1613 kprintf("%s: ahd_intr - referenced scb not "
1614 "valid during SELTO scb(0x%x)\n",
1615 ahd_name(ahd), scbid);
1616 ahd_dump_card_state(ahd);
1617 } else {
1618 struct ahd_devinfo devinfo;
1619 #ifdef AHD_DEBUG
1620 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1621 ahd_print_path(ahd, scb);
1622 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1623 scbid);
1624 }
1625 #endif
1626 ahd_scb_devinfo(ahd, &devinfo, scb);
1627 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1628 ahd_freeze_devq(ahd, scb);
1629
1630 /*
1631 * Cancel any pending transactions on the device
1632 * now that it seems to be missing. This will
1633 * also revert us to async/narrow transfers until
1634 * we can renegotiate with the device.
1635 */
1636 ahd_handle_devreset(ahd, &devinfo,
1637 CAM_LUN_WILDCARD,
1638 CAM_SEL_TIMEOUT,
1639 "Selection Timeout",
1640 /*verbose_level*/1);
1641 }
1642 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1643 ahd_iocell_first_selection(ahd);
1644 ahd_unpause(ahd);
1645 } else if ((status0 & (SELDI|SELDO)) != 0) {
1646
1647 ahd_iocell_first_selection(ahd);
1648 ahd_unpause(ahd);
1649 } else if (status3 != 0) {
1650 kprintf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1651 ahd_name(ahd), status3);
1652 ahd_outb(ahd, CLRSINT3, status3);
1653 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1654
1655 /* Make sure the sequencer is in a safe location. */
1656 ahd_clear_critical_section(ahd);
1657
1658 ahd_handle_lqiphase_error(ahd, lqistat1);
1659 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1660 /*
1661 * This status can be delayed during some
1662 * streaming operations. The SCSIPHASE
1663 * handler has already dealt with this case
1664 * so just clear the error.
1665 */
1666 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1667 } else if ((status & BUSFREE) != 0
1668 || (lqistat1 & LQOBUSFREE) != 0) {
1669 u_int lqostat1;
1670 int restart;
1671 int clear_fifo;
1672 int packetized;
1673 u_int mode;
1674
1675 /*
1676 * Clear our selection hardware as soon as possible.
1677 * We may have an entry in the waiting Q for this target,
1678 * that is affected by this busfree and we don't want to
1679 * go about selecting the target while we handle the event.
1680 */
1681 ahd_outb(ahd, SCSISEQ0, 0);
1682
1683 /* Make sure the sequencer is in a safe location. */
1684 ahd_clear_critical_section(ahd);
1685
1686 /*
1687 * Determine what we were up to at the time of
1688 * the busfree.
1689 */
1690 mode = AHD_MODE_SCSI;
1691 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1692 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1693 switch (busfreetime) {
1694 case BUSFREE_DFF0:
1695 case BUSFREE_DFF1:
1696 {
1697 u_int scbid;
1698 struct scb *scb;
1699
1700 mode = busfreetime == BUSFREE_DFF0
1701 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1702 ahd_set_modes(ahd, mode, mode);
1703 scbid = ahd_get_scbptr(ahd);
1704 scb = ahd_lookup_scb(ahd, scbid);
1705 if (scb == NULL) {
1706 kprintf("%s: Invalid SCB %d in DFF%d "
1707 "during unexpected busfree\n",
1708 ahd_name(ahd), scbid, mode);
1709 packetized = 0;
1710 } else
1711 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1712 clear_fifo = 1;
1713 break;
1714 }
1715 case BUSFREE_LQO:
1716 clear_fifo = 0;
1717 packetized = 1;
1718 break;
1719 default:
1720 clear_fifo = 0;
1721 packetized = (lqostat1 & LQOBUSFREE) != 0;
1722 if (!packetized
1723 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1724 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1725 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1726 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1727 /*
1728 * Assume packetized if we are not
1729 * on the bus in a non-packetized
1730 * capacity and any pending selection
1731 * was a packetized selection.
1732 */
1733 packetized = 1;
1734 break;
1735 }
1736
1737 #ifdef AHD_DEBUG
1738 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1739 kprintf("Saw Busfree. Busfreetime = 0x%x.\n",
1740 busfreetime);
1741 #endif
1742 /*
1743 * Busfrees that occur in non-packetized phases are
1744 * handled by the nonpkt_busfree handler.
1745 */
1746 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1747 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1748 } else {
1749 packetized = 0;
1750 restart = ahd_handle_nonpkt_busfree(ahd);
1751 }
1752 /*
1753 * Clear the busfree interrupt status. The setting of
1754 * the interrupt is a pulse, so in a perfect world, we
1755 * would not need to muck with the ENBUSFREE logic. This
1756 * would ensure that if the bus moves on to another
1757 * connection, busfree protection is still in force. If
1758 * BUSFREEREV is broken, however, we must manually clear
1759 * the ENBUSFREE if the busfree occurred during a non-pack
1760 * connection so that we don't get false positives during
1761 * future, packetized, connections.
1762 */
1763 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1764 if (packetized == 0
1765 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1766 ahd_outb(ahd, SIMODE1,
1767 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1768
1769 if (clear_fifo)
1770 ahd_clear_fifo(ahd, mode);
1771
1772 ahd_clear_msg_state(ahd);
1773 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1774 if (restart) {
1775 ahd_restart(ahd);
1776 } else {
1777 ahd_unpause(ahd);
1778 }
1779 } else {
1780 kprintf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1781 ahd_name(ahd), status);
1782 ahd_dump_card_state(ahd);
1783 ahd_clear_intstat(ahd);
1784 ahd_unpause(ahd);
1785 }
1786 }
1787
1788 static void
1789 ahd_handle_transmission_error(struct ahd_softc *ahd)
1790 {
1791 struct scb *scb;
1792 u_int scbid;
1793 u_int lqistat1;
1794 u_int lqistat2;
1795 u_int msg_out;
1796 u_int curphase;
1797 u_int lastphase;
1798 u_int perrdiag;
1799 u_int cur_col;
1800 int silent;
1801
1802 scb = NULL;
1803 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1804 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1805 lqistat2 = ahd_inb(ahd, LQISTAT2);
1806 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1807 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1808 u_int lqistate;
1809
1810 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1811 lqistate = ahd_inb(ahd, LQISTATE);
1812 if ((lqistate >= 0x1E && lqistate <= 0x24)
1813 || (lqistate == 0x29)) {
1814 #ifdef AHD_DEBUG
1815 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1816 kprintf("%s: NLQCRC found via LQISTATE\n",
1817 ahd_name(ahd));
1818 }
1819 #endif
1820 lqistat1 |= LQICRCI_NLQ;
1821 }
1822 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1823 }
1824
1825 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1826 lastphase = ahd_inb(ahd, LASTPHASE);
1827 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1828 perrdiag = ahd_inb(ahd, PERRDIAG);
1829 msg_out = MSG_INITIATOR_DET_ERR;
1830 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1831
1832 /*
1833 * Try to find the SCB associated with this error.
1834 */
1835 silent = FALSE;
1836 if (lqistat1 == 0
1837 || (lqistat1 & LQICRCI_NLQ) != 0) {
1838 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1839 ahd_set_active_fifo(ahd);
1840 scbid = ahd_get_scbptr(ahd);
1841 scb = ahd_lookup_scb(ahd, scbid);
1842 if (scb != NULL && SCB_IS_SILENT(scb))
1843 silent = TRUE;
1844 }
1845
1846 cur_col = 0;
1847 if (silent == FALSE) {
1848 kprintf("%s: Transmission error detected\n", ahd_name(ahd));
1849 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1850 ahd_lastphase_print(lastphase, &cur_col, 50);
1851 ahd_scsisigi_print(curphase, &cur_col, 50);
1852 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1853 kprintf("\n");
1854 ahd_dump_card_state(ahd);
1855 }
1856
1857 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1858 if (silent == FALSE) {
1859 kprintf("%s: Gross protocol error during incoming "
1860 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1861 ahd_name(ahd), lqistat1);
1862 }
1863 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1864 return;
1865 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1866 /*
1867 * A CRC error has been detected on an incoming LQ.
1868 * The bus is currently hung on the last ACK.
1869 * Hit LQIRETRY to release the last ack, and
1870 * wait for the sequencer to determine that ATNO
1871 * is asserted while in message out to take us
1872 * to our host message loop. No NONPACKREQ or
1873 * LQIPHASE type errors will occur in this
1874 * scenario. After this first LQIRETRY, the LQI
1875 * manager will be in ISELO where it will
1876 * happily sit until another packet phase begins.
1877 * Unexpected bus free detection is enabled
1878 * through any phases that occur after we release
1879 * this last ack until the LQI manager sees a
1880 * packet phase. This implies we may have to
1881 * ignore a perfectly valid "unexected busfree"
1882 * after our "initiator detected error" message is
1883 * sent. A busfree is the expected response after
1884 * we tell the target that it's L_Q was corrupted.
1885 * (SPI4R09 10.7.3.3.3)
1886 */
1887 ahd_outb(ahd, LQCTL2, LQIRETRY);
1888 kprintf("LQIRetry for LQICRCI_LQ to release ACK\n");
1889 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1890 /*
1891 * We detected a CRC error in a NON-LQ packet.
1892 * The hardware has varying behavior in this situation
1893 * depending on whether this packet was part of a
1894 * stream or not.
1895 *
1896 * PKT by PKT mode:
1897 * The hardware has already acked the complete packet.
1898 * If the target honors our outstanding ATN condition,
1899 * we should be (or soon will be) in MSGOUT phase.
1900 * This will trigger the LQIPHASE_LQ status bit as the
1901 * hardware was expecting another LQ. Unexpected
1902 * busfree detection is enabled. Once LQIPHASE_LQ is
1903 * true (first entry into host message loop is much
1904 * the same), we must clear LQIPHASE_LQ and hit
1905 * LQIRETRY so the hardware is ready to handle
1906 * a future LQ. NONPACKREQ will not be asserted again
1907 * once we hit LQIRETRY until another packet is
1908 * processed. The target may either go busfree
1909 * or start another packet in response to our message.
1910 *
1911 * Read Streaming P0 asserted:
1912 * If we raise ATN and the target completes the entire
1913 * stream (P0 asserted during the last packet), the
1914 * hardware will ack all data and return to the ISTART
1915 * state. When the target reponds to our ATN condition,
1916 * LQIPHASE_LQ will be asserted. We should respond to
1917 * this with an LQIRETRY to prepare for any future
1918 * packets. NONPACKREQ will not be asserted again
1919 * once we hit LQIRETRY until another packet is
1920 * processed. The target may either go busfree or
1921 * start another packet in response to our message.
1922 * Busfree detection is enabled.
1923 *
1924 * Read Streaming P0 not asserted:
1925 * If we raise ATN and the target transitions to
1926 * MSGOUT in or after a packet where P0 is not
1927 * asserted, the hardware will assert LQIPHASE_NLQ.
1928 * We should respond to the LQIPHASE_NLQ with an
1929 * LQIRETRY. Should the target stay in a non-pkt
1930 * phase after we send our message, the hardware
1931 * will assert LQIPHASE_LQ. Recovery is then just as
1932 * listed above for the read streaming with P0 asserted.
1933 * Busfree detection is enabled.
1934 */
1935 if (silent == FALSE)
1936 kprintf("LQICRC_NLQ\n");
1937 if (scb == NULL) {
1938 kprintf("%s: No SCB valid for LQICRC_NLQ. "
1939 "Resetting bus\n", ahd_name(ahd));
1940 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1941 return;
1942 }
1943 } else if ((lqistat1 & LQIBADLQI) != 0) {
1944 kprintf("Need to handle BADLQI!\n");
1945 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1946 return;
1947 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1948 if ((curphase & ~P_DATAIN_DT) != 0) {
1949 /* Ack the byte. So we can continue. */
1950 if (silent == FALSE)
1951 kprintf("Acking %s to clear perror\n",
1952 ahd_lookup_phase_entry(curphase)->phasemsg);
1953 ahd_inb(ahd, SCSIDAT);
1954 }
1955
1956 if (curphase == P_MESGIN)
1957 msg_out = MSG_PARITY_ERROR;
1958 }
1959
1960 /*
1961 * We've set the hardware to assert ATN if we
1962 * get a parity error on "in" phases, so all we
1963 * need to do is stuff the message buffer with
1964 * the appropriate message. "In" phases have set
1965 * mesg_out to something other than MSG_NOP.
1966 */
1967 ahd->send_msg_perror = msg_out;
1968 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1969 scb->flags |= SCB_TRANSMISSION_ERROR;
1970 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1971 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1972 ahd_unpause(ahd);
1973 }
1974
1975 static void
1976 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1977 {
1978 /*
1979 * Clear the sources of the interrupts.
1980 */
1981 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1982 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1983
1984 /*
1985 * If the "illegal" phase changes were in response
1986 * to our ATN to flag a CRC error, AND we ended up
1987 * on packet boundaries, clear the error, restart the
1988 * LQI manager as appropriate, and go on our merry
1989 * way toward sending the message. Otherwise, reset
1990 * the bus to clear the error.
1991 */
1992 ahd_set_active_fifo(ahd);
1993 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1994 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
1995 if ((lqistat1 & LQIPHASE_LQ) != 0) {
1996 kprintf("LQIRETRY for LQIPHASE_LQ\n");
1997 ahd_outb(ahd, LQCTL2, LQIRETRY);
1998 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
1999 kprintf("LQIRETRY for LQIPHASE_NLQ\n");
2000 ahd_outb(ahd, LQCTL2, LQIRETRY);
2001 } else
2002 panic("ahd_handle_lqiphase_error: No phase errors\n");
2003 ahd_dump_card_state(ahd);
2004 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2005 ahd_unpause(ahd);
2006 } else {
2007 kprintf("Reseting Channel for LQI Phase error\n");
2008 ahd_dump_card_state(ahd);
2009 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2010 }
2011 }
2012
2013 /*
2014 * Packetized unexpected or expected busfree.
2015 * Entered in mode based on busfreetime.
2016 */
2017 static int
2018 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2019 {
2020 u_int lqostat1;
2021
2022 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2023 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2024 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2025 if ((lqostat1 & LQOBUSFREE) != 0) {
2026 struct scb *scb;
2027 u_int scbid;
2028 u_int saved_scbptr;
2029 u_int waiting_h;
2030 u_int waiting_t;
2031 u_int next;
2032
2033 /*
2034 * The LQO manager detected an unexpected busfree
2035 * either:
2036 *
2037 * 1) During an outgoing LQ.
2038 * 2) After an outgoing LQ but before the first
2039 * REQ of the command packet.
2040 * 3) During an outgoing command packet.
2041 *
2042 * In all cases, CURRSCB is pointing to the
2043 * SCB that encountered the failure. Clean
2044 * up the queue, clear SELDO and LQOBUSFREE,
2045 * and allow the sequencer to restart the select
2046 * out at its lesure.
2047 */
2048 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2049 scbid = ahd_inw(ahd, CURRSCB);
2050 scb = ahd_lookup_scb(ahd, scbid);
2051 if (scb == NULL)
2052 panic("SCB not valid during LQOBUSFREE");
2053 /*
2054 * Clear the status.
2055 */
2056 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2057 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2058 ahd_outb(ahd, CLRLQOINT1, 0);
2059 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2060 ahd_flush_device_writes(ahd);
2061 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2062
2063 /*
2064 * Return the LQO manager to its idle loop. It will
2065 * not do this automatically if the busfree occurs
2066 * after the first REQ of either the LQ or command
2067 * packet or between the LQ and command packet.
2068 */
2069 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2070
2071 /*
2072 * Update the waiting for selection queue so
2073 * we restart on the correct SCB.
2074 */
2075 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2076 saved_scbptr = ahd_get_scbptr(ahd);
2077 if (waiting_h != scbid) {
2078
2079 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2080 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2081 if (waiting_t == waiting_h) {
2082 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2083 next = SCB_LIST_NULL;
2084 } else {
2085 ahd_set_scbptr(ahd, waiting_h);
2086 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2087 }
2088 ahd_set_scbptr(ahd, scbid);
2089 ahd_outw(ahd, SCB_NEXT2, next);
2090 }
2091 ahd_set_scbptr(ahd, saved_scbptr);
2092 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2093 if (SCB_IS_SILENT(scb) == FALSE) {
2094 ahd_print_path(ahd, scb);
2095 kprintf("Probable outgoing LQ CRC error. "
2096 "Retrying command\n");
2097 }
2098 scb->crc_retry_count++;
2099 } else {
2100 aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2101 aic_freeze_scb(scb);
2102 ahd_freeze_devq(ahd, scb);
2103 }
2104 /* Return unpausing the sequencer. */
2105 return (0);
2106 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2107 /*
2108 * Ignore what are really parity errors that
2109 * occur on the last REQ of a free running
2110 * clock prior to going busfree. Some drives
2111 * do not properly active negate just before
2112 * going busfree resulting in a parity glitch.
2113 */
2114 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2115 #ifdef AHD_DEBUG
2116 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2117 kprintf("%s: Parity on last REQ detected "
2118 "during busfree phase.\n",
2119 ahd_name(ahd));
2120 #endif
2121 /* Return unpausing the sequencer. */
2122 return (0);
2123 }
2124 if (ahd->src_mode != AHD_MODE_SCSI) {
2125 u_int scbid;
2126 struct scb *scb;
2127
2128 scbid = ahd_get_scbptr(ahd);
2129 scb = ahd_lookup_scb(ahd, scbid);
2130 ahd_print_path(ahd, scb);
2131 kprintf("Unexpected PKT busfree condition\n");
2132 ahd_dump_card_state(ahd);
2133 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2134 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2135 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2136
2137 /* Return restarting the sequencer. */
2138 return (1);
2139 }
2140 kprintf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2141 ahd_dump_card_state(ahd);
2142 /* Restart the sequencer. */
2143 return (1);
2144 }
2145
2146 /*
2147 * Non-packetized unexpected or expected busfree.
2148 */
2149 static int
2150 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2151 {
2152 struct ahd_devinfo devinfo;
2153 struct scb *scb;
2154 u_int lastphase;
2155 u_int saved_scsiid;
2156 u_int saved_lun;
2157 u_int target;
2158 u_int initiator_role_id;
2159 u_int scbid;
2160 u_int ppr_busfree;
2161 int printerror;
2162
2163 /*
2164 * Look at what phase we were last in. If its message out,
2165 * chances are pretty good that the busfree was in response
2166 * to one of our abort requests.
2167 */
2168 lastphase = ahd_inb(ahd, LASTPHASE);
2169 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2170 saved_lun = ahd_inb(ahd, SAVED_LUN);
2171 target = SCSIID_TARGET(ahd, saved_scsiid);
2172 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2173 ahd_compile_devinfo(&devinfo, initiator_role_id,
2174 target, saved_lun, 'A', ROLE_INITIATOR);
2175 printerror = 1;
2176
2177 scbid = ahd_get_scbptr(ahd);
2178 scb = ahd_lookup_scb(ahd, scbid);
2179 if (scb != NULL
2180 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2181 scb = NULL;
2182
2183 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2184 if (lastphase == P_MESGOUT) {
2185 u_int tag;
2186
2187 tag = SCB_LIST_NULL;
2188 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2189 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2190 int found;
2191 int sent_msg;
2192
2193 if (scb == NULL) {
2194 ahd_print_devinfo(ahd, &devinfo);
2195 kprintf("Abort for unidentified "
2196 "connection completed.\n");
2197 /* restart the sequencer. */
2198 return (1);
2199 }
2200 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2201 ahd_print_path(ahd, scb);
2202 kprintf("SCB %d - Abort%s Completed.\n",
2203 SCB_GET_TAG(scb),
2204 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2205
2206 if (sent_msg == MSG_ABORT_TAG)
2207 tag = SCB_GET_TAG(scb);
2208
2209 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2210 /*
2211 * This abort is in response to an
2212 * unexpected switch to command phase
2213 * for a packetized connection. Since
2214 * the identify message was never sent,
2215 * "saved lun" is 0. We really want to
2216 * abort only the SCB that encountered
2217 * this error, which could have a different
2218 * lun. The SCB will be retried so the OS
2219 * will see the UA after renegotiating to
2220 * packetized.
2221 */
2222 tag = SCB_GET_TAG(scb);
2223 saved_lun = scb->hscb->lun;
2224 }
2225 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2226 tag, ROLE_INITIATOR,
2227 CAM_REQ_ABORTED);
2228 kprintf("found == 0x%x\n", found);
2229 printerror = 0;
2230 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2231 MSG_BUS_DEV_RESET, TRUE)) {
2232 #if defined(__DragonFly__) || defined(__FreeBSD__)
2233 /*
2234 * Don't mark the user's request for this BDR
2235 * as completing with CAM_BDR_SENT. CAM3
2236 * specifies CAM_REQ_CMP.
2237 */
2238 if (scb != NULL
2239 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2240 && ahd_match_scb(ahd, scb, target, 'A',
2241 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2242 ROLE_INITIATOR))
2243 aic_set_transaction_status(scb, CAM_REQ_CMP);
2244 #endif
2245 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2246 CAM_BDR_SENT, "Bus Device Reset",
2247 /*verbose_level*/0);
2248 printerror = 0;
2249 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2250 && ppr_busfree == 0) {
2251 struct ahd_initiator_tinfo *tinfo;
2252 struct ahd_tmode_tstate *tstate;
2253
2254 /*
2255 * PPR Rejected.
2256 *
2257 * If the previous negotiation was packetized,
2258 * this could be because the device has been
2259 * reset without our knowledge. Force our
2260 * current negotiation to async and retry the
2261 * negotiation. Otherwise retry the command
2262 * with non-ppr negotiation.
2263 */
2264 #ifdef AHD_DEBUG
2265 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2266 kprintf("PPR negotiation rejected busfree.\n");
2267 #endif
2268 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2269 devinfo.our_scsiid,
2270 devinfo.target, &tstate);
2271 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2272 ahd_set_width(ahd, &devinfo,
2273 MSG_EXT_WDTR_BUS_8_BIT,
2274 AHD_TRANS_CUR,
2275 /*paused*/TRUE);
2276 ahd_set_syncrate(ahd, &devinfo,
2277 /*period*/0, /*offset*/0,
2278 /*ppr_options*/0,
2279 AHD_TRANS_CUR,
2280 /*paused*/TRUE);
2281 /*
2282 * The expect PPR busfree handler below
2283 * will effect the retry and necessary
2284 * abort.
2285 */
2286 } else {
2287 tinfo->curr.transport_version = 2;
2288 tinfo->goal.transport_version = 2;
2289 tinfo->goal.ppr_options = 0;
2290 /*
2291 * Remove any SCBs in the waiting for selection
2292 * queue that may also be for this target so
2293 * that command ordering is preserved.
2294 */
2295 ahd_freeze_devq(ahd, scb);
2296 ahd_qinfifo_requeue_tail(ahd, scb);
2297 printerror = 0;
2298 }
2299 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2300 && ppr_busfree == 0) {
2301 /*
2302 * Negotiation Rejected. Go-narrow and
2303 * retry command.
2304 */
2305 #ifdef AHD_DEBUG
2306 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2307 kprintf("WDTR negotiation rejected busfree.\n");
2308 #endif
2309 ahd_set_width(ahd, &devinfo,
2310 MSG_EXT_WDTR_BUS_8_BIT,
2311 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2312 /*paused*/TRUE);
2313 /*
2314 * Remove any SCBs in the waiting for selection
2315 * queue that may also be for this target so that
2316 * command ordering is preserved.
2317 */
2318 ahd_freeze_devq(ahd, scb);
2319 ahd_qinfifo_requeue_tail(ahd, scb);
2320 printerror = 0;
2321 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2322 && ppr_busfree == 0) {
2323 /*
2324 * Negotiation Rejected. Go-async and
2325 * retry command.
2326 */
2327 #ifdef AHD_DEBUG
2328 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2329 kprintf("SDTR negotiation rejected busfree.\n");
2330 #endif
2331 ahd_set_syncrate(ahd, &devinfo,
2332 /*period*/0, /*offset*/0,
2333 /*ppr_options*/0,
2334 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2335 /*paused*/TRUE);
2336 /*
2337 * Remove any SCBs in the waiting for selection
2338 * queue that may also be for this target so that
2339 * command ordering is preserved.
2340 */
2341 ahd_freeze_devq(ahd, scb);
2342 ahd_qinfifo_requeue_tail(ahd, scb);
2343 printerror = 0;
2344 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2345 && ahd_sent_msg(ahd, AHDMSG_1B,
2346 MSG_INITIATOR_DET_ERR, TRUE)) {
2347
2348 #ifdef AHD_DEBUG
2349 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2350 kprintf("Expected IDE Busfree\n");
2351 #endif
2352 printerror = 0;
2353 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2354 && ahd_sent_msg(ahd, AHDMSG_1B,
2355 MSG_MESSAGE_REJECT, TRUE)) {
2356
2357 #ifdef AHD_DEBUG
2358 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2359 kprintf("Expected QAS Reject Busfree\n");
2360 #endif
2361 printerror = 0;
2362 }
2363 }
2364
2365 /*
2366 * The busfree required flag is honored at the end of
2367 * the message phases. We check it last in case we
2368 * had to send some other message that caused a busfree.
2369 */
2370 if (printerror != 0
2371 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2372 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2373
2374 ahd_freeze_devq(ahd, scb);
2375 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2376 aic_freeze_scb(scb);
2377 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2378 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2379 SCB_GET_CHANNEL(ahd, scb),
2380 SCB_GET_LUN(scb), SCB_LIST_NULL,
2381 ROLE_INITIATOR, CAM_REQ_ABORTED);
2382 } else {
2383 #ifdef AHD_DEBUG
2384 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2385 kprintf("PPR Negotiation Busfree.\n");
2386 #endif
2387 ahd_done(ahd, scb);
2388 }
2389 printerror = 0;
2390 }
2391 if (printerror != 0) {
2392 int aborted;
2393
2394 aborted = 0;
2395 if (scb != NULL) {
2396 u_int tag;
2397
2398 if ((scb->hscb->control & TAG_ENB) != 0)
2399 tag = SCB_GET_TAG(scb);
2400 else
2401 tag = SCB_LIST_NULL;
2402 ahd_print_path(ahd, scb);
2403 aborted = ahd_abort_scbs(ahd, target, 'A',
2404 SCB_GET_LUN(scb), tag,
2405 ROLE_INITIATOR,
2406 CAM_UNEXP_BUSFREE);
2407 } else {
2408 /*
2409 * We had not fully identified this connection,
2410 * so we cannot abort anything.
2411 */
2412 kprintf("%s: ", ahd_name(ahd));
2413 }
2414 kprintf("Unexpected busfree %s, %d SCBs aborted, "
2415 "PRGMCNT == 0x%x\n",
2416 ahd_lookup_phase_entry(lastphase)->phasemsg,
2417 aborted,
2418 ahd_inw(ahd, PRGMCNT));
2419 ahd_dump_card_state(ahd);
2420 if (lastphase != P_BUSFREE)
2421 ahd_force_renegotiation(ahd, &devinfo);
2422 }
2423 /* Always restart the sequencer. */
2424 return (1);
2425 }
2426
2427 static void
2428 ahd_handle_proto_violation(struct ahd_softc *ahd)
2429 {
2430 struct ahd_devinfo devinfo;
2431 struct scb *scb;
2432 u_int scbid;
2433 u_int seq_flags;
2434 u_int curphase;
2435 u_int lastphase;
2436 int found;
2437
2438 ahd_fetch_devinfo(ahd, &devinfo);
2439 scbid = ahd_get_scbptr(ahd);
2440 scb = ahd_lookup_scb(ahd, scbid);
2441 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2442 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2443 lastphase = ahd_inb(ahd, LASTPHASE);
2444 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2445
2446 /*
2447 * The reconnecting target either did not send an
2448 * identify message, or did, but we didn't find an SCB
2449 * to match.
2450 */
2451 ahd_print_devinfo(ahd, &devinfo);
2452 kprintf("Target did not send an IDENTIFY message. "
2453 "LASTPHASE = 0x%x.\n", lastphase);
2454 scb = NULL;
2455 } else if (scb == NULL) {
2456 /*
2457 * We don't seem to have an SCB active for this
2458 * transaction. Print an error and reset the bus.
2459 */
2460 ahd_print_devinfo(ahd, &devinfo);
2461 kprintf("No SCB found during protocol violation\n");
2462 goto proto_violation_reset;
2463 } else {
2464 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2465 if ((seq_flags & NO_CDB_SENT) != 0) {
2466 ahd_print_path(ahd, scb);
2467 kprintf("No or incomplete CDB sent to device.\n");
2468 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2469 & STATUS_RCVD) == 0) {
2470 /*
2471 * The target never bothered to provide status to
2472 * us prior to completing the command. Since we don't
2473 * know the disposition of this command, we must attempt
2474 * to abort it. Assert ATN and prepare to send an abort
2475 * message.
2476 */
2477 ahd_print_path(ahd, scb);
2478 kprintf("Completed command without status.\n");
2479 } else {
2480 ahd_print_path(ahd, scb);
2481 kprintf("Unknown protocol violation.\n");
2482 ahd_dump_card_state(ahd);
2483 }
2484 }
2485 if ((lastphase & ~P_DATAIN_DT) == 0
2486 || lastphase == P_COMMAND) {
2487 proto_violation_reset:
2488 /*
2489 * Target either went directly to data
2490 * phase or didn't respond to our ATN.
2491 * The only safe thing to do is to blow
2492 * it away with a bus reset.
2493 */
2494 found = ahd_reset_channel(ahd, 'A', TRUE);
2495 kprintf("%s: Issued Channel %c Bus Reset. "
2496 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2497 } else {
2498 /*
2499 * Leave the selection hardware off in case
2500 * this abort attempt will affect yet to
2501 * be sent commands.
2502 */
2503 ahd_outb(ahd, SCSISEQ0,
2504 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2505 ahd_assert_atn(ahd);
2506 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2507 if (scb == NULL) {
2508 ahd_print_devinfo(ahd, &devinfo);
2509 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2510 ahd->msgout_len = 1;
2511 ahd->msgout_index = 0;
2512 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2513 } else {
2514 ahd_print_path(ahd, scb);
2515 scb->flags |= SCB_ABORT;
2516 }
2517 kprintf("Protocol violation %s. Attempting to abort.\n",
2518 ahd_lookup_phase_entry(curphase)->phasemsg);
2519 }
2520 }
2521
2522 /*
2523 * Force renegotiation to occur the next time we initiate
2524 * a command to the current device.
2525 */
2526 static void
2527 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2528 {
2529 struct ahd_initiator_tinfo *targ_info;
2530 struct ahd_tmode_tstate *tstate;
2531
2532 #ifdef AHD_DEBUG
2533 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2534 ahd_print_devinfo(ahd, devinfo);
2535 kprintf("Forcing renegotiation\n");
2536 }
2537 #endif
2538 targ_info = ahd_fetch_transinfo(ahd,
2539 devinfo->channel,
2540 devinfo->our_scsiid,
2541 devinfo->target,
2542 &tstate);
2543 ahd_update_neg_request(ahd, devinfo, tstate,
2544 targ_info, AHD_NEG_IF_NON_ASYNC);
2545 }
2546
2547 #define AHD_MAX_STEPS 2000
2548 void
2549 ahd_clear_critical_section(struct ahd_softc *ahd)
2550 {
2551 ahd_mode_state saved_modes;
2552 int stepping;
2553 int steps;
2554 int first_instr;
2555 u_int simode0;
2556 u_int simode1;
2557 u_int simode3;
2558 u_int lqimode0;
2559 u_int lqimode1;
2560 u_int lqomode0;
2561 u_int lqomode1;
2562
2563 if (ahd->num_critical_sections == 0)
2564 return;
2565
2566 stepping = FALSE;
2567 steps = 0;
2568 first_instr = 0;
2569 simode0 = 0;
2570 simode1 = 0;
2571 simode3 = 0;
2572 lqimode0 = 0;
2573 lqimode1 = 0;
2574 lqomode0 = 0;
2575 lqomode1 = 0;
2576 saved_modes = ahd_save_modes(ahd);
2577 for (;;) {
2578 struct cs *cs;
2579 u_int seqaddr;
2580 u_int i;
2581
2582 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2583 seqaddr = ahd_inw(ahd, CURADDR);
2584
2585 cs = ahd->critical_sections;
2586 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2587
2588 if (cs->begin < seqaddr && cs->end >= seqaddr)
2589 break;
2590 }
2591
2592 if (i == ahd->num_critical_sections)
2593 break;
2594
2595 if (steps > AHD_MAX_STEPS) {
2596 kprintf("%s: Infinite loop in critical section\n"
2597 "%s: First Instruction 0x%x now 0x%x\n",
2598 ahd_name(ahd), ahd_name(ahd), first_instr,
2599 seqaddr);
2600 ahd_dump_card_state(ahd);
2601 panic("critical section loop");
2602 }
2603
2604 steps++;
2605 #ifdef AHD_DEBUG
2606 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2607 kprintf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2608 seqaddr);
2609 #endif
2610 if (stepping == FALSE) {
2611
2612 first_instr = seqaddr;
2613 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2614 simode0 = ahd_inb(ahd, SIMODE0);
2615 simode3 = ahd_inb(ahd, SIMODE3);
2616 lqimode0 = ahd_inb(ahd, LQIMODE0);
2617 lqimode1 = ahd_inb(ahd, LQIMODE1);
2618 lqomode0 = ahd_inb(ahd, LQOMODE0);
2619 lqomode1 = ahd_inb(ahd, LQOMODE1);
2620 ahd_outb(ahd, SIMODE0, 0);
2621 ahd_outb(ahd, SIMODE3, 0);
2622 ahd_outb(ahd, LQIMODE0, 0);
2623 ahd_outb(ahd, LQIMODE1, 0);
2624 ahd_outb(ahd, LQOMODE0, 0);
2625 ahd_outb(ahd, LQOMODE1, 0);
2626 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2627 simode1 = ahd_inb(ahd, SIMODE1);
2628 /*
2629 * We don't clear ENBUSFREE. Unfortunately
2630 * we cannot re-enable busfree detection within
2631 * the current connection, so we must leave it
2632 * on while single stepping.
2633 */
2634 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2635 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2636 stepping = TRUE;
2637 }
2638 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2639 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2640 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2641 ahd_outb(ahd, HCNTRL, ahd->unpause);
2642 while (!ahd_is_paused(ahd))
2643 aic_delay(200);
2644 ahd_update_modes(ahd);
2645 }
2646 if (stepping) {
2647 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2648 ahd_outb(ahd, SIMODE0, simode0);
2649 ahd_outb(ahd, SIMODE3, simode3);
2650 ahd_outb(ahd, LQIMODE0, lqimode0);
2651 ahd_outb(ahd, LQIMODE1, lqimode1);
2652 ahd_outb(ahd, LQOMODE0, lqomode0);
2653 ahd_outb(ahd, LQOMODE1, lqomode1);
2654 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2655 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2656 ahd_outb(ahd, SIMODE1, simode1);
2657 /*
2658 * SCSIINT seems to glitch occassionally when
2659 * the interrupt masks are restored. Clear SCSIINT
2660 * one more time so that only persistent errors
2661 * are seen as a real interrupt.
2662 */
2663 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2664 }
2665 ahd_restore_modes(ahd, saved_modes);
2666 }
2667
2668 /*
2669 * Clear any pending interrupt status.
2670 */
2671 void
2672 ahd_clear_intstat(struct ahd_softc *ahd)
2673 {
2674 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2675 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2676 /* Clear any interrupt conditions this may have caused */
2677 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2678 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2679 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2680 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2681 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2682 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2683 |CLRLQOATNPKT|CLRLQOTCRC);
2684 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2685 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2686 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2687 ahd_outb(ahd, CLRLQOINT0, 0);
2688 ahd_outb(ahd, CLRLQOINT1, 0);
2689 }
2690 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2691 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2692 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2693 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2694 |CLRIOERR|CLROVERRUN);
2695 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2696 }
2697
2698 /**************************** Debugging Routines ******************************/
2699 #ifdef AHD_DEBUG
2700 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2701 #endif
2702 void
2703 ahd_print_scb(struct scb *scb)
2704 {
2705 struct hardware_scb *hscb;
2706 int i;
2707
2708 hscb = scb->hscb;
2709 kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2710 (void *)scb,
2711 hscb->control,
2712 hscb->scsiid,
2713 hscb->lun,
2714 hscb->cdb_len);
2715 kprintf("Shared Data: ");
2716 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2717 kprintf("%#02x", hscb->shared_data.idata.cdb[i]);
2718 kprintf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2719 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2720 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2721 aic_le32toh(hscb->datacnt),
2722 aic_le32toh(hscb->sgptr),
2723 SCB_GET_TAG(scb));
2724 ahd_dump_sglist(scb);
2725 }
2726
2727 void
2728 ahd_dump_sglist(struct scb *scb)
2729 {
2730 int i;
2731
2732 if (scb->sg_count > 0) {
2733 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2734 struct ahd_dma64_seg *sg_list;
2735
2736 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2737 for (i = 0; i < scb->sg_count; i++) {
2738 uint64_t addr;
2739 uint32_t len;
2740
2741 addr = aic_le64toh(sg_list[i].addr);
2742 len = aic_le32toh(sg_list[i].len);
2743 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2744 i,
2745 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2746 (uint32_t)(addr & 0xFFFFFFFF),
2747 sg_list[i].len & AHD_SG_LEN_MASK,
2748 (sg_list[i].len & AHD_DMA_LAST_SEG)
2749 ? " Last" : "");
2750 }
2751 } else {
2752 struct ahd_dma_seg *sg_list;
2753
2754 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2755 for (i = 0; i < scb->sg_count; i++) {
2756 uint32_t len;
2757
2758 len = aic_le32toh(sg_list[i].len);
2759 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2760 i,
2761 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2762 aic_le32toh(sg_list[i].addr),
2763 len & AHD_SG_LEN_MASK,
2764 len & AHD_DMA_LAST_SEG ? " Last" : "");
2765 }
2766 }
2767 }
2768 }
2769
2770 /************************* Transfer Negotiation *******************************/
2771 /*
2772 * Allocate per target mode instance (ID we respond to as a target)
2773 * transfer negotiation data structures.
2774 */
2775 static struct ahd_tmode_tstate *
2776 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2777 {
2778 struct ahd_tmode_tstate *master_tstate;
2779 struct ahd_tmode_tstate *tstate;
2780 int i;
2781
2782 master_tstate = ahd->enabled_targets[ahd->our_id];
2783 if (ahd->enabled_targets[scsi_id] != NULL
2784 && ahd->enabled_targets[scsi_id] != master_tstate)
2785 panic("%s: ahd_alloc_tstate - Target already allocated",
2786 ahd_name(ahd));
2787 tstate = kmalloc(sizeof(*tstate), M_DEVBUF, M_INTWAIT);
2788
2789 /*
2790 * If we have allocated a master tstate, copy user settings from
2791 * the master tstate (taken from SRAM or the EEPROM) for this
2792 * channel, but reset our current and goal settings to async/narrow
2793 * until an initiator talks to us.
2794 */
2795 if (master_tstate != NULL) {
2796 memcpy(tstate, master_tstate, sizeof(*tstate));
2797 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2798 for (i = 0; i < 16; i++) {
2799 memset(&tstate->transinfo[i].curr, 0,
2800 sizeof(tstate->transinfo[i].curr));
2801 memset(&tstate->transinfo[i].goal, 0,
2802 sizeof(tstate->transinfo[i].goal));
2803 }
2804 } else
2805 memset(tstate, 0, sizeof(*tstate));
2806 ahd->enabled_targets[scsi_id] = tstate;
2807 return (tstate);
2808 }
2809
2810 #ifdef AHD_TARGET_MODE
2811 /*
2812 * Free per target mode instance (ID we respond to as a target)
2813 * transfer negotiation data structures.
2814 */
2815 static void
2816 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2817 {
2818 struct ahd_tmode_tstate *tstate;
2819
2820 /*
2821 * Don't clean up our "master" tstate.
2822 * It has our default user settings.
2823 */
2824 if (scsi_id == ahd->our_id
2825 && force == FALSE)
2826 return;
2827
2828 tstate = ahd->enabled_targets[scsi_id];
2829 if (tstate != NULL)
2830 kfree(tstate, M_DEVBUF);
2831 ahd->enabled_targets[scsi_id] = NULL;
2832 }
2833 #endif
2834
2835 /*
2836 * Called when we have an active connection to a target on the bus,
2837 * this function finds the nearest period to the input period limited
2838 * by the capabilities of the bus connectivity of and sync settings for
2839 * the target.
2840 */
2841 void
2842 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2843 struct ahd_initiator_tinfo *tinfo,
2844 u_int *period, u_int *ppr_options, role_t role)
2845 {
2846 struct ahd_transinfo *transinfo;
2847 u_int maxsync;
2848
2849 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2850 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2851 maxsync = AHD_SYNCRATE_PACED;
2852 } else {
2853 maxsync = AHD_SYNCRATE_ULTRA;
2854 /* Can't do DT related options on an SE bus */
2855 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2856 }
2857 /*
2858 * Never allow a value higher than our current goal
2859 * period otherwise we may allow a target initiated
2860 * negotiation to go above the limit as set by the
2861 * user. In the case of an initiator initiated
2862 * sync negotiation, we limit based on the user
2863 * setting. This allows the system to still accept
2864 * incoming negotiations even if target initiated
2865 * negotiation is not performed.
2866 */
2867 if (role == ROLE_TARGET)
2868 transinfo = &tinfo->user;
2869 else
2870 transinfo = &tinfo->goal;
2871 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2872 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2873 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2874 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2875 }
2876 if (transinfo->period == 0) {
2877 *period = 0;
2878 *ppr_options = 0;
2879 } else {
2880 *period = MAX(*period, transinfo->period);
2881 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2882 }
2883 }
2884
2885 /*
2886 * Look up the valid period to SCSIRATE conversion in our table.
2887 * Return the period and offset that should be sent to the target
2888 * if this was the beginning of an SDTR.
2889 */
2890 void
2891 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2892 u_int *ppr_options, u_int maxsync)
2893 {
2894 if (*period < maxsync)
2895 *period = maxsync;
2896
2897 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2898 && *period > AHD_SYNCRATE_MIN_DT)
2899 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2900
2901 if (*period > AHD_SYNCRATE_MIN)
2902 *period = 0;
2903
2904 /* Honor PPR option conformance rules. */
2905 if (*period > AHD_SYNCRATE_PACED)
2906 *ppr_options &= ~MSG_EXT_PPR_RTI;
2907
2908 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2909 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2910
2911 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2912 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2913
2914 /* Skip all PACED only entries if IU is not available */
2915 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2916 && *period < AHD_SYNCRATE_DT)
2917 *period = AHD_SYNCRATE_DT;
2918
2919 /* Skip all DT only entries if DT is not available */
2920 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2921 && *period < AHD_SYNCRATE_ULTRA2)
2922 *period = AHD_SYNCRATE_ULTRA2;
2923 }
2924
2925 /*
2926 * Truncate the given synchronous offset to a value the
2927 * current adapter type and syncrate are capable of.
2928 */
2929 void
2930 ahd_validate_offset(struct ahd_softc *ahd,
2931 struct ahd_initiator_tinfo *tinfo,
2932 u_int period, u_int *offset, int wide,
2933 role_t role)
2934 {
2935 u_int maxoffset;
2936
2937 /* Limit offset to what we can do */
2938 if (period == 0)
2939 maxoffset = 0;
2940 else if (period <= AHD_SYNCRATE_PACED) {
2941 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2942 maxoffset = MAX_OFFSET_PACED_BUG;
2943 else
2944 maxoffset = MAX_OFFSET_PACED;
2945 } else
2946 maxoffset = MAX_OFFSET_NON_PACED;
2947 *offset = MIN(*offset, maxoffset);
2948 if (tinfo != NULL) {
2949 if (role == ROLE_TARGET)
2950 *offset = MIN(*offset, tinfo->user.offset);
2951 else
2952 *offset = MIN(*offset, tinfo->goal.offset);
2953 }
2954 }
2955
2956 /*
2957 * Truncate the given transfer width parameter to a value the
2958 * current adapter type is capable of.
2959 */
2960 void
2961 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2962 u_int *bus_width, role_t role)
2963 {
2964 switch (*bus_width) {
2965 default:
2966 if (ahd->features & AHD_WIDE) {
2967 /* Respond Wide */
2968 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2969 break;
2970 }
2971 /* FALLTHROUGH */
2972 case MSG_EXT_WDTR_BUS_8_BIT:
2973 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2974 break;
2975 }
2976 if (tinfo != NULL) {
2977 if (role == ROLE_TARGET)
2978 *bus_width = MIN(tinfo->user.width, *bus_width);
2979 else
2980 *bus_width = MIN(tinfo->goal.width, *bus_width);
2981 }
2982 }
2983
2984 /*
2985 * Update the bitmask of targets for which the controller should
2986 * negotiate with at the next convenient oportunity. This currently
2987 * means the next time we send the initial identify messages for
2988 * a new transaction.
2989 */
2990 int
2991 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2992 struct ahd_tmode_tstate *tstate,
2993 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
2994 {
2995 u_int auto_negotiate_orig;
2996
2997 auto_negotiate_orig = tstate->auto_negotiate;
2998 if (neg_type == AHD_NEG_ALWAYS) {
2999 /*
3000 * Force our "current" settings to be
3001 * unknown so that unless a bus reset
3002 * occurs the need to renegotiate is
3003 * recorded persistently.
3004 */
3005 if ((ahd->features & AHD_WIDE) != 0)
3006 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3007 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3008 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3009 }
3010 if (tinfo->curr.period != tinfo->goal.period
3011 || tinfo->curr.width != tinfo->goal.width
3012 || tinfo->curr.offset != tinfo->goal.offset
3013 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3014 || (neg_type == AHD_NEG_IF_NON_ASYNC
3015 && (tinfo->goal.offset != 0
3016 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3017 || tinfo->goal.ppr_options != 0)))
3018 tstate->auto_negotiate |= devinfo->target_mask;
3019 else
3020 tstate->auto_negotiate &= ~devinfo->target_mask;
3021
3022 return (auto_negotiate_orig != tstate->auto_negotiate);
3023 }
3024
3025 /*
3026 * Update the user/goal/curr tables of synchronous negotiation
3027 * parameters as well as, in the case of a current or active update,
3028 * any data structures on the host controller. In the case of an
3029 * active update, the specified target is currently talking to us on
3030 * the bus, so the transfer parameter update must take effect
3031 * immediately.
3032 */
3033 void
3034 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3035 u_int period, u_int offset, u_int ppr_options,
3036 u_int type, int paused)
3037 {
3038 struct ahd_initiator_tinfo *tinfo;
3039 struct ahd_tmode_tstate *tstate;
3040 u_int old_period;
3041 u_int old_offset;
3042 u_int old_ppr;
3043 int active;
3044 int update_needed;
3045
3046 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3047 update_needed = 0;
3048
3049 if (period == 0 || offset == 0) {
3050 period = 0;
3051 offset = 0;
3052 }
3053
3054 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3055 devinfo->target, &tstate);
3056
3057 if ((type & AHD_TRANS_USER) != 0) {
3058 tinfo->user.period = period;
3059 tinfo->user.offset = offset;
3060 tinfo->user.ppr_options = ppr_options;
3061 }
3062
3063 if ((type & AHD_TRANS_GOAL) != 0) {
3064 tinfo->goal.period = period;
3065 tinfo->goal.offset = offset;
3066 tinfo->goal.ppr_options = ppr_options;
3067 }
3068
3069 old_period = tinfo->curr.period;
3070 old_offset = tinfo->curr.offset;
3071 old_ppr = tinfo->curr.ppr_options;
3072
3073 if ((type & AHD_TRANS_CUR) != 0
3074 && (old_period != period
3075 || old_offset != offset
3076 || old_ppr != ppr_options)) {
3077
3078 update_needed++;
3079
3080 tinfo->curr.period = period;
3081 tinfo->curr.offset = offset;
3082 tinfo->curr.ppr_options = ppr_options;
3083
3084 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3085 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3086 if (bootverbose) {
3087 if (offset != 0) {
3088 int options;
3089
3090 kprintf("%s: target %d synchronous with "
3091 "period = 0x%x, offset = 0x%x",
3092 ahd_name(ahd), devinfo->target,
3093 period, offset);
3094 options = 0;
3095 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3096 kprintf("(RDSTRM");
3097 options++;
3098 }
3099 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3100 kprintf("%s", options ? "|DT" : "(DT");
3101 options++;
3102 }
3103 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3104 kprintf("%s", options ? "|IU" : "(IU");
3105 options++;
3106 }
3107 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3108 kprintf("%s", options ? "|RTI" : "(RTI");
3109 options++;
3110 }
3111 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3112 kprintf("%s", options ? "|QAS" : "(QAS");
3113 options++;
3114 }
3115 if (options != 0)
3116 kprintf(")\n");
3117 else
3118 kprintf("\n");
3119 } else {
3120 kprintf("%s: target %d using "
3121 "asynchronous transfers%s\n",
3122 ahd_name(ahd), devinfo->target,
3123 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3124 ? "(QAS)" : "");
3125 }
3126 }
3127 }
3128 /*
3129 * Always refresh the neg-table to handle the case of the
3130 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3131 * We will always renegotiate in that case if this is a
3132 * packetized request. Also manage the busfree expected flag
3133 * from this common routine so that we catch changes due to
3134 * WDTR or SDTR messages.
3135 */
3136 if ((type & AHD_TRANS_CUR) != 0) {
3137 if (!paused)
3138 ahd_pause(ahd);
3139 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3140 if (!paused)
3141 ahd_unpause(ahd);
3142 if (ahd->msg_type != MSG_TYPE_NONE) {
3143 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3144 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3145 #ifdef AHD_DEBUG
3146 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3147 ahd_print_devinfo(ahd, devinfo);
3148 kprintf("Expecting IU Change busfree\n");
3149 }
3150 #endif
3151 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3152 | MSG_FLAG_IU_REQ_CHANGED;
3153 }
3154 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3155 #ifdef AHD_DEBUG
3156 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3157 kprintf("PPR with IU_REQ outstanding\n");
3158 #endif
3159 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3160 }
3161 }
3162 }
3163
3164 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3165 tinfo, AHD_NEG_TO_GOAL);
3166
3167 if (update_needed && active)
3168 ahd_update_pending_scbs(ahd);
3169 }
3170
3171 /*
3172 * Update the user/goal/curr tables of wide negotiation
3173 * parameters as well as, in the case of a current or active update,
3174 * any data structures on the host controller. In the case of an
3175 * active update, the specified target is currently talking to us on
3176 * the bus, so the transfer parameter update must take effect
3177 * immediately.
3178 */
3179 void
3180 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3181 u_int width, u_int type, int paused)
3182 {
3183 struct ahd_initiator_tinfo *tinfo;
3184 struct ahd_tmode_tstate *tstate;
3185 u_int oldwidth;
3186 int active;
3187 int update_needed;
3188
3189 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3190 update_needed = 0;
3191 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3192 devinfo->target, &tstate);
3193
3194 if ((type & AHD_TRANS_USER) != 0)
3195 tinfo->user.width = width;
3196
3197 if ((type & AHD_TRANS_GOAL) != 0)
3198 tinfo->goal.width = width;
3199
3200 oldwidth = tinfo->curr.width;
3201 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3202
3203 update_needed++;
3204
3205 tinfo->curr.width = width;
3206 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3207 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3208 if (bootverbose) {
3209 kprintf("%s: target %d using %dbit transfers\n",
3210 ahd_name(ahd), devinfo->target,
3211 8 * (0x01 << width));
3212 }
3213 }
3214
3215 if ((type & AHD_TRANS_CUR) != 0) {
3216 if (!paused)
3217 ahd_pause(ahd);
3218 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3219 if (!paused)
3220 ahd_unpause(ahd);
3221 }
3222
3223 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3224 tinfo, AHD_NEG_TO_GOAL);
3225 if (update_needed && active)
3226 ahd_update_pending_scbs(ahd);
3227
3228 }
3229
3230 /*
3231 * Update the current state of tagged queuing for a given target.
3232 */
3233 void
3234 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3235 ahd_queue_alg alg)
3236 {
3237 ahd_platform_set_tags(ahd, devinfo, alg);
3238 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3239 devinfo->lun, AC_TRANSFER_NEG, &alg);
3240 }
3241
3242 static void
3243 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3244 struct ahd_transinfo *tinfo)
3245 {
3246 ahd_mode_state saved_modes;
3247 u_int period;
3248 u_int ppr_opts;
3249 u_int con_opts;
3250 u_int offset;
3251 u_int saved_negoaddr;
3252 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3253
3254 saved_modes = ahd_save_modes(ahd);
3255 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3256
3257 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3258 ahd_outb(ahd, NEGOADDR, devinfo->target);
3259 period = tinfo->period;
3260 offset = tinfo->offset;
3261 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3262 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3263 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3264 con_opts = 0;
3265 if (period == 0)
3266 period = AHD_SYNCRATE_ASYNC;
3267 if (period == AHD_SYNCRATE_160) {
3268
3269 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3270 /*
3271 * When the SPI4 spec was finalized, PACE transfers
3272 * was not made a configurable option in the PPR
3273 * message. Instead it is assumed to be enabled for
3274 * any syncrate faster than 80MHz. Nevertheless,
3275 * Harpoon2A4 allows this to be configurable.
3276 *
3277 * Harpoon2A4 also assumes at most 2 data bytes per
3278 * negotiated REQ/ACK offset. Paced transfers take
3279 * 4, so we must adjust our offset.
3280 */
3281 ppr_opts |= PPROPT_PACE;
3282 offset *= 2;
3283
3284 /*
3285 * Harpoon2A assumed that there would be a
3286 * fallback rate between 160MHz and 80Mhz,
3287 * so 7 is used as the period factor rather
3288 * than 8 for 160MHz.
3289 */
3290 period = AHD_SYNCRATE_REVA_160;
3291 }
3292 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3293 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3294 ~AHD_PRECOMP_MASK;
3295 } else {
3296 /*
3297 * Precomp should be disabled for non-paced transfers.
3298 */
3299 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3300
3301 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3302 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3303 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3304 /*
3305 * Slow down our CRC interval to be
3306 * compatible with non-packetized
3307 * U160 devices that can't handle a
3308 * CRC at full speed.
3309 */
3310 con_opts |= ENSLOWCRC;
3311 }
3312
3313 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3314 /*
3315 * On H2A4, revert to a slower slewrate
3316 * on non-paced transfers.
3317 */
3318 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3319 ~AHD_SLEWRATE_MASK;
3320 }
3321 }
3322
3323 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3324 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3325 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3326 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3327
3328 ahd_outb(ahd, NEGPERIOD, period);
3329 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3330 ahd_outb(ahd, NEGOFFSET, offset);
3331
3332 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3333 con_opts |= WIDEXFER;
3334
3335 /*
3336 * During packetized transfers, the target will
3337 * give us the oportunity to send command packets
3338 * without us asserting attention.
3339 */
3340 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3341 con_opts |= ENAUTOATNO;
3342 ahd_outb(ahd, NEGCONOPTS, con_opts);
3343 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3344 ahd_restore_modes(ahd, saved_modes);
3345 }
3346
3347 /*
3348 * When the transfer settings for a connection change, setup for
3349 * negotiation in pending SCBs to effect the change as quickly as
3350 * possible. We also cancel any negotiations that are scheduled
3351 * for inflight SCBs that have not been started yet.
3352 */
3353 static void
3354 ahd_update_pending_scbs(struct ahd_softc *ahd)
3355 {
3356 struct scb *pending_scb;
3357 int pending_scb_count;
3358 int paused;
3359 u_int saved_scbptr;
3360 ahd_mode_state saved_modes;
3361
3362 /*
3363 * Traverse the pending SCB list and ensure that all of the
3364 * SCBs there have the proper settings. We can only safely
3365 * clear the negotiation required flag (setting requires the
3366 * execution queue to be modified) and this is only possible
3367 * if we are not already attempting to select out for this
3368 * SCB. For this reason, all callers only call this routine
3369 * if we are changing the negotiation settings for the currently
3370 * active transaction on the bus.
3371 */
3372 pending_scb_count = 0;
3373 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3374 struct ahd_devinfo devinfo;
3375 struct ahd_initiator_tinfo *tinfo;
3376 struct ahd_tmode_tstate *tstate;
3377
3378 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3379 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3380 devinfo.our_scsiid,
3381 devinfo.target, &tstate);
3382 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3383 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3384 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3385 pending_scb->hscb->control &= ~MK_MESSAGE;
3386 }
3387 ahd_sync_scb(ahd, pending_scb,
3388 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3389 pending_scb_count++;
3390 }
3391
3392 if (pending_scb_count == 0)
3393 return;
3394
3395 if (ahd_is_paused(ahd)) {
3396 paused = 1;
3397 } else {
3398 paused = 0;
3399 ahd_pause(ahd);
3400 }
3401
3402 /*
3403 * Force the sequencer to reinitialize the selection for
3404 * the command at the head of the execution queue if it
3405 * has already been setup. The negotiation changes may
3406 * effect whether we select-out with ATN. It is only
3407 * safe to clear ENSELO when the bus is not free and no
3408 * selection is in progres or completed.
3409 */
3410 saved_modes = ahd_save_modes(ahd);
3411 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3412 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3413 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3414 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3415 saved_scbptr = ahd_get_scbptr(ahd);
3416 /* Ensure that the hscbs down on the card match the new information */
3417 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3418 u_int scb_tag;
3419 u_int control;
3420
3421 scb_tag = SCB_GET_TAG(pending_scb);
3422 ahd_set_scbptr(ahd, scb_tag);
3423 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3424 control &= ~MK_MESSAGE;
3425 control |= pending_scb->hscb->control & MK_MESSAGE;
3426 ahd_outb(ahd, SCB_CONTROL, control);
3427 }
3428 ahd_set_scbptr(ahd, saved_scbptr);
3429 ahd_restore_modes(ahd, saved_modes);
3430
3431 if (paused == 0)
3432 ahd_unpause(ahd);
3433 }
3434
3435 /**************************** Pathing Information *****************************/
3436 static void
3437 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3438 {
3439 ahd_mode_state saved_modes;
3440 u_int saved_scsiid;
3441 role_t role;
3442 int our_id;
3443
3444 saved_modes = ahd_save_modes(ahd);
3445 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3446
3447 if (ahd_inb(ahd, SSTAT0) & TARGET)
3448 role = ROLE_TARGET;
3449 else
3450 role = ROLE_INITIATOR;
3451
3452 if (role == ROLE_TARGET
3453 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3454 /* We were selected, so pull our id from TARGIDIN */
3455 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3456 } else if (role == ROLE_TARGET)
3457 our_id = ahd_inb(ahd, TOWNID);
3458 else
3459 our_id = ahd_inb(ahd, IOWNID);
3460
3461 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3462 ahd_compile_devinfo(devinfo,
3463 our_id,
3464 SCSIID_TARGET(ahd, saved_scsiid),
3465 ahd_inb(ahd, SAVED_LUN),
3466 SCSIID_CHANNEL(ahd, saved_scsiid),
3467 role);
3468 ahd_restore_modes(ahd, saved_modes);
3469 }
3470
3471 void
3472 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3473 {
3474 kprintf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3475 devinfo->target, devinfo->lun);
3476 }
3477
3478 struct ahd_phase_table_entry*
3479 ahd_lookup_phase_entry(int phase)
3480 {
3481 struct ahd_phase_table_entry *entry;
3482 struct ahd_phase_table_entry *last_entry;
3483
3484 /*
3485 * num_phases doesn't include the default entry which
3486 * will be returned if the phase doesn't match.
3487 */
3488 last_entry = &ahd_phase_table[num_phases];
3489 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3490 if (phase == entry->phase)
3491 break;
3492 }
3493 return (entry);
3494 }
3495
3496 void
3497 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3498 u_int lun, char channel, role_t role)
3499 {
3500 devinfo->our_scsiid = our_id;
3501 devinfo->target = target;
3502 devinfo->lun = lun;
3503 devinfo->target_offset = target;
3504 devinfo->channel = channel;
3505 devinfo->role = role;
3506 if (channel == 'B')
3507 devinfo->target_offset += 8;
3508 devinfo->target_mask = (0x01 << devinfo->target_offset);
3509 }
3510
3511 static void
3512 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3513 struct scb *scb)
3514 {
3515 role_t role;
3516 int our_id;
3517
3518 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3519 role = ROLE_INITIATOR;
3520 if ((scb->hscb->control & TARGET_SCB) != 0)
3521 role = ROLE_TARGET;
3522 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3523 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3524 }
3525
3526
3527 /************************ Message Phase Processing ****************************/
3528 /*
3529 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3530 * or enters the initial message out phase, we are interrupted. Fill our
3531 * outgoing message buffer with the appropriate message and beging handing
3532 * the message phase(s) manually.
3533 */
3534 static void
3535 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3536 struct scb *scb)
3537 {
3538 /*
3539 * To facilitate adding multiple messages together,
3540 * each routine should increment the index and len
3541 * variables instead of setting them explicitly.
3542 */
3543 ahd->msgout_index = 0;
3544 ahd->msgout_len = 0;
3545
3546 if (ahd_currently_packetized(ahd))
3547 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3548
3549 if (ahd->send_msg_perror
3550 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3551 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3552 ahd->msgout_len++;
3553 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3554 #ifdef AHD_DEBUG
3555 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3556 kprintf("Setting up for Parity Error delivery\n");
3557 #endif
3558 return;
3559 } else if (scb == NULL) {
3560 kprintf("%s: WARNING. No pending message for "
3561 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3562 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3563 ahd->msgout_len++;
3564 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3565 return;
3566 }
3567
3568 if ((scb->flags & SCB_DEVICE_RESET) == 0
3569 && (scb->flags & SCB_PACKETIZED) == 0
3570 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3571 u_int identify_msg;
3572
3573 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3574 if ((scb->hscb->control & DISCENB) != 0)
3575 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3576 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3577 ahd->msgout_len++;
3578
3579 if ((scb->hscb->control & TAG_ENB) != 0) {
3580 ahd->msgout_buf[ahd->msgout_index++] =
3581 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3582 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3583 ahd->msgout_len += 2;
3584 }
3585 }
3586
3587 if (scb->flags & SCB_DEVICE_RESET) {
3588 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3589 ahd->msgout_len++;
3590 ahd_print_path(ahd, scb);
3591 kprintf("Bus Device Reset Message Sent\n");
3592 /*
3593 * Clear our selection hardware in advance of
3594 * the busfree. We may have an entry in the waiting
3595 * Q for this target, and we don't want to go about
3596 * selecting while we handle the busfree and blow it
3597 * away.
3598 */
3599 ahd_outb(ahd, SCSISEQ0, 0);
3600 } else if ((scb->flags & SCB_ABORT) != 0) {
3601
3602 if ((scb->hscb->control & TAG_ENB) != 0) {
3603 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3604 } else {
3605 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3606 }
3607 ahd->msgout_len++;
3608 ahd_print_path(ahd, scb);
3609 kprintf("Abort%s Message Sent\n",
3610 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3611 /*
3612 * Clear our selection hardware in advance of
3613 * the busfree. We may have an entry in the waiting
3614 * Q for this target, and we don't want to go about
3615 * selecting while we handle the busfree and blow it
3616 * away.
3617 */
3618 ahd_outb(ahd, SCSISEQ0, 0);
3619 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3620 ahd_build_transfer_msg(ahd, devinfo);
3621 /*
3622 * Clear our selection hardware in advance of potential
3623 * PPR IU status change busfree. We may have an entry in
3624 * the waiting Q for this target, and we don't want to go
3625 * about selecting while we handle the busfree and blow
3626 * it away.
3627 */
3628 ahd_outb(ahd, SCSISEQ0, 0);
3629 } else {
3630 kprintf("ahd_intr: AWAITING_MSG for an SCB that "
3631 "does not have a waiting message\n");
3632 kprintf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3633 devinfo->target_mask);
3634 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3635 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3636 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3637 scb->flags);
3638 }
3639
3640 /*
3641 * Clear the MK_MESSAGE flag from the SCB so we aren't
3642 * asked to send this message again.
3643 */
3644 ahd_outb(ahd, SCB_CONTROL,
3645 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3646 scb->hscb->control &= ~MK_MESSAGE;
3647 ahd->msgout_index = 0;
3648 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3649 }
3650
3651 /*
3652 * Build an appropriate transfer negotiation message for the
3653 * currently active target.
3654 */
3655 static void
3656 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3657 {
3658 /*
3659 * We need to initiate transfer negotiations.
3660 * If our current and goal settings are identical,
3661 * we want to renegotiate due to a check condition.
3662 */
3663 struct ahd_initiator_tinfo *tinfo;
3664 struct ahd_tmode_tstate *tstate;
3665 int dowide;
3666 int dosync;
3667 int doppr;
3668 u_int period;
3669 u_int ppr_options;
3670 u_int offset;
3671
3672 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3673 devinfo->target, &tstate);
3674 /*
3675 * Filter our period based on the current connection.
3676 * If we can't perform DT transfers on this segment (not in LVD
3677 * mode for instance), then our decision to issue a PPR message
3678 * may change.
3679 */
3680 period = tinfo->goal.period;
3681 offset = tinfo->goal.offset;
3682 ppr_options = tinfo->goal.ppr_options;
3683 /* Target initiated PPR is not allowed in the SCSI spec */
3684 if (devinfo->role == ROLE_TARGET)
3685 ppr_options = 0;
3686 ahd_devlimited_syncrate(ahd, tinfo, &period,
3687 &ppr_options, devinfo->role);
3688 dowide = tinfo->curr.width != tinfo->goal.width;
3689 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3690 /*
3691 * Only use PPR if we have options that need it, even if the device
3692 * claims to support it. There might be an expander in the way
3693 * that doesn't.
3694 */
3695 doppr = ppr_options != 0;
3696
3697 if (!dowide && !dosync && !doppr) {
3698 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3699 dosync = tinfo->goal.offset != 0;
3700 }
3701
3702 if (!dowide && !dosync && !doppr) {
3703 /*
3704 * Force async with a WDTR message if we have a wide bus,
3705 * or just issue an SDTR with a 0 offset.
3706 */
3707 if ((ahd->features & AHD_WIDE) != 0)
3708 dowide = 1;
3709 else
3710 dosync = 1;
3711
3712 if (bootverbose) {
3713 ahd_print_devinfo(ahd, devinfo);
3714 kprintf("Ensuring async\n");
3715 }
3716 }
3717 /* Target initiated PPR is not allowed in the SCSI spec */
3718 if (devinfo->role == ROLE_TARGET)
3719 doppr = 0;
3720
3721 /*
3722 * Both the PPR message and SDTR message require the
3723 * goal syncrate to be limited to what the target device
3724 * is capable of handling (based on whether an LVD->SE
3725 * expander is on the bus), so combine these two cases.
3726 * Regardless, guarantee that if we are using WDTR and SDTR
3727 * messages that WDTR comes first.
3728 */
3729 if (doppr || (dosync && !dowide)) {
3730
3731 offset = tinfo->goal.offset;
3732 ahd_validate_offset(ahd, tinfo, period, &offset,
3733 doppr ? tinfo->goal.width
3734 : tinfo->curr.width,
3735 devinfo->role);
3736 if (doppr) {
3737 ahd_construct_ppr(ahd, devinfo, period, offset,
3738 tinfo->goal.width, ppr_options);
3739 } else {
3740 ahd_construct_sdtr(ahd, devinfo, period, offset);
3741 }
3742 } else {
3743 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3744 }
3745 }
3746
3747 /*
3748 * Build a synchronous negotiation message in our message
3749 * buffer based on the input parameters.
3750 */
3751 static void
3752 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3753 u_int period, u_int offset)
3754 {
3755 if (offset == 0)
3756 period = AHD_ASYNC_XFER_PERIOD;
3757 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3758 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3759 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3760 ahd->msgout_buf[ahd->msgout_index++] = period;
3761 ahd->msgout_buf[ahd->msgout_index++] = offset;
3762 ahd->msgout_len += 5;
3763 if (bootverbose) {
3764 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3765 ahd_name(ahd), devinfo->channel, devinfo->target,
3766 devinfo->lun, period, offset);
3767 }
3768 }
3769
3770 /*
3771 * Build a wide negotiateion message in our message
3772 * buffer based on the input parameters.
3773 */
3774 static void
3775 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3776 u_int bus_width)
3777 {
3778 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3779 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3780 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3781 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3782 ahd->msgout_len += 4;
3783 if (bootverbose) {
3784 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
3785 ahd_name(ahd), devinfo->channel, devinfo->target,
3786 devinfo->lun, bus_width);
3787 }
3788 }
3789
3790 /*
3791 * Build a parallel protocol request message in our message
3792 * buffer based on the input parameters.
3793 */
3794 static void
3795 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3796 u_int period, u_int offset, u_int bus_width,
3797 u_int ppr_options)
3798 {
3799 /*
3800 * Always request precompensation from
3801 * the other target if we are running
3802 * at paced syncrates.
3803 */
3804 if (period <= AHD_SYNCRATE_PACED)
3805 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3806 if (offset == 0)
3807 period = AHD_ASYNC_XFER_PERIOD;
3808 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3809 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3810 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3811 ahd->msgout_buf[ahd->msgout_index++] = period;
3812 ahd->msgout_buf[ahd->msgout_index++] = 0;
3813 ahd->msgout_buf[ahd->msgout_index++] = offset;
3814 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3815 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3816 ahd->msgout_len += 8;
3817 if (bootverbose) {
3818 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3819 "offset %x, ppr_options %x\n", ahd_name(ahd),
3820 devinfo->channel, devinfo->target, devinfo->lun,
3821 bus_width, period, offset, ppr_options);
3822 }
3823 }
3824
3825 /*
3826 * Clear any active message state.
3827 */
3828 static void
3829 ahd_clear_msg_state(struct ahd_softc *ahd)
3830 {
3831 ahd_mode_state saved_modes;
3832
3833 saved_modes = ahd_save_modes(ahd);
3834 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3835 ahd->send_msg_perror = 0;
3836 ahd->msg_flags = MSG_FLAG_NONE;
3837 ahd->msgout_len = 0;
3838 ahd->msgin_index = 0;
3839 ahd->msg_type = MSG_TYPE_NONE;
3840 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3841 /*
3842 * The target didn't care to respond to our
3843 * message request, so clear ATN.
3844 */
3845 ahd_outb(ahd, CLRSINT1, CLRATNO);
3846 }
3847 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3848 ahd_outb(ahd, SEQ_FLAGS2,
3849 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3850 ahd_restore_modes(ahd, saved_modes);
3851 }
3852
3853 /*
3854 * Manual message loop handler.
3855 */
3856 static void
3857 ahd_handle_message_phase(struct ahd_softc *ahd)
3858 {
3859 struct ahd_devinfo devinfo;
3860 u_int bus_phase;
3861 int end_session;
3862
3863 ahd_fetch_devinfo(ahd, &devinfo);
3864 end_session = FALSE;
3865 bus_phase = ahd_inb(ahd, LASTPHASE);
3866
3867 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3868 kprintf("LQIRETRY for LQIPHASE_OUTPKT\n");
3869 ahd_outb(ahd, LQCTL2, LQIRETRY);
3870 }
3871 reswitch:
3872 switch (ahd->msg_type) {
3873 case MSG_TYPE_INITIATOR_MSGOUT:
3874 {
3875 int lastbyte;
3876 int phasemis;
3877 int msgdone;
3878
3879 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3880 panic("HOST_MSG_LOOP interrupt with no active message");
3881
3882 #ifdef AHD_DEBUG
3883 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3884 ahd_print_devinfo(ahd, &devinfo);
3885 kprintf("INITIATOR_MSG_OUT");
3886 }
3887 #endif
3888 phasemis = bus_phase != P_MESGOUT;
3889 if (phasemis) {
3890 #ifdef AHD_DEBUG
3891 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3892 kprintf(" PHASEMIS %s\n",
3893 ahd_lookup_phase_entry(bus_phase)
3894 ->phasemsg);
3895 }
3896 #endif
3897 if (bus_phase == P_MESGIN) {
3898 /*
3899 * Change gears and see if
3900 * this messages is of interest to
3901 * us or should be passed back to
3902 * the sequencer.
3903 */
3904 ahd_outb(ahd, CLRSINT1, CLRATNO);
3905 ahd->send_msg_perror = 0;
3906 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3907 ahd->msgin_index = 0;
3908 goto reswitch;
3909 }
3910 end_session = TRUE;
3911 break;
3912 }
3913
3914 if (ahd->send_msg_perror) {
3915 ahd_outb(ahd, CLRSINT1, CLRATNO);
3916 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3917 #ifdef AHD_DEBUG
3918 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3919 kprintf(" byte 0x%x\n", ahd->send_msg_perror);
3920 #endif
3921 /*
3922 * If we are notifying the target of a CRC error
3923 * during packetized operations, the target is
3924 * within its rights to acknowledge our message
3925 * with a busfree.
3926 */
3927 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3928 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3929 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3930
3931 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3932 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3933 break;
3934 }
3935
3936 msgdone = ahd->msgout_index == ahd->msgout_len;
3937 if (msgdone) {
3938 /*
3939 * The target has requested a retry.
3940 * Re-assert ATN, reset our message index to
3941 * 0, and try again.
3942 */
3943 ahd->msgout_index = 0;
3944 ahd_assert_atn(ahd);
3945 }
3946
3947 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3948 if (lastbyte) {
3949 /* Last byte is signified by dropping ATN */
3950 ahd_outb(ahd, CLRSINT1, CLRATNO);
3951 }
3952
3953 /*
3954 * Clear our interrupt status and present
3955 * the next byte on the bus.
3956 */
3957 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3958 #ifdef AHD_DEBUG
3959 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3960 kprintf(" byte 0x%x\n",
3961 ahd->msgout_buf[ahd->msgout_index]);
3962 #endif
3963 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3964 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3965 break;
3966 }
3967 case MSG_TYPE_INITIATOR_MSGIN:
3968 {
3969 int phasemis;
3970 int message_done;
3971
3972 #ifdef AHD_DEBUG
3973 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3974 ahd_print_devinfo(ahd, &devinfo);
3975 kprintf("INITIATOR_MSG_IN");
3976 }
3977 #endif
3978 phasemis = bus_phase != P_MESGIN;
3979 if (phasemis) {
3980 #ifdef AHD_DEBUG
3981 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3982 kprintf(" PHASEMIS %s\n",
3983 ahd_lookup_phase_entry(bus_phase)
3984 ->phasemsg);
3985 }
3986 #endif
3987 ahd->msgin_index = 0;
3988 if (bus_phase == P_MESGOUT
3989 && (ahd->send_msg_perror != 0
3990 || (ahd->msgout_len != 0
3991 && ahd->msgout_index == 0))) {
3992 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3993 goto reswitch;
3994 }
3995 end_session = TRUE;
3996 break;
3997 }
3998
3999 /* Pull the byte in without acking it */
4000 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4001 #ifdef AHD_DEBUG
4002 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4003 kprintf(" byte 0x%x\n",
4004 ahd->msgin_buf[ahd->msgin_index]);
4005 #endif
4006
4007 message_done = ahd_parse_msg(ahd, &devinfo);
4008
4009 if (message_done) {
4010 /*
4011 * Clear our incoming message buffer in case there
4012 * is another message following this one.
4013 */
4014 ahd->msgin_index = 0;
4015
4016 /*
4017 * If this message illicited a response,
4018 * assert ATN so the target takes us to the
4019 * message out phase.
4020 */
4021 if (ahd->msgout_len != 0) {
4022 #ifdef AHD_DEBUG
4023 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4024 ahd_print_devinfo(ahd, &devinfo);
4025 kprintf("Asserting ATN for response\n");
4026 }
4027 #endif
4028 ahd_assert_atn(ahd);
4029 }
4030 } else
4031 ahd->msgin_index++;
4032
4033 if (message_done == MSGLOOP_TERMINATED) {
4034 end_session = TRUE;
4035 } else {
4036 /* Ack the byte */
4037 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4038 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4039 }
4040 break;
4041 }
4042 case MSG_TYPE_TARGET_MSGIN:
4043 {
4044 int msgdone;
4045 int msgout_request;
4046
4047 /*
4048 * By default, the message loop will continue.
4049 */
4050 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4051
4052 if (ahd->msgout_len == 0)
4053 panic("Target MSGIN with no active message");
4054
4055 /*
4056 * If we interrupted a mesgout session, the initiator
4057 * will not know this until our first REQ. So, we
4058 * only honor mesgout requests after we've sent our
4059 * first byte.
4060 */
4061 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4062 && ahd->msgout_index > 0)
4063 msgout_request = TRUE;
4064 else
4065 msgout_request = FALSE;
4066
4067 if (msgout_request) {
4068
4069 /*
4070 * Change gears and see if
4071 * this messages is of interest to
4072 * us or should be passed back to
4073 * the sequencer.
4074 */
4075 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4076 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4077 ahd->msgin_index = 0;
4078 /* Dummy read to REQ for first byte */
4079 ahd_inb(ahd, SCSIDAT);
4080 ahd_outb(ahd, SXFRCTL0,
4081 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4082 break;
4083 }
4084
4085 msgdone = ahd->msgout_index == ahd->msgout_len;
4086 if (msgdone) {
4087 ahd_outb(ahd, SXFRCTL0,
4088 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4089 end_session = TRUE;
4090 break;
4091 }
4092
4093 /*
4094 * Present the next byte on the bus.
4095 */
4096 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4097 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4098 break;
4099 }
4100 case MSG_TYPE_TARGET_MSGOUT:
4101 {
4102 int lastbyte;
4103 int msgdone;
4104
4105 /*
4106 * By default, the message loop will continue.
4107 */
4108 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4109
4110 /*
4111 * The initiator signals that this is
4112 * the last byte by dropping ATN.
4113 */
4114 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4115
4116 /*
4117 * Read the latched byte, but turn off SPIOEN first
4118 * so that we don't inadvertently cause a REQ for the
4119 * next byte.
4120 */
4121 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4122 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4123 msgdone = ahd_parse_msg(ahd, &devinfo);
4124 if (msgdone == MSGLOOP_TERMINATED) {
4125 /*
4126 * The message is *really* done in that it caused
4127 * us to go to bus free. The sequencer has already
4128 * been reset at this point, so pull the ejection
4129 * handle.
4130 */
4131 return;
4132 }
4133
4134 ahd->msgin_index++;
4135
4136 /*
4137 * XXX Read spec about initiator dropping ATN too soon
4138 * and use msgdone to detect it.
4139 */
4140 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4141 ahd->msgin_index = 0;
4142
4143 /*
4144 * If this message illicited a response, transition
4145 * to the Message in phase and send it.
4146 */
4147 if (ahd->msgout_len != 0) {
4148 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4149 ahd_outb(ahd, SXFRCTL0,
4150 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4151 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4152 ahd->msgin_index = 0;
4153 break;
4154 }
4155 }
4156
4157 if (lastbyte)
4158 end_session = TRUE;
4159 else {
4160 /* Ask for the next byte. */
4161 ahd_outb(ahd, SXFRCTL0,
4162 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4163 }
4164
4165 break;
4166 }
4167 default:
4168 panic("Unknown REQINIT message type");
4169 }
4170
4171 if (end_session) {
4172 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4173 kprintf("%s: Returning to Idle Loop\n",
4174 ahd_name(ahd));
4175 ahd_clear_msg_state(ahd);
4176
4177 /*
4178 * Perform the equivalent of a clear_target_state.
4179 */
4180 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4181 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4182 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4183 } else {
4184 ahd_clear_msg_state(ahd);
4185 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4186 }
4187 }
4188 }
4189
4190 /*
4191 * See if we sent a particular extended message to the target.
4192 * If "full" is true, return true only if the target saw the full
4193 * message. If "full" is false, return true if the target saw at
4194 * least the first byte of the message.
4195 */
4196 static int
4197 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4198 {
4199 int found;
4200 u_int index;
4201
4202 found = FALSE;
4203 index = 0;
4204
4205 while (index < ahd->msgout_len) {
4206 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4207 u_int end_index;
4208
4209 end_index = index + 1 + ahd->msgout_buf[index + 1];
4210 if (ahd->msgout_buf[index+2] == msgval
4211 && type == AHDMSG_EXT) {
4212
4213 if (full) {
4214 if (ahd->msgout_index > end_index)
4215 found = TRUE;
4216 } else if (ahd->msgout_index > index)
4217 found = TRUE;
4218 }
4219 index = end_index;
4220 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4221 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4222
4223 /* Skip tag type and tag id or residue param*/
4224 index += 2;
4225 } else {
4226 /* Single byte message */
4227 if (type == AHDMSG_1B
4228 && ahd->msgout_index > index
4229 && (ahd->msgout_buf[index] == msgval
4230 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4231 && msgval == MSG_IDENTIFYFLAG)))
4232 found = TRUE;
4233 index++;
4234 }
4235
4236 if (found)
4237 break;
4238 }
4239 return (found);
4240 }
4241
4242 /*
4243 * Wait for a complete incoming message, parse it, and respond accordingly.
4244 */
4245 static int
4246 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4247 {
4248 struct ahd_initiator_tinfo *tinfo;
4249 struct ahd_tmode_tstate *tstate;
4250 int reject;
4251 int done;
4252 int response;
4253
4254 done = MSGLOOP_IN_PROG;
4255 response = FALSE;
4256 reject = FALSE;
4257 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4258 devinfo->target, &tstate);
4259
4260 /*
4261 * Parse as much of the message as is available,
4262 * rejecting it if we don't support it. When
4263 * the entire message is available and has been
4264 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4265 * that we have parsed an entire message.
4266 *
4267 * In the case of extended messages, we accept the length
4268 * byte outright and perform more checking once we know the
4269 * extended message type.
4270 */
4271 switch (ahd->msgin_buf[0]) {
4272 case MSG_DISCONNECT:
4273 case MSG_SAVEDATAPOINTER:
4274 case MSG_CMDCOMPLETE:
4275 case MSG_RESTOREPOINTERS:
4276 case MSG_IGN_WIDE_RESIDUE:
4277 /*
4278 * End our message loop as these are messages
4279 * the sequencer handles on its own.
4280 */
4281 done = MSGLOOP_TERMINATED;
4282 break;
4283 case MSG_MESSAGE_REJECT:
4284 response = ahd_handle_msg_reject(ahd, devinfo);
4285 /* FALLTHROUGH */
4286 case MSG_NOOP:
4287 done = MSGLOOP_MSGCOMPLETE;
4288 break;
4289 case MSG_EXTENDED:
4290 {
4291 /* Wait for enough of the message to begin validation */
4292 if (ahd->msgin_index < 2)
4293 break;
4294 switch (ahd->msgin_buf[2]) {
4295 case MSG_EXT_SDTR:
4296 {
4297 u_int period;
4298 u_int ppr_options;
4299 u_int offset;
4300 u_int saved_offset;
4301
4302 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4303 reject = TRUE;
4304 break;
4305 }
4306
4307 /*
4308 * Wait until we have both args before validating
4309 * and acting on this message.
4310 *
4311 * Add one to MSG_EXT_SDTR_LEN to account for
4312 * the extended message preamble.
4313 */
4314 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4315 break;
4316
4317 period = ahd->msgin_buf[3];
4318 ppr_options = 0;
4319 saved_offset = offset = ahd->msgin_buf[4];
4320 ahd_devlimited_syncrate(ahd, tinfo, &period,
4321 &ppr_options, devinfo->role);
4322 ahd_validate_offset(ahd, tinfo, period, &offset,
4323 tinfo->curr.width, devinfo->role);
4324 if (bootverbose) {
4325 kprintf("(%s:%c:%d:%d): Received "
4326 "SDTR period %x, offset %x\n\t"
4327 "Filtered to period %x, offset %x\n",
4328 ahd_name(ahd), devinfo->channel,
4329 devinfo->target, devinfo->lun,
4330 ahd->msgin_buf[3], saved_offset,
4331 period, offset);
4332 }
4333 ahd_set_syncrate(ahd, devinfo, period,
4334 offset, ppr_options,
4335 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4336 /*paused*/TRUE);
4337
4338 /*
4339 * See if we initiated Sync Negotiation
4340 * and didn't have to fall down to async
4341 * transfers.
4342 */
4343 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4344 /* We started it */
4345 if (saved_offset != offset) {
4346 /* Went too low - force async */
4347 reject = TRUE;
4348 }
4349 } else {
4350 /*
4351 * Send our own SDTR in reply
4352 */
4353 if (bootverbose
4354 && devinfo->role == ROLE_INITIATOR) {
4355 kprintf("(%s:%c:%d:%d): Target "
4356 "Initiated SDTR\n",
4357 ahd_name(ahd), devinfo->channel,
4358 devinfo->target, devinfo->lun);
4359 }
4360 ahd->msgout_index = 0;
4361 ahd->msgout_len = 0;
4362 ahd_construct_sdtr(ahd, devinfo,
4363 period, offset);
4364 ahd->msgout_index = 0;
4365 response = TRUE;
4366 }
4367 done = MSGLOOP_MSGCOMPLETE;
4368 break;
4369 }
4370 case MSG_EXT_WDTR:
4371 {
4372 u_int bus_width;
4373 u_int saved_width;
4374 u_int sending_reply;
4375
4376 sending_reply = FALSE;
4377 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4378 reject = TRUE;
4379 break;
4380 }
4381
4382 /*
4383 * Wait until we have our arg before validating
4384 * and acting on this message.
4385 *
4386 * Add one to MSG_EXT_WDTR_LEN to account for
4387 * the extended message preamble.
4388 */
4389 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4390 break;
4391
4392 bus_width = ahd->msgin_buf[3];
4393 saved_width = bus_width;
4394 ahd_validate_width(ahd, tinfo, &bus_width,
4395 devinfo->role);
4396 if (bootverbose) {
4397 kprintf("(%s:%c:%d:%d): Received WDTR "
4398 "%x filtered to %x\n",
4399 ahd_name(ahd), devinfo->channel,
4400 devinfo->target, devinfo->lun,
4401 saved_width, bus_width);
4402 }
4403
4404 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4405 /*
4406 * Don't send a WDTR back to the
4407 * target, since we asked first.
4408 * If the width went higher than our
4409 * request, reject it.
4410 */
4411 if (saved_width > bus_width) {
4412 reject = TRUE;
4413 kprintf("(%s:%c:%d:%d): requested %dBit "
4414 "transfers. Rejecting...\n",
4415 ahd_name(ahd), devinfo->channel,
4416 devinfo->target, devinfo->lun,
4417 8 * (0x01 << bus_width));
4418 bus_width = 0;
4419 }
4420 } else {
4421 /*
4422 * Send our own WDTR in reply
4423 */
4424 if (bootverbose
4425 && devinfo->role == ROLE_INITIATOR) {
4426 kprintf("(%s:%c:%d:%d): Target "
4427 "Initiated WDTR\n",
4428 ahd_name(ahd), devinfo->channel,
4429 devinfo->target, devinfo->lun);
4430 }
4431 ahd->msgout_index = 0;
4432 ahd->msgout_len = 0;
4433 ahd_construct_wdtr(ahd, devinfo, bus_width);
4434 ahd->msgout_index = 0;
4435 response = TRUE;
4436 sending_reply = TRUE;
4437 }
4438 /*
4439 * After a wide message, we are async, but
4440 * some devices don't seem to honor this portion
4441 * of the spec. Force a renegotiation of the
4442 * sync component of our transfer agreement even
4443 * if our goal is async. By updating our width
4444 * after forcing the negotiation, we avoid
4445 * renegotiating for width.
4446 */
4447 ahd_update_neg_request(ahd, devinfo, tstate,
4448 tinfo, AHD_NEG_ALWAYS);
4449 ahd_set_width(ahd, devinfo, bus_width,
4450 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4451 /*paused*/TRUE);
4452 if (sending_reply == FALSE && reject == FALSE) {
4453
4454 /*
4455 * We will always have an SDTR to send.
4456 */
4457 ahd->msgout_index = 0;
4458 ahd->msgout_len = 0;
4459 ahd_build_transfer_msg(ahd, devinfo);
4460 ahd->msgout_index = 0;
4461 response = TRUE;
4462 }
4463 done = MSGLOOP_MSGCOMPLETE;
4464 break;
4465 }
4466 case MSG_EXT_PPR:
4467 {
4468 u_int period;
4469 u_int offset;
4470 u_int bus_width;
4471 u_int ppr_options;
4472 u_int saved_width;
4473 u_int saved_offset;
4474 u_int saved_ppr_options;
4475
4476 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4477 reject = TRUE;
4478 break;
4479 }
4480
4481 /*
4482 * Wait until we have all args before validating
4483 * and acting on this message.
4484 *
4485 * Add one to MSG_EXT_PPR_LEN to account for
4486 * the extended message preamble.
4487 */
4488 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4489 break;
4490
4491 period = ahd->msgin_buf[3];
4492 offset = ahd->msgin_buf[5];
4493 bus_width = ahd->msgin_buf[6];
4494 saved_width = bus_width;
4495 ppr_options = ahd->msgin_buf[7];
4496 /*
4497 * According to the spec, a DT only
4498 * period factor with no DT option
4499 * set implies async.
4500 */
4501 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4502 && period <= 9)
4503 offset = 0;
4504 saved_ppr_options = ppr_options;
4505 saved_offset = offset;
4506
4507 /*
4508 * Transfer options are only available if we
4509 * are negotiating wide.
4510 */
4511 if (bus_width == 0)
4512 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4513
4514 ahd_validate_width(ahd, tinfo, &bus_width,
4515 devinfo->role);
4516 ahd_devlimited_syncrate(ahd, tinfo, &period,
4517 &ppr_options, devinfo->role);
4518 ahd_validate_offset(ahd, tinfo, period, &offset,
4519 bus_width, devinfo->role);
4520
4521 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4522 /*
4523 * If we are unable to do any of the
4524 * requested options (we went too low),
4525 * then we'll have to reject the message.
4526 */
4527 if (saved_width > bus_width
4528 || saved_offset != offset
4529 || saved_ppr_options != ppr_options) {
4530 reject = TRUE;
4531 period = 0;
4532 offset = 0;
4533 bus_width = 0;
4534 ppr_options = 0;
4535 }
4536 } else {
4537 if (devinfo->role != ROLE_TARGET)
4538 kprintf("(%s:%c:%d:%d): Target "
4539 "Initiated PPR\n",
4540 ahd_name(ahd), devinfo->channel,
4541 devinfo->target, devinfo->lun);
4542 else
4543 kprintf("(%s:%c:%d:%d): Initiator "
4544 "Initiated PPR\n",
4545 ahd_name(ahd), devinfo->channel,
4546 devinfo->target, devinfo->lun);
4547 ahd->msgout_index = 0;
4548 ahd->msgout_len = 0;
4549 ahd_construct_ppr(ahd, devinfo, period, offset,
4550 bus_width, ppr_options);
4551 ahd->msgout_index = 0;
4552 response = TRUE;
4553 }
4554 if (bootverbose) {
4555 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
4556 "period %x, offset %x,options %x\n"
4557 "\tFiltered to width %x, period %x, "
4558 "offset %x, options %x\n",
4559 ahd_name(ahd), devinfo->channel,
4560 devinfo->target, devinfo->lun,
4561 saved_width, ahd->msgin_buf[3],
4562 saved_offset, saved_ppr_options,
4563 bus_width, period, offset, ppr_options);
4564 }
4565 ahd_set_width(ahd, devinfo, bus_width,
4566 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4567 /*paused*/TRUE);
4568 ahd_set_syncrate(ahd, devinfo, period,
4569 offset, ppr_options,
4570 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4571 /*paused*/TRUE);
4572
4573 done = MSGLOOP_MSGCOMPLETE;
4574 break;
4575 }
4576 default:
4577 /* Unknown extended message. Reject it. */
4578 reject = TRUE;
4579 break;
4580 }
4581 break;
4582 }
4583 #ifdef AHD_TARGET_MODE
4584 case MSG_BUS_DEV_RESET:
4585 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4586 CAM_BDR_SENT,
4587 "Bus Device Reset Received",
4588 /*verbose_level*/0);
4589 ahd_restart(ahd);
4590 done = MSGLOOP_TERMINATED;
4591 break;
4592 case MSG_ABORT_TAG:
4593 case MSG_ABORT:
4594 case MSG_CLEAR_QUEUE:
4595 {
4596 int tag;
4597
4598 /* Target mode messages */
4599 if (devinfo->role != ROLE_TARGET) {
4600 reject = TRUE;
4601 break;
4602 }
4603 tag = SCB_LIST_NULL;
4604 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4605 tag = ahd_inb(ahd, INITIATOR_TAG);
4606 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4607 devinfo->lun, tag, ROLE_TARGET,
4608 CAM_REQ_ABORTED);
4609
4610 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4611 if (tstate != NULL) {
4612 struct ahd_tmode_lstate* lstate;
4613
4614 lstate = tstate->enabled_luns[devinfo->lun];
4615 if (lstate != NULL) {
4616 ahd_queue_lstate_event(ahd, lstate,
4617 devinfo->our_scsiid,
4618 ahd->msgin_buf[0],
4619 /*arg*/tag);
4620 ahd_send_lstate_events(ahd, lstate);
4621 }
4622 }
4623 ahd_restart(ahd);
4624 done = MSGLOOP_TERMINATED;
4625 break;
4626 }
4627 #endif
4628 case MSG_QAS_REQUEST:
4629 #ifdef AHD_DEBUG
4630 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4631 kprintf("%s: QAS request. SCSISIGI == 0x%x\n",
4632 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4633 #endif
4634 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4635 /* FALLTHROUGH */
4636 case MSG_TERM_IO_PROC:
4637 default:
4638 reject = TRUE;
4639 break;
4640 }
4641
4642 if (reject) {
4643 /*
4644 * Setup to reject the message.
4645 */
4646 ahd->msgout_index = 0;
4647 ahd->msgout_len = 1;
4648 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4649 done = MSGLOOP_MSGCOMPLETE;
4650 response = TRUE;
4651 }
4652
4653 if (done != MSGLOOP_IN_PROG && !response)
4654 /* Clear the outgoing message buffer */
4655 ahd->msgout_len = 0;
4656
4657 return (done);
4658 }
4659
4660 /*
4661 * Process a message reject message.
4662 */
4663 static int
4664 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4665 {
4666 /*
4667 * What we care about here is if we had an
4668 * outstanding SDTR or WDTR message for this
4669 * target. If we did, this is a signal that
4670 * the target is refusing negotiation.
4671 */
4672 struct scb *scb;
4673 struct ahd_initiator_tinfo *tinfo;
4674 struct ahd_tmode_tstate *tstate;
4675 u_int scb_index;
4676 u_int last_msg;
4677 int response = 0;
4678
4679 scb_index = ahd_get_scbptr(ahd);
4680 scb = ahd_lookup_scb(ahd, scb_index);
4681 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4682 devinfo->our_scsiid,
4683 devinfo->target, &tstate);
4684 /* Might be necessary */
4685 last_msg = ahd_inb(ahd, LAST_MSG);
4686
4687 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4688 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4689 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4690 /*
4691 * Target may not like our SPI-4 PPR Options.
4692 * Attempt to negotiate 80MHz which will turn
4693 * off these options.
4694 */
4695 if (bootverbose) {
4696 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4697 "Trying simple U160 PPR\n",
4698 ahd_name(ahd), devinfo->channel,
4699 devinfo->target, devinfo->lun);
4700 }
4701 tinfo->goal.period = AHD_SYNCRATE_DT;
4702 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4703 | MSG_EXT_PPR_QAS_REQ
4704 | MSG_EXT_PPR_DT_REQ;
4705 } else {
4706 /*
4707 * Target does not support the PPR message.
4708 * Attempt to negotiate SPI-2 style.
4709 */
4710 if (bootverbose) {
4711 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4712 "Trying WDTR/SDTR\n",
4713 ahd_name(ahd), devinfo->channel,
4714 devinfo->target, devinfo->lun);
4715 }
4716 tinfo->goal.ppr_options = 0;
4717 tinfo->curr.transport_version = 2;
4718 tinfo->goal.transport_version = 2;
4719 }
4720 ahd->msgout_index = 0;
4721 ahd->msgout_len = 0;
4722 ahd_build_transfer_msg(ahd, devinfo);
4723 ahd->msgout_index = 0;
4724 response = 1;
4725 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4726
4727 /* note 8bit xfers */
4728 kprintf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4729 "8bit transfers\n", ahd_name(ahd),
4730 devinfo->channel, devinfo->target, devinfo->lun);
4731 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4732 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4733 /*paused*/TRUE);
4734 /*
4735 * No need to clear the sync rate. If the target
4736 * did not accept the command, our syncrate is
4737 * unaffected. If the target started the negotiation,
4738 * but rejected our response, we already cleared the
4739 * sync rate before sending our WDTR.
4740 */
4741 if (tinfo->goal.offset != tinfo->curr.offset) {
4742
4743 /* Start the sync negotiation */
4744 ahd->msgout_index = 0;
4745 ahd->msgout_len = 0;
4746 ahd_build_transfer_msg(ahd, devinfo);
4747 ahd->msgout_index = 0;
4748 response = 1;
4749 }
4750 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4751 /* note asynch xfers and clear flag */
4752 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4753 /*offset*/0, /*ppr_options*/0,
4754 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4755 /*paused*/TRUE);
4756 kprintf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4757 "Using asynchronous transfers\n",
4758 ahd_name(ahd), devinfo->channel,
4759 devinfo->target, devinfo->lun);
4760 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4761 int tag_type;
4762 int mask;
4763
4764 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4765
4766 if (tag_type == MSG_SIMPLE_TASK) {
4767 kprintf("(%s:%c:%d:%d): refuses tagged commands. "
4768 "Performing non-tagged I/O\n", ahd_name(ahd),
4769 devinfo->channel, devinfo->target, devinfo->lun);
4770 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4771 mask = ~0x23;
4772 } else {
4773 kprintf("(%s:%c:%d:%d): refuses %s tagged commands. "
4774 "Performing simple queue tagged I/O only\n",
4775 ahd_name(ahd), devinfo->channel, devinfo->target,
4776 devinfo->lun, tag_type == MSG_ORDERED_TASK
4777 ? "ordered" : "head of queue");
4778 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4779 mask = ~0x03;
4780 }
4781
4782 /*
4783 * Resend the identify for this CCB as the target
4784 * may believe that the selection is invalid otherwise.
4785 */
4786 ahd_outb(ahd, SCB_CONTROL,
4787 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4788 scb->hscb->control &= mask;
4789 aic_set_transaction_tag(scb, /*enabled*/FALSE,
4790 /*type*/MSG_SIMPLE_TASK);
4791 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4792 ahd_assert_atn(ahd);
4793 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4794 SCB_GET_TAG(scb));
4795
4796 /*
4797 * Requeue all tagged commands for this target
4798 * currently in our posession so they can be
4799 * converted to untagged commands.
4800 */
4801 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4802 SCB_GET_CHANNEL(ahd, scb),
4803 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4804 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4805 SEARCH_COMPLETE);
4806 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4807 /*
4808 * Most likely the device believes that we had
4809 * previously negotiated packetized.
4810 */
4811 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4812 | MSG_FLAG_IU_REQ_CHANGED;
4813
4814 ahd_force_renegotiation(ahd, devinfo);
4815 ahd->msgout_index = 0;
4816 ahd->msgout_len = 0;
4817 ahd_build_transfer_msg(ahd, devinfo);
4818 ahd->msgout_index = 0;
4819 response = 1;
4820 } else {
4821 /*
4822 * Otherwise, we ignore it.
4823 */
4824 kprintf("%s:%c:%d: Message reject for %x -- ignored\n",
4825 ahd_name(ahd), devinfo->channel, devinfo->target,
4826 last_msg);
4827 }
4828 return (response);
4829 }
4830
4831 /*
4832 * Process an ingnore wide residue message.
4833 */
4834 static void
4835 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4836 {
4837 u_int scb_index;
4838 struct scb *scb;
4839
4840 scb_index = ahd_get_scbptr(ahd);
4841 scb = ahd_lookup_scb(ahd, scb_index);
4842 /*
4843 * XXX Actually check data direction in the sequencer?
4844 * Perhaps add datadir to some spare bits in the hscb?
4845 */
4846 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4847 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
4848 /*
4849 * Ignore the message if we haven't
4850 * seen an appropriate data phase yet.
4851 */
4852 } else {
4853 /*
4854 * If the residual occurred on the last
4855 * transfer and the transfer request was
4856 * expected to end on an odd count, do
4857 * nothing. Otherwise, subtract a byte
4858 * and update the residual count accordingly.
4859 */
4860 uint32_t sgptr;
4861
4862 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4863 if ((sgptr & SG_LIST_NULL) != 0
4864 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4865 & SCB_XFERLEN_ODD) != 0) {
4866 /*
4867 * If the residual occurred on the last
4868 * transfer and the transfer request was
4869 * expected to end on an odd count, do
4870 * nothing.
4871 */
4872 } else {
4873 uint32_t data_cnt;
4874 uint64_t data_addr;
4875 uint32_t sglen;
4876
4877 /* Pull in the rest of the sgptr */
4878 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4879 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4880 if ((sgptr & SG_LIST_NULL) != 0) {
4881 /*
4882 * The residual data count is not updated
4883 * for the command run to completion case.
4884 * Explicitly zero the count.
4885 */
4886 data_cnt &= ~AHD_SG_LEN_MASK;
4887 }
4888 data_addr = ahd_inq(ahd, SHADDR);
4889 data_cnt += 1;
4890 data_addr -= 1;
4891 sgptr &= SG_PTR_MASK;
4892 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4893 struct ahd_dma64_seg *sg;
4894
4895 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4896
4897 /*
4898 * The residual sg ptr points to the next S/G
4899 * to load so we must go back one.
4900 */
4901 sg--;
4902 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4903 if (sg != scb->sg_list
4904 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4905
4906 sg--;
4907 sglen = aic_le32toh(sg->len);
4908 /*
4909 * Preserve High Address and SG_LIST
4910 * bits while setting the count to 1.
4911 */
4912 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4913 data_addr = aic_le64toh(sg->addr)
4914 + (sglen & AHD_SG_LEN_MASK)
4915 - 1;
4916
4917 /*
4918 * Increment sg so it points to the
4919 * "next" sg.
4920 */
4921 sg++;
4922 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4923 sg);
4924 }
4925 } else {
4926 struct ahd_dma_seg *sg;
4927
4928 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4929
4930 /*
4931 * The residual sg ptr points to the next S/G
4932 * to load so we must go back one.
4933 */
4934 sg--;
4935 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4936 if (sg != scb->sg_list
4937 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4938
4939 sg--;
4940 sglen = aic_le32toh(sg->len);
4941 /*
4942 * Preserve High Address and SG_LIST
4943 * bits while setting the count to 1.
4944 */
4945 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4946 data_addr = aic_le32toh(sg->addr)
4947 + (sglen & AHD_SG_LEN_MASK)
4948 - 1;
4949
4950 /*
4951 * Increment sg so it points to the
4952 * "next" sg.
4953 */
4954 sg++;
4955 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4956 sg);
4957 }
4958 }
4959 /*
4960 * Toggle the "oddness" of the transfer length
4961 * to handle this mid-transfer ignore wide
4962 * residue. This ensures that the oddness is
4963 * correct for subsequent data transfers.
4964 */
4965 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4966 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4967 ^ SCB_XFERLEN_ODD);
4968
4969 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4970 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4971 /*
4972 * The FIFO's pointers will be updated if/when the
4973 * sequencer re-enters a data phase.
4974 */
4975 }
4976 }
4977 }
4978
4979
4980 /*
4981 * Reinitialize the data pointers for the active transfer
4982 * based on its current residual.
4983 */
4984 static void
4985 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4986 {
4987 struct scb *scb;
4988 ahd_mode_state saved_modes;
4989 u_int scb_index;
4990 u_int wait;
4991 uint32_t sgptr;
4992 uint32_t resid;
4993 uint64_t dataptr;
4994
4995 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
4996 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
4997
4998 scb_index = ahd_get_scbptr(ahd);
4999 scb = ahd_lookup_scb(ahd, scb_index);
5000
5001 /*
5002 * Release and reacquire the FIFO so we
5003 * have a clean slate.
5004 */
5005 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5006 wait = 1000;
5007 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5008 aic_delay(100);
5009 if (wait == 0) {
5010 ahd_print_path(ahd, scb);
5011 kprintf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5012 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5013 }
5014 saved_modes = ahd_save_modes(ahd);
5015 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5016 ahd_outb(ahd, DFFSTAT,
5017 ahd_inb(ahd, DFFSTAT)
5018 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5019
5020 /*
5021 * Determine initial values for data_addr and data_cnt
5022 * for resuming the data phase.
5023 */
5024 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5025 sgptr &= SG_PTR_MASK;
5026
5027 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5028 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5029 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5030
5031 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5032 struct ahd_dma64_seg *sg;
5033
5034 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5035
5036 /* The residual sg_ptr always points to the next sg */
5037 sg--;
5038
5039 dataptr = aic_le64toh(sg->addr)
5040 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5041 - resid;
5042 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5043 } else {
5044 struct ahd_dma_seg *sg;
5045
5046 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5047
5048 /* The residual sg_ptr always points to the next sg */
5049 sg--;
5050
5051 dataptr = aic_le32toh(sg->addr)
5052 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5053 - resid;
5054 ahd_outb(ahd, HADDR + 4,
5055 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5056 }
5057 ahd_outl(ahd, HADDR, dataptr);
5058 ahd_outb(ahd, HCNT + 2, resid >> 16);
5059 ahd_outb(ahd, HCNT + 1, resid >> 8);
5060 ahd_outb(ahd, HCNT, resid);
5061 }
5062
5063 /*
5064 * Handle the effects of issuing a bus device reset message.
5065 */
5066 static void
5067 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5068 u_int lun, cam_status status, char *message,
5069 int verbose_level)
5070 {
5071 #ifdef AHD_TARGET_MODE
5072 struct ahd_tmode_tstate* tstate;
5073 #endif
5074 int found;
5075
5076 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5077 lun, SCB_LIST_NULL, devinfo->role,
5078 status);
5079
5080 #ifdef AHD_TARGET_MODE
5081 /*
5082 * Send an immediate notify ccb to all target mord peripheral
5083 * drivers affected by this action.
5084 */
5085 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5086 if (tstate != NULL) {
5087 u_int cur_lun;
5088 u_int max_lun;
5089
5090 if (lun != CAM_LUN_WILDCARD) {
5091 cur_lun = 0;
5092 max_lun = AHD_NUM_LUNS - 1;
5093 } else {
5094 cur_lun = lun;
5095 max_lun = lun;
5096 }
5097 for (cur_lun <= max_lun; cur_lun++) {
5098 struct ahd_tmode_lstate* lstate;
5099
5100 lstate = tstate->enabled_luns[cur_lun];
5101 if (lstate == NULL)
5102 continue;
5103
5104 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5105 MSG_BUS_DEV_RESET, /*arg*/0);
5106 ahd_send_lstate_events(ahd, lstate);
5107 }
5108 }
5109 #endif
5110
5111 /*
5112 * Go back to async/narrow transfers and renegotiate.
5113 */
5114 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5115 AHD_TRANS_CUR, /*paused*/TRUE);
5116 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5117 /*ppr_options*/0, AHD_TRANS_CUR,
5118 /*paused*/TRUE);
5119
5120 if (status != CAM_SEL_TIMEOUT)
5121 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5122 lun, AC_SENT_BDR, NULL);
5123
5124 if (message != NULL
5125 && (verbose_level <= bootverbose))
5126 kprintf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5127 message, devinfo->channel, devinfo->target, found);
5128 }
5129
5130 #ifdef AHD_TARGET_MODE
5131 static void
5132 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5133 struct scb *scb)
5134 {
5135
5136 /*
5137 * To facilitate adding multiple messages together,
5138 * each routine should increment the index and len
5139 * variables instead of setting them explicitly.
5140 */
5141 ahd->msgout_index = 0;
5142 ahd->msgout_len = 0;
5143
5144 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5145 ahd_build_transfer_msg(ahd, devinfo);
5146 else
5147 panic("ahd_intr: AWAITING target message with no message");
5148
5149 ahd->msgout_index = 0;
5150 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5151 }
5152 #endif
5153 /**************************** Initialization **********************************/
5154 static u_int
5155 ahd_sglist_size(struct ahd_softc *ahd)
5156 {
5157 bus_size_t list_size;
5158
5159 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5160 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5161 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5162 return (list_size);
5163 }
5164
5165 /*
5166 * Calculate the optimum S/G List allocation size. S/G elements used
5167 * for a given transaction must be physically contiguous. Assume the
5168 * OS will allocate full pages to us, so it doesn't make sense to request
5169 * less than a page.
5170 */
5171 static u_int
5172 ahd_sglist_allocsize(struct ahd_softc *ahd)
5173 {
5174 bus_size_t sg_list_increment;
5175 bus_size_t sg_list_size;
5176 bus_size_t max_list_size;
5177 bus_size_t best_list_size;
5178
5179 /* Start out with the minimum required for AHD_NSEG. */
5180 sg_list_increment = ahd_sglist_size(ahd);
5181 sg_list_size = sg_list_increment;
5182
5183 /* Get us as close as possible to a page in size. */
5184 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5185 sg_list_size += sg_list_increment;
5186
5187 /*
5188 * Try to reduce the amount of wastage by allocating
5189 * multiple pages.
5190 */
5191 best_list_size = sg_list_size;
5192 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5193 if (max_list_size < 4 * PAGE_SIZE)
5194 max_list_size = 4 * PAGE_SIZE;
5195 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5196 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5197 while ((sg_list_size + sg_list_increment) <= max_list_size
5198 && (sg_list_size % PAGE_SIZE) != 0) {
5199 bus_size_t new_mod;
5200 bus_size_t best_mod;
5201
5202 sg_list_size += sg_list_increment;
5203 new_mod = sg_list_size % PAGE_SIZE;
5204 best_mod = best_list_size % PAGE_SIZE;
5205 if (new_mod > best_mod || new_mod == 0) {
5206 best_list_size = sg_list_size;
5207 }
5208 }
5209 return (best_list_size);
5210 }
5211
5212 /*
5213 * Allocate a controller structure for a new device
5214 * and perform initial initializion.
5215 */
5216 struct ahd_softc *
5217 ahd_alloc(void *platform_arg, char *name)
5218 {
5219 struct ahd_softc *ahd;
5220
5221 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5222 ahd = kmalloc(sizeof(*ahd), M_DEVBUF, M_INTWAIT);
5223 #else
5224 ahd = device_get_softc((device_t)platform_arg);
5225 #endif
5226 memset(ahd, 0, sizeof(*ahd));
5227 ahd->seep_config = kmalloc(sizeof(*ahd->seep_config),M_DEVBUF,M_INTWAIT);
5228 LIST_INIT(&ahd->pending_scbs);
5229 LIST_INIT(&ahd->timedout_scbs);
5230 /* We don't know our unit number until the OSM sets it */
5231 ahd->name = name;
5232 ahd->unit = -1;
5233 ahd->description = NULL;
5234 ahd->bus_description = NULL;
5235 ahd->channel = 'A';
5236 ahd->chip = AHD_NONE;
5237 ahd->features = AHD_FENONE;
5238 ahd->bugs = AHD_BUGNONE;
5239 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5240 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5241 aic_timer_init(&ahd->reset_timer);
5242 aic_timer_init(&ahd->stat_timer);
5243 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5244 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5245 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5246 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5247 ahd->int_coalescing_stop_threshold =
5248 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5249
5250 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5251 ahd_free(ahd);
5252 ahd = NULL;
5253 }
5254 #ifdef AHD_DEBUG
5255 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5256 kprintf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5257 ahd_name(ahd), (u_int)sizeof(struct scb),
5258 (u_int)sizeof(struct hardware_scb));
5259 }
5260 #endif
5261 return (ahd);
5262 }
5263
5264 int
5265 ahd_softc_init(struct ahd_softc *ahd)
5266 {
5267
5268 ahd->unpause = 0;
5269 ahd->pause = PAUSE;
5270 return (0);
5271 }
5272
5273 void
5274 ahd_softc_insert(struct ahd_softc *ahd)
5275 {
5276 struct ahd_softc *list_ahd;
5277
5278 #if AIC_PCI_CONFIG > 0
5279 /*
5280 * Second Function PCI devices need to inherit some
5281 * settings from function 0.
5282 */
5283 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5284 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5285 aic_dev_softc_t list_pci;
5286 aic_dev_softc_t pci;
5287
5288 list_pci = list_ahd->dev_softc;
5289 pci = ahd->dev_softc;
5290 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5291 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
5292 struct ahd_softc *master;
5293 struct ahd_softc *slave;
5294
5295 if (aic_get_pci_function(list_pci) == 0) {
5296 master = list_ahd;
5297 slave = ahd;
5298 } else {
5299 master = ahd;
5300 slave = list_ahd;
5301 }
5302 slave->flags &= ~AHD_BIOS_ENABLED;
5303 slave->flags |=
5304 master->flags & AHD_BIOS_ENABLED;
5305 break;
5306 }
5307 }
5308 }
5309 #endif
5310
5311 /*
5312 * Insertion sort into our list of softcs.
5313 */
5314 list_ahd = TAILQ_FIRST(&ahd_tailq);
5315 while (list_ahd != NULL
5316 && ahd_softc_comp(ahd, list_ahd) <= 0)
5317 list_ahd = TAILQ_NEXT(list_ahd, links);
5318 if (list_ahd != NULL)
5319 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5320 else
5321 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5322 ahd->init_level++;
5323 }
5324
5325 /*
5326 * Verify that the passed in softc pointer is for a
5327 * controller that is still configured.
5328 */
5329 struct ahd_softc *
5330 ahd_find_softc(struct ahd_softc *ahd)
5331 {
5332 struct ahd_softc *list_ahd;
5333
5334 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5335 if (list_ahd == ahd)
5336 return (ahd);
5337 }
5338 return (NULL);
5339 }
5340
5341 void
5342 ahd_set_unit(struct ahd_softc *ahd, int unit)
5343 {
5344 ahd->unit = unit;
5345 }
5346
5347 void
5348 ahd_set_name(struct ahd_softc *ahd, char *name)
5349 {
5350 if (ahd->name != NULL)
5351 kfree(ahd->name, M_DEVBUF);
5352 ahd->name = name;
5353 }
5354
5355 void
5356 ahd_free(struct ahd_softc *ahd)
5357 {
5358 int i;
5359
5360 ahd_terminate_recovery_thread(ahd);
5361 switch (ahd->init_level) {
5362 default:
5363 case 5:
5364 ahd_shutdown(ahd);
5365 /* FALLTHROUGH */
5366 case 4:
5367 aic_dmamap_unload(ahd, ahd->shared_data_dmat,
5368 ahd->shared_data_map.dmamap);
5369 /* FALLTHROUGH */
5370 case 3:
5371 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5372 ahd->shared_data_map.dmamap);
5373 aic_dmamap_destroy(ahd, ahd->shared_data_dmat,
5374 ahd->shared_data_map.dmamap);
5375 /* FALLTHROUGH */
5376 case 2:
5377 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5378 case 1:
5379 #ifndef __linux__
5380 aic_dma_tag_destroy(ahd, ahd->buffer_dmat);
5381 #endif
5382 break;
5383 case 0:
5384 break;
5385 }
5386
5387 #ifndef __linux__
5388 aic_dma_tag_destroy(ahd, ahd->parent_dmat);
5389 #endif
5390 ahd_platform_free(ahd);
5391 ahd_fini_scbdata(ahd);
5392 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5393 struct ahd_tmode_tstate *tstate;
5394
5395 tstate = ahd->enabled_targets[i];
5396 if (tstate != NULL) {
5397 #if AHD_TARGET_MODE
5398 int j;
5399
5400 for (j = 0; j < AHD_NUM_LUNS; j++) {
5401 struct ahd_tmode_lstate *lstate;
5402
5403 lstate = tstate->enabled_luns[j];
5404 if (lstate != NULL) {
5405 xpt_free_path(lstate->path);
5406 kfree(lstate, M_DEVBUF);
5407 }
5408 }
5409 #endif
5410 kfree(tstate, M_DEVBUF);
5411 }
5412 }
5413 #if AHD_TARGET_MODE
5414 if (ahd->black_hole != NULL) {
5415 xpt_free_path(ahd->black_hole->path);
5416 kfree(ahd->black_hole, M_DEVBUF);
5417 }
5418 #endif
5419 if (ahd->name != NULL)
5420 kfree(ahd->name, M_DEVBUF);
5421 if (ahd->seep_config != NULL)
5422 kfree(ahd->seep_config, M_DEVBUF);
5423 if (ahd->saved_stack != NULL)
5424 kfree(ahd->saved_stack, M_DEVBUF);
5425 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5426 kfree(ahd, M_DEVBUF);
5427 #endif
5428 return;
5429 }
5430
5431 void
5432 ahd_shutdown(void *arg)
5433 {
5434 struct ahd_softc *ahd;
5435
5436 ahd = (struct ahd_softc *)arg;
5437
5438 /*
5439 * Stop periodic timer callbacks.
5440 */
5441 aic_timer_stop(&ahd->reset_timer);
5442 aic_timer_stop(&ahd->stat_timer);
5443
5444 /* This will reset most registers to 0, but not all */
5445 ahd_reset(ahd, /*reinit*/FALSE);
5446 }
5447
5448 /*
5449 * Reset the controller and record some information about it
5450 * that is only available just after a reset. If "reinit" is
5451 * non-zero, this reset occured after initial configuration
5452 * and the caller requests that the chip be fully reinitialized
5453 * to a runable state. Chip interrupts are *not* enabled after
5454 * a reinitialization. The caller must enable interrupts via
5455 * ahd_intr_enable().
5456 */
5457 int
5458 ahd_reset(struct ahd_softc *ahd, int reinit)
5459 {
5460 u_int sxfrctl1;
5461 int wait;
5462 uint32_t cmd;
5463
5464 /*
5465 * Preserve the value of the SXFRCTL1 register for all channels.
5466 * It contains settings that affect termination and we don't want
5467 * to disturb the integrity of the bus.
5468 */
5469 ahd_pause(ahd);
5470 ahd_update_modes(ahd);
5471 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5472 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5473
5474 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5475 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5476 uint32_t mod_cmd;
5477
5478 /*
5479 * A4 Razor #632
5480 * During the assertion of CHIPRST, the chip
5481 * does not disable its parity logic prior to
5482 * the start of the reset. This may cause a
5483 * parity error to be detected and thus a
5484 * spurious SERR or PERR assertion. Disble
5485 * PERR and SERR responses during the CHIPRST.
5486 */
5487 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5488 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5489 mod_cmd, /*bytes*/2);
5490 }
5491 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5492
5493 /*
5494 * Ensure that the reset has finished. We delay 1000us
5495 * prior to reading the register to make sure the chip
5496 * has sufficiently completed its reset to handle register
5497 * accesses.
5498 */
5499 wait = 1000;
5500 do {
5501 aic_delay(1000);
5502 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5503
5504 if (wait == 0) {
5505 kprintf("%s: WARNING - Failed chip reset! "
5506 "Trying to initialize anyway.\n", ahd_name(ahd));
5507 }
5508 ahd_outb(ahd, HCNTRL, ahd->pause);
5509
5510 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5511 /*
5512 * Clear any latched PCI error status and restore
5513 * previous SERR and PERR response enables.
5514 */
5515 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5516 0xFF, /*bytes*/1);
5517 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5518 cmd, /*bytes*/2);
5519 }
5520
5521 /*
5522 * Mode should be SCSI after a chip reset, but lets
5523 * set it just to be safe. We touch the MODE_PTR
5524 * register directly so as to bypass the lazy update
5525 * code in ahd_set_modes().
5526 */
5527 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5528 ahd_outb(ahd, MODE_PTR,
5529 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5530
5531 /*
5532 * Restore SXFRCTL1.
5533 *
5534 * We must always initialize STPWEN to 1 before we
5535 * restore the saved values. STPWEN is initialized
5536 * to a tri-state condition which can only be cleared
5537 * by turning it on.
5538 */
5539 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5540 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5541
5542 /* Determine chip configuration */
5543 ahd->features &= ~AHD_WIDE;
5544 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5545 ahd->features |= AHD_WIDE;
5546
5547 /*
5548 * If a recovery action has forced a chip reset,
5549 * re-initialize the chip to our liking.
5550 */
5551 if (reinit != 0)
5552 ahd_chip_init(ahd);
5553
5554 return (0);
5555 }
5556
5557 /*
5558 * Determine the number of SCBs available on the controller
5559 */
5560 int
5561 ahd_probe_scbs(struct ahd_softc *ahd) {
5562 int i;
5563
5564 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5565 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5566 for (i = 0; i < AHD_SCB_MAX; i++) {
5567 int j;
5568
5569 ahd_set_scbptr(ahd, i);
5570 ahd_outw(ahd, SCB_BASE, i);
5571 for (j = 2; j < 64; j++)
5572 ahd_outb(ahd, SCB_BASE+j, 0);
5573 /* Start out life as unallocated (needing an abort) */
5574 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5575 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5576 break;
5577 ahd_set_scbptr(ahd, 0);
5578 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5579 break;
5580 }
5581 return (i);
5582 }
5583
5584 static void
5585 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5586 {
5587 bus_addr_t *baddr;
5588
5589 baddr = (bus_addr_t *)arg;
5590 *baddr = segs->ds_addr;
5591 }
5592
5593 static void
5594 ahd_initialize_hscbs(struct ahd_softc *ahd)
5595 {
5596 int i;
5597
5598 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5599 ahd_set_scbptr(ahd, i);
5600
5601 /* Clear the control byte. */
5602 ahd_outb(ahd, SCB_CONTROL, 0);
5603
5604 /* Set the next pointer */
5605 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5606 }
5607 }
5608
5609 static int
5610 ahd_init_scbdata(struct ahd_softc *ahd)
5611 {
5612 struct scb_data *scb_data;
5613 int i;
5614
5615 scb_data = &ahd->scb_data;
5616 TAILQ_INIT(&scb_data->free_scbs);
5617 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5618 LIST_INIT(&scb_data->free_scb_lists[i]);
5619 LIST_INIT(&scb_data->any_dev_free_scb_list);
5620 SLIST_INIT(&scb_data->hscb_maps);
5621 SLIST_INIT(&scb_data->sg_maps);
5622 SLIST_INIT(&scb_data->sense_maps);
5623
5624 /* Determine the number of hardware SCBs and initialize them */
5625 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5626 if (scb_data->maxhscbs == 0) {
5627 kprintf("%s: No SCB space found\n", ahd_name(ahd));
5628 return (ENXIO);
5629 }
5630
5631 ahd_initialize_hscbs(ahd);
5632
5633 /*
5634 * Create our DMA tags. These tags define the kinds of device
5635 * accessible memory allocations and memory mappings we will
5636 * need to perform during normal operation.
5637 *
5638 * Unless we need to further restrict the allocation, we rely
5639 * on the restrictions of the parent dmat, hence the common
5640 * use of MAXADDR and MAXSIZE.
5641 */
5642
5643 /* DMA tag for our hardware scb structures */
5644 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5645 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5646 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5647 /*highaddr*/BUS_SPACE_MAXADDR,
5648 /*filter*/NULL, /*filterarg*/NULL,
5649 PAGE_SIZE, /*nsegments*/1,
5650 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5651 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5652 goto error_exit;
5653 }
5654
5655 scb_data->init_level++;
5656
5657 /* DMA tag for our S/G structures. */
5658 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5659 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5660 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5661 /*highaddr*/BUS_SPACE_MAXADDR,
5662 /*filter*/NULL, /*filterarg*/NULL,
5663 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5664 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5665 /*flags*/0, &scb_data->sg_dmat) != 0) {
5666 goto error_exit;
5667 }
5668 #ifdef AHD_DEBUG
5669 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5670 kprintf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5671 ahd_sglist_allocsize(ahd));
5672 #endif
5673
5674 scb_data->init_level++;
5675
5676 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5677 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5678 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5679 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5680 /*highaddr*/BUS_SPACE_MAXADDR,
5681 /*filter*/NULL, /*filterarg*/NULL,
5682 PAGE_SIZE, /*nsegments*/1,
5683 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5684 /*flags*/0, &scb_data->sense_dmat) != 0) {
5685 goto error_exit;
5686 }
5687
5688 scb_data->init_level++;
5689
5690 /* Perform initial CCB allocation */
5691 ahd_alloc_scbs(ahd);
5692
5693 if (scb_data->numscbs == 0) {
5694 kprintf("%s: ahd_init_scbdata - "
5695 "Unable to allocate initial scbs\n",
5696 ahd_name(ahd));
5697 goto error_exit;
5698 }
5699
5700 /*
5701 * Note that we were successful
5702 */
5703 return (0);
5704
5705 error_exit:
5706
5707 return (ENOMEM);
5708 }
5709
5710 static struct scb *
5711 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5712 {
5713 struct scb *scb;
5714
5715 /*
5716 * Look on the pending list.
5717 */
5718 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5719 if (SCB_GET_TAG(scb) == tag)
5720 return (scb);
5721 }
5722
5723 /*
5724 * Then on all of the collision free lists.
5725 */
5726 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5727 struct scb *list_scb;
5728
5729 list_scb = scb;
5730 do {
5731 if (SCB_GET_TAG(list_scb) == tag)
5732 return (list_scb);
5733 list_scb = LIST_NEXT(list_scb, collision_links);
5734 } while (list_scb);
5735 }
5736
5737 /*
5738 * And finally on the generic free list.
5739 */
5740 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5741 if (SCB_GET_TAG(scb) == tag)
5742 return (scb);
5743 }
5744
5745 return (NULL);
5746 }
5747
5748 static void
5749 ahd_fini_scbdata(struct ahd_softc *ahd)
5750 {
5751 struct scb_data *scb_data;
5752
5753 scb_data = &ahd->scb_data;
5754 if (scb_data == NULL)
5755 return;
5756
5757 switch (scb_data->init_level) {
5758 default:
5759 case 7:
5760 {
5761 struct map_node *sns_map;
5762
5763 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5764 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5765 aic_dmamap_unload(ahd, scb_data->sense_dmat,
5766 sns_map->dmamap);
5767 aic_dmamem_free(ahd, scb_data->sense_dmat,
5768 sns_map->vaddr, sns_map->dmamap);
5769 kfree(sns_map, M_DEVBUF);
5770 }
5771 aic_dma_tag_destroy(ahd, scb_data->sense_dmat);
5772 /* FALLTHROUGH */
5773 }
5774 case 6:
5775 {
5776 struct map_node *sg_map;
5777
5778 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5779 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5780 aic_dmamap_unload(ahd, scb_data->sg_dmat,
5781 sg_map->dmamap);
5782 aic_dmamem_free(ahd, scb_data->sg_dmat,
5783 sg_map->vaddr, sg_map->dmamap);
5784 kfree(sg_map, M_DEVBUF);
5785 }
5786 aic_dma_tag_destroy(ahd, scb_data->sg_dmat);
5787 /* FALLTHROUGH */
5788 }
5789 case 5:
5790 {
5791 struct map_node *hscb_map;
5792
5793 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5794 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5795 aic_dmamap_unload(ahd, scb_data->hscb_dmat,
5796 hscb_map->dmamap);
5797 aic_dmamem_free(ahd, scb_data->hscb_dmat,
5798 hscb_map->vaddr, hscb_map->dmamap);
5799 kfree(hscb_map, M_DEVBUF);
5800 }
5801 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5802 /* FALLTHROUGH */
5803 }
5804 case 4:
5805 case 3:
5806 case 2:
5807 case 1:
5808 case 0:
5809 break;
5810 }
5811 }
5812
5813 /*
5814 * DSP filter Bypass must be enabled until the first selection
5815 * after a change in bus mode (Razor #491 and #493).
5816 */
5817 static void
5818 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5819 {
5820 ahd_mode_state saved_modes;
5821
5822 saved_modes = ahd_save_modes(ahd);
5823 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5824 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5825 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5826 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5827 #ifdef AHD_DEBUG
5828 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5829 kprintf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5830 #endif
5831 ahd_restore_modes(ahd, saved_modes);
5832 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5833 }
5834
5835 static void
5836 ahd_iocell_first_selection(struct ahd_softc *ahd)
5837 {
5838 ahd_mode_state saved_modes;
5839 u_int sblkctl;
5840
5841 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5842 return;
5843 saved_modes = ahd_save_modes(ahd);
5844 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5845 sblkctl = ahd_inb(ahd, SBLKCTL);
5846 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5847 #ifdef AHD_DEBUG
5848 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5849 kprintf("%s: iocell first selection\n", ahd_name(ahd));
5850 #endif
5851 if ((sblkctl & ENAB40) != 0) {
5852 ahd_outb(ahd, DSPDATACTL,
5853 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5854 #ifdef AHD_DEBUG
5855 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5856 kprintf("%s: BYPASS now disabled\n", ahd_name(ahd));
5857 #endif
5858 }
5859 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5860 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5861 ahd_restore_modes(ahd, saved_modes);
5862 ahd->flags |= AHD_HAD_FIRST_SEL;
5863 }
5864
5865 /*************************** SCB Management ***********************************/
5866 static void
5867 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5868 {
5869 struct scb_list *free_list;
5870 struct scb_tailq *free_tailq;
5871 struct scb *first_scb;
5872
5873 scb->flags |= SCB_ON_COL_LIST;
5874 AHD_SET_SCB_COL_IDX(scb, col_idx);
5875 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5876 free_tailq = &ahd->scb_data.free_scbs;
5877 first_scb = LIST_FIRST(free_list);
5878 if (first_scb != NULL) {
5879 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5880 } else {
5881 LIST_INSERT_HEAD(free_list, scb, collision_links);
5882 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5883 }
5884 }
5885
5886 static void
5887 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5888 {
5889 struct scb_list *free_list;
5890 struct scb_tailq *free_tailq;
5891 struct scb *first_scb;
5892 u_int col_idx;
5893
5894 scb->flags &= ~SCB_ON_COL_LIST;
5895 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5896 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5897 free_tailq = &ahd->scb_data.free_scbs;
5898 first_scb = LIST_FIRST(free_list);
5899 if (first_scb == scb) {
5900 struct scb *next_scb;
5901
5902 /*
5903 * Maintain order in the collision free
5904 * lists for fairness if this device has
5905 * other colliding tags active.
5906 */
5907 next_scb = LIST_NEXT(scb, collision_links);
5908 if (next_scb != NULL) {
5909 TAILQ_INSERT_AFTER(free_tailq, scb,
5910 next_scb, links.tqe);
5911 }
5912 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5913 }
5914 LIST_REMOVE(scb, collision_links);
5915 }
5916
5917 /*
5918 * Get a free scb. If there are none, see if we can allocate a new SCB.
5919 */
5920 struct scb *
5921 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5922 {
5923 struct scb *scb;
5924 int tries;
5925
5926 tries = 0;
5927 look_again:
5928 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5929 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5930 ahd_rem_col_list(ahd, scb);
5931 goto found;
5932 }
5933 }
5934 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5935
5936 if (tries++ != 0)
5937 return (NULL);
5938 ahd_alloc_scbs(ahd);
5939 goto look_again;
5940 }
5941 LIST_REMOVE(scb, links.le);
5942 if (col_idx != AHD_NEVER_COL_IDX
5943 && (scb->col_scb != NULL)
5944 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5945 LIST_REMOVE(scb->col_scb, links.le);
5946 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5947 }
5948 found:
5949 scb->flags |= SCB_ACTIVE;
5950 return (scb);
5951 }
5952
5953 /*
5954 * Return an SCB resource to the free list.
5955 */
5956 void
5957 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5958 {
5959
5960 /* Clean up for the next user */
5961 scb->flags = SCB_FLAG_NONE;
5962 scb->hscb->control = 0;
5963 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5964
5965 if (scb->col_scb == NULL) {
5966
5967 /*
5968 * No collision possible. Just free normally.
5969 */
5970 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5971 scb, links.le);
5972 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5973
5974 /*
5975 * The SCB we might have collided with is on
5976 * a free collision list. Put both SCBs on
5977 * the generic list.
5978 */
5979 ahd_rem_col_list(ahd, scb->col_scb);
5980 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5981 scb, links.le);
5982 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5983 scb->col_scb, links.le);
5984 } else if ((scb->col_scb->flags
5985 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
5986 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
5987
5988 /*
5989 * The SCB we might collide with on the next allocation
5990 * is still active in a non-packetized, tagged, context.
5991 * Put us on the SCB collision list.
5992 */
5993 ahd_add_col_list(ahd, scb,
5994 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
5995 } else {
5996 /*
5997 * The SCB we might collide with on the next allocation
5998 * is either active in a packetized context, or free.
5999 * Since we can't collide, put this SCB on the generic
6000 * free list.
6001 */
6002 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6003 scb, links.le);
6004 }
6005
6006 aic_platform_scb_free(ahd, scb);
6007 }
6008
6009 void
6010 ahd_alloc_scbs(struct ahd_softc *ahd)
6011 {
6012 struct scb_data *scb_data;
6013 struct scb *next_scb;
6014 struct hardware_scb *hscb;
6015 struct map_node *hscb_map;
6016 struct map_node *sg_map;
6017 struct map_node *sense_map;
6018 uint8_t *segs;
6019 uint8_t *sense_data;
6020 bus_addr_t hscb_busaddr;
6021 bus_addr_t sg_busaddr;
6022 bus_addr_t sense_busaddr;
6023 int newcount;
6024 int i;
6025
6026 scb_data = &ahd->scb_data;
6027 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
6028 /* Can't allocate any more */
6029 return;
6030
6031 if (scb_data->scbs_left != 0) {
6032 int offset;
6033
6034 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
6035 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
6036 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
6037 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
6038 } else {
6039 hscb_map = kmalloc(sizeof(*hscb_map), M_DEVBUF, M_INTWAIT);
6040
6041 /* Allocate the next batch of hardware SCBs */
6042 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat,
6043 (void **)&hscb_map->vaddr,
6044 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
6045 kfree(hscb_map, M_DEVBUF);
6046 return;
6047 }
6048
6049 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
6050
6051 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
6052 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6053 &hscb_map->busaddr, /*flags*/0);
6054
6055 hscb = (struct hardware_scb *)hscb_map->vaddr;
6056 hscb_busaddr = hscb_map->busaddr;
6057 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6058 }
6059
6060 if (scb_data->sgs_left != 0) {
6061 int offset;
6062
6063 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6064 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6065 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6066 segs = sg_map->vaddr + offset;
6067 sg_busaddr = sg_map->busaddr + offset;
6068 } else {
6069 sg_map = kmalloc(sizeof(*sg_map), M_DEVBUF, M_INTWAIT);
6070
6071 /* Allocate the next batch of S/G lists */
6072 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat,
6073 (void **)&sg_map->vaddr,
6074 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
6075 kfree(sg_map, M_DEVBUF);
6076 return;
6077 }
6078
6079 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6080
6081 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6082 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6083 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0);
6084
6085 segs = sg_map->vaddr;
6086 sg_busaddr = sg_map->busaddr;
6087 scb_data->sgs_left =
6088 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6089 #ifdef AHD_DEBUG
6090 if (ahd_debug & AHD_SHOW_MEMORY)
6091 kprintf("Mapped SG data\n");
6092 #endif
6093 }
6094
6095 if (scb_data->sense_left != 0) {
6096 int offset;
6097
6098 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6099 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6100 sense_data = sense_map->vaddr + offset;
6101 sense_busaddr = sense_map->busaddr + offset;
6102 } else {
6103 sense_map = kmalloc(sizeof(*sense_map), M_DEVBUF, M_INTWAIT);
6104
6105 /* Allocate the next batch of sense buffers */
6106 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat,
6107 (void **)&sense_map->vaddr,
6108 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6109 kfree(sense_map, M_DEVBUF);
6110 return;
6111 }
6112
6113 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6114
6115 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6116 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6117 &sense_map->busaddr, /*flags*/0);
6118
6119 sense_data = sense_map->vaddr;
6120 sense_busaddr = sense_map->busaddr;
6121 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6122 #ifdef AHD_DEBUG
6123 if (ahd_debug & AHD_SHOW_MEMORY)
6124 kprintf("Mapped sense data\n");
6125 #endif
6126 }
6127
6128 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6129 newcount = MIN(newcount, scb_data->sgs_left);
6130 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6131 scb_data->sense_left -= newcount;
6132 scb_data->scbs_left -= newcount;
6133 scb_data->sgs_left -= newcount;
6134 for (i = 0; i < newcount; i++) {
6135 struct scb_platform_data *pdata;
6136 u_int col_tag;
6137 #ifndef __linux__
6138 int error;
6139 #endif
6140
6141 next_scb = kmalloc(sizeof(*next_scb), M_DEVBUF, M_INTWAIT);
6142 pdata = kmalloc(sizeof(*pdata), M_DEVBUF, M_INTWAIT);
6143 next_scb->platform_data = pdata;
6144 next_scb->hscb_map = hscb_map;
6145 next_scb->sg_map = sg_map;
6146 next_scb->sense_map = sense_map;
6147 next_scb->sg_list = segs;
6148 next_scb->sense_data = sense_data;
6149 next_scb->sense_busaddr = sense_busaddr;
6150 memset(hscb, 0, sizeof(*hscb));
6151 next_scb->hscb = hscb;
6152 hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
6153
6154 /*
6155 * The sequencer always starts with the second entry.
6156 * The first entry is embedded in the scb.
6157 */
6158 next_scb->sg_list_busaddr = sg_busaddr;
6159 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6160 next_scb->sg_list_busaddr
6161 += sizeof(struct ahd_dma64_seg);
6162 else
6163 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6164 next_scb->ahd_softc = ahd;
6165 next_scb->flags = SCB_FLAG_NONE;
6166 #ifndef __linux__
6167 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6168 &next_scb->dmamap);
6169 if (error != 0) {
6170 kfree(next_scb, M_DEVBUF);
6171 kfree(pdata, M_DEVBUF);
6172 break;
6173 }
6174 #endif
6175 next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
6176 col_tag = scb_data->numscbs ^ 0x100;
6177 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6178 if (next_scb->col_scb != NULL)
6179 next_scb->col_scb->col_scb = next_scb;
6180 ahd_free_scb(ahd, next_scb);
6181 hscb++;
6182 hscb_busaddr += sizeof(*hscb);
6183 segs += ahd_sglist_size(ahd);
6184 sg_busaddr += ahd_sglist_size(ahd);
6185 sense_data += AHD_SENSE_BUFSIZE;
6186 sense_busaddr += AHD_SENSE_BUFSIZE;
6187 scb_data->numscbs++;
6188 }
6189 }
6190
6191 void
6192 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6193 {
6194 const char *speed;
6195 const char *type;
6196 int len;
6197
6198 len = ksprintf(buf, "%s: ",
6199 ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6200 buf += len;
6201
6202 speed = "Ultra320 ";
6203 if ((ahd->features & AHD_WIDE) != 0) {
6204 type = "Wide ";
6205 } else {
6206 type = "Single ";
6207 }
6208 len = ksprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6209 speed, type, ahd->channel, ahd->our_id);
6210 buf += len;
6211
6212 ksprintf(buf, "%s, %d SCBs", ahd->bus_description,
6213 ahd->scb_data.maxhscbs);
6214 }
6215
6216 static const char *channel_strings[] = {
6217 "Primary Low",
6218 "Primary High",
6219 "Secondary Low",
6220 "Secondary High"
6221 };
6222
6223 static const char *termstat_strings[] = {
6224 "Terminated Correctly",
6225 "Over Terminated",
6226 "Under Terminated",
6227 "Not Configured"
6228 };
6229
6230 /*
6231 * Start the board, ready for normal operation
6232 */
6233 int
6234 ahd_init(struct ahd_softc *ahd)
6235 {
6236 uint8_t *next_vaddr;
6237 bus_addr_t next_baddr;
6238 size_t driver_data_size;
6239 int i;
6240 int error;
6241 u_int warn_user;
6242 uint8_t current_sensing;
6243 uint8_t fstat;
6244
6245 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6246
6247 ahd->stack_size = ahd_probe_stack_size(ahd);
6248 ahd->saved_stack = kmalloc(ahd->stack_size * sizeof(uint16_t),
6249 M_DEVBUF, M_WAITOK);
6250
6251 /*
6252 * Verify that the compiler hasn't over-agressively
6253 * padded important structures.
6254 */
6255 if (sizeof(struct hardware_scb) != 64)
6256 panic("Hardware SCB size is incorrect");
6257
6258 #ifdef AHD_DEBUG
6259 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6260 ahd->flags |= AHD_SEQUENCER_DEBUG;
6261 #endif
6262
6263 /*
6264 * Default to allowing initiator operations.
6265 */
6266 ahd->flags |= AHD_INITIATORROLE;
6267
6268 /*
6269 * Only allow target mode features if this unit has them enabled.
6270 */
6271 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6272 ahd->features &= ~AHD_TARGETMODE;
6273
6274 #ifndef __linux__
6275 /* DMA tag for mapping buffers into device visible space. */
6276 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6277 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6278 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6279 ? (bus_addr_t)0x7FFFFFFFFFULL
6280 : BUS_SPACE_MAXADDR_32BIT,
6281 /*highaddr*/BUS_SPACE_MAXADDR,
6282 /*filter*/NULL, /*filterarg*/NULL,
6283 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6284 /*nsegments*/AHD_NSEG,
6285 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6286 /*flags*/BUS_DMA_ALLOCNOW,
6287 &ahd->buffer_dmat) != 0) {
6288 return (ENOMEM);
6289 }
6290 #endif
6291
6292 ahd->init_level++;
6293
6294 /*
6295 * DMA tag for our command fifos and other data in system memory
6296 * the card's sequencer must be able to access. For initiator
6297 * roles, we need to allocate space for the qoutfifo. When providing
6298 * for the target mode role, we must additionally provide space for
6299 * the incoming target command fifo.
6300 */
6301 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6302 + sizeof(struct hardware_scb);
6303 if ((ahd->features & AHD_TARGETMODE) != 0)
6304 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6305 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6306 driver_data_size += PKT_OVERRUN_BUFSIZE;
6307 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6308 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6309 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6310 /*highaddr*/BUS_SPACE_MAXADDR,
6311 /*filter*/NULL, /*filterarg*/NULL,
6312 driver_data_size,
6313 /*nsegments*/1,
6314 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6315 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6316 return (ENOMEM);
6317 }
6318
6319 ahd->init_level++;
6320
6321 /* Allocation of driver data */
6322 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat,
6323 (void **)&ahd->shared_data_map.vaddr,
6324 BUS_DMA_NOWAIT,
6325 &ahd->shared_data_map.dmamap) != 0) {
6326 return (ENOMEM);
6327 }
6328
6329 ahd->init_level++;
6330
6331 /* And permanently map it in */
6332 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6333 ahd->shared_data_map.vaddr, driver_data_size,
6334 ahd_dmamap_cb, &ahd->shared_data_map.busaddr,
6335 /*flags*/0);
6336 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6337 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6338 next_baddr = ahd->shared_data_map.busaddr
6339 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6340 if ((ahd->features & AHD_TARGETMODE) != 0) {
6341 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6342 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6343 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6344 }
6345
6346 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6347 ahd->overrun_buf = next_vaddr;
6348 next_vaddr += PKT_OVERRUN_BUFSIZE;
6349 next_baddr += PKT_OVERRUN_BUFSIZE;
6350 }
6351
6352 /*
6353 * We need one SCB to serve as the "next SCB". Since the
6354 * tag identifier in this SCB will never be used, there is
6355 * no point in using a valid HSCB tag from an SCB pulled from
6356 * the standard free pool. So, we allocate this "sentinel"
6357 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6358 */
6359 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6360 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6361 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6362
6363 ahd->init_level++;
6364
6365 /* Allocate SCB data now that buffer_dmat is initialized */
6366 if (ahd_init_scbdata(ahd) != 0)
6367 return (ENOMEM);
6368
6369 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6370 ahd->flags &= ~AHD_RESET_BUS_A;
6371
6372 /*
6373 * Before committing these settings to the chip, give
6374 * the OSM one last chance to modify our configuration.
6375 */
6376 ahd_platform_init(ahd);
6377
6378 /* Bring up the chip. */
6379 ahd_chip_init(ahd);
6380
6381 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6382
6383 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6384 goto init_done;
6385
6386 /*
6387 * Verify termination based on current draw and
6388 * warn user if the bus is over/under terminated.
6389 */
6390 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6391 CURSENSE_ENB);
6392 if (error != 0) {
6393 kprintf("%s: current sensing timeout 1\n", ahd_name(ahd));
6394 goto init_done;
6395 }
6396 for (i = 20, fstat = FLX_FSTAT_BUSY;
6397 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6398 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6399 if (error != 0) {
6400 kprintf("%s: current sensing timeout 2\n",
6401 ahd_name(ahd));
6402 goto init_done;
6403 }
6404 }
6405 if (i == 0) {
6406 kprintf("%s: Timedout during current-sensing test\n",
6407 ahd_name(ahd));
6408 goto init_done;
6409 }
6410
6411 /* Latch Current Sensing status. */
6412 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, &current_sensing);
6413 if (error != 0) {
6414 kprintf("%s: current sensing timeout 3\n", ahd_name(ahd));
6415 goto init_done;
6416 }
6417
6418 /* Diable current sensing. */
6419 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6420
6421 #ifdef AHD_DEBUG
6422 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6423 kprintf("%s: current_sensing == 0x%x\n",
6424 ahd_name(ahd), current_sensing);
6425 }
6426 #endif
6427 warn_user = 0;
6428 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6429 u_int term_stat;
6430
6431 term_stat = (current_sensing & FLX_CSTAT_MASK);
6432 switch (term_stat) {
6433 case FLX_CSTAT_OVER:
6434 case FLX_CSTAT_UNDER:
6435 warn_user++;
6436 case FLX_CSTAT_INVALID:
6437 case FLX_CSTAT_OKAY:
6438 if (warn_user == 0 && bootverbose == 0)
6439 break;
6440 kprintf("%s: %s Channel %s\n", ahd_name(ahd),
6441 channel_strings[i], termstat_strings[term_stat]);
6442 break;
6443 }
6444 }
6445 if (warn_user) {
6446 kprintf("%s: WARNING. Termination is not configured correctly.\n"
6447 "%s: WARNING. SCSI bus operations may FAIL.\n",
6448 ahd_name(ahd), ahd_name(ahd));
6449 }
6450 init_done:
6451 ahd_restart(ahd);
6452 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
6453 ahd_stat_timer, ahd);
6454 return (0);
6455 }
6456
6457 /*
6458 * (Re)initialize chip state after a chip reset.
6459 */
6460 static void
6461 ahd_chip_init(struct ahd_softc *ahd)
6462 {
6463 uint32_t busaddr;
6464 u_int sxfrctl1;
6465 u_int scsiseq_template;
6466 u_int wait;
6467 u_int i;
6468 u_int target;
6469
6470 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6471 /*
6472 * Take the LED out of diagnostic mode
6473 */
6474 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6475
6476 /*
6477 * Return HS_MAILBOX to its default value.
6478 */
6479 ahd->hs_mailbox = 0;
6480 ahd_outb(ahd, HS_MAILBOX, 0);
6481
6482 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6483 ahd_outb(ahd, IOWNID, ahd->our_id);
6484 ahd_outb(ahd, TOWNID, ahd->our_id);
6485 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6486 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6487 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6488 && (ahd->seltime != STIMESEL_MIN)) {
6489 /*
6490 * The selection timer duration is twice as long
6491 * as it should be. Halve it by adding "1" to
6492 * the user specified setting.
6493 */
6494 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6495 } else {
6496 sxfrctl1 |= ahd->seltime;
6497 }
6498
6499 ahd_outb(ahd, SXFRCTL0, DFON);
6500 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6501 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6502
6503 /*
6504 * Now that termination is set, wait for up
6505 * to 500ms for our transceivers to settle. If
6506 * the adapter does not have a cable attached,
6507 * the transceivers may never settle, so don't
6508 * complain if we fail here.
6509 */
6510 for (wait = 10000;
6511 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6512 wait--)
6513 aic_delay(100);
6514
6515 /* Clear any false bus resets due to the transceivers settling */
6516 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6517 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6518
6519 /* Initialize mode specific S/G state. */
6520 for (i = 0; i < 2; i++) {
6521 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6522 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6523 ahd_outb(ahd, SG_STATE, 0);
6524 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6525 ahd_outb(ahd, SEQIMODE,
6526 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6527 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6528 }
6529
6530 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6531 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6532 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6533 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6534 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6535 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6536 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6537 } else {
6538 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6539 }
6540 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6541 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6542 /*
6543 * Do not issue a target abort when a split completion
6544 * error occurs. Let our PCIX interrupt handler deal
6545 * with it instead. H2A4 Razor #625
6546 */
6547 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6548
6549 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6550 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6551
6552 /*
6553 * Tweak IOCELL settings.
6554 */
6555 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6556 for (i = 0; i < NUMDSPS; i++) {
6557 ahd_outb(ahd, DSPSELECT, i);
6558 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6559 }
6560 #ifdef AHD_DEBUG
6561 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6562 kprintf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6563 WRTBIASCTL_HP_DEFAULT);
6564 #endif
6565 }
6566 ahd_setup_iocell_workaround(ahd);
6567
6568 /*
6569 * Enable LQI Manager interrupts.
6570 */
6571 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6572 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6573 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6574 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6575 /*
6576 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6577 * manually for the command phase at the start of a packetized
6578 * selection case. ENLQOBUSFREE should be made redundant by
6579 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6580 * events fail to assert the BUSFREE interrupt so we must
6581 * also enable LQOBUSFREE interrupts.
6582 */
6583 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6584
6585 /*
6586 * Setup sequencer interrupt handlers.
6587 */
6588 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6589 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6590
6591 /*
6592 * Setup SCB Offset registers.
6593 */
6594 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6595 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6596 pkt_long_lun));
6597 } else {
6598 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6599 }
6600 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6601 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6602 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6603 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6604 shared_data.idata.cdb));
6605 ahd_outb(ahd, QNEXTPTR,
6606 offsetof(struct hardware_scb, next_hscb_busaddr));
6607 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6608 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6609 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6610 ahd_outb(ahd, LUNLEN,
6611 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6612 } else {
6613 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6614 }
6615 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6616 ahd_outb(ahd, MAXCMD, 0xFF);
6617 ahd_outb(ahd, SCBAUTOPTR,
6618 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6619
6620 /* We haven't been enabled for target mode yet. */
6621 ahd_outb(ahd, MULTARGID, 0);
6622 ahd_outb(ahd, MULTARGID + 1, 0);
6623
6624 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6625 /* Initialize the negotiation table. */
6626 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6627 /*
6628 * Clear the spare bytes in the neg table to avoid
6629 * spurious parity errors.
6630 */
6631 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6632 ahd_outb(ahd, NEGOADDR, target);
6633 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6634 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6635 ahd_outb(ahd, ANNEXDAT, 0);
6636 }
6637 }
6638 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6639 struct ahd_devinfo devinfo;
6640 struct ahd_initiator_tinfo *tinfo;
6641 struct ahd_tmode_tstate *tstate;
6642
6643 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6644 target, &tstate);
6645 ahd_compile_devinfo(&devinfo, ahd->our_id,
6646 target, CAM_LUN_WILDCARD,
6647 'A', ROLE_INITIATOR);
6648 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6649 }
6650
6651 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6652 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6653
6654 #if NEEDS_MORE_TESTING
6655 /*
6656 * Always enable abort on incoming L_Qs if this feature is
6657 * supported. We use this to catch invalid SCB references.
6658 */
6659 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6660 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6661 else
6662 #endif
6663 ahd_outb(ahd, LQCTL1, 0);
6664
6665 /* All of our queues are empty */
6666 ahd->qoutfifonext = 0;
6667 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6668 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6669 for (i = 0; i < AHD_QOUT_SIZE; i++)
6670 ahd->qoutfifo[i].valid_tag = 0;
6671 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6672
6673 ahd->qinfifonext = 0;
6674 for (i = 0; i < AHD_QIN_SIZE; i++)
6675 ahd->qinfifo[i] = SCB_LIST_NULL;
6676
6677 if ((ahd->features & AHD_TARGETMODE) != 0) {
6678 /* All target command blocks start out invalid. */
6679 for (i = 0; i < AHD_TMODE_CMDS; i++)
6680 ahd->targetcmds[i].cmd_valid = 0;
6681 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6682 ahd->tqinfifonext = 1;
6683 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6684 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6685 }
6686
6687 /* Initialize Scratch Ram. */
6688 ahd_outb(ahd, SEQ_FLAGS, 0);
6689 ahd_outb(ahd, SEQ_FLAGS2, 0);
6690
6691 /* We don't have any waiting selections */
6692 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6693 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6694 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6695 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6696 for (i = 0; i < AHD_NUM_TARGETS; i++)
6697 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6698
6699 /*
6700 * Nobody is waiting to be DMAed into the QOUTFIFO.
6701 */
6702 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6703 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6704 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6705 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6706 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6707
6708 /*
6709 * The Freeze Count is 0.
6710 */
6711 ahd->qfreeze_cnt = 0;
6712 ahd_outw(ahd, QFREEZE_COUNT, 0);
6713 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6714
6715 /*
6716 * Tell the sequencer where it can find our arrays in memory.
6717 */
6718 busaddr = ahd->shared_data_map.busaddr;
6719 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6720 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6721
6722 /*
6723 * Setup the allowed SCSI Sequences based on operational mode.
6724 * If we are a target, we'll enable select in operations once
6725 * we've had a lun enabled.
6726 */
6727 scsiseq_template = ENAUTOATNP;
6728 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6729 scsiseq_template |= ENRSELI;
6730 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6731
6732 /* There are no busy SCBs yet. */
6733 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6734 int lun;
6735
6736 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6737 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6738 }
6739
6740 /*
6741 * Initialize the group code to command length table.
6742 * Vendor Unique codes are set to 0 so we only capture
6743 * the first byte of the cdb. These can be overridden
6744 * when target mode is enabled.
6745 */
6746 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6747 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6748 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6749 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6750 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6751 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6752 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6753 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6754
6755 /* Tell the sequencer of our initial queue positions */
6756 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6757 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6758 ahd->qinfifonext = 0;
6759 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6760 ahd_set_hescb_qoff(ahd, 0);
6761 ahd_set_snscb_qoff(ahd, 0);
6762 ahd_set_sescb_qoff(ahd, 0);
6763 ahd_set_sdscb_qoff(ahd, 0);
6764
6765 /*
6766 * Tell the sequencer which SCB will be the next one it receives.
6767 */
6768 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6769 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6770
6771 /*
6772 * Default to coalescing disabled.
6773 */
6774 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6775 ahd_outw(ahd, CMDS_PENDING, 0);
6776 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6777 ahd->int_coalescing_maxcmds,
6778 ahd->int_coalescing_mincmds);
6779 ahd_enable_coalescing(ahd, FALSE);
6780
6781 ahd_loadseq(ahd);
6782 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6783 }
6784
6785 /*
6786 * Setup default device and controller settings.
6787 * This should only be called if our probe has
6788 * determined that no configuration data is available.
6789 */
6790 int
6791 ahd_default_config(struct ahd_softc *ahd)
6792 {
6793 int targ;
6794
6795 ahd->our_id = 7;
6796
6797 /*
6798 * Allocate a tstate to house information for our
6799 * initiator presence on the bus as well as the user
6800 * data for any target mode initiator.
6801 */
6802 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6803 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6804 "Failing attach\n", ahd_name(ahd));
6805 return (ENOMEM);
6806 }
6807
6808 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6809 struct ahd_devinfo devinfo;
6810 struct ahd_initiator_tinfo *tinfo;
6811 struct ahd_tmode_tstate *tstate;
6812 uint16_t target_mask;
6813
6814 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6815 targ, &tstate);
6816 /*
6817 * We support SPC2 and SPI4.
6818 */
6819 tinfo->user.protocol_version = 4;
6820 tinfo->user.transport_version = 4;
6821
6822 target_mask = 0x01 << targ;
6823 ahd->user_discenable |= target_mask;
6824 tstate->discenable |= target_mask;
6825 ahd->user_tagenable |= target_mask;
6826 #ifdef AHD_FORCE_160
6827 tinfo->user.period = AHD_SYNCRATE_DT;
6828 #else
6829 tinfo->user.period = AHD_SYNCRATE_160;
6830 #endif
6831 tinfo->user.offset = MAX_OFFSET;
6832 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6833 | MSG_EXT_PPR_WR_FLOW
6834 | MSG_EXT_PPR_HOLD_MCS
6835 | MSG_EXT_PPR_IU_REQ
6836 | MSG_EXT_PPR_QAS_REQ
6837 | MSG_EXT_PPR_DT_REQ;
6838 if ((ahd->features & AHD_RTI) != 0)
6839 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6840
6841 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6842
6843 /*
6844 * Start out Async/Narrow/Untagged and with
6845 * conservative protocol support.
6846 */
6847 tinfo->goal.protocol_version = 2;
6848 tinfo->goal.transport_version = 2;
6849 tinfo->curr.protocol_version = 2;
6850 tinfo->curr.transport_version = 2;
6851 ahd_compile_devinfo(&devinfo, ahd->our_id,
6852 targ, CAM_LUN_WILDCARD,
6853 'A', ROLE_INITIATOR);
6854 tstate->tagenable &= ~target_mask;
6855 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6856 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6857 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6858 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6859 /*paused*/TRUE);
6860 }
6861 return (0);
6862 }
6863
6864 /*
6865 * Parse device configuration information.
6866 */
6867 int
6868 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6869 {
6870 int targ;
6871 int max_targ;
6872
6873 max_targ = sc->max_targets & CFMAXTARG;
6874 ahd->our_id = sc->brtime_id & CFSCSIID;
6875
6876 /*
6877 * Allocate a tstate to house information for our
6878 * initiator presence on the bus as well as the user
6879 * data for any target mode initiator.
6880 */
6881 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6882 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6883 "Failing attach\n", ahd_name(ahd));
6884 return (ENOMEM);
6885 }
6886
6887 for (targ = 0; targ < max_targ; targ++) {
6888 struct ahd_devinfo devinfo;
6889 struct ahd_initiator_tinfo *tinfo;
6890 struct ahd_transinfo *user_tinfo;
6891 struct ahd_tmode_tstate *tstate;
6892 uint16_t target_mask;
6893
6894 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6895 targ, &tstate);
6896 user_tinfo = &tinfo->user;
6897
6898 /*
6899 * We support SPC2 and SPI4.
6900 */
6901 tinfo->user.protocol_version = 4;
6902 tinfo->user.transport_version = 4;
6903
6904 target_mask = 0x01 << targ;
6905 ahd->user_discenable &= ~target_mask;
6906 tstate->discenable &= ~target_mask;
6907 ahd->user_tagenable &= ~target_mask;
6908 if (sc->device_flags[targ] & CFDISC) {
6909 tstate->discenable |= target_mask;
6910 ahd->user_discenable |= target_mask;
6911 ahd->user_tagenable |= target_mask;
6912 } else {
6913 /*
6914 * Cannot be packetized without disconnection.
6915 */
6916 sc->device_flags[targ] &= ~CFPACKETIZED;
6917 }
6918
6919 user_tinfo->ppr_options = 0;
6920 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6921 if (user_tinfo->period < CFXFER_ASYNC) {
6922 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6923 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6924 user_tinfo->offset = MAX_OFFSET;
6925 } else {
6926 user_tinfo->offset = 0;
6927 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6928 }
6929 #ifdef AHD_FORCE_160
6930 if (user_tinfo->period <= AHD_SYNCRATE_160)
6931 user_tinfo->period = AHD_SYNCRATE_DT;
6932 #endif
6933
6934 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6935 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6936 | MSG_EXT_PPR_WR_FLOW
6937 | MSG_EXT_PPR_HOLD_MCS
6938 | MSG_EXT_PPR_IU_REQ;
6939 if ((ahd->features & AHD_RTI) != 0)
6940 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6941 }
6942
6943 if ((sc->device_flags[targ] & CFQAS) != 0)
6944 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6945
6946 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6947 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6948 else
6949 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6950 #ifdef AHD_DEBUG
6951 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6952 kprintf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6953 user_tinfo->period, user_tinfo->offset,
6954 user_tinfo->ppr_options);
6955 #endif
6956 /*
6957 * Start out Async/Narrow/Untagged and with
6958 * conservative protocol support.
6959 */
6960 tstate->tagenable &= ~target_mask;
6961 tinfo->goal.protocol_version = 2;
6962 tinfo->goal.transport_version = 2;
6963 tinfo->curr.protocol_version = 2;
6964 tinfo->curr.transport_version = 2;
6965 ahd_compile_devinfo(&devinfo, ahd->our_id,
6966 targ, CAM_LUN_WILDCARD,
6967 'A', ROLE_INITIATOR);
6968 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6969 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6970 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6971 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6972 /*paused*/TRUE);
6973 }
6974
6975 ahd->flags &= ~AHD_SPCHK_ENB_A;
6976 if (sc->bios_control & CFSPARITY)
6977 ahd->flags |= AHD_SPCHK_ENB_A;
6978
6979 ahd->flags &= ~AHD_RESET_BUS_A;
6980 if (sc->bios_control & CFRESETB)
6981 ahd->flags |= AHD_RESET_BUS_A;
6982
6983 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
6984 if (sc->bios_control & CFEXTEND)
6985 ahd->flags |= AHD_EXTENDED_TRANS_A;
6986
6987 ahd->flags &= ~AHD_BIOS_ENABLED;
6988 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
6989 ahd->flags |= AHD_BIOS_ENABLED;
6990
6991 ahd->flags &= ~AHD_STPWLEVEL_A;
6992 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
6993 ahd->flags |= AHD_STPWLEVEL_A;
6994
6995 return (0);
6996 }
6997
6998 /*
6999 * Parse device configuration information.
7000 */
7001 int
7002 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
7003 {
7004 int error;
7005
7006 error = ahd_verify_vpd_cksum(vpd);
7007 if (error == 0)
7008 return (EINVAL);
7009 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
7010 ahd->flags |= AHD_BOOT_CHANNEL;
7011 return (0);
7012 }
7013
7014 void
7015 ahd_intr_enable(struct ahd_softc *ahd, int enable)
7016 {
7017 u_int hcntrl;
7018
7019 hcntrl = ahd_inb(ahd, HCNTRL);
7020 hcntrl &= ~INTEN;
7021 ahd->pause &= ~INTEN;
7022 ahd->unpause &= ~INTEN;
7023 if (enable) {
7024 hcntrl |= INTEN;
7025 ahd->pause |= INTEN;
7026 ahd->unpause |= INTEN;
7027 }
7028 ahd_outb(ahd, HCNTRL, hcntrl);
7029 }
7030
7031 void
7032 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7033 u_int mincmds)
7034 {
7035 if (timer > AHD_TIMER_MAX_US)
7036 timer = AHD_TIMER_MAX_US;
7037 ahd->int_coalescing_timer = timer;
7038
7039 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7040 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7041 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7042 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7043 ahd->int_coalescing_maxcmds = maxcmds;
7044 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7045 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7046 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7047 }
7048
7049 void
7050 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7051 {
7052
7053 ahd->hs_mailbox &= ~ENINT_COALESCE;
7054 if (enable)
7055 ahd->hs_mailbox |= ENINT_COALESCE;
7056 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7057 ahd_flush_device_writes(ahd);
7058 ahd_run_qoutfifo(ahd);
7059 }
7060
7061 /*
7062 * Ensure that the card is paused in a location
7063 * outside of all critical sections and that all
7064 * pending work is completed prior to returning.
7065 * This routine should only be called from outside
7066 * an interrupt context.
7067 */
7068 void
7069 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7070 {
7071 u_int intstat;
7072 u_int maxloops;
7073
7074 maxloops = 1000;
7075 ahd->flags |= AHD_ALL_INTERRUPTS;
7076 ahd_pause(ahd);
7077 /*
7078 * Freeze the outgoing selections. We do this only
7079 * until we are safely paused without further selections
7080 * pending.
7081 */
7082 ahd->qfreeze_cnt--;
7083 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7084 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7085 do {
7086
7087 ahd_unpause(ahd);
7088 /*
7089 * Give the sequencer some time to service
7090 * any active selections.
7091 */
7092 aic_delay(500);
7093
7094 ahd_intr(ahd);
7095 ahd_pause(ahd);
7096 intstat = ahd_inb(ahd, INTSTAT);
7097 if ((intstat & INT_PEND) == 0) {
7098 ahd_clear_critical_section(ahd);
7099 intstat = ahd_inb(ahd, INTSTAT);
7100 }
7101 } while (--maxloops
7102 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7103 && ((intstat & INT_PEND) != 0
7104 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7105 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7106
7107 if (maxloops == 0) {
7108 kprintf("Infinite interrupt loop, INTSTAT = %x",
7109 ahd_inb(ahd, INTSTAT));
7110 }
7111 ahd->qfreeze_cnt++;
7112 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7113
7114 ahd_flush_qoutfifo(ahd);
7115
7116 ahd_platform_flushwork(ahd);
7117 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7118 }
7119
7120 int
7121 ahd_suspend(struct ahd_softc *ahd)
7122 {
7123
7124 ahd_pause_and_flushwork(ahd);
7125
7126 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7127 ahd_unpause(ahd);
7128 return (EBUSY);
7129 }
7130 ahd_shutdown(ahd);
7131 return (0);
7132 }
7133
7134 int
7135 ahd_resume(struct ahd_softc *ahd)
7136 {
7137
7138 ahd_reset(ahd, /*reinit*/TRUE);
7139 ahd_intr_enable(ahd, TRUE);
7140 ahd_restart(ahd);
7141 return (0);
7142 }
7143
7144 /************************** Busy Target Table *********************************/
7145 /*
7146 * Set SCBPTR to the SCB that contains the busy
7147 * table entry for TCL. Return the offset into
7148 * the SCB that contains the entry for TCL.
7149 * saved_scbid is dereferenced and set to the
7150 * scbid that should be restored once manipualtion
7151 * of the TCL entry is complete.
7152 */
7153 static __inline u_int
7154 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7155 {
7156 /*
7157 * Index to the SCB that contains the busy entry.
7158 */
7159 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7160 *saved_scbid = ahd_get_scbptr(ahd);
7161 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7162 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7163
7164 /*
7165 * And now calculate the SCB offset to the entry.
7166 * Each entry is 2 bytes wide, hence the
7167 * multiplication by 2.
7168 */
7169 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7170 }
7171
7172 /*
7173 * Return the untagged transaction id for a given target/channel lun.
7174 */
7175 u_int
7176 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7177 {
7178 u_int scbid;
7179 u_int scb_offset;
7180 u_int saved_scbptr;
7181
7182 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7183 scbid = ahd_inw_scbram(ahd, scb_offset);
7184 ahd_set_scbptr(ahd, saved_scbptr);
7185 return (scbid);
7186 }
7187
7188 void
7189 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7190 {
7191 u_int scb_offset;
7192 u_int saved_scbptr;
7193
7194 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7195 ahd_outw(ahd, scb_offset, scbid);
7196 ahd_set_scbptr(ahd, saved_scbptr);
7197 }
7198
7199 /************************** SCB and SCB queue management **********************/
7200 int
7201 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7202 char channel, int lun, u_int tag, role_t role)
7203 {
7204 int targ = SCB_GET_TARGET(ahd, scb);
7205 char chan = SCB_GET_CHANNEL(ahd, scb);
7206 int slun = SCB_GET_LUN(scb);
7207 int match;
7208
7209 match = ((chan == channel) || (channel == ALL_CHANNELS));
7210 if (match != 0)
7211 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7212 if (match != 0)
7213 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7214 if (match != 0) {
7215 #if AHD_TARGET_MODE
7216 int group;
7217
7218 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7219 if (role == ROLE_INITIATOR) {
7220 match = (group != XPT_FC_GROUP_TMODE)
7221 && ((tag == SCB_GET_TAG(scb))
7222 || (tag == SCB_LIST_NULL));
7223 } else if (role == ROLE_TARGET) {
7224 match = (group == XPT_FC_GROUP_TMODE)
7225 && ((tag == scb->io_ctx->csio.tag_id)
7226 || (tag == SCB_LIST_NULL));
7227 }
7228 #else /* !AHD_TARGET_MODE */
7229 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7230 #endif /* AHD_TARGET_MODE */
7231 }
7232
7233 return match;
7234 }
7235
7236 void
7237 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7238 {
7239 int target;
7240 char channel;
7241 int lun;
7242
7243 target = SCB_GET_TARGET(ahd, scb);
7244 lun = SCB_GET_LUN(scb);
7245 channel = SCB_GET_CHANNEL(ahd, scb);
7246
7247 ahd_search_qinfifo(ahd, target, channel, lun,
7248 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7249 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7250
7251 ahd_platform_freeze_devq(ahd, scb);
7252 }
7253
7254 void
7255 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7256 {
7257 struct scb *prev_scb;
7258 ahd_mode_state saved_modes;
7259
7260 saved_modes = ahd_save_modes(ahd);
7261 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7262 prev_scb = NULL;
7263 if (ahd_qinfifo_count(ahd) != 0) {
7264 u_int prev_tag;
7265 u_int prev_pos;
7266
7267 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7268 prev_tag = ahd->qinfifo[prev_pos];
7269 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7270 }
7271 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7272 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7273 ahd_restore_modes(ahd, saved_modes);
7274 }
7275
7276 static void
7277 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7278 struct scb *scb)
7279 {
7280 if (prev_scb == NULL) {
7281 uint32_t busaddr;
7282
7283 busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7284 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7285 } else {
7286 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7287 ahd_sync_scb(ahd, prev_scb,
7288 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7289 }
7290 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7291 ahd->qinfifonext++;
7292 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7293 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7294 }
7295
7296 static int
7297 ahd_qinfifo_count(struct ahd_softc *ahd)
7298 {
7299 u_int qinpos;
7300 u_int wrap_qinpos;
7301 u_int wrap_qinfifonext;
7302
7303 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7304 qinpos = ahd_get_snscb_qoff(ahd);
7305 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7306 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7307 if (wrap_qinfifonext >= wrap_qinpos)
7308 return (wrap_qinfifonext - wrap_qinpos);
7309 else
7310 return (wrap_qinfifonext
7311 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7312 }
7313
7314 void
7315 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7316 {
7317 struct scb *scb;
7318 ahd_mode_state saved_modes;
7319 u_int pending_cmds;
7320
7321 saved_modes = ahd_save_modes(ahd);
7322 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7323
7324 /*
7325 * Don't count any commands as outstanding that the
7326 * sequencer has already marked for completion.
7327 */
7328 ahd_flush_qoutfifo(ahd);
7329
7330 pending_cmds = 0;
7331 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7332 pending_cmds++;
7333 }
7334 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7335 ahd_restore_modes(ahd, saved_modes);
7336 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7337 }
7338
7339 void
7340 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7341 {
7342 cam_status ostat;
7343 cam_status cstat;
7344
7345 ostat = aic_get_transaction_status(scb);
7346 if (ostat == CAM_REQ_INPROG)
7347 aic_set_transaction_status(scb, status);
7348 cstat = aic_get_transaction_status(scb);
7349 if (cstat != CAM_REQ_CMP)
7350 aic_freeze_scb(scb);
7351 ahd_done(ahd, scb);
7352 }
7353
7354 int
7355 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7356 int lun, u_int tag, role_t role, uint32_t status,
7357 ahd_search_action action)
7358 {
7359 struct scb *scb;
7360 struct scb *mk_msg_scb;
7361 struct scb *prev_scb;
7362 ahd_mode_state saved_modes;
7363 u_int qinstart;
7364 u_int qinpos;
7365 u_int qintail;
7366 u_int tid_next;
7367 u_int tid_prev;
7368 u_int scbid;
7369 u_int seq_flags2;
7370 u_int savedscbptr;
7371 uint32_t busaddr;
7372 int found;
7373 int targets;
7374
7375 /* Must be in CCHAN mode */
7376 saved_modes = ahd_save_modes(ahd);
7377 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7378
7379 /*
7380 * Halt any pending SCB DMA. The sequencer will reinitiate
7381 * this dma if the qinfifo is not empty once we unpause.
7382 */
7383 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7384 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7385 ahd_outb(ahd, CCSCBCTL,
7386 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7387 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7388 ;
7389 }
7390 /* Determine sequencer's position in the qinfifo. */
7391 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7392 qinstart = ahd_get_snscb_qoff(ahd);
7393 qinpos = AHD_QIN_WRAP(qinstart);
7394 found = 0;
7395 prev_scb = NULL;
7396
7397 if (action == SEARCH_PRINT) {
7398 kprintf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7399 qinstart, ahd->qinfifonext);
7400 }
7401
7402 /*
7403 * Start with an empty queue. Entries that are not chosen
7404 * for removal will be re-added to the queue as we go.
7405 */
7406 ahd->qinfifonext = qinstart;
7407 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7408 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7409
7410 while (qinpos != qintail) {
7411 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7412 if (scb == NULL) {
7413 kprintf("qinpos = %d, SCB index = %d\n",
7414 qinpos, ahd->qinfifo[qinpos]);
7415 panic("Loop 1\n");
7416 }
7417
7418 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7419 /*
7420 * We found an scb that needs to be acted on.
7421 */
7422 found++;
7423 switch (action) {
7424 case SEARCH_COMPLETE:
7425 if ((scb->flags & SCB_ACTIVE) == 0)
7426 kprintf("Inactive SCB in qinfifo\n");
7427 ahd_done_with_status(ahd, scb, status);
7428 /* FALLTHROUGH */
7429 case SEARCH_REMOVE:
7430 break;
7431 case SEARCH_PRINT:
7432 kprintf(" 0x%x", ahd->qinfifo[qinpos]);
7433 /* FALLTHROUGH */
7434 case SEARCH_COUNT:
7435 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7436 prev_scb = scb;
7437 break;
7438 }
7439 } else {
7440 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7441 prev_scb = scb;
7442 }
7443 qinpos = AHD_QIN_WRAP(qinpos+1);
7444 }
7445
7446 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7447
7448 if (action == SEARCH_PRINT)
7449 kprintf("\nWAITING_TID_QUEUES:\n");
7450
7451 /*
7452 * Search waiting for selection lists. We traverse the
7453 * list of "their ids" waiting for selection and, if
7454 * appropriate, traverse the SCBs of each "their id"
7455 * looking for matches.
7456 */
7457 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7458 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7459 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7460 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7461 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7462 } else
7463 mk_msg_scb = NULL;
7464 savedscbptr = ahd_get_scbptr(ahd);
7465 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7466 tid_prev = SCB_LIST_NULL;
7467 targets = 0;
7468 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7469 u_int tid_head;
7470 u_int tid_tail;
7471
7472 targets++;
7473 if (targets > AHD_NUM_TARGETS)
7474 panic("TID LIST LOOP");
7475
7476 if (scbid >= ahd->scb_data.numscbs) {
7477 kprintf("%s: Waiting TID List inconsistency. "
7478 "SCB index == 0x%x, yet numscbs == 0x%x.",
7479 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7480 ahd_dump_card_state(ahd);
7481 panic("for safety");
7482 }
7483 scb = ahd_lookup_scb(ahd, scbid);
7484 if (scb == NULL) {
7485 kprintf("%s: SCB = 0x%x Not Active!\n",
7486 ahd_name(ahd), scbid);
7487 panic("Waiting TID List traversal\n");
7488 }
7489 ahd_set_scbptr(ahd, scbid);
7490 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7491 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7492 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7493 tid_prev = scbid;
7494 continue;
7495 }
7496
7497 /*
7498 * We found a list of scbs that needs to be searched.
7499 */
7500 if (action == SEARCH_PRINT)
7501 kprintf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7502 tid_head = scbid;
7503 found += ahd_search_scb_list(ahd, target, channel,
7504 lun, tag, role, status,
7505 action, &tid_head, &tid_tail,
7506 SCB_GET_TARGET(ahd, scb));
7507 /*
7508 * Check any MK_MESSAGE SCB that is still waiting to
7509 * enter this target's waiting for selection queue.
7510 */
7511 if (mk_msg_scb != NULL
7512 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7513 lun, tag, role)) {
7514
7515 /*
7516 * We found an scb that needs to be acted on.
7517 */
7518 found++;
7519 switch (action) {
7520 case SEARCH_COMPLETE:
7521 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7522 kprintf("Inactive SCB pending MK_MSG\n");
7523 ahd_done_with_status(ahd, mk_msg_scb, status);
7524 /* FALLTHROUGH */
7525 case SEARCH_REMOVE:
7526 {
7527 u_int tail_offset;
7528
7529 kprintf("Removing MK_MSG scb\n");
7530
7531 /*
7532 * Reset our tail to the tail of the
7533 * main per-target list.
7534 */
7535 tail_offset = WAITING_SCB_TAILS
7536 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7537 ahd_outw(ahd, tail_offset, tid_tail);
7538
7539 seq_flags2 &= ~PENDING_MK_MESSAGE;
7540 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7541 ahd_outw(ahd, CMDS_PENDING,
7542 ahd_inw(ahd, CMDS_PENDING)-1);
7543 mk_msg_scb = NULL;
7544 break;
7545 }
7546 case SEARCH_PRINT:
7547 kprintf(" 0x%x", SCB_GET_TAG(scb));
7548 /* FALLTHROUGH */
7549 case SEARCH_COUNT:
7550 break;
7551 }
7552 }
7553
7554 if (mk_msg_scb != NULL
7555 && SCBID_IS_NULL(tid_head)
7556 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7557 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7558
7559 /*
7560 * When removing the last SCB for a target
7561 * queue with a pending MK_MESSAGE scb, we
7562 * must queue the MK_MESSAGE scb.
7563 */
7564 kprintf("Queueing mk_msg_scb\n");
7565 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7566 seq_flags2 &= ~PENDING_MK_MESSAGE;
7567 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7568 mk_msg_scb = NULL;
7569 }
7570 if (tid_head != scbid)
7571 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7572 if (!SCBID_IS_NULL(tid_head))
7573 tid_prev = tid_head;
7574 if (action == SEARCH_PRINT)
7575 kprintf(")\n");
7576 }
7577
7578 /* Restore saved state. */
7579 ahd_set_scbptr(ahd, savedscbptr);
7580 ahd_restore_modes(ahd, saved_modes);
7581 return (found);
7582 }
7583
7584 static int
7585 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7586 int lun, u_int tag, role_t role, uint32_t status,
7587 ahd_search_action action, u_int *list_head,
7588 u_int *list_tail, u_int tid)
7589 {
7590 struct scb *scb;
7591 u_int scbid;
7592 u_int next;
7593 u_int prev;
7594 int found;
7595
7596 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7597 found = 0;
7598 prev = SCB_LIST_NULL;
7599 next = *list_head;
7600 *list_tail = SCB_LIST_NULL;
7601 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7602 if (scbid >= ahd->scb_data.numscbs) {
7603 kprintf("%s:SCB List inconsistency. "
7604 "SCB == 0x%x, yet numscbs == 0x%x.",
7605 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7606 ahd_dump_card_state(ahd);
7607 panic("for safety");
7608 }
7609 scb = ahd_lookup_scb(ahd, scbid);
7610 if (scb == NULL) {
7611 kprintf("%s: SCB = %d Not Active!\n",
7612 ahd_name(ahd), scbid);
7613 panic("Waiting List traversal\n");
7614 }
7615 ahd_set_scbptr(ahd, scbid);
7616 *list_tail = scbid;
7617 next = ahd_inw_scbram(ahd, SCB_NEXT);
7618 if (ahd_match_scb(ahd, scb, target, channel,
7619 lun, SCB_LIST_NULL, role) == 0) {
7620 prev = scbid;
7621 continue;
7622 }
7623 found++;
7624 switch (action) {
7625 case SEARCH_COMPLETE:
7626 if ((scb->flags & SCB_ACTIVE) == 0)
7627 kprintf("Inactive SCB in Waiting List\n");
7628 ahd_done_with_status(ahd, scb, status);
7629 /* FALLTHROUGH */
7630 case SEARCH_REMOVE:
7631 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7632 *list_tail = prev;
7633 if (SCBID_IS_NULL(prev))
7634 *list_head = next;
7635 break;
7636 case SEARCH_PRINT:
7637 kprintf("0x%x ", scbid);
7638 case SEARCH_COUNT:
7639 prev = scbid;
7640 break;
7641 }
7642 if (found > AHD_SCB_MAX)
7643 panic("SCB LIST LOOP");
7644 }
7645 if (action == SEARCH_COMPLETE
7646 || action == SEARCH_REMOVE)
7647 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7648 return (found);
7649 }
7650
7651 static void
7652 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7653 u_int tid_cur, u_int tid_next)
7654 {
7655 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7656
7657 if (SCBID_IS_NULL(tid_cur)) {
7658
7659 /* Bypass current TID list */
7660 if (SCBID_IS_NULL(tid_prev)) {
7661 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7662 } else {
7663 ahd_set_scbptr(ahd, tid_prev);
7664 ahd_outw(ahd, SCB_NEXT2, tid_next);
7665 }
7666 if (SCBID_IS_NULL(tid_next))
7667 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7668 } else {
7669
7670 /* Stitch through tid_cur */
7671 if (SCBID_IS_NULL(tid_prev)) {
7672 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7673 } else {
7674 ahd_set_scbptr(ahd, tid_prev);
7675 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7676 }
7677 ahd_set_scbptr(ahd, tid_cur);
7678 ahd_outw(ahd, SCB_NEXT2, tid_next);
7679
7680 if (SCBID_IS_NULL(tid_next))
7681 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7682 }
7683 }
7684
7685 /*
7686 * Manipulate the waiting for selection list and return the
7687 * scb that follows the one that we remove.
7688 */
7689 static u_int
7690 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7691 u_int prev, u_int next, u_int tid)
7692 {
7693 u_int tail_offset;
7694
7695 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7696 if (!SCBID_IS_NULL(prev)) {
7697 ahd_set_scbptr(ahd, prev);
7698 ahd_outw(ahd, SCB_NEXT, next);
7699 }
7700
7701 /*
7702 * SCBs that have MK_MESSAGE set in them may
7703 * cause the tail pointer to be updated without
7704 * setting the next pointer of the previous tail.
7705 * Only clear the tail if the removed SCB was
7706 * the tail.
7707 */
7708 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7709 if (SCBID_IS_NULL(next)
7710 && ahd_inw(ahd, tail_offset) == scbid)
7711 ahd_outw(ahd, tail_offset, prev);
7712
7713 ahd_add_scb_to_free_list(ahd, scbid);
7714 return (next);
7715 }
7716
7717 /*
7718 * Add the SCB as selected by SCBPTR onto the on chip list of
7719 * free hardware SCBs. This list is empty/unused if we are not
7720 * performing SCB paging.
7721 */
7722 static void
7723 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7724 {
7725 /* XXX Need some other mechanism to designate "free". */
7726 /*
7727 * Invalidate the tag so that our abort
7728 * routines don't think it's active.
7729 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7730 */
7731 }
7732
7733 /******************************** Error Handling ******************************/
7734 /*
7735 * Abort all SCBs that match the given description (target/channel/lun/tag),
7736 * setting their status to the passed in status if the status has not already
7737 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7738 * is paused before it is called.
7739 */
7740 int
7741 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7742 int lun, u_int tag, role_t role, uint32_t status)
7743 {
7744 struct scb *scbp;
7745 struct scb *scbp_next;
7746 u_int i, j;
7747 u_int maxtarget;
7748 u_int minlun;
7749 u_int maxlun;
7750 int found;
7751 ahd_mode_state saved_modes;
7752
7753 /* restore this when we're done */
7754 saved_modes = ahd_save_modes(ahd);
7755 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7756
7757 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7758 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7759
7760 /*
7761 * Clean out the busy target table for any untagged commands.
7762 */
7763 i = 0;
7764 maxtarget = 16;
7765 if (target != CAM_TARGET_WILDCARD) {
7766 i = target;
7767 if (channel == 'B')
7768 i += 8;
7769 maxtarget = i + 1;
7770 }
7771
7772 if (lun == CAM_LUN_WILDCARD) {
7773 minlun = 0;
7774 maxlun = AHD_NUM_LUNS_NONPKT;
7775 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7776 minlun = maxlun = 0;
7777 } else {
7778 minlun = lun;
7779 maxlun = lun + 1;
7780 }
7781
7782 if (role != ROLE_TARGET) {
7783 for (;i < maxtarget; i++) {
7784 for (j = minlun;j < maxlun; j++) {
7785 u_int scbid;
7786 u_int tcl;
7787
7788 tcl = BUILD_TCL_RAW(i, 'A', j);
7789 scbid = ahd_find_busy_tcl(ahd, tcl);
7790 scbp = ahd_lookup_scb(ahd, scbid);
7791 if (scbp == NULL
7792 || ahd_match_scb(ahd, scbp, target, channel,
7793 lun, tag, role) == 0)
7794 continue;
7795 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7796 }
7797 }
7798 }
7799
7800 /*
7801 * Don't abort commands that have already completed,
7802 * but haven't quite made it up to the host yet.
7803 */
7804 ahd_flush_qoutfifo(ahd);
7805
7806 /*
7807 * Go through the pending CCB list and look for
7808 * commands for this target that are still active.
7809 * These are other tagged commands that were
7810 * disconnected when the reset occurred.
7811 */
7812 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7813 while (scbp_next != NULL) {
7814 scbp = scbp_next;
7815 scbp_next = LIST_NEXT(scbp, pending_links);
7816 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7817 cam_status ostat;
7818
7819 ostat = aic_get_transaction_status(scbp);
7820 if (ostat == CAM_REQ_INPROG)
7821 aic_set_transaction_status(scbp, status);
7822 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7823 aic_freeze_scb(scbp);
7824 if ((scbp->flags & SCB_ACTIVE) == 0)
7825 kprintf("Inactive SCB on pending list\n");
7826 ahd_done(ahd, scbp);
7827 found++;
7828 }
7829 }
7830 ahd_restore_modes(ahd, saved_modes);
7831 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7832 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7833 return found;
7834 }
7835
7836 static void
7837 ahd_reset_current_bus(struct ahd_softc *ahd)
7838 {
7839 uint8_t scsiseq;
7840
7841 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7842 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7843 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7844 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7845 ahd_flush_device_writes(ahd);
7846 aic_delay(AHD_BUSRESET_DELAY);
7847 /* Turn off the bus reset */
7848 ahd_outb(ahd, SCSISEQ0, scsiseq);
7849 ahd_flush_device_writes(ahd);
7850 aic_delay(AHD_BUSRESET_DELAY);
7851 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7852 /*
7853 * 2A Razor #474
7854 * Certain chip state is not cleared for
7855 * SCSI bus resets that we initiate, so
7856 * we must reset the chip.
7857 */
7858 ahd_reset(ahd, /*reinit*/TRUE);
7859 ahd_intr_enable(ahd, /*enable*/TRUE);
7860 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7861 }
7862
7863 ahd_clear_intstat(ahd);
7864 }
7865
7866 int
7867 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7868 {
7869 struct ahd_devinfo devinfo;
7870 u_int initiator;
7871 u_int target;
7872 u_int max_scsiid;
7873 int found;
7874 u_int fifo;
7875 u_int next_fifo;
7876
7877 ahd->pending_device = NULL;
7878
7879 ahd_compile_devinfo(&devinfo,
7880 CAM_TARGET_WILDCARD,
7881 CAM_TARGET_WILDCARD,
7882 CAM_LUN_WILDCARD,
7883 channel, ROLE_UNKNOWN);
7884 ahd_pause(ahd);
7885
7886 /* Make sure the sequencer is in a safe location. */
7887 ahd_clear_critical_section(ahd);
7888
7889 #if AHD_TARGET_MODE
7890 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7891 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7892 }
7893 #endif
7894 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7895
7896 /*
7897 * Disable selections so no automatic hardware
7898 * functions will modify chip state.
7899 */
7900 ahd_outb(ahd, SCSISEQ0, 0);
7901 ahd_outb(ahd, SCSISEQ1, 0);
7902
7903 /*
7904 * Safely shut down our DMA engines. Always start with
7905 * the FIFO that is not currently active (if any are
7906 * actively connected).
7907 */
7908 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7909 if (next_fifo > CURRFIFO_1)
7910 /* If disconneced, arbitrarily start with FIFO1. */
7911 next_fifo = fifo = 0;
7912 do {
7913 next_fifo ^= CURRFIFO_1;
7914 ahd_set_modes(ahd, next_fifo, next_fifo);
7915 ahd_outb(ahd, DFCNTRL,
7916 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7917 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7918 aic_delay(10);
7919 /*
7920 * Set CURRFIFO to the now inactive channel.
7921 */
7922 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7923 ahd_outb(ahd, DFFSTAT, next_fifo);
7924 } while (next_fifo != fifo);
7925
7926 /*
7927 * Reset the bus if we are initiating this reset
7928 */
7929 ahd_clear_msg_state(ahd);
7930 ahd_outb(ahd, SIMODE1,
7931 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7932
7933 if (initiate_reset)
7934 ahd_reset_current_bus(ahd);
7935
7936 ahd_clear_intstat(ahd);
7937
7938 /*
7939 * Clean up all the state information for the
7940 * pending transactions on this bus.
7941 */
7942 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7943 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7944 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7945
7946 /*
7947 * Cleanup anything left in the FIFOs.
7948 */
7949 ahd_clear_fifo(ahd, 0);
7950 ahd_clear_fifo(ahd, 1);
7951
7952 /*
7953 * Revert to async/narrow transfers until we renegotiate.
7954 */
7955 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7956 for (target = 0; target <= max_scsiid; target++) {
7957
7958 if (ahd->enabled_targets[target] == NULL)
7959 continue;
7960 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7961 struct ahd_devinfo devinfo;
7962
7963 ahd_compile_devinfo(&devinfo, target, initiator,
7964 CAM_LUN_WILDCARD,
7965 'A', ROLE_UNKNOWN);
7966 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7967 AHD_TRANS_CUR, /*paused*/TRUE);
7968 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7969 /*offset*/0, /*ppr_options*/0,
7970 AHD_TRANS_CUR, /*paused*/TRUE);
7971 }
7972 }
7973
7974 #ifdef AHD_TARGET_MODE
7975 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7976
7977 /*
7978 * Send an immediate notify ccb to all target more peripheral
7979 * drivers affected by this action.
7980 */
7981 for (target = 0; target <= max_scsiid; target++) {
7982 struct ahd_tmode_tstate* tstate;
7983 u_int lun;
7984
7985 tstate = ahd->enabled_targets[target];
7986 if (tstate == NULL)
7987 continue;
7988 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
7989 struct ahd_tmode_lstate* lstate;
7990
7991 lstate = tstate->enabled_luns[lun];
7992 if (lstate == NULL)
7993 continue;
7994
7995 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
7996 EVENT_TYPE_BUS_RESET, /*arg*/0);
7997 ahd_send_lstate_events(ahd, lstate);
7998 }
7999 }
8000 #endif
8001 /* Notify the XPT that a bus reset occurred */
8002 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
8003 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
8004 ahd_restart(ahd);
8005 /*
8006 * Freeze the SIMQ until our poller can determine that
8007 * the bus reset has really gone away. We set the initial
8008 * timer to 0 to have the check performed as soon as possible
8009 * from the timer context.
8010 */
8011 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
8012 ahd->flags |= AHD_RESET_POLL_ACTIVE;
8013 aic_freeze_simq(ahd);
8014 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8015 }
8016 return (found);
8017 }
8018
8019
8020 #define AHD_RESET_POLL_MS 1
8021 static void
8022 ahd_reset_poll(void *arg)
8023 {
8024 struct ahd_softc *ahd;
8025 u_int scsiseq1;
8026
8027 ahd = ahd_find_softc((struct ahd_softc *)arg);
8028 if (ahd == NULL) {
8029 kprintf("ahd_reset_poll: Instance %p no longer exists\n", arg);
8030 return;
8031 }
8032 ahd_lock();
8033 ahd_pause(ahd);
8034 ahd_update_modes(ahd);
8035 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8036 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8037 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8038 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS,
8039 ahd_reset_poll, ahd);
8040 ahd_unpause(ahd);
8041 ahd_unlock();
8042 return;
8043 }
8044
8045 /* Reset is now low. Complete chip reinitialization. */
8046 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8047 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8048 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8049 ahd_unpause(ahd);
8050 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8051 ahd_unlock();
8052 aic_release_simq(ahd);
8053 }
8054
8055 /**************************** Statistics Processing ***************************/
8056 static void
8057 ahd_stat_timer(void *arg)
8058 {
8059 struct ahd_softc *ahd;
8060 int enint_coal;
8061
8062 ahd = ahd_find_softc((struct ahd_softc *)arg);
8063 if (ahd == NULL) {
8064 kprintf("ahd_stat_timer: Instance %p no longer exists\n", arg);
8065 return;
8066 }
8067 ahd_lock();
8068
8069 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8070 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8071 enint_coal |= ENINT_COALESCE;
8072 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8073 enint_coal &= ~ENINT_COALESCE;
8074
8075 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8076 ahd_enable_coalescing(ahd, enint_coal);
8077 #ifdef AHD_DEBUG
8078 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8079 kprintf("%s: Interrupt coalescing "
8080 "now %sabled. Cmds %d\n",
8081 ahd_name(ahd),
8082 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8083 ahd->cmdcmplt_total);
8084 #endif
8085 }
8086
8087 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8088 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8089 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8090 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
8091 ahd_stat_timer, ahd);
8092 ahd_unlock();
8093 }
8094
8095 /****************************** Status Processing *****************************/
8096 void
8097 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8098 {
8099 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8100 ahd_handle_scsi_status(ahd, scb);
8101 } else {
8102 ahd_calc_residual(ahd, scb);
8103 ahd_done(ahd, scb);
8104 }
8105 }
8106
8107 void
8108 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8109 {
8110 struct hardware_scb *hscb;
8111 int paused;
8112
8113 /*
8114 * The sequencer freezes its select-out queue
8115 * anytime a SCSI status error occurs. We must
8116 * handle the error and increment our qfreeze count
8117 * to allow the sequencer to continue. We don't
8118 * bother clearing critical sections here since all
8119 * operations are on data structures that the sequencer
8120 * is not touching once the queue is frozen.
8121 */
8122 hscb = scb->hscb;
8123
8124 if (ahd_is_paused(ahd)) {
8125 paused = 1;
8126 } else {
8127 paused = 0;
8128 ahd_pause(ahd);
8129 }
8130
8131 /* Freeze the queue until the client sees the error. */
8132 ahd_freeze_devq(ahd, scb);
8133 aic_freeze_scb(scb);
8134 ahd->qfreeze_cnt++;
8135 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8136
8137 if (paused == 0)
8138 ahd_unpause(ahd);
8139
8140 /* Don't want to clobber the original sense code */
8141 if ((scb->flags & SCB_SENSE) != 0) {
8142 /*
8143 * Clear the SCB_SENSE Flag and perform
8144 * a normal command completion.
8145 */
8146 scb->flags &= ~SCB_SENSE;
8147 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8148 ahd_done(ahd, scb);
8149 return;
8150 }
8151 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8152 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8153 switch (hscb->shared_data.istatus.scsi_status) {
8154 case STATUS_PKT_SENSE:
8155 {
8156 struct scsi_status_iu_header *siu;
8157
8158 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8159 siu = (struct scsi_status_iu_header *)scb->sense_data;
8160 aic_set_scsi_status(scb, siu->status);
8161 #ifdef AHD_DEBUG
8162 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8163 ahd_print_path(ahd, scb);
8164 kprintf("SCB 0x%x Received PKT Status of 0x%x\n",
8165 SCB_GET_TAG(scb), siu->status);
8166 kprintf("\tflags = 0x%x, sense len = 0x%x, "
8167 "pktfail = 0x%x\n",
8168 siu->flags, scsi_4btoul(siu->sense_length),
8169 scsi_4btoul(siu->pkt_failures_length));
8170 }
8171 #endif
8172 if ((siu->flags & SIU_RSPVALID) != 0) {
8173 ahd_print_path(ahd, scb);
8174 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8175 kprintf("Unable to parse pkt_failures\n");
8176 } else {
8177
8178 switch (SIU_PKTFAIL_CODE(siu)) {
8179 case SIU_PFC_NONE:
8180 kprintf("No packet failure found\n");
8181 break;
8182 case SIU_PFC_CIU_FIELDS_INVALID:
8183 kprintf("Invalid Command IU Field\n");
8184 break;
8185 case SIU_PFC_TMF_NOT_SUPPORTED:
8186 kprintf("TMF not supportd\n");
8187 break;
8188 case SIU_PFC_TMF_FAILED:
8189 kprintf("TMF failed\n");
8190 break;
8191 case SIU_PFC_INVALID_TYPE_CODE:
8192 kprintf("Invalid L_Q Type code\n");
8193 break;
8194 case SIU_PFC_ILLEGAL_REQUEST:
8195 kprintf("Illegal request\n");
8196 default:
8197 break;
8198 }
8199 }
8200 if (siu->status == SCSI_STATUS_OK)
8201 aic_set_transaction_status(scb,
8202 CAM_REQ_CMP_ERR);
8203 }
8204 if ((siu->flags & SIU_SNSVALID) != 0) {
8205 scb->flags |= SCB_PKT_SENSE;
8206 #ifdef AHD_DEBUG
8207 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8208 kprintf("Sense data available\n");
8209 #endif
8210 }
8211 ahd_done(ahd, scb);
8212 break;
8213 }
8214 case SCSI_STATUS_CMD_TERMINATED:
8215 case SCSI_STATUS_CHECK_COND:
8216 {
8217 struct ahd_devinfo devinfo;
8218 struct ahd_dma_seg *sg;
8219 struct scsi_sense *sc;
8220 struct ahd_initiator_tinfo *targ_info;
8221 struct ahd_tmode_tstate *tstate;
8222 struct ahd_transinfo *tinfo;
8223 #ifdef AHD_DEBUG
8224 if (ahd_debug & AHD_SHOW_SENSE) {
8225 ahd_print_path(ahd, scb);
8226 kprintf("SCB %d: requests Check Status\n",
8227 SCB_GET_TAG(scb));
8228 }
8229 #endif
8230
8231 if (aic_perform_autosense(scb) == 0)
8232 break;
8233
8234 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8235 SCB_GET_TARGET(ahd, scb),
8236 SCB_GET_LUN(scb),
8237 SCB_GET_CHANNEL(ahd, scb),
8238 ROLE_INITIATOR);
8239 targ_info = ahd_fetch_transinfo(ahd,
8240 devinfo.channel,
8241 devinfo.our_scsiid,
8242 devinfo.target,
8243 &tstate);
8244 tinfo = &targ_info->curr;
8245 sg = scb->sg_list;
8246 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8247 /*
8248 * Save off the residual if there is one.
8249 */
8250 ahd_update_residual(ahd, scb);
8251 #ifdef AHD_DEBUG
8252 if (ahd_debug & AHD_SHOW_SENSE) {
8253 ahd_print_path(ahd, scb);
8254 kprintf("Sending Sense\n");
8255 }
8256 #endif
8257 scb->sg_count = 0;
8258 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8259 aic_get_sense_bufsize(ahd, scb),
8260 /*last*/TRUE);
8261 sc->opcode = REQUEST_SENSE;
8262 sc->byte2 = 0;
8263 if (tinfo->protocol_version <= SCSI_REV_2
8264 && SCB_GET_LUN(scb) < 8)
8265 sc->byte2 = SCB_GET_LUN(scb) << 5;
8266 sc->unused[0] = 0;
8267 sc->unused[1] = 0;
8268 sc->length = aic_get_sense_bufsize(ahd, scb);
8269 sc->control = 0;
8270
8271 /*
8272 * We can't allow the target to disconnect.
8273 * This will be an untagged transaction and
8274 * having the target disconnect will make this
8275 * transaction indestinguishable from outstanding
8276 * tagged transactions.
8277 */
8278 hscb->control = 0;
8279
8280 /*
8281 * This request sense could be because the
8282 * the device lost power or in some other
8283 * way has lost our transfer negotiations.
8284 * Renegotiate if appropriate. Unit attention
8285 * errors will be reported before any data
8286 * phases occur.
8287 */
8288 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
8289 ahd_update_neg_request(ahd, &devinfo,
8290 tstate, targ_info,
8291 AHD_NEG_IF_NON_ASYNC);
8292 }
8293 if (tstate->auto_negotiate & devinfo.target_mask) {
8294 hscb->control |= MK_MESSAGE;
8295 scb->flags &=
8296 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8297 scb->flags |= SCB_AUTO_NEGOTIATE;
8298 }
8299 hscb->cdb_len = sizeof(*sc);
8300 ahd_setup_data_scb(ahd, scb);
8301 scb->flags |= SCB_SENSE;
8302 ahd_queue_scb(ahd, scb);
8303 /*
8304 * Ensure we have enough time to actually
8305 * retrieve the sense, but only schedule
8306 * the timer if we are not in recovery or
8307 * this is a recovery SCB that is allowed
8308 * to have an active timer.
8309 */
8310 if (ahd->scb_data.recovery_scbs == 0
8311 || (scb->flags & SCB_RECOVERY_SCB) != 0)
8312 aic_scb_timer_reset(scb, 5 * 1000);
8313 break;
8314 }
8315 case SCSI_STATUS_OK:
8316 kprintf("%s: Interrupted for staus of 0???\n",
8317 ahd_name(ahd));
8318 /* FALLTHROUGH */
8319 default:
8320 ahd_done(ahd, scb);
8321 break;
8322 }
8323 }
8324
8325 /*
8326 * Calculate the residual for a just completed SCB.
8327 */
8328 void
8329 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8330 {
8331 struct hardware_scb *hscb;
8332 struct initiator_status *spkt;
8333 uint32_t sgptr;
8334 uint32_t resid_sgptr;
8335 uint32_t resid;
8336
8337 /*
8338 * 5 cases.
8339 * 1) No residual.
8340 * SG_STATUS_VALID clear in sgptr.
8341 * 2) Transferless command
8342 * 3) Never performed any transfers.
8343 * sgptr has SG_FULL_RESID set.
8344 * 4) No residual but target did not
8345 * save data pointers after the
8346 * last transfer, so sgptr was
8347 * never updated.
8348 * 5) We have a partial residual.
8349 * Use residual_sgptr to determine
8350 * where we are.
8351 */
8352
8353 hscb = scb->hscb;
8354 sgptr = aic_le32toh(hscb->sgptr);
8355 if ((sgptr & SG_STATUS_VALID) == 0)
8356 /* Case 1 */
8357 return;
8358 sgptr &= ~SG_STATUS_VALID;
8359
8360 if ((sgptr & SG_LIST_NULL) != 0)
8361 /* Case 2 */
8362 return;
8363
8364 /*
8365 * Residual fields are the same in both
8366 * target and initiator status packets,
8367 * so we can always use the initiator fields
8368 * regardless of the role for this SCB.
8369 */
8370 spkt = &hscb->shared_data.istatus;
8371 resid_sgptr = aic_le32toh(spkt->residual_sgptr);
8372 if ((sgptr & SG_FULL_RESID) != 0) {
8373 /* Case 3 */
8374 resid = aic_get_transfer_length(scb);
8375 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8376 /* Case 4 */
8377 return;
8378 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8379 ahd_print_path(ahd, scb);
8380 kprintf("data overrun detected Tag == 0x%x.\n",
8381 SCB_GET_TAG(scb));
8382 ahd_freeze_devq(ahd, scb);
8383 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8384 aic_freeze_scb(scb);
8385 return;
8386 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8387 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8388 /* NOTREACHED */
8389 } else {
8390 struct ahd_dma_seg *sg;
8391
8392 /*
8393 * Remainder of the SG where the transfer
8394 * stopped.
8395 */
8396 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8397 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8398
8399 /* The residual sg_ptr always points to the next sg */
8400 sg--;
8401
8402 /*
8403 * Add up the contents of all residual
8404 * SG segments that are after the SG where
8405 * the transfer stopped.
8406 */
8407 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8408 sg++;
8409 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
8410 }
8411 }
8412 if ((scb->flags & SCB_SENSE) == 0)
8413 aic_set_residual(scb, resid);
8414 else
8415 aic_set_sense_residual(scb, resid);
8416
8417 #ifdef AHD_DEBUG
8418 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8419 ahd_print_path(ahd, scb);
8420 kprintf("Handled %sResidual of %d bytes\n",
8421 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8422 }
8423 #endif
8424 }
8425
8426 /******************************* Target Mode **********************************/
8427 #ifdef AHD_TARGET_MODE
8428 /*
8429 * Add a target mode event to this lun's queue
8430 */
8431 static void
8432 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8433 u_int initiator_id, u_int event_type, u_int event_arg)
8434 {
8435 struct ahd_tmode_event *event;
8436 int pending;
8437
8438 xpt_freeze_devq(lstate->path, /*count*/1);
8439 if (lstate->event_w_idx >= lstate->event_r_idx)
8440 pending = lstate->event_w_idx - lstate->event_r_idx;
8441 else
8442 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8443 - (lstate->event_r_idx - lstate->event_w_idx);
8444
8445 if (event_type == EVENT_TYPE_BUS_RESET
8446 || event_type == MSG_BUS_DEV_RESET) {
8447 /*
8448 * Any earlier events are irrelevant, so reset our buffer.
8449 * This has the effect of allowing us to deal with reset
8450 * floods (an external device holding down the reset line)
8451 * without losing the event that is really interesting.
8452 */
8453 lstate->event_r_idx = 0;
8454 lstate->event_w_idx = 0;
8455 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8456 }
8457
8458 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8459 xpt_print_path(lstate->path);
8460 kprintf("immediate event %x:%x lost\n",
8461 lstate->event_buffer[lstate->event_r_idx].event_type,
8462 lstate->event_buffer[lstate->event_r_idx].event_arg);
8463 lstate->event_r_idx++;
8464 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8465 lstate->event_r_idx = 0;
8466 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8467 }
8468
8469 event = &lstate->event_buffer[lstate->event_w_idx];
8470 event->initiator_id = initiator_id;
8471 event->event_type = event_type;
8472 event->event_arg = event_arg;
8473 lstate->event_w_idx++;
8474 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8475 lstate->event_w_idx = 0;
8476 }
8477
8478 /*
8479 * Send any target mode events queued up waiting
8480 * for immediate notify resources.
8481 */
8482 void
8483 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8484 {
8485 struct ccb_hdr *ccbh;
8486 struct ccb_immed_notify *inot;
8487
8488 while (lstate->event_r_idx != lstate->event_w_idx
8489 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8490 struct ahd_tmode_event *event;
8491
8492 event = &lstate->event_buffer[lstate->event_r_idx];
8493 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8494 inot = (struct ccb_immed_notify *)ccbh;
8495 switch (event->event_type) {
8496 case EVENT_TYPE_BUS_RESET:
8497 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8498 break;
8499 default:
8500 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8501 inot->message_args[0] = event->event_type;
8502 inot->message_args[1] = event->event_arg;
8503 break;
8504 }
8505 inot->initiator_id = event->initiator_id;
8506 inot->sense_len = 0;
8507 xpt_done((union ccb *)inot);
8508 lstate->event_r_idx++;
8509 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8510 lstate->event_r_idx = 0;
8511 }
8512 }
8513 #endif
8514
8515 /******************** Sequencer Program Patching/Download *********************/
8516
8517 #ifdef AHD_DUMP_SEQ
8518 void
8519 ahd_dumpseq(struct ahd_softc* ahd)
8520 {
8521 int i;
8522 int max_prog;
8523
8524 max_prog = 2048;
8525
8526 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8527 ahd_outw(ahd, PRGMCNT, 0);
8528 for (i = 0; i < max_prog; i++) {
8529 uint8_t ins_bytes[4];
8530
8531 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8532 kprintf("0x%08x\n", ins_bytes[0] << 24
8533 | ins_bytes[1] << 16
8534 | ins_bytes[2] << 8
8535 | ins_bytes[3]);
8536 }
8537 }
8538 #endif
8539
8540 static void
8541 ahd_loadseq(struct ahd_softc *ahd)
8542 {
8543 struct cs cs_table[num_critical_sections];
8544 u_int begin_set[num_critical_sections];
8545 u_int end_set[num_critical_sections];
8546 struct patch *cur_patch;
8547 u_int cs_count;
8548 u_int cur_cs;
8549 u_int i;
8550 int downloaded;
8551 u_int skip_addr;
8552 u_int sg_prefetch_cnt;
8553 u_int sg_prefetch_cnt_limit;
8554 u_int sg_prefetch_align;
8555 u_int sg_size;
8556 u_int cacheline_mask;
8557 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8558
8559 if (bootverbose)
8560 kprintf("%s: Downloading Sequencer Program...",
8561 ahd_name(ahd));
8562
8563 #if DOWNLOAD_CONST_COUNT != 8
8564 #error "Download Const Mismatch"
8565 #endif
8566 /*
8567 * Start out with 0 critical sections
8568 * that apply to this firmware load.
8569 */
8570 cs_count = 0;
8571 cur_cs = 0;
8572 memset(begin_set, 0, sizeof(begin_set));
8573 memset(end_set, 0, sizeof(end_set));
8574
8575 /*
8576 * Setup downloadable constant table.
8577 *
8578 * The computation for the S/G prefetch variables is
8579 * a bit complicated. We would like to always fetch
8580 * in terms of cachelined sized increments. However,
8581 * if the cacheline is not an even multiple of the
8582 * SG element size or is larger than our SG RAM, using
8583 * just the cache size might leave us with only a portion
8584 * of an SG element at the tail of a prefetch. If the
8585 * cacheline is larger than our S/G prefetch buffer less
8586 * the size of an SG element, we may round down to a cacheline
8587 * that doesn't contain any or all of the S/G of interest
8588 * within the bounds of our S/G ram. Provide variables to
8589 * the sequencer that will allow it to handle these edge
8590 * cases.
8591 */
8592 /* Start by aligning to the nearest cacheline. */
8593 sg_prefetch_align = ahd->pci_cachesize;
8594 if (sg_prefetch_align == 0)
8595 sg_prefetch_align = 8;
8596 /* Round down to the nearest power of 2. */
8597 while (powerof2(sg_prefetch_align) == 0)
8598 sg_prefetch_align--;
8599
8600 cacheline_mask = sg_prefetch_align - 1;
8601
8602 /*
8603 * If the cacheline boundary is greater than half our prefetch RAM
8604 * we risk not being able to fetch even a single complete S/G
8605 * segment if we align to that boundary.
8606 */
8607 if (sg_prefetch_align > CCSGADDR_MAX/2)
8608 sg_prefetch_align = CCSGADDR_MAX/2;
8609 /* Start by fetching a single cacheline. */
8610 sg_prefetch_cnt = sg_prefetch_align;
8611 /*
8612 * Increment the prefetch count by cachelines until
8613 * at least one S/G element will fit.
8614 */
8615 sg_size = sizeof(struct ahd_dma_seg);
8616 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8617 sg_size = sizeof(struct ahd_dma64_seg);
8618 while (sg_prefetch_cnt < sg_size)
8619 sg_prefetch_cnt += sg_prefetch_align;
8620 /*
8621 * If the cacheline is not an even multiple of
8622 * the S/G size, we may only get a partial S/G when
8623 * we align. Add a cacheline if this is the case.
8624 */
8625 if ((sg_prefetch_align % sg_size) != 0
8626 && (sg_prefetch_cnt < CCSGADDR_MAX))
8627 sg_prefetch_cnt += sg_prefetch_align;
8628 /*
8629 * Lastly, compute a value that the sequencer can use
8630 * to determine if the remainder of the CCSGRAM buffer
8631 * has a full S/G element in it.
8632 */
8633 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8634 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8635 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8636 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8637 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8638 download_consts[SG_SIZEOF] = sg_size;
8639 download_consts[PKT_OVERRUN_BUFOFFSET] =
8640 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8641 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8642 download_consts[CACHELINE_MASK] = cacheline_mask;
8643 cur_patch = patches;
8644 downloaded = 0;
8645 skip_addr = 0;
8646 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8647 ahd_outw(ahd, PRGMCNT, 0);
8648
8649 for (i = 0; i < sizeof(seqprog)/4; i++) {
8650 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8651 /*
8652 * Don't download this instruction as it
8653 * is in a patch that was removed.
8654 */
8655 continue;
8656 }
8657 /*
8658 * Move through the CS table until we find a CS
8659 * that might apply to this instruction.
8660 */
8661 for (; cur_cs < num_critical_sections; cur_cs++) {
8662 if (critical_sections[cur_cs].end <= i) {
8663 if (begin_set[cs_count] == TRUE
8664 && end_set[cs_count] == FALSE) {
8665 cs_table[cs_count].end = downloaded;
8666 end_set[cs_count] = TRUE;
8667 cs_count++;
8668 }
8669 continue;
8670 }
8671 if (critical_sections[cur_cs].begin <= i
8672 && begin_set[cs_count] == FALSE) {
8673 cs_table[cs_count].begin = downloaded;
8674 begin_set[cs_count] = TRUE;
8675 }
8676 break;
8677 }
8678 ahd_download_instr(ahd, i, download_consts);
8679 downloaded++;
8680 }
8681
8682 ahd->num_critical_sections = cs_count;
8683 if (cs_count != 0) {
8684 cs_count *= sizeof(struct cs);
8685 ahd->critical_sections = kmalloc(cs_count, M_DEVBUF, M_INTWAIT);
8686 memcpy(ahd->critical_sections, cs_table, cs_count);
8687 }
8688 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8689
8690 if (bootverbose) {
8691 kprintf(" %d instructions downloaded\n", downloaded);
8692 kprintf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8693 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8694 }
8695 }
8696
8697 static int
8698 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8699 u_int start_instr, u_int *skip_addr)
8700 {
8701 struct patch *cur_patch;
8702 struct patch *last_patch;
8703 u_int num_patches;
8704
8705 num_patches = sizeof(patches)/sizeof(struct patch);
8706 last_patch = &patches[num_patches];
8707 cur_patch = *start_patch;
8708
8709 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8710
8711 if (cur_patch->patch_func(ahd) == 0) {
8712
8713 /* Start rejecting code */
8714 *skip_addr = start_instr + cur_patch->skip_instr;
8715 cur_patch += cur_patch->skip_patch;
8716 } else {
8717 /* Accepted this patch. Advance to the next
8718 * one and wait for our intruction pointer to
8719 * hit this point.
8720 */
8721 cur_patch++;
8722 }
8723 }
8724
8725 *start_patch = cur_patch;
8726 if (start_instr < *skip_addr)
8727 /* Still skipping */
8728 return (0);
8729
8730 return (1);
8731 }
8732
8733 static u_int
8734 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8735 {
8736 struct patch *cur_patch;
8737 int address_offset;
8738 u_int skip_addr;
8739 u_int i;
8740
8741 address_offset = 0;
8742 cur_patch = patches;
8743 skip_addr = 0;
8744
8745 for (i = 0; i < address;) {
8746
8747 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8748
8749 if (skip_addr > i) {
8750 int end_addr;
8751
8752 end_addr = MIN(address, skip_addr);
8753 address_offset += end_addr - i;
8754 i = skip_addr;
8755 } else {
8756 i++;
8757 }
8758 }
8759 return (address - address_offset);
8760 }
8761
8762 static void
8763 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8764 {
8765 union ins_formats instr;
8766 struct ins_format1 *fmt1_ins;
8767 struct ins_format3 *fmt3_ins;
8768 u_int opcode;
8769
8770 /*
8771 * The firmware is always compiled into a little endian format.
8772 */
8773 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8774
8775 fmt1_ins = &instr.format1;
8776 fmt3_ins = NULL;
8777
8778 /* Pull the opcode */
8779 opcode = instr.format1.opcode;
8780 switch (opcode) {
8781 case AIC_OP_JMP:
8782 case AIC_OP_JC:
8783 case AIC_OP_JNC:
8784 case AIC_OP_CALL:
8785 case AIC_OP_JNE:
8786 case AIC_OP_JNZ:
8787 case AIC_OP_JE:
8788 case AIC_OP_JZ:
8789 {
8790 fmt3_ins = &instr.format3;
8791 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8792 /* FALLTHROUGH */
8793 }
8794 case AIC_OP_OR:
8795 case AIC_OP_AND:
8796 case AIC_OP_XOR:
8797 case AIC_OP_ADD:
8798 case AIC_OP_ADC:
8799 case AIC_OP_BMOV:
8800 if (fmt1_ins->parity != 0) {
8801 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8802 }
8803 fmt1_ins->parity = 0;
8804 /* FALLTHROUGH */
8805 case AIC_OP_ROL:
8806 {
8807 int i, count;
8808
8809 /* Calculate odd parity for the instruction */
8810 for (i = 0, count = 0; i < 31; i++) {
8811 uint32_t mask;
8812
8813 mask = 0x01 << i;
8814 if ((instr.integer & mask) != 0)
8815 count++;
8816 }
8817 if ((count & 0x01) == 0)
8818 instr.format1.parity = 1;
8819
8820 /* The sequencer is a little endian cpu */
8821 instr.integer = aic_htole32(instr.integer);
8822 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8823 break;
8824 }
8825 default:
8826 panic("Unknown opcode encountered in seq program");
8827 break;
8828 }
8829 }
8830
8831 static int
8832 ahd_probe_stack_size(struct ahd_softc *ahd)
8833 {
8834 int last_probe;
8835
8836 last_probe = 0;
8837 while (1) {
8838 int i;
8839
8840 /*
8841 * We avoid using 0 as a pattern to avoid
8842 * confusion if the stack implementation
8843 * "back-fills" with zeros when "poping'
8844 * entries.
8845 */
8846 for (i = 1; i <= last_probe+1; i++) {
8847 ahd_outb(ahd, STACK, i & 0xFF);
8848 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8849 }
8850
8851 /* Verify */
8852 for (i = last_probe+1; i > 0; i--) {
8853 u_int stack_entry;
8854
8855 stack_entry = ahd_inb(ahd, STACK)
8856 |(ahd_inb(ahd, STACK) << 8);
8857 if (stack_entry != i)
8858 goto sized;
8859 }
8860 last_probe++;
8861 }
8862 sized:
8863 return (last_probe);
8864 }
8865
8866 void
8867 ahd_dump_all_cards_state(void)
8868 {
8869 struct ahd_softc *list_ahd;
8870
8871 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8872 ahd_dump_card_state(list_ahd);
8873 }
8874 }
8875
8876 int
8877 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8878 const char *name, u_int address, u_int value,
8879 u_int *cur_column, u_int wrap_point)
8880 {
8881 int printed;
8882 u_int printed_mask;
8883
8884 if (cur_column != NULL && *cur_column >= wrap_point) {
8885 kprintf("\n");
8886 *cur_column = 0;
8887 }
8888 printed = kprintf("%s[0x%x]", name, value);
8889 if (table == NULL) {
8890 printed += kprintf(" ");
8891 *cur_column += printed;
8892 return (printed);
8893 }
8894 printed_mask = 0;
8895 while (printed_mask != 0xFF) {
8896 int entry;
8897
8898 for (entry = 0; entry < num_entries; entry++) {
8899 if (((value & table[entry].mask)
8900 != table[entry].value)
8901 || ((printed_mask & table[entry].mask)
8902 == table[entry].mask))
8903 continue;
8904
8905 printed += kprintf("%s%s",
8906 printed_mask == 0 ? ":(" : "|",
8907 table[entry].name);
8908 printed_mask |= table[entry].mask;
8909
8910 break;
8911 }
8912 if (entry >= num_entries)
8913 break;
8914 }
8915 if (printed_mask != 0)
8916 printed += kprintf(") ");
8917 else
8918 printed += kprintf(" ");
8919 if (cur_column != NULL)
8920 *cur_column += printed;
8921 return (printed);
8922 }
8923
8924 void
8925 ahd_dump_card_state(struct ahd_softc *ahd)
8926 {
8927 struct scb *scb;
8928 ahd_mode_state saved_modes;
8929 u_int dffstat;
8930 int paused;
8931 u_int scb_index;
8932 u_int saved_scb_index;
8933 u_int cur_col;
8934 int i;
8935
8936 if (ahd_is_paused(ahd)) {
8937 paused = 1;
8938 } else {
8939 paused = 0;
8940 ahd_pause(ahd);
8941 }
8942 saved_modes = ahd_save_modes(ahd);
8943 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8944 kprintf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8945 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8946 ahd_name(ahd),
8947 ahd_inw(ahd, CURADDR),
8948 ahd_build_mode_state(ahd, ahd->saved_src_mode,
8949 ahd->saved_dst_mode));
8950 if (paused)
8951 kprintf("Card was paused\n");
8952
8953 if (ahd_check_cmdcmpltqueues(ahd))
8954 kprintf("Completions are pending\n");
8955
8956 /*
8957 * Mode independent registers.
8958 */
8959 cur_col = 0;
8960 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
8961 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
8962 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
8963 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8964 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8965 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8966 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8967 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8968 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8969 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8970 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8971 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8972 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8973 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8974 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8975 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8976 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8977 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8978 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
8979 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
8980 &cur_col, 50);
8981 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
8982 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
8983 &cur_col, 50);
8984 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
8985 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
8986 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
8987 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
8988 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
8989 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
8990 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
8991 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
8992 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
8993 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
8994 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
8995 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
8996 kprintf("\n");
8997 kprintf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8998 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8999 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
9000 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
9001 ahd_inw(ahd, NEXTSCB));
9002 cur_col = 0;
9003 /* QINFIFO */
9004 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
9005 CAM_LUN_WILDCARD, SCB_LIST_NULL,
9006 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
9007 saved_scb_index = ahd_get_scbptr(ahd);
9008 kprintf("Pending list:");
9009 i = 0;
9010 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9011 if (i++ > AHD_SCB_MAX)
9012 break;
9013 cur_col = kprintf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
9014 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
9015 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9016 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
9017 &cur_col, 60);
9018 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
9019 &cur_col, 60);
9020 }
9021 kprintf("\nTotal %d\n", i);
9022
9023 kprintf("Kernel Free SCB list: ");
9024 i = 0;
9025 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
9026 struct scb *list_scb;
9027
9028 list_scb = scb;
9029 do {
9030 kprintf("%d ", SCB_GET_TAG(list_scb));
9031 list_scb = LIST_NEXT(list_scb, collision_links);
9032 } while (list_scb && i++ < AHD_SCB_MAX);
9033 }
9034
9035 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
9036 if (i++ > AHD_SCB_MAX)
9037 break;
9038 kprintf("%d ", SCB_GET_TAG(scb));
9039 }
9040 kprintf("\n");
9041
9042 kprintf("Sequencer Complete DMA-inprog list: ");
9043 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
9044 i = 0;
9045 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9046 ahd_set_scbptr(ahd, scb_index);
9047 kprintf("%d ", scb_index);
9048 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9049 }
9050 kprintf("\n");
9051
9052 kprintf("Sequencer Complete list: ");
9053 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9054 i = 0;
9055 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9056 ahd_set_scbptr(ahd, scb_index);
9057 kprintf("%d ", scb_index);
9058 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9059 }
9060 kprintf("\n");
9061
9062
9063 kprintf("Sequencer DMA-Up and Complete list: ");
9064 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9065 i = 0;
9066 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9067 ahd_set_scbptr(ahd, scb_index);
9068 kprintf("%d ", scb_index);
9069 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9070 }
9071 kprintf("\n");
9072 kprintf("Sequencer On QFreeze and Complete list: ");
9073 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9074 i = 0;
9075 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9076 ahd_set_scbptr(ahd, scb_index);
9077 kprintf("%d ", scb_index);
9078 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9079 }
9080 kprintf("\n");
9081 ahd_set_scbptr(ahd, saved_scb_index);
9082 dffstat = ahd_inb(ahd, DFFSTAT);
9083 for (i = 0; i < 2; i++) {
9084 #ifdef AHD_DEBUG
9085 struct scb *fifo_scb;
9086 #endif
9087 u_int fifo_scbptr;
9088
9089 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9090 fifo_scbptr = ahd_get_scbptr(ahd);
9091 kprintf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9092 ahd_name(ahd), i,
9093 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9094 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9095 cur_col = 0;
9096 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9097 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9098 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9099 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9100 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9101 &cur_col, 50);
9102 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9103 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9104 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9105 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9106 if (cur_col > 50) {
9107 kprintf("\n");
9108 cur_col = 0;
9109 }
9110 cur_col += kprintf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9111 ahd_inl(ahd, SHADDR+4),
9112 ahd_inl(ahd, SHADDR),
9113 (ahd_inb(ahd, SHCNT)
9114 | (ahd_inb(ahd, SHCNT + 1) << 8)
9115 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9116 if (cur_col > 50) {
9117 kprintf("\n");
9118 cur_col = 0;
9119 }
9120 cur_col += kprintf("HADDR = 0x%x%x, HCNT = 0x%x ",
9121 ahd_inl(ahd, HADDR+4),
9122 ahd_inl(ahd, HADDR),
9123 (ahd_inb(ahd, HCNT)
9124 | (ahd_inb(ahd, HCNT + 1) << 8)
9125 | (ahd_inb(ahd, HCNT + 2) << 16)));
9126 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9127 #ifdef AHD_DEBUG
9128 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9129 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9130 if (fifo_scb != NULL)
9131 ahd_dump_sglist(fifo_scb);
9132 }
9133 #endif
9134 }
9135 kprintf("\nLQIN: ");
9136 for (i = 0; i < 20; i++)
9137 kprintf("0x%x ", ahd_inb(ahd, LQIN + i));
9138 kprintf("\n");
9139 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9140 kprintf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9141 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9142 ahd_inb(ahd, OPTIONMODE));
9143 kprintf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9144 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9145 ahd_inb(ahd, MAXCMDCNT));
9146 kprintf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9147 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9148 ahd_inb(ahd, SAVED_LUN));
9149 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9150 kprintf("\n");
9151 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9152 cur_col = 0;
9153 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9154 kprintf("\n");
9155 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9156 kprintf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9157 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9158 ahd_inw(ahd, DINDEX));
9159 kprintf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9160 ahd_name(ahd), ahd_get_scbptr(ahd),
9161 ahd_inw_scbram(ahd, SCB_NEXT),
9162 ahd_inw_scbram(ahd, SCB_NEXT2));
9163 kprintf("CDB %x %x %x %x %x %x\n",
9164 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9165 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9166 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9167 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9168 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9169 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9170 kprintf("STACK:");
9171 for (i = 0; i < ahd->stack_size; i++) {
9172 ahd->saved_stack[i] =
9173 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9174 kprintf(" 0x%x", ahd->saved_stack[i]);
9175 }
9176 for (i = ahd->stack_size-1; i >= 0; i--) {
9177 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9178 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9179 }
9180 kprintf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9181 ahd_platform_dump_card_state(ahd);
9182 ahd_restore_modes(ahd, saved_modes);
9183 if (paused == 0)
9184 ahd_unpause(ahd);
9185 }
9186
9187 void
9188 ahd_dump_scbs(struct ahd_softc *ahd)
9189 {
9190 ahd_mode_state saved_modes;
9191 u_int saved_scb_index;
9192 int i;
9193
9194 saved_modes = ahd_save_modes(ahd);
9195 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9196 saved_scb_index = ahd_get_scbptr(ahd);
9197 for (i = 0; i < AHD_SCB_MAX; i++) {
9198 ahd_set_scbptr(ahd, i);
9199 kprintf("%3d", i);
9200 kprintf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9201 ahd_inb_scbram(ahd, SCB_CONTROL),
9202 ahd_inb_scbram(ahd, SCB_SCSIID),
9203 ahd_inw_scbram(ahd, SCB_NEXT),
9204 ahd_inw_scbram(ahd, SCB_NEXT2),
9205 ahd_inl_scbram(ahd, SCB_SGPTR),
9206 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9207 }
9208 kprintf("\n");
9209 ahd_set_scbptr(ahd, saved_scb_index);
9210 ahd_restore_modes(ahd, saved_modes);
9211 }
9212
9213
9214 /*************************** Timeout Handling *********************************/
9215 void
9216 ahd_timeout(struct scb *scb)
9217 {
9218 struct ahd_softc *ahd;
9219
9220 ahd = scb->ahd_softc;
9221 if ((scb->flags & SCB_ACTIVE) != 0) {
9222 if ((scb->flags & SCB_TIMEDOUT) == 0) {
9223 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb,
9224 timedout_links);
9225 scb->flags |= SCB_TIMEDOUT;
9226 }
9227 ahd_wakeup_recovery_thread(ahd);
9228 }
9229 }
9230
9231 /*
9232 * ahd_recover_commands determines if any of the commands that have currently
9233 * timedout are the root cause for this timeout. Innocent commands are given
9234 * a new timeout while we wait for the command executing on the bus to timeout.
9235 * This routine is invoked from a thread context so we are allowed to sleep.
9236 * Our lock is not held on entry.
9237 */
9238 void
9239 ahd_recover_commands(struct ahd_softc *ahd)
9240 {
9241 struct scb *scb;
9242 struct scb *active_scb;
9243 int found;
9244 int was_paused;
9245 u_int active_scbptr;
9246 u_int last_phase;
9247
9248 ahd_lock();
9249
9250 /*
9251 * Pause the controller and manually flush any
9252 * commands that have just completed but that our
9253 * interrupt handler has yet to see.
9254 */
9255 was_paused = ahd_is_paused(ahd);
9256
9257 kprintf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd),
9258 was_paused ? "" : "not ");
9259 ahd_dump_card_state(ahd);
9260
9261 ahd_pause_and_flushwork(ahd);
9262
9263 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) {
9264 /*
9265 * The timedout commands have already
9266 * completed. This typically means
9267 * that either the timeout value was on
9268 * the hairy edge of what the device
9269 * requires or - more likely - interrupts
9270 * are not happening.
9271 */
9272 kprintf("%s: Timedout SCBs already complete. "
9273 "Interrupts may not be functioning.\n", ahd_name(ahd));
9274 ahd_unpause(ahd);
9275 ahd_unlock();
9276 return;
9277 }
9278
9279 /*
9280 * Determine identity of SCB acting on the bus.
9281 * This test only catches non-packetized transactions.
9282 * Due to the fleeting nature of packetized operations,
9283 * we can't easily determine that a packetized operation
9284 * is on the bus.
9285 */
9286 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9287 last_phase = ahd_inb(ahd, LASTPHASE);
9288 active_scbptr = ahd_get_scbptr(ahd);
9289 active_scb = NULL;
9290 if (last_phase != P_BUSFREE
9291 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)
9292 active_scb = ahd_lookup_scb(ahd, active_scbptr);
9293
9294 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9295 int target;
9296 int lun;
9297 char channel;
9298
9299 target = SCB_GET_TARGET(ahd, scb);
9300 channel = SCB_GET_CHANNEL(ahd, scb);
9301 lun = SCB_GET_LUN(scb);
9302
9303 ahd_print_path(ahd, scb);
9304 kprintf("SCB %d - timed out\n", SCB_GET_TAG(scb));
9305
9306 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
9307 /*
9308 * Been down this road before.
9309 * Do a full bus reset.
9310 */
9311 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
9312 bus_reset:
9313 found = ahd_reset_channel(ahd, channel,
9314 /*Initiate Reset*/TRUE);
9315 kprintf("%s: Issued Channel %c Bus Reset. "
9316 "%d SCBs aborted\n", ahd_name(ahd), channel,
9317 found);
9318 continue;
9319 }
9320
9321 /*
9322 * Remove the command from the timedout list in
9323 * preparation for requeing it.
9324 */
9325 LIST_REMOVE(scb, timedout_links);
9326 scb->flags &= ~SCB_TIMEDOUT;
9327
9328 if (active_scb != NULL) {
9329
9330 if (active_scb != scb) {
9331
9332 /*
9333 * If the active SCB is not us, assume that
9334 * the active SCB has a longer timeout than
9335 * the timedout SCB, and wait for the active
9336 * SCB to timeout. As a safeguard, only
9337 * allow this deferral to continue if some
9338 * untimed-out command is outstanding.
9339 */
9340 if (ahd_other_scb_timeout(ahd, scb,
9341 active_scb) == 0)
9342 goto bus_reset;
9343 continue;
9344 }
9345
9346 /*
9347 * We're active on the bus, so assert ATN
9348 * and hope that the target responds.
9349 */
9350 ahd_set_recoveryscb(ahd, active_scb);
9351 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
9352 ahd_outb(ahd, MSG_OUT, HOST_MSG);
9353 ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
9354 ahd_print_path(ahd, active_scb);
9355 kprintf("BDR message in message buffer\n");
9356 aic_scb_timer_reset(scb, 2 * 1000);
9357 break;
9358 } else if (last_phase != P_BUSFREE
9359 && ahd_inb(ahd, SCSIPHASE) == 0) {
9360 /*
9361 * SCB is not identified, there
9362 * is no pending REQ, and the sequencer
9363 * has not seen a busfree. Looks like
9364 * a stuck connection waiting to
9365 * go busfree. Reset the bus.
9366 */
9367 kprintf("%s: Connection stuck awaiting busfree or "
9368 "Identify Msg.\n", ahd_name(ahd));
9369 goto bus_reset;
9370 } else if (ahd_search_qinfifo(ahd, target, channel, lun,
9371 SCB_GET_TAG(scb),
9372 ROLE_INITIATOR, /*status*/0,
9373 SEARCH_COUNT) > 0) {
9374
9375 /*
9376 * We haven't even gone out on the bus
9377 * yet, so the timeout must be due to
9378 * some other command. Reset the timer
9379 * and go on.
9380 */
9381 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0)
9382 goto bus_reset;
9383 } else {
9384 /*
9385 * This SCB is for a disconnected transaction
9386 * and we haven't found a better candidate on
9387 * the bus to explain this timeout.
9388 */
9389 ahd_set_recoveryscb(ahd, scb);
9390
9391 /*
9392 * Actually re-queue this SCB in an attempt
9393 * to select the device before it reconnects.
9394 * In either case (selection or reselection),
9395 * we will now issue a target reset to the
9396 * timed-out device.
9397 */
9398 scb->flags |= SCB_DEVICE_RESET;
9399 scb->hscb->cdb_len = 0;
9400 scb->hscb->task_attribute = 0;
9401 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK;
9402
9403 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9404 if ((scb->flags & SCB_PACKETIZED) != 0) {
9405 /*
9406 * Mark the SCB has having an outstanding
9407 * task management function. Should the command
9408 * complete normally before the task management
9409 * function can be sent, the host will be
9410 * notified to abort our requeued SCB.
9411 */
9412 ahd_outb(ahd, SCB_TASK_MANAGEMENT,
9413 scb->hscb->task_management);
9414 } else {
9415 /*
9416 * If non-packetized, set the MK_MESSAGE control
9417 * bit indicating that we desire to send a
9418 * message. We also set the disconnected flag
9419 * since there is no guarantee that our SCB
9420 * control byte matches the version on the
9421 * card. We don't want the sequencer to abort
9422 * the command thinking an unsolicited
9423 * reselection occurred.
9424 */
9425 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
9426
9427 /*
9428 * The sequencer will never re-reference the
9429 * in-core SCB. To make sure we are notified
9430 * during reslection, set the MK_MESSAGE flag in
9431 * the card's copy of the SCB.
9432 */
9433 ahd_outb(ahd, SCB_CONTROL,
9434 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE);
9435 }
9436
9437 /*
9438 * Clear out any entries in the QINFIFO first
9439 * so we are the next SCB for this target
9440 * to run.
9441 */
9442 ahd_search_qinfifo(ahd, target, channel, lun,
9443 SCB_LIST_NULL, ROLE_INITIATOR,
9444 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
9445 ahd_qinfifo_requeue_tail(ahd, scb);
9446 ahd_set_scbptr(ahd, active_scbptr);
9447 ahd_print_path(ahd, scb);
9448 kprintf("Queuing a BDR SCB\n");
9449 aic_scb_timer_reset(scb, 2 * 1000);
9450 break;
9451 }
9452 }
9453
9454 /*
9455 * Any remaining SCBs were not the "culprit", so remove
9456 * them from the timeout list. The timer for these commands
9457 * will be reset once the recovery SCB completes.
9458 */
9459 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9460
9461 LIST_REMOVE(scb, timedout_links);
9462 scb->flags &= ~SCB_TIMEDOUT;
9463 }
9464
9465 ahd_unpause(ahd);
9466 ahd_unlock();
9467 }
9468
9469 /*
9470 * Re-schedule a timeout for the passed in SCB if we determine that some
9471 * other SCB is in the process of recovery or an SCB with a longer
9472 * timeout is still pending. Limit our search to just "other_scb"
9473 * if it is non-NULL.
9474 */
9475 static int
9476 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb,
9477 struct scb *other_scb)
9478 {
9479 u_int newtimeout;
9480 int found;
9481
9482 ahd_print_path(ahd, scb);
9483 kprintf("Other SCB Timeout%s",
9484 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
9485 ? " again\n" : "\n");
9486
9487 newtimeout = aic_get_timeout(scb);
9488 scb->flags |= SCB_OTHERTCL_TIMEOUT;
9489 found = 0;
9490 if (other_scb != NULL) {
9491 if ((other_scb->flags
9492 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9493 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9494 found++;
9495 newtimeout = MAX(aic_get_timeout(other_scb),
9496 newtimeout);
9497 }
9498 } else {
9499 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) {
9500 if ((other_scb->flags
9501 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9502 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9503 found++;
9504 newtimeout = MAX(aic_get_timeout(other_scb),
9505 newtimeout);
9506 }
9507 }
9508 }
9509
9510 if (found != 0)
9511 aic_scb_timer_reset(scb, newtimeout);
9512 else {
9513 ahd_print_path(ahd, scb);
9514 kprintf("No other SCB worth waiting for...\n");
9515 }
9516
9517 return (found != 0);
9518 }
9519
9520 /**************************** Flexport Logic **********************************/
9521 /*
9522 * Read count 16bit words from 16bit word address start_addr from the
9523 * SEEPROM attached to the controller, into buf, using the controller's
9524 * SEEPROM reading state machine. Optionally treat the data as a byte
9525 * stream in terms of byte order.
9526 */
9527 int
9528 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9529 u_int start_addr, u_int count, int bytestream)
9530 {
9531 u_int cur_addr;
9532 u_int end_addr;
9533 int error;
9534
9535 /*
9536 * If we never make it through the loop even once,
9537 * we were passed invalid arguments.
9538 */
9539 error = EINVAL;
9540 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9541 end_addr = start_addr + count;
9542 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9543
9544 ahd_outb(ahd, SEEADR, cur_addr);
9545 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9546
9547 error = ahd_wait_seeprom(ahd);
9548 if (error)
9549 break;
9550 if (bytestream != 0) {
9551 uint8_t *bytestream_ptr;
9552
9553 bytestream_ptr = (uint8_t *)buf;
9554 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9555 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9556 } else {
9557 /*
9558 * ahd_inw() already handles machine byte order.
9559 */
9560 *buf = ahd_inw(ahd, SEEDAT);
9561 }
9562 buf++;
9563 }
9564 return (error);
9565 }
9566
9567 /*
9568 * Write count 16bit words from buf, into SEEPROM attache to the
9569 * controller starting at 16bit word address start_addr, using the
9570 * controller's SEEPROM writing state machine.
9571 */
9572 int
9573 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9574 u_int start_addr, u_int count)
9575 {
9576 u_int cur_addr;
9577 u_int end_addr;
9578 int error;
9579 int retval;
9580
9581 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9582 error = ENOENT;
9583
9584 /* Place the chip into write-enable mode */
9585 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9586 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9587 error = ahd_wait_seeprom(ahd);
9588 if (error)
9589 return (error);
9590
9591 /*
9592 * Write the data. If we don't get throught the loop at
9593 * least once, the arguments were invalid.
9594 */
9595 retval = EINVAL;
9596 end_addr = start_addr + count;
9597 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9598 ahd_outw(ahd, SEEDAT, *buf++);
9599 ahd_outb(ahd, SEEADR, cur_addr);
9600 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9601
9602 retval = ahd_wait_seeprom(ahd);
9603 if (retval)
9604 break;
9605 }
9606
9607 /*
9608 * Disable writes.
9609 */
9610 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9611 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9612 error = ahd_wait_seeprom(ahd);
9613 if (error)
9614 return (error);
9615 return (retval);
9616 }
9617
9618 /*
9619 * Wait ~100us for the serial eeprom to satisfy our request.
9620 */
9621 int
9622 ahd_wait_seeprom(struct ahd_softc *ahd)
9623 {
9624 int cnt;
9625
9626 cnt = 5000;
9627 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9628 aic_delay(5);
9629
9630 if (cnt == 0)
9631 return (ETIMEDOUT);
9632 return (0);
9633 }
9634
9635 /*
9636 * Validate the two checksums in the per_channel
9637 * vital product data struct.
9638 */
9639 int
9640 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9641 {
9642 int i;
9643 int maxaddr;
9644 uint32_t checksum;
9645 uint8_t *vpdarray;
9646
9647 vpdarray = (uint8_t *)vpd;
9648 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9649 checksum = 0;
9650 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9651 checksum = checksum + vpdarray[i];
9652 if (checksum == 0
9653 || (-checksum & 0xFF) != vpd->vpd_checksum)
9654 return (0);
9655
9656 checksum = 0;
9657 maxaddr = offsetof(struct vpd_config, checksum);
9658 for (i = offsetof(struct vpd_config, default_target_flags);
9659 i < maxaddr; i++)
9660 checksum = checksum + vpdarray[i];
9661 if (checksum == 0
9662 || (-checksum & 0xFF) != vpd->checksum)
9663 return (0);
9664 return (1);
9665 }
9666
9667 int
9668 ahd_verify_cksum(struct seeprom_config *sc)
9669 {
9670 int i;
9671 int maxaddr;
9672 uint32_t checksum;
9673 uint16_t *scarray;
9674
9675 maxaddr = (sizeof(*sc)/2) - 1;
9676 checksum = 0;
9677 scarray = (uint16_t *)sc;
9678
9679 for (i = 0; i < maxaddr; i++)
9680 checksum = checksum + scarray[i];
9681 if (checksum == 0
9682 || (checksum & 0xFFFF) != sc->checksum) {
9683 return (0);
9684 } else {
9685 return (1);
9686 }
9687 }
9688
9689 int
9690 ahd_acquire_seeprom(struct ahd_softc *ahd)
9691 {
9692 /*
9693 * We should be able to determine the SEEPROM type
9694 * from the flexport logic, but unfortunately not
9695 * all implementations have this logic and there is
9696 * no programatic method for determining if the logic
9697 * is present.
9698 */
9699 return (1);
9700 #if 0
9701 uint8_t seetype;
9702 int error;
9703
9704 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9705 if (error != 0
9706 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9707 return (0);
9708 return (1);
9709 #endif
9710 }
9711
9712 void
9713 ahd_release_seeprom(struct ahd_softc *ahd)
9714 {
9715 /* Currently a no-op */
9716 }
9717
9718 int
9719 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9720 {
9721 int error;
9722
9723 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9724 if (addr > 7)
9725 panic("ahd_write_flexport: address out of range");
9726 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9727 error = ahd_wait_flexport(ahd);
9728 if (error != 0)
9729 return (error);
9730 ahd_outb(ahd, BRDDAT, value);
9731 ahd_flush_device_writes(ahd);
9732 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9733 ahd_flush_device_writes(ahd);
9734 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9735 ahd_flush_device_writes(ahd);
9736 ahd_outb(ahd, BRDCTL, 0);
9737 ahd_flush_device_writes(ahd);
9738 return (0);
9739 }
9740
9741 int
9742 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9743 {
9744 int error;
9745
9746 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9747 if (addr > 7)
9748 panic("ahd_read_flexport: address out of range");
9749 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9750 error = ahd_wait_flexport(ahd);
9751 if (error != 0)
9752 return (error);
9753 *value = ahd_inb(ahd, BRDDAT);
9754 ahd_outb(ahd, BRDCTL, 0);
9755 ahd_flush_device_writes(ahd);
9756 return (0);
9757 }
9758
9759 /*
9760 * Wait at most 2 seconds for flexport arbitration to succeed.
9761 */
9762 int
9763 ahd_wait_flexport(struct ahd_softc *ahd)
9764 {
9765 int cnt;
9766
9767 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9768 cnt = 1000000 * 2 / 5;
9769 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9770 aic_delay(5);
9771
9772 if (cnt == 0)
9773 return (ETIMEDOUT);
9774 return (0);
9775 }
9776
9777 /************************* Target Mode ****************************************/
9778 #ifdef AHD_TARGET_MODE
9779 cam_status
9780 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9781 struct ahd_tmode_tstate **tstate,
9782 struct ahd_tmode_lstate **lstate,
9783 int notfound_failure)
9784 {
9785
9786 if ((ahd->features & AHD_TARGETMODE) == 0)
9787 return (CAM_REQ_INVALID);
9788
9789 /*
9790 * Handle the 'black hole' device that sucks up
9791 * requests to unattached luns on enabled targets.
9792 */
9793 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9794 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9795 *tstate = NULL;
9796 *lstate = ahd->black_hole;
9797 } else {
9798 u_int max_id;
9799
9800 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9801 if (ccb->ccb_h.target_id > max_id)
9802 return (CAM_TID_INVALID);
9803
9804 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9805 return (CAM_LUN_INVALID);
9806
9807 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9808 *lstate = NULL;
9809 if (*tstate != NULL)
9810 *lstate =
9811 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9812 }
9813
9814 if (notfound_failure != 0 && *lstate == NULL)
9815 return (CAM_PATH_INVALID);
9816
9817 return (CAM_REQ_CMP);
9818 }
9819
9820 void
9821 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9822 {
9823 #if NOT_YET
9824 struct ahd_tmode_tstate *tstate;
9825 struct ahd_tmode_lstate *lstate;
9826 struct ccb_en_lun *cel;
9827 cam_status status;
9828 u_int target;
9829 u_int lun;
9830 u_int target_mask;
9831 u_long s;
9832 char channel;
9833
9834 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9835 /*notfound_failure*/FALSE);
9836
9837 if (status != CAM_REQ_CMP) {
9838 ccb->ccb_h.status = status;
9839 return;
9840 }
9841
9842 if ((ahd->features & AHD_MULTIROLE) != 0) {
9843 u_int our_id;
9844
9845 our_id = ahd->our_id;
9846 if (ccb->ccb_h.target_id != our_id) {
9847 if ((ahd->features & AHD_MULTI_TID) != 0
9848 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9849 /*
9850 * Only allow additional targets if
9851 * the initiator role is disabled.
9852 * The hardware cannot handle a re-select-in
9853 * on the initiator id during a re-select-out
9854 * on a different target id.
9855 */
9856 status = CAM_TID_INVALID;
9857 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9858 || ahd->enabled_luns > 0) {
9859 /*
9860 * Only allow our target id to change
9861 * if the initiator role is not configured
9862 * and there are no enabled luns which
9863 * are attached to the currently registered
9864 * scsi id.
9865 */
9866 status = CAM_TID_INVALID;
9867 }
9868 }
9869 }
9870
9871 if (status != CAM_REQ_CMP) {
9872 ccb->ccb_h.status = status;
9873 return;
9874 }
9875
9876 /*
9877 * We now have an id that is valid.
9878 * If we aren't in target mode, switch modes.
9879 */
9880 if ((ahd->flags & AHD_TARGETROLE) == 0
9881 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9882 u_long s;
9883
9884 kprintf("Configuring Target Mode\n");
9885 ahd_lock();
9886 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9887 ccb->ccb_h.status = CAM_BUSY;
9888 ahd_unlock();
9889 return;
9890 }
9891 ahd->flags |= AHD_TARGETROLE;
9892 if ((ahd->features & AHD_MULTIROLE) == 0)
9893 ahd->flags &= ~AHD_INITIATORROLE;
9894 ahd_pause(ahd);
9895 ahd_loadseq(ahd);
9896 ahd_restart(ahd);
9897 ahd_unlock();
9898 }
9899 cel = &ccb->cel;
9900 target = ccb->ccb_h.target_id;
9901 lun = ccb->ccb_h.target_lun;
9902 channel = SIM_CHANNEL(ahd, sim);
9903 target_mask = 0x01 << target;
9904 if (channel == 'B')
9905 target_mask <<= 8;
9906
9907 if (cel->enable != 0) {
9908 u_int scsiseq1;
9909
9910 /* Are we already enabled?? */
9911 if (lstate != NULL) {
9912 xpt_print_path(ccb->ccb_h.path);
9913 kprintf("Lun already enabled\n");
9914 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9915 return;
9916 }
9917
9918 if (cel->grp6_len != 0
9919 || cel->grp7_len != 0) {
9920 /*
9921 * Don't (yet?) support vendor
9922 * specific commands.
9923 */
9924 ccb->ccb_h.status = CAM_REQ_INVALID;
9925 kprintf("Non-zero Group Codes\n");
9926 return;
9927 }
9928
9929 /*
9930 * Seems to be okay.
9931 * Setup our data structures.
9932 */
9933 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9934 tstate = ahd_alloc_tstate(ahd, target, channel);
9935 if (tstate == NULL) {
9936 xpt_print_path(ccb->ccb_h.path);
9937 kprintf("Couldn't allocate tstate\n");
9938 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9939 return;
9940 }
9941 }
9942 lstate = kmalloc(sizeof(*lstate), M_DEVBUF, M_INTWAIT | M_ZERO);
9943 status = xpt_create_path(&lstate->path, /*periph*/NULL,
9944 xpt_path_path_id(ccb->ccb_h.path),
9945 xpt_path_target_id(ccb->ccb_h.path),
9946 xpt_path_lun_id(ccb->ccb_h.path));
9947 if (status != CAM_REQ_CMP) {
9948 kfree(lstate, M_DEVBUF);
9949 xpt_print_path(ccb->ccb_h.path);
9950 kprintf("Couldn't allocate path\n");
9951 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9952 return;
9953 }
9954 SLIST_INIT(&lstate->accept_tios);
9955 SLIST_INIT(&lstate->immed_notifies);
9956 ahd_lock();
9957 ahd_pause(ahd);
9958 if (target != CAM_TARGET_WILDCARD) {
9959 tstate->enabled_luns[lun] = lstate;
9960 ahd->enabled_luns++;
9961
9962 if ((ahd->features & AHD_MULTI_TID) != 0) {
9963 u_int targid_mask;
9964
9965 targid_mask = ahd_inw(ahd, TARGID);
9966 targid_mask |= target_mask;
9967 ahd_outw(ahd, TARGID, targid_mask);
9968 ahd_update_scsiid(ahd, targid_mask);
9969 } else {
9970 u_int our_id;
9971 char channel;
9972
9973 channel = SIM_CHANNEL(ahd, sim);
9974 our_id = SIM_SCSI_ID(ahd, sim);
9975
9976 /*
9977 * This can only happen if selections
9978 * are not enabled
9979 */
9980 if (target != our_id) {
9981 u_int sblkctl;
9982 char cur_channel;
9983 int swap;
9984
9985 sblkctl = ahd_inb(ahd, SBLKCTL);
9986 cur_channel = (sblkctl & SELBUSB)
9987 ? 'B' : 'A';
9988 if ((ahd->features & AHD_TWIN) == 0)
9989 cur_channel = 'A';
9990 swap = cur_channel != channel;
9991 ahd->our_id = target;
9992
9993 if (swap)
9994 ahd_outb(ahd, SBLKCTL,
9995 sblkctl ^ SELBUSB);
9996
9997 ahd_outb(ahd, SCSIID, target);
9998
9999 if (swap)
10000 ahd_outb(ahd, SBLKCTL, sblkctl);
10001 }
10002 }
10003 } else
10004 ahd->black_hole = lstate;
10005 /* Allow select-in operations */
10006 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
10007 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10008 scsiseq1 |= ENSELI;
10009 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10010 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10011 scsiseq1 |= ENSELI;
10012 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10013 }
10014 ahd_unpause(ahd);
10015 ahd_unlock();
10016 ccb->ccb_h.status = CAM_REQ_CMP;
10017 xpt_print_path(ccb->ccb_h.path);
10018 kprintf("Lun now enabled for target mode\n");
10019 } else {
10020 struct scb *scb;
10021 int i, empty;
10022
10023 if (lstate == NULL) {
10024 ccb->ccb_h.status = CAM_LUN_INVALID;
10025 return;
10026 }
10027
10028 ahd_lock();
10029
10030 ccb->ccb_h.status = CAM_REQ_CMP;
10031 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
10032 struct ccb_hdr *ccbh;
10033
10034 ccbh = &scb->io_ctx->ccb_h;
10035 if (ccbh->func_code == XPT_CONT_TARGET_IO
10036 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
10037 kprintf("CTIO pending\n");
10038 ccb->ccb_h.status = CAM_REQ_INVALID;
10039 ahd_unlock();
10040 return;
10041 }
10042 }
10043
10044 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
10045 kprintf("ATIOs pending\n");
10046 ccb->ccb_h.status = CAM_REQ_INVALID;
10047 }
10048
10049 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
10050 kprintf("INOTs pending\n");
10051 ccb->ccb_h.status = CAM_REQ_INVALID;
10052 }
10053
10054 if (ccb->ccb_h.status != CAM_REQ_CMP) {
10055 ahd_unlock();
10056 return;
10057 }
10058
10059 xpt_print_path(ccb->ccb_h.path);
10060 kprintf("Target mode disabled\n");
10061 xpt_free_path(lstate->path);
10062 kfree(lstate, M_DEVBUF);
10063
10064 ahd_pause(ahd);
10065 /* Can we clean up the target too? */
10066 if (target != CAM_TARGET_WILDCARD) {
10067 tstate->enabled_luns[lun] = NULL;
10068 ahd->enabled_luns--;
10069 for (empty = 1, i = 0; i < 8; i++)
10070 if (tstate->enabled_luns[i] != NULL) {
10071 empty = 0;
10072 break;
10073 }
10074
10075 if (empty) {
10076 ahd_free_tstate(ahd, target, channel,
10077 /*force*/FALSE);
10078 if (ahd->features & AHD_MULTI_TID) {
10079 u_int targid_mask;
10080
10081 targid_mask = ahd_inw(ahd, TARGID);
10082 targid_mask &= ~target_mask;
10083 ahd_outw(ahd, TARGID, targid_mask);
10084 ahd_update_scsiid(ahd, targid_mask);
10085 }
10086 }
10087 } else {
10088
10089 ahd->black_hole = NULL;
10090
10091 /*
10092 * We can't allow selections without
10093 * our black hole device.
10094 */
10095 empty = TRUE;
10096 }
10097 if (ahd->enabled_luns == 0) {
10098 /* Disallow select-in */
10099 u_int scsiseq1;
10100
10101 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10102 scsiseq1 &= ~ENSELI;
10103 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10104 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10105 scsiseq1 &= ~ENSELI;
10106 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10107
10108 if ((ahd->features & AHD_MULTIROLE) == 0) {
10109 kprintf("Configuring Initiator Mode\n");
10110 ahd->flags &= ~AHD_TARGETROLE;
10111 ahd->flags |= AHD_INITIATORROLE;
10112 ahd_pause(ahd);
10113 ahd_loadseq(ahd);
10114 ahd_restart(ahd);
10115 /*
10116 * Unpaused. The extra unpause
10117 * that follows is harmless.
10118 */
10119 }
10120 }
10121 ahd_unpause(ahd);
10122 ahd_unlock();
10123 }
10124 #endif
10125 }
10126
10127 static void
10128 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
10129 {
10130 #if NOT_YET
10131 u_int scsiid_mask;
10132 u_int scsiid;
10133
10134 if ((ahd->features & AHD_MULTI_TID) == 0)
10135 panic("ahd_update_scsiid called on non-multitid unit\n");
10136
10137 /*
10138 * Since we will rely on the TARGID mask
10139 * for selection enables, ensure that OID
10140 * in SCSIID is not set to some other ID
10141 * that we don't want to allow selections on.
10142 */
10143 if ((ahd->features & AHD_ULTRA2) != 0)
10144 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
10145 else
10146 scsiid = ahd_inb(ahd, SCSIID);
10147 scsiid_mask = 0x1 << (scsiid & OID);
10148 if ((targid_mask & scsiid_mask) == 0) {
10149 u_int our_id;
10150
10151 /* ffs counts from 1 */
10152 our_id = ffs(targid_mask);
10153 if (our_id == 0)
10154 our_id = ahd->our_id;
10155 else
10156 our_id--;
10157 scsiid &= TID;
10158 scsiid |= our_id;
10159 }
10160 if ((ahd->features & AHD_ULTRA2) != 0)
10161 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
10162 else
10163 ahd_outb(ahd, SCSIID, scsiid);
10164 #endif
10165 }
10166
10167 void
10168 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
10169 {
10170 struct target_cmd *cmd;
10171
10172 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
10173 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
10174
10175 /*
10176 * Only advance through the queue if we
10177 * have the resources to process the command.
10178 */
10179 if (ahd_handle_target_cmd(ahd, cmd) != 0)
10180 break;
10181
10182 cmd->cmd_valid = 0;
10183 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
10184 ahd->shared_data_dmamap,
10185 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
10186 sizeof(struct target_cmd),
10187 BUS_DMASYNC_PREREAD);
10188 ahd->tqinfifonext++;
10189
10190 /*
10191 * Lazily update our position in the target mode incoming
10192 * command queue as seen by the sequencer.
10193 */
10194 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
10195 u_int hs_mailbox;
10196
10197 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
10198 hs_mailbox &= ~HOST_TQINPOS;
10199 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
10200 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
10201 }
10202 }
10203 }
10204
10205 static int
10206 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
10207 {
10208 struct ahd_tmode_tstate *tstate;
10209 struct ahd_tmode_lstate *lstate;
10210 struct ccb_accept_tio *atio;
10211 uint8_t *byte;
10212 int initiator;
10213 int target;
10214 int lun;
10215
10216 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
10217 target = SCSIID_OUR_ID(cmd->scsiid);
10218 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
10219
10220 byte = cmd->bytes;
10221 tstate = ahd->enabled_targets[target];
10222 lstate = NULL;
10223 if (tstate != NULL)
10224 lstate = tstate->enabled_luns[lun];
10225
10226 /*
10227 * Commands for disabled luns go to the black hole driver.
10228 */
10229 if (lstate == NULL)
10230 lstate = ahd->black_hole;
10231
10232 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
10233 if (atio == NULL) {
10234 ahd->flags |= AHD_TQINFIFO_BLOCKED;
10235 /*
10236 * Wait for more ATIOs from the peripheral driver for this lun.
10237 */
10238 return (1);
10239 } else
10240 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
10241 #ifdef AHD_DEBUG
10242 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10243 kprintf("Incoming command from %d for %d:%d%s\n",
10244 initiator, target, lun,
10245 lstate == ahd->black_hole ? "(Black Holed)" : "");
10246 #endif
10247 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
10248
10249 if (lstate == ahd->black_hole) {
10250 /* Fill in the wildcards */
10251 atio->ccb_h.target_id = target;
10252 atio->ccb_h.target_lun = lun;
10253 }
10254
10255 /*
10256 * Package it up and send it off to
10257 * whomever has this lun enabled.
10258 */
10259 atio->sense_len = 0;
10260 atio->init_id = initiator;
10261 if (byte[0] != 0xFF) {
10262 /* Tag was included */
10263 atio->tag_action = *byte++;
10264 atio->tag_id = *byte++;
10265 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
10266 } else {
10267 atio->ccb_h.flags = 0;
10268 }
10269 byte++;
10270
10271 /* Okay. Now determine the cdb size based on the command code */
10272 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
10273 case 0:
10274 atio->cdb_len = 6;
10275 break;
10276 case 1:
10277 case 2:
10278 atio->cdb_len = 10;
10279 break;
10280 case 4:
10281 atio->cdb_len = 16;
10282 break;
10283 case 5:
10284 atio->cdb_len = 12;
10285 break;
10286 case 3:
10287 default:
10288 /* Only copy the opcode. */
10289 atio->cdb_len = 1;
10290 kprintf("Reserved or VU command code type encountered\n");
10291 break;
10292 }
10293
10294 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
10295
10296 atio->ccb_h.status |= CAM_CDB_RECVD;
10297
10298 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
10299 /*
10300 * We weren't allowed to disconnect.
10301 * We're hanging on the bus until a
10302 * continue target I/O comes in response
10303 * to this accept tio.
10304 */
10305 #ifdef AHD_DEBUG
10306 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10307 kprintf("Received Immediate Command %d:%d:%d - %p\n",
10308 initiator, target, lun, ahd->pending_device);
10309 #endif
10310 ahd->pending_device = lstate;
10311 ahd_freeze_ccb((union ccb *)atio);
10312 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
10313 }
10314 xpt_done((union ccb*)atio);
10315 return (0);
10316 }
10317
10318 #endif
A repo for keeping AMD64 port code before merging with the master