2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vrreg.h,v 1.7.2.5 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vrreg.h,v 1.7 2005/06/20 13:01:15 joerg Exp $
37 * Rhine register definitions.
40 #define VR_PAR0 0x00 /* node address 0 to 4 */
41 #define VR_PAR1 0x04 /* node address 2 to 6 */
42 #define VR_RXCFG 0x06 /* receiver config register */
43 #define VR_TXCFG 0x07 /* transmit config register */
44 #define VR_COMMAND 0x08 /* command register */
45 #define VR_ISR 0x0C /* interrupt/status register */
46 #define VR_IMR 0x0E /* interrupt mask register */
47 #define VR_MAR0 0x10 /* multicast hash 0 */
48 #define VR_MAR1 0x14 /* multicast hash 1 */
49 #define VR_RXADDR 0x18 /* rx descriptor list start addr */
50 #define VR_TXADDR 0x1C /* tx descriptor list start addr */
51 #define VR_CURRXDESC0 0x20
52 #define VR_CURRXDESC1 0x24
53 #define VR_CURRXDESC2 0x28
54 #define VR_CURRXDESC3 0x2C
55 #define VR_NEXTRXDESC0 0x30
56 #define VR_NEXTRXDESC1 0x34
57 #define VR_NEXTRXDESC2 0x38
58 #define VR_NEXTRXDESC3 0x3C
59 #define VR_CURTXDESC0 0x40
60 #define VR_CURTXDESC1 0x44
61 #define VR_CURTXDESC2 0x48
62 #define VR_CURTXDESC3 0x4C
63 #define VR_NEXTTXDESC0 0x50
64 #define VR_NEXTTXDESC1 0x54
65 #define VR_NEXTTXDESC2 0x58
66 #define VR_NEXTTXDESC3 0x5C
67 #define VR_CURRXDMA 0x60 /* current RX DMA address */
68 #define VR_CURTXDMA 0x64 /* current TX DMA address */
69 #define VR_TALLYCNT 0x68 /* tally counter test register */
70 #define VR_PHYADDR 0x6C
71 #define VR_MIISTAT 0x6D
74 #define VR_MIICMD 0x70
75 #define VR_MIIADDR 0x71
76 #define VR_MIIDATA 0x72
80 #define VR_CONFIG 0x78
81 #define VR_MPA_CNT 0x7C
82 #define VR_CRC_CNT 0x7E
83 #define VR_STICKHW 0x83
86 #define VR_MISC_CR1 0x81
87 #define VR_MISCCR1_FORSRST 0x40
92 #define VR_RXCFG_RX_ERRPKTS 0x01
93 #define VR_RXCFG_RX_RUNT 0x02
94 #define VR_RXCFG_RX_MULTI 0x04
95 #define VR_RXCFG_RX_BROAD 0x08
96 #define VR_RXCFG_RX_PROMISC 0x10
97 #define VR_RXCFG_RX_THRESH 0xE0
99 #define VR_RXTHRESH_32BYTES 0x00
100 #define VR_RXTHRESH_64BYTES 0x20
101 #define VR_RXTHRESH_128BYTES 0x40
102 #define VR_RXTHRESH_256BYTES 0x60
103 #define VR_RXTHRESH_512BYTES 0x80
104 #define VR_RXTHRESH_768BYTES 0xA0
105 #define VR_RXTHRESH_1024BYTES 0xC0
106 #define VR_RXTHRESH_STORENFWD 0xE0
111 #define VR_TXCFG_RSVD0 0x01
112 #define VR_TXCFG_LOOPBKMODE 0x06
113 #define VR_TXCFG_BACKOFF 0x08
114 #define VR_TXCFG_RSVD1 0x10
115 #define VR_TXCFG_TX_THRESH 0xE0
117 #define VR_TXTHRESH_32BYTES 0x00
118 #define VR_TXTHRESH_64BYTES 0x20
119 #define VR_TXTHRESH_128BYTES 0x40
120 #define VR_TXTHRESH_256BYTES 0x60
121 #define VR_TXTHRESH_512BYTES 0x80
122 #define VR_TXTHRESH_768BYTES 0xA0
123 #define VR_TXTHRESH_1024BYTES 0xC0
124 #define VR_TXTHRESH_STORENFWD 0xE0
127 * Command register bits.
129 #define VR_CMD_INIT 0x0001
130 #define VR_CMD_START 0x0002
131 #define VR_CMD_STOP 0x0004
132 #define VR_CMD_RX_ON 0x0008
133 #define VR_CMD_TX_ON 0x0010
134 #define VR_CMD_TX_GO 0x0020
135 #define VR_CMD_RX_GO 0x0040
136 #define VR_CMD_RSVD 0x0080
137 #define VR_CMD_RX_EARLY 0x0100
138 #define VR_CMD_TX_EARLY 0x0200
139 #define VR_CMD_FULLDUPLEX 0x0400
140 #define VR_CMD_TX_NOPOLL 0x0800
142 #define VR_CMD_RESET 0x8000
145 * Interrupt status bits.
147 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */
148 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */
149 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */
150 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
151 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
152 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */
153 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */
154 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */
155 #define VR_ISR_RX_EARLY 0x0100 /* rx early */
156 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */
157 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */
158 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (3065) */
159 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */
160 #define VR_ISR_RX_DROPPED 0x0800
161 #define VR_ISR_RX_NOBUF2 0x1000
162 #define VR_ISR_TX_ABRT2 0x2000
163 #define VR_ISR_LINKSTAT2 0x4000
164 #define VR_ISR_MAGICPACKET 0x8000
167 * Interrupt mask bits.
169 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */
170 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */
171 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */
172 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */
173 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */
174 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */
175 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */
176 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */
177 #define VR_IMR_RX_EARLY 0x0100 /* rx early */
178 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */
179 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */
180 #define VR_IMR_RX_DROPPED 0x0800
181 #define VR_IMR_RX_NOBUF2 0x1000
182 #define VR_IMR_TX_ABRT2 0x2000
183 #define VR_IMR_LINKSTAT2 0x4000
184 #define VR_IMR_MAGICPACKET 0x8000
187 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \
188 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \
189 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED)
192 * MII status register.
195 #define VR_MIISTAT_SPEED 0x01
196 #define VR_MIISTAT_LINKFAULT 0x02
197 #define VR_MIISTAT_MGTREADERR 0x04
198 #define VR_MIISTAT_MIIERR 0x08
199 #define VR_MIISTAT_PHYOPT 0x10
200 #define VR_MIISTAT_MDC_SPEED 0x20
201 #define VR_MIISTAT_RSVD 0x40
202 #define VR_MIISTAT_GPIO1POLL 0x80
205 * MII command register bits.
207 #define VR_MIICMD_CLK 0x01
208 #define VR_MIICMD_DATAOUT 0x02
209 #define VR_MIICMD_DATAIN 0x04
210 #define VR_MIICMD_DIR 0x08
211 #define VR_MIICMD_DIRECTPGM 0x10
212 #define VR_MIICMD_WRITE_ENB 0x20
213 #define VR_MIICMD_READ_ENB 0x40
214 #define VR_MIICMD_AUTOPOLL 0x80
217 * EEPROM control bits.
219 #define VR_EECSR_DATAIN 0x01 /* data out */
220 #define VR_EECSR_DATAOUT 0x02 /* data in */
221 #define VR_EECSR_CLK 0x04 /* clock */
222 #define VR_EECSR_CS 0x08 /* chip select */
223 #define VR_EECSR_DPM 0x10
224 #define VR_EECSR_LOAD 0x20
225 #define VR_EECSR_EMBP 0x40
226 #define VR_EECSR_EEPR 0x80
228 #define VR_EECMD_WRITE 0x140
229 #define VR_EECMD_READ 0x180
230 #define VR_EECMD_ERASE 0x1c0
233 * Test register bits.
235 #define VR_TEST_TEST0 0x01
236 #define VR_TEST_TEST1 0x02
237 #define VR_TEST_TEST2 0x04
238 #define VR_TEST_TSTUD 0x08
239 #define VR_TEST_TSTOV 0x10
240 #define VR_TEST_BKOFF 0x20
241 #define VR_TEST_FCOL 0x40
242 #define VR_TEST_HBDES 0x80
245 * Config register bits.
247 #define VR_CFG_GPIO2OUTENB 0x00000001
248 #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */
249 #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */
250 #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */
251 #define VR_CFG_MIIOPT 0x00000010
252 #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */
253 #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */
254 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */
255 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */
256 #define VR_CFG_MRREADWAIT 0x00000200
257 #define VR_CFG_MRWRITEWAIT 0x00000400
258 #define VR_CFG_RX_ARB 0x00000800
259 #define VR_CFG_TX_ARB 0x00001000
260 #define VR_CFG_READMULTI 0x00002000
261 #define VR_CFG_TX_PACE 0x00004000
262 #define VR_CFG_TX_QDIS 0x00008000
263 #define VR_CFG_ROMSEL0 0x00010000
264 #define VR_CFG_ROMSEL1 0x00020000
265 #define VR_CFG_ROMSEL2 0x00040000
266 #define VR_CFG_ROMTIMESEL 0x00080000
267 #define VR_CFG_RSVD0 0x00100000
268 #define VR_CFG_ROMDLY 0x00200000
269 #define VR_CFG_ROMOPT 0x00400000
270 #define VR_CFG_RSVD1 0x00800000
271 #define VR_CFG_BACKOFFOPT 0x01000000
272 #define VR_CFG_BACKOFFMOD 0x02000000
273 #define VR_CFG_CAPEFFECT 0x04000000
274 #define VR_CFG_BACKOFFRAND 0x08000000
275 #define VR_CFG_MAGICKPACKET 0x10000000
276 #define VR_CFG_PCIREADLINE 0x20000000
277 #define VR_CFG_DIAG 0x40000000
278 #define VR_CFG_GPIOEN 0x80000000
281 #define VR_STICKHW_DS0 0x01
282 #define VR_STICKHW_DS1 0x02
283 #define VR_STICKHW_WOL_ENB 0x04
284 #define VR_STICKHW_WOL_STS 0x08
285 #define VR_STICKHW_LEGWOL_ENB 0x80
288 * BCR0 register bits. (At least for the VT6102 chip.)
290 #define VR_BCR0_DMA_LENGTH 0x07
292 #define VR_BCR0_DMA_32BYTES 0x00
293 #define VR_BCR0_DMA_64BYTES 0x01
294 #define VR_BCR0_DMA_128BYTES 0x02
295 #define VR_BCR0_DMA_256BYTES 0x03
296 #define VR_BCR0_DMA_512BYTES 0x04
297 #define VR_BCR0_DMA_1024BYTES 0x05
298 #define VR_BCR0_DMA_STORENFWD 0x07
300 #define VR_BCR0_RX_THRESH 0x38
302 #define VR_BCR0_RXTHRESHCFG 0x00
303 #define VR_BCR0_RXTHRESH64BYTES 0x08
304 #define VR_BCR0_RXTHRESH128BYTES 0x10
305 #define VR_BCR0_RXTHRESH256BYTES 0x18
306 #define VR_BCR0_RXTHRESH512BYTES 0x20
307 #define VR_BCR0_RXTHRESH1024BYTES 0x28
308 #define VR_BCR0_RXTHRESHSTORENFWD 0x38
309 #define VR_BCR0_EXTLED 0x40
310 #define VR_BCR0_MED2 0x80
313 * BCR1 register bits. (At least for the VT6102 chip.)
315 #define VR_BCR1_POT0 0x01
316 #define VR_BCR1_POT1 0x02
317 #define VR_BCR1_POT2 0x04
318 #define VR_BCR1_TX_THRESH 0x38
319 #define VR_BCR1_TXTHRESHCFG 0x00
320 #define VR_BCR1_TXTHRESH64BYTES 0x08
321 #define VR_BCR1_TXTHRESH128BYTES 0x10
322 #define VR_BCR1_TXTHRESH256BYTES 0x18
323 #define VR_BCR1_TXTHRESH512BYTES 0x20
324 #define VR_BCR1_TXTHRESH1024BYTES 0x28
325 #define VR_BCR1_TXTHRESHSTORENFWD 0x38
328 * Rhine TX/RX list structure.
338 #define vr_data vr_ptr1
339 #define vr_next vr_ptr2
342 #define VR_RXSTAT_RXERR 0x00000001
343 #define VR_RXSTAT_CRCERR 0x00000002
344 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004
345 #define VR_RXSTAT_FIFOOFLOW 0x00000008
346 #define VR_RXSTAT_GIANT 0x00000010
347 #define VR_RXSTAT_RUNT 0x00000020
348 #define VR_RXSTAT_BUSERR 0x00000040
349 #define VR_RXSTAT_BUFFERR 0x00000080
350 #define VR_RXSTAT_LASTFRAG 0x00000100
351 #define VR_RXSTAT_FIRSTFRAG 0x00000200
352 #define VR_RXSTAT_RLINK 0x00000400
353 #define VR_RXSTAT_RX_PHYS 0x00000800
354 #define VR_RXSTAT_RX_BROAD 0x00001000
355 #define VR_RXSTAT_RX_MULTI 0x00002000
356 #define VR_RXSTAT_RX_OK 0x00004000
357 #define VR_RXSTAT_RXLEN 0x07FF0000
358 #define VR_RXSTAT_RXLEN_EXT 0x78000000
359 #define VR_RXSTAT_OWN 0x80000000
361 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16)
362 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN)
364 #define VR_RXCTL_BUFLEN 0x000007FF
365 #define VR_RXCTL_BUFLEN_EXT 0x00007800
366 #define VR_RXCTL_CHAIN 0x00008000
367 #define VR_RXCTL_RX_INTR 0x00800000
369 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR)
371 #define VR_TXSTAT_DEFER 0x00000001
372 #define VR_TXSTAT_UNDERRUN 0x00000002
373 #define VR_TXSTAT_COLLCNT 0x00000078
374 #define VR_TXSTAT_SQE 0x00000080
375 #define VR_TXSTAT_ABRT 0x00000100
376 #define VR_TXSTAT_LATECOLL 0x00000200
377 #define VR_TXSTAT_CARRLOST 0x00000400
378 #define VR_TXSTAT_UDF 0x00000800
379 #define VR_TXSTAT_BUSERR 0x00002000
380 #define VR_TXSTAT_JABTIMEO 0x00004000
381 #define VR_TXSTAT_ERRSUM 0x00008000
382 #define VR_TXSTAT_OWN 0x80000000
384 #define VR_TXCTL_BUFLEN 0x000007FF
385 #define VR_TXCTL_BUFLEN_EXT 0x00007800
386 #define VR_TXCTL_TLINK 0x00008000
387 #define VR_TXCTL_FIRSTFRAG 0x00200000
388 #define VR_TXCTL_LASTFRAG 0x00400000
389 #define VR_TXCTL_FINT 0x00800000
392 #define VR_MAXFRAGS 16
393 #define VR_RX_LIST_CNT 64
394 #define VR_TX_LIST_CNT 128
395 #define VR_MIN_FRAMELEN 60
396 #define VR_FRAMELEN 1536
397 #define VR_RXLEN 1520
399 #define VR_TXOWN(x) x->vr_ptr->vr_status
401 struct vr_list_data
{
402 struct vr_desc vr_rx_list
[VR_RX_LIST_CNT
];
403 struct vr_desc vr_tx_list
[VR_TX_LIST_CNT
];
407 struct vr_desc
*vr_ptr
;
408 struct mbuf
*vr_mbuf
;
409 struct vr_chain
*vr_nextdesc
;
412 struct vr_chain_onefrag
{
413 struct vr_desc
*vr_ptr
;
414 struct mbuf
*vr_mbuf
;
415 struct vr_chain_onefrag
*vr_nextdesc
;
418 struct vr_chain_data
{
419 struct vr_chain_onefrag vr_rx_chain
[VR_RX_LIST_CNT
];
420 struct vr_chain vr_tx_chain
[VR_TX_LIST_CNT
];
422 struct vr_chain_onefrag
*vr_rx_head
;
424 struct vr_chain
*vr_tx_head
;
425 struct vr_chain
*vr_tx_tail
;
426 struct vr_chain
*vr_tx_free
;
435 struct vr_mii_frame
{
440 uint8_t mii_turnaround
;
447 #define VR_MII_STARTDELIM 0x01
448 #define VR_MII_READOP 0x02
449 #define VR_MII_WRITEOP 0x01
450 #define VR_MII_TURNAROUND 0x02
452 #define VR_FLAG_FORCEDELAY 1
453 #define VR_FLAG_SCHEDDELAY 2
454 #define VR_FLAG_DELAYTIMEO 3
457 struct arpcom arpcom
; /* interface info */
458 bus_space_handle_t vr_bhandle
; /* bus space handle */
459 bus_space_tag_t vr_btag
; /* bus space tag */
460 struct resource
*vr_res
;
461 struct resource
*vr_irq
;
464 uint8_t vr_revid
; /* Rhine chip revision */
465 uint8_t vr_flags
; /* See VR_F_* below */
466 struct vr_list_data
*vr_ldata
;
467 struct vr_chain_data vr_cdata
;
468 struct callout vr_stat_timer
;
472 #define VR_F_RESTART 0x01 /* Restart unit on next tick */
475 * register space access macros
477 #define CSR_WRITE_4(sc, reg, val) \
478 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val)
479 #define CSR_WRITE_2(sc, reg, val) \
480 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val)
481 #define CSR_WRITE_1(sc, reg, val) \
482 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val)
484 #define CSR_READ_4(sc, reg) \
485 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg)
486 #define CSR_READ_2(sc, reg) \
487 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg)
488 #define CSR_READ_1(sc, reg) \
489 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg)
491 #define VR_TIMEOUT 1000
492 #define ETHER_ALIGN 2
495 * General constants that are fun to know.
499 #define VIA_VENDORID 0x1106
502 * VIA Rhine device IDs.
504 #define VIA_DEVICEID_RHINE 0x3043
505 #define VIA_DEVICEID_RHINE_II 0x6100
506 #define VIA_DEVICEID_RHINE_II_2 0x3065
507 #define VIA_DEVICEID_RHINE_III 0x3106
508 #define VIA_DEVICEID_RHINE_III_M 0x3053
511 * Delta Electronics device ID.
513 #define DELTA_VENDORID 0x1500
518 #define DELTA_DEVICEID_RHINE_II 0x1320
523 #define ADDTRON_VENDORID 0x4033
526 * Addtron device IDs.
528 #define ADDTRON_DEVICEID_RHINE_II 0x1320
531 * VIA Rhine revision IDs
534 #define REV_ID_VT3043_E 0x04
535 #define REV_ID_VT3071_A 0x20
536 #define REV_ID_VT3071_B 0x21
537 #define REV_ID_VT3065_A 0x40
538 #define REV_ID_VT3065_B 0x41
539 #define REV_ID_VT3065_C 0x42
540 #define REV_ID_VT6102_APOLLO 0x74
541 #define REV_ID_VT3106 0x80
542 #define REV_ID_VT3106_J 0x80 /* 0x80-0x8F */
543 #define REV_ID_VT3106_S 0x90 /* 0x90-0xA0 */
546 * PCI low memory base and low I/O base register, and
547 * other PCI registers.
550 #define VR_PCI_VENDOR_ID 0x00
551 #define VR_PCI_DEVICE_ID 0x02
552 #define VR_PCI_COMMAND 0x04
553 #define VR_PCI_STATUS 0x06
554 #define VR_PCI_REVID 0x08
555 #define VR_PCI_CLASSCODE 0x09
556 #define VR_PCI_LATENCY_TIMER 0x0D
557 #define VR_PCI_HEADER_TYPE 0x0E
558 #define VR_PCI_LOIO 0x10
559 #define VR_PCI_LOMEM 0x14
560 #define VR_PCI_BIOSROM 0x30
561 #define VR_PCI_INTLINE 0x3C
562 #define VR_PCI_INTPIN 0x3D
563 #define VR_PCI_MINGNT 0x3E
564 #define VR_PCI_MINLAT 0x0F
565 #define VR_PCI_RESETOPT 0x48
566 #define VR_PCI_EEPROM_DATA 0x4C
567 #define VR_PCI_MODE 0x50
569 #define VR_MODE3_MIION 0x04
571 /* power management registers */
572 #define VR_PCI_CAPID 0xDC /* 8 bits */
573 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */
574 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */
575 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
577 #define VR_PSTATE_MASK 0x0003
578 #define VR_PSTATE_D0 0x0000
579 #define VR_PSTATE_D1 0x0002
580 #define VR_PSTATE_D2 0x0002
581 #define VR_PSTATE_D3 0x0003
582 #define VR_PME_EN 0x0010
583 #define VR_PME_STATUS 0x8000