2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_vr.c,v 1.26.2.13 2003/02/06 04:46:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/vr/if_vr.c,v 1.28 2005/06/20 13:01:15 joerg Exp $
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * The Rhine has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/thread2.h>
73 #include <net/ifq_var.h>
74 #include <net/if_arp.h>
75 #include <net/ethernet.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
81 #include <vm/vm.h> /* for vtophys */
82 #include <vm/pmap.h> /* for vtophys */
83 #include <machine/bus_pio.h>
84 #include <machine/bus_memio.h>
85 #include <machine/bus.h>
86 #include <machine/resource.h>
90 #include <dev/netif/mii_layer/mii.h>
91 #include <dev/netif/mii_layer/miivar.h>
93 #include <bus/pci/pcireg.h>
94 #include <bus/pci/pcivar.h>
98 #include <dev/netif/vr/if_vrreg.h>
100 /* "controller miibus0" required. See GENERIC if you get errors here. */
101 #include "miibus_if.h"
106 * Various supported device vendors/types and their names.
108 static struct vr_type vr_devs
[] = {
109 { VIA_VENDORID
, VIA_DEVICEID_RHINE
,
110 "VIA VT3043 Rhine I 10/100BaseTX" },
111 { VIA_VENDORID
, VIA_DEVICEID_RHINE_II
,
112 "VIA VT86C100A Rhine II 10/100BaseTX" },
113 { VIA_VENDORID
, VIA_DEVICEID_RHINE_II_2
,
114 "VIA VT6102 Rhine II 10/100BaseTX" },
115 { VIA_VENDORID
, VIA_DEVICEID_RHINE_III
,
116 "VIA VT6105 Rhine III 10/100BaseTX" },
117 { VIA_VENDORID
, VIA_DEVICEID_RHINE_III_M
,
118 "VIA VT6105M Rhine III 10/100BaseTX" },
119 { DELTA_VENDORID
, DELTA_DEVICEID_RHINE_II
,
120 "Delta Electronics Rhine II 10/100BaseTX" },
121 { ADDTRON_VENDORID
, ADDTRON_DEVICEID_RHINE_II
,
122 "Addtron Technology Rhine II 10/100BaseTX" },
126 static int vr_probe(device_t
);
127 static int vr_attach(device_t
);
128 static int vr_detach(device_t
);
130 static int vr_newbuf(struct vr_softc
*, struct vr_chain_onefrag
*,
132 static int vr_encap(struct vr_softc
*, struct vr_chain
*, struct mbuf
* );
134 static void vr_rxeof(struct vr_softc
*);
135 static void vr_rxeoc(struct vr_softc
*);
136 static void vr_txeof(struct vr_softc
*);
137 static void vr_txeoc(struct vr_softc
*);
138 static void vr_tick(void *);
139 static void vr_intr(void *);
140 static void vr_start(struct ifnet
*);
141 static int vr_ioctl(struct ifnet
*, u_long
, caddr_t
, struct ucred
*);
142 static void vr_init(void *);
143 static void vr_stop(struct vr_softc
*);
144 static void vr_watchdog(struct ifnet
*);
145 static void vr_shutdown(device_t
);
146 static int vr_ifmedia_upd(struct ifnet
*);
147 static void vr_ifmedia_sts(struct ifnet
*, struct ifmediareq
*);
150 static void vr_mii_sync(struct vr_softc
*);
151 static void vr_mii_send(struct vr_softc
*, uint32_t, int);
153 static int vr_mii_readreg(struct vr_softc
*, struct vr_mii_frame
*);
154 static int vr_mii_writereg(struct vr_softc
*, struct vr_mii_frame
*);
155 static int vr_miibus_readreg(device_t
, int, int);
156 static int vr_miibus_writereg(device_t
, int, int, int);
157 static void vr_miibus_statchg(device_t
);
159 static void vr_setcfg(struct vr_softc
*, int);
160 static uint8_t vr_calchash(uint8_t *);
161 static void vr_setmulti(struct vr_softc
*);
162 static void vr_reset(struct vr_softc
*);
163 static int vr_list_rx_init(struct vr_softc
*);
164 static int vr_list_tx_init(struct vr_softc
*);
165 #ifdef DEVICE_POLLING
166 static void vr_poll(struct ifnet
*ifp
, enum poll_cmd cmd
, int count
);
170 #define VR_RES SYS_RES_IOPORT
171 #define VR_RID VR_PCI_LOIO
173 #define VR_RES SYS_RES_MEMORY
174 #define VR_RID VR_PCI_LOMEM
177 static device_method_t vr_methods
[] = {
178 /* Device interface */
179 DEVMETHOD(device_probe
, vr_probe
),
180 DEVMETHOD(device_attach
, vr_attach
),
181 DEVMETHOD(device_detach
, vr_detach
),
182 DEVMETHOD(device_shutdown
, vr_shutdown
),
185 DEVMETHOD(bus_print_child
, bus_generic_print_child
),
186 DEVMETHOD(bus_driver_added
, bus_generic_driver_added
),
189 DEVMETHOD(miibus_readreg
, vr_miibus_readreg
),
190 DEVMETHOD(miibus_writereg
, vr_miibus_writereg
),
191 DEVMETHOD(miibus_statchg
, vr_miibus_statchg
),
196 static driver_t vr_driver
= {
199 sizeof(struct vr_softc
)
202 static devclass_t vr_devclass
;
204 DECLARE_DUMMY_MODULE(if_vr
);
205 DRIVER_MODULE(if_vr
, pci
, vr_driver
, vr_devclass
, 0, 0);
206 DRIVER_MODULE(miibus
, vr
, miibus_driver
, miibus_devclass
, 0, 0);
208 #define VR_SETBIT(sc, reg, x) \
209 CSR_WRITE_1(sc, reg, \
210 CSR_READ_1(sc, reg) | (x))
212 #define VR_CLRBIT(sc, reg, x) \
213 CSR_WRITE_1(sc, reg, \
214 CSR_READ_1(sc, reg) & ~(x))
216 #define VR_SETBIT16(sc, reg, x) \
217 CSR_WRITE_2(sc, reg, \
218 CSR_READ_2(sc, reg) | (x))
220 #define VR_CLRBIT16(sc, reg, x) \
221 CSR_WRITE_2(sc, reg, \
222 CSR_READ_2(sc, reg) & ~(x))
224 #define VR_SETBIT32(sc, reg, x) \
225 CSR_WRITE_4(sc, reg, \
226 CSR_READ_4(sc, reg) | (x))
228 #define VR_CLRBIT32(sc, reg, x) \
229 CSR_WRITE_4(sc, reg, \
230 CSR_READ_4(sc, reg) & ~(x))
233 CSR_WRITE_1(sc, VR_MIICMD, \
234 CSR_READ_1(sc, VR_MIICMD) | (x))
237 CSR_WRITE_1(sc, VR_MIICMD, \
238 CSR_READ_1(sc, VR_MIICMD) & ~(x))
242 * Sync the PHYs by setting data bit and strobing the clock 32 times.
245 vr_mii_sync(struct vr_softc
*sc
)
249 SIO_SET(VR_MIICMD_DIR
|VR_MIICMD_DATAIN
);
251 for (i
= 0; i
< 32; i
++) {
252 SIO_SET(VR_MIICMD_CLK
);
254 SIO_CLR(VR_MIICMD_CLK
);
260 * Clock a series of bits through the MII.
263 vr_mii_send(struct vr_softc
*sc
, uint32_t bits
, int cnt
)
267 SIO_CLR(VR_MIICMD_CLK
);
269 for (i
= (0x1 << (cnt
- 1)); i
; i
>>= 1) {
271 SIO_SET(VR_MIICMD_DATAIN
);
273 SIO_CLR(VR_MIICMD_DATAIN
);
275 SIO_CLR(VR_MIICMD_CLK
);
277 SIO_SET(VR_MIICMD_CLK
);
283 * Read an PHY register through the MII.
286 vr_mii_readreg(struct vr_softc
*sc
, struct vr_mii_frame
*frame
)
293 /* Set up frame for RX. */
294 frame
->mii_stdelim
= VR_MII_STARTDELIM
;
295 frame
->mii_opcode
= VR_MII_READOP
;
296 frame
->mii_turnaround
= 0;
299 CSR_WRITE_1(sc
, VR_MIICMD
, 0);
300 VR_SETBIT(sc
, VR_MIICMD
, VR_MIICMD_DIRECTPGM
);
302 /* Turn on data xmit. */
303 SIO_SET(VR_MIICMD_DIR
);
307 /* Send command/address info. */
308 vr_mii_send(sc
, frame
->mii_stdelim
, 2);
309 vr_mii_send(sc
, frame
->mii_opcode
, 2);
310 vr_mii_send(sc
, frame
->mii_phyaddr
, 5);
311 vr_mii_send(sc
, frame
->mii_regaddr
, 5);
314 SIO_CLR((VR_MIICMD_CLK
|VR_MIICMD_DATAIN
));
316 SIO_SET(VR_MIICMD_CLK
);
320 SIO_CLR(VR_MIICMD_DIR
);
323 SIO_CLR(VR_MIICMD_CLK
);
325 ack
= CSR_READ_4(sc
, VR_MIICMD
) & VR_MIICMD_DATAOUT
;
326 SIO_SET(VR_MIICMD_CLK
);
330 * Now try reading data bits. If the ack failed, we still
331 * need to clock through 16 cycles to keep the PHY(s) in sync.
334 for(i
= 0; i
< 16; i
++) {
335 SIO_CLR(VR_MIICMD_CLK
);
337 SIO_SET(VR_MIICMD_CLK
);
343 for (i
= 0x8000; i
; i
>>= 1) {
344 SIO_CLR(VR_MIICMD_CLK
);
347 if (CSR_READ_4(sc
, VR_MIICMD
) & VR_MIICMD_DATAOUT
)
348 frame
->mii_data
|= i
;
351 SIO_SET(VR_MIICMD_CLK
);
356 SIO_CLR(VR_MIICMD_CLK
);
358 SIO_SET(VR_MIICMD_CLK
);
373 /* Set the PHY address. */
374 CSR_WRITE_1(sc
, VR_PHYADDR
, (CSR_READ_1(sc
, VR_PHYADDR
)& 0xe0)|
377 /* Set the register address. */
378 CSR_WRITE_1(sc
, VR_MIIADDR
, frame
->mii_regaddr
);
379 VR_SETBIT(sc
, VR_MIICMD
, VR_MIICMD_READ_ENB
);
381 for (i
= 0; i
< 10000; i
++) {
382 if ((CSR_READ_1(sc
, VR_MIICMD
) & VR_MIICMD_READ_ENB
) == 0)
386 frame
->mii_data
= CSR_READ_2(sc
, VR_MIIDATA
);
396 * Write to a PHY register through the MII.
399 vr_mii_writereg(struct vr_softc
*sc
, struct vr_mii_frame
*frame
)
405 CSR_WRITE_1(sc
, VR_MIICMD
, 0);
406 VR_SETBIT(sc
, VR_MIICMD
, VR_MIICMD_DIRECTPGM
);
408 /* Set up frame for TX. */
409 frame
->mii_stdelim
= VR_MII_STARTDELIM
;
410 frame
->mii_opcode
= VR_MII_WRITEOP
;
411 frame
->mii_turnaround
= VR_MII_TURNAROUND
;
413 /* Turn on data output. */
414 SIO_SET(VR_MIICMD_DIR
);
418 vr_mii_send(sc
, frame
->mii_stdelim
, 2);
419 vr_mii_send(sc
, frame
->mii_opcode
, 2);
420 vr_mii_send(sc
, frame
->mii_phyaddr
, 5);
421 vr_mii_send(sc
, frame
->mii_regaddr
, 5);
422 vr_mii_send(sc
, frame
->mii_turnaround
, 2);
423 vr_mii_send(sc
, frame
->mii_data
, 16);
426 SIO_SET(VR_MIICMD_CLK
);
428 SIO_CLR(VR_MIICMD_CLK
);
432 SIO_CLR(VR_MIICMD_DIR
);
444 /* Set the PHY-adress */
445 CSR_WRITE_1(sc
, VR_PHYADDR
, (CSR_READ_1(sc
, VR_PHYADDR
)& 0xe0)|
448 /* Set the register address and data to write. */
449 CSR_WRITE_1(sc
, VR_MIIADDR
, frame
->mii_regaddr
);
450 CSR_WRITE_2(sc
, VR_MIIDATA
, frame
->mii_data
);
452 VR_SETBIT(sc
, VR_MIICMD
, VR_MIICMD_WRITE_ENB
);
454 for (i
= 0; i
< 10000; i
++) {
455 if ((CSR_READ_1(sc
, VR_MIICMD
) & VR_MIICMD_WRITE_ENB
) == 0)
467 vr_miibus_readreg(device_t dev
, int phy
, int reg
)
469 struct vr_mii_frame frame
;
472 sc
= device_get_softc(dev
);
474 switch (sc
->vr_revid
) {
475 case REV_ID_VT6102_APOLLO
:
483 bzero(&frame
, sizeof(frame
));
485 frame
.mii_phyaddr
= phy
;
486 frame
.mii_regaddr
= reg
;
487 vr_mii_readreg(sc
, &frame
);
489 return(frame
.mii_data
);
493 vr_miibus_writereg(device_t dev
, int phy
, int reg
, int data
)
495 struct vr_mii_frame frame
;
498 sc
= device_get_softc(dev
);
500 switch (sc
->vr_revid
) {
501 case REV_ID_VT6102_APOLLO
:
509 bzero(&frame
, sizeof(frame
));
511 frame
.mii_phyaddr
= phy
;
512 frame
.mii_regaddr
= reg
;
513 frame
.mii_data
= data
;
515 vr_mii_writereg(sc
, &frame
);
521 vr_miibus_statchg(device_t dev
)
523 struct mii_data
*mii
;
526 sc
= device_get_softc(dev
);
527 mii
= device_get_softc(sc
->vr_miibus
);
528 vr_setcfg(sc
, mii
->mii_media_active
);
532 * Calculate CRC of a multicast group address, return the lower 6 bits.
535 vr_calchash(uint8_t *addr
)
541 /* Compute CRC for the address value. */
542 crc
= 0xFFFFFFFF; /* initial value */
544 for (i
= 0; i
< 6; i
++) {
546 for (j
= 0; j
< 8; j
++) {
547 carry
= ((crc
& 0x80000000) ? 1 : 0) ^ (c
& 0x01);
551 crc
= (crc
^ 0x04c11db6) | carry
;
555 /* return the filter bit position */
556 return((crc
>> 26) & 0x0000003F);
560 * Program the 64-bit multicast hash filter.
563 vr_setmulti(struct vr_softc
*sc
)
567 uint32_t hashes
[2] = { 0, 0 };
568 struct ifmultiaddr
*ifma
;
572 ifp
= &sc
->arpcom
.ac_if
;
574 rxfilt
= CSR_READ_1(sc
, VR_RXCFG
);
576 if (ifp
->if_flags
& IFF_ALLMULTI
|| ifp
->if_flags
& IFF_PROMISC
) {
577 rxfilt
|= VR_RXCFG_RX_MULTI
;
578 CSR_WRITE_1(sc
, VR_RXCFG
, rxfilt
);
579 CSR_WRITE_4(sc
, VR_MAR0
, 0xFFFFFFFF);
580 CSR_WRITE_4(sc
, VR_MAR1
, 0xFFFFFFFF);
584 /* First, zero out all the existing hash bits. */
585 CSR_WRITE_4(sc
, VR_MAR0
, 0);
586 CSR_WRITE_4(sc
, VR_MAR1
, 0);
588 /* Now program new ones. */
589 for (ifma
= ifp
->if_multiaddrs
.lh_first
; ifma
!= NULL
;
590 ifma
= ifma
->ifma_link
.le_next
) {
591 if (ifma
->ifma_addr
->sa_family
!= AF_LINK
)
593 h
= vr_calchash(LLADDR((struct sockaddr_dl
*)ifma
->ifma_addr
));
595 hashes
[0] |= (1 << h
);
597 hashes
[1] |= (1 << (h
- 32));
602 rxfilt
|= VR_RXCFG_RX_MULTI
;
604 rxfilt
&= ~VR_RXCFG_RX_MULTI
;
606 CSR_WRITE_4(sc
, VR_MAR0
, hashes
[0]);
607 CSR_WRITE_4(sc
, VR_MAR1
, hashes
[1]);
608 CSR_WRITE_1(sc
, VR_RXCFG
, rxfilt
);
612 * In order to fiddle with the
613 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
614 * first have to put the transmit and/or receive logic in the idle state.
617 vr_setcfg(struct vr_softc
*sc
, int media
)
621 if (CSR_READ_2(sc
, VR_COMMAND
) & (VR_CMD_TX_ON
|VR_CMD_RX_ON
)) {
623 VR_CLRBIT16(sc
, VR_COMMAND
, (VR_CMD_TX_ON
|VR_CMD_RX_ON
));
626 if ((media
& IFM_GMASK
) == IFM_FDX
)
627 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_FULLDUPLEX
);
629 VR_CLRBIT16(sc
, VR_COMMAND
, VR_CMD_FULLDUPLEX
);
632 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_TX_ON
|VR_CMD_RX_ON
);
636 vr_reset(struct vr_softc
*sc
)
640 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_RESET
);
642 for (i
= 0; i
< VR_TIMEOUT
; i
++) {
644 if (!(CSR_READ_2(sc
, VR_COMMAND
) & VR_CMD_RESET
))
647 if (i
== VR_TIMEOUT
) {
648 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
650 if (sc
->vr_revid
< REV_ID_VT3065_A
) {
651 if_printf(ifp
, "reset never completed!\n");
653 /* Use newer force reset command */
654 if_printf(ifp
, "Using force reset command.\n");
655 VR_SETBIT(sc
, VR_MISC_CR1
, VR_MISCCR1_FORSRST
);
659 /* Wait a little while for the chip to get its brains in order. */
664 * Probe for a VIA Rhine chip. Check the PCI vendor and device
665 * IDs against our list and return a device name if we find a match.
668 vr_probe(device_t dev
)
673 vid
= pci_get_vendor(dev
);
674 did
= pci_get_device(dev
);
676 for (t
= vr_devs
; t
->vr_name
!= NULL
; ++t
) {
677 if (vid
== t
->vr_vid
&& did
== t
->vr_did
) {
678 device_set_desc(dev
, t
->vr_name
);
687 * Attach the interface. Allocate softc structures, do ifmedia
688 * setup and ethernet/BPF attach.
691 vr_attach(device_t dev
)
694 uint8_t eaddr
[ETHER_ADDR_LEN
];
702 sc
= device_get_softc(dev
);
703 callout_init(&sc
->vr_stat_timer
);
706 * Handle power management nonsense.
709 command
= pci_read_config(dev
, VR_PCI_CAPID
, 4) & 0x000000FF;
710 if (command
== 0x01) {
711 command
= pci_read_config(dev
, VR_PCI_PWRMGMTCTRL
, 4);
712 if (command
& VR_PSTATE_MASK
) {
713 uint32_t iobase
, membase
, irq
;
715 /* Save important PCI config data. */
716 iobase
= pci_read_config(dev
, VR_PCI_LOIO
, 4);
717 membase
= pci_read_config(dev
, VR_PCI_LOMEM
, 4);
718 irq
= pci_read_config(dev
, VR_PCI_INTLINE
, 4);
720 /* Reset the power state. */
721 device_printf(dev
, "chip is in D%d power mode "
722 "-- setting to D0\n", command
& VR_PSTATE_MASK
);
723 command
&= 0xFFFFFFFC;
724 pci_write_config(dev
, VR_PCI_PWRMGMTCTRL
, command
, 4);
726 /* Restore PCI config data. */
727 pci_write_config(dev
, VR_PCI_LOIO
, iobase
, 4);
728 pci_write_config(dev
, VR_PCI_LOMEM
, membase
, 4);
729 pci_write_config(dev
, VR_PCI_INTLINE
, irq
, 4);
734 * Map control/status registers.
736 command
= pci_read_config(dev
, PCIR_COMMAND
, 4);
737 command
|= (PCIM_CMD_PORTEN
|PCIM_CMD_MEMEN
|PCIM_CMD_BUSMASTEREN
);
738 pci_write_config(dev
, PCIR_COMMAND
, command
, 4);
739 command
= pci_read_config(dev
, PCIR_COMMAND
, 4);
740 sc
->vr_revid
= pci_read_config(dev
, VR_PCI_REVID
, 4) & 0x000000FF;
743 if (!(command
& PCIM_CMD_PORTEN
)) {
744 device_printf(dev
, "failed to enable I/O ports!\n");
749 if (!(command
& PCIM_CMD_MEMEN
)) {
750 device_printf(dev
, "failed to enable memory mapping!\n");
756 sc
->vr_res
= bus_alloc_resource_any(dev
, VR_RES
, &rid
, RF_ACTIVE
);
758 if (sc
->vr_res
== NULL
) {
759 device_printf(dev
, "couldn't map ports/memory\n");
764 sc
->vr_btag
= rman_get_bustag(sc
->vr_res
);
765 sc
->vr_bhandle
= rman_get_bushandle(sc
->vr_res
);
767 /* Allocate interrupt */
769 sc
->vr_irq
= bus_alloc_resource_any(dev
, SYS_RES_IRQ
, &rid
,
770 RF_SHAREABLE
| RF_ACTIVE
);
772 if (sc
->vr_irq
== NULL
) {
773 device_printf(dev
, "couldn't map interrupt\n");
774 bus_release_resource(dev
, VR_RES
, VR_RID
, sc
->vr_res
);
779 error
= bus_setup_intr(dev
, sc
->vr_irq
, INTR_TYPE_NET
,
780 vr_intr
, sc
, &sc
->vr_intrhand
, NULL
);
783 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->vr_irq
);
784 bus_release_resource(dev
, VR_RES
, VR_RID
, sc
->vr_res
);
785 device_printf(dev
, "couldn't set up irq\n");
790 * Windows may put the chip in suspend mode when it
791 * shuts down. Be sure to kick it in the head to wake it
794 VR_CLRBIT(sc
, VR_STICKHW
, (VR_STICKHW_DS0
|VR_STICKHW_DS1
));
796 ifp
= &sc
->arpcom
.ac_if
;
797 if_initname(ifp
, device_get_name(dev
), device_get_unit(dev
));
799 /* Reset the adapter. */
803 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
804 * initialization and disable AUTOPOLL.
806 pci_write_config(dev
, VR_PCI_MODE
,
807 pci_read_config(dev
, VR_PCI_MODE
, 4) | (VR_MODE3_MIION
<< 24), 4);
808 VR_CLRBIT(sc
, VR_MIICMD
, VR_MIICMD_AUTOPOLL
);
811 * Get station address. The way the Rhine chips work,
812 * you're not allowed to directly access the EEPROM once
813 * they've been programmed a special way. Consequently,
814 * we need to read the node address from the PAR0 and PAR1
817 VR_SETBIT(sc
, VR_EECSR
, VR_EECSR_LOAD
);
819 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
820 eaddr
[i
] = CSR_READ_1(sc
, VR_PAR0
+ i
);
822 sc
->vr_ldata
= contigmalloc(sizeof(struct vr_list_data
), M_DEVBUF
,
823 M_NOWAIT
, 0, 0xffffffff, PAGE_SIZE
, 0);
825 if (sc
->vr_ldata
== NULL
) {
826 device_printf(dev
, "no memory for list buffers!\n");
827 bus_teardown_intr(dev
, sc
->vr_irq
, sc
->vr_intrhand
);
828 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->vr_irq
);
829 bus_release_resource(dev
, VR_RES
, VR_RID
, sc
->vr_res
);
834 bzero(sc
->vr_ldata
, sizeof(struct vr_list_data
));
837 ifp
->if_mtu
= ETHERMTU
;
838 ifp
->if_flags
= IFF_BROADCAST
| IFF_SIMPLEX
| IFF_MULTICAST
;
839 ifp
->if_ioctl
= vr_ioctl
;
840 ifp
->if_start
= vr_start
;
841 #ifdef DEVICE_POLLING
842 ifp
->if_poll
= vr_poll
;
844 ifp
->if_watchdog
= vr_watchdog
;
845 ifp
->if_init
= vr_init
;
846 ifp
->if_baudrate
= 10000000;
847 ifq_set_maxlen(&ifp
->if_snd
, VR_TX_LIST_CNT
- 1);
848 ifq_set_ready(&ifp
->if_snd
);
853 if (mii_phy_probe(dev
, &sc
->vr_miibus
,
854 vr_ifmedia_upd
, vr_ifmedia_sts
)) {
855 if_printf(ifp
, "MII without any phy!\n");
856 bus_teardown_intr(dev
, sc
->vr_irq
, sc
->vr_intrhand
);
857 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->vr_irq
);
858 bus_release_resource(dev
, VR_RES
, VR_RID
, sc
->vr_res
);
859 contigfree(sc
->vr_ldata
,
860 sizeof(struct vr_list_data
), M_DEVBUF
);
865 /* Call MI attach routine. */
866 ether_ifattach(ifp
, eaddr
);
874 vr_detach(device_t dev
)
876 struct vr_softc
*sc
= device_get_softc(dev
);
877 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
884 bus_generic_detach(dev
);
885 device_delete_child(dev
, sc
->vr_miibus
);
887 bus_teardown_intr(dev
, sc
->vr_irq
, sc
->vr_intrhand
);
891 bus_release_resource(dev
, SYS_RES_IRQ
, 0, sc
->vr_irq
);
892 bus_release_resource(dev
, VR_RES
, VR_RID
, sc
->vr_res
);
894 contigfree(sc
->vr_ldata
, sizeof(struct vr_list_data
), M_DEVBUF
);
900 * Initialize the transmit descriptors.
903 vr_list_tx_init(struct vr_softc
*sc
)
905 struct vr_chain_data
*cd
;
906 struct vr_list_data
*ld
;
911 for (i
= 0; i
< VR_TX_LIST_CNT
; i
++) {
912 cd
->vr_tx_chain
[i
].vr_ptr
= &ld
->vr_tx_list
[i
];
913 if (i
== (VR_TX_LIST_CNT
- 1))
917 cd
->vr_tx_chain
[i
].vr_nextdesc
= &cd
->vr_tx_chain
[nexti
];
920 cd
->vr_tx_free
= &cd
->vr_tx_chain
[0];
921 cd
->vr_tx_tail
= cd
->vr_tx_head
= NULL
;
928 * Initialize the RX descriptors and allocate mbufs for them. Note that
929 * we arrange the descriptors in a closed ring, so that the last descriptor
930 * points back to the first.
933 vr_list_rx_init(struct vr_softc
*sc
)
935 struct vr_chain_data
*cd
;
936 struct vr_list_data
*ld
;
942 for (i
= 0; i
< VR_RX_LIST_CNT
; i
++) {
943 cd
->vr_rx_chain
[i
].vr_ptr
= (struct vr_desc
*)&ld
->vr_rx_list
[i
];
944 if (vr_newbuf(sc
, &cd
->vr_rx_chain
[i
], NULL
) == ENOBUFS
)
946 if (i
== (VR_RX_LIST_CNT
- 1))
950 cd
->vr_rx_chain
[i
].vr_nextdesc
= &cd
->vr_rx_chain
[nexti
];
951 ld
->vr_rx_list
[i
].vr_next
= vtophys(&ld
->vr_rx_list
[nexti
]);
954 cd
->vr_rx_head
= &cd
->vr_rx_chain
[0];
960 * Initialize an RX descriptor and attach an MBUF cluster.
961 * Note: the length fields are only 11 bits wide, which means the
962 * largest size we can specify is 2047. This is important because
963 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
964 * overflow the field and make a mess.
967 vr_newbuf(struct vr_softc
*sc
, struct vr_chain_onefrag
*c
, struct mbuf
*m
)
969 struct mbuf
*m_new
= NULL
;
972 m_new
= m_getcl(MB_DONTWAIT
, MT_DATA
, M_PKTHDR
);
975 m_new
->m_len
= m_new
->m_pkthdr
.len
= MCLBYTES
;
978 m_new
->m_len
= m_new
->m_pkthdr
.len
= MCLBYTES
;
979 m_new
->m_data
= m_new
->m_ext
.ext_buf
;
982 m_adj(m_new
, sizeof(uint64_t));
985 c
->vr_ptr
->vr_status
= VR_RXSTAT
;
986 c
->vr_ptr
->vr_data
= vtophys(mtod(m_new
, caddr_t
));
987 c
->vr_ptr
->vr_ctl
= VR_RXCTL
| VR_RXLEN
;
993 * A frame has been uploaded: pass the resulting mbuf chain up to
994 * the higher level protocols.
997 vr_rxeof(struct vr_softc
*sc
)
1001 struct vr_chain_onefrag
*cur_rx
;
1005 ifp
= &sc
->arpcom
.ac_if
;
1007 while(!((rxstat
= sc
->vr_cdata
.vr_rx_head
->vr_ptr
->vr_status
) &
1009 struct mbuf
*m0
= NULL
;
1011 cur_rx
= sc
->vr_cdata
.vr_rx_head
;
1012 sc
->vr_cdata
.vr_rx_head
= cur_rx
->vr_nextdesc
;
1013 m
= cur_rx
->vr_mbuf
;
1016 * If an error occurs, update stats, clear the
1017 * status word and leave the mbuf cluster in place:
1018 * it should simply get re-used next time this descriptor
1019 * comes up in the ring.
1021 if (rxstat
& VR_RXSTAT_RXERR
) {
1023 if_printf(ifp
, "rx error (%02x):", rxstat
& 0x000000ff);
1024 if (rxstat
& VR_RXSTAT_CRCERR
)
1025 printf(" crc error");
1026 if (rxstat
& VR_RXSTAT_FRAMEALIGNERR
)
1027 printf(" frame alignment error\n");
1028 if (rxstat
& VR_RXSTAT_FIFOOFLOW
)
1029 printf(" FIFO overflow");
1030 if (rxstat
& VR_RXSTAT_GIANT
)
1031 printf(" received giant packet");
1032 if (rxstat
& VR_RXSTAT_RUNT
)
1033 printf(" received runt packet");
1034 if (rxstat
& VR_RXSTAT_BUSERR
)
1035 printf(" system bus error");
1036 if (rxstat
& VR_RXSTAT_BUFFERR
)
1037 printf("rx buffer error");
1039 vr_newbuf(sc
, cur_rx
, m
);
1043 /* No errors; receive the packet. */
1044 total_len
= VR_RXBYTES(cur_rx
->vr_ptr
->vr_status
);
1047 * XXX The VIA Rhine chip includes the CRC with every
1048 * received frame, and there's no way to turn this
1049 * behavior off (at least, I can't find anything in
1050 * the manual that explains how to do it) so we have
1051 * to trim off the CRC manually.
1053 total_len
-= ETHER_CRC_LEN
;
1055 m0
= m_devget(mtod(m
, char *) - ETHER_ALIGN
,
1056 total_len
+ ETHER_ALIGN
, 0, ifp
, NULL
);
1057 vr_newbuf(sc
, cur_rx
, m
);
1062 m_adj(m0
, ETHER_ALIGN
);
1066 (*ifp
->if_input
)(ifp
, m
);
1071 vr_rxeoc(struct vr_softc
*sc
)
1076 ifp
= &sc
->arpcom
.ac_if
;
1080 VR_CLRBIT16(sc
, VR_COMMAND
, VR_CMD_RX_ON
);
1083 /* Wait for receiver to stop */
1085 i
&& (CSR_READ_2(sc
, VR_COMMAND
) & VR_CMD_RX_ON
);
1087 ; /* Wait for receiver to stop */
1090 if_printf(ifp
, "rx shutdown error!\n");
1091 sc
->vr_flags
|= VR_F_RESTART
;
1097 CSR_WRITE_4(sc
, VR_RXADDR
, vtophys(sc
->vr_cdata
.vr_rx_head
->vr_ptr
));
1098 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_RX_ON
);
1099 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_RX_GO
);
1103 * A frame was downloaded to the chip. It's safe for us to clean up
1107 vr_txeof(struct vr_softc
*sc
)
1109 struct vr_chain
*cur_tx
;
1112 ifp
= &sc
->arpcom
.ac_if
;
1114 /* Reset the timeout timer; if_txeoc will clear it. */
1118 if (sc
->vr_cdata
.vr_tx_head
== NULL
)
1122 * Go through our tx list and free mbufs for those
1123 * frames that have been transmitted.
1125 while(sc
->vr_cdata
.vr_tx_head
->vr_mbuf
!= NULL
) {
1129 cur_tx
= sc
->vr_cdata
.vr_tx_head
;
1130 txstat
= cur_tx
->vr_ptr
->vr_status
;
1132 if ((txstat
& VR_TXSTAT_ABRT
) ||
1133 (txstat
& VR_TXSTAT_UDF
)) {
1135 i
&& (CSR_READ_2(sc
, VR_COMMAND
) & VR_CMD_TX_ON
);
1137 ; /* Wait for chip to shutdown */
1139 if_printf(ifp
, "tx shutdown timeout\n");
1140 sc
->vr_flags
|= VR_F_RESTART
;
1143 VR_TXOWN(cur_tx
) = VR_TXSTAT_OWN
;
1144 CSR_WRITE_4(sc
, VR_TXADDR
, vtophys(cur_tx
->vr_ptr
));
1148 if (txstat
& VR_TXSTAT_OWN
)
1151 if (txstat
& VR_TXSTAT_ERRSUM
) {
1153 if (txstat
& VR_TXSTAT_DEFER
)
1154 ifp
->if_collisions
++;
1155 if (txstat
& VR_TXSTAT_LATECOLL
)
1156 ifp
->if_collisions
++;
1159 ifp
->if_collisions
+=(txstat
& VR_TXSTAT_COLLCNT
) >> 3;
1162 if (cur_tx
->vr_mbuf
!= NULL
) {
1163 m_freem(cur_tx
->vr_mbuf
);
1164 cur_tx
->vr_mbuf
= NULL
;
1167 if (sc
->vr_cdata
.vr_tx_head
== sc
->vr_cdata
.vr_tx_tail
) {
1168 sc
->vr_cdata
.vr_tx_head
= NULL
;
1169 sc
->vr_cdata
.vr_tx_tail
= NULL
;
1173 sc
->vr_cdata
.vr_tx_head
= cur_tx
->vr_nextdesc
;
1178 * TX 'end of channel' interrupt handler.
1181 vr_txeoc(struct vr_softc
*sc
)
1185 ifp
= &sc
->arpcom
.ac_if
;
1187 if (sc
->vr_cdata
.vr_tx_head
== NULL
) {
1188 ifp
->if_flags
&= ~IFF_OACTIVE
;
1189 sc
->vr_cdata
.vr_tx_tail
= NULL
;
1197 struct vr_softc
*sc
= xsc
;
1198 struct mii_data
*mii
;
1202 if (sc
->vr_flags
& VR_F_RESTART
) {
1203 if_printf(&sc
->arpcom
.ac_if
, "restarting\n");
1207 sc
->vr_flags
&= ~VR_F_RESTART
;
1210 mii
= device_get_softc(sc
->vr_miibus
);
1213 callout_reset(&sc
->vr_stat_timer
, hz
, vr_tick
, sc
);
1221 struct vr_softc
*sc
;
1226 ifp
= &sc
->arpcom
.ac_if
;
1228 /* Supress unwanted interrupts. */
1229 if (!(ifp
->if_flags
& IFF_UP
)) {
1234 /* Disable interrupts. */
1235 if ((ifp
->if_flags
& IFF_POLLING
) == 0)
1236 CSR_WRITE_2(sc
, VR_IMR
, 0x0000);
1239 status
= CSR_READ_2(sc
, VR_ISR
);
1241 CSR_WRITE_2(sc
, VR_ISR
, status
);
1243 if ((status
& VR_INTRS
) == 0)
1246 if (status
& VR_ISR_RX_OK
)
1249 if (status
& VR_ISR_RX_DROPPED
) {
1250 if_printf(ifp
, "rx packet lost\n");
1254 if ((status
& VR_ISR_RX_ERR
) || (status
& VR_ISR_RX_NOBUF
) ||
1255 (status
& VR_ISR_RX_NOBUF
) || (status
& VR_ISR_RX_OFLOW
)) {
1256 if_printf(ifp
, "receive error (%04x)", status
);
1257 if (status
& VR_ISR_RX_NOBUF
)
1258 printf(" no buffers");
1259 if (status
& VR_ISR_RX_OFLOW
)
1260 printf(" overflow");
1261 if (status
& VR_ISR_RX_DROPPED
)
1262 printf(" packet lost");
1267 if ((status
& VR_ISR_BUSERR
) || (status
& VR_ISR_TX_UNDERRUN
)) {
1273 if ((status
& VR_ISR_TX_OK
) || (status
& VR_ISR_TX_ABRT
) ||
1274 (status
& VR_ISR_TX_ABRT2
) || (status
& VR_ISR_UDFI
)) {
1276 if ((status
& VR_ISR_UDFI
) ||
1277 (status
& VR_ISR_TX_ABRT2
) ||
1278 (status
& VR_ISR_TX_ABRT
)) {
1280 if (sc
->vr_cdata
.vr_tx_head
!= NULL
) {
1281 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_TX_ON
);
1282 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_TX_GO
);
1291 /* Re-enable interrupts. */
1292 if ((ifp
->if_flags
& IFF_POLLING
) == 0)
1293 CSR_WRITE_2(sc
, VR_IMR
, VR_INTRS
);
1295 if (!ifq_is_empty(&ifp
->if_snd
))
1300 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1301 * pointers to the fragment pointers.
1304 vr_encap(struct vr_softc
*sc
, struct vr_chain
*c
, struct mbuf
*m_head
)
1307 struct vr_desc
*f
= NULL
;
1314 * The VIA Rhine wants packet buffers to be longword
1315 * aligned, but very often our mbufs aren't. Rather than
1316 * waste time trying to decide when to copy and when not
1317 * to copy, just do it all the time.
1319 m_new
= m_getl(m_head
->m_pkthdr
.len
, MB_DONTWAIT
, MT_DATA
, M_PKTHDR
,
1321 if (m_new
== NULL
) {
1322 if_printf(&sc
->arpcom
.ac_if
, "no memory for tx list\n");
1325 m_copydata(m_head
, 0, m_head
->m_pkthdr
.len
,
1326 mtod(m_new
, caddr_t
));
1327 m_new
->m_pkthdr
.len
= m_new
->m_len
= m_head
->m_pkthdr
.len
;
1329 * The Rhine chip doesn't auto-pad, so we have to make
1330 * sure to pad short frames out to the minimum frame length
1333 if (m_new
->m_len
< VR_MIN_FRAMELEN
) {
1334 m_new
->m_pkthdr
.len
+= VR_MIN_FRAMELEN
- m_new
->m_len
;
1335 m_new
->m_len
= m_new
->m_pkthdr
.len
;
1338 f
->vr_data
= vtophys(mtod(m_new
, caddr_t
));
1339 f
->vr_ctl
= total_len
= m_new
->m_len
;
1340 f
->vr_ctl
|= VR_TXCTL_TLINK
|VR_TXCTL_FIRSTFRAG
;
1345 c
->vr_ptr
->vr_ctl
|= VR_TXCTL_LASTFRAG
|VR_TXCTL_FINT
;
1346 c
->vr_ptr
->vr_next
= vtophys(c
->vr_nextdesc
->vr_ptr
);
1352 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1353 * to the mbuf data regions directly in the transmit lists. We also save a
1354 * copy of the pointers since the transmit list fragment pointers are
1355 * physical addresses.
1358 vr_start(struct ifnet
*ifp
)
1360 struct vr_softc
*sc
;
1361 struct mbuf
*m_head
= NULL
;
1362 struct vr_chain
*cur_tx
= NULL
, *start_tx
;
1366 if (ifp
->if_flags
& IFF_OACTIVE
)
1369 /* Check for an available queue slot. If there are none, punt. */
1370 if (sc
->vr_cdata
.vr_tx_free
->vr_mbuf
!= NULL
) {
1371 ifp
->if_flags
|= IFF_OACTIVE
;
1375 start_tx
= sc
->vr_cdata
.vr_tx_free
;
1377 while(sc
->vr_cdata
.vr_tx_free
->vr_mbuf
== NULL
) {
1378 m_head
= ifq_poll(&ifp
->if_snd
);
1382 /* Pick a descriptor off the free list. */
1383 cur_tx
= sc
->vr_cdata
.vr_tx_free
;
1384 sc
->vr_cdata
.vr_tx_free
= cur_tx
->vr_nextdesc
;
1386 /* Pack the data into the descriptor. */
1387 if (vr_encap(sc
, cur_tx
, m_head
)) {
1388 ifp
->if_flags
|= IFF_OACTIVE
;
1393 m_head
= ifq_dequeue(&ifp
->if_snd
);
1394 if (cur_tx
!= start_tx
)
1395 VR_TXOWN(cur_tx
) = VR_TXSTAT_OWN
;
1397 BPF_MTAP(ifp
, m_head
);
1400 VR_TXOWN(cur_tx
) = VR_TXSTAT_OWN
;
1401 VR_SETBIT16(sc
, VR_COMMAND
, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO
);
1404 /* If there are no frames queued, bail. */
1408 sc
->vr_cdata
.vr_tx_tail
= cur_tx
;
1410 if (sc
->vr_cdata
.vr_tx_head
== NULL
)
1411 sc
->vr_cdata
.vr_tx_head
= start_tx
;
1414 * Set a timeout in case the chip goes out to lunch.
1422 struct vr_softc
*sc
= xsc
;
1423 struct ifnet
*ifp
= &sc
->arpcom
.ac_if
;
1424 struct mii_data
*mii
;
1427 mii
= device_get_softc(sc
->vr_miibus
);
1431 /* Cancel pending I/O and free all RX/TX buffers. */
1435 /* Set our station address. */
1436 for (i
= 0; i
< ETHER_ADDR_LEN
; i
++)
1437 CSR_WRITE_1(sc
, VR_PAR0
+ i
, sc
->arpcom
.ac_enaddr
[i
]);
1440 VR_CLRBIT(sc
, VR_BCR0
, VR_BCR0_DMA_LENGTH
);
1441 VR_SETBIT(sc
, VR_BCR0
, VR_BCR0_DMA_STORENFWD
);
1444 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1445 * so we must set both.
1447 VR_CLRBIT(sc
, VR_BCR0
, VR_BCR0_RX_THRESH
);
1448 VR_SETBIT(sc
, VR_BCR0
, VR_BCR0_RXTHRESH128BYTES
);
1450 VR_CLRBIT(sc
, VR_BCR1
, VR_BCR1_TX_THRESH
);
1451 VR_SETBIT(sc
, VR_BCR1
, VR_BCR1_TXTHRESHSTORENFWD
);
1453 VR_CLRBIT(sc
, VR_RXCFG
, VR_RXCFG_RX_THRESH
);
1454 VR_SETBIT(sc
, VR_RXCFG
, VR_RXTHRESH_128BYTES
);
1456 VR_CLRBIT(sc
, VR_TXCFG
, VR_TXCFG_TX_THRESH
);
1457 VR_SETBIT(sc
, VR_TXCFG
, VR_TXTHRESH_STORENFWD
);
1459 /* Init circular RX list. */
1460 if (vr_list_rx_init(sc
) == ENOBUFS
) {
1463 if_printf(ifp
, "initialization failed: no memory for rx buffers\n");
1467 /* Init tx descriptors. */
1468 vr_list_tx_init(sc
);
1470 /* If we want promiscuous mode, set the allframes bit. */
1471 if (ifp
->if_flags
& IFF_PROMISC
)
1472 VR_SETBIT(sc
, VR_RXCFG
, VR_RXCFG_RX_PROMISC
);
1474 VR_CLRBIT(sc
, VR_RXCFG
, VR_RXCFG_RX_PROMISC
);
1476 /* Set capture broadcast bit to capture broadcast frames. */
1477 if (ifp
->if_flags
& IFF_BROADCAST
)
1478 VR_SETBIT(sc
, VR_RXCFG
, VR_RXCFG_RX_BROAD
);
1480 VR_CLRBIT(sc
, VR_RXCFG
, VR_RXCFG_RX_BROAD
);
1483 * Program the multicast filter, if necessary.
1488 * Load the address of the RX list.
1490 CSR_WRITE_4(sc
, VR_RXADDR
, vtophys(sc
->vr_cdata
.vr_rx_head
->vr_ptr
));
1492 /* Enable receiver and transmitter. */
1493 CSR_WRITE_2(sc
, VR_COMMAND
, VR_CMD_TX_NOPOLL
|VR_CMD_START
|
1494 VR_CMD_TX_ON
|VR_CMD_RX_ON
|
1497 CSR_WRITE_4(sc
, VR_TXADDR
, vtophys(&sc
->vr_ldata
->vr_tx_list
[0]));
1500 * Enable interrupts, unless we are polling.
1502 CSR_WRITE_2(sc
, VR_ISR
, 0xFFFF);
1503 if ((ifp
->if_flags
& IFF_POLLING
) == 0)
1504 CSR_WRITE_2(sc
, VR_IMR
, VR_INTRS
);
1508 ifp
->if_flags
|= IFF_RUNNING
;
1509 ifp
->if_flags
&= ~IFF_OACTIVE
;
1513 callout_reset(&sc
->vr_stat_timer
, hz
, vr_tick
, sc
);
1517 * Set media options.
1520 vr_ifmedia_upd(struct ifnet
*ifp
)
1522 struct vr_softc
*sc
;
1526 if (ifp
->if_flags
& IFF_UP
)
1533 * Report current media status.
1536 vr_ifmedia_sts(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
1538 struct vr_softc
*sc
;
1539 struct mii_data
*mii
;
1542 mii
= device_get_softc(sc
->vr_miibus
);
1544 ifmr
->ifm_active
= mii
->mii_media_active
;
1545 ifmr
->ifm_status
= mii
->mii_media_status
;
1549 vr_ioctl(struct ifnet
*ifp
, u_long command
, caddr_t data
, struct ucred
*cr
)
1551 struct vr_softc
*sc
= ifp
->if_softc
;
1552 struct ifreq
*ifr
= (struct ifreq
*) data
;
1553 struct mii_data
*mii
;
1560 if (ifp
->if_flags
& IFF_UP
) {
1563 if (ifp
->if_flags
& IFF_RUNNING
)
1575 mii
= device_get_softc(sc
->vr_miibus
);
1576 error
= ifmedia_ioctl(ifp
, ifr
, &mii
->mii_media
, command
);
1579 error
= ether_ioctl(ifp
, command
, data
);
1588 #ifdef DEVICE_POLLING
1591 vr_poll(struct ifnet
*ifp
, enum poll_cmd cmd
, int count
)
1593 struct vr_softc
*sc
= ifp
->if_softc
;
1597 /* disable interrupts */
1598 CSR_WRITE_2(sc
, VR_IMR
, 0x0000);
1600 case POLL_DEREGISTER
:
1601 /* enable interrupts */
1602 CSR_WRITE_2(sc
, VR_IMR
, VR_INTRS
);
1612 vr_watchdog(struct ifnet
*ifp
)
1614 struct vr_softc
*sc
;
1619 if_printf(ifp
, "watchdog timeout\n");
1621 #ifdef DEVICE_POLLING
1622 if (++sc
->vr_wdogerrors
== 1 && (ifp
->if_flags
& IFF_POLLING
) == 0) {
1623 if_printf(ifp
, "ints don't seem to be working, "
1624 "emergency switch to polling\n");
1625 emergency_poll_enable("if_vr");
1626 ether_poll_register(ifp
); /* XXX illegal */
1635 if (!ifq_is_empty(&ifp
->if_snd
))
1640 * Stop the adapter and free any mbufs allocated to the
1644 vr_stop(struct vr_softc
*sc
)
1649 ifp
= &sc
->arpcom
.ac_if
;
1652 callout_stop(&sc
->vr_stat_timer
);
1654 VR_SETBIT16(sc
, VR_COMMAND
, VR_CMD_STOP
);
1655 VR_CLRBIT16(sc
, VR_COMMAND
, (VR_CMD_RX_ON
|VR_CMD_TX_ON
));
1656 CSR_WRITE_2(sc
, VR_IMR
, 0x0000);
1657 CSR_WRITE_4(sc
, VR_TXADDR
, 0x00000000);
1658 CSR_WRITE_4(sc
, VR_RXADDR
, 0x00000000);
1661 * Free data in the RX lists.
1663 for (i
= 0; i
< VR_RX_LIST_CNT
; i
++) {
1664 if (sc
->vr_cdata
.vr_rx_chain
[i
].vr_mbuf
!= NULL
) {
1665 m_freem(sc
->vr_cdata
.vr_rx_chain
[i
].vr_mbuf
);
1666 sc
->vr_cdata
.vr_rx_chain
[i
].vr_mbuf
= NULL
;
1669 bzero((char *)&sc
->vr_ldata
->vr_rx_list
,
1670 sizeof(sc
->vr_ldata
->vr_rx_list
));
1673 * Free the TX list buffers.
1675 for (i
= 0; i
< VR_TX_LIST_CNT
; i
++) {
1676 if (sc
->vr_cdata
.vr_tx_chain
[i
].vr_mbuf
!= NULL
) {
1677 m_freem(sc
->vr_cdata
.vr_tx_chain
[i
].vr_mbuf
);
1678 sc
->vr_cdata
.vr_tx_chain
[i
].vr_mbuf
= NULL
;
1682 bzero((char *)&sc
->vr_ldata
->vr_tx_list
,
1683 sizeof(sc
->vr_ldata
->vr_tx_list
));
1685 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
1689 * Stop all chip I/O so that the kernel's probe routines don't
1690 * get confused by errant DMAs when rebooting.
1693 vr_shutdown(device_t dev
)
1695 struct vr_softc
*sc
;
1697 sc
= device_get_softc(dev
);