sys/i386/include/cpufunc.h

   1 /*-
   2  * Copyright (c) 1993 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by the University of
  16  *      California, Berkeley and its contributors.
  17  * 4. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
  34  * $DragonFly: src/sys/i386/include/Attic/cpufunc.h,v 1.13 2005/06/03 23:57:31 dillon Exp $
  35  */
  36
  37 /*
  38  * Functions to provide access to special i386 instructions.
  39  */
  40
  41 #ifndef _MACHINE_CPUFUNC_H_
  42 #define _MACHINE_CPUFUNC_H_
  43
  44 #include <sys/cdefs.h>
  45
  46 __BEGIN_DECLS
  47 #define readb(va)       (*(volatile u_int8_t *) (va))
  48 #define readw(va)       (*(volatile u_int16_t *) (va))
  49 #define readl(va)       (*(volatile u_int32_t *) (va))
  50
  51 #define writeb(va, d)   (*(volatile u_int8_t *) (va) = (d))
  52 #define writew(va, d)   (*(volatile u_int16_t *) (va) = (d))
  53 #define writel(va, d)   (*(volatile u_int32_t *) (va) = (d))
  54
  55 #ifdef  __GNUC__
  56
  57 #ifdef SMP
  58 #include "lock.h"               /* XXX */
  59 #endif
  60
  61 #ifdef SWTCH_OPTIM_STATS
  62 extern  int     tlb_flush_count;        /* XXX */
  63 #endif
  64
  65 static __inline void
  66 breakpoint(void)
  67 {
  68         __asm __volatile("int $3");
  69 }
  70
  71 /*
  72  * Find the first 1 in mask, starting with bit 0 and return the
  73  * bit number.  If mask is 0 the result is undefined.
  74  */
  75 static __inline u_int
  76 bsfl(u_int mask)
  77 {
  78         u_int   result;
  79
  80         __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
  81         return (result);
  82 }
  83
  84 /*
  85  * Find the last 1 in mask, starting with bit 31 and return the
  86  * bit number.  If mask is 0 the result is undefined.
  87  */
  88 static __inline u_int
  89 bsrl(u_int mask)
  90 {
  91         u_int   result;
  92
  93         __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
  94         return (result);
  95 }
  96
  97 /*
  98  * Test and set the specified bit (1 << bit) in the integer.  The
  99  * previous value of the bit is returned (0 or 1).
 100  */
 101 static __inline int
 102 btsl(u_int *mask, int bit)
 103 {
 104         int result;
 105
 106         __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
 107                     "=r"(result), "=m"(*mask) : "r" (bit));
 108         return(result);
 109 }
 110
 111 /*
 112  * Test and clear the specified bit (1 << bit) in the integer.  The
 113  * previous value of the bit is returned (0 or 1).
 114  */
 115 static __inline int
 116 btrl(u_int *mask, int bit)
 117 {
 118         int result;
 119
 120         __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
 121                     "=r"(result), "=m"(*mask) : "r" (bit));
 122         return(result);
 123 }
 124
 125 static __inline void
 126 do_cpuid(u_int ax, u_int *p)
 127 {
 128         __asm __volatile("cpuid"
 129                          : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
 130                          :  "0" (ax));
 131 }
 132
 133 static __inline void
 134 cpu_disable_intr(void)
 135 {
 136         __asm __volatile("cli" : : : "memory");
 137 }
 138
 139 static __inline void
 140 cpu_enable_intr(void)
 141 {
 142         __asm __volatile("sti");
 143 }
 144
 145 /*
 146  * Cpu and compiler memory ordering fence.  mfence ensures strong read and
 147  * write ordering.
 148  *
 149  * A serializing or fence instruction is required here.  A locked bus
 150  * cycle on data for which we already own cache mastership is the most
 151  * portable.
 152  */
 153 static __inline void
 154 cpu_mfence(void)
 155 {
 156 #ifdef SMP
 157         __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
 158 #else
 159         __asm __volatile("" : : : "memory");
 160 #endif
 161 }
 162
 163 /*
 164  * cpu_lfence() ensures strong read ordering for reads issued prior
 165  * to the instruction verses reads issued afterwords.
 166  *
 167  * A serializing or fence instruction is required here.  A locked bus
 168  * cycle on data for which we already own cache mastership is the most
 169  * portable.
 170  */
 171 static __inline void
 172 cpu_lfence(void)
 173 {
 174 #ifdef SMP
 175         __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
 176 #else
 177         __asm __volatile("" : : : "memory");
 178 #endif
 179 }
 180
 181 /*
 182  * cpu_lfence() ensures strong write ordering for writes issued prior
 183  * to the instruction verses writes issued afterwords.  Writes are
 184  * ordered on intel cpus so we do not actually have to do anything.
 185  */
 186 static __inline void
 187 cpu_sfence(void)
 188 {
 189         __asm __volatile("" : : : "memory");
 190 }
 191
 192 /*
 193  * cpu_ccfence() prevents the compiler from reordering instructions, in
 194  * particular stores, relative to the current cpu.  Use cpu_sfence() if
 195  * you need to guarentee ordering by both the compiler and by the cpu.
 196  *
 197  * This also prevents the compiler from caching memory loads into local
 198  * variables across the routine.
 199  */
 200 static __inline void
 201 cpu_ccfence(void)
 202 {
 203         __asm __volatile("" : : : "memory");
 204 }
 205
 206 #ifdef _KERNEL
 207
 208 #define HAVE_INLINE_FFS
 209
 210 static __inline int
 211 ffs(int mask)
 212 {
 213         /*
 214          * Note that gcc-2's builtin ffs would be used if we didn't declare
 215          * this inline or turn off the builtin.  The builtin is faster but
 216          * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
 217          * versions.
 218          */
 219          return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
 220 }
 221
 222 #define HAVE_INLINE_FLS
 223
 224 static __inline int
 225 fls(int mask)
 226 {
 227         return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
 228 }
 229
 230 #endif /* _KERNEL */
 231
 232 /*
 233  * The following complications are to get around gcc not having a
 234  * constraint letter for the range 0..255.  We still put "d" in the
 235  * constraint because "i" isn't a valid constraint when the port
 236  * isn't constant.  This only matters for -O0 because otherwise
 237  * the non-working version gets optimized away.
 238  *
 239  * Use an expression-statement instead of a conditional expression
 240  * because gcc-2.6.0 would promote the operands of the conditional
 241  * and produce poor code for "if ((inb(var) & const1) == const2)".
 242  *
 243  * The unnecessary test `(port) < 0x10000' is to generate a warning if
 244  * the `port' has type u_short or smaller.  Such types are pessimal.
 245  * This actually only works for signed types.  The range check is
 246  * careful to avoid generating warnings.
 247  */
 248 #define inb(port) __extension__ ({                                      \
 249         u_char  _data;                                                  \
 250         if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100     \
 251             && (port) < 0x10000)                                        \
 252                 _data = inbc(port);                                     \
 253         else                                                            \
 254                 _data = inbv(port);                                     \
 255         _data; })
 256
 257 #define outb(port, data) (                                              \
 258         __builtin_constant_p(port) && ((port) & 0xffff) < 0x100         \
 259         && (port) < 0x10000                                             \
 260         ? outbc(port, data) : outbv(port, data))
 261
 262 static __inline u_char
 263 inbc(u_int port)
 264 {
 265         u_char  data;
 266
 267         __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
 268         return (data);
 269 }
 270
 271 static __inline void
 272 outbc(u_int port, u_char data)
 273 {
 274         __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
 275 }
 276
 277 static __inline u_char
 278 inbv(u_int port)
 279 {
 280         u_char  data;
 281         /*
 282          * We use %%dx and not %1 here because i/o is done at %dx and not at
 283          * %edx, while gcc generates inferior code (movw instead of movl)
 284          * if we tell it to load (u_short) port.
 285          */
 286         __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
 287         return (data);
 288 }
 289
 290 static __inline u_int
 291 inl(u_int port)
 292 {
 293         u_int   data;
 294
 295         __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
 296         return (data);
 297 }
 298
 299 static __inline void
 300 insb(u_int port, void *addr, size_t cnt)
 301 {
 302         __asm __volatile("cld; rep; insb"
 303                          : "=D" (addr), "=c" (cnt)
 304                          :  "0" (addr),  "1" (cnt), "d" (port)
 305                          : "memory");
 306 }
 307
 308 static __inline void
 309 insw(u_int port, void *addr, size_t cnt)
 310 {
 311         __asm __volatile("cld; rep; insw"
 312                          : "=D" (addr), "=c" (cnt)
 313                          :  "0" (addr),  "1" (cnt), "d" (port)
 314                          : "memory");
 315 }
 316
 317 static __inline void
 318 insl(u_int port, void *addr, size_t cnt)
 319 {
 320         __asm __volatile("cld; rep; insl"
 321                          : "=D" (addr), "=c" (cnt)
 322                          :  "0" (addr),  "1" (cnt), "d" (port)
 323                          : "memory");
 324 }
 325
 326 static __inline void
 327 invd(void)
 328 {
 329         __asm __volatile("invd");
 330 }
 331
 332 #if defined(_KERNEL)
 333
 334 /*
 335  * If we are not a true-SMP box then smp_invltlb() is a NOP.  Note that this
 336  * will cause the invl*() functions to be equivalent to the cpu_invl*()
 337  * functions.
 338  */
 339 #ifdef SMP
 340 void smp_invltlb(void);
 341 #else
 342 #define smp_invltlb()
 343 #endif
 344
 345 /*
 346  * Invalidate a patricular VA on this cpu only
 347  */
 348 static __inline void
 349 cpu_invlpg(void *addr)
 350 {
 351         __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
 352 }
 353
 354 /*
 355  * Invalidate the TLB on this cpu only
 356  */
 357 static __inline void
 358 cpu_invltlb(void)
 359 {
 360         u_int   temp;
 361         /*
 362          * This should be implemented as load_cr3(rcr3()) when load_cr3()
 363          * is inlined.
 364          */
 365         __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
 366                          : : "memory");
 367 #if defined(SWTCH_OPTIM_STATS)
 368         ++tlb_flush_count;
 369 #endif
 370 }
 371
 372 #endif  /* _KERNEL */
 373
 374 static __inline u_short
 375 inw(u_int port)
 376 {
 377         u_short data;
 378
 379         __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
 380         return (data);
 381 }
 382
 383 static __inline u_int
 384 loadandclear(volatile u_int *addr)
 385 {
 386         u_int   result;
 387
 388         __asm __volatile("xorl %0,%0; xchgl %1,%0"
 389                          : "=&r" (result) : "m" (*addr));
 390         return (result);
 391 }
 392
 393 static __inline void
 394 outbv(u_int port, u_char data)
 395 {
 396         u_char  al;
 397         /*
 398          * Use an unnecessary assignment to help gcc's register allocator.
 399          * This make a large difference for gcc-1.40 and a tiny difference
 400          * for gcc-2.6.0.  For gcc-1.40, al had to be ``asm("ax")'' for
 401          * best results.  gcc-2.6.0 can't handle this.
 402          */
 403         al = data;
 404         __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
 405 }
 406
 407 static __inline void
 408 outl(u_int port, u_int data)
 409 {
 410         /*
 411          * outl() and outw() aren't used much so we haven't looked at
 412          * possible micro-optimizations such as the unnecessary
 413          * assignment for them.
 414          */
 415         __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
 416 }
 417
 418 static __inline void
 419 outsb(u_int port, const void *addr, size_t cnt)
 420 {
 421         __asm __volatile("cld; rep; outsb"
 422                          : "=S" (addr), "=c" (cnt)
 423                          :  "0" (addr),  "1" (cnt), "d" (port));
 424 }
 425
 426 static __inline void
 427 outsw(u_int port, const void *addr, size_t cnt)
 428 {
 429         __asm __volatile("cld; rep; outsw"
 430                          : "=S" (addr), "=c" (cnt)
 431                          :  "0" (addr),  "1" (cnt), "d" (port));
 432 }
 433
 434 static __inline void
 435 outsl(u_int port, const void *addr, size_t cnt)
 436 {
 437         __asm __volatile("cld; rep; outsl"
 438                          : "=S" (addr), "=c" (cnt)
 439                          :  "0" (addr),  "1" (cnt), "d" (port));
 440 }
 441
 442 static __inline void
 443 outw(u_int port, u_short data)
 444 {
 445         __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
 446 }
 447
 448 static __inline u_int
 449 rcr2(void)
 450 {
 451         u_int   data;
 452
 453         __asm __volatile("movl %%cr2,%0" : "=r" (data));
 454         return (data);
 455 }
 456
 457 static __inline u_int
 458 read_eflags(void)
 459 {
 460         u_int   ef;
 461
 462         __asm __volatile("pushfl; popl %0" : "=r" (ef));
 463         return (ef);
 464 }
 465
 466 static __inline u_int64_t
 467 rdmsr(u_int msr)
 468 {
 469         u_int64_t rv;
 470
 471         __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
 472         return (rv);
 473 }
 474
 475 static __inline u_int64_t
 476 rdpmc(u_int pmc)
 477 {
 478         u_int64_t rv;
 479
 480         __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
 481         return (rv);
 482 }
 483
 484 static __inline u_int64_t
 485 rdtsc(void)
 486 {
 487         u_int64_t rv;
 488
 489         __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
 490         return (rv);
 491 }
 492
 493 static __inline void
 494 wbinvd(void)
 495 {
 496         __asm __volatile("wbinvd");
 497 }
 498
 499 static __inline void
 500 write_eflags(u_int ef)
 501 {
 502         __asm __volatile("pushl %0; popfl" : : "r" (ef));
 503 }
 504
 505 static __inline void
 506 wrmsr(u_int msr, u_int64_t newval)
 507 {
 508         __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
 509 }
 510
 511 static __inline u_int
 512 rfs(void)
 513 {
 514         u_int sel;
 515         __asm __volatile("movl %%fs,%0" : "=rm" (sel));
 516         return (sel);
 517 }
 518
 519 static __inline u_int
 520 rgs(void)
 521 {
 522         u_int sel;
 523         __asm __volatile("movl %%gs,%0" : "=rm" (sel));
 524         return (sel);
 525 }
 526
 527 static __inline void
 528 load_fs(u_int sel)
 529 {
 530         __asm __volatile("movl %0,%%fs" : : "rm" (sel));
 531 }
 532
 533 static __inline void
 534 load_gs(u_int sel)
 535 {
 536         __asm __volatile("movl %0,%%gs" : : "rm" (sel));
 537 }
 538
 539 static __inline u_int
 540 rdr0(void)
 541 {
 542         u_int   data;
 543         __asm __volatile("movl %%dr0,%0" : "=r" (data));
 544         return (data);
 545 }
 546
 547 static __inline void
 548 load_dr0(u_int sel)
 549 {
 550         __asm __volatile("movl %0,%%dr0" : : "r" (sel));
 551 }
 552
 553 static __inline u_int
 554 rdr1(void)
 555 {
 556         u_int   data;
 557         __asm __volatile("movl %%dr1,%0" : "=r" (data));
 558         return (data);
 559 }
 560
 561 static __inline void
 562 load_dr1(u_int sel)
 563 {
 564         __asm __volatile("movl %0,%%dr1" : : "r" (sel));
 565 }
 566
 567 static __inline u_int
 568 rdr2(void)
 569 {
 570         u_int   data;
 571         __asm __volatile("movl %%dr2,%0" : "=r" (data));
 572         return (data);
 573 }
 574
 575 static __inline void
 576 load_dr2(u_int sel)
 577 {
 578         __asm __volatile("movl %0,%%dr2" : : "r" (sel));
 579 }
 580
 581 static __inline u_int
 582 rdr3(void)
 583 {
 584         u_int   data;
 585         __asm __volatile("movl %%dr3,%0" : "=r" (data));
 586         return (data);
 587 }
 588
 589 static __inline void
 590 load_dr3(u_int sel)
 591 {
 592         __asm __volatile("movl %0,%%dr3" : : "r" (sel));
 593 }
 594
 595 static __inline u_int
 596 rdr4(void)
 597 {
 598         u_int   data;
 599         __asm __volatile("movl %%dr4,%0" : "=r" (data));
 600         return (data);
 601 }
 602
 603 static __inline void
 604 load_dr4(u_int sel)
 605 {
 606         __asm __volatile("movl %0,%%dr4" : : "r" (sel));
 607 }
 608
 609 static __inline u_int
 610 rdr5(void)
 611 {
 612         u_int   data;
 613         __asm __volatile("movl %%dr5,%0" : "=r" (data));
 614         return (data);
 615 }
 616
 617 static __inline void
 618 load_dr5(u_int sel)
 619 {
 620         __asm __volatile("movl %0,%%dr5" : : "r" (sel));
 621 }
 622
 623 static __inline u_int
 624 rdr6(void)
 625 {
 626         u_int   data;
 627         __asm __volatile("movl %%dr6,%0" : "=r" (data));
 628         return (data);
 629 }
 630
 631 static __inline void
 632 load_dr6(u_int sel)
 633 {
 634         __asm __volatile("movl %0,%%dr6" : : "r" (sel));
 635 }
 636
 637 static __inline u_int
 638 rdr7(void)
 639 {
 640         u_int   data;
 641         __asm __volatile("movl %%dr7,%0" : "=r" (data));
 642         return (data);
 643 }
 644
 645 static __inline void
 646 load_dr7(u_int sel)
 647 {
 648         __asm __volatile("movl %0,%%dr7" : : "r" (sel));
 649 }
 650
 651 #else /* !__GNUC__ */
 652
 653 int     breakpoint      (void);
 654 u_int   bsfl            (u_int mask);
 655 u_int   bsrl            (u_int mask);
 656 void    cpu_disable_intr (void);
 657 void    do_cpuid        (u_int ax, u_int *p);
 658 void    cpu_enable_intr (void);
 659 u_char  inb             (u_int port);
 660 u_int   inl             (u_int port);
 661 void    insb            (u_int port, void *addr, size_t cnt);
 662 void    insl            (u_int port, void *addr, size_t cnt);
 663 void    insw            (u_int port, void *addr, size_t cnt);
 664 void    invd            (void);
 665 u_short inw             (u_int port);
 666 u_int   loadandclear    (u_int *addr);
 667 void    outb            (u_int port, u_char data);
 668 void    outl            (u_int port, u_int data);
 669 void    outsb           (u_int port, void *addr, size_t cnt);
 670 void    outsl           (u_int port, void *addr, size_t cnt);
 671 void    outsw           (u_int port, void *addr, size_t cnt);
 672 void    outw            (u_int port, u_short data);
 673 u_int   rcr2            (void);
 674 u_int64_t rdmsr         (u_int msr);
 675 u_int64_t rdpmc         (u_int pmc);
 676 u_int64_t rdtsc         (void);
 677 u_int   read_eflags     (void);
 678 void    wbinvd          (void);
 679 void    write_eflags    (u_int ef);
 680 void    wrmsr           (u_int msr, u_int64_t newval);
 681 u_int   rfs             (void);
 682 u_int   rgs             (void);
 683 void    load_fs         (u_int sel);
 684 void    load_gs         (u_int sel);
 685
 686 #endif  /* __GNUC__ */
 687
 688 void    load_cr0        (u_int cr0);
 689 void    load_cr3        (u_int cr3);
 690 void    load_cr4        (u_int cr4);
 691 void    ltr             (u_short sel);
 692 u_int   rcr0            (void);
 693 u_int   rcr3            (void);
 694 u_int   rcr4            (void);
 695 void    reset_dbregs    (void);
 696 __END_DECLS
 697
 698 #endif /* !_MACHINE_CPUFUNC_H_ */