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Add support for Broadcom BCM4401-B0.
[dragonfly/netmp.git] / sys / dev / netif / bfe / if_bfe.c
blob47706461b849009badcf35d14a89a3892cb1171d
1 /*
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
7 */
8
9 /*
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.18 2005/07/01 12:39:54 joerg Exp $
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
38 #include <sys/mbuf.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/thread2.h>
44
45 #include <net/if.h>
46 #include <net/ifq_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51
52 #include <net/bpf.h>
53
54 #include <net/if_types.h>
55 #include <net/vlan/if_vlan_var.h>
56
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60
61 #include <machine/bus_memio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
64 #include <sys/bus.h>
65 #include <sys/rman.h>
66
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
69 #include <bus/pci/pcidevs.h>
70
71 #include <dev/netif/mii_layer/mii.h>
72 #include <dev/netif/mii_layer/miivar.h>
73
74 #include "if_bfereg.h"
75
76 MODULE_DEPEND(bfe, pci, 1, 1, 1);
77 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
78
79 /* "controller miibus0" required. See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
83
84 static struct bfe_type bfe_devs[] = {
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
86 "Broadcom BCM4401 Fast Ethernet" },
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
88 "Broadcom BCM4401-B0 Fast Ethernet" },
89 { 0, 0, NULL }
90 };
91
92 static int bfe_probe(device_t);
93 static int bfe_attach(device_t);
94 static int bfe_detach(device_t);
95 static void bfe_release_resources(struct bfe_softc *);
96 static void bfe_intr(void *);
97 static void bfe_start(struct ifnet *);
98 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
99 static void bfe_init(void *);
100 static void bfe_stop(struct bfe_softc *);
101 static void bfe_watchdog(struct ifnet *);
102 static void bfe_shutdown(device_t);
103 static void bfe_tick(void *);
104 static void bfe_txeof(struct bfe_softc *);
105 static void bfe_rxeof(struct bfe_softc *);
106 static void bfe_set_rx_mode(struct bfe_softc *);
107 static int bfe_list_rx_init(struct bfe_softc *);
108 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
109 static void bfe_rx_ring_free(struct bfe_softc *);
110
111 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
112 static int bfe_ifmedia_upd(struct ifnet *);
113 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
114 static int bfe_miibus_readreg(device_t, int, int);
115 static int bfe_miibus_writereg(device_t, int, int, int);
116 static void bfe_miibus_statchg(device_t);
117 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
118 u_long, const int);
119 static void bfe_get_config(struct bfe_softc *sc);
120 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
121 static void bfe_stats_update(struct bfe_softc *);
122 static void bfe_clear_stats (struct bfe_softc *);
123 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
124 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
125 static int bfe_resetphy(struct bfe_softc *);
126 static int bfe_setupphy(struct bfe_softc *);
127 static void bfe_chip_reset(struct bfe_softc *);
128 static void bfe_chip_halt(struct bfe_softc *);
129 static void bfe_core_reset(struct bfe_softc *);
130 static void bfe_core_disable(struct bfe_softc *);
131 static int bfe_dma_alloc(device_t);
132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
134 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
135
136 static device_method_t bfe_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, bfe_probe),
139 DEVMETHOD(device_attach, bfe_attach),
140 DEVMETHOD(device_detach, bfe_detach),
141 DEVMETHOD(device_shutdown, bfe_shutdown),
142
143 /* bus interface */
144 DEVMETHOD(bus_print_child, bus_generic_print_child),
145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
146
147 /* MII interface */
148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
151
152 { 0, 0 }
153 };
154
155 static driver_t bfe_driver = {
156 "bfe",
157 bfe_methods,
158 sizeof(struct bfe_softc)
159 };
160
161 static devclass_t bfe_devclass;
162
163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
165
166 /*
167 * Probe for a Broadcom 4401 chip.
168 */
169 static int
170 bfe_probe(device_t dev)
171 {
172 struct bfe_type *t;
173 uint16_t vendor, product;
174
175 vendor = pci_get_vendor(dev);
176 product = pci_get_device(dev);
177
178 for (t = bfe_devs; t->bfe_name != NULL; t++) {
179 if (vendor == t->bfe_vid && product == t->bfe_did) {
180 device_set_desc_copy(dev, t->bfe_name);
181 return(0);
182 }
183 }
184
185 return(ENXIO);
186 }
187
188 static int
189 bfe_dma_alloc(device_t dev)
190 {
191 struct bfe_softc *sc;
192 int error, i;
193
194 sc = device_get_softc(dev);
195
196 /* parent tag */
197 error = bus_dma_tag_create(NULL, /* parent */
198 PAGE_SIZE, 0, /* alignment, boundary */
199 BUS_SPACE_MAXADDR, /* lowaddr */
200 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
201 NULL, NULL, /* filter, filterarg */
202 MAXBSIZE, /* maxsize */
203 BUS_SPACE_UNRESTRICTED, /* num of segments */
204 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
205 BUS_DMA_ALLOCNOW, /* flags */
206 &sc->bfe_parent_tag);
207
208 if (error) {
209 device_printf(dev, "could not allocate dma tag\n");
210 return(ENOMEM);
211 }
212
213
214 /* tag for TX ring */
215 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
216 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
217 NULL, NULL, BFE_TX_LIST_SIZE, 1,
218 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
219
220 if (error) {
221 device_printf(dev, "could not allocate dma tag\n");
222 return(ENOMEM);
223 }
224
225 /* tag for RX ring */
226 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
227 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
228 NULL, NULL, BFE_RX_LIST_SIZE, 1,
229 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
230
231 if (error) {
232 device_printf(dev, "could not allocate dma tag\n");
233 return(ENOMEM);
234 }
235
236 /* tag for mbufs */
237 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
238 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
239 1, BUS_SPACE_MAXSIZE_32BIT, 0,
240 &sc->bfe_tag);
241
242 if (error) {
243 device_printf(dev, "could not allocate dma tag\n");
244 return(ENOMEM);
245 }
246
247 /* pre allocate dmamaps for RX list */
248 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
249 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
250 if (error) {
251 device_printf(dev, "cannot create DMA map for RX\n");
252 return(ENOMEM);
253 }
254 }
255
256 /* pre allocate dmamaps for TX list */
257 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
258 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
259 if (error) {
260 device_printf(dev, "cannot create DMA map for TX\n");
261 return(ENOMEM);
262 }
263 }
264
265 /* Alloc dma for rx ring */
266 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
267 BUS_DMA_WAITOK, &sc->bfe_rx_map);
268
269 if (error)
270 return(ENOMEM);
271
272 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
273 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
274 sc->bfe_rx_list, sizeof(struct bfe_desc),
275 bfe_dma_map, &sc->bfe_rx_dma, 0);
276
277 if (error)
278 return(ENOMEM);
279
280 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
281
282 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
283 BUS_DMA_WAITOK, &sc->bfe_tx_map);
284 if (error)
285 return(ENOMEM);
286
287 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
288 sc->bfe_tx_list, sizeof(struct bfe_desc),
289 bfe_dma_map, &sc->bfe_tx_dma, 0);
290 if (error)
291 return(ENOMEM);
292
293 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
294 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
295
296 return(0);
297 }
298
299 static int
300 bfe_attach(device_t dev)
301 {
302 struct ifnet *ifp;
303 struct bfe_softc *sc;
304 int error = 0, rid;
305
306 sc = device_get_softc(dev);
307
308 sc->bfe_dev = dev;
309 callout_init(&sc->bfe_stat_timer);
310
311 /*
312 * Handle power management nonsense.
313 */
314 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
315 uint32_t membase, irq;
316
317 /* Save important PCI config data. */
318 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
319 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
320
321 /* Reset the power state. */
322 device_printf(dev, "chip is in D%d power mode"
323 " -- setting to D0\n", pci_get_powerstate(dev));
324
325 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
326
327 /* Restore PCI config data. */
328 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
329 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
330 }
331
332 /*
333 * Map control/status registers.
334 */
335 pci_enable_busmaster(dev);
336
337 rid = BFE_PCI_MEMLO;
338 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
339 RF_ACTIVE);
340 if (sc->bfe_res == NULL) {
341 device_printf(dev, "couldn't map memory\n");
342 error = ENXIO;
343 goto fail;
344 }
345
346 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
347 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
348
349 /* Allocate interrupt */
350 rid = 0;
351
352 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
353 RF_SHAREABLE | RF_ACTIVE);
354 if (sc->bfe_irq == NULL) {
355 device_printf(dev, "couldn't map interrupt\n");
356 error = ENXIO;
357 goto fail;
358 }
359
360 if (bfe_dma_alloc(dev)) {
361 device_printf(dev, "failed to allocate DMA resources\n");
362 bfe_release_resources(sc);
363 error = ENXIO;
364 goto fail;
365 }
366
367 /* Set up ifnet structure */
368 ifp = &sc->arpcom.ac_if;
369 ifp->if_softc = sc;
370 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
371 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
372 ifp->if_ioctl = bfe_ioctl;
373 ifp->if_start = bfe_start;
374 ifp->if_watchdog = bfe_watchdog;
375 ifp->if_init = bfe_init;
376 ifp->if_mtu = ETHERMTU;
377 ifp->if_baudrate = 10000000;
378 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
379 ifq_set_ready(&ifp->if_snd);
380
381 bfe_get_config(sc);
382
383 /* Reset the chip and turn on the PHY */
384 bfe_chip_reset(sc);
385
386 if (mii_phy_probe(dev, &sc->bfe_miibus,
387 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
388 device_printf(dev, "MII without any PHY!\n");
389 error = ENXIO;
390 goto fail;
391 }
392
393 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
394
395 /*
396 * Hook interrupt last to avoid having to lock softc
397 */
398 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
399 bfe_intr, sc, &sc->bfe_intrhand, NULL);
400
401 if (error) {
402 ether_ifdetach(ifp);
403 bfe_release_resources(sc);
404 device_printf(dev, "couldn't set up irq\n");
405 goto fail;
406 }
407 fail:
408 if (error)
409 bfe_release_resources(sc);
410 return(error);
411 }
412
413 static int
414 bfe_detach(device_t dev)
415 {
416 struct bfe_softc *sc = device_get_softc(dev);
417 struct ifnet *ifp = &sc->arpcom.ac_if;
418
419 crit_enter();
420
421 if (device_is_attached(dev)) {
422 bfe_stop(sc);
423 ether_ifdetach(ifp);
424 }
425
426 bfe_chip_reset(sc);
427
428 if (sc->bfe_miibus != NULL)
429 device_delete_child(dev, sc->bfe_miibus);
430 bus_generic_detach(dev);
431
432 bfe_release_resources(sc);
433
434 crit_exit();
435
436 return(0);
437 }
438
439 /*
440 * Stop all chip I/O so that the kernel's probe routines don't
441 * get confused by errant DMAs when rebooting.
442 */
443 static void
444 bfe_shutdown(device_t dev)
445 {
446 struct bfe_softc *sc = device_get_softc(dev);
447
448 crit_enter();
449
450 bfe_stop(sc);
451
452 crit_exit();
453 }
454
455 static int
456 bfe_miibus_readreg(device_t dev, int phy, int reg)
457 {
458 struct bfe_softc *sc;
459 uint32_t ret;
460
461 sc = device_get_softc(dev);
462 if (phy != sc->bfe_phyaddr)
463 return(0);
464 bfe_readphy(sc, reg, &ret);
465
466 return(ret);
467 }
468
469 static int
470 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
471 {
472 struct bfe_softc *sc;
473
474 sc = device_get_softc(dev);
475 if (phy != sc->bfe_phyaddr)
476 return(0);
477 bfe_writephy(sc, reg, val);
478
479 return(0);
480 }
481
482 static void
483 bfe_miibus_statchg(device_t dev)
484 {
485 return;
486 }
487
488 static void
489 bfe_tx_ring_free(struct bfe_softc *sc)
490 {
491 int i;
492
493 for (i = 0; i < BFE_TX_LIST_CNT; i++)
494 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
495 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
496 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
497 bus_dmamap_unload(sc->bfe_tag,
498 sc->bfe_tx_ring[i].bfe_map);
499 bus_dmamap_destroy(sc->bfe_tag,
500 sc->bfe_tx_ring[i].bfe_map);
501 }
502 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
503 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
504 }
505
506 static void
507 bfe_rx_ring_free(struct bfe_softc *sc)
508 {
509 int i;
510
511 for (i = 0; i < BFE_RX_LIST_CNT; i++)
512 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
513 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
514 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
515 bus_dmamap_unload(sc->bfe_tag,
516 sc->bfe_rx_ring[i].bfe_map);
517 bus_dmamap_destroy(sc->bfe_tag,
518 sc->bfe_rx_ring[i].bfe_map);
519 }
520 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
521 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
522 }
523
524
525 static int
526 bfe_list_rx_init(struct bfe_softc *sc)
527 {
528 int i;
529
530 for (i = 0; i < BFE_RX_LIST_CNT; i++)
531 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
532 return(ENOBUFS);
533
534 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
535 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
536
537 sc->bfe_rx_cons = 0;
538
539 return(0);
540 }
541
542 static int
543 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
544 {
545 struct bfe_rxheader *rx_header;
546 struct bfe_desc *d;
547 struct bfe_data *r;
548 uint32_t ctrl;
549
550 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
551 return(EINVAL);
552
553 if (m == NULL) {
554 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
555 if (m == NULL)
556 return(ENOBUFS);
557 m->m_len = m->m_pkthdr.len = MCLBYTES;
558 }
559 else
560 m->m_data = m->m_ext.ext_buf;
561
562 rx_header = mtod(m, struct bfe_rxheader *);
563 rx_header->len = 0;
564 rx_header->flags = 0;
565
566 /* Map the mbuf into DMA */
567 sc->bfe_rx_cnt = c;
568 d = &sc->bfe_rx_list[c];
569 r = &sc->bfe_rx_ring[c];
570 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
571 MCLBYTES, bfe_dma_map_desc, d, 0);
572 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
573
574 ctrl = ETHER_MAX_LEN + 32;
575
576 if(c == BFE_RX_LIST_CNT - 1)
577 ctrl |= BFE_DESC_EOT;
578
579 d->bfe_ctrl = ctrl;
580 r->bfe_mbuf = m;
581 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
582 return(0);
583 }
584
585 static void
586 bfe_get_config(struct bfe_softc *sc)
587 {
588 uint8_t eeprom[128];
589
590 bfe_read_eeprom(sc, eeprom);
591
592 sc->arpcom.ac_enaddr[0] = eeprom[79];
593 sc->arpcom.ac_enaddr[1] = eeprom[78];
594 sc->arpcom.ac_enaddr[2] = eeprom[81];
595 sc->arpcom.ac_enaddr[3] = eeprom[80];
596 sc->arpcom.ac_enaddr[4] = eeprom[83];
597 sc->arpcom.ac_enaddr[5] = eeprom[82];
598
599 sc->bfe_phyaddr = eeprom[90] & 0x1f;
600 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
601
602 sc->bfe_core_unit = 0;
603 sc->bfe_dma_offset = BFE_PCI_DMA;
604 }
605
606 static void
607 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
608 {
609 uint32_t bar_orig, pci_rev, val;
610
611 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
612 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
613 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
614
615 val = CSR_READ_4(sc, BFE_SBINTVEC);
616 val |= cores;
617 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
618
619 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
620 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
621 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
622
623 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
624 }
625
626 static void
627 bfe_clear_stats(struct bfe_softc *sc)
628 {
629 u_long reg;
630
631 crit_enter();
632
633 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
634 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
635 CSR_READ_4(sc, reg);
636 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
637 CSR_READ_4(sc, reg);
638
639 crit_exit();
640 }
641
642 static int
643 bfe_resetphy(struct bfe_softc *sc)
644 {
645 uint32_t val;
646
647 crit_enter();
648
649 bfe_writephy(sc, 0, BMCR_RESET);
650 DELAY(100);
651 bfe_readphy(sc, 0, &val);
652 if (val & BMCR_RESET) {
653 crit_exit();
654 if_printf(&sc->arpcom.ac_if,
655 "PHY Reset would not complete.\n");
656 return(ENXIO);
657 }
658
659 crit_exit();
660 return(0);
661 }
662
663 static void
664 bfe_chip_halt(struct bfe_softc *sc)
665 {
666 crit_enter();
667
668 /* disable interrupts - not that it actually does..*/
669 CSR_WRITE_4(sc, BFE_IMASK, 0);
670 CSR_READ_4(sc, BFE_IMASK);
671
672 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
673 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
674
675 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
676 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
677 DELAY(10);
678
679 crit_exit();
680 }
681
682 static void
683 bfe_chip_reset(struct bfe_softc *sc)
684 {
685 uint32_t val;
686
687 crit_enter();
688
689 /* Set the interrupt vector for the enet core */
690 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
691
692 /* is core up? */
693 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
694 if (val == BFE_CLOCK) {
695 /* It is, so shut it down */
696 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
697 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
698 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
699 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
700 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
701 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
702 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
703 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
704 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
705 }
706
707 bfe_core_reset(sc);
708 bfe_clear_stats(sc);
709
710 /*
711 * We want the phy registers to be accessible even when
712 * the driver is "downed" so initialize MDC preamble, frequency,
713 * and whether internal or external phy here.
714 */
715
716 /* 4402 has 62.5Mhz SB clock and internal phy */
717 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
718
719 /* Internal or external PHY? */
720 val = CSR_READ_4(sc, BFE_DEVCTRL);
721 if (!(val & BFE_IPP))
722 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
723 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
724 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
725 DELAY(100);
726 }
727
728 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
729 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
730 BFE_LAZY_FC_MASK));
731
732 /*
733 * We don't want lazy interrupts, so just send them at the end of a
734 * frame, please
735 */
736 BFE_OR(sc, BFE_RCV_LAZY, 0);
737
738 /* Set max lengths, accounting for VLAN tags */
739 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
740 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
741
742 /* Set watermark XXX - magic */
743 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
744
745 /*
746 * Initialise DMA channels - not forgetting dma addresses need to be
747 * added to BFE_PCI_DMA
748 */
749 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
750 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
751
752 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
753 BFE_RX_CTRL_ENABLE);
754 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
755
756 bfe_resetphy(sc);
757 bfe_setupphy(sc);
758
759 crit_exit();
760 }
761
762 static void
763 bfe_core_disable(struct bfe_softc *sc)
764 {
765 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
766 return;
767
768 /*
769 * Set reject, wait for it set, then wait for the core to stop being busy
770 * Then set reset and reject and enable the clocks
771 */
772 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
773 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
774 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
775 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
776 BFE_RESET));
777 CSR_READ_4(sc, BFE_SBTMSLOW);
778 DELAY(10);
779 /* Leave reset and reject set */
780 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
781 DELAY(10);
782 }
783
784 static void
785 bfe_core_reset(struct bfe_softc *sc)
786 {
787 uint32_t val;
788
789 /* Disable the core */
790 bfe_core_disable(sc);
791
792 /* and bring it back up */
793 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
794 CSR_READ_4(sc, BFE_SBTMSLOW);
795 DELAY(10);
796
797 /* Chip bug, clear SERR, IB and TO if they are set. */
798 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
799 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
800 val = CSR_READ_4(sc, BFE_SBIMSTATE);
801 if (val & (BFE_IBE | BFE_TO))
802 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
803
804 /* Clear reset and allow it to move through the core */
805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
806 CSR_READ_4(sc, BFE_SBTMSLOW);
807 DELAY(10);
808
809 /* Leave the clock set */
810 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
811 CSR_READ_4(sc, BFE_SBTMSLOW);
812 DELAY(10);
813 }
814
815 static void
816 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
817 {
818 uint32_t val;
819
820 val = ((uint32_t) data[2]) << 24;
821 val |= ((uint32_t) data[3]) << 16;
822 val |= ((uint32_t) data[4]) << 8;
823 val |= ((uint32_t) data[5]);
824 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
825 val = (BFE_CAM_HI_VALID |
826 (((uint32_t) data[0]) << 8) |
827 (((uint32_t) data[1])));
828 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
829 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
830 (index << BFE_CAM_INDEX_SHIFT)));
831 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
832 }
833
834 static void
835 bfe_set_rx_mode(struct bfe_softc *sc)
836 {
837 struct ifnet *ifp = &sc->arpcom.ac_if;
838 uint32_t val;
839 int i = 0;
840
841 val = CSR_READ_4(sc, BFE_RXCONF);
842
843 if (ifp->if_flags & IFF_PROMISC)
844 val |= BFE_RXCONF_PROMISC;
845 else
846 val &= ~BFE_RXCONF_PROMISC;
847
848 if (ifp->if_flags & IFF_BROADCAST)
849 val &= ~BFE_RXCONF_DBCAST;
850 else
851 val |= BFE_RXCONF_DBCAST;
852
853
854 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
855 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
856
857 CSR_WRITE_4(sc, BFE_RXCONF, val);
858 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
859 }
860
861 static void
862 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
863 {
864 uint32_t *ptr;
865
866 ptr = arg;
867 *ptr = segs->ds_addr;
868 }
869
870 static void
871 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
872 {
873 struct bfe_desc *d;
874
875 d = arg;
876 /* The chip needs all addresses to be added to BFE_PCI_DMA */
877 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
878 }
879
880 static void
881 bfe_release_resources(struct bfe_softc *sc)
882 {
883 device_t dev;
884 int i;
885
886 dev = sc->bfe_dev;
887
888 if (sc->bfe_intrhand != NULL)
889 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
890
891 if (sc->bfe_irq != NULL)
892 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
893
894 if (sc->bfe_res != NULL)
895 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
896
897 if (sc->bfe_tx_tag != NULL) {
898 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
899 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
900 bus_dma_tag_destroy(sc->bfe_tx_tag);
901 sc->bfe_tx_tag = NULL;
902 }
903
904 if (sc->bfe_rx_tag != NULL) {
905 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
906 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
907 bus_dma_tag_destroy(sc->bfe_rx_tag);
908 sc->bfe_rx_tag = NULL;
909 }
910
911 if (sc->bfe_tag != NULL) {
912 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
913 bus_dmamap_destroy(sc->bfe_tag,
914 sc->bfe_tx_ring[i].bfe_map);
915 }
916 bus_dma_tag_destroy(sc->bfe_tag);
917 sc->bfe_tag = NULL;
918 }
919
920 if (sc->bfe_parent_tag != NULL)
921 bus_dma_tag_destroy(sc->bfe_parent_tag);
922 }
923
924 static void
925 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
926 {
927 long i;
928 uint16_t *ptr = (uint16_t *)data;
929
930 for (i = 0; i < 128; i += 2)
931 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
932 }
933
934 static int
935 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
936 u_long timeout, const int clear)
937 {
938 u_long i;
939
940 for (i = 0; i < timeout; i++) {
941 uint32_t val = CSR_READ_4(sc, reg);
942
943 if (clear && !(val & bit))
944 break;
945 if (!clear && (val & bit))
946 break;
947 DELAY(10);
948 }
949 if (i == timeout) {
950 if_printf(&sc->arpcom.ac_if,
951 "BUG! Timeout waiting for bit %08x of register "
952 "%x to %s.\n", bit, reg,
953 (clear ? "clear" : "set"));
954 return -1;
955 }
956 return 0;
957 }
958
959 static int
960 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
961 {
962 int err;
963
964 crit_enter();
965
966 /* Clear MII ISR */
967 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
968 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
969 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
970 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
971 (reg << BFE_MDIO_RA_SHIFT) |
972 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
973 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
974 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
975
976 crit_exit();
977 return(err);
978 }
979
980 static int
981 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
982 {
983 int status;
984
985 crit_enter();
986
987 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
988 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
989 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
990 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
991 (reg << BFE_MDIO_RA_SHIFT) |
992 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
993 (val & BFE_MDIO_DATA_DATA)));
994 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
995
996 crit_exit();
997
998 return status;
999 }
1000
1001 /*
1002 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1003 * twice
1004 */
1005 static int
1006 bfe_setupphy(struct bfe_softc *sc)
1007 {
1008 uint32_t val;
1009
1010 crit_enter();
1011
1012 /* Enable activity LED */
1013 bfe_readphy(sc, 26, &val);
1014 bfe_writephy(sc, 26, val & 0x7fff);
1015 bfe_readphy(sc, 26, &val);
1016
1017 /* Enable traffic meter LED mode */
1018 bfe_readphy(sc, 27, &val);
1019 bfe_writephy(sc, 27, val | (1 << 6));
1020
1021 crit_exit();
1022 return(0);
1023 }
1024
1025 static void
1026 bfe_stats_update(struct bfe_softc *sc)
1027 {
1028 u_long reg;
1029 uint32_t *val;
1030
1031 val = &sc->bfe_hwstats.tx_good_octets;
1032 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1033 *val++ += CSR_READ_4(sc, reg);
1034 val = &sc->bfe_hwstats.rx_good_octets;
1035 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1036 *val++ += CSR_READ_4(sc, reg);
1037 }
1038
1039 static void
1040 bfe_txeof(struct bfe_softc *sc)
1041 {
1042 struct ifnet *ifp = &sc->arpcom.ac_if;
1043 uint32_t i, chipidx;
1044
1045 crit_enter();
1046
1047 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1048 chipidx /= sizeof(struct bfe_desc);
1049
1050 i = sc->bfe_tx_cons;
1051 /* Go through the mbufs and free those that have been transmitted */
1052 while (i != chipidx) {
1053 struct bfe_data *r = &sc->bfe_tx_ring[i];
1054 if (r->bfe_mbuf != NULL) {
1055 ifp->if_opackets++;
1056 m_freem(r->bfe_mbuf);
1057 r->bfe_mbuf = NULL;
1058 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1059 }
1060 sc->bfe_tx_cnt--;
1061 BFE_INC(i, BFE_TX_LIST_CNT);
1062 }
1063
1064 if (i != sc->bfe_tx_cons) {
1065 /* we freed up some mbufs */
1066 sc->bfe_tx_cons = i;
1067 ifp->if_flags &= ~IFF_OACTIVE;
1068 }
1069 if (sc->bfe_tx_cnt == 0)
1070 ifp->if_timer = 0;
1071 else
1072 ifp->if_timer = 5;
1073
1074 crit_exit();
1075 }
1076
1077 /* Pass a received packet up the stack */
1078 static void
1079 bfe_rxeof(struct bfe_softc *sc)
1080 {
1081 struct ifnet *ifp = &sc->arpcom.ac_if;
1082 struct mbuf *m;
1083 struct bfe_rxheader *rxheader;
1084 struct bfe_data *r;
1085 uint32_t cons, status, current, len, flags;
1086
1087 crit_enter();
1088
1089 cons = sc->bfe_rx_cons;
1090 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1091 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1092
1093 while (current != cons) {
1094 r = &sc->bfe_rx_ring[cons];
1095 m = r->bfe_mbuf;
1096 rxheader = mtod(m, struct bfe_rxheader*);
1097 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1098 len = rxheader->len;
1099 r->bfe_mbuf = NULL;
1100
1101 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1102 flags = rxheader->flags;
1103
1104 len -= ETHER_CRC_LEN;
1105
1106 /* flag an error and try again */
1107 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1108 ifp->if_ierrors++;
1109 if (flags & BFE_RX_FLAG_SERR)
1110 ifp->if_collisions++;
1111 bfe_list_newbuf(sc, cons, m);
1112 BFE_INC(cons, BFE_RX_LIST_CNT);
1113 continue;
1114 }
1115
1116 /* Go past the rx header */
1117 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1118 bfe_list_newbuf(sc, cons, m);
1119 BFE_INC(cons, BFE_RX_LIST_CNT);
1120 ifp->if_ierrors++;
1121 continue;
1122 }
1123
1124 m_adj(m, BFE_RX_OFFSET);
1125 m->m_len = m->m_pkthdr.len = len;
1126
1127 ifp->if_ipackets++;
1128 m->m_pkthdr.rcvif = ifp;
1129
1130 (*ifp->if_input)(ifp, m);
1131 BFE_INC(cons, BFE_RX_LIST_CNT);
1132 }
1133 sc->bfe_rx_cons = cons;
1134
1135 crit_exit();
1136 }
1137
1138 static void
1139 bfe_intr(void *xsc)
1140 {
1141 struct bfe_softc *sc = xsc;
1142 struct ifnet *ifp = &sc->arpcom.ac_if;
1143 uint32_t istat, imask, flag;
1144
1145 crit_enter();
1146
1147 istat = CSR_READ_4(sc, BFE_ISTAT);
1148 imask = CSR_READ_4(sc, BFE_IMASK);
1149
1150 /*
1151 * Defer unsolicited interrupts - This is necessary because setting the
1152 * chips interrupt mask register to 0 doesn't actually stop the
1153 * interrupts
1154 */
1155 istat &= imask;
1156 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1157 CSR_READ_4(sc, BFE_ISTAT);
1158
1159 /* not expecting this interrupt, disregard it */
1160 if (istat == 0) {
1161 crit_exit();
1162 return;
1163 }
1164
1165 if (istat & BFE_ISTAT_ERRORS) {
1166 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1167 if (flag & BFE_STAT_EMASK)
1168 ifp->if_oerrors++;
1169
1170 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1171 if (flag & BFE_RX_FLAG_ERRORS)
1172 ifp->if_ierrors++;
1173
1174 ifp->if_flags &= ~IFF_RUNNING;
1175 bfe_init(sc);
1176 }
1177
1178 /* A packet was received */
1179 if (istat & BFE_ISTAT_RX)
1180 bfe_rxeof(sc);
1181
1182 /* A packet was sent */
1183 if (istat & BFE_ISTAT_TX)
1184 bfe_txeof(sc);
1185
1186 /* We have packets pending, fire them out */
1187 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1188 bfe_start(ifp);
1189
1190 crit_exit();
1191 }
1192
1193 static int
1194 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1195 {
1196 struct bfe_desc *d = NULL;
1197 struct bfe_data *r = NULL;
1198 struct mbuf *m;
1199 uint32_t frag, cur, cnt = 0;
1200
1201 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1202 return(ENOBUFS);
1203
1204 /*
1205 * Start packing the mbufs in this chain into
1206 * the fragment pointers. Stop when we run out
1207 * of fragments or hit the end of the mbuf chain.
1208 */
1209 m = m_head;
1210 cur = frag = *txidx;
1211 cnt = 0;
1212
1213 for (m = m_head; m != NULL; m = m->m_next) {
1214 if (m->m_len != 0) {
1215 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1216 return(ENOBUFS);
1217
1218 d = &sc->bfe_tx_list[cur];
1219 r = &sc->bfe_tx_ring[cur];
1220 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1221 /* always intterupt on completion */
1222 d->bfe_ctrl |= BFE_DESC_IOC;
1223 if (cnt == 0)
1224 /* Set start of frame */
1225 d->bfe_ctrl |= BFE_DESC_SOF;
1226 if (cur == BFE_TX_LIST_CNT - 1)
1227 /*
1228 * Tell the chip to wrap to the start of the
1229 *descriptor list
1230 */
1231 d->bfe_ctrl |= BFE_DESC_EOT;
1232
1233 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1234 m->m_len, bfe_dma_map_desc, d, 0);
1235 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1236 BUS_DMASYNC_PREREAD);
1237
1238 frag = cur;
1239 BFE_INC(cur, BFE_TX_LIST_CNT);
1240 cnt++;
1241 }
1242 }
1243
1244 if (m != NULL)
1245 return(ENOBUFS);
1246
1247 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1248 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1249 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1250
1251 *txidx = cur;
1252 sc->bfe_tx_cnt += cnt;
1253 return(0);
1254 }
1255
1256 /*
1257 * Set up to transmit a packet
1258 */
1259 static void
1260 bfe_start(struct ifnet *ifp)
1261 {
1262 struct bfe_softc *sc = ifp->if_softc;
1263 struct mbuf *m_head = NULL;
1264 int idx;
1265
1266 crit_enter();
1267
1268 /*
1269 * not much point trying to send if the link is down or we have nothing to
1270 * send
1271 */
1272 if (!sc->bfe_link) {
1273 crit_exit();
1274 return;
1275 }
1276
1277 if (ifp->if_flags & IFF_OACTIVE) {
1278 crit_exit();
1279 return;
1280 }
1281
1282 idx = sc->bfe_tx_prod;
1283
1284 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1285 m_head = ifq_poll(&ifp->if_snd);
1286 if (m_head == NULL)
1287 break;
1288
1289 /*
1290 * Pack the data into the tx ring. If we dont have enough room, let
1291 * the chip drain the ring
1292 */
1293 if (bfe_encap(sc, m_head, &idx)) {
1294 ifp->if_flags |= IFF_OACTIVE;
1295 break;
1296 }
1297 m_head = ifq_dequeue(&ifp->if_snd);
1298
1299 /*
1300 * If there's a BPF listener, bounce a copy of this frame
1301 * to him.
1302 */
1303 BPF_MTAP(ifp, m_head);
1304 }
1305
1306 sc->bfe_tx_prod = idx;
1307 /* Transmit - twice due to apparent hardware bug */
1308 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1309 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1310
1311 /*
1312 * Set a timeout in case the chip goes out to lunch.
1313 */
1314 ifp->if_timer = 5;
1315
1316 crit_exit();
1317 }
1318
1319 static void
1320 bfe_init(void *xsc)
1321 {
1322 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1323 struct ifnet *ifp = &sc->arpcom.ac_if;
1324
1325 crit_enter();
1326
1327 if (ifp->if_flags & IFF_RUNNING) {
1328 crit_exit();
1329 return;
1330 }
1331
1332 bfe_stop(sc);
1333 bfe_chip_reset(sc);
1334
1335 if (bfe_list_rx_init(sc) == ENOBUFS) {
1336 if_printf(ifp, "bfe_init failed. "
1337 " Not enough memory for list buffers\n");
1338 bfe_stop(sc);
1339 crit_exit();
1340 return;
1341 }
1342
1343 bfe_set_rx_mode(sc);
1344
1345 /* Enable the chip and core */
1346 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1347 /* Enable interrupts */
1348 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1349
1350 bfe_ifmedia_upd(ifp);
1351 ifp->if_flags |= IFF_RUNNING;
1352 ifp->if_flags &= ~IFF_OACTIVE;
1353
1354 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1355 crit_exit();
1356 }
1357
1358 /*
1359 * Set media options.
1360 */
1361 static int
1362 bfe_ifmedia_upd(struct ifnet *ifp)
1363 {
1364 struct bfe_softc *sc = ifp->if_softc;
1365 struct mii_data *mii;
1366
1367 crit_enter();
1368
1369 mii = device_get_softc(sc->bfe_miibus);
1370 sc->bfe_link = 0;
1371 if (mii->mii_instance) {
1372 struct mii_softc *miisc;
1373 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1374 miisc = LIST_NEXT(miisc, mii_list))
1375 mii_phy_reset(miisc);
1376 }
1377 mii_mediachg(mii);
1378
1379 crit_exit();
1380 return(0);
1381 }
1382
1383 /*
1384 * Report current media status.
1385 */
1386 static void
1387 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1388 {
1389 struct bfe_softc *sc = ifp->if_softc;
1390 struct mii_data *mii;
1391
1392 crit_enter();
1393
1394 mii = device_get_softc(sc->bfe_miibus);
1395 mii_pollstat(mii);
1396 ifmr->ifm_active = mii->mii_media_active;
1397 ifmr->ifm_status = mii->mii_media_status;
1398
1399 crit_exit();
1400 }
1401
1402 static int
1403 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1404 {
1405 struct bfe_softc *sc = ifp->if_softc;
1406 struct ifreq *ifr = (struct ifreq *) data;
1407 struct mii_data *mii;
1408 int error = 0;
1409
1410 crit_enter();
1411
1412 switch (command) {
1413 case SIOCSIFFLAGS:
1414 if (ifp->if_flags & IFF_UP)
1415 if (ifp->if_flags & IFF_RUNNING)
1416 bfe_set_rx_mode(sc);
1417 else
1418 bfe_init(sc);
1419 else if (ifp->if_flags & IFF_RUNNING)
1420 bfe_stop(sc);
1421 break;
1422 case SIOCADDMULTI:
1423 case SIOCDELMULTI:
1424 if (ifp->if_flags & IFF_RUNNING)
1425 bfe_set_rx_mode(sc);
1426 break;
1427 case SIOCGIFMEDIA:
1428 case SIOCSIFMEDIA:
1429 mii = device_get_softc(sc->bfe_miibus);
1430 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1431 command);
1432 break;
1433 default:
1434 error = ether_ioctl(ifp, command, data);
1435 break;
1436 }
1437
1438 crit_exit();
1439
1440 return error;
1441 }
1442
1443 static void
1444 bfe_watchdog(struct ifnet *ifp)
1445 {
1446 struct bfe_softc *sc = ifp->if_softc;
1447
1448 if_printf(ifp, "watchdog timeout -- resetting\n");
1449
1450 crit_enter();
1451
1452 ifp->if_flags &= ~IFF_RUNNING;
1453 bfe_init(sc);
1454
1455 ifp->if_oerrors++;
1456
1457 crit_exit();
1458 }
1459
1460 static void
1461 bfe_tick(void *xsc)
1462 {
1463 struct bfe_softc *sc = xsc;
1464 struct mii_data *mii;
1465
1466 crit_enter();
1467
1468 mii = device_get_softc(sc->bfe_miibus);
1469
1470 bfe_stats_update(sc);
1471 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1472
1473 if (sc->bfe_link) {
1474 crit_exit();
1475 return;
1476 }
1477
1478 mii_tick(mii);
1479 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1480 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1481 sc->bfe_link++;
1482
1483 if (!sc->bfe_link)
1484 sc->bfe_link++;
1485
1486 crit_exit();
1487 }
1488
1489 /*
1490 * Stop the adapter and free any mbufs allocated to the
1491 * RX and TX lists.
1492 */
1493 static void
1494 bfe_stop(struct bfe_softc *sc)
1495 {
1496 struct ifnet *ifp = &sc->arpcom.ac_if;
1497
1498 crit_enter();
1499
1500 callout_stop(&sc->bfe_stat_timer);
1501
1502 bfe_chip_halt(sc);
1503 bfe_tx_ring_free(sc);
1504 bfe_rx_ring_free(sc);
1505
1506 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1507
1508 crit_exit();
1509 }
MP support for (parts of) the network stack