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10Base-TX -> 10Base-T and 1000Base-TX -> 1000Base-T. Although 1000Base-TX
[dragonfly/netmp.git] / sys / dev / netif / mii_layer / brgphy.c
blobf23de00e46a01d1b44c57d3bce7d14fc70934b58
1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
2
3 /*
4 * Copyright (c) 2000
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.20 2008/03/16 15:50:22 hasso Exp $
36 */
37
38 /*
39 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always
40 * 1000mbps; all we need to negotiate here is full or half duplex.
41 */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/socket.h>
47 #include <sys/bus.h>
48 #include <sys/sysctl.h>
49
50 #include <net/ethernet.h>
51 #include <net/if.h>
52 #include <net/if_media.h>
53 #include <net/if_arp.h>
54
55 #include "mii.h"
56 #include "miivar.h"
57 #include "miidevs.h"
58
59 #include "brgphyreg.h"
60 #include <dev/netif/bge/if_bgereg.h>
61
62 #include "miibus_if.h"
63
64 static int brgphy_probe(device_t);
65 static int brgphy_attach(device_t);
66
67 static const struct mii_phydesc brgphys[] = {
68 MII_PHYDESC(xxBROADCOM, BCM5400),
69 MII_PHYDESC(xxBROADCOM, BCM5401),
70 MII_PHYDESC(xxBROADCOM, BCM5411),
71 MII_PHYDESC(xxBROADCOM, BCM5421),
72 MII_PHYDESC(xxBROADCOM, BCM54K2),
73 MII_PHYDESC(xxBROADCOM, BCM5462),
74
75 MII_PHYDESC(xxBROADCOM, BCM5701),
76 MII_PHYDESC(xxBROADCOM, BCM5703),
77 MII_PHYDESC(xxBROADCOM, BCM5704),
78 MII_PHYDESC(xxBROADCOM, BCM5705),
79
80 MII_PHYDESC(xxBROADCOM, BCM5714),
81 MII_PHYDESC(xxBROADCOM, BCM5750),
82 MII_PHYDESC(xxBROADCOM, BCM5752),
83 MII_PHYDESC(xxBROADCOM2,BCM5755),
84 MII_PHYDESC(xxBROADCOM, BCM5780),
85 MII_PHYDESC(xxBROADCOM2,BCM5787),
86
87 MII_PHYDESC(xxBROADCOM, BCM5706C),
88 MII_PHYDESC(xxBROADCOM, BCM5708C),
89
90 MII_PHYDESC_NULL
91 };
92
93 static device_method_t brgphy_methods[] = {
94 /* device interface */
95 DEVMETHOD(device_probe, brgphy_probe),
96 DEVMETHOD(device_attach, brgphy_attach),
97 DEVMETHOD(device_detach, ukphy_detach),
98 DEVMETHOD(device_shutdown, bus_generic_shutdown),
99 { 0, 0 }
100 };
101
102 static devclass_t brgphy_devclass;
103
104 static driver_t brgphy_driver = {
105 "brgphy",
106 brgphy_methods,
107 sizeof(struct mii_softc)
108 };
109
110 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0);
111
112 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
113 static void brgphy_status(struct mii_softc *);
114 static void brgphy_mii_phy_auto(struct mii_softc *);
115 static void brgphy_reset(struct mii_softc *);
116 static void brgphy_loop(struct mii_softc *);
117
118 static void brgphy_bcm5401_dspcode(struct mii_softc *);
119 static void brgphy_bcm5411_dspcode(struct mii_softc *);
120 static void brgphy_bcm5421_dspcode(struct mii_softc *);
121 static void brgphy_bcm54k2_dspcode(struct mii_softc *);
122
123 static void brgphy_adc_bug(struct mii_softc *);
124 static void brgphy_5704_a0_bug(struct mii_softc *);
125 static void brgphy_ber_bug(struct mii_softc *);
126 static void brgphy_crc_bug(struct mii_softc *);
127
128 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
129 static void brgphy_eth_wirespeed(struct mii_softc *);
130
131 static int
132 brgphy_probe(device_t dev)
133 {
134 struct mii_attach_args *ma = device_get_ivars(dev);
135 const struct mii_phydesc *mpd;
136
137 mpd = mii_phy_match(ma, brgphys);
138 if (mpd != NULL) {
139 device_set_desc(dev, mpd->mpd_name);
140 return (0);
141 }
142 return(ENXIO);
143 }
144
145 static int
146 brgphy_attach(device_t dev)
147 {
148 struct mii_softc *sc;
149 struct mii_attach_args *ma;
150 struct mii_data *mii;
151
152 sc = device_get_softc(dev);
153 ma = device_get_ivars(dev);
154 mii_softc_init(sc, ma);
155 sc->mii_dev = device_get_parent(dev);
156 mii = device_get_softc(sc->mii_dev);
157 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
158
159 sc->mii_inst = mii->mii_instance;
160 sc->mii_service = brgphy_service;
161 sc->mii_reset = brgphy_reset;
162 sc->mii_pdata = mii;
163
164 sc->mii_flags |= MIIF_NOISOLATE;
165 mii->mii_instance++;
166
167 brgphy_reset(sc);
168
169 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
170
171 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
172 MII_MEDIA_NONE);
173 #if 0
174 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
175 MII_MEDIA_100_TX);
176 #endif
177
178 #undef ADD
179
180 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
181 if (sc->mii_capabilities & BMSR_EXTSTAT)
182 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
183
184 device_printf(dev, " ");
185 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
186 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
187 mii_phy_add_media(sc);
188 else
189 kprintf("no media present");
190 kprintf("\n");
191
192 MIIBUS_MEDIAINIT(sc->mii_dev);
193 return(0);
194 }
195
196 static int
197 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
198 {
199 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
200 int reg, speed, gig;
201
202 switch (cmd) {
203 case MII_POLLSTAT:
204 /*
205 * If we're not polling our PHY instance, just return.
206 */
207 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
208 return (0);
209 break;
210
211 case MII_MEDIACHG:
212 /*
213 * If the media indicates a different PHY instance,
214 * isolate ourselves.
215 */
216 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
217 reg = PHY_READ(sc, MII_BMCR);
218 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
219 return (0);
220 }
221
222 /*
223 * If the interface is not up, don't do anything.
224 */
225 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
226 break;
227
228 brgphy_reset(sc); /* XXX hardware bug work-around */
229
230 switch (IFM_SUBTYPE(ife->ifm_media)) {
231 case IFM_AUTO:
232 #ifdef foo
233 /*
234 * If we're already in auto mode, just return.
235 */
236 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
237 return (0);
238 #endif
239 brgphy_mii_phy_auto(sc);
240 break;
241 case IFM_1000_T:
242 speed = BRGPHY_S1000;
243 goto setit;
244 case IFM_100_TX:
245 speed = BRGPHY_S100;
246 goto setit;
247 case IFM_10_T:
248 speed = BRGPHY_S10;
249 setit:
250 brgphy_loop(sc);
251 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
252 speed |= BRGPHY_BMCR_FDX;
253 gig = BRGPHY_1000CTL_AFD;
254 } else {
255 gig = BRGPHY_1000CTL_AHD;
256 }
257
258 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
259 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
260 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
261
262 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
263 break;
264
265 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
266 PHY_WRITE(sc, BRGPHY_MII_BMCR,
267 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
268
269 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
270 break;
271
272 /*
273 * When settning the link manually, one side must
274 * be the master and the other the slave. However
275 * ifmedia doesn't give us a good way to specify
276 * this, so we fake it by using one of the LINK
277 * flags. If LINK0 is set, we program the PHY to
278 * be a master, otherwise it's a slave.
279 */
280 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
281 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
282 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
283 } else {
284 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
285 gig|BRGPHY_1000CTL_MSE);
286 }
287 break;
288 #ifdef foo
289 case IFM_NONE:
290 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
291 break;
292 #endif
293 case IFM_100_T4:
294 default:
295 return (EINVAL);
296 }
297 break;
298
299 case MII_TICK:
300 /*
301 * If we're not currently selected, just return.
302 */
303 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
304 return (0);
305
306 /*
307 * Is the interface even up?
308 */
309 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
310 return (0);
311
312 /*
313 * Only used for autonegotiation.
314 */
315 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
316 break;
317
318 /*
319 * Check to see if we have link. If we do, we don't
320 * need to restart the autonegotiation process. Read
321 * the BMSR twice in case it's latched.
322 */
323 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
324 if (reg & BRGPHY_AUXSTS_LINK)
325 break;
326
327 /*
328 * Only retry autonegotiation every 5 seconds.
329 */
330 if (++sc->mii_ticks <= sc->mii_anegticks)
331 break;
332
333 sc->mii_ticks = 0;
334 brgphy_mii_phy_auto(sc);
335 break;
336 }
337
338 /* Update the media status. */
339 brgphy_status(sc);
340
341 /*
342 * Callback if something changed. Note that we need to poke
343 * the DSP on the Broadcom PHYs if the media changes.
344 */
345 if (sc->mii_media_active != mii->mii_media_active ||
346 sc->mii_media_status != mii->mii_media_status ||
347 cmd == MII_MEDIACHG) {
348 switch (sc->mii_model) {
349 case MII_MODEL_xxBROADCOM_BCM5400:
350 brgphy_bcm5401_dspcode(sc);
351 break;
352 case MII_MODEL_xxBROADCOM_BCM5401:
353 if (sc->mii_rev == 1 || sc->mii_rev == 3)
354 brgphy_bcm5401_dspcode(sc);
355 break;
356 case MII_MODEL_xxBROADCOM_BCM5411:
357 brgphy_bcm5411_dspcode(sc);
358 break;
359 }
360 }
361 mii_phy_update(sc, cmd);
362 return (0);
363 }
364
365 static void
366 brgphy_status(struct mii_softc *sc)
367 {
368 struct mii_data *mii = sc->mii_pdata;
369 int bmcr, aux;
370
371 mii->mii_media_status = IFM_AVALID;
372 mii->mii_media_active = IFM_ETHER;
373
374 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
375 if (aux & BRGPHY_AUXSTS_LINK)
376 mii->mii_media_status |= IFM_ACTIVE;
377
378 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
379 if (bmcr & BRGPHY_BMCR_LOOP)
380 mii->mii_media_active |= IFM_LOOP;
381
382 if (bmcr & BRGPHY_BMCR_AUTOEN) {
383 if ((PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_ACOMP) == 0) {
384 /* Erg, still trying, I guess... */
385 mii->mii_media_active |= IFM_NONE;
386 return;
387 }
388
389 switch (aux & BRGPHY_AUXSTS_AN_RES) {
390 case BRGPHY_RES_1000FD:
391 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
392 break;
393 case BRGPHY_RES_1000HD:
394 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
395 break;
396 case BRGPHY_RES_100FD:
397 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
398 break;
399 case BRGPHY_RES_100T4:
400 mii->mii_media_active |= IFM_100_T4;
401 break;
402 case BRGPHY_RES_100HD:
403 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
404 break;
405 case BRGPHY_RES_10FD:
406 mii->mii_media_active |= IFM_10_T | IFM_FDX;
407 break;
408 case BRGPHY_RES_10HD:
409 mii->mii_media_active |= IFM_10_T | IFM_HDX;
410 break;
411 default:
412 mii->mii_media_active |= IFM_NONE;
413 break;
414 }
415 } else {
416 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
417 }
418 }
419
420
421 static void
422 brgphy_mii_phy_auto(struct mii_softc *sc)
423 {
424 int ktcr = 0;
425
426 brgphy_loop(sc);
427 brgphy_reset(sc);
428 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
429 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
430 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
431 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
432 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
433 DELAY(1000);
434 PHY_WRITE(sc, BRGPHY_MII_ANAR,
435 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
436 DELAY(1000);
437 PHY_WRITE(sc, BRGPHY_MII_BMCR,
438 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
439 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
440 }
441
442 static void
443 brgphy_loop(struct mii_softc *sc)
444 {
445 uint32_t bmsr;
446 int i;
447
448 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
449 for (i = 0; i < 15000; i++) {
450 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
451 if (!(bmsr & BRGPHY_BMSR_LINK))
452 break;
453 DELAY(10);
454 }
455 }
456
457 static void
458 brgphy_reset(struct mii_softc *sc)
459 {
460 struct ifnet *ifp;
461
462 mii_phy_reset(sc);
463
464 switch (sc->mii_model) {
465 case MII_MODEL_xxBROADCOM_BCM5400:
466 brgphy_bcm5401_dspcode(sc);
467 break;
468 case MII_MODEL_xxBROADCOM_BCM5401:
469 if (sc->mii_rev == 1 || sc->mii_rev == 3)
470 brgphy_bcm5401_dspcode(sc);
471 break;
472 case MII_MODEL_xxBROADCOM_BCM5411:
473 brgphy_bcm5411_dspcode(sc);
474 break;
475 case MII_MODEL_xxBROADCOM_BCM5421:
476 brgphy_bcm5421_dspcode(sc);
477 break;
478 case MII_MODEL_xxBROADCOM_BCM54K2:
479 brgphy_bcm54k2_dspcode(sc);
480 break;
481 }
482
483 ifp = sc->mii_pdata->mii_ifp;
484 if (strncmp(ifp->if_xname, "bge", 3) == 0) {
485 struct bge_softc *bge_sc = ifp->if_softc;
486
487 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG)
488 brgphy_adc_bug(sc);
489 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG)
490 brgphy_5704_a0_bug(sc);
491 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) {
492 brgphy_ber_bug(sc);
493 } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) {
494 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
495 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
496
497 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) {
498 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
499 PHY_WRITE(sc, BRGPHY_TEST1,
500 BRGPHY_TEST1_TRIM_EN | 0x4);
501 } else {
502 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
503 }
504
505 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
506 }
507 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG)
508 brgphy_crc_bug(sc);
509
510 /* Set Jumbo frame settings in the PHY. */
511 brgphy_jumbo_settings(sc, ifp->if_mtu);
512
513 /* Enable Ethernet@Wirespeed */
514 if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED)
515 brgphy_eth_wirespeed(sc);
516
517 /* Enable Link LED on Dell boxes */
518 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) {
519 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
520 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
521 & ~BRGPHY_PHY_EXTCTL_3_LED);
522 }
523 } else if (strncmp(ifp->if_xname, "bce", 3) == 0) {
524 brgphy_ber_bug(sc);
525 brgphy_jumbo_settings(sc, ifp->if_mtu);
526 brgphy_eth_wirespeed(sc);
527 }
528 }
529
530 /* Turn off tap power management on 5401. */
531 static void
532 brgphy_bcm5401_dspcode(struct mii_softc *sc)
533 {
534 static const struct {
535 int reg;
536 uint16_t val;
537 } dspcode[] = {
538 { BRGPHY_MII_AUXCTL, 0x0c20 },
539 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
540 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
541 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
542 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
543 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
544 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
545 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
546 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
547 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
548 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
549 { 0, 0 },
550 };
551 int i;
552
553 for (i = 0; dspcode[i].reg != 0; i++)
554 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
555 DELAY(40);
556 }
557
558 /* Setting some undocumented voltage */
559 static void
560 brgphy_bcm5411_dspcode(struct mii_softc *sc)
561 {
562 static const struct {
563 int reg;
564 uint16_t val;
565 } dspcode[] = {
566 { 0x1c, 0x8c23 },
567 { 0x1c, 0x8ca3 },
568 { 0x1c, 0x8c23 },
569 { 0, 0 },
570 };
571 int i;
572
573 for (i = 0; dspcode[i].reg != 0; i++)
574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
575 }
576
577 static void
578 brgphy_bcm5421_dspcode(struct mii_softc *sc)
579 {
580 uint16_t data;
581
582 /* Set Class A mode */
583 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
584 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
585 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
586
587 /* Set FFE gamma override to -0.125 */
588 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
589 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
590 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
591 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
592 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
593 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
594 }
595
596 static void
597 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
598 {
599 static const struct {
600 int reg;
601 uint16_t val;
602 } dspcode[] = {
603 { 4, 0x01e1 },
604 { 9, 0x0300 },
605 { 0, 0 },
606 };
607 int i;
608
609 for (i = 0; dspcode[i].reg != 0; i++)
610 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
611 }
612
613 static void
614 brgphy_adc_bug(struct mii_softc *sc)
615 {
616 static const struct {
617 int reg;
618 uint16_t val;
619 } dspcode[] = {
620 { BRGPHY_MII_AUXCTL, 0x0c00 },
621 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
622 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
623 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
624 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
625 { BRGPHY_MII_AUXCTL, 0x0400 },
626 { 0, 0 },
627 };
628 int i;
629
630 for (i = 0; dspcode[i].reg != 0; i++)
631 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
632 }
633
634 static void
635 brgphy_5704_a0_bug(struct mii_softc *sc)
636 {
637 static const struct {
638 int reg;
639 u_int16_t val;
640 } dspcode[] = {
641 { 0x1c, 0x8d68 },
642 { 0x1c, 0x8d68 },
643 { 0, 0 },
644 };
645 int i;
646
647 for (i = 0; dspcode[i].reg != 0; i++)
648 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
649 }
650
651 static void
652 brgphy_ber_bug(struct mii_softc *sc)
653 {
654 static const struct {
655 int reg;
656 uint16_t val;
657 } dspcode[] = {
658 { BRGPHY_MII_AUXCTL, 0x0c00 },
659 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
660 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
661 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
662 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
663 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
664 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
665 { BRGPHY_MII_AUXCTL, 0x0400 },
666 { 0, 0 },
667 };
668 int i;
669
670 for (i = 0; dspcode[i].reg != 0; i++)
671 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
672 }
673
674 static void
675 brgphy_crc_bug(struct mii_softc *sc)
676 {
677 static const struct {
678 int reg;
679 uint16_t val;
680 } dspcode[] = {
681 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
682 { 0x1c, 0x8c68 },
683 { 0x1c, 0x8d68 },
684 { 0x1c, 0x8c68 },
685 { 0, 0 },
686 };
687 int i;
688
689 for (i = 0; dspcode[i].reg != 0; i++)
690 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
691 }
692
693 static void
694 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
695 {
696 uint32_t val;
697
698 /* Set or clear jumbo frame settings in the PHY. */
699 if (mtu > ETHER_MAX_LEN) {
700 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
701 /* BCM5401 PHY cannot read-modify-write. */
702 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
703 } else {
704 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
705 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
706 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
707 val | BRGPHY_AUXCTL_LONG_PKT);
708 }
709
710 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
711 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
712 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
713 } else {
714 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
715 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
716 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
717 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
718
719 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
720 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
721 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
722 }
723 }
724
725 static void
726 brgphy_eth_wirespeed(struct mii_softc *sc)
727 {
728 u_int32_t val;
729
730 /* Enable Ethernet@Wirespeed */
731 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
732 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
733 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
734 }
MP support for (parts of) the network stack