sys/bus/u4b/controller/xhci_pci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /* $FreeBSD: head/sys/dev/usb/controller/xhci_pci.c 276717 2015-01-05 20:22:18Z hselasky $ */
  27
  28 #include <sys/stdint.h>
  29 #include <sys/param.h>
  30 #include <sys/queue.h>
  31 #include <sys/types.h>
  32 #include <sys/systm.h>
  33 #include <sys/kernel.h>
  34 #include <sys/bus.h>
  35 #include <sys/module.h>
  36 #include <sys/lock.h>
  37 #include <sys/mutex.h>
  38 #include <sys/condvar.h>
  39 #include <sys/sysctl.h>
  40 #include <sys/unistd.h>
  41 #include <sys/callout.h>
  42 #include <sys/malloc.h>
  43 #include <sys/priv.h>
  44
  45 #include <bus/u4b/usb.h>
  46 #include <bus/u4b/usbdi.h>
  47
  48 #include <bus/u4b/usb_core.h>
  49 #include <bus/u4b/usb_busdma.h>
  50 #include <bus/u4b/usb_process.h>
  51 #include <bus/u4b/usb_util.h>
  52
  53 #include <bus/u4b/usb_controller.h>
  54 #include <bus/u4b/usb_bus.h>
  55 #include <bus/u4b/usb_pci.h>
  56 #include <bus/u4b/controller/xhci.h>
  57 #include <bus/u4b/controller/xhcireg.h>
  58 #include "usb_if.h"
  59
  60 static device_probe_t xhci_pci_probe;
  61 static device_attach_t xhci_pci_attach;
  62 static device_detach_t xhci_pci_detach;
  63 static usb_take_controller_t xhci_pci_take_controller;
  64
  65 static device_method_t xhci_device_methods[] = {
  66         /* device interface */
  67         DEVMETHOD(device_probe, xhci_pci_probe),
  68         DEVMETHOD(device_attach, xhci_pci_attach),
  69         DEVMETHOD(device_detach, xhci_pci_detach),
  70         DEVMETHOD(device_suspend, bus_generic_suspend),
  71         DEVMETHOD(device_resume, bus_generic_resume),
  72         DEVMETHOD(device_shutdown, bus_generic_shutdown),
  73         DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
  74
  75         DEVMETHOD_END
  76 };
  77
  78 static driver_t xhci_driver = {
  79         .name = "xhci",
  80         .methods = xhci_device_methods,
  81         .size = sizeof(struct xhci_softc),
  82 };
  83
  84 static devclass_t xhci_devclass;
  85
  86 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
  87 MODULE_DEPEND(xhci, usb, 1, 1, 1);
  88
  89 static const char *
  90 xhci_pci_match(device_t self)
  91 {
  92         uint32_t device_id = pci_get_devid(self);
  93
  94         switch (device_id) {
  95         case 0x01941033:
  96                 return ("NEC uPD720200 USB 3.0 controller");
  97
  98         case 0x10421b21:
  99                 return ("ASMedia ASM1042 USB 3.0 controller");
 100
 101         case 0x0f358086:
 102                 return ("Intel Intel BayTrail USB 3.0 controller");
 103         case 0x9c318086:
 104         case 0x1e318086:
 105                 return ("Intel Panther Point USB 3.0 controller");
 106         case 0x8c318086:
 107                 return ("Intel Lynx Point USB 3.0 controller");
 108         case 0x8cb18086:
 109                 return ("Intel Wildcat Point USB 3.0 controller");
 110         case 0x9cb18086:
 111                 return ("Intel Wildcat Point-LB USB 3.0 controller");
 112         default:
 113                 break;
 114         }
 115
 116         if ((pci_get_class(self) == PCIC_SERIALBUS)
 117             && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
 118             && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
 119                 return ("XHCI (generic) USB 3.0 controller");
 120         }
 121         return (NULL);                  /* dunno */
 122 }
 123
 124 static int
 125 xhci_pci_probe(device_t self)
 126 {
 127         const char *desc = xhci_pci_match(self);
 128
 129         if (desc) {
 130                 device_set_desc(self, desc);
 131                 return (0);
 132         } else {
 133                 return (ENXIO);
 134         }
 135 }
 136
 137 static int xhci_use_msi = 1;
 138 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
 139
 140 static void
 141 xhci_interrupt_poll(void *_sc)
 142 {
 143         struct xhci_softc *sc = _sc;
 144         USB_BUS_UNLOCK(&sc->sc_bus);
 145         xhci_interrupt(sc);
 146         USB_BUS_LOCK(&sc->sc_bus);
 147         usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
 148 }
 149
 150 static int
 151 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
 152 {
 153         uint32_t temp;
 154         uint32_t usb3_mask;
 155         uint32_t usb2_mask;
 156
 157         temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
 158             pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
 159
 160         temp |= set;
 161         temp &= ~clear;
 162
 163         /* Don't set bits which the hardware doesn't support */
 164         usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
 165         usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
 166
 167         pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
 168         pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
 169
 170         device_printf(self, "Port routing mask set to 0x%08x\n", temp);
 171
 172         return (0);
 173 }
 174
 175 static int
 176 xhci_pci_attach(device_t self)
 177 {
 178         struct xhci_softc *sc = device_get_softc(self);
 179         int err, rid;
 180         uint8_t usedma32;
 181 #if defined(__DragonFly__)
 182         int irq_flags;
 183 #else
 184         int count;
 185 #endif
 186
 187         rid = PCI_XHCI_CBMEM;
 188         sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
 189             RF_ACTIVE);
 190         if (!sc->sc_io_res) {
 191                 device_printf(self, "Could not map memory\n");
 192                 return (ENOMEM);
 193         }
 194         sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
 195         sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
 196         sc->sc_io_size = rman_get_size(sc->sc_io_res);
 197
 198         /* check for USB 3.0 controllers which don't support 64-bit DMA */
 199         switch (pci_get_devid(self)) {
 200         case 0x01941033:        /* NEC uPD720200 USB 3.0 controller */
 201         case 0x00141912:        /* NEC uPD720201 USB 3.0 controller */
 202         case 0x78141022:        /* AMD A10-7300, tested does not work w/64-bit DMA */
 203                 usedma32 = 1;
 204                 break;
 205         default:
 206                 usedma32 = 0;
 207                 break;
 208         }
 209
 210         if (xhci_init(sc, self, usedma32)) {
 211                 device_printf(self, "Could not initialize softc\n");
 212                 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
 213                     sc->sc_io_res);
 214                 return (ENXIO);
 215         }
 216
 217         pci_enable_busmaster(self);
 218
 219         usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0);
 220
 221         rid = 0;
 222 #if defined(__DragonFly__)
 223         pci_alloc_1intr(self, xhci_use_msi, &rid, &irq_flags);
 224         sc->sc_irq_rid = rid;
 225 #else
 226         if (xhci_use_msi) {
 227                 count = pci_msi_count(self);
 228                 if (count >= 1) {
 229                         count = 1;
 230                         if (pci_alloc_msi(self, &rid, 1, count) == 0) {
 231                                 if (bootverbose)
 232                                         device_printf(self, "MSI enabled\n");
 233                                 sc->sc_irq_rid = 1;
 234                         }
 235                 }
 236         }
 237 #endif
 238
 239         /*
 240          * hw.usb.xhci.use_polling=1 to force polling.
 241          */
 242         if (xhci_use_polling() == 0) {
 243 #if defined(__DragonFly__)
 244                 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ,
 245                     &rid, irq_flags);
 246 #else
 247                 sc->sc_irq_res = bus_alloc_resource_any(
 248                                         self, SYS_RES_IRQ,
 249                                         &sc->sc_irq_rid,
 250                                         RF_SHAREABLE | RF_ACTIVE);
 251 #endif
 252                 if (sc->sc_irq_res == NULL) {
 253                         pci_release_msi(self);
 254                         device_printf(self, "Could not allocate IRQ\n");
 255                         /* goto error; FALLTHROUGH - use polling */
 256                 }
 257         }
 258         sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
 259         if (sc->sc_bus.bdev == NULL) {
 260                 device_printf(self, "Could not add USB device\n");
 261                 goto error;
 262         }
 263         device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
 264
 265         ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
 266
 267         if (sc->sc_irq_res != NULL) {
 268                 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
 269                     (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL);
 270                 if (err != 0) {
 271                         bus_release_resource(self, SYS_RES_IRQ,
 272                             rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
 273                         sc->sc_irq_res = NULL;
 274                         pci_release_msi(self);
 275                         device_printf(self, "Could not setup IRQ, err=%d\n", err);
 276                         sc->sc_intr_hdl = NULL;
 277                 }
 278         }
 279         if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
 280                 if (xhci_use_polling() != 0) {
 281                         device_printf(self, "Interrupt polling at %dHz\n", hz);
 282                         USB_BUS_LOCK(&sc->sc_bus);
 283                         xhci_interrupt_poll(sc);
 284                         USB_BUS_UNLOCK(&sc->sc_bus);
 285                 } else
 286                         goto error;
 287         }
 288
 289         /* On Intel chipsets reroute ports from EHCI to XHCI controller. */
 290         switch (pci_get_devid(self)) {
 291         case 0x0f358086:        /* BayTrail */
 292         case 0x9c318086:        /* Panther Point */
 293         case 0x1e318086:        /* Panther Point */
 294         case 0x8c318086:        /* Lynx Point */
 295         case 0x8cb18086:        /* Wildcat Point */
 296         case 0x9cb18086:        /* Wildcat Point-LP */
 297                 sc->sc_port_route = &xhci_pci_port_route;
 298                 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
 299                 break;
 300         default:
 301                 break;
 302         }
 303
 304         xhci_pci_take_controller(self);
 305
 306         err = xhci_halt_controller(sc);
 307
 308         if (err == 0)
 309                 err = xhci_start_controller(sc);
 310
 311         if (err == 0)
 312                 err = device_probe_and_attach(sc->sc_bus.bdev);
 313
 314         if (err) {
 315                 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
 316                 goto error;
 317         }
 318         return (0);
 319
 320 error:
 321         xhci_pci_detach(self);
 322         return (ENXIO);
 323 }
 324
 325 static int
 326 xhci_pci_detach(device_t self)
 327 {
 328         struct xhci_softc *sc = device_get_softc(self);
 329         device_t bdev;
 330
 331         if (sc->sc_bus.bdev != NULL) {
 332                 bdev = sc->sc_bus.bdev;
 333                 device_detach(bdev);
 334                 device_delete_child(self, bdev);
 335         }
 336         /* during module unload there are lots of children leftover */
 337         device_delete_children(self);
 338
 339         usb_callout_drain(&sc->sc_callout);
 340         xhci_halt_controller(sc);
 341
 342         pci_disable_busmaster(self);
 343
 344         if (sc->sc_irq_res && sc->sc_intr_hdl) {
 345                 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
 346                 sc->sc_intr_hdl = NULL;
 347         }
 348         if (sc->sc_irq_res) {
 349                 bus_release_resource(self, SYS_RES_IRQ,
 350                     rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
 351                 sc->sc_irq_res = NULL;
 352                 pci_release_msi(self);
 353         }
 354         if (sc->sc_io_res) {
 355                 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
 356                     sc->sc_io_res);
 357                 sc->sc_io_res = NULL;
 358         }
 359
 360         xhci_uninit(sc);
 361
 362         return (0);
 363 }
 364
 365 static int
 366 xhci_pci_take_controller(device_t self)
 367 {
 368         struct xhci_softc *sc = device_get_softc(self);
 369         uint32_t cparams;
 370         uint32_t eecp;
 371         uint32_t eec;
 372         uint16_t to;
 373         uint8_t bios_sem;
 374
 375         cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 376
 377         eec = -1;
 378
 379         /* Synchronise with the BIOS if it owns the controller. */
 380         for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
 381             eecp += XHCI_XECP_NEXT(eec) << 2) {
 382                 eec = XREAD4(sc, capa, eecp);
 383
 384                 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
 385                         continue;
 386                 bios_sem = XREAD1(sc, capa, eecp +
 387                     XHCI_XECP_BIOS_SEM);
 388                 if (bios_sem == 0)
 389                         continue;
 390                 device_printf(sc->sc_bus.bdev, "waiting for BIOS "
 391                     "to give up control\n");
 392                 XWRITE1(sc, capa, eecp +
 393                     XHCI_XECP_OS_SEM, 1);
 394                 to = 500;
 395                 while (1) {
 396                         bios_sem = XREAD1(sc, capa, eecp +
 397                             XHCI_XECP_BIOS_SEM);
 398                         if (bios_sem == 0)
 399                                 break;
 400
 401                         if (--to == 0) {
 402                                 device_printf(sc->sc_bus.bdev,
 403                                     "timed out waiting for BIOS\n");
 404                                 break;
 405                         }
 406                         usb_pause_mtx(NULL, hz / 100);  /* wait 10ms */
 407                 }
 408         }
 409         return (0);
 410 }