?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Missing TX_UNK -> TX_POLL conversion
[dragonfly.git] / sys / dev / netif / nfe / if_nfe.c
blob11d5c5047678cdb4df93727b93f97418394971c9
1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.24 2008/06/25 16:25:58 sephe Exp $ */
3
4 /*
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
42 *
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
46 *
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 */
55
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
57
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
60
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
64 #include <sys/bus.h>
65 #include <sys/interrupt.h>
66 #include <sys/proc.h>
67 #include <sys/rman.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
72
73 #include <net/ethernet.h>
74 #include <net/if.h>
75 #include <net/bpf.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
88
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
96
97 #define NFE_CSUM
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
106
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
110
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 #endif
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 struct mbuf *);
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_tick(void *);
143 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
144 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
145 int);
146 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 int, bus_addr_t);
148 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 int);
150 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
151 int);
152 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
153 int);
154
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
156
157 #define NFE_DEBUG
158 #ifdef NFE_DEBUG
159
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_imtime = -1;
163
164 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
165 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
166 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
167
168 #define DPRINTF(sc, fmt, ...) do { \
169 if ((sc)->sc_debug) { \
170 if_printf(&(sc)->arpcom.ac_if, \
171 fmt, __VA_ARGS__); \
172 } \
173 } while (0)
174
175 #define DPRINTFN(sc, lv, fmt, ...) do { \
176 if ((sc)->sc_debug >= (lv)) { \
177 if_printf(&(sc)->arpcom.ac_if, \
178 fmt, __VA_ARGS__); \
179 } \
180 } while (0)
181
182 #else /* !NFE_DEBUG */
183
184 #define DPRINTF(sc, fmt, ...)
185 #define DPRINTFN(sc, lv, fmt, ...)
186
187 #endif /* NFE_DEBUG */
188
189 struct nfe_dma_ctx {
190 int nsegs;
191 bus_dma_segment_t *segs;
192 };
193
194 static const struct nfe_dev {
195 uint16_t vid;
196 uint16_t did;
197 const char *desc;
198 } nfe_devices[] = {
199 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
200 "NVIDIA nForce Fast Ethernet" },
201
202 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
203 "NVIDIA nForce2 Fast Ethernet" },
204
205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
206 "NVIDIA nForce3 Gigabit Ethernet" },
207
208 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
209 chipset, and possibly also the 400R; it might be both nForce2- and
210 nForce3-based boards can use the same MCPs (= southbridges) */
211 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
212 "NVIDIA nForce3 Gigabit Ethernet" },
213
214 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
215 "NVIDIA nForce3 Gigabit Ethernet" },
216
217 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
218 "NVIDIA nForce3 Gigabit Ethernet" },
219
220 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
221 "NVIDIA nForce3 Gigabit Ethernet" },
222
223 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
224 "NVIDIA CK804 Gigabit Ethernet" },
225
226 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
227 "NVIDIA CK804 Gigabit Ethernet" },
228
229 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
230 "NVIDIA MCP04 Gigabit Ethernet" },
231
232 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
233 "NVIDIA MCP04 Gigabit Ethernet" },
234
235 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
236 "NVIDIA MCP51 Gigabit Ethernet" },
237
238 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
239 "NVIDIA MCP51 Gigabit Ethernet" },
240
241 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
242 "NVIDIA MCP55 Gigabit Ethernet" },
243
244 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
245 "NVIDIA MCP55 Gigabit Ethernet" },
246
247 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
248 "NVIDIA MCP61 Gigabit Ethernet" },
249
250 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
251 "NVIDIA MCP61 Gigabit Ethernet" },
252
253 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
254 "NVIDIA MCP61 Gigabit Ethernet" },
255
256 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
257 "NVIDIA MCP61 Gigabit Ethernet" },
258
259 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
260 "NVIDIA MCP65 Gigabit Ethernet" },
261
262 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
263 "NVIDIA MCP65 Gigabit Ethernet" },
264
265 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
266 "NVIDIA MCP65 Gigabit Ethernet" },
267
268 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
269 "NVIDIA MCP65 Gigabit Ethernet" },
270
271 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
272 "NVIDIA MCP67 Gigabit Ethernet" },
273
274 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
275 "NVIDIA MCP67 Gigabit Ethernet" },
276
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
278 "NVIDIA MCP67 Gigabit Ethernet" },
279
280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
281 "NVIDIA MCP67 Gigabit Ethernet" },
282
283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
284 "NVIDIA MCP73 Gigabit Ethernet" },
285
286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
287 "NVIDIA MCP73 Gigabit Ethernet" },
288
289 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
290 "NVIDIA MCP73 Gigabit Ethernet" },
291
292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
293 "NVIDIA MCP73 Gigabit Ethernet" },
294
295 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
296 "NVIDIA MCP77 Gigabit Ethernet" },
297
298 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
299 "NVIDIA MCP77 Gigabit Ethernet" },
300
301 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
302 "NVIDIA MCP77 Gigabit Ethernet" },
303
304 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
305 "NVIDIA MCP77 Gigabit Ethernet" },
306
307 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
308 "NVIDIA MCP79 Gigabit Ethernet" },
309
310 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
311 "NVIDIA MCP79 Gigabit Ethernet" },
312
313 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
314 "NVIDIA MCP79 Gigabit Ethernet" },
315
316 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
317 "NVIDIA MCP79 Gigabit Ethernet" },
318
319 { 0, 0, NULL }
320 };
321
322 static device_method_t nfe_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, nfe_probe),
325 DEVMETHOD(device_attach, nfe_attach),
326 DEVMETHOD(device_detach, nfe_detach),
327 DEVMETHOD(device_suspend, nfe_suspend),
328 DEVMETHOD(device_resume, nfe_resume),
329 DEVMETHOD(device_shutdown, nfe_shutdown),
330
331 /* Bus interface */
332 DEVMETHOD(bus_print_child, bus_generic_print_child),
333 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
334
335 /* MII interface */
336 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
337 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
338 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
339
340 { 0, 0 }
341 };
342
343 static driver_t nfe_driver = {
344 "nfe",
345 nfe_methods,
346 sizeof(struct nfe_softc)
347 };
348
349 static devclass_t nfe_devclass;
350
351 DECLARE_DUMMY_MODULE(if_nfe);
352 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
353 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
354 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
355
356 static int
357 nfe_probe(device_t dev)
358 {
359 const struct nfe_dev *n;
360 uint16_t vid, did;
361
362 vid = pci_get_vendor(dev);
363 did = pci_get_device(dev);
364 for (n = nfe_devices; n->desc != NULL; ++n) {
365 if (vid == n->vid && did == n->did) {
366 struct nfe_softc *sc = device_get_softc(dev);
367
368 switch (did) {
369 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
370 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
371 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
372 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
373 sc->sc_flags = NFE_JUMBO_SUP |
374 NFE_HW_CSUM;
375 break;
376 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
377 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
378 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
379 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
380 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
381 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
382 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
383 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
384 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
385 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
386 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
387 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
388 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
389 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
390 sc->sc_flags = NFE_40BIT_ADDR;
391 break;
392 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
393 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
395 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
396 sc->sc_flags = NFE_JUMBO_SUP |
397 NFE_40BIT_ADDR |
398 NFE_HW_CSUM;
399 break;
400 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
402 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
403 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
404 sc->sc_flags = NFE_JUMBO_SUP |
405 NFE_40BIT_ADDR;
406 break;
407 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
408 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
409 sc->sc_flags = NFE_JUMBO_SUP |
410 NFE_40BIT_ADDR |
411 NFE_HW_CSUM |
412 NFE_HW_VLAN;
413 break;
414 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
415 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
416 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
417 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
418 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
419 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
420 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
421 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
422 sc->sc_flags = NFE_40BIT_ADDR |
423 NFE_HW_CSUM;
424 break;
425 }
426
427 device_set_desc(dev, n->desc);
428 device_set_async_attach(dev, TRUE);
429 return 0;
430 }
431 }
432 return ENXIO;
433 }
434
435 static int
436 nfe_attach(device_t dev)
437 {
438 struct nfe_softc *sc = device_get_softc(dev);
439 struct ifnet *ifp = &sc->arpcom.ac_if;
440 uint8_t eaddr[ETHER_ADDR_LEN];
441 int error;
442
443 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
444 lwkt_serialize_init(&sc->sc_jbuf_serializer);
445
446 /*
447 * Initialize sysctl variables
448 */
449 sc->sc_imtime = nfe_imtime;
450 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
451 sc->sc_rx_ring_count = nfe_rx_ring_count;
452 sc->sc_debug = nfe_debug;
453
454 sc->sc_mem_rid = PCIR_BAR(0);
455
456 #ifndef BURN_BRIDGES
457 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
458 uint32_t mem, irq;
459
460 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
461 irq = pci_read_config(dev, PCIR_INTLINE, 4);
462
463 device_printf(dev, "chip is in D%d power mode "
464 "-- setting to D0\n", pci_get_powerstate(dev));
465
466 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
467
468 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
469 pci_write_config(dev, PCIR_INTLINE, irq, 4);
470 }
471 #endif /* !BURN_BRIDGE */
472
473 /* Enable bus mastering */
474 pci_enable_busmaster(dev);
475
476 /* Allocate IO memory */
477 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
478 &sc->sc_mem_rid, RF_ACTIVE);
479 if (sc->sc_mem_res == NULL) {
480 device_printf(dev, "cound not allocate io memory\n");
481 return ENXIO;
482 }
483 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
484 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
485
486 /* Allocate IRQ */
487 sc->sc_irq_rid = 0;
488 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
489 &sc->sc_irq_rid,
490 RF_SHAREABLE | RF_ACTIVE);
491 if (sc->sc_irq_res == NULL) {
492 device_printf(dev, "could not allocate irq\n");
493 error = ENXIO;
494 goto fail;
495 }
496
497 nfe_get_macaddr(sc, eaddr);
498
499 /*
500 * Allocate Tx and Rx rings.
501 */
502 error = nfe_alloc_tx_ring(sc, &sc->txq);
503 if (error) {
504 device_printf(dev, "could not allocate Tx ring\n");
505 goto fail;
506 }
507
508 error = nfe_alloc_rx_ring(sc, &sc->rxq);
509 if (error) {
510 device_printf(dev, "could not allocate Rx ring\n");
511 goto fail;
512 }
513
514 /*
515 * Create sysctl tree
516 */
517 sysctl_ctx_init(&sc->sc_sysctl_ctx);
518 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
519 SYSCTL_STATIC_CHILDREN(_hw),
520 OID_AUTO,
521 device_get_nameunit(dev),
522 CTLFLAG_RD, 0, "");
523 if (sc->sc_sysctl_tree == NULL) {
524 device_printf(dev, "can't add sysctl node\n");
525 error = ENXIO;
526 goto fail;
527 }
528 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
529 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
530 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
531 sc, 0, nfe_sysctl_imtime, "I",
532 "Interrupt moderation time (usec). "
533 "-1 to disable interrupt moderation.");
534 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
535 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
536 0, "RX ring count");
537 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
538 "debug", CTLFLAG_RW, &sc->sc_debug,
539 0, "control debugging printfs");
540
541 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
542 nfe_ifmedia_sts);
543 if (error) {
544 device_printf(dev, "MII without any phy\n");
545 goto fail;
546 }
547
548 ifp->if_softc = sc;
549 ifp->if_mtu = ETHERMTU;
550 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
551 ifp->if_ioctl = nfe_ioctl;
552 ifp->if_start = nfe_start;
553 #ifdef DEVICE_POLLING
554 ifp->if_poll = nfe_poll;
555 #endif
556 ifp->if_watchdog = nfe_watchdog;
557 ifp->if_init = nfe_init;
558 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
559 ifq_set_ready(&ifp->if_snd);
560
561 ifp->if_capabilities = IFCAP_VLAN_MTU;
562
563 if (sc->sc_flags & NFE_HW_VLAN)
564 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
565
566 #ifdef NFE_CSUM
567 if (sc->sc_flags & NFE_HW_CSUM) {
568 ifp->if_capabilities |= IFCAP_HWCSUM;
569 ifp->if_hwassist = NFE_CSUM_FEATURES;
570 }
571 #else
572 sc->sc_flags &= ~NFE_HW_CSUM;
573 #endif
574 ifp->if_capenable = ifp->if_capabilities;
575
576 callout_init(&sc->sc_tick_ch);
577
578 ether_ifattach(ifp, eaddr, NULL);
579
580 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
581 &sc->sc_ih, ifp->if_serializer);
582 if (error) {
583 device_printf(dev, "could not setup intr\n");
584 ether_ifdetach(ifp);
585 goto fail;
586 }
587
588 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
589 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
590
591 return 0;
592 fail:
593 nfe_detach(dev);
594 return error;
595 }
596
597 static int
598 nfe_detach(device_t dev)
599 {
600 struct nfe_softc *sc = device_get_softc(dev);
601
602 if (device_is_attached(dev)) {
603 struct ifnet *ifp = &sc->arpcom.ac_if;
604
605 lwkt_serialize_enter(ifp->if_serializer);
606 nfe_stop(sc);
607 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
608 lwkt_serialize_exit(ifp->if_serializer);
609
610 ether_ifdetach(ifp);
611 }
612
613 if (sc->sc_miibus != NULL)
614 device_delete_child(dev, sc->sc_miibus);
615 bus_generic_detach(dev);
616
617 if (sc->sc_sysctl_tree != NULL)
618 sysctl_ctx_free(&sc->sc_sysctl_ctx);
619
620 if (sc->sc_irq_res != NULL) {
621 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
622 sc->sc_irq_res);
623 }
624
625 if (sc->sc_mem_res != NULL) {
626 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
627 sc->sc_mem_res);
628 }
629
630 nfe_free_tx_ring(sc, &sc->txq);
631 nfe_free_rx_ring(sc, &sc->rxq);
632
633 return 0;
634 }
635
636 static void
637 nfe_shutdown(device_t dev)
638 {
639 struct nfe_softc *sc = device_get_softc(dev);
640 struct ifnet *ifp = &sc->arpcom.ac_if;
641
642 lwkt_serialize_enter(ifp->if_serializer);
643 nfe_stop(sc);
644 lwkt_serialize_exit(ifp->if_serializer);
645 }
646
647 static int
648 nfe_suspend(device_t dev)
649 {
650 struct nfe_softc *sc = device_get_softc(dev);
651 struct ifnet *ifp = &sc->arpcom.ac_if;
652
653 lwkt_serialize_enter(ifp->if_serializer);
654 nfe_stop(sc);
655 lwkt_serialize_exit(ifp->if_serializer);
656
657 return 0;
658 }
659
660 static int
661 nfe_resume(device_t dev)
662 {
663 struct nfe_softc *sc = device_get_softc(dev);
664 struct ifnet *ifp = &sc->arpcom.ac_if;
665
666 lwkt_serialize_enter(ifp->if_serializer);
667 if (ifp->if_flags & IFF_UP)
668 nfe_init(sc);
669 lwkt_serialize_exit(ifp->if_serializer);
670
671 return 0;
672 }
673
674 static void
675 nfe_miibus_statchg(device_t dev)
676 {
677 struct nfe_softc *sc = device_get_softc(dev);
678 struct mii_data *mii = device_get_softc(sc->sc_miibus);
679 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
680
681 phy = NFE_READ(sc, NFE_PHY_IFACE);
682 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
683
684 seed = NFE_READ(sc, NFE_RNDSEED);
685 seed &= ~NFE_SEED_MASK;
686
687 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
688 phy |= NFE_PHY_HDX; /* half-duplex */
689 misc |= NFE_MISC1_HDX;
690 }
691
692 switch (IFM_SUBTYPE(mii->mii_media_active)) {
693 case IFM_1000_T: /* full-duplex only */
694 link |= NFE_MEDIA_1000T;
695 seed |= NFE_SEED_1000T;
696 phy |= NFE_PHY_1000T;
697 break;
698 case IFM_100_TX:
699 link |= NFE_MEDIA_100TX;
700 seed |= NFE_SEED_100TX;
701 phy |= NFE_PHY_100TX;
702 break;
703 case IFM_10_T:
704 link |= NFE_MEDIA_10T;
705 seed |= NFE_SEED_10T;
706 break;
707 }
708
709 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
710
711 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
712 NFE_WRITE(sc, NFE_MISC1, misc);
713 NFE_WRITE(sc, NFE_LINKSPEED, link);
714 }
715
716 static int
717 nfe_miibus_readreg(device_t dev, int phy, int reg)
718 {
719 struct nfe_softc *sc = device_get_softc(dev);
720 uint32_t val;
721 int ntries;
722
723 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
724
725 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
726 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
727 DELAY(100);
728 }
729
730 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
731
732 for (ntries = 0; ntries < 1000; ntries++) {
733 DELAY(100);
734 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
735 break;
736 }
737 if (ntries == 1000) {
738 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
739 return 0;
740 }
741
742 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
743 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
744 return 0;
745 }
746
747 val = NFE_READ(sc, NFE_PHY_DATA);
748 if (val != 0xffffffff && val != 0)
749 sc->mii_phyaddr = phy;
750
751 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
752
753 return val;
754 }
755
756 static void
757 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
758 {
759 struct nfe_softc *sc = device_get_softc(dev);
760 uint32_t ctl;
761 int ntries;
762
763 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
764
765 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
766 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
767 DELAY(100);
768 }
769
770 NFE_WRITE(sc, NFE_PHY_DATA, val);
771 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
772 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
773
774 for (ntries = 0; ntries < 1000; ntries++) {
775 DELAY(100);
776 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
777 break;
778 }
779
780 #ifdef NFE_DEBUG
781 if (ntries == 1000)
782 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
783 #endif
784 }
785
786 #ifdef DEVICE_POLLING
787
788 static void
789 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
790 {
791 struct nfe_softc *sc = ifp->if_softc;
792
793 ASSERT_SERIALIZED(ifp->if_serializer);
794
795 switch(cmd) {
796 case POLL_REGISTER:
797 /* Disable interrupts */
798 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
799 break;
800 case POLL_DEREGISTER:
801 /* enable interrupts */
802 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
803 break;
804 case POLL_AND_CHECK_STATUS:
805 /* fall through */
806 case POLL_ONLY:
807 if (ifp->if_flags & IFF_RUNNING) {
808 nfe_rxeof(sc);
809 nfe_txeof(sc);
810 }
811 break;
812 }
813 }
814
815 #endif
816
817 static void
818 nfe_intr(void *arg)
819 {
820 struct nfe_softc *sc = arg;
821 struct ifnet *ifp = &sc->arpcom.ac_if;
822 uint32_t r;
823
824 r = NFE_READ(sc, NFE_IRQ_STATUS);
825 if (r == 0)
826 return; /* not for us */
827 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
828
829 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
830
831 if (r & NFE_IRQ_LINK) {
832 NFE_READ(sc, NFE_PHY_STATUS);
833 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
834 DPRINTF(sc, "link state changed %s\n", "");
835 }
836
837 if (ifp->if_flags & IFF_RUNNING) {
838 /* check Rx ring */
839 nfe_rxeof(sc);
840
841 /* check Tx ring */
842 nfe_txeof(sc);
843 }
844 }
845
846 static int
847 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
848 {
849 struct nfe_softc *sc = ifp->if_softc;
850 struct ifreq *ifr = (struct ifreq *)data;
851 struct mii_data *mii;
852 int error = 0, mask;
853
854 switch (cmd) {
855 case SIOCSIFMTU:
856 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
857 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
858 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
859 ifr->ifr_mtu > ETHERMTU)) {
860 return EINVAL;
861 } else if (ifp->if_mtu != ifr->ifr_mtu) {
862 ifp->if_mtu = ifr->ifr_mtu;
863 nfe_init(sc);
864 }
865 break;
866 case SIOCSIFFLAGS:
867 if (ifp->if_flags & IFF_UP) {
868 /*
869 * If only the PROMISC or ALLMULTI flag changes, then
870 * don't do a full re-init of the chip, just update
871 * the Rx filter.
872 */
873 if ((ifp->if_flags & IFF_RUNNING) &&
874 ((ifp->if_flags ^ sc->sc_if_flags) &
875 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
876 nfe_setmulti(sc);
877 } else {
878 if (!(ifp->if_flags & IFF_RUNNING))
879 nfe_init(sc);
880 }
881 } else {
882 if (ifp->if_flags & IFF_RUNNING)
883 nfe_stop(sc);
884 }
885 sc->sc_if_flags = ifp->if_flags;
886 break;
887 case SIOCADDMULTI:
888 case SIOCDELMULTI:
889 if (ifp->if_flags & IFF_RUNNING)
890 nfe_setmulti(sc);
891 break;
892 case SIOCSIFMEDIA:
893 case SIOCGIFMEDIA:
894 mii = device_get_softc(sc->sc_miibus);
895 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
896 break;
897 case SIOCSIFCAP:
898 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
899 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
900 ifp->if_capenable ^= mask;
901 if (IFCAP_TXCSUM & ifp->if_capenable)
902 ifp->if_hwassist = NFE_CSUM_FEATURES;
903 else
904 ifp->if_hwassist = 0;
905
906 if (ifp->if_flags & IFF_RUNNING)
907 nfe_init(sc);
908 }
909 break;
910 default:
911 error = ether_ioctl(ifp, cmd, data);
912 break;
913 }
914 return error;
915 }
916
917 static void
918 nfe_rxeof(struct nfe_softc *sc)
919 {
920 struct ifnet *ifp = &sc->arpcom.ac_if;
921 struct nfe_rx_ring *ring = &sc->rxq;
922 int reap;
923 #ifdef ETHER_INPUT_CHAIN
924 struct mbuf_chain chain[MAXCPU];
925 #endif
926
927 reap = 0;
928 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
929
930 #ifdef ETHER_INPUT_CHAIN
931 ether_input_chain_init(chain);
932 #endif
933
934 for (;;) {
935 struct nfe_rx_data *data = &ring->data[ring->cur];
936 struct mbuf *m;
937 uint16_t flags;
938 int len, error;
939
940 if (sc->sc_flags & NFE_40BIT_ADDR) {
941 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
942
943 flags = le16toh(desc64->flags);
944 len = le16toh(desc64->length) & 0x3fff;
945 } else {
946 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
947
948 flags = le16toh(desc32->flags);
949 len = le16toh(desc32->length) & 0x3fff;
950 }
951
952 if (flags & NFE_RX_READY)
953 break;
954
955 reap = 1;
956
957 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
958 if (!(flags & NFE_RX_VALID_V1))
959 goto skip;
960
961 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
962 flags &= ~NFE_RX_ERROR;
963 len--; /* fix buffer length */
964 }
965 } else {
966 if (!(flags & NFE_RX_VALID_V2))
967 goto skip;
968
969 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
970 flags &= ~NFE_RX_ERROR;
971 len--; /* fix buffer length */
972 }
973 }
974
975 if (flags & NFE_RX_ERROR) {
976 ifp->if_ierrors++;
977 goto skip;
978 }
979
980 m = data->m;
981
982 if (sc->sc_flags & NFE_USE_JUMBO)
983 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
984 else
985 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
986 if (error) {
987 ifp->if_ierrors++;
988 goto skip;
989 }
990
991 /* finalize mbuf */
992 m->m_pkthdr.len = m->m_len = len;
993 m->m_pkthdr.rcvif = ifp;
994
995 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
996 (flags & NFE_RX_CSUMOK)) {
997 if (flags & NFE_RX_IP_CSUMOK_V2) {
998 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
999 CSUM_IP_VALID;
1000 }
1001
1002 if (flags &
1003 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1004 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1005 CSUM_PSEUDO_HDR |
1006 CSUM_FRAG_NOT_CHECKED;
1007 m->m_pkthdr.csum_data = 0xffff;
1008 }
1009 }
1010
1011 ifp->if_ipackets++;
1012 #ifdef ETHER_INPUT_CHAIN
1013 #ifdef ETHER_INPUT2
1014 ether_input_chain2(ifp, m, chain);
1015 #else
1016 ether_input_chain(ifp, m, chain);
1017 #endif
1018 #else
1019 ifp->if_input(ifp, m);
1020 #endif
1021 skip:
1022 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1023 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1024 }
1025
1026 if (reap) {
1027 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1028 #ifdef ETHER_INPUT_CHAIN
1029 ether_input_dispatch(chain);
1030 #endif
1031 }
1032 }
1033
1034 static void
1035 nfe_txeof(struct nfe_softc *sc)
1036 {
1037 struct ifnet *ifp = &sc->arpcom.ac_if;
1038 struct nfe_tx_ring *ring = &sc->txq;
1039 struct nfe_tx_data *data = NULL;
1040
1041 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1042 while (ring->next != ring->cur) {
1043 uint16_t flags;
1044
1045 if (sc->sc_flags & NFE_40BIT_ADDR)
1046 flags = le16toh(ring->desc64[ring->next].flags);
1047 else
1048 flags = le16toh(ring->desc32[ring->next].flags);
1049
1050 if (flags & NFE_TX_VALID)
1051 break;
1052
1053 data = &ring->data[ring->next];
1054
1055 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1056 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1057 goto skip;
1058
1059 if ((flags & NFE_TX_ERROR_V1) != 0) {
1060 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1061 NFE_V1_TXERR);
1062 ifp->if_oerrors++;
1063 } else {
1064 ifp->if_opackets++;
1065 }
1066 } else {
1067 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1068 goto skip;
1069
1070 if ((flags & NFE_TX_ERROR_V2) != 0) {
1071 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1072 NFE_V2_TXERR);
1073 ifp->if_oerrors++;
1074 } else {
1075 ifp->if_opackets++;
1076 }
1077 }
1078
1079 if (data->m == NULL) { /* should not get there */
1080 if_printf(ifp,
1081 "last fragment bit w/o associated mbuf!\n");
1082 goto skip;
1083 }
1084
1085 /* last fragment of the mbuf chain transmitted */
1086 bus_dmamap_sync(ring->data_tag, data->map,
1087 BUS_DMASYNC_POSTWRITE);
1088 bus_dmamap_unload(ring->data_tag, data->map);
1089 m_freem(data->m);
1090 data->m = NULL;
1091
1092 ifp->if_timer = 0;
1093 skip:
1094 ring->queued--;
1095 KKASSERT(ring->queued >= 0);
1096 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1097 }
1098
1099 if (data != NULL) { /* at least one slot freed */
1100 ifp->if_flags &= ~IFF_OACTIVE;
1101 if_devstart(ifp);
1102 }
1103 }
1104
1105 static int
1106 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1107 {
1108 struct nfe_dma_ctx ctx;
1109 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1110 struct nfe_tx_data *data, *data_map;
1111 bus_dmamap_t map;
1112 struct nfe_desc64 *desc64 = NULL;
1113 struct nfe_desc32 *desc32 = NULL;
1114 uint16_t flags = 0;
1115 uint32_t vtag = 0;
1116 int error, i, j;
1117
1118 data = &ring->data[ring->cur];
1119 map = data->map;
1120 data_map = data; /* Remember who owns the DMA map */
1121
1122 ctx.nsegs = NFE_MAX_SCATTER;
1123 ctx.segs = segs;
1124 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1125 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1126 if (error && error != EFBIG) {
1127 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1128 goto back;
1129 }
1130
1131 if (error) { /* error == EFBIG */
1132 struct mbuf *m_new;
1133
1134 m_new = m_defrag(m0, MB_DONTWAIT);
1135 if (m_new == NULL) {
1136 if_printf(&sc->arpcom.ac_if,
1137 "could not defrag TX mbuf\n");
1138 error = ENOBUFS;
1139 goto back;
1140 } else {
1141 m0 = m_new;
1142 }
1143
1144 ctx.nsegs = NFE_MAX_SCATTER;
1145 ctx.segs = segs;
1146 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1147 nfe_buf_dma_addr, &ctx,
1148 BUS_DMA_NOWAIT);
1149 if (error) {
1150 if_printf(&sc->arpcom.ac_if,
1151 "could not map defraged TX mbuf\n");
1152 goto back;
1153 }
1154 }
1155
1156 error = 0;
1157
1158 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1159 bus_dmamap_unload(ring->data_tag, map);
1160 error = ENOBUFS;
1161 goto back;
1162 }
1163
1164 /* setup h/w VLAN tagging */
1165 if (m0->m_flags & M_VLANTAG)
1166 vtag = m0->m_pkthdr.ether_vlantag;
1167
1168 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1169 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1170 flags |= NFE_TX_IP_CSUM;
1171 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1172 flags |= NFE_TX_TCP_CSUM;
1173 }
1174
1175 /*
1176 * XXX urm. somebody is unaware of how hardware works. You
1177 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1178 * the ring until the entire chain is actually *VALID*. Otherwise
1179 * the hardware may encounter a partially initialized chain that
1180 * is marked as being ready to go when it in fact is not ready to
1181 * go.
1182 */
1183
1184 for (i = 0; i < ctx.nsegs; i++) {
1185 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1186 data = &ring->data[j];
1187
1188 if (sc->sc_flags & NFE_40BIT_ADDR) {
1189 desc64 = &ring->desc64[j];
1190 #if defined(__LP64__)
1191 desc64->physaddr[0] =
1192 htole32(segs[i].ds_addr >> 32);
1193 #endif
1194 desc64->physaddr[1] =
1195 htole32(segs[i].ds_addr & 0xffffffff);
1196 desc64->length = htole16(segs[i].ds_len - 1);
1197 desc64->vtag = htole32(vtag);
1198 desc64->flags = htole16(flags);
1199 } else {
1200 desc32 = &ring->desc32[j];
1201 desc32->physaddr = htole32(segs[i].ds_addr);
1202 desc32->length = htole16(segs[i].ds_len - 1);
1203 desc32->flags = htole16(flags);
1204 }
1205
1206 /* csum flags and vtag belong to the first fragment only */
1207 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1208 vtag = 0;
1209
1210 ring->queued++;
1211 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1212 }
1213
1214 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1215 if (sc->sc_flags & NFE_40BIT_ADDR) {
1216 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1217 } else {
1218 if (sc->sc_flags & NFE_JUMBO_SUP)
1219 flags = NFE_TX_LASTFRAG_V2;
1220 else
1221 flags = NFE_TX_LASTFRAG_V1;
1222 desc32->flags |= htole16(flags);
1223 }
1224
1225 /*
1226 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1227 * whole mess until the first descriptor in the map is flagged.
1228 */
1229 for (i = ctx.nsegs - 1; i >= 0; --i) {
1230 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1231 if (sc->sc_flags & NFE_40BIT_ADDR) {
1232 desc64 = &ring->desc64[j];
1233 desc64->flags |= htole16(NFE_TX_VALID);
1234 } else {
1235 desc32 = &ring->desc32[j];
1236 desc32->flags |= htole16(NFE_TX_VALID);
1237 }
1238 }
1239 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1240
1241 /* Exchange DMA map */
1242 data_map->map = data->map;
1243 data->map = map;
1244 data->m = m0;
1245
1246 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1247 back:
1248 if (error)
1249 m_freem(m0);
1250 return error;
1251 }
1252
1253 static void
1254 nfe_start(struct ifnet *ifp)
1255 {
1256 struct nfe_softc *sc = ifp->if_softc;
1257 struct nfe_tx_ring *ring = &sc->txq;
1258 int count = 0;
1259 struct mbuf *m0;
1260
1261 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1262 return;
1263
1264 for (;;) {
1265 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1266 if (m0 == NULL)
1267 break;
1268
1269 ETHER_BPF_MTAP(ifp, m0);
1270
1271 if (nfe_encap(sc, ring, m0) != 0) {
1272 ifp->if_flags |= IFF_OACTIVE;
1273 break;
1274 }
1275 ++count;
1276
1277 /*
1278 * NOTE:
1279 * `m0' may be freed in nfe_encap(), so
1280 * it should not be touched any more.
1281 */
1282 }
1283 if (count == 0) /* nothing sent */
1284 return;
1285
1286 /* Sync TX descriptor ring */
1287 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1288
1289 /* Kick Tx */
1290 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1291
1292 /*
1293 * Set a timeout in case the chip goes out to lunch.
1294 */
1295 ifp->if_timer = 5;
1296 }
1297
1298 static void
1299 nfe_watchdog(struct ifnet *ifp)
1300 {
1301 struct nfe_softc *sc = ifp->if_softc;
1302
1303 if (ifp->if_flags & IFF_RUNNING) {
1304 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1305 nfe_txeof(sc);
1306 return;
1307 }
1308
1309 if_printf(ifp, "watchdog timeout\n");
1310
1311 nfe_init(ifp->if_softc);
1312
1313 ifp->if_oerrors++;
1314 }
1315
1316 static void
1317 nfe_init(void *xsc)
1318 {
1319 struct nfe_softc *sc = xsc;
1320 struct ifnet *ifp = &sc->arpcom.ac_if;
1321 uint32_t tmp;
1322 int error;
1323
1324 nfe_stop(sc);
1325
1326 /*
1327 * NOTE:
1328 * Switching between jumbo frames and normal frames should
1329 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1330 */
1331 if (ifp->if_mtu > ETHERMTU) {
1332 sc->sc_flags |= NFE_USE_JUMBO;
1333 sc->rxq.bufsz = NFE_JBYTES;
1334 if (bootverbose)
1335 if_printf(ifp, "use jumbo frames\n");
1336 } else {
1337 sc->sc_flags &= ~NFE_USE_JUMBO;
1338 sc->rxq.bufsz = MCLBYTES;
1339 if (bootverbose)
1340 if_printf(ifp, "use non-jumbo frames\n");
1341 }
1342
1343 error = nfe_init_tx_ring(sc, &sc->txq);
1344 if (error) {
1345 nfe_stop(sc);
1346 return;
1347 }
1348
1349 error = nfe_init_rx_ring(sc, &sc->rxq);
1350 if (error) {
1351 nfe_stop(sc);
1352 return;
1353 }
1354
1355 NFE_WRITE(sc, NFE_TX_POLL, 0);
1356 NFE_WRITE(sc, NFE_STATUS, 0);
1357
1358 sc->rxtxctl = NFE_RXTX_BIT2;
1359 if (sc->sc_flags & NFE_40BIT_ADDR)
1360 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1361 else if (sc->sc_flags & NFE_JUMBO_SUP)
1362 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1363
1364 if (ifp->if_capenable & IFCAP_RXCSUM)
1365 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1366
1367 /*
1368 * Although the adapter is capable of stripping VLAN tags from received
1369 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1370 * purpose. This will be done in software by our network stack.
1371 */
1372 if (sc->sc_flags & NFE_HW_VLAN)
1373 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1374
1375 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1376 DELAY(10);
1377 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1378
1379 if (sc->sc_flags & NFE_HW_VLAN)
1380 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1381
1382 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1383
1384 /* set MAC address */
1385 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1386
1387 /* tell MAC where rings are in memory */
1388 #ifdef __LP64__
1389 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1390 #endif
1391 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1392 #ifdef __LP64__
1393 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1394 #endif
1395 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1396
1397 NFE_WRITE(sc, NFE_RING_SIZE,
1398 (sc->sc_rx_ring_count - 1) << 16 |
1399 (NFE_TX_RING_COUNT - 1));
1400
1401 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1402
1403 /* force MAC to wakeup */
1404 tmp = NFE_READ(sc, NFE_PWR_STATE);
1405 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1406 DELAY(10);
1407 tmp = NFE_READ(sc, NFE_PWR_STATE);
1408 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1409
1410 /*
1411 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1412 * It is unclear how wide the timer is. Base programming does
1413 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1414 * we don't get any interrupt moderation. TX moderation is
1415 * possible by using the timer interrupt instead of TX_DONE.
1416 *
1417 * It is unclear whether there are other bits that can be
1418 * set to make the NFE device actually do interrupt moderation
1419 * on the RX side.
1420 *
1421 * For now set a 128uS interval as a placemark, but don't use
1422 * the timer.
1423 */
1424 if (sc->sc_imtime < 0)
1425 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1426 else
1427 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1428
1429 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1430 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1431 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1432
1433 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1434 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1435
1436 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1437 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1438
1439 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1440 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1441 DELAY(10);
1442 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1443
1444 /* set Rx filter */
1445 nfe_setmulti(sc);
1446
1447 nfe_ifmedia_upd(ifp);
1448
1449 /* enable Rx */
1450 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1451
1452 /* enable Tx */
1453 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1454
1455 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1456
1457 #ifdef DEVICE_POLLING
1458 if ((ifp->if_flags & IFF_POLLING) == 0)
1459 #endif
1460 /* enable interrupts */
1461 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1462
1463 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1464
1465 ifp->if_flags |= IFF_RUNNING;
1466 ifp->if_flags &= ~IFF_OACTIVE;
1467
1468 /*
1469 * If we had stuff in the tx ring before its all cleaned out now
1470 * so we are not going to get an interrupt, jump-start any pending
1471 * output.
1472 */
1473 if_devstart(ifp);
1474 }
1475
1476 static void
1477 nfe_stop(struct nfe_softc *sc)
1478 {
1479 struct ifnet *ifp = &sc->arpcom.ac_if;
1480
1481 callout_stop(&sc->sc_tick_ch);
1482
1483 ifp->if_timer = 0;
1484 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1485
1486 /*
1487 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1488 * or do they directly reset/terminate the DMA hardware? Nobody
1489 * knows.
1490 *
1491 * Add two delays:
1492 *
1493 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1494 * watchdog timeout that occurs after a stop/init sequence. I am
1495 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1496 * due to dhclient) is queueing an interrupt to the microcontroller
1497 * which gets delayed until after we clear the control registers
1498 * down below, resulting in mass confusion. TX KICK is clearly
1499 * hardware aided whereas the other bits in the control register
1500 * are more likely to be polled by the microcontroller.
1501 *
1502 * (2) Delay after zeroing out TX and RX CTL registers, under the
1503 * assumption that primary DMA is initiated and terminated by
1504 * the microcontroller and not hardware (and anyway, one can hardly
1505 * expect the DMA engine to just instantly stop!). We don't want
1506 * to rip the rings out from under it before it has had a chance to
1507 * actually stop!
1508 */
1509 DELAY(1000);
1510
1511 /* Abort Tx */
1512 NFE_WRITE(sc, NFE_TX_CTL, 0);
1513
1514 /* Disable Rx */
1515 NFE_WRITE(sc, NFE_RX_CTL, 0);
1516
1517 /* Disable interrupts */
1518 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1519
1520 DELAY(1000);
1521
1522 /* Reset Tx and Rx rings */
1523 nfe_reset_tx_ring(sc, &sc->txq);
1524 nfe_reset_rx_ring(sc, &sc->rxq);
1525 }
1526
1527 static int
1528 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1529 {
1530 int i, j, error, descsize;
1531 void **desc;
1532
1533 if (sc->sc_flags & NFE_40BIT_ADDR) {
1534 desc = (void **)&ring->desc64;
1535 descsize = sizeof(struct nfe_desc64);
1536 } else {
1537 desc = (void **)&ring->desc32;
1538 descsize = sizeof(struct nfe_desc32);
1539 }
1540
1541 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1542 M_DEVBUF, M_WAITOK | M_ZERO);
1543 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1544 M_DEVBUF, M_WAITOK | M_ZERO);
1545
1546 ring->bufsz = MCLBYTES;
1547 ring->cur = ring->next = 0;
1548
1549 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1550 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1551 NULL, NULL,
1552 sc->sc_rx_ring_count * descsize, 1,
1553 sc->sc_rx_ring_count * descsize,
1554 0, &ring->tag);
1555 if (error) {
1556 if_printf(&sc->arpcom.ac_if,
1557 "could not create desc RX DMA tag\n");
1558 return error;
1559 }
1560
1561 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1562 &ring->map);
1563 if (error) {
1564 if_printf(&sc->arpcom.ac_if,
1565 "could not allocate RX desc DMA memory\n");
1566 bus_dma_tag_destroy(ring->tag);
1567 ring->tag = NULL;
1568 return error;
1569 }
1570
1571 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1572 sc->sc_rx_ring_count * descsize,
1573 nfe_ring_dma_addr, &ring->physaddr,
1574 BUS_DMA_WAITOK);
1575 if (error) {
1576 if_printf(&sc->arpcom.ac_if,
1577 "could not load RX desc DMA map\n");
1578 bus_dmamem_free(ring->tag, *desc, ring->map);
1579 bus_dma_tag_destroy(ring->tag);
1580 ring->tag = NULL;
1581 return error;
1582 }
1583
1584 if (sc->sc_flags & NFE_JUMBO_SUP) {
1585 error = nfe_jpool_alloc(sc, ring);
1586 if (error) {
1587 if_printf(&sc->arpcom.ac_if,
1588 "could not allocate jumbo frames\n");
1589 return error;
1590 }
1591 }
1592
1593 error = bus_dma_tag_create(NULL, 1, 0,
1594 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1595 NULL, NULL,
1596 MCLBYTES, 1, MCLBYTES,
1597 0, &ring->data_tag);
1598 if (error) {
1599 if_printf(&sc->arpcom.ac_if,
1600 "could not create RX mbuf DMA tag\n");
1601 return error;
1602 }
1603
1604 /* Create a spare RX mbuf DMA map */
1605 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1606 if (error) {
1607 if_printf(&sc->arpcom.ac_if,
1608 "could not create spare RX mbuf DMA map\n");
1609 bus_dma_tag_destroy(ring->data_tag);
1610 ring->data_tag = NULL;
1611 return error;
1612 }
1613
1614 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1615 error = bus_dmamap_create(ring->data_tag, 0,
1616 &ring->data[i].map);
1617 if (error) {
1618 if_printf(&sc->arpcom.ac_if,
1619 "could not create %dth RX mbuf DMA mapn", i);
1620 goto fail;
1621 }
1622 }
1623 return 0;
1624 fail:
1625 for (j = 0; j < i; ++j)
1626 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1627 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1628 bus_dma_tag_destroy(ring->data_tag);
1629 ring->data_tag = NULL;
1630 return error;
1631 }
1632
1633 static void
1634 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1635 {
1636 int i;
1637
1638 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1639 struct nfe_rx_data *data = &ring->data[i];
1640
1641 if (data->m != NULL) {
1642 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1643 bus_dmamap_unload(ring->data_tag, data->map);
1644 m_freem(data->m);
1645 data->m = NULL;
1646 }
1647 }
1648 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1649
1650 ring->cur = ring->next = 0;
1651 }
1652
1653 static int
1654 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1655 {
1656 int i;
1657
1658 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1659 int error;
1660
1661 /* XXX should use a function pointer */
1662 if (sc->sc_flags & NFE_USE_JUMBO)
1663 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1664 else
1665 error = nfe_newbuf_std(sc, ring, i, 1);
1666 if (error) {
1667 if_printf(&sc->arpcom.ac_if,
1668 "could not allocate RX buffer\n");
1669 return error;
1670 }
1671
1672 nfe_set_ready_rxdesc(sc, ring, i);
1673 }
1674 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1675
1676 return 0;
1677 }
1678
1679 static void
1680 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1681 {
1682 if (ring->data_tag != NULL) {
1683 struct nfe_rx_data *data;
1684 int i;
1685
1686 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1687 data = &ring->data[i];
1688
1689 if (data->m != NULL) {
1690 bus_dmamap_unload(ring->data_tag, data->map);
1691 m_freem(data->m);
1692 }
1693 bus_dmamap_destroy(ring->data_tag, data->map);
1694 }
1695 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1696 bus_dma_tag_destroy(ring->data_tag);
1697 }
1698
1699 nfe_jpool_free(sc, ring);
1700
1701 if (ring->jbuf != NULL)
1702 kfree(ring->jbuf, M_DEVBUF);
1703 if (ring->data != NULL)
1704 kfree(ring->data, M_DEVBUF);
1705
1706 if (ring->tag != NULL) {
1707 void *desc;
1708
1709 if (sc->sc_flags & NFE_40BIT_ADDR)
1710 desc = ring->desc64;
1711 else
1712 desc = ring->desc32;
1713
1714 bus_dmamap_unload(ring->tag, ring->map);
1715 bus_dmamem_free(ring->tag, desc, ring->map);
1716 bus_dma_tag_destroy(ring->tag);
1717 }
1718 }
1719
1720 static struct nfe_jbuf *
1721 nfe_jalloc(struct nfe_softc *sc)
1722 {
1723 struct ifnet *ifp = &sc->arpcom.ac_if;
1724 struct nfe_jbuf *jbuf;
1725
1726 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1727
1728 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1729 if (jbuf != NULL) {
1730 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1731 jbuf->inuse = 1;
1732 } else {
1733 if_printf(ifp, "no free jumbo buffer\n");
1734 }
1735
1736 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1737
1738 return jbuf;
1739 }
1740
1741 static void
1742 nfe_jfree(void *arg)
1743 {
1744 struct nfe_jbuf *jbuf = arg;
1745 struct nfe_softc *sc = jbuf->sc;
1746 struct nfe_rx_ring *ring = jbuf->ring;
1747
1748 if (&ring->jbuf[jbuf->slot] != jbuf)
1749 panic("%s: free wrong jumbo buffer\n", __func__);
1750 else if (jbuf->inuse == 0)
1751 panic("%s: jumbo buffer already freed\n", __func__);
1752
1753 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1754 atomic_subtract_int(&jbuf->inuse, 1);
1755 if (jbuf->inuse == 0)
1756 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1757 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1758 }
1759
1760 static void
1761 nfe_jref(void *arg)
1762 {
1763 struct nfe_jbuf *jbuf = arg;
1764 struct nfe_rx_ring *ring = jbuf->ring;
1765
1766 if (&ring->jbuf[jbuf->slot] != jbuf)
1767 panic("%s: ref wrong jumbo buffer\n", __func__);
1768 else if (jbuf->inuse == 0)
1769 panic("%s: jumbo buffer already freed\n", __func__);
1770
1771 atomic_add_int(&jbuf->inuse, 1);
1772 }
1773
1774 static int
1775 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1776 {
1777 struct nfe_jbuf *jbuf;
1778 bus_addr_t physaddr;
1779 caddr_t buf;
1780 int i, error;
1781
1782 /*
1783 * Allocate a big chunk of DMA'able memory.
1784 */
1785 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1786 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1787 NULL, NULL,
1788 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1789 0, &ring->jtag);
1790 if (error) {
1791 if_printf(&sc->arpcom.ac_if,
1792 "could not create jumbo DMA tag\n");
1793 return error;
1794 }
1795
1796 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1797 BUS_DMA_WAITOK, &ring->jmap);
1798 if (error) {
1799 if_printf(&sc->arpcom.ac_if,
1800 "could not allocate jumbo DMA memory\n");
1801 bus_dma_tag_destroy(ring->jtag);
1802 ring->jtag = NULL;
1803 return error;
1804 }
1805
1806 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1807 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1808 BUS_DMA_WAITOK);
1809 if (error) {
1810 if_printf(&sc->arpcom.ac_if,
1811 "could not load jumbo DMA map\n");
1812 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1813 bus_dma_tag_destroy(ring->jtag);
1814 ring->jtag = NULL;
1815 return error;
1816 }
1817
1818 /* ..and split it into 9KB chunks */
1819 SLIST_INIT(&ring->jfreelist);
1820
1821 buf = ring->jpool;
1822 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1823 jbuf = &ring->jbuf[i];
1824
1825 jbuf->sc = sc;
1826 jbuf->ring = ring;
1827 jbuf->inuse = 0;
1828 jbuf->slot = i;
1829 jbuf->buf = buf;
1830 jbuf->physaddr = physaddr;
1831
1832 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1833
1834 buf += NFE_JBYTES;
1835 physaddr += NFE_JBYTES;
1836 }
1837
1838 return 0;
1839 }
1840
1841 static void
1842 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1843 {
1844 if (ring->jtag != NULL) {
1845 bus_dmamap_unload(ring->jtag, ring->jmap);
1846 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1847 bus_dma_tag_destroy(ring->jtag);
1848 }
1849 }
1850
1851 static int
1852 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1853 {
1854 int i, j, error, descsize;
1855 void **desc;
1856
1857 if (sc->sc_flags & NFE_40BIT_ADDR) {
1858 desc = (void **)&ring->desc64;
1859 descsize = sizeof(struct nfe_desc64);
1860 } else {
1861 desc = (void **)&ring->desc32;
1862 descsize = sizeof(struct nfe_desc32);
1863 }
1864
1865 ring->queued = 0;
1866 ring->cur = ring->next = 0;
1867
1868 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1869 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1870 NULL, NULL,
1871 NFE_TX_RING_COUNT * descsize, 1,
1872 NFE_TX_RING_COUNT * descsize,
1873 0, &ring->tag);
1874 if (error) {
1875 if_printf(&sc->arpcom.ac_if,
1876 "could not create TX desc DMA map\n");
1877 return error;
1878 }
1879
1880 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1881 &ring->map);
1882 if (error) {
1883 if_printf(&sc->arpcom.ac_if,
1884 "could not allocate TX desc DMA memory\n");
1885 bus_dma_tag_destroy(ring->tag);
1886 ring->tag = NULL;
1887 return error;
1888 }
1889
1890 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1891 NFE_TX_RING_COUNT * descsize,
1892 nfe_ring_dma_addr, &ring->physaddr,
1893 BUS_DMA_WAITOK);
1894 if (error) {
1895 if_printf(&sc->arpcom.ac_if,
1896 "could not load TX desc DMA map\n");
1897 bus_dmamem_free(ring->tag, *desc, ring->map);
1898 bus_dma_tag_destroy(ring->tag);
1899 ring->tag = NULL;
1900 return error;
1901 }
1902
1903 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1904 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1905 NULL, NULL,
1906 NFE_JBYTES * NFE_MAX_SCATTER,
1907 NFE_MAX_SCATTER, NFE_JBYTES,
1908 0, &ring->data_tag);
1909 if (error) {
1910 if_printf(&sc->arpcom.ac_if,
1911 "could not create TX buf DMA tag\n");
1912 return error;
1913 }
1914
1915 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1916 error = bus_dmamap_create(ring->data_tag, 0,
1917 &ring->data[i].map);
1918 if (error) {
1919 if_printf(&sc->arpcom.ac_if,
1920 "could not create %dth TX buf DMA map\n", i);
1921 goto fail;
1922 }
1923 }
1924
1925 return 0;
1926 fail:
1927 for (j = 0; j < i; ++j)
1928 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1929 bus_dma_tag_destroy(ring->data_tag);
1930 ring->data_tag = NULL;
1931 return error;
1932 }
1933
1934 static void
1935 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1936 {
1937 int i;
1938
1939 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1940 struct nfe_tx_data *data = &ring->data[i];
1941
1942 if (sc->sc_flags & NFE_40BIT_ADDR)
1943 ring->desc64[i].flags = 0;
1944 else
1945 ring->desc32[i].flags = 0;
1946
1947 if (data->m != NULL) {
1948 bus_dmamap_sync(ring->data_tag, data->map,
1949 BUS_DMASYNC_POSTWRITE);
1950 bus_dmamap_unload(ring->data_tag, data->map);
1951 m_freem(data->m);
1952 data->m = NULL;
1953 }
1954 }
1955 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1956
1957 ring->queued = 0;
1958 ring->cur = ring->next = 0;
1959 }
1960
1961 static int
1962 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1963 struct nfe_tx_ring *ring __unused)
1964 {
1965 return 0;
1966 }
1967
1968 static void
1969 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1970 {
1971 if (ring->data_tag != NULL) {
1972 struct nfe_tx_data *data;
1973 int i;
1974
1975 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1976 data = &ring->data[i];
1977
1978 if (data->m != NULL) {
1979 bus_dmamap_unload(ring->data_tag, data->map);
1980 m_freem(data->m);
1981 }
1982 bus_dmamap_destroy(ring->data_tag, data->map);
1983 }
1984
1985 bus_dma_tag_destroy(ring->data_tag);
1986 }
1987
1988 if (ring->tag != NULL) {
1989 void *desc;
1990
1991 if (sc->sc_flags & NFE_40BIT_ADDR)
1992 desc = ring->desc64;
1993 else
1994 desc = ring->desc32;
1995
1996 bus_dmamap_unload(ring->tag, ring->map);
1997 bus_dmamem_free(ring->tag, desc, ring->map);
1998 bus_dma_tag_destroy(ring->tag);
1999 }
2000 }
2001
2002 static int
2003 nfe_ifmedia_upd(struct ifnet *ifp)
2004 {
2005 struct nfe_softc *sc = ifp->if_softc;
2006 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2007
2008 if (mii->mii_instance != 0) {
2009 struct mii_softc *miisc;
2010
2011 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2012 mii_phy_reset(miisc);
2013 }
2014 mii_mediachg(mii);
2015
2016 return 0;
2017 }
2018
2019 static void
2020 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2021 {
2022 struct nfe_softc *sc = ifp->if_softc;
2023 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2024
2025 mii_pollstat(mii);
2026 ifmr->ifm_status = mii->mii_media_status;
2027 ifmr->ifm_active = mii->mii_media_active;
2028 }
2029
2030 static void
2031 nfe_setmulti(struct nfe_softc *sc)
2032 {
2033 struct ifnet *ifp = &sc->arpcom.ac_if;
2034 struct ifmultiaddr *ifma;
2035 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2036 uint32_t filter = NFE_RXFILTER_MAGIC;
2037 int i;
2038
2039 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2040 bzero(addr, ETHER_ADDR_LEN);
2041 bzero(mask, ETHER_ADDR_LEN);
2042 goto done;
2043 }
2044
2045 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2046 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2047
2048 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2049 caddr_t maddr;
2050
2051 if (ifma->ifma_addr->sa_family != AF_LINK)
2052 continue;
2053
2054 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2055 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2056 addr[i] &= maddr[i];
2057 mask[i] &= ~maddr[i];
2058 }
2059 }
2060
2061 for (i = 0; i < ETHER_ADDR_LEN; i++)
2062 mask[i] |= addr[i];
2063
2064 done:
2065 addr[0] |= 0x01; /* make sure multicast bit is set */
2066
2067 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2068 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2069 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2070 addr[5] << 8 | addr[4]);
2071 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2072 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2073 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2074 mask[5] << 8 | mask[4]);
2075
2076 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2077 NFE_WRITE(sc, NFE_RXFILTER, filter);
2078 }
2079
2080 static void
2081 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2082 {
2083 uint32_t tmp;
2084
2085 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2086 addr[0] = (tmp >> 8) & 0xff;
2087 addr[1] = (tmp & 0xff);
2088
2089 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2090 addr[2] = (tmp >> 24) & 0xff;
2091 addr[3] = (tmp >> 16) & 0xff;
2092 addr[4] = (tmp >> 8) & 0xff;
2093 addr[5] = (tmp & 0xff);
2094 }
2095
2096 static void
2097 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2098 {
2099 NFE_WRITE(sc, NFE_MACADDR_LO,
2100 addr[5] << 8 | addr[4]);
2101 NFE_WRITE(sc, NFE_MACADDR_HI,
2102 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2103 }
2104
2105 static void
2106 nfe_tick(void *arg)
2107 {
2108 struct nfe_softc *sc = arg;
2109 struct ifnet *ifp = &sc->arpcom.ac_if;
2110 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2111
2112 lwkt_serialize_enter(ifp->if_serializer);
2113
2114 mii_tick(mii);
2115 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2116
2117 lwkt_serialize_exit(ifp->if_serializer);
2118 }
2119
2120 static void
2121 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2122 {
2123 if (error)
2124 return;
2125
2126 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2127
2128 *((uint32_t *)arg) = seg->ds_addr;
2129 }
2130
2131 static void
2132 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2133 bus_size_t mapsz __unused, int error)
2134 {
2135 struct nfe_dma_ctx *ctx = arg;
2136 int i;
2137
2138 if (error)
2139 return;
2140
2141 KASSERT(nsegs <= ctx->nsegs,
2142 ("too many segments(%d), should be <= %d\n",
2143 nsegs, ctx->nsegs));
2144
2145 ctx->nsegs = nsegs;
2146 for (i = 0; i < nsegs; ++i)
2147 ctx->segs[i] = segs[i];
2148 }
2149
2150 static int
2151 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2152 int wait)
2153 {
2154 struct nfe_rx_data *data = &ring->data[idx];
2155 struct nfe_dma_ctx ctx;
2156 bus_dma_segment_t seg;
2157 bus_dmamap_t map;
2158 struct mbuf *m;
2159 int error;
2160
2161 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2162 if (m == NULL)
2163 return ENOBUFS;
2164 m->m_len = m->m_pkthdr.len = MCLBYTES;
2165
2166 ctx.nsegs = 1;
2167 ctx.segs = &seg;
2168 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2169 m, nfe_buf_dma_addr, &ctx,
2170 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2171 if (error) {
2172 m_freem(m);
2173 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2174 return error;
2175 }
2176
2177 /* Unload originally mapped mbuf */
2178 bus_dmamap_unload(ring->data_tag, data->map);
2179
2180 /* Swap this DMA map with tmp DMA map */
2181 map = data->map;
2182 data->map = ring->data_tmpmap;
2183 ring->data_tmpmap = map;
2184
2185 /* Caller is assumed to have collected the old mbuf */
2186 data->m = m;
2187
2188 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2189
2190 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2191 return 0;
2192 }
2193
2194 static int
2195 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2196 int wait)
2197 {
2198 struct nfe_rx_data *data = &ring->data[idx];
2199 struct nfe_jbuf *jbuf;
2200 struct mbuf *m;
2201
2202 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2203 if (m == NULL)
2204 return ENOBUFS;
2205
2206 jbuf = nfe_jalloc(sc);
2207 if (jbuf == NULL) {
2208 m_freem(m);
2209 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2210 "-- packet dropped!\n");
2211 return ENOBUFS;
2212 }
2213
2214 m->m_ext.ext_arg = jbuf;
2215 m->m_ext.ext_buf = jbuf->buf;
2216 m->m_ext.ext_free = nfe_jfree;
2217 m->m_ext.ext_ref = nfe_jref;
2218 m->m_ext.ext_size = NFE_JBYTES;
2219
2220 m->m_data = m->m_ext.ext_buf;
2221 m->m_flags |= M_EXT;
2222 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2223
2224 /* Caller is assumed to have collected the old mbuf */
2225 data->m = m;
2226
2227 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2228
2229 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2230 return 0;
2231 }
2232
2233 static void
2234 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2235 bus_addr_t physaddr)
2236 {
2237 if (sc->sc_flags & NFE_40BIT_ADDR) {
2238 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2239
2240 #if defined(__LP64__)
2241 desc64->physaddr[0] = htole32(physaddr >> 32);
2242 #endif
2243 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2244 } else {
2245 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2246
2247 desc32->physaddr = htole32(physaddr);
2248 }
2249 }
2250
2251 static void
2252 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2253 {
2254 if (sc->sc_flags & NFE_40BIT_ADDR) {
2255 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2256
2257 desc64->length = htole16(ring->bufsz);
2258 desc64->flags = htole16(NFE_RX_READY);
2259 } else {
2260 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2261
2262 desc32->length = htole16(ring->bufsz);
2263 desc32->flags = htole16(NFE_RX_READY);
2264 }
2265 }
2266
2267 static int
2268 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2269 {
2270 struct nfe_softc *sc = arg1;
2271 struct ifnet *ifp = &sc->arpcom.ac_if;
2272 int error, v;
2273
2274 lwkt_serialize_enter(ifp->if_serializer);
2275
2276 v = sc->sc_imtime;
2277 error = sysctl_handle_int(oidp, &v, 0, req);
2278 if (error || req->newptr == NULL)
2279 goto back;
2280 if (v == 0) {
2281 error = EINVAL;
2282 goto back;
2283 }
2284
2285 if (sc->sc_imtime != v) {
2286 int old_imtime = sc->sc_imtime;
2287
2288 sc->sc_imtime = v;
2289 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2290
2291 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2292 == IFF_RUNNING) {
2293 if (old_imtime > 0 && sc->sc_imtime > 0) {
2294 NFE_WRITE(sc, NFE_IMTIMER,
2295 NFE_IMTIME(sc->sc_imtime));
2296 } else if ((old_imtime * sc->sc_imtime) < 0) {
2297 ifp->if_init(sc);
2298 }
2299 }
2300 }
2301 back:
2302 lwkt_serialize_exit(ifp->if_serializer);
2303 return error;
2304 }
DragonFly BSD