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drm: Implement and use Linux struct device
[dragonfly.git] / sys / dev / drm / radeon / radeon_kms.c
blobb7bc60755ec973f4494a39e3155aaefbe039f5ec
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <drm/drmP.h>
29 #include "radeon.h"
30 #include <uapi_drm/radeon_drm.h>
31 #include "radeon_asic.h"
32 #include "radeon_kms.h"
33
34 #include <linux/slab.h>
35 #ifdef PM_TODO
36 #include <linux/pm_runtime.h>
37 #endif
38
39 #ifdef PM_TODO
40 #if defined(CONFIG_VGA_SWITCHEROO)
41 bool radeon_has_atpx(void);
42 #else
43 static inline bool radeon_has_atpx(void) { return false; }
44 #endif
45 #endif
46
47 /**
48 * radeon_driver_unload_kms - Main unload function for KMS.
49 *
50 * @dev: drm dev pointer
51 *
52 * This is the main unload function for KMS (all asics).
53 * It calls radeon_modeset_fini() to tear down the
54 * displays, and radeon_device_fini() to tear down
55 * the rest of the device (CP, writeback, etc.).
56 * Returns 0 on success.
57 */
58 int radeon_driver_unload_kms(struct drm_device *dev)
59 {
60 struct radeon_device *rdev = dev->dev_private;
61
62 if (rdev == NULL)
63 return 0;
64
65 if (rdev->rmmio == NULL)
66 goto done_free;
67
68 #ifdef PM_TODO
69 pm_runtime_get_sync(dev->dev);
70 #endif
71
72 radeon_acpi_fini(rdev);
73 radeon_modeset_fini(rdev);
74 radeon_device_fini(rdev);
75
76 done_free:
77 /* XXX pending drm update, after this accessing pdev is illegal! */
78 drm_fini_pdev(&dev->pdev);
79 kfree(rdev);
80 dev->dev_private = NULL;
81 return 0;
82 }
83
84 /**
85 * radeon_driver_load_kms - Main load function for KMS.
86 *
87 * @dev: drm dev pointer
88 * @flags: device flags
89 *
90 * This is the main load function for KMS (all asics).
91 * It calls radeon_device_init() to set up the non-display
92 * parts of the chip (asic init, CP, writeback, etc.), and
93 * radeon_modeset_init() to set up the display parts
94 * (crtcs, encoders, hotplug detect, etc.).
95 * Returns 0 on success, error on failure.
96 */
97 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
98 {
99 struct radeon_device *rdev;
100 int r, acpi_status;
101
102 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
103 if (rdev == NULL) {
104 return -ENOMEM;
105 }
106 dev->dev_private = (void *)rdev;
107
108 /* update BUS flag */
109 if (drm_pci_device_is_agp(dev)) {
110 DRM_INFO("RADEON_IS_AGP\n");
111 flags |= RADEON_IS_AGP;
112 } else if (pci_is_pcie(dev->dev->bsddev)) {
113 DRM_INFO("RADEON_IS_PCIE\n");
114 flags |= RADEON_IS_PCIE;
115 } else {
116 DRM_INFO("RADEON_IS_PCI\n");
117 flags |= RADEON_IS_PCI;
118 }
119
120 #ifdef PM_TODO
121 if ((radeon_runtime_pm != 0) &&
122 radeon_has_atpx() &&
123 ((flags & RADEON_IS_IGP) == 0))
124 #endif
125
126 /* radeon_device_init should report only fatal error
127 * like memory allocation failure or iomapping failure,
128 * or memory manager initialization failure, it must
129 * properly initialize the GPU MC controller and permit
130 * VRAM allocation
131 */
132 r = radeon_device_init(rdev, dev, dev->pdev, flags);
133 if (r) {
134 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
135 goto out;
136 }
137
138 /* Again modeset_init should fail only on fatal error
139 * otherwise it should provide enough functionalities
140 * for shadowfb to run
141 */
142 r = radeon_modeset_init(rdev);
143 if (r)
144 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
145
146 /* Call ACPI methods: require modeset init
147 * but failure is not fatal
148 */
149 if (!r) {
150 acpi_status = radeon_acpi_init(rdev);
151 if (acpi_status)
152 dev_dbg(&dev->pdev->dev,
153 "Error during ACPI methods call\n");
154 }
155
156 #ifdef PM_TODO
157 if (radeon_is_px(dev)) {
158 pm_runtime_use_autosuspend(dev->dev);
159 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
160 pm_runtime_set_active(dev->dev);
161 pm_runtime_allow(dev->dev);
162 pm_runtime_mark_last_busy(dev->dev);
163 pm_runtime_put_autosuspend(dev->dev);
164 }
165 #endif
166
167 out:
168 if (r)
169 radeon_driver_unload_kms(dev);
170
171
172 return r;
173 }
174
175 /**
176 * radeon_set_filp_rights - Set filp right.
177 *
178 * @dev: drm dev pointer
179 * @owner: drm file
180 * @applier: drm file
181 * @value: value
182 *
183 * Sets the filp rights for the device (all asics).
184 */
185 static void radeon_set_filp_rights(struct drm_device *dev,
186 struct drm_file **owner,
187 struct drm_file *applier,
188 uint32_t *value)
189 {
190 mutex_lock(&dev->struct_mutex);
191 if (*value == 1) {
192 /* wants rights */
193 if (!*owner)
194 *owner = applier;
195 } else if (*value == 0) {
196 /* revokes rights */
197 if (*owner == applier)
198 *owner = NULL;
199 }
200 *value = *owner == applier ? 1 : 0;
201 mutex_unlock(&dev->struct_mutex);
202 }
203
204 /*
205 * Userspace get information ioctl
206 */
207 /**
208 * radeon_info_ioctl - answer a device specific request.
209 *
210 * @rdev: radeon device pointer
211 * @data: request object
212 * @filp: drm filp
213 *
214 * This function is used to pass device specific parameters to the userspace
215 * drivers. Examples include: pci device id, pipeline parms, tiling params,
216 * etc. (all asics).
217 * Returns 0 on success, -EINVAL on failure.
218 */
219 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
220 {
221 struct radeon_device *rdev = dev->dev_private;
222 struct drm_radeon_info *info = data;
223 struct radeon_mode_info *minfo = &rdev->mode_info;
224 uint32_t *value, value_tmp, *value_ptr, value_size;
225 uint64_t value64;
226 struct drm_crtc *crtc;
227 int i, found;
228
229 value_ptr = (uint32_t *)((unsigned long)info->value);
230 value = &value_tmp;
231 value_size = sizeof(uint32_t);
232
233 switch (info->request) {
234 case RADEON_INFO_DEVICE_ID:
235 *value = dev->pdev->device;
236 break;
237 case RADEON_INFO_NUM_GB_PIPES:
238 *value = rdev->num_gb_pipes;
239 break;
240 case RADEON_INFO_NUM_Z_PIPES:
241 *value = rdev->num_z_pipes;
242 break;
243 case RADEON_INFO_ACCEL_WORKING:
244 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
245 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
246 *value = false;
247 else
248 *value = rdev->accel_working;
249 break;
250 case RADEON_INFO_CRTC_FROM_ID:
251 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
252 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
253 return -EFAULT;
254 }
255 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
256 crtc = (struct drm_crtc *)minfo->crtcs[i];
257 if (crtc && crtc->base.id == *value) {
258 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
259 *value = radeon_crtc->crtc_id;
260 found = 1;
261 break;
262 }
263 }
264 if (!found) {
265 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
266 return -EINVAL;
267 }
268 break;
269 case RADEON_INFO_ACCEL_WORKING2:
270 if (rdev->family == CHIP_HAWAII) {
271 if (rdev->accel_working) {
272 if (rdev->new_fw)
273 *value = 3;
274 else
275 *value = 2;
276 } else {
277 *value = 0;
278 }
279 } else {
280 *value = rdev->accel_working;
281 }
282 break;
283 case RADEON_INFO_TILING_CONFIG:
284 if (rdev->family >= CHIP_BONAIRE)
285 *value = rdev->config.cik.tile_config;
286 else if (rdev->family >= CHIP_TAHITI)
287 *value = rdev->config.si.tile_config;
288 else if (rdev->family >= CHIP_CAYMAN)
289 *value = rdev->config.cayman.tile_config;
290 else if (rdev->family >= CHIP_CEDAR)
291 *value = rdev->config.evergreen.tile_config;
292 else if (rdev->family >= CHIP_RV770)
293 *value = rdev->config.rv770.tile_config;
294 else if (rdev->family >= CHIP_R600)
295 *value = rdev->config.r600.tile_config;
296 else {
297 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
298 return -EINVAL;
299 }
300 break;
301 case RADEON_INFO_WANT_HYPERZ:
302 /* The "value" here is both an input and output parameter.
303 * If the input value is 1, filp requests hyper-z access.
304 * If the input value is 0, filp revokes its hyper-z access.
305 *
306 * When returning, the value is 1 if filp owns hyper-z access,
307 * 0 otherwise. */
308 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
309 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
310 return -EFAULT;
311 }
312 if (*value >= 2) {
313 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
314 return -EINVAL;
315 }
316 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
317 break;
318 case RADEON_INFO_WANT_CMASK:
319 /* The same logic as Hyper-Z. */
320 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
321 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
322 return -EFAULT;
323 }
324 if (*value >= 2) {
325 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
326 return -EINVAL;
327 }
328 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
329 break;
330 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
331 /* return clock value in KHz */
332 if (rdev->asic->get_xclk)
333 *value = radeon_get_xclk(rdev) * 10;
334 else
335 *value = rdev->clock.spll.reference_freq * 10;
336 break;
337 case RADEON_INFO_NUM_BACKENDS:
338 if (rdev->family >= CHIP_BONAIRE)
339 *value = rdev->config.cik.max_backends_per_se *
340 rdev->config.cik.max_shader_engines;
341 else if (rdev->family >= CHIP_TAHITI)
342 *value = rdev->config.si.max_backends_per_se *
343 rdev->config.si.max_shader_engines;
344 else if (rdev->family >= CHIP_CAYMAN)
345 *value = rdev->config.cayman.max_backends_per_se *
346 rdev->config.cayman.max_shader_engines;
347 else if (rdev->family >= CHIP_CEDAR)
348 *value = rdev->config.evergreen.max_backends;
349 else if (rdev->family >= CHIP_RV770)
350 *value = rdev->config.rv770.max_backends;
351 else if (rdev->family >= CHIP_R600)
352 *value = rdev->config.r600.max_backends;
353 else {
354 return -EINVAL;
355 }
356 break;
357 case RADEON_INFO_NUM_TILE_PIPES:
358 if (rdev->family >= CHIP_BONAIRE)
359 *value = rdev->config.cik.max_tile_pipes;
360 else if (rdev->family >= CHIP_TAHITI)
361 *value = rdev->config.si.max_tile_pipes;
362 else if (rdev->family >= CHIP_CAYMAN)
363 *value = rdev->config.cayman.max_tile_pipes;
364 else if (rdev->family >= CHIP_CEDAR)
365 *value = rdev->config.evergreen.max_tile_pipes;
366 else if (rdev->family >= CHIP_RV770)
367 *value = rdev->config.rv770.max_tile_pipes;
368 else if (rdev->family >= CHIP_R600)
369 *value = rdev->config.r600.max_tile_pipes;
370 else {
371 return -EINVAL;
372 }
373 break;
374 case RADEON_INFO_FUSION_GART_WORKING:
375 *value = 1;
376 break;
377 case RADEON_INFO_BACKEND_MAP:
378 if (rdev->family >= CHIP_BONAIRE)
379 *value = rdev->config.cik.backend_map;
380 else if (rdev->family >= CHIP_TAHITI)
381 *value = rdev->config.si.backend_map;
382 else if (rdev->family >= CHIP_CAYMAN)
383 *value = rdev->config.cayman.backend_map;
384 else if (rdev->family >= CHIP_CEDAR)
385 *value = rdev->config.evergreen.backend_map;
386 else if (rdev->family >= CHIP_RV770)
387 *value = rdev->config.rv770.backend_map;
388 else if (rdev->family >= CHIP_R600)
389 *value = rdev->config.r600.backend_map;
390 else {
391 return -EINVAL;
392 }
393 break;
394 case RADEON_INFO_VA_START:
395 /* this is where we report if vm is supported or not */
396 if (rdev->family < CHIP_CAYMAN)
397 return -EINVAL;
398 *value = RADEON_VA_RESERVED_SIZE;
399 break;
400 case RADEON_INFO_IB_VM_MAX_SIZE:
401 /* this is where we report if vm is supported or not */
402 if (rdev->family < CHIP_CAYMAN)
403 return -EINVAL;
404 *value = RADEON_IB_VM_MAX_SIZE;
405 break;
406 case RADEON_INFO_MAX_PIPES:
407 if (rdev->family >= CHIP_BONAIRE)
408 *value = rdev->config.cik.max_cu_per_sh;
409 else if (rdev->family >= CHIP_TAHITI)
410 *value = rdev->config.si.max_cu_per_sh;
411 else if (rdev->family >= CHIP_CAYMAN)
412 *value = rdev->config.cayman.max_pipes_per_simd;
413 else if (rdev->family >= CHIP_CEDAR)
414 *value = rdev->config.evergreen.max_pipes;
415 else if (rdev->family >= CHIP_RV770)
416 *value = rdev->config.rv770.max_pipes;
417 else if (rdev->family >= CHIP_R600)
418 *value = rdev->config.r600.max_pipes;
419 else {
420 return -EINVAL;
421 }
422 break;
423 case RADEON_INFO_TIMESTAMP:
424 if (rdev->family < CHIP_R600) {
425 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
426 return -EINVAL;
427 }
428 value = (uint32_t*)&value64;
429 value_size = sizeof(uint64_t);
430 value64 = radeon_get_gpu_clock_counter(rdev);
431 break;
432 case RADEON_INFO_MAX_SE:
433 if (rdev->family >= CHIP_BONAIRE)
434 *value = rdev->config.cik.max_shader_engines;
435 else if (rdev->family >= CHIP_TAHITI)
436 *value = rdev->config.si.max_shader_engines;
437 else if (rdev->family >= CHIP_CAYMAN)
438 *value = rdev->config.cayman.max_shader_engines;
439 else if (rdev->family >= CHIP_CEDAR)
440 *value = rdev->config.evergreen.num_ses;
441 else
442 *value = 1;
443 break;
444 case RADEON_INFO_MAX_SH_PER_SE:
445 if (rdev->family >= CHIP_BONAIRE)
446 *value = rdev->config.cik.max_sh_per_se;
447 else if (rdev->family >= CHIP_TAHITI)
448 *value = rdev->config.si.max_sh_per_se;
449 else
450 return -EINVAL;
451 break;
452 case RADEON_INFO_FASTFB_WORKING:
453 *value = rdev->fastfb_working;
454 break;
455 case RADEON_INFO_RING_WORKING:
456 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
457 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
458 return -EFAULT;
459 }
460 switch (*value) {
461 case RADEON_CS_RING_GFX:
462 case RADEON_CS_RING_COMPUTE:
463 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
464 break;
465 case RADEON_CS_RING_DMA:
466 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
467 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
468 break;
469 case RADEON_CS_RING_UVD:
470 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
471 break;
472 case RADEON_CS_RING_VCE:
473 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
474 break;
475 default:
476 return -EINVAL;
477 }
478 break;
479 case RADEON_INFO_SI_TILE_MODE_ARRAY:
480 if (rdev->family >= CHIP_BONAIRE) {
481 value = rdev->config.cik.tile_mode_array;
482 value_size = sizeof(uint32_t)*32;
483 } else if (rdev->family >= CHIP_TAHITI) {
484 value = rdev->config.si.tile_mode_array;
485 value_size = sizeof(uint32_t)*32;
486 } else {
487 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
488 return -EINVAL;
489 }
490 break;
491 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
492 if (rdev->family >= CHIP_BONAIRE) {
493 value = rdev->config.cik.macrotile_mode_array;
494 value_size = sizeof(uint32_t)*16;
495 } else {
496 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
497 return -EINVAL;
498 }
499 break;
500 case RADEON_INFO_SI_CP_DMA_COMPUTE:
501 *value = 1;
502 break;
503 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
504 if (rdev->family >= CHIP_BONAIRE) {
505 *value = rdev->config.cik.backend_enable_mask;
506 } else if (rdev->family >= CHIP_TAHITI) {
507 *value = rdev->config.si.backend_enable_mask;
508 } else {
509 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
510 }
511 break;
512 case RADEON_INFO_MAX_SCLK:
513 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
514 rdev->pm.dpm_enabled)
515 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
516 else
517 *value = rdev->pm.default_sclk * 10;
518 break;
519 case RADEON_INFO_VCE_FW_VERSION:
520 *value = rdev->vce.fw_version;
521 break;
522 case RADEON_INFO_VCE_FB_VERSION:
523 *value = rdev->vce.fb_version;
524 break;
525 case RADEON_INFO_NUM_BYTES_MOVED:
526 value = (uint32_t*)&value64;
527 value_size = sizeof(uint64_t);
528 value64 = atomic64_read(&rdev->num_bytes_moved);
529 break;
530 case RADEON_INFO_VRAM_USAGE:
531 value = (uint32_t*)&value64;
532 value_size = sizeof(uint64_t);
533 value64 = atomic64_read(&rdev->vram_usage);
534 break;
535 case RADEON_INFO_GTT_USAGE:
536 value = (uint32_t*)&value64;
537 value_size = sizeof(uint64_t);
538 value64 = atomic64_read(&rdev->gtt_usage);
539 break;
540 case RADEON_INFO_ACTIVE_CU_COUNT:
541 if (rdev->family >= CHIP_BONAIRE)
542 *value = rdev->config.cik.active_cus;
543 else if (rdev->family >= CHIP_TAHITI)
544 *value = rdev->config.si.active_cus;
545 else if (rdev->family >= CHIP_CAYMAN)
546 *value = rdev->config.cayman.active_simds;
547 else if (rdev->family >= CHIP_CEDAR)
548 *value = rdev->config.evergreen.active_simds;
549 else if (rdev->family >= CHIP_RV770)
550 *value = rdev->config.rv770.active_simds;
551 else if (rdev->family >= CHIP_R600)
552 *value = rdev->config.r600.active_simds;
553 else
554 *value = 1;
555 break;
556 default:
557 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
558 return -EINVAL;
559 }
560 if (copy_to_user(value_ptr, (char*)value, value_size)) {
561 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
562 return -EFAULT;
563 }
564 return 0;
565 }
566
567
568 /*
569 * Outdated mess for old drm with Xorg being in charge (void function now).
570 */
571 /**
572 * radeon_driver_firstopen_kms - drm callback for last close
573 *
574 * @dev: drm dev pointer
575 *
576 * Switch vga switcheroo state after last close (all asics).
577 */
578 void radeon_driver_lastclose_kms(struct drm_device *dev)
579 {
580 #ifdef DUMBBELL_WIP
581 vga_switcheroo_process_delayed_switch();
582 #endif /* DUMBBELL_WIP */
583 }
584
585 /**
586 * radeon_driver_open_kms - drm callback for open
587 *
588 * @dev: drm dev pointer
589 * @file_priv: drm file
590 *
591 * On device open, init vm on cayman+ (all asics).
592 * Returns 0 on success, error on failure.
593 */
594 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
595 {
596 struct radeon_device *rdev = dev->dev_private;
597
598 file_priv->driver_priv = NULL;
599
600 #ifdef PM_TODO
601 r = pm_runtime_get_sync(dev->dev);
602 if (r < 0)
603 return r;
604 #endif
605
606 /* new gpu have virtual address space support */
607 if (rdev->family >= CHIP_CAYMAN) {
608 struct radeon_fpriv *fpriv;
609 struct radeon_vm *vm;
610 int r;
611
612 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
613 if (unlikely(!fpriv)) {
614 return -ENOMEM;
615 }
616
617 vm = &fpriv->vm;
618 r = radeon_vm_init(rdev, vm);
619 if (r) {
620 kfree(fpriv);
621 return r;
622 }
623
624 if (rdev->accel_working) {
625 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
626 if (r) {
627 radeon_vm_fini(rdev, vm);
628 kfree(fpriv);
629 return r;
630 }
631
632 /* map the ib pool buffer read only into
633 * virtual address space */
634 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
635 rdev->ring_tmp_bo.bo);
636 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
637 RADEON_VA_IB_OFFSET,
638 RADEON_VM_PAGE_READABLE |
639 RADEON_VM_PAGE_SNOOPED);
640
641 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
642 if (r) {
643 radeon_vm_fini(rdev, vm);
644 kfree(fpriv);
645 return r;
646 }
647 }
648 file_priv->driver_priv = fpriv;
649 }
650
651 #ifdef PM_TODO
652 pm_runtime_mark_last_busy(dev->dev);
653 pm_runtime_put_autosuspend(dev->dev);
654 #endif
655 return 0;
656 }
657
658 /**
659 * radeon_driver_postclose_kms - drm callback for post close
660 *
661 * @dev: drm dev pointer
662 * @file_priv: drm file
663 *
664 * On device post close, tear down vm on cayman+ (all asics).
665 */
666 void radeon_driver_postclose_kms(struct drm_device *dev,
667 struct drm_file *file_priv)
668 {
669 struct radeon_device *rdev = dev->dev_private;
670
671 /* new gpu have virtual address space support */
672 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
673 struct radeon_fpriv *fpriv = file_priv->driver_priv;
674 struct radeon_vm *vm = &fpriv->vm;
675 int r;
676
677 if (rdev->accel_working) {
678 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
679 if (!r) {
680 if (vm->ib_bo_va)
681 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
682 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
683 }
684 }
685
686 radeon_vm_fini(rdev, vm);
687 kfree(fpriv);
688 file_priv->driver_priv = NULL;
689 }
690 }
691
692 /**
693 * radeon_driver_preclose_kms - drm callback for pre close
694 *
695 * @dev: drm dev pointer
696 * @file_priv: drm file
697 *
698 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
699 * (all asics).
700 */
701 void radeon_driver_preclose_kms(struct drm_device *dev,
702 struct drm_file *file_priv)
703 {
704 struct radeon_device *rdev = dev->dev_private;
705 if (rdev->hyperz_filp == file_priv)
706 rdev->hyperz_filp = NULL;
707 if (rdev->cmask_filp == file_priv)
708 rdev->cmask_filp = NULL;
709 radeon_uvd_free_handles(rdev, file_priv);
710 radeon_vce_free_handles(rdev, file_priv);
711 }
712
713 /*
714 * VBlank related functions.
715 */
716 /**
717 * radeon_get_vblank_counter_kms - get frame count
718 *
719 * @dev: drm dev pointer
720 * @crtc: crtc to get the frame count from
721 *
722 * Gets the frame count on the requested crtc (all asics).
723 * Returns frame count on success, -EINVAL on failure.
724 */
725 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
726 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
727 {
728 int vpos, hpos, stat;
729 u32 count;
730 struct radeon_device *rdev = dev->dev_private;
731
732 if (crtc < 0 || crtc >= rdev->num_crtc) {
733 DRM_ERROR("Invalid crtc %d\n", crtc);
734 return -EINVAL;
735 }
736
737 /* The hw increments its frame counter at start of vsync, not at start
738 * of vblank, as is required by DRM core vblank counter handling.
739 * Cook the hw count here to make it appear to the caller as if it
740 * incremented at start of vblank. We measure distance to start of
741 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
742 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
743 * result by 1 to give the proper appearance to caller.
744 */
745 if (rdev->mode_info.crtcs[crtc]) {
746 /* Repeat readout if needed to provide stable result if
747 * we cross start of vsync during the queries.
748 */
749 do {
750 count = radeon_get_vblank_counter(rdev, crtc);
751 /* Ask radeon_get_crtc_scanoutpos to return vpos as
752 * distance to start of vblank, instead of regular
753 * vertical scanout pos.
754 */
755 stat = radeon_get_crtc_scanoutpos(
756 dev, crtc, GET_DISTANCE_TO_VBLANKSTART,
757 &vpos, &hpos, NULL, NULL,
758 &rdev->mode_info.crtcs[crtc]->base.hwmode);
759 } while (count != radeon_get_vblank_counter(rdev, crtc));
760
761 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
762 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
763 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
764 }
765 else {
766 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
767 crtc, vpos);
768
769 /* Bump counter if we are at >= leading edge of vblank,
770 * but before vsync where vpos would turn negative and
771 * the hw counter really increments.
772 */
773 if (vpos >= 0)
774 count++;
775 }
776 }
777 else {
778 /* Fallback to use value as is. */
779 count = radeon_get_vblank_counter(rdev, crtc);
780 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
781 }
782
783 return count;
784 }
785
786 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
787 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
788 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
789 int *max_error,
790 struct timeval *vblank_time,
791 unsigned flags);
792
793 /**
794 * radeon_enable_vblank_kms - enable vblank interrupt
795 *
796 * @dev: drm dev pointer
797 * @crtc: crtc to enable vblank interrupt for
798 *
799 * Enable the interrupt on the requested crtc (all asics).
800 * Returns 0 on success, -EINVAL on failure.
801 */
802 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
803 {
804 struct radeon_device *rdev = dev->dev_private;
805 unsigned long irqflags;
806 int r;
807
808 if (crtc < 0 || crtc >= rdev->num_crtc) {
809 DRM_ERROR("Invalid crtc %d\n", crtc);
810 return -EINVAL;
811 }
812
813 spin_lock_irqsave(&rdev->irq.lock, irqflags);
814 rdev->irq.crtc_vblank_int[crtc] = true;
815 r = radeon_irq_set(rdev);
816 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
817 return r;
818 }
819
820 /**
821 * radeon_disable_vblank_kms - disable vblank interrupt
822 *
823 * @dev: drm dev pointer
824 * @crtc: crtc to disable vblank interrupt for
825 *
826 * Disable the interrupt on the requested crtc (all asics).
827 */
828 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
829 {
830 struct radeon_device *rdev = dev->dev_private;
831 unsigned long irqflags;
832
833 if (crtc < 0 || crtc >= rdev->num_crtc) {
834 DRM_ERROR("Invalid crtc %d\n", crtc);
835 return;
836 }
837
838 spin_lock_irqsave(&rdev->irq.lock, irqflags);
839 rdev->irq.crtc_vblank_int[crtc] = false;
840 radeon_irq_set(rdev);
841 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
842 }
843
844 /**
845 * radeon_get_vblank_timestamp_kms - get vblank timestamp
846 *
847 * @dev: drm dev pointer
848 * @crtc: crtc to get the timestamp for
849 * @max_error: max error
850 * @vblank_time: time value
851 * @flags: flags passed to the driver
852 *
853 * Gets the timestamp on the requested crtc based on the
854 * scanout position. (all asics).
855 * Returns postive status flags on success, negative error on failure.
856 */
857 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
858 int *max_error,
859 struct timeval *vblank_time,
860 unsigned flags)
861 {
862 struct drm_crtc *drmcrtc;
863 struct radeon_device *rdev = dev->dev_private;
864
865 if (crtc < 0 || crtc >= dev->num_crtcs) {
866 DRM_ERROR("Invalid crtc %d\n", crtc);
867 return -EINVAL;
868 }
869
870 /* Get associated drm_crtc: */
871 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
872 if (!drmcrtc)
873 return -EINVAL;
874
875 /* Helper routine in DRM core does all the work: */
876 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
877 vblank_time, flags,
878 &drmcrtc->hwmode);
879 }
880
881 #define KMS_INVALID_IOCTL(name) \
882 static int name(struct drm_device *dev, void *data, struct drm_file \
883 *file_priv) \
884 { \
885 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
886 return -EINVAL; \
887 }
888
889 /*
890 * All these ioctls are invalid in kms world.
891 */
892 KMS_INVALID_IOCTL(radeon_cp_init_kms)
893 KMS_INVALID_IOCTL(radeon_cp_start_kms)
894 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
895 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
896 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
897 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
898 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
899 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
900 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
901 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
902 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
903 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
904 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
905 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
906 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
907 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
908 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
909 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
910 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
911 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
912 KMS_INVALID_IOCTL(radeon_mem_free_kms)
913 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
914 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
915 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
916 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
917 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
918 KMS_INVALID_IOCTL(radeon_surface_free_kms)
919
920
921 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
922 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
923 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
924 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
925 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
926 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
927 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
928 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
929 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
930 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
931 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
932 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
933 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
934 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
935 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
936 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
937 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
938 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
939 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
940 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
941 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
942 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
943 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
944 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
945 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
946 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
947 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
948 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
949 /* KMS */
950 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
951 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
952 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
953 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
954 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
955 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
956 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
957 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
963 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
964 };
965 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
DragonFly BSD