sys/dev/drm/i915/i915_gem_tiling.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32
  33 /**
  34  * DOC: buffer object tiling
  35  *
  36  * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
  37  * declare fence register requirements.
  38  *
  39  * In principle GEM doesn't care at all about the internal data layout of an
  40  * object, and hence it also doesn't care about tiling or swizzling. There's two
  41  * exceptions:
  42  *
  43  * - For X and Y tiling the hardware provides detilers for CPU access, so called
  44  *   fences. Since there's only a limited amount of them the kernel must manage
  45  *   these, and therefore userspace must tell the kernel the object tiling if it
  46  *   wants to use fences for detiling.
  47  * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
  48  *   depends upon the physical page frame number. When swapping such objects the
  49  *   page frame number might change and the kernel must be able to fix this up
  50  *   and hence now the tiling. Note that on a subset of platforms with
  51  *   asymmetric memory channel population the swizzling pattern changes in an
  52  *   unknown way, and for those the kernel simply forbids swapping completely.
  53  *
  54  * Since neither of this applies for new tiling layouts on modern platforms like
  55  * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
  56  * Anything else can be handled in userspace entirely without the kernel's
  57  * invovlement.
  58  */
  59
  60 /* Check pitch constriants for all chips & tiling formats */
  61 static bool
  62 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
  63 {
  64         int tile_width;
  65
  66         /* Linear is always fine */
  67         if (tiling_mode == I915_TILING_NONE)
  68                 return true;
  69
  70         if (IS_GEN2(dev) ||
  71             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
  72                 tile_width = 128;
  73         else
  74                 tile_width = 512;
  75
  76         /* check maximum stride & object size */
  77         /* i965+ stores the end address of the gtt mapping in the fence
  78          * reg, so dont bother to check the size */
  79         if (INTEL_INFO(dev)->gen >= 7) {
  80                 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
  81                         return false;
  82         } else if (INTEL_INFO(dev)->gen >= 4) {
  83                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
  84                         return false;
  85         } else {
  86                 if (stride > 8192)
  87                         return false;
  88
  89                 if (IS_GEN3(dev)) {
  90                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
  91                                 return false;
  92                 } else {
  93                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
  94                                 return false;
  95                 }
  96         }
  97
  98         if (stride < tile_width)
  99                 return false;
 100
 101         /* 965+ just needs multiples of tile width */
 102         if (INTEL_INFO(dev)->gen >= 4) {
 103                 if (stride & (tile_width - 1))
 104                         return false;
 105                 return true;
 106         }
 107
 108         /* Pre-965 needs power of two tile widths */
 109         if (stride & (stride - 1))
 110                 return false;
 111
 112         return true;
 113 }
 114
 115 /* Is the current GTT allocation valid for the change in tiling? */
 116 static bool
 117 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
 118 {
 119         u32 size;
 120
 121         if (tiling_mode == I915_TILING_NONE)
 122                 return true;
 123
 124         if (INTEL_INFO(obj->base.dev)->gen >= 4)
 125                 return true;
 126
 127         if (INTEL_INFO(obj->base.dev)->gen == 3) {
 128                 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
 129                         return false;
 130         } else {
 131                 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK)
 132                         return false;
 133         }
 134
 135         size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
 136         if (i915_gem_obj_ggtt_size(obj) != size)
 137                 return false;
 138
 139         if (i915_gem_obj_ggtt_offset(obj) & (size - 1))
 140                 return false;
 141
 142         return true;
 143 }
 144
 145 /**
 146  * i915_gem_set_tiling - IOCTL handler to set tiling mode
 147  * @dev: DRM device
 148  * @data: data pointer for the ioctl
 149  * @file: DRM file for the ioctl call
 150  *
 151  * Sets the tiling mode of an object, returning the required swizzling of
 152  * bit 6 of addresses in the object.
 153  *
 154  * Called by the user via ioctl.
 155  *
 156  * Returns:
 157  * Zero on success, negative errno on failure.
 158  */
 159 int
 160 i915_gem_set_tiling(struct drm_device *dev, void *data,
 161                    struct drm_file *file)
 162 {
 163         struct drm_i915_gem_set_tiling *args = data;
 164         struct drm_i915_private *dev_priv = dev->dev_private;
 165         struct drm_i915_gem_object *obj;
 166         int ret = 0;
 167
 168         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 169         if (&obj->base == NULL)
 170                 return -ENOENT;
 171
 172         if (!i915_tiling_ok(dev,
 173                             args->stride, obj->base.size, args->tiling_mode)) {
 174                 drm_gem_object_unreference_unlocked(&obj->base);
 175                 return -EINVAL;
 176         }
 177
 178         mutex_lock(&dev->struct_mutex);
 179         if (obj->pin_display || obj->framebuffer_references) {
 180                 ret = -EBUSY;
 181                 goto err;
 182         }
 183
 184         if (args->tiling_mode == I915_TILING_NONE) {
 185                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 186                 args->stride = 0;
 187         } else {
 188                 if (args->tiling_mode == I915_TILING_X)
 189                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 190                 else
 191                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 192
 193                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
 194                  * from aborting the application on sw fallbacks to bit 17,
 195                  * and we use the pread/pwrite bit17 paths to swizzle for it.
 196                  * If there was a user that was relying on the swizzle
 197                  * information for drm_intel_bo_map()ed reads/writes this would
 198                  * break it, but we don't have any of those.
 199                  */
 200                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 201                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 202                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 203                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 204
 205                 /* If we can't handle the swizzling, make it untiled. */
 206                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
 207                         args->tiling_mode = I915_TILING_NONE;
 208                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 209                         args->stride = 0;
 210                 }
 211         }
 212
 213         if (args->tiling_mode != obj->tiling_mode ||
 214             args->stride != obj->stride) {
 215                 /* We need to rebind the object if its current allocation
 216                  * no longer meets the alignment restrictions for its new
 217                  * tiling mode. Otherwise we can just leave it alone, but
 218                  * need to ensure that any fence register is updated before
 219                  * the next fenced (either through the GTT or by the BLT unit
 220                  * on older GPUs) access.
 221                  *
 222                  * After updating the tiling parameters, we then flag whether
 223                  * we need to update an associated fence register. Note this
 224                  * has to also include the unfenced register the GPU uses
 225                  * whilst executing a fenced command for an untiled object.
 226                  */
 227                 if (obj->map_and_fenceable &&
 228                     !i915_gem_object_fence_ok(obj, args->tiling_mode))
 229                         ret = i915_gem_object_ggtt_unbind(obj);
 230
 231                 if (ret == 0) {
 232                         if (obj->pages &&
 233                             obj->madv == I915_MADV_WILLNEED &&
 234                             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
 235                                 if (args->tiling_mode == I915_TILING_NONE)
 236                                         i915_gem_object_unpin_pages(obj);
 237                                 if (obj->tiling_mode == I915_TILING_NONE)
 238                                         i915_gem_object_pin_pages(obj);
 239                         }
 240
 241                         obj->fence_dirty =
 242                                 obj->last_fenced_req ||
 243                                 obj->fence_reg != I915_FENCE_REG_NONE;
 244
 245                         obj->tiling_mode = args->tiling_mode;
 246                         obj->stride = args->stride;
 247
 248                         /* Force the fence to be reacquired for GTT access */
 249                         i915_gem_release_mmap(obj);
 250                 }
 251         }
 252         /* we have to maintain this existing ABI... */
 253         args->stride = obj->stride;
 254         args->tiling_mode = obj->tiling_mode;
 255
 256         /* Try to preallocate memory required to save swizzling on put-pages */
 257         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 258                 if (obj->bit_17 == NULL) {
 259                         obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
 260                                               sizeof(long), GFP_KERNEL);
 261                 }
 262         } else {
 263                 kfree(obj->bit_17);
 264                 obj->bit_17 = NULL;
 265         }
 266
 267 err:
 268         drm_gem_object_unreference(&obj->base);
 269         mutex_unlock(&dev->struct_mutex);
 270
 271         return ret;
 272 }
 273
 274 /**
 275  * i915_gem_get_tiling - IOCTL handler to get tiling mode
 276  * @dev: DRM device
 277  * @data: data pointer for the ioctl
 278  * @file: DRM file for the ioctl call
 279  *
 280  * Returns the current tiling mode and required bit 6 swizzling for the object.
 281  *
 282  * Called by the user via ioctl.
 283  *
 284  * Returns:
 285  * Zero on success, negative errno on failure.
 286  */
 287 int
 288 i915_gem_get_tiling(struct drm_device *dev, void *data,
 289                    struct drm_file *file)
 290 {
 291         struct drm_i915_gem_get_tiling *args = data;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct drm_i915_gem_object *obj;
 294
 295         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 296         if (&obj->base == NULL)
 297                 return -ENOENT;
 298
 299         mutex_lock(&dev->struct_mutex);
 300
 301         args->tiling_mode = obj->tiling_mode;
 302         switch (obj->tiling_mode) {
 303         case I915_TILING_X:
 304                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
 305                 break;
 306         case I915_TILING_Y:
 307                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
 308                 break;
 309         case I915_TILING_NONE:
 310                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
 311                 break;
 312         default:
 313                 DRM_ERROR("unknown tiling mode\n");
 314         }
 315
 316         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
 317         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
 318                 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
 319         else
 320                 args->phys_swizzle_mode = args->swizzle_mode;
 321         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
 322                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
 323         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
 324                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
 325
 326         drm_gem_object_unreference(&obj->base);
 327         mutex_unlock(&dev->struct_mutex);
 328
 329         return 0;
 330 }