1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/async.h>
31 #include "intel_drv.h"
32 #include <drm/i915_drm.h>
33 #include <drm/drm_legacy.h>
35 #include "i915_vgpu.h"
36 #include "intel_ringbuffer.h"
37 #include <linux/workqueue.h>
40 static int i915_getparam(struct drm_device
*dev
, void *data
,
41 struct drm_file
*file_priv
)
43 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
44 drm_i915_getparam_t
*param
= data
;
47 switch (param
->param
) {
48 case I915_PARAM_IRQ_ACTIVE
:
49 case I915_PARAM_ALLOW_BATCHBUFFER
:
50 case I915_PARAM_LAST_DISPATCH
:
51 /* Reject all old ums/dri params. */
53 case I915_PARAM_CHIPSET_ID
:
54 value
= dev
->pdev
->device
;
56 case I915_PARAM_REVISION
:
57 value
= dev
->pdev
->revision
;
59 case I915_PARAM_HAS_GEM
:
62 case I915_PARAM_NUM_FENCES_AVAIL
:
63 value
= dev_priv
->num_fence_regs
;
65 case I915_PARAM_HAS_OVERLAY
:
66 value
= dev_priv
->overlay
? 1 : 0;
68 case I915_PARAM_HAS_PAGEFLIPPING
:
71 case I915_PARAM_HAS_EXECBUF2
:
75 case I915_PARAM_HAS_BSD
:
76 value
= intel_ring_initialized(&dev_priv
->ring
[VCS
]);
78 case I915_PARAM_HAS_BLT
:
79 value
= intel_ring_initialized(&dev_priv
->ring
[BCS
]);
81 case I915_PARAM_HAS_VEBOX
:
82 value
= intel_ring_initialized(&dev_priv
->ring
[VECS
]);
84 case I915_PARAM_HAS_BSD2
:
85 value
= intel_ring_initialized(&dev_priv
->ring
[VCS2
]);
87 case I915_PARAM_HAS_RELAXED_FENCING
:
90 case I915_PARAM_HAS_COHERENT_RINGS
:
93 case I915_PARAM_HAS_EXEC_CONSTANTS
:
94 value
= INTEL_INFO(dev
)->gen
>= 4;
96 case I915_PARAM_HAS_RELAXED_DELTA
:
99 case I915_PARAM_HAS_GEN7_SOL_RESET
:
102 case I915_PARAM_HAS_LLC
:
103 value
= HAS_LLC(dev
);
105 case I915_PARAM_HAS_WT
:
108 case I915_PARAM_HAS_ALIASING_PPGTT
:
109 value
= USES_PPGTT(dev
);
111 case I915_PARAM_HAS_WAIT_TIMEOUT
:
114 case I915_PARAM_HAS_SEMAPHORES
:
115 value
= i915_semaphore_is_enabled(dev
);
117 case I915_PARAM_HAS_PINNED_BATCHES
:
120 case I915_PARAM_HAS_EXEC_NO_RELOC
:
123 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
126 case I915_PARAM_CMD_PARSER_VERSION
:
127 value
= i915_cmd_parser_get_version();
129 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
132 case I915_PARAM_SUBSLICE_TOTAL
:
133 value
= INTEL_INFO(dev
)->subslice_total
;
137 case I915_PARAM_EU_TOTAL
:
138 value
= INTEL_INFO(dev
)->eu_total
;
142 case I915_PARAM_HAS_GPU_RESET
:
143 value
= i915
.enable_hangcheck
&&
144 intel_has_gpu_reset(dev
);
146 case I915_PARAM_HAS_RESOURCE_STREAMER
:
147 value
= HAS_RESOURCE_STREAMER(dev
);
150 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
154 if (copy_to_user(param
->value
, &value
, sizeof(int))) {
155 DRM_ERROR("copy_to_user failed\n");
162 static int i915_get_bridge_dev(struct drm_device
*dev
)
164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 static struct pci_dev i915_bridge_dev
;
167 i915_bridge_dev
.dev
.bsddev
= pci_find_dbsf(0, 0, 0, 0);
168 if (!i915_bridge_dev
.dev
.bsddev
) {
169 DRM_ERROR("bridge device not found\n");
173 dev_priv
->bridge_dev
= &i915_bridge_dev
;
177 #define MCHBAR_I915 0x44
178 #define MCHBAR_I965 0x48
179 #define MCHBAR_SIZE (4*4096)
181 #define DEVEN_REG 0x54
182 #define DEVEN_MCHBAR_EN (1 << 28)
184 /* Allocate space for the MCH regs if needed, return nonzero on error */
186 intel_alloc_mchbar_resource(struct drm_device
*dev
)
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
191 u32 temp_lo
, temp_hi
= 0;
194 if (INTEL_INFO(dev
)->gen
>= 4)
195 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
196 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
197 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
199 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
202 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
206 /* Get some space for it */
207 vga
= device_get_parent(dev
->dev
->bsddev
);
208 dev_priv
->mch_res_rid
= 0x100;
209 dev_priv
->mch_res
= BUS_ALLOC_RESOURCE(device_get_parent(vga
),
210 dev
->dev
->bsddev
, SYS_RES_MEMORY
, &dev_priv
->mch_res_rid
, 0, ~0UL,
211 MCHBAR_SIZE
, RF_ACTIVE
| RF_SHAREABLE
, -1);
212 if (dev_priv
->mch_res
== NULL
) {
213 DRM_ERROR("failed mchbar resource alloc\n");
217 if (INTEL_INFO(dev
)->gen
>= 4)
218 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
219 upper_32_bits(rman_get_start(dev_priv
->mch_res
)));
221 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
222 lower_32_bits(rman_get_start(dev_priv
->mch_res
)));
226 /* Setup MCHBAR if possible, return true if we should disable it again */
228 intel_setup_mchbar(struct drm_device
*dev
)
230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
231 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
235 if (IS_VALLEYVIEW(dev
))
238 dev_priv
->mchbar_need_disable
= false;
240 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
241 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
242 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
244 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
248 /* If it's already enabled, don't have to do anything */
252 if (intel_alloc_mchbar_resource(dev
))
255 dev_priv
->mchbar_need_disable
= true;
257 /* Space is allocated or reserved, so enable it. */
258 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
259 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
,
260 temp
| DEVEN_MCHBAR_EN
);
262 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
263 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
268 intel_teardown_mchbar(struct drm_device
*dev
)
270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
275 if (dev_priv
->mchbar_need_disable
) {
276 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
277 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, &temp
);
278 temp
&= ~DEVEN_MCHBAR_EN
;
279 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN_REG
, temp
);
281 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
283 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
);
287 if (dev_priv
->mch_res
!= NULL
) {
288 vga
= device_get_parent(dev
->dev
->bsddev
);
289 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga
), dev
->dev
->bsddev
,
290 SYS_RES_MEMORY
, dev_priv
->mch_res_rid
, dev_priv
->mch_res
);
291 BUS_RELEASE_RESOURCE(device_get_parent(vga
), dev
->dev
->bsddev
,
292 SYS_RES_MEMORY
, dev_priv
->mch_res_rid
, dev_priv
->mch_res
);
293 dev_priv
->mch_res
= NULL
;
298 /* true = enable decode, false = disable decoder */
299 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
301 struct drm_device
*dev
= cookie
;
303 intel_modeset_vga_set_state(dev
, state
);
305 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
306 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
308 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
311 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
313 struct drm_device
*dev
= pci_get_drvdata(pdev
);
314 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
316 if (state
== VGA_SWITCHEROO_ON
) {
317 pr_info("switched on\n");
318 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
319 /* i915 resume handler doesn't set to D0 */
320 pci_set_power_state(dev
->pdev
, PCI_D0
);
321 i915_resume_switcheroo(dev
);
322 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
324 pr_err("switched off\n");
325 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
326 i915_suspend_switcheroo(dev
, pmm
);
327 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
331 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
333 struct drm_device
*dev
= pci_get_drvdata(pdev
);
336 * FIXME: open_count is protected by drm_global_mutex but that would lead to
337 * locking inversion with the driver load path. And the access here is
338 * completely racy anyway. So don't bother with locking for now.
340 return dev
->open_count
== 0;
343 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
344 .set_gpu_state
= i915_switcheroo_set_state
,
346 .can_switch
= i915_switcheroo_can_switch
,
350 static int i915_load_modeset_init(struct drm_device
*dev
)
352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
355 ret
= intel_parse_bios(dev
);
357 DRM_INFO("failed to find VBIOS tables\n");
360 /* If we have > 1 VGA cards, then we need to arbitrate access
361 * to the common VGA resources.
363 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
364 * then we do not take part in VGA arbitration and the
365 * vga_client_register() fails with -ENODEV.
367 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
368 if (ret
&& ret
!= -ENODEV
)
371 intel_register_dsm_handler();
373 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
, false);
375 goto cleanup_vga_client
;
377 /* Initialise stolen first so that we may reserve preallocated
378 * objects for the BIOS to KMS transition.
380 ret
= i915_gem_init_stolen(dev
);
382 goto cleanup_vga_switcheroo
;
385 intel_power_domains_init_hw(dev_priv
);
387 ret
= intel_irq_install(dev_priv
);
389 goto cleanup_gem_stolen
;
391 /* Important: The output setup functions called by modeset_init need
392 * working irqs for e.g. gmbus and dp aux transfers. */
393 intel_modeset_init(dev
);
395 /* intel_guc_ucode_init() needs the mutex to allocate GEM objects */
396 mutex_lock(&dev
->struct_mutex
);
398 intel_guc_ucode_init(dev
);
400 mutex_unlock(&dev
->struct_mutex
);
402 ret
= i915_gem_init(dev
);
406 intel_modeset_gem_init(dev
);
408 /* Always safe in the mode setting case. */
409 /* FIXME: do pre/post-mode set stuff in core KMS code */
410 dev
->vblank_disable_allowed
= 1;
411 if (INTEL_INFO(dev
)->num_pipes
== 0)
414 ret
= intel_fbdev_init(dev
);
418 /* Only enable hotplug handling once the fbdev is fully set up. */
419 intel_hpd_init(dev_priv
);
422 * Some ports require correctly set-up hpd registers for detection to
423 * work properly (leading to ghost connected connector status), e.g. VGA
424 * on gm45. Hence we can only set up the initial fbdev config after hpd
425 * irqs are fully enabled. Now we should scan for the initial config
426 * only once hotplug handling is enabled, but due to screwed-up locking
427 * around kms/fbdev init we can't protect the fdbev initial config
428 * scanning against hotplug events. Hence do this first and ignore the
429 * tiny window where we will loose hotplug notifactions.
431 async_schedule(intel_fbdev_initial_config
, dev_priv
);
433 drm_kms_helper_poll_init(dev
);
438 mutex_lock(&dev
->struct_mutex
);
439 i915_gem_cleanup_ringbuffer(dev
);
440 i915_gem_context_fini(dev
);
441 mutex_unlock(&dev
->struct_mutex
);
443 intel_guc_ucode_fini(dev
);
444 drm_irq_uninstall(dev
);
446 i915_gem_cleanup_stolen(dev
);
448 cleanup_vga_switcheroo
:
449 vga_switcheroo_unregister_client(dev
->pdev
);
451 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
457 #if IS_ENABLED(CONFIG_FB)
458 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
460 struct apertures_struct
*ap
;
461 struct pci_dev
*pdev
= dev_priv
->dev
->pdev
;
465 ap
= alloc_apertures(1);
469 ap
->ranges
[0].base
= dev_priv
->gtt
.mappable_base
;
470 ap
->ranges
[0].size
= dev_priv
->gtt
.mappable_end
;
473 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
475 ret
= remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
482 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
488 #if !defined(CONFIG_VGA_CONSOLE)
489 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
493 #elif !defined(CONFIG_DUMMY_CONSOLE)
494 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
499 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
503 DRM_INFO("Replacing VGA console driver\n");
506 if (con_is_bound(&vga_con
))
507 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
509 ret
= do_unregister_con_driver(&vga_con
);
511 /* Ignore "already unregistered". */
521 static void i915_dump_device_info(struct drm_i915_private
*dev_priv
)
524 const struct intel_device_info
*info
= &dev_priv
->info
;
526 #define PRINT_S(name) "%s"
528 #define PRINT_FLAG(name) info->name ? #name "," : ""
530 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
531 DEV_INFO_FOR_EACH_FLAG(PRINT_S
, SEP_EMPTY
),
533 dev_priv
->dev
->pdev
->device
,
534 dev_priv
->dev
->pdev
->revision
,
535 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_COMMA
));
543 static void cherryview_sseu_info_init(struct drm_device
*dev
)
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 struct intel_device_info
*info
;
549 info
= (struct intel_device_info
*)&dev_priv
->info
;
550 fuse
= I915_READ(CHV_FUSE_GT
);
552 info
->slice_total
= 1;
554 if (!(fuse
& CHV_FGT_DISABLE_SS0
)) {
555 info
->subslice_per_slice
++;
556 eu_dis
= fuse
& (CHV_FGT_EU_DIS_SS0_R0_MASK
|
557 CHV_FGT_EU_DIS_SS0_R1_MASK
);
558 info
->eu_total
+= 8 - hweight32(eu_dis
);
561 if (!(fuse
& CHV_FGT_DISABLE_SS1
)) {
562 info
->subslice_per_slice
++;
563 eu_dis
= fuse
& (CHV_FGT_EU_DIS_SS1_R0_MASK
|
564 CHV_FGT_EU_DIS_SS1_R1_MASK
);
565 info
->eu_total
+= 8 - hweight32(eu_dis
);
568 info
->subslice_total
= info
->subslice_per_slice
;
570 * CHV expected to always have a uniform distribution of EU
573 info
->eu_per_subslice
= info
->subslice_total
?
574 info
->eu_total
/ info
->subslice_total
:
577 * CHV supports subslice power gating on devices with more than
578 * one subslice, and supports EU power gating on devices with
579 * more than one EU pair per subslice.
581 info
->has_slice_pg
= 0;
582 info
->has_subslice_pg
= (info
->subslice_total
> 1);
583 info
->has_eu_pg
= (info
->eu_per_subslice
> 2);
586 static void gen9_sseu_info_init(struct drm_device
*dev
)
588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
589 struct intel_device_info
*info
;
590 int s_max
= 3, ss_max
= 4, eu_max
= 8;
592 u32 fuse2
, s_enable
, ss_disable
, eu_disable
;
595 info
= (struct intel_device_info
*)&dev_priv
->info
;
596 fuse2
= I915_READ(GEN8_FUSE2
);
597 s_enable
= (fuse2
& GEN8_F2_S_ENA_MASK
) >>
599 ss_disable
= (fuse2
& GEN9_F2_SS_DIS_MASK
) >>
600 GEN9_F2_SS_DIS_SHIFT
;
602 info
->slice_total
= hweight32(s_enable
);
604 * The subslice disable field is global, i.e. it applies
605 * to each of the enabled slices.
607 info
->subslice_per_slice
= ss_max
- hweight32(ss_disable
);
608 info
->subslice_total
= info
->slice_total
*
609 info
->subslice_per_slice
;
612 * Iterate through enabled slices and subslices to
613 * count the total enabled EU.
615 for (s
= 0; s
< s_max
; s
++) {
616 if (!(s_enable
& (0x1 << s
)))
617 /* skip disabled slice */
620 eu_disable
= I915_READ(GEN9_EU_DISABLE(s
));
621 for (ss
= 0; ss
< ss_max
; ss
++) {
624 if (ss_disable
& (0x1 << ss
))
625 /* skip disabled subslice */
628 eu_per_ss
= eu_max
- hweight8((eu_disable
>> (ss
*8)) &
632 * Record which subslice(s) has(have) 7 EUs. we
633 * can tune the hash used to spread work among
634 * subslices if they are unbalanced.
637 info
->subslice_7eu
[s
] |= 1 << ss
;
639 info
->eu_total
+= eu_per_ss
;
644 * SKL is expected to always have a uniform distribution
645 * of EU across subslices with the exception that any one
646 * EU in any one subslice may be fused off for die
647 * recovery. BXT is expected to be perfectly uniform in EU
650 info
->eu_per_subslice
= info
->subslice_total
?
651 DIV_ROUND_UP(info
->eu_total
,
652 info
->subslice_total
) : 0;
654 * SKL supports slice power gating on devices with more than
655 * one slice, and supports EU power gating on devices with
656 * more than one EU pair per subslice. BXT supports subslice
657 * power gating on devices with more than one subslice, and
658 * supports EU power gating on devices with more than one EU
661 info
->has_slice_pg
= (IS_SKYLAKE(dev
) && (info
->slice_total
> 1));
662 info
->has_subslice_pg
= (IS_BROXTON(dev
) && (info
->subslice_total
> 1));
663 info
->has_eu_pg
= (info
->eu_per_subslice
> 2);
666 static void broadwell_sseu_info_init(struct drm_device
*dev
)
668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 struct intel_device_info
*info
;
670 const int s_max
= 3, ss_max
= 3, eu_max
= 8;
672 u32 fuse2
, eu_disable
[s_max
], s_enable
, ss_disable
;
674 fuse2
= I915_READ(GEN8_FUSE2
);
675 s_enable
= (fuse2
& GEN8_F2_S_ENA_MASK
) >> GEN8_F2_S_ENA_SHIFT
;
676 ss_disable
= (fuse2
& GEN8_F2_SS_DIS_MASK
) >> GEN8_F2_SS_DIS_SHIFT
;
678 eu_disable
[0] = I915_READ(GEN8_EU_DISABLE0
) & GEN8_EU_DIS0_S0_MASK
;
679 eu_disable
[1] = (I915_READ(GEN8_EU_DISABLE0
) >> GEN8_EU_DIS0_S1_SHIFT
) |
680 ((I915_READ(GEN8_EU_DISABLE1
) & GEN8_EU_DIS1_S1_MASK
) <<
681 (32 - GEN8_EU_DIS0_S1_SHIFT
));
682 eu_disable
[2] = (I915_READ(GEN8_EU_DISABLE1
) >> GEN8_EU_DIS1_S2_SHIFT
) |
683 ((I915_READ(GEN8_EU_DISABLE2
) & GEN8_EU_DIS2_S2_MASK
) <<
684 (32 - GEN8_EU_DIS1_S2_SHIFT
));
687 info
= (struct intel_device_info
*)&dev_priv
->info
;
688 info
->slice_total
= hweight32(s_enable
);
691 * The subslice disable field is global, i.e. it applies
692 * to each of the enabled slices.
694 info
->subslice_per_slice
= ss_max
- hweight32(ss_disable
);
695 info
->subslice_total
= info
->slice_total
* info
->subslice_per_slice
;
698 * Iterate through enabled slices and subslices to
699 * count the total enabled EU.
701 for (s
= 0; s
< s_max
; s
++) {
702 if (!(s_enable
& (0x1 << s
)))
703 /* skip disabled slice */
706 for (ss
= 0; ss
< ss_max
; ss
++) {
709 if (ss_disable
& (0x1 << ss
))
710 /* skip disabled subslice */
713 n_disabled
= hweight8(eu_disable
[s
] >> (ss
* eu_max
));
716 * Record which subslices have 7 EUs.
718 if (eu_max
- n_disabled
== 7)
719 info
->subslice_7eu
[s
] |= 1 << ss
;
721 info
->eu_total
+= eu_max
- n_disabled
;
726 * BDW is expected to always have a uniform distribution of EU across
727 * subslices with the exception that any one EU in any one subslice may
728 * be fused off for die recovery.
730 info
->eu_per_subslice
= info
->subslice_total
?
731 DIV_ROUND_UP(info
->eu_total
, info
->subslice_total
) : 0;
734 * BDW supports slice power gating on devices with more than
737 info
->has_slice_pg
= (info
->slice_total
> 1);
738 info
->has_subslice_pg
= 0;
743 * Determine various intel_device_info fields at runtime.
745 * Use it when either:
746 * - it's judged too laborious to fill n static structures with the limit
747 * when a simple if statement does the job,
748 * - run-time checks (eg read fuse/strap registers) are needed.
750 * This function needs to be called:
751 * - after the MMIO has been setup as we are reading registers,
752 * - after the PCH has been detected,
753 * - before the first usage of the fields it can tweak.
755 static void intel_device_info_runtime_init(struct drm_device
*dev
)
757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
758 struct intel_device_info
*info
;
761 info
= (struct intel_device_info
*)&dev_priv
->info
;
764 * Skylake and Broxton currently don't expose the topmost plane as its
765 * use is exclusive with the legacy cursor and we only want to expose
766 * one of those, not both. Until we can safely expose the topmost plane
767 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
768 * we don't expose the topmost plane at all to prevent ABI breakage
771 if (IS_BROXTON(dev
)) {
772 info
->num_sprites
[PIPE_A
] = 2;
773 info
->num_sprites
[PIPE_B
] = 2;
774 info
->num_sprites
[PIPE_C
] = 1;
775 } else if (IS_VALLEYVIEW(dev
))
776 for_each_pipe(dev_priv
, pipe
)
777 info
->num_sprites
[pipe
] = 2;
779 for_each_pipe(dev_priv
, pipe
)
780 info
->num_sprites
[pipe
] = 1;
782 if (i915
.disable_display
) {
783 DRM_INFO("Display disabled (module parameter)\n");
785 } else if (info
->num_pipes
> 0 &&
786 (INTEL_INFO(dev
)->gen
== 7 || INTEL_INFO(dev
)->gen
== 8) &&
787 !IS_VALLEYVIEW(dev
)) {
788 u32 fuse_strap
= I915_READ(FUSE_STRAP
);
789 u32 sfuse_strap
= I915_READ(SFUSE_STRAP
);
792 * SFUSE_STRAP is supposed to have a bit signalling the display
793 * is fused off. Unfortunately it seems that, at least in
794 * certain cases, fused off display means that PCH display
795 * reads don't land anywhere. In that case, we read 0s.
797 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
798 * should be set when taking over after the firmware.
800 if (fuse_strap
& ILK_INTERNAL_DISPLAY_DISABLE
||
801 sfuse_strap
& SFUSE_STRAP_DISPLAY_DISABLED
||
802 (dev_priv
->pch_type
== PCH_CPT
&&
803 !(sfuse_strap
& SFUSE_STRAP_FUSE_LOCK
))) {
804 DRM_INFO("Display fused off, disabling\n");
809 /* Initialize slice/subslice/EU info */
810 if (IS_CHERRYVIEW(dev
))
811 cherryview_sseu_info_init(dev
);
812 else if (IS_BROADWELL(dev
))
813 broadwell_sseu_info_init(dev
);
814 else if (INTEL_INFO(dev
)->gen
>= 9)
815 gen9_sseu_info_init(dev
);
817 DRM_DEBUG_DRIVER("slice total: %u\n", info
->slice_total
);
818 DRM_DEBUG_DRIVER("subslice total: %u\n", info
->subslice_total
);
819 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info
->subslice_per_slice
);
820 DRM_DEBUG_DRIVER("EU total: %u\n", info
->eu_total
);
821 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info
->eu_per_subslice
);
822 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
823 info
->has_slice_pg
? "y" : "n");
824 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
825 info
->has_subslice_pg
? "y" : "n");
826 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
827 info
->has_eu_pg
? "y" : "n");
830 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
832 if (!IS_VALLEYVIEW(dev_priv
))
836 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
837 * CHV x1 PHY (DP/HDMI D)
838 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
840 if (IS_CHERRYVIEW(dev_priv
)) {
841 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
842 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
844 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
849 * i915_driver_load - setup chip and create an initial config
851 * @flags: startup flags
853 * The driver load routine has to do several things:
854 * - drive output discovery via intel_modeset_init()
855 * - initialize the memory manager
856 * - allocate initial config memory
857 * - setup the DRM framebuffer with the allocated memory
859 int i915_driver_load(struct drm_device
*dev
, unsigned long flags
)
861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
862 struct intel_device_info
*info
, *device_info
;
863 int ret
= 0, mmio_bar
, mmio_size
;
864 uint32_t aperture_size
;
866 /* XXX: struct pci_dev */
867 info
= i915_get_device_id(dev
->pdev
->device
);
869 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
870 if (dev_priv
== NULL
)
873 dev
->dev_private
= dev_priv
;
876 /* Setup the write-once "constant" device info */
877 device_info
= (struct intel_device_info
*)&dev_priv
->info
;
878 memcpy(device_info
, info
, sizeof(dev_priv
->info
));
879 device_info
->device_id
= dev
->pdev
->device
;
881 lockinit(&dev_priv
->irq_lock
, "userirq", 0, LK_CANRECURSE
);
882 lockinit(&dev_priv
->gpu_error
.lock
, "915err", 0, LK_CANRECURSE
);
883 lockinit(&dev_priv
->backlight_lock
, "i915bl", 0, LK_CANRECURSE
);
884 lockinit(&dev_priv
->uncore
.lock
, "915gt", 0, LK_CANRECURSE
);
885 spin_init(&dev_priv
->mm
.object_stat_lock
, "i915osl");
886 spin_init(&dev_priv
->mmio_flip_lock
, "i915mfl");
887 lockinit(&dev_priv
->sb_lock
, "i915sbl", 0, LK_CANRECURSE
);
888 lockinit(&dev_priv
->modeset_restore_lock
, "i915mrl", 0, LK_CANRECURSE
);
889 lockinit(&dev_priv
->csr_lock
, "i915csr", 0, LK_CANRECURSE
);
890 lockinit(&dev_priv
->av_mutex
, "i915am", 0, LK_CANRECURSE
);
894 intel_display_crc_init(dev
);
896 i915_dump_device_info(dev_priv
);
898 /* Not all pre-production machines fall into this category, only the
899 * very first ones. Almost everything should work, except for maybe
900 * suspend/resume. And we don't implement workarounds that affect only
901 * pre-production machines. */
902 if (IS_HSW_EARLY_SDV(dev
))
903 DRM_INFO("This is an early pre-production Haswell machine. "
904 "It may not be fully functional.\n");
906 if (i915_get_bridge_dev(dev
)) {
911 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
912 /* Before gen4, the registers and the GTT are behind different BARs.
913 * However, from gen4 onwards, the registers and the GTT are shared
914 * in the same BAR, so we want to restrict this ioremap from
915 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
916 * the register BAR remains the same size for all the earlier
917 * generations up to Ironlake.
920 mmio_size
= 512*1024;
922 mmio_size
= 2*1024*1024;
924 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, mmio_size
);
925 if (!dev_priv
->regs
) {
926 DRM_ERROR("failed to map registers\n");
931 /* This must be called before any calls to HAS_PCH_* */
932 intel_detect_pch(dev
);
934 intel_uncore_init(dev
);
936 /* Load CSR Firmware for SKL */
937 intel_csr_ucode_init(dev
);
939 ret
= i915_gem_gtt_init(dev
);
943 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
944 * otherwise the vga fbdev driver falls over. */
945 ret
= i915_kick_out_firmware_fb(dev_priv
);
947 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
951 ret
= i915_kick_out_vgacon(dev_priv
);
953 DRM_ERROR("failed to remove conflicting VGA console\n");
958 pci_set_master(dev
->pdev
);
960 /* overlay on gen2 is broken and can't address above 1G */
962 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
964 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
965 * using 32bit addressing, overwriting memory if HWS is located
968 * The documentation also mentions an issue with undefined
969 * behaviour if any general state is accessed within a page above 4GB,
970 * which also needs to be handled carefully.
972 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
973 dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
976 aperture_size
= dev_priv
->gtt
.mappable_end
;
978 dev_priv
->gtt
.mappable
=
979 io_mapping_create_wc(dev_priv
->gtt
.mappable_base
,
981 if (dev_priv
->gtt
.mappable
== NULL
) {
986 dev_priv
->gtt
.mtrr
= arch_phys_wc_add(dev_priv
->gtt
.mappable_base
,
989 /* The i915 workqueue is primarily used for batched retirement of
990 * requests (and thus managing bo) once the task has been completed
991 * by the GPU. i915_gem_retire_requests() is called directly when we
992 * need high-priority retirement, such as waiting for an explicit
995 * It is also used for periodic low-priority events, such as
996 * idle-timers and recording error state.
998 * All tasks on the workqueue are expected to acquire the dev mutex
999 * so there is no point in running more than one instance of the
1000 * workqueue at any time. Use an ordered one.
1002 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
1003 if (dev_priv
->wq
== NULL
) {
1004 DRM_ERROR("Failed to create our workqueue.\n");
1009 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
1010 if (dev_priv
->hotplug
.dp_wq
== NULL
) {
1011 DRM_ERROR("Failed to create our dp workqueue.\n");
1016 dev_priv
->gpu_error
.hangcheck_wq
=
1017 alloc_ordered_workqueue("i915-hangcheck", 0);
1018 if (dev_priv
->gpu_error
.hangcheck_wq
== NULL
) {
1019 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1024 intel_irq_init(dev_priv
);
1025 intel_uncore_sanitize(dev
);
1027 /* Try to make sure MCHBAR is enabled before poking at it */
1028 intel_setup_mchbar(dev
);
1029 intel_setup_gmbus(dev
);
1030 intel_opregion_setup(dev
);
1034 /* On the 945G/GM, the chipset reports the MSI capability on the
1035 * integrated graphics even though the support isn't actually there
1036 * according to the published specs. It doesn't appear to function
1037 * correctly in testing on 945G.
1038 * This may be a side effect of MSI having been made available for PEG
1039 * and the registers being closely associated.
1041 * According to chipset errata, on the 965GM, MSI interrupts may
1042 * be lost or delayed, but we use them anyways to avoid
1043 * stuck interrupts on some machines.
1046 if (!IS_I945G(dev
) && !IS_I945GM(dev
))
1047 pci_enable_msi(dev
->pdev
);
1050 intel_device_info_runtime_init(dev
);
1052 intel_init_dpio(dev_priv
);
1054 if (INTEL_INFO(dev
)->num_pipes
) {
1055 ret
= drm_vblank_init(dev
, INTEL_INFO(dev
)->num_pipes
);
1057 goto out_gem_unload
;
1060 intel_power_domains_init(dev_priv
);
1062 ret
= i915_load_modeset_init(dev
);
1064 DRM_ERROR("failed to init modeset\n");
1065 goto out_power_well
;
1069 * Notify a valid surface after modesetting,
1070 * when running inside a VM.
1072 if (intel_vgpu_active(dev
))
1073 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1075 i915_setup_sysfs(dev
);
1077 if (INTEL_INFO(dev
)->num_pipes
) {
1078 /* Must be done after probing outputs */
1079 intel_opregion_init(dev
);
1081 acpi_video_register();
1086 intel_gpu_ips_init(dev_priv
);
1088 intel_runtime_pm_enable(dev_priv
);
1090 i915_audio_component_init(dev_priv
);
1095 intel_power_domains_fini(dev_priv
);
1096 drm_vblank_cleanup(dev
);
1099 intel_teardown_gmbus(dev
);
1100 intel_teardown_mchbar(dev
);
1101 pm_qos_remove_request(&dev_priv
->pm_qos
);
1102 destroy_workqueue(dev_priv
->gpu_error
.hangcheck_wq
);
1104 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
1106 destroy_workqueue(dev_priv
->wq
);
1108 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
1110 io_mapping_free(dev_priv
->gtt
.mappable
);
1113 i915_global_gtt_cleanup(dev
);
1115 intel_csr_ucode_fini(dev
);
1116 intel_uncore_fini(dev
);
1118 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1121 pci_dev_put(dev_priv
->bridge_dev
);
1127 int i915_driver_unload(struct drm_device
*dev
)
1129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1132 i915_audio_component_cleanup(dev_priv
);
1134 ret
= i915_gem_suspend(dev
);
1136 DRM_ERROR("failed to idle hardware: %d\n", ret
);
1140 intel_power_domains_fini(dev_priv
);
1142 intel_gpu_ips_teardown();
1144 i915_teardown_sysfs(dev
);
1147 WARN_ON(unregister_oom_notifier(&dev_priv
->mm
.oom_notifier
));
1148 unregister_shrinker(&dev_priv
->mm
.shrinker
);
1150 io_mapping_free(dev_priv
->gtt
.mappable
);
1152 arch_phys_wc_del(dev_priv
->gtt
.mtrr
);
1155 acpi_video_unregister();
1158 intel_fbdev_fini(dev
);
1160 drm_vblank_cleanup(dev
);
1162 intel_modeset_cleanup(dev
);
1165 * free the memory space allocated for the child device
1166 * config parsed from VBT
1168 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1169 kfree(dev_priv
->vbt
.child_dev
);
1170 dev_priv
->vbt
.child_dev
= NULL
;
1171 dev_priv
->vbt
.child_dev_num
= 0;
1173 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1174 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1175 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1176 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1179 vga_switcheroo_unregister_client(dev
->pdev
);
1180 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1183 /* Free error state after interrupts are fully disabled. */
1184 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1186 i915_destroy_error_state(dev
);
1188 if (dev
->pdev
->msi_enabled
)
1189 pci_disable_msi(dev
->pdev
);
1192 intel_opregion_fini(dev
);
1194 /* Flush any outstanding unpin_work. */
1195 flush_workqueue(dev_priv
->wq
);
1197 intel_guc_ucode_fini(dev
);
1198 mutex_lock(&dev
->struct_mutex
);
1199 i915_gem_cleanup_ringbuffer(dev
);
1200 i915_gem_context_fini(dev
);
1201 mutex_unlock(&dev
->struct_mutex
);
1202 intel_fbc_cleanup_cfb(dev_priv
);
1203 i915_gem_cleanup_stolen(dev
);
1205 intel_csr_ucode_fini(dev
);
1207 intel_teardown_gmbus(dev
);
1208 intel_teardown_mchbar(dev
);
1210 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
1211 destroy_workqueue(dev_priv
->wq
);
1212 destroy_workqueue(dev_priv
->gpu_error
.hangcheck_wq
);
1213 pm_qos_remove_request(&dev_priv
->pm_qos
);
1215 i915_global_gtt_cleanup(dev
);
1217 intel_uncore_fini(dev
);
1219 if (dev_priv
->regs
!= NULL
)
1220 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
1223 kmem_cache_destroy(dev_priv
->slab
);
1226 pci_dev_put(dev_priv
->bridge_dev
);
1232 int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1236 ret
= i915_gem_open(dev
, file
);
1244 * i915_driver_lastclose - clean up after all DRM clients have exited
1247 * Take care of cleaning up after all DRM clients have exited. In the
1248 * mode setting case, we want to restore the kernel's initial mode (just
1249 * in case the last client left us in a bad state).
1251 * Additionally, in the non-mode setting case, we'll tear down the GTT
1252 * and DMA structures, since the kernel won't be using them, and clea
1255 void i915_driver_lastclose(struct drm_device
*dev
)
1257 intel_fbdev_restore_mode(dev
);
1259 vga_switcheroo_process_delayed_switch();
1263 void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
1265 mutex_lock(&dev
->struct_mutex
);
1266 i915_gem_context_close(dev
, file
);
1267 i915_gem_release(dev
, file
);
1268 mutex_unlock(&dev
->struct_mutex
);
1270 intel_modeset_preclose(dev
, file
);
1273 void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1275 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1277 if (file_priv
&& file_priv
->bsd_ring
)
1278 file_priv
->bsd_ring
= NULL
;
1283 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
1284 struct drm_file
*file
)
1289 const struct drm_ioctl_desc i915_ioctls
[] = {
1290 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1291 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
1292 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
1293 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
1294 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
1295 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
1296 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
|DRM_UNLOCKED
),
1297 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1298 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
1299 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
1300 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1301 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
1302 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1303 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1304 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
1305 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
1306 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
1307 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1308 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
|DRM_UNLOCKED
),
1309 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1310 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1311 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1312 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1313 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1314 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1315 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1316 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1317 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
|DRM_UNLOCKED
),
1318 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1319 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1320 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1321 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1322 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1323 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1324 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1325 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1326 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1327 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1328 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, DRM_UNLOCKED
),
1329 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1330 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1331 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1332 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1333 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
|DRM_UNLOCKED
),
1334 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1335 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1336 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1337 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1338 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_get_reset_stats_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1340 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1342 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1343 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
1346 int i915_max_ioctl
= ARRAY_SIZE(i915_ioctls
);