sys/dev/drm/i915/dvo_ivch.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Thomas Richter <thor@math.tu-berlin.de>
  26  *
  27  * Minor modifications (Dithering enable):
  28  *    Thomas Richter <thor@math.tu-berlin.de>
  29  *
  30  */
  31
  32 #include "dvo.h"
  33
  34 /*
  35  * register definitions for the i82807aa.
  36  *
  37  * Documentation on this chipset can be found in datasheet #29069001 at
  38  * intel.com.
  39  */
  40
  41 /*
  42  * VCH Revision & GMBus Base Addr
  43  */
  44 #define VR00            0x00
  45 # define VR00_BASE_ADDRESS_MASK         0x007f
  46
  47 /*
  48  * Functionality Enable
  49  */
  50 #define VR01            0x01
  51
  52 /*
  53  * Enable the panel fitter
  54  */
  55 # define VR01_PANEL_FIT_ENABLE          (1 << 3)
  56 /*
  57  * Enables the LCD display.
  58  *
  59  * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
  60  */
  61 # define VR01_LCD_ENABLE                (1 << 2)
  62 /** Enables the DVO repeater. */
  63 # define VR01_DVO_BYPASS_ENABLE         (1 << 1)
  64 /** Enables the DVO clock */
  65 # define VR01_DVO_ENABLE                (1 << 0)
  66 /** Enable dithering for 18bpp panels. Not documented. */
  67 # define VR01_DITHER_ENABLE             (1 << 4)
  68
  69 /*
  70  * LCD Interface Format
  71  */
  72 #define VR10            0x10
  73 /** Enables LVDS output instead of CMOS */
  74 # define VR10_LVDS_ENABLE               (1 << 4)
  75 /** Enables 18-bit LVDS output. */
  76 # define VR10_INTERFACE_1X18            (0 << 2)
  77 /** Enables 24-bit LVDS or CMOS output */
  78 # define VR10_INTERFACE_1X24            (1 << 2)
  79 /** Enables 2x18-bit LVDS or CMOS output. */
  80 # define VR10_INTERFACE_2X18            (2 << 2)
  81 /** Enables 2x24-bit LVDS output */
  82 # define VR10_INTERFACE_2X24            (3 << 2)
  83 /** Mask that defines the depth of the pipeline */
  84 # define VR10_INTERFACE_DEPTH_MASK      (3 << 2)
  85
  86 /*
  87  * VR20 LCD Horizontal Display Size
  88  */
  89 #define VR20    0x20
  90
  91 /*
  92  * LCD Vertical Display Size
  93  */
  94 #define VR21    0x21
  95
  96 /*
  97  * Panel power down status
  98  */
  99 #define VR30            0x30
 100 /** Read only bit indicating that the panel is not in a safe poweroff state. */
 101 # define VR30_PANEL_ON                  (1 << 15)
 102
 103 #define VR40            0x40
 104 # define VR40_STALL_ENABLE              (1 << 13)
 105 # define VR40_VERTICAL_INTERP_ENABLE    (1 << 12)
 106 # define VR40_ENHANCED_PANEL_FITTING    (1 << 11)
 107 # define VR40_HORIZONTAL_INTERP_ENABLE  (1 << 10)
 108 # define VR40_AUTO_RATIO_ENABLE         (1 << 9)
 109 # define VR40_CLOCK_GATING_ENABLE       (1 << 8)
 110
 111 /*
 112  * Panel Fitting Vertical Ratio
 113  * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
 114  */
 115 #define VR41            0x41
 116
 117 /*
 118  * Panel Fitting Horizontal Ratio
 119  * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
 120  */
 121 #define VR42            0x42
 122
 123 /*
 124  * Horizontal Image Size
 125  */
 126 #define VR43            0x43
 127
 128 /* VR80 GPIO 0
 129  */
 130 #define VR80        0x80
 131 #define VR81        0x81
 132 #define VR82        0x82
 133 #define VR83        0x83
 134 #define VR84        0x84
 135 #define VR85        0x85
 136 #define VR86        0x86
 137 #define VR87        0x87
 138
 139 /* VR88 GPIO 8
 140  */
 141 #define VR88        0x88
 142
 143 /* Graphics BIOS scratch 0
 144  */
 145 #define VR8E        0x8E
 146 # define VR8E_PANEL_TYPE_MASK           (0xf << 0)
 147 # define VR8E_PANEL_INTERFACE_CMOS      (0 << 4)
 148 # define VR8E_PANEL_INTERFACE_LVDS      (1 << 4)
 149 # define VR8E_FORCE_DEFAULT_PANEL       (1 << 5)
 150
 151 /* Graphics BIOS scratch 1
 152  */
 153 #define VR8F        0x8F
 154 # define VR8F_VCH_PRESENT               (1 << 0)
 155 # define VR8F_DISPLAY_CONN              (1 << 1)
 156 # define VR8F_POWER_MASK                (0x3c)
 157 # define VR8F_POWER_POS                 (2)
 158
 159 /* Some Bios implementations do not restore the DVO state upon
 160  * resume from standby. Thus, this driver has to handle it
 161  * instead. The following list contains all registers that
 162  * require saving.
 163  */
 164 static const uint16_t backup_addresses[] = {
 165         0x11, 0x12,
 166         0x18, 0x19, 0x1a, 0x1f,
 167         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
 168         0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
 169         0x8e, 0x8f,
 170         0x10            /* this must come last */
 171 };
 172
 173
 174 struct ivch_priv {
 175         bool quiet;
 176
 177         uint16_t width, height;
 178
 179         /* Register backup */
 180
 181         uint16_t reg_backup[ARRAY_SIZE(backup_addresses)];
 182 };
 183
 184
 185 static void ivch_dump_regs(struct intel_dvo_device *dvo);
 186 /**
 187  * Reads a register on the ivch.
 188  *
 189  * Each of the 256 registers are 16 bits long.
 190  */
 191 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
 192 {
 193         struct intel_iic_softc *sc;
 194         struct ivch_priv *priv = dvo->dev_priv;
 195         struct i2c_adapter *adapter = dvo->i2c_bus;
 196         u8 out_buf[1];
 197         u8 in_buf[2];
 198
 199         struct i2c_msg msgs[] = {
 200                 {
 201                         .slave = dvo->slave_addr << 1,
 202                         .flags = I2C_M_RD,
 203                         .len = 0,
 204                 },
 205                 {
 206                         .slave = 0 << 1,
 207                         .flags = I2C_M_NOSTART,
 208                         .len = 1,
 209                         .buf = out_buf,
 210                 },
 211                 {
 212                         .slave = dvo->slave_addr << 1,
 213                         .flags = I2C_M_RD | I2C_M_NOSTART,
 214                         .len = 2,
 215                         .buf = in_buf,
 216                 }
 217         };
 218
 219         *data = 0;      /* silence gcc warnings */
 220         out_buf[0] = addr;
 221
 222         sc = device_get_softc(adapter);
 223
 224         if (iicbus_transfer(adapter, msgs, 3) == 0) {
 225                 *data = (in_buf[1] << 8) | in_buf[0];
 226                 return true;
 227         }
 228
 229         if (!priv->quiet) {
 230                 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
 231                                 "%s:%02x.\n",
 232                           addr, sc->name, dvo->slave_addr);
 233         }
 234         return false;
 235 }
 236
 237 /** Writes a 16-bit register on the ivch */
 238 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
 239 {
 240         struct intel_iic_softc *sc;
 241         struct ivch_priv *priv = dvo->dev_priv;
 242         struct i2c_adapter *adapter = dvo->i2c_bus;
 243         u8 out_buf[3];
 244         struct i2c_msg msg = {
 245                 .slave = dvo->slave_addr << 1,
 246                 .flags = 0,
 247                 .len = 3,
 248                 .buf = out_buf,
 249         };
 250
 251         out_buf[0] = addr;
 252         out_buf[1] = data & 0xff;
 253         out_buf[2] = data >> 8;
 254
 255         sc = device_get_softc(adapter);
 256
 257         if (iicbus_transfer(adapter, &msg, 1) == 0)
 258                 return true;
 259
 260         if (!priv->quiet) {
 261                 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
 262                           addr, sc->name, dvo->slave_addr);
 263         }
 264
 265         return false;
 266 }
 267
 268 /** Probes the given bus and slave address for an ivch */
 269 static bool ivch_init(struct intel_dvo_device *dvo,
 270                       struct i2c_adapter *adapter)
 271 {
 272         struct ivch_priv *priv;
 273         uint16_t temp;
 274         int i;
 275
 276         priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
 277         if (priv == NULL)
 278                 return false;
 279
 280         dvo->i2c_bus = adapter;
 281         dvo->dev_priv = priv;
 282         priv->quiet = true;
 283
 284         if (!ivch_read(dvo, VR00, &temp))
 285                 goto out;
 286         priv->quiet = false;
 287
 288         /* Since the identification bits are probably zeroes, which doesn't seem
 289          * very unique, check that the value in the base address field matches
 290          * the address it's responding on.
 291          */
 292         if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
 293                 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
 294                           "(%d vs %d)\n",
 295                           (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
 296                 goto out;
 297         }
 298
 299         ivch_read(dvo, VR20, &priv->width);
 300         ivch_read(dvo, VR21, &priv->height);
 301
 302         /* Make a backup of the registers to be able to restore them
 303          * upon suspend.
 304          */
 305         for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
 306                 ivch_read(dvo, backup_addresses[i], priv->reg_backup + i);
 307
 308         ivch_dump_regs(dvo);
 309
 310         return true;
 311
 312 out:
 313         kfree(priv);
 314         return false;
 315 }
 316
 317 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
 318 {
 319         return connector_status_connected;
 320 }
 321
 322 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
 323                                             struct drm_display_mode *mode)
 324 {
 325         if (mode->clock > 112000)
 326                 return MODE_CLOCK_HIGH;
 327
 328         return MODE_OK;
 329 }
 330
 331 /* Restore the DVO registers after a resume
 332  * from RAM. Registers have been saved during
 333  * the initialization.
 334  */
 335 static void ivch_reset(struct intel_dvo_device *dvo)
 336 {
 337         struct ivch_priv *priv = dvo->dev_priv;
 338         int i;
 339
 340         DRM_DEBUG_KMS("Resetting the IVCH registers\n");
 341
 342         ivch_write(dvo, VR10, 0x0000);
 343
 344         for (i = 0; i < ARRAY_SIZE(backup_addresses); i++)
 345                 ivch_write(dvo, backup_addresses[i], priv->reg_backup[i]);
 346 }
 347
 348 /** Sets the power state of the panel connected to the ivch */
 349 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable)
 350 {
 351         int i;
 352         uint16_t vr01, vr30, backlight;
 353
 354         ivch_reset(dvo);
 355
 356         /* Set the new power state of the panel. */
 357         if (!ivch_read(dvo, VR01, &vr01))
 358                 return;
 359
 360         if (enable)
 361                 backlight = 1;
 362         else
 363                 backlight = 0;
 364
 365         ivch_write(dvo, VR80, backlight);
 366
 367         if (enable)
 368                 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
 369         else
 370                 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
 371
 372         ivch_write(dvo, VR01, vr01);
 373
 374         /* Wait for the panel to make its state transition */
 375         for (i = 0; i < 100; i++) {
 376                 if (!ivch_read(dvo, VR30, &vr30))
 377                         break;
 378
 379                 if (((vr30 & VR30_PANEL_ON) != 0) == enable)
 380                         break;
 381                 udelay(1000);
 382         }
 383         /* wait some more; vch may fail to resync sometimes without this */
 384         udelay(16 * 1000);
 385 }
 386
 387 static bool ivch_get_hw_state(struct intel_dvo_device *dvo)
 388 {
 389         uint16_t vr01;
 390
 391         ivch_reset(dvo);
 392
 393         /* Set the new power state of the panel. */
 394         if (!ivch_read(dvo, VR01, &vr01))
 395                 return false;
 396
 397         if (vr01 & VR01_LCD_ENABLE)
 398                 return true;
 399         else
 400                 return false;
 401 }
 402
 403 static void ivch_mode_set(struct intel_dvo_device *dvo,
 404                           const struct drm_display_mode *mode,
 405                           const struct drm_display_mode *adjusted_mode)
 406 {
 407         struct ivch_priv *priv = dvo->dev_priv;
 408         uint16_t vr40 = 0;
 409         uint16_t vr01 = 0;
 410         uint16_t vr10;
 411
 412         ivch_reset(dvo);
 413
 414         vr10 = priv->reg_backup[ARRAY_SIZE(backup_addresses) - 1];
 415
 416         /* Enable dithering for 18 bpp pipelines */
 417         vr10 &= VR10_INTERFACE_DEPTH_MASK;
 418         if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18)
 419                 vr01 = VR01_DITHER_ENABLE;
 420
 421         vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
 422                 VR40_HORIZONTAL_INTERP_ENABLE);
 423
 424         if (mode->hdisplay != adjusted_mode->crtc_hdisplay ||
 425             mode->vdisplay != adjusted_mode->crtc_vdisplay) {
 426                 uint16_t x_ratio, y_ratio;
 427
 428                 vr01 |= VR01_PANEL_FIT_ENABLE;
 429                 vr40 |= VR40_CLOCK_GATING_ENABLE;
 430                 x_ratio = (((mode->hdisplay - 1) << 16) /
 431                            (adjusted_mode->crtc_hdisplay - 1)) >> 2;
 432                 y_ratio = (((mode->vdisplay - 1) << 16) /
 433                            (adjusted_mode->crtc_vdisplay - 1)) >> 2;
 434                 ivch_write(dvo, VR42, x_ratio);
 435                 ivch_write(dvo, VR41, y_ratio);
 436         } else {
 437                 vr01 &= ~VR01_PANEL_FIT_ENABLE;
 438                 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
 439         }
 440         vr40 &= ~VR40_AUTO_RATIO_ENABLE;
 441
 442         ivch_write(dvo, VR01, vr01);
 443         ivch_write(dvo, VR40, vr40);
 444 }
 445
 446 static void ivch_dump_regs(struct intel_dvo_device *dvo)
 447 {
 448         uint16_t val;
 449
 450         ivch_read(dvo, VR00, &val);
 451         DRM_DEBUG_KMS("VR00: 0x%04x\n", val);
 452         ivch_read(dvo, VR01, &val);
 453         DRM_DEBUG_KMS("VR01: 0x%04x\n", val);
 454         ivch_read(dvo, VR10, &val);
 455         DRM_DEBUG_KMS("VR10: 0x%04x\n", val);
 456         ivch_read(dvo, VR30, &val);
 457         DRM_DEBUG_KMS("VR30: 0x%04x\n", val);
 458         ivch_read(dvo, VR40, &val);
 459         DRM_DEBUG_KMS("VR40: 0x%04x\n", val);
 460
 461         /* GPIO registers */
 462         ivch_read(dvo, VR80, &val);
 463         DRM_DEBUG_KMS("VR80: 0x%04x\n", val);
 464         ivch_read(dvo, VR81, &val);
 465         DRM_DEBUG_KMS("VR81: 0x%04x\n", val);
 466         ivch_read(dvo, VR82, &val);
 467         DRM_DEBUG_KMS("VR82: 0x%04x\n", val);
 468         ivch_read(dvo, VR83, &val);
 469         DRM_DEBUG_KMS("VR83: 0x%04x\n", val);
 470         ivch_read(dvo, VR84, &val);
 471         DRM_DEBUG_KMS("VR84: 0x%04x\n", val);
 472         ivch_read(dvo, VR85, &val);
 473         DRM_DEBUG_KMS("VR85: 0x%04x\n", val);
 474         ivch_read(dvo, VR86, &val);
 475         DRM_DEBUG_KMS("VR86: 0x%04x\n", val);
 476         ivch_read(dvo, VR87, &val);
 477         DRM_DEBUG_KMS("VR87: 0x%04x\n", val);
 478         ivch_read(dvo, VR88, &val);
 479         DRM_DEBUG_KMS("VR88: 0x%04x\n", val);
 480
 481         /* Scratch register 0 - AIM Panel type */
 482         ivch_read(dvo, VR8E, &val);
 483         DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);
 484
 485         /* Scratch register 1 - Status register */
 486         ivch_read(dvo, VR8F, &val);
 487         DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);
 488 }
 489
 490 static void ivch_destroy(struct intel_dvo_device *dvo)
 491 {
 492         struct ivch_priv *priv = dvo->dev_priv;
 493
 494         if (priv) {
 495                 kfree(priv);
 496                 dvo->dev_priv = NULL;
 497         }
 498 }
 499
 500 struct intel_dvo_dev_ops ivch_ops = {
 501         .init = ivch_init,
 502         .dpms = ivch_dpms,
 503         .get_hw_state = ivch_get_hw_state,
 504         .mode_valid = ivch_mode_valid,
 505         .mode_set = ivch_mode_set,
 506         .detect = ivch_detect,
 507         .dump_regs = ivch_dump_regs,
 508         .destroy = ivch_destroy,
 509 };