2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
30 #define CH7017_TV_DISPLAY_MODE 0x00
31 #define CH7017_FLICKER_FILTER 0x01
32 #define CH7017_VIDEO_BANDWIDTH 0x02
33 #define CH7017_TEXT_ENHANCEMENT 0x03
34 #define CH7017_START_ACTIVE_VIDEO 0x04
35 #define CH7017_HORIZONTAL_POSITION 0x05
36 #define CH7017_VERTICAL_POSITION 0x06
37 #define CH7017_BLACK_LEVEL 0x07
38 #define CH7017_CONTRAST_ENHANCEMENT 0x08
39 #define CH7017_TV_PLL 0x09
40 #define CH7017_TV_PLL_M 0x0a
41 #define CH7017_TV_PLL_N 0x0b
42 #define CH7017_SUB_CARRIER_0 0x0c
43 #define CH7017_CIV_CONTROL 0x10
44 #define CH7017_CIV_0 0x11
45 #define CH7017_CHROMA_BOOST 0x14
46 #define CH7017_CLOCK_MODE 0x1c
47 #define CH7017_INPUT_CLOCK 0x1d
48 #define CH7017_GPIO_CONTROL 0x1e
49 #define CH7017_INPUT_DATA_FORMAT 0x1f
50 #define CH7017_CONNECTION_DETECT 0x20
51 #define CH7017_DAC_CONTROL 0x21
52 #define CH7017_BUFFERED_CLOCK_OUTPUT 0x22
53 #define CH7017_DEFEAT_VSYNC 0x47
54 #define CH7017_TEST_PATTERN 0x48
56 #define CH7017_POWER_MANAGEMENT 0x49
57 /** Enables the TV output path. */
58 #define CH7017_TV_EN (1 << 0)
59 #define CH7017_DAC0_POWER_DOWN (1 << 1)
60 #define CH7017_DAC1_POWER_DOWN (1 << 2)
61 #define CH7017_DAC2_POWER_DOWN (1 << 3)
62 #define CH7017_DAC3_POWER_DOWN (1 << 4)
63 /** Powers down the TV out block, and DAC0-3 */
64 #define CH7017_TV_POWER_DOWN_EN (1 << 5)
66 #define CH7017_VERSION_ID 0x4a
68 #define CH7017_DEVICE_ID 0x4b
69 #define CH7017_DEVICE_ID_VALUE 0x1b
70 #define CH7018_DEVICE_ID_VALUE 0x1a
71 #define CH7019_DEVICE_ID_VALUE 0x19
73 #define CH7017_XCLK_D2_ADJUST 0x53
74 #define CH7017_UP_SCALER_COEFF_0 0x55
75 #define CH7017_UP_SCALER_COEFF_1 0x56
76 #define CH7017_UP_SCALER_COEFF_2 0x57
77 #define CH7017_UP_SCALER_COEFF_3 0x58
78 #define CH7017_UP_SCALER_COEFF_4 0x59
79 #define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a
80 #define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b
81 #define CH7017_GPIO_INVERT 0x5c
82 #define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d
83 #define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e
85 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f
86 /**< Low bits of horizontal active pixel input */
88 #define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60
89 /** High bits of horizontal active pixel input */
90 #define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0)
91 /** High bits of vertical active line output */
92 #define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3)
94 #define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61
95 /**< Low bits of vertical active line output */
97 #define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62
98 /**< Low bits of horizontal active pixel output */
100 #define CH7017_LVDS_POWER_DOWN 0x63
101 /** High bits of horizontal active pixel output */
102 #define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0)
103 /** Enables the LVDS power down state transition */
104 #define CH7017_LVDS_POWER_DOWN_EN (1 << 6)
105 /** Enables the LVDS upscaler */
106 #define CH7017_LVDS_UPSCALER_EN (1 << 7)
107 #define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
109 #define CH7017_LVDS_ENCODING 0x64
110 #define CH7017_LVDS_DITHER_2D (1 << 2)
111 #define CH7017_LVDS_DITHER_DIS (1 << 3)
112 #define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4)
113 #define CH7017_LVDS_24_BIT (1 << 5)
115 #define CH7017_LVDS_ENCODING_2 0x65
117 #define CH7017_LVDS_PLL_CONTROL 0x66
118 /** Enables the LVDS panel output path */
119 #define CH7017_LVDS_PANEN (1 << 0)
120 /** Enables the LVDS panel backlight */
121 #define CH7017_LVDS_BKLEN (1 << 3)
123 #define CH7017_POWER_SEQUENCING_T1 0x67
124 #define CH7017_POWER_SEQUENCING_T2 0x68
125 #define CH7017_POWER_SEQUENCING_T3 0x69
126 #define CH7017_POWER_SEQUENCING_T4 0x6a
127 #define CH7017_POWER_SEQUENCING_T5 0x6b
128 #define CH7017_GPIO_DRIVER_TYPE 0x6c
129 #define CH7017_GPIO_DATA 0x6d
130 #define CH7017_GPIO_DIRECTION_CONTROL 0x6e
132 #define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71
133 # define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4
134 # define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0
135 # define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80
137 #define CH7017_LVDS_PLL_VCO_CONTROL 0x72
138 # define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80
139 # define CH7017_LVDS_PLL_VCO_SHIFT 4
140 # define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0
142 #define CH7017_OUTPUTS_ENABLE 0x73
143 # define CH7017_CHARGE_PUMP_LOW 0x0
144 # define CH7017_CHARGE_PUMP_HIGH 0x3
145 # define CH7017_LVDS_CHANNEL_A (1 << 3)
146 # define CH7017_LVDS_CHANNEL_B (1 << 4)
147 # define CH7017_TV_DAC_A (1 << 5)
148 # define CH7017_TV_DAC_B (1 << 6)
149 # define CH7017_DDC_SELECT_DC2 (1 << 7)
151 #define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74
152 #define CH7017_LVDS_PLL_EMI_REDUCTION 0x75
153 #define CH7017_LVDS_POWER_DOWN_FLICKER 0x76
155 #define CH7017_LVDS_CONTROL_2 0x78
156 # define CH7017_LOOP_FILTER_SHIFT 5
157 # define CH7017_PHASE_DETECTOR_SHIFT 0
159 #define CH7017_BANG_LIMIT_CONTROL 0x7f
165 static void ch7017_dump_regs(struct intel_dvo_device
*dvo
);
166 static void ch7017_dpms(struct intel_dvo_device
*dvo
, bool enable
);
168 static bool ch7017_read(struct intel_dvo_device
*dvo
, u8 addr
, u8
*val
)
170 struct i2c_msg msgs
[] = {
172 .slave
= dvo
->slave_addr
<< 1,
178 .slave
= dvo
->slave_addr
<< 1,
184 return iicbus_transfer(dvo
->i2c_bus
, msgs
, 2) == 0;
187 static bool ch7017_write(struct intel_dvo_device
*dvo
, u8 addr
, u8 val
)
189 uint8_t buf
[2] = { addr
, val
};
190 struct i2c_msg msg
= {
191 .slave
= dvo
->slave_addr
<< 1,
196 return iicbus_transfer(dvo
->i2c_bus
, &msg
, 1) == 0;
199 /** Probes for a CH7017 on the given bus and slave address. */
200 static bool ch7017_init(struct intel_dvo_device
*dvo
,
201 struct i2c_adapter
*adapter
)
203 struct intel_iic_softc
*sc
;
204 struct ch7017_priv
*priv
;
208 sc
= device_get_softc(adapter
);
210 priv
= kzalloc(sizeof(struct ch7017_priv
), GFP_KERNEL
);
214 dvo
->i2c_bus
= adapter
;
215 dvo
->dev_priv
= priv
;
217 if (!ch7017_read(dvo
, CH7017_DEVICE_ID
, &val
))
221 case CH7017_DEVICE_ID_VALUE
:
224 case CH7018_DEVICE_ID_VALUE
:
227 case CH7019_DEVICE_ID_VALUE
:
231 DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
233 val
, sc
->name
, dvo
->slave_addr
);
237 DRM_DEBUG_KMS("%s detected on %s, addr %d\n",
238 str
, sc
->name
, dvo
->slave_addr
);
246 static enum drm_connector_status
ch7017_detect(struct intel_dvo_device
*dvo
)
248 return connector_status_connected
;
251 static enum drm_mode_status
ch7017_mode_valid(struct intel_dvo_device
*dvo
,
252 struct drm_display_mode
*mode
)
254 if (mode
->clock
> 160000)
255 return MODE_CLOCK_HIGH
;
260 static void ch7017_mode_set(struct intel_dvo_device
*dvo
,
261 struct drm_display_mode
*mode
,
262 struct drm_display_mode
*adjusted_mode
)
264 uint8_t lvds_pll_feedback_div
, lvds_pll_vco_control
;
265 uint8_t outputs_enable
, lvds_control_2
, lvds_power_down
;
266 uint8_t horizontal_active_pixel_input
;
267 uint8_t horizontal_active_pixel_output
, vertical_active_line_output
;
268 uint8_t active_input_line_output
;
270 DRM_DEBUG_KMS("Registers before mode setting\n");
271 ch7017_dump_regs(dvo
);
273 /* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
274 if (mode
->clock
< 100000) {
275 outputs_enable
= CH7017_LVDS_CHANNEL_A
| CH7017_CHARGE_PUMP_LOW
;
276 lvds_pll_feedback_div
= CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED
|
277 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT
) |
278 (13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT
);
279 lvds_pll_vco_control
= CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED
|
280 (2 << CH7017_LVDS_PLL_VCO_SHIFT
) |
281 (3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT
);
282 lvds_control_2
= (1 << CH7017_LOOP_FILTER_SHIFT
) |
283 (0 << CH7017_PHASE_DETECTOR_SHIFT
);
285 outputs_enable
= CH7017_LVDS_CHANNEL_A
| CH7017_CHARGE_PUMP_HIGH
;
286 lvds_pll_feedback_div
= CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED
|
287 (2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT
) |
288 (3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT
);
289 lvds_pll_feedback_div
= 35;
290 lvds_control_2
= (3 << CH7017_LOOP_FILTER_SHIFT
) |
291 (0 << CH7017_PHASE_DETECTOR_SHIFT
);
292 if (1) { /* XXX: dual channel panel detection. Assume yes for now. */
293 outputs_enable
|= CH7017_LVDS_CHANNEL_B
;
294 lvds_pll_vco_control
= CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED
|
295 (2 << CH7017_LVDS_PLL_VCO_SHIFT
) |
296 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT
);
298 lvds_pll_vco_control
= CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED
|
299 (1 << CH7017_LVDS_PLL_VCO_SHIFT
) |
300 (13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT
);
304 horizontal_active_pixel_input
= mode
->hdisplay
& 0x00ff;
306 vertical_active_line_output
= mode
->vdisplay
& 0x00ff;
307 horizontal_active_pixel_output
= mode
->hdisplay
& 0x00ff;
309 active_input_line_output
= ((mode
->hdisplay
& 0x0700) >> 8) |
310 (((mode
->vdisplay
& 0x0700) >> 8) << 3);
312 lvds_power_down
= CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED
|
313 (mode
->hdisplay
& 0x0700) >> 8;
315 ch7017_dpms(dvo
, false);
316 ch7017_write(dvo
, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT
,
317 horizontal_active_pixel_input
);
318 ch7017_write(dvo
, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT
,
319 horizontal_active_pixel_output
);
320 ch7017_write(dvo
, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT
,
321 vertical_active_line_output
);
322 ch7017_write(dvo
, CH7017_ACTIVE_INPUT_LINE_OUTPUT
,
323 active_input_line_output
);
324 ch7017_write(dvo
, CH7017_LVDS_PLL_VCO_CONTROL
, lvds_pll_vco_control
);
325 ch7017_write(dvo
, CH7017_LVDS_PLL_FEEDBACK_DIV
, lvds_pll_feedback_div
);
326 ch7017_write(dvo
, CH7017_LVDS_CONTROL_2
, lvds_control_2
);
327 ch7017_write(dvo
, CH7017_OUTPUTS_ENABLE
, outputs_enable
);
329 /* Turn the LVDS back on with new settings. */
330 ch7017_write(dvo
, CH7017_LVDS_POWER_DOWN
, lvds_power_down
);
332 DRM_DEBUG_KMS("Registers after mode setting\n");
333 ch7017_dump_regs(dvo
);
336 /* set the CH7017 power state */
337 static void ch7017_dpms(struct intel_dvo_device
*dvo
, bool enable
)
341 ch7017_read(dvo
, CH7017_LVDS_POWER_DOWN
, &val
);
343 /* Turn off TV/VGA, and never turn it on since we don't support it. */
344 ch7017_write(dvo
, CH7017_POWER_MANAGEMENT
,
345 CH7017_DAC0_POWER_DOWN
|
346 CH7017_DAC1_POWER_DOWN
|
347 CH7017_DAC2_POWER_DOWN
|
348 CH7017_DAC3_POWER_DOWN
|
349 CH7017_TV_POWER_DOWN_EN
);
352 /* Turn on the LVDS */
353 ch7017_write(dvo
, CH7017_LVDS_POWER_DOWN
,
354 val
& ~CH7017_LVDS_POWER_DOWN_EN
);
356 /* Turn off the LVDS */
357 ch7017_write(dvo
, CH7017_LVDS_POWER_DOWN
,
358 val
| CH7017_LVDS_POWER_DOWN_EN
);
361 /* XXX: Should actually wait for update power status somehow */
365 static bool ch7017_get_hw_state(struct intel_dvo_device
*dvo
)
369 ch7017_read(dvo
, CH7017_LVDS_POWER_DOWN
, &val
);
371 if (val
& CH7017_LVDS_POWER_DOWN_EN
)
377 static void ch7017_dump_regs(struct intel_dvo_device
*dvo
)
383 ch7017_read(dvo, reg, &val); \
384 DRM_DEBUG_KMS(#reg ": %02x\n", val); \
387 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT
);
388 DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT
);
389 DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT
);
390 DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT
);
391 DUMP(CH7017_LVDS_PLL_VCO_CONTROL
);
392 DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV
);
393 DUMP(CH7017_LVDS_CONTROL_2
);
394 DUMP(CH7017_OUTPUTS_ENABLE
);
395 DUMP(CH7017_LVDS_POWER_DOWN
);
398 static void ch7017_destroy(struct intel_dvo_device
*dvo
)
400 struct ch7017_priv
*priv
= dvo
->dev_priv
;
404 dvo
->dev_priv
= NULL
;
408 struct intel_dvo_dev_ops ch7017_ops
= {
410 .detect
= ch7017_detect
,
411 .mode_valid
= ch7017_mode_valid
,
412 .mode_set
= ch7017_mode_set
,
414 .get_hw_state
= ch7017_get_hw_state
,
415 .dump_regs
= ch7017_dump_regs
,
416 .destroy
= ch7017_destroy
,