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Add flag to indicate that the NIC does not have power control capability.
[dragonfly.git] / sys / dev / netif / nfe / if_nfe.c
blob7253a411c61423ac67d54a06b288989ae99bff41
1 /* $OpenBSD: if_nfe.c,v 1.63 2006/06/17 18:00:43 brad Exp $ */
2 /* $DragonFly: src/sys/dev/netif/nfe/if_nfe.c,v 1.25 2008/06/27 13:30:56 sephe Exp $ */
3
4 /*
5 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Sepherosa Ziehau <sepherosa@gmail.com> and
9 * Matthew Dillon <dillon@apollo.backplane.com>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 * 3. Neither the name of The DragonFly Project nor the names of its
22 * contributors may be used to endorse or promote products derived
23 * from this software without specific, prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
28 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
29 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
30 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
31 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
33 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr>
41 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org>
42 *
43 * Permission to use, copy, modify, and distribute this software for any
44 * purpose with or without fee is hereby granted, provided that the above
45 * copyright notice and this permission notice appear in all copies.
46 *
47 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
48 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
49 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
50 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
51 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
52 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
53 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 */
55
56 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */
57
58 #include "opt_polling.h"
59 #include "opt_ethernet.h"
60
61 #include <sys/param.h>
62 #include <sys/endian.h>
63 #include <sys/kernel.h>
64 #include <sys/bus.h>
65 #include <sys/interrupt.h>
66 #include <sys/proc.h>
67 #include <sys/rman.h>
68 #include <sys/serialize.h>
69 #include <sys/socket.h>
70 #include <sys/sockio.h>
71 #include <sys/sysctl.h>
72
73 #include <net/ethernet.h>
74 #include <net/if.h>
75 #include <net/bpf.h>
76 #include <net/if_arp.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/ifq_var.h>
80 #include <net/if_types.h>
81 #include <net/if_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
87 #include <bus/pci/pcidevs.h>
88
89 #include <dev/netif/mii_layer/mii.h>
90 #include <dev/netif/mii_layer/miivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/nfe/if_nfereg.h>
95 #include <dev/netif/nfe/if_nfevar.h>
96
97 #define NFE_CSUM
98 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
99
100 static int nfe_probe(device_t);
101 static int nfe_attach(device_t);
102 static int nfe_detach(device_t);
103 static void nfe_shutdown(device_t);
104 static int nfe_resume(device_t);
105 static int nfe_suspend(device_t);
106
107 static int nfe_miibus_readreg(device_t, int, int);
108 static void nfe_miibus_writereg(device_t, int, int, int);
109 static void nfe_miibus_statchg(device_t);
110
111 #ifdef DEVICE_POLLING
112 static void nfe_poll(struct ifnet *, enum poll_cmd, int);
113 #endif
114 static void nfe_intr(void *);
115 static int nfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void nfe_rxeof(struct nfe_softc *);
117 static void nfe_txeof(struct nfe_softc *);
118 static int nfe_encap(struct nfe_softc *, struct nfe_tx_ring *,
119 struct mbuf *);
120 static void nfe_start(struct ifnet *);
121 static void nfe_watchdog(struct ifnet *);
122 static void nfe_init(void *);
123 static void nfe_stop(struct nfe_softc *);
124 static struct nfe_jbuf *nfe_jalloc(struct nfe_softc *);
125 static void nfe_jfree(void *);
126 static void nfe_jref(void *);
127 static int nfe_jpool_alloc(struct nfe_softc *, struct nfe_rx_ring *);
128 static void nfe_jpool_free(struct nfe_softc *, struct nfe_rx_ring *);
129 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
130 static void nfe_reset_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
131 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
132 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *);
133 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
134 static void nfe_reset_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
135 static int nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
136 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *);
137 static int nfe_ifmedia_upd(struct ifnet *);
138 static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static void nfe_setmulti(struct nfe_softc *);
140 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *);
141 static void nfe_set_macaddr(struct nfe_softc *, const uint8_t *);
142 static void nfe_tick(void *);
143 static void nfe_ring_dma_addr(void *, bus_dma_segment_t *, int, int);
144 static void nfe_buf_dma_addr(void *, bus_dma_segment_t *, int, bus_size_t,
145 int);
146 static void nfe_set_paddr_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
147 int, bus_addr_t);
148 static void nfe_set_ready_rxdesc(struct nfe_softc *, struct nfe_rx_ring *,
149 int);
150 static int nfe_newbuf_std(struct nfe_softc *, struct nfe_rx_ring *, int,
151 int);
152 static int nfe_newbuf_jumbo(struct nfe_softc *, struct nfe_rx_ring *, int,
153 int);
154
155 static int nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS);
156
157 #define NFE_DEBUG
158 #ifdef NFE_DEBUG
159
160 static int nfe_debug = 0;
161 static int nfe_rx_ring_count = NFE_RX_RING_DEF_COUNT;
162 static int nfe_imtime = -1;
163
164 TUNABLE_INT("hw.nfe.rx_ring_count", &nfe_rx_ring_count);
165 TUNABLE_INT("hw.nfe.imtime", &nfe_imtime);
166 TUNABLE_INT("hw.nfe.debug", &nfe_debug);
167
168 #define DPRINTF(sc, fmt, ...) do { \
169 if ((sc)->sc_debug) { \
170 if_printf(&(sc)->arpcom.ac_if, \
171 fmt, __VA_ARGS__); \
172 } \
173 } while (0)
174
175 #define DPRINTFN(sc, lv, fmt, ...) do { \
176 if ((sc)->sc_debug >= (lv)) { \
177 if_printf(&(sc)->arpcom.ac_if, \
178 fmt, __VA_ARGS__); \
179 } \
180 } while (0)
181
182 #else /* !NFE_DEBUG */
183
184 #define DPRINTF(sc, fmt, ...)
185 #define DPRINTFN(sc, lv, fmt, ...)
186
187 #endif /* NFE_DEBUG */
188
189 struct nfe_dma_ctx {
190 int nsegs;
191 bus_dma_segment_t *segs;
192 };
193
194 static const struct nfe_dev {
195 uint16_t vid;
196 uint16_t did;
197 const char *desc;
198 } nfe_devices[] = {
199 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN,
200 "NVIDIA nForce Fast Ethernet" },
201
202 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN,
203 "NVIDIA nForce2 Fast Ethernet" },
204
205 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1,
206 "NVIDIA nForce3 Gigabit Ethernet" },
207
208 /* XXX TGEN the next chip can also be found in the nForce2 Ultra 400Gb
209 chipset, and possibly also the 400R; it might be both nForce2- and
210 nForce3-based boards can use the same MCPs (= southbridges) */
211 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN2,
212 "NVIDIA nForce3 Gigabit Ethernet" },
213
214 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN3,
215 "NVIDIA nForce3 Gigabit Ethernet" },
216
217 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4,
218 "NVIDIA nForce3 Gigabit Ethernet" },
219
220 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN5,
221 "NVIDIA nForce3 Gigabit Ethernet" },
222
223 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN1,
224 "NVIDIA CK804 Gigabit Ethernet" },
225
226 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_CK804_LAN2,
227 "NVIDIA CK804 Gigabit Ethernet" },
228
229 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1,
230 "NVIDIA MCP04 Gigabit Ethernet" },
231
232 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2,
233 "NVIDIA MCP04 Gigabit Ethernet" },
234
235 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN1,
236 "NVIDIA MCP51 Gigabit Ethernet" },
237
238 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_LAN2,
239 "NVIDIA MCP51 Gigabit Ethernet" },
240
241 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1,
242 "NVIDIA MCP55 Gigabit Ethernet" },
243
244 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2,
245 "NVIDIA MCP55 Gigabit Ethernet" },
246
247 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1,
248 "NVIDIA MCP61 Gigabit Ethernet" },
249
250 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2,
251 "NVIDIA MCP61 Gigabit Ethernet" },
252
253 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3,
254 "NVIDIA MCP61 Gigabit Ethernet" },
255
256 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4,
257 "NVIDIA MCP61 Gigabit Ethernet" },
258
259 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1,
260 "NVIDIA MCP65 Gigabit Ethernet" },
261
262 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2,
263 "NVIDIA MCP65 Gigabit Ethernet" },
264
265 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3,
266 "NVIDIA MCP65 Gigabit Ethernet" },
267
268 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4,
269 "NVIDIA MCP65 Gigabit Ethernet" },
270
271 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1,
272 "NVIDIA MCP67 Gigabit Ethernet" },
273
274 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2,
275 "NVIDIA MCP67 Gigabit Ethernet" },
276
277 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3,
278 "NVIDIA MCP67 Gigabit Ethernet" },
279
280 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4,
281 "NVIDIA MCP67 Gigabit Ethernet" },
282
283 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1,
284 "NVIDIA MCP73 Gigabit Ethernet" },
285
286 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2,
287 "NVIDIA MCP73 Gigabit Ethernet" },
288
289 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3,
290 "NVIDIA MCP73 Gigabit Ethernet" },
291
292 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4,
293 "NVIDIA MCP73 Gigabit Ethernet" },
294
295 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1,
296 "NVIDIA MCP77 Gigabit Ethernet" },
297
298 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2,
299 "NVIDIA MCP77 Gigabit Ethernet" },
300
301 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3,
302 "NVIDIA MCP77 Gigabit Ethernet" },
303
304 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4,
305 "NVIDIA MCP77 Gigabit Ethernet" },
306
307 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1,
308 "NVIDIA MCP79 Gigabit Ethernet" },
309
310 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2,
311 "NVIDIA MCP79 Gigabit Ethernet" },
312
313 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3,
314 "NVIDIA MCP79 Gigabit Ethernet" },
315
316 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4,
317 "NVIDIA MCP79 Gigabit Ethernet" },
318
319 { 0, 0, NULL }
320 };
321
322 static device_method_t nfe_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, nfe_probe),
325 DEVMETHOD(device_attach, nfe_attach),
326 DEVMETHOD(device_detach, nfe_detach),
327 DEVMETHOD(device_suspend, nfe_suspend),
328 DEVMETHOD(device_resume, nfe_resume),
329 DEVMETHOD(device_shutdown, nfe_shutdown),
330
331 /* Bus interface */
332 DEVMETHOD(bus_print_child, bus_generic_print_child),
333 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
334
335 /* MII interface */
336 DEVMETHOD(miibus_readreg, nfe_miibus_readreg),
337 DEVMETHOD(miibus_writereg, nfe_miibus_writereg),
338 DEVMETHOD(miibus_statchg, nfe_miibus_statchg),
339
340 { 0, 0 }
341 };
342
343 static driver_t nfe_driver = {
344 "nfe",
345 nfe_methods,
346 sizeof(struct nfe_softc)
347 };
348
349 static devclass_t nfe_devclass;
350
351 DECLARE_DUMMY_MODULE(if_nfe);
352 MODULE_DEPEND(if_nfe, miibus, 1, 1, 1);
353 DRIVER_MODULE(if_nfe, pci, nfe_driver, nfe_devclass, 0, 0);
354 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0);
355
356 static int
357 nfe_probe(device_t dev)
358 {
359 const struct nfe_dev *n;
360 uint16_t vid, did;
361
362 vid = pci_get_vendor(dev);
363 did = pci_get_device(dev);
364 for (n = nfe_devices; n->desc != NULL; ++n) {
365 if (vid == n->vid && did == n->did) {
366 struct nfe_softc *sc = device_get_softc(dev);
367
368 switch (did) {
369 case PCI_PRODUCT_NVIDIA_NFORCE_LAN:
370 case PCI_PRODUCT_NVIDIA_NFORCE2_LAN:
371 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN1:
372 sc->sc_flags = NFE_NO_PWRCTL;
373 break;
374 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2:
375 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3:
376 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4:
377 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5:
378 sc->sc_flags = NFE_JUMBO_SUP |
379 NFE_HW_CSUM |
380 NFE_NO_PWRCTL;
381 break;
382 case PCI_PRODUCT_NVIDIA_MCP51_LAN1:
383 case PCI_PRODUCT_NVIDIA_MCP51_LAN2:
384 case PCI_PRODUCT_NVIDIA_MCP61_LAN1:
385 case PCI_PRODUCT_NVIDIA_MCP61_LAN2:
386 case PCI_PRODUCT_NVIDIA_MCP61_LAN3:
387 case PCI_PRODUCT_NVIDIA_MCP61_LAN4:
388 case PCI_PRODUCT_NVIDIA_MCP67_LAN1:
389 case PCI_PRODUCT_NVIDIA_MCP67_LAN2:
390 case PCI_PRODUCT_NVIDIA_MCP67_LAN3:
391 case PCI_PRODUCT_NVIDIA_MCP67_LAN4:
392 case PCI_PRODUCT_NVIDIA_MCP73_LAN1:
393 case PCI_PRODUCT_NVIDIA_MCP73_LAN2:
394 case PCI_PRODUCT_NVIDIA_MCP73_LAN3:
395 case PCI_PRODUCT_NVIDIA_MCP73_LAN4:
396 sc->sc_flags = NFE_40BIT_ADDR;
397 break;
398 case PCI_PRODUCT_NVIDIA_CK804_LAN1:
399 case PCI_PRODUCT_NVIDIA_CK804_LAN2:
400 case PCI_PRODUCT_NVIDIA_MCP04_LAN1:
401 case PCI_PRODUCT_NVIDIA_MCP04_LAN2:
402 sc->sc_flags = NFE_JUMBO_SUP |
403 NFE_40BIT_ADDR |
404 NFE_HW_CSUM |
405 NFE_NO_PWRCTL;
406 break;
407 case PCI_PRODUCT_NVIDIA_MCP65_LAN1:
408 case PCI_PRODUCT_NVIDIA_MCP65_LAN2:
409 case PCI_PRODUCT_NVIDIA_MCP65_LAN3:
410 case PCI_PRODUCT_NVIDIA_MCP65_LAN4:
411 sc->sc_flags = NFE_JUMBO_SUP |
412 NFE_40BIT_ADDR;
413 break;
414 case PCI_PRODUCT_NVIDIA_MCP55_LAN1:
415 case PCI_PRODUCT_NVIDIA_MCP55_LAN2:
416 sc->sc_flags = NFE_JUMBO_SUP |
417 NFE_40BIT_ADDR |
418 NFE_HW_CSUM |
419 NFE_HW_VLAN;
420 break;
421 case PCI_PRODUCT_NVIDIA_MCP77_LAN1:
422 case PCI_PRODUCT_NVIDIA_MCP77_LAN2:
423 case PCI_PRODUCT_NVIDIA_MCP77_LAN3:
424 case PCI_PRODUCT_NVIDIA_MCP77_LAN4:
425 case PCI_PRODUCT_NVIDIA_MCP79_LAN1:
426 case PCI_PRODUCT_NVIDIA_MCP79_LAN2:
427 case PCI_PRODUCT_NVIDIA_MCP79_LAN3:
428 case PCI_PRODUCT_NVIDIA_MCP79_LAN4:
429 sc->sc_flags = NFE_40BIT_ADDR |
430 NFE_HW_CSUM;
431 break;
432 }
433
434 device_set_desc(dev, n->desc);
435 device_set_async_attach(dev, TRUE);
436 return 0;
437 }
438 }
439 return ENXIO;
440 }
441
442 static int
443 nfe_attach(device_t dev)
444 {
445 struct nfe_softc *sc = device_get_softc(dev);
446 struct ifnet *ifp = &sc->arpcom.ac_if;
447 uint8_t eaddr[ETHER_ADDR_LEN];
448 int error;
449
450 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
451 lwkt_serialize_init(&sc->sc_jbuf_serializer);
452
453 /*
454 * Initialize sysctl variables
455 */
456 sc->sc_imtime = nfe_imtime;
457 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
458 sc->sc_rx_ring_count = nfe_rx_ring_count;
459 sc->sc_debug = nfe_debug;
460
461 sc->sc_mem_rid = PCIR_BAR(0);
462
463 #ifndef BURN_BRIDGES
464 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
465 uint32_t mem, irq;
466
467 mem = pci_read_config(dev, sc->sc_mem_rid, 4);
468 irq = pci_read_config(dev, PCIR_INTLINE, 4);
469
470 device_printf(dev, "chip is in D%d power mode "
471 "-- setting to D0\n", pci_get_powerstate(dev));
472
473 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
474
475 pci_write_config(dev, sc->sc_mem_rid, mem, 4);
476 pci_write_config(dev, PCIR_INTLINE, irq, 4);
477 }
478 #endif /* !BURN_BRIDGE */
479
480 /* Enable bus mastering */
481 pci_enable_busmaster(dev);
482
483 /* Allocate IO memory */
484 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
485 &sc->sc_mem_rid, RF_ACTIVE);
486 if (sc->sc_mem_res == NULL) {
487 device_printf(dev, "cound not allocate io memory\n");
488 return ENXIO;
489 }
490 sc->sc_memh = rman_get_bushandle(sc->sc_mem_res);
491 sc->sc_memt = rman_get_bustag(sc->sc_mem_res);
492
493 /* Allocate IRQ */
494 sc->sc_irq_rid = 0;
495 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
496 &sc->sc_irq_rid,
497 RF_SHAREABLE | RF_ACTIVE);
498 if (sc->sc_irq_res == NULL) {
499 device_printf(dev, "could not allocate irq\n");
500 error = ENXIO;
501 goto fail;
502 }
503
504 nfe_get_macaddr(sc, eaddr);
505
506 /*
507 * Allocate Tx and Rx rings.
508 */
509 error = nfe_alloc_tx_ring(sc, &sc->txq);
510 if (error) {
511 device_printf(dev, "could not allocate Tx ring\n");
512 goto fail;
513 }
514
515 error = nfe_alloc_rx_ring(sc, &sc->rxq);
516 if (error) {
517 device_printf(dev, "could not allocate Rx ring\n");
518 goto fail;
519 }
520
521 /*
522 * Create sysctl tree
523 */
524 sysctl_ctx_init(&sc->sc_sysctl_ctx);
525 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
526 SYSCTL_STATIC_CHILDREN(_hw),
527 OID_AUTO,
528 device_get_nameunit(dev),
529 CTLFLAG_RD, 0, "");
530 if (sc->sc_sysctl_tree == NULL) {
531 device_printf(dev, "can't add sysctl node\n");
532 error = ENXIO;
533 goto fail;
534 }
535 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
536 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
537 OID_AUTO, "imtimer", CTLTYPE_INT | CTLFLAG_RW,
538 sc, 0, nfe_sysctl_imtime, "I",
539 "Interrupt moderation time (usec). "
540 "-1 to disable interrupt moderation.");
541 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
542 "rx_ring_count", CTLFLAG_RD, &sc->sc_rx_ring_count,
543 0, "RX ring count");
544 SYSCTL_ADD_INT(NULL, SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
545 "debug", CTLFLAG_RW, &sc->sc_debug,
546 0, "control debugging printfs");
547
548 error = mii_phy_probe(dev, &sc->sc_miibus, nfe_ifmedia_upd,
549 nfe_ifmedia_sts);
550 if (error) {
551 device_printf(dev, "MII without any phy\n");
552 goto fail;
553 }
554
555 ifp->if_softc = sc;
556 ifp->if_mtu = ETHERMTU;
557 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
558 ifp->if_ioctl = nfe_ioctl;
559 ifp->if_start = nfe_start;
560 #ifdef DEVICE_POLLING
561 ifp->if_poll = nfe_poll;
562 #endif
563 ifp->if_watchdog = nfe_watchdog;
564 ifp->if_init = nfe_init;
565 ifq_set_maxlen(&ifp->if_snd, NFE_IFQ_MAXLEN);
566 ifq_set_ready(&ifp->if_snd);
567
568 ifp->if_capabilities = IFCAP_VLAN_MTU;
569
570 if (sc->sc_flags & NFE_HW_VLAN)
571 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
572
573 #ifdef NFE_CSUM
574 if (sc->sc_flags & NFE_HW_CSUM) {
575 ifp->if_capabilities |= IFCAP_HWCSUM;
576 ifp->if_hwassist = NFE_CSUM_FEATURES;
577 }
578 #else
579 sc->sc_flags &= ~NFE_HW_CSUM;
580 #endif
581 ifp->if_capenable = ifp->if_capabilities;
582
583 callout_init(&sc->sc_tick_ch);
584
585 ether_ifattach(ifp, eaddr, NULL);
586
587 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, nfe_intr, sc,
588 &sc->sc_ih, ifp->if_serializer);
589 if (error) {
590 device_printf(dev, "could not setup intr\n");
591 ether_ifdetach(ifp);
592 goto fail;
593 }
594
595 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
596 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
597
598 return 0;
599 fail:
600 nfe_detach(dev);
601 return error;
602 }
603
604 static int
605 nfe_detach(device_t dev)
606 {
607 struct nfe_softc *sc = device_get_softc(dev);
608
609 if (device_is_attached(dev)) {
610 struct ifnet *ifp = &sc->arpcom.ac_if;
611
612 lwkt_serialize_enter(ifp->if_serializer);
613 nfe_stop(sc);
614 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_ih);
615 lwkt_serialize_exit(ifp->if_serializer);
616
617 ether_ifdetach(ifp);
618 }
619
620 if (sc->sc_miibus != NULL)
621 device_delete_child(dev, sc->sc_miibus);
622 bus_generic_detach(dev);
623
624 if (sc->sc_sysctl_tree != NULL)
625 sysctl_ctx_free(&sc->sc_sysctl_ctx);
626
627 if (sc->sc_irq_res != NULL) {
628 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
629 sc->sc_irq_res);
630 }
631
632 if (sc->sc_mem_res != NULL) {
633 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
634 sc->sc_mem_res);
635 }
636
637 nfe_free_tx_ring(sc, &sc->txq);
638 nfe_free_rx_ring(sc, &sc->rxq);
639
640 return 0;
641 }
642
643 static void
644 nfe_shutdown(device_t dev)
645 {
646 struct nfe_softc *sc = device_get_softc(dev);
647 struct ifnet *ifp = &sc->arpcom.ac_if;
648
649 lwkt_serialize_enter(ifp->if_serializer);
650 nfe_stop(sc);
651 lwkt_serialize_exit(ifp->if_serializer);
652 }
653
654 static int
655 nfe_suspend(device_t dev)
656 {
657 struct nfe_softc *sc = device_get_softc(dev);
658 struct ifnet *ifp = &sc->arpcom.ac_if;
659
660 lwkt_serialize_enter(ifp->if_serializer);
661 nfe_stop(sc);
662 lwkt_serialize_exit(ifp->if_serializer);
663
664 return 0;
665 }
666
667 static int
668 nfe_resume(device_t dev)
669 {
670 struct nfe_softc *sc = device_get_softc(dev);
671 struct ifnet *ifp = &sc->arpcom.ac_if;
672
673 lwkt_serialize_enter(ifp->if_serializer);
674 if (ifp->if_flags & IFF_UP)
675 nfe_init(sc);
676 lwkt_serialize_exit(ifp->if_serializer);
677
678 return 0;
679 }
680
681 static void
682 nfe_miibus_statchg(device_t dev)
683 {
684 struct nfe_softc *sc = device_get_softc(dev);
685 struct mii_data *mii = device_get_softc(sc->sc_miibus);
686 uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET;
687
688 phy = NFE_READ(sc, NFE_PHY_IFACE);
689 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
690
691 seed = NFE_READ(sc, NFE_RNDSEED);
692 seed &= ~NFE_SEED_MASK;
693
694 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
695 phy |= NFE_PHY_HDX; /* half-duplex */
696 misc |= NFE_MISC1_HDX;
697 }
698
699 switch (IFM_SUBTYPE(mii->mii_media_active)) {
700 case IFM_1000_T: /* full-duplex only */
701 link |= NFE_MEDIA_1000T;
702 seed |= NFE_SEED_1000T;
703 phy |= NFE_PHY_1000T;
704 break;
705 case IFM_100_TX:
706 link |= NFE_MEDIA_100TX;
707 seed |= NFE_SEED_100TX;
708 phy |= NFE_PHY_100TX;
709 break;
710 case IFM_10_T:
711 link |= NFE_MEDIA_10T;
712 seed |= NFE_SEED_10T;
713 break;
714 }
715
716 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */
717
718 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
719 NFE_WRITE(sc, NFE_MISC1, misc);
720 NFE_WRITE(sc, NFE_LINKSPEED, link);
721 }
722
723 static int
724 nfe_miibus_readreg(device_t dev, int phy, int reg)
725 {
726 struct nfe_softc *sc = device_get_softc(dev);
727 uint32_t val;
728 int ntries;
729
730 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
731
732 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
733 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
734 DELAY(100);
735 }
736
737 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg);
738
739 for (ntries = 0; ntries < 1000; ntries++) {
740 DELAY(100);
741 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
742 break;
743 }
744 if (ntries == 1000) {
745 DPRINTFN(sc, 2, "timeout waiting for PHY %s\n", "");
746 return 0;
747 }
748
749 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) {
750 DPRINTFN(sc, 2, "could not read PHY %s\n", "");
751 return 0;
752 }
753
754 val = NFE_READ(sc, NFE_PHY_DATA);
755 if (val != 0xffffffff && val != 0)
756 sc->mii_phyaddr = phy;
757
758 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val);
759
760 return val;
761 }
762
763 static void
764 nfe_miibus_writereg(device_t dev, int phy, int reg, int val)
765 {
766 struct nfe_softc *sc = device_get_softc(dev);
767 uint32_t ctl;
768 int ntries;
769
770 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
771
772 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) {
773 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY);
774 DELAY(100);
775 }
776
777 NFE_WRITE(sc, NFE_PHY_DATA, val);
778 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg;
779 NFE_WRITE(sc, NFE_PHY_CTL, ctl);
780
781 for (ntries = 0; ntries < 1000; ntries++) {
782 DELAY(100);
783 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY))
784 break;
785 }
786
787 #ifdef NFE_DEBUG
788 if (ntries == 1000)
789 DPRINTFN(sc, 2, "could not write to PHY %s\n", "");
790 #endif
791 }
792
793 #ifdef DEVICE_POLLING
794
795 static void
796 nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
797 {
798 struct nfe_softc *sc = ifp->if_softc;
799
800 ASSERT_SERIALIZED(ifp->if_serializer);
801
802 switch(cmd) {
803 case POLL_REGISTER:
804 /* Disable interrupts */
805 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
806 break;
807 case POLL_DEREGISTER:
808 /* enable interrupts */
809 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
810 break;
811 case POLL_AND_CHECK_STATUS:
812 /* fall through */
813 case POLL_ONLY:
814 if (ifp->if_flags & IFF_RUNNING) {
815 nfe_rxeof(sc);
816 nfe_txeof(sc);
817 }
818 break;
819 }
820 }
821
822 #endif
823
824 static void
825 nfe_intr(void *arg)
826 {
827 struct nfe_softc *sc = arg;
828 struct ifnet *ifp = &sc->arpcom.ac_if;
829 uint32_t r;
830
831 r = NFE_READ(sc, NFE_IRQ_STATUS);
832 if (r == 0)
833 return; /* not for us */
834 NFE_WRITE(sc, NFE_IRQ_STATUS, r);
835
836 DPRINTFN(sc, 5, "%s: interrupt register %x\n", __func__, r);
837
838 if (r & NFE_IRQ_LINK) {
839 NFE_READ(sc, NFE_PHY_STATUS);
840 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
841 DPRINTF(sc, "link state changed %s\n", "");
842 }
843
844 if (ifp->if_flags & IFF_RUNNING) {
845 /* check Rx ring */
846 nfe_rxeof(sc);
847
848 /* check Tx ring */
849 nfe_txeof(sc);
850 }
851 }
852
853 static int
854 nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
855 {
856 struct nfe_softc *sc = ifp->if_softc;
857 struct ifreq *ifr = (struct ifreq *)data;
858 struct mii_data *mii;
859 int error = 0, mask;
860
861 switch (cmd) {
862 case SIOCSIFMTU:
863 if (((sc->sc_flags & NFE_JUMBO_SUP) &&
864 ifr->ifr_mtu > NFE_JUMBO_MTU) ||
865 ((sc->sc_flags & NFE_JUMBO_SUP) == 0 &&
866 ifr->ifr_mtu > ETHERMTU)) {
867 return EINVAL;
868 } else if (ifp->if_mtu != ifr->ifr_mtu) {
869 ifp->if_mtu = ifr->ifr_mtu;
870 nfe_init(sc);
871 }
872 break;
873 case SIOCSIFFLAGS:
874 if (ifp->if_flags & IFF_UP) {
875 /*
876 * If only the PROMISC or ALLMULTI flag changes, then
877 * don't do a full re-init of the chip, just update
878 * the Rx filter.
879 */
880 if ((ifp->if_flags & IFF_RUNNING) &&
881 ((ifp->if_flags ^ sc->sc_if_flags) &
882 (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
883 nfe_setmulti(sc);
884 } else {
885 if (!(ifp->if_flags & IFF_RUNNING))
886 nfe_init(sc);
887 }
888 } else {
889 if (ifp->if_flags & IFF_RUNNING)
890 nfe_stop(sc);
891 }
892 sc->sc_if_flags = ifp->if_flags;
893 break;
894 case SIOCADDMULTI:
895 case SIOCDELMULTI:
896 if (ifp->if_flags & IFF_RUNNING)
897 nfe_setmulti(sc);
898 break;
899 case SIOCSIFMEDIA:
900 case SIOCGIFMEDIA:
901 mii = device_get_softc(sc->sc_miibus);
902 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
903 break;
904 case SIOCSIFCAP:
905 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & IFCAP_HWCSUM;
906 if (mask && (ifp->if_capabilities & IFCAP_HWCSUM)) {
907 ifp->if_capenable ^= mask;
908 if (IFCAP_TXCSUM & ifp->if_capenable)
909 ifp->if_hwassist = NFE_CSUM_FEATURES;
910 else
911 ifp->if_hwassist = 0;
912
913 if (ifp->if_flags & IFF_RUNNING)
914 nfe_init(sc);
915 }
916 break;
917 default:
918 error = ether_ioctl(ifp, cmd, data);
919 break;
920 }
921 return error;
922 }
923
924 static void
925 nfe_rxeof(struct nfe_softc *sc)
926 {
927 struct ifnet *ifp = &sc->arpcom.ac_if;
928 struct nfe_rx_ring *ring = &sc->rxq;
929 int reap;
930 #ifdef ETHER_INPUT_CHAIN
931 struct mbuf_chain chain[MAXCPU];
932 #endif
933
934 reap = 0;
935 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
936
937 #ifdef ETHER_INPUT_CHAIN
938 ether_input_chain_init(chain);
939 #endif
940
941 for (;;) {
942 struct nfe_rx_data *data = &ring->data[ring->cur];
943 struct mbuf *m;
944 uint16_t flags;
945 int len, error;
946
947 if (sc->sc_flags & NFE_40BIT_ADDR) {
948 struct nfe_desc64 *desc64 = &ring->desc64[ring->cur];
949
950 flags = le16toh(desc64->flags);
951 len = le16toh(desc64->length) & 0x3fff;
952 } else {
953 struct nfe_desc32 *desc32 = &ring->desc32[ring->cur];
954
955 flags = le16toh(desc32->flags);
956 len = le16toh(desc32->length) & 0x3fff;
957 }
958
959 if (flags & NFE_RX_READY)
960 break;
961
962 reap = 1;
963
964 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
965 if (!(flags & NFE_RX_VALID_V1))
966 goto skip;
967
968 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) {
969 flags &= ~NFE_RX_ERROR;
970 len--; /* fix buffer length */
971 }
972 } else {
973 if (!(flags & NFE_RX_VALID_V2))
974 goto skip;
975
976 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) {
977 flags &= ~NFE_RX_ERROR;
978 len--; /* fix buffer length */
979 }
980 }
981
982 if (flags & NFE_RX_ERROR) {
983 ifp->if_ierrors++;
984 goto skip;
985 }
986
987 m = data->m;
988
989 if (sc->sc_flags & NFE_USE_JUMBO)
990 error = nfe_newbuf_jumbo(sc, ring, ring->cur, 0);
991 else
992 error = nfe_newbuf_std(sc, ring, ring->cur, 0);
993 if (error) {
994 ifp->if_ierrors++;
995 goto skip;
996 }
997
998 /* finalize mbuf */
999 m->m_pkthdr.len = m->m_len = len;
1000 m->m_pkthdr.rcvif = ifp;
1001
1002 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
1003 (flags & NFE_RX_CSUMOK)) {
1004 if (flags & NFE_RX_IP_CSUMOK_V2) {
1005 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1006 CSUM_IP_VALID;
1007 }
1008
1009 if (flags &
1010 (NFE_RX_UDP_CSUMOK_V2 | NFE_RX_TCP_CSUMOK_V2)) {
1011 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1012 CSUM_PSEUDO_HDR |
1013 CSUM_FRAG_NOT_CHECKED;
1014 m->m_pkthdr.csum_data = 0xffff;
1015 }
1016 }
1017
1018 ifp->if_ipackets++;
1019 #ifdef ETHER_INPUT_CHAIN
1020 #ifdef ETHER_INPUT2
1021 ether_input_chain2(ifp, m, chain);
1022 #else
1023 ether_input_chain(ifp, m, chain);
1024 #endif
1025 #else
1026 ifp->if_input(ifp, m);
1027 #endif
1028 skip:
1029 nfe_set_ready_rxdesc(sc, ring, ring->cur);
1030 sc->rxq.cur = (sc->rxq.cur + 1) % sc->sc_rx_ring_count;
1031 }
1032
1033 if (reap) {
1034 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1035 #ifdef ETHER_INPUT_CHAIN
1036 ether_input_dispatch(chain);
1037 #endif
1038 }
1039 }
1040
1041 static void
1042 nfe_txeof(struct nfe_softc *sc)
1043 {
1044 struct ifnet *ifp = &sc->arpcom.ac_if;
1045 struct nfe_tx_ring *ring = &sc->txq;
1046 struct nfe_tx_data *data = NULL;
1047
1048 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_POSTREAD);
1049 while (ring->next != ring->cur) {
1050 uint16_t flags;
1051
1052 if (sc->sc_flags & NFE_40BIT_ADDR)
1053 flags = le16toh(ring->desc64[ring->next].flags);
1054 else
1055 flags = le16toh(ring->desc32[ring->next].flags);
1056
1057 if (flags & NFE_TX_VALID)
1058 break;
1059
1060 data = &ring->data[ring->next];
1061
1062 if ((sc->sc_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) {
1063 if (!(flags & NFE_TX_LASTFRAG_V1) && data->m == NULL)
1064 goto skip;
1065
1066 if ((flags & NFE_TX_ERROR_V1) != 0) {
1067 if_printf(ifp, "tx v1 error 0x%4b\n", flags,
1068 NFE_V1_TXERR);
1069 ifp->if_oerrors++;
1070 } else {
1071 ifp->if_opackets++;
1072 }
1073 } else {
1074 if (!(flags & NFE_TX_LASTFRAG_V2) && data->m == NULL)
1075 goto skip;
1076
1077 if ((flags & NFE_TX_ERROR_V2) != 0) {
1078 if_printf(ifp, "tx v2 error 0x%4b\n", flags,
1079 NFE_V2_TXERR);
1080 ifp->if_oerrors++;
1081 } else {
1082 ifp->if_opackets++;
1083 }
1084 }
1085
1086 if (data->m == NULL) { /* should not get there */
1087 if_printf(ifp,
1088 "last fragment bit w/o associated mbuf!\n");
1089 goto skip;
1090 }
1091
1092 /* last fragment of the mbuf chain transmitted */
1093 bus_dmamap_sync(ring->data_tag, data->map,
1094 BUS_DMASYNC_POSTWRITE);
1095 bus_dmamap_unload(ring->data_tag, data->map);
1096 m_freem(data->m);
1097 data->m = NULL;
1098
1099 ifp->if_timer = 0;
1100 skip:
1101 ring->queued--;
1102 KKASSERT(ring->queued >= 0);
1103 ring->next = (ring->next + 1) % NFE_TX_RING_COUNT;
1104 }
1105
1106 if (data != NULL) { /* at least one slot freed */
1107 ifp->if_flags &= ~IFF_OACTIVE;
1108 if_devstart(ifp);
1109 }
1110 }
1111
1112 static int
1113 nfe_encap(struct nfe_softc *sc, struct nfe_tx_ring *ring, struct mbuf *m0)
1114 {
1115 struct nfe_dma_ctx ctx;
1116 bus_dma_segment_t segs[NFE_MAX_SCATTER];
1117 struct nfe_tx_data *data, *data_map;
1118 bus_dmamap_t map;
1119 struct nfe_desc64 *desc64 = NULL;
1120 struct nfe_desc32 *desc32 = NULL;
1121 uint16_t flags = 0;
1122 uint32_t vtag = 0;
1123 int error, i, j;
1124
1125 data = &ring->data[ring->cur];
1126 map = data->map;
1127 data_map = data; /* Remember who owns the DMA map */
1128
1129 ctx.nsegs = NFE_MAX_SCATTER;
1130 ctx.segs = segs;
1131 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1132 nfe_buf_dma_addr, &ctx, BUS_DMA_NOWAIT);
1133 if (error && error != EFBIG) {
1134 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
1135 goto back;
1136 }
1137
1138 if (error) { /* error == EFBIG */
1139 struct mbuf *m_new;
1140
1141 m_new = m_defrag(m0, MB_DONTWAIT);
1142 if (m_new == NULL) {
1143 if_printf(&sc->arpcom.ac_if,
1144 "could not defrag TX mbuf\n");
1145 error = ENOBUFS;
1146 goto back;
1147 } else {
1148 m0 = m_new;
1149 }
1150
1151 ctx.nsegs = NFE_MAX_SCATTER;
1152 ctx.segs = segs;
1153 error = bus_dmamap_load_mbuf(ring->data_tag, map, m0,
1154 nfe_buf_dma_addr, &ctx,
1155 BUS_DMA_NOWAIT);
1156 if (error) {
1157 if_printf(&sc->arpcom.ac_if,
1158 "could not map defraged TX mbuf\n");
1159 goto back;
1160 }
1161 }
1162
1163 error = 0;
1164
1165 if (ring->queued + ctx.nsegs >= NFE_TX_RING_COUNT - 1) {
1166 bus_dmamap_unload(ring->data_tag, map);
1167 error = ENOBUFS;
1168 goto back;
1169 }
1170
1171 /* setup h/w VLAN tagging */
1172 if (m0->m_flags & M_VLANTAG)
1173 vtag = m0->m_pkthdr.ether_vlantag;
1174
1175 if (sc->arpcom.ac_if.if_capenable & IFCAP_TXCSUM) {
1176 if (m0->m_pkthdr.csum_flags & CSUM_IP)
1177 flags |= NFE_TX_IP_CSUM;
1178 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1179 flags |= NFE_TX_TCP_CSUM;
1180 }
1181
1182 /*
1183 * XXX urm. somebody is unaware of how hardware works. You
1184 * absolutely CANNOT set NFE_TX_VALID on the next descriptor in
1185 * the ring until the entire chain is actually *VALID*. Otherwise
1186 * the hardware may encounter a partially initialized chain that
1187 * is marked as being ready to go when it in fact is not ready to
1188 * go.
1189 */
1190
1191 for (i = 0; i < ctx.nsegs; i++) {
1192 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1193 data = &ring->data[j];
1194
1195 if (sc->sc_flags & NFE_40BIT_ADDR) {
1196 desc64 = &ring->desc64[j];
1197 #if defined(__LP64__)
1198 desc64->physaddr[0] =
1199 htole32(segs[i].ds_addr >> 32);
1200 #endif
1201 desc64->physaddr[1] =
1202 htole32(segs[i].ds_addr & 0xffffffff);
1203 desc64->length = htole16(segs[i].ds_len - 1);
1204 desc64->vtag = htole32(vtag);
1205 desc64->flags = htole16(flags);
1206 } else {
1207 desc32 = &ring->desc32[j];
1208 desc32->physaddr = htole32(segs[i].ds_addr);
1209 desc32->length = htole16(segs[i].ds_len - 1);
1210 desc32->flags = htole16(flags);
1211 }
1212
1213 /* csum flags and vtag belong to the first fragment only */
1214 flags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_CSUM);
1215 vtag = 0;
1216
1217 ring->queued++;
1218 KKASSERT(ring->queued <= NFE_TX_RING_COUNT);
1219 }
1220
1221 /* the whole mbuf chain has been DMA mapped, fix last descriptor */
1222 if (sc->sc_flags & NFE_40BIT_ADDR) {
1223 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2);
1224 } else {
1225 if (sc->sc_flags & NFE_JUMBO_SUP)
1226 flags = NFE_TX_LASTFRAG_V2;
1227 else
1228 flags = NFE_TX_LASTFRAG_V1;
1229 desc32->flags |= htole16(flags);
1230 }
1231
1232 /*
1233 * Set NFE_TX_VALID backwards so the hardware doesn't see the
1234 * whole mess until the first descriptor in the map is flagged.
1235 */
1236 for (i = ctx.nsegs - 1; i >= 0; --i) {
1237 j = (ring->cur + i) % NFE_TX_RING_COUNT;
1238 if (sc->sc_flags & NFE_40BIT_ADDR) {
1239 desc64 = &ring->desc64[j];
1240 desc64->flags |= htole16(NFE_TX_VALID);
1241 } else {
1242 desc32 = &ring->desc32[j];
1243 desc32->flags |= htole16(NFE_TX_VALID);
1244 }
1245 }
1246 ring->cur = (ring->cur + ctx.nsegs) % NFE_TX_RING_COUNT;
1247
1248 /* Exchange DMA map */
1249 data_map->map = data->map;
1250 data->map = map;
1251 data->m = m0;
1252
1253 bus_dmamap_sync(ring->data_tag, map, BUS_DMASYNC_PREWRITE);
1254 back:
1255 if (error)
1256 m_freem(m0);
1257 return error;
1258 }
1259
1260 static void
1261 nfe_start(struct ifnet *ifp)
1262 {
1263 struct nfe_softc *sc = ifp->if_softc;
1264 struct nfe_tx_ring *ring = &sc->txq;
1265 int count = 0;
1266 struct mbuf *m0;
1267
1268 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1269 return;
1270
1271 for (;;) {
1272 m0 = ifq_dequeue(&ifp->if_snd, NULL);
1273 if (m0 == NULL)
1274 break;
1275
1276 ETHER_BPF_MTAP(ifp, m0);
1277
1278 if (nfe_encap(sc, ring, m0) != 0) {
1279 ifp->if_flags |= IFF_OACTIVE;
1280 break;
1281 }
1282 ++count;
1283
1284 /*
1285 * NOTE:
1286 * `m0' may be freed in nfe_encap(), so
1287 * it should not be touched any more.
1288 */
1289 }
1290 if (count == 0) /* nothing sent */
1291 return;
1292
1293 /* Sync TX descriptor ring */
1294 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1295
1296 /* Kick Tx */
1297 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl);
1298
1299 /*
1300 * Set a timeout in case the chip goes out to lunch.
1301 */
1302 ifp->if_timer = 5;
1303 }
1304
1305 static void
1306 nfe_watchdog(struct ifnet *ifp)
1307 {
1308 struct nfe_softc *sc = ifp->if_softc;
1309
1310 if (ifp->if_flags & IFF_RUNNING) {
1311 if_printf(ifp, "watchdog timeout - lost interrupt recovered\n");
1312 nfe_txeof(sc);
1313 return;
1314 }
1315
1316 if_printf(ifp, "watchdog timeout\n");
1317
1318 nfe_init(ifp->if_softc);
1319
1320 ifp->if_oerrors++;
1321 }
1322
1323 static void
1324 nfe_init(void *xsc)
1325 {
1326 struct nfe_softc *sc = xsc;
1327 struct ifnet *ifp = &sc->arpcom.ac_if;
1328 uint32_t tmp;
1329 int error;
1330
1331 nfe_stop(sc);
1332
1333 /*
1334 * NOTE:
1335 * Switching between jumbo frames and normal frames should
1336 * be done _after_ nfe_stop() but _before_ nfe_init_rx_ring().
1337 */
1338 if (ifp->if_mtu > ETHERMTU) {
1339 sc->sc_flags |= NFE_USE_JUMBO;
1340 sc->rxq.bufsz = NFE_JBYTES;
1341 if (bootverbose)
1342 if_printf(ifp, "use jumbo frames\n");
1343 } else {
1344 sc->sc_flags &= ~NFE_USE_JUMBO;
1345 sc->rxq.bufsz = MCLBYTES;
1346 if (bootverbose)
1347 if_printf(ifp, "use non-jumbo frames\n");
1348 }
1349
1350 error = nfe_init_tx_ring(sc, &sc->txq);
1351 if (error) {
1352 nfe_stop(sc);
1353 return;
1354 }
1355
1356 error = nfe_init_rx_ring(sc, &sc->rxq);
1357 if (error) {
1358 nfe_stop(sc);
1359 return;
1360 }
1361
1362 NFE_WRITE(sc, NFE_TX_POLL, 0);
1363 NFE_WRITE(sc, NFE_STATUS, 0);
1364
1365 sc->rxtxctl = NFE_RXTX_BIT2;
1366 if (sc->sc_flags & NFE_40BIT_ADDR)
1367 sc->rxtxctl |= NFE_RXTX_V3MAGIC;
1368 else if (sc->sc_flags & NFE_JUMBO_SUP)
1369 sc->rxtxctl |= NFE_RXTX_V2MAGIC;
1370
1371 if (ifp->if_capenable & IFCAP_RXCSUM)
1372 sc->rxtxctl |= NFE_RXTX_RXCSUM;
1373
1374 /*
1375 * Although the adapter is capable of stripping VLAN tags from received
1376 * frames (NFE_RXTX_VTAG_STRIP), we do not enable this functionality on
1377 * purpose. This will be done in software by our network stack.
1378 */
1379 if (sc->sc_flags & NFE_HW_VLAN)
1380 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT;
1381
1382 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl);
1383 DELAY(10);
1384 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1385
1386 if (sc->sc_flags & NFE_HW_VLAN)
1387 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE);
1388
1389 NFE_WRITE(sc, NFE_SETUP_R6, 0);
1390
1391 /* set MAC address */
1392 nfe_set_macaddr(sc, sc->arpcom.ac_enaddr);
1393
1394 /* tell MAC where rings are in memory */
1395 #ifdef __LP64__
1396 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, sc->rxq.physaddr >> 32);
1397 #endif
1398 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, sc->rxq.physaddr & 0xffffffff);
1399 #ifdef __LP64__
1400 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, sc->txq.physaddr >> 32);
1401 #endif
1402 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, sc->txq.physaddr & 0xffffffff);
1403
1404 NFE_WRITE(sc, NFE_RING_SIZE,
1405 (sc->sc_rx_ring_count - 1) << 16 |
1406 (NFE_TX_RING_COUNT - 1));
1407
1408 NFE_WRITE(sc, NFE_RXBUFSZ, sc->rxq.bufsz);
1409
1410 /* force MAC to wakeup */
1411 tmp = NFE_READ(sc, NFE_PWR_STATE);
1412 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_WAKEUP);
1413 DELAY(10);
1414 tmp = NFE_READ(sc, NFE_PWR_STATE);
1415 NFE_WRITE(sc, NFE_PWR_STATE, tmp | NFE_PWR_VALID);
1416
1417 /*
1418 * NFE_IMTIMER generates a periodic interrupt via NFE_IRQ_TIMER.
1419 * It is unclear how wide the timer is. Base programming does
1420 * not seem to effect NFE_IRQ_TX_DONE or NFE_IRQ_RX_DONE so
1421 * we don't get any interrupt moderation. TX moderation is
1422 * possible by using the timer interrupt instead of TX_DONE.
1423 *
1424 * It is unclear whether there are other bits that can be
1425 * set to make the NFE device actually do interrupt moderation
1426 * on the RX side.
1427 *
1428 * For now set a 128uS interval as a placemark, but don't use
1429 * the timer.
1430 */
1431 if (sc->sc_imtime < 0)
1432 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME_DEFAULT);
1433 else
1434 NFE_WRITE(sc, NFE_IMTIMER, NFE_IMTIME(sc->sc_imtime));
1435
1436 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC);
1437 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC);
1438 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC);
1439
1440 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */
1441 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC);
1442
1443 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC);
1444 NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC);
1445
1446 sc->rxtxctl &= ~NFE_RXTX_BIT2;
1447 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl);
1448 DELAY(10);
1449 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl);
1450
1451 /* set Rx filter */
1452 nfe_setmulti(sc);
1453
1454 nfe_ifmedia_upd(ifp);
1455
1456 /* enable Rx */
1457 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START);
1458
1459 /* enable Tx */
1460 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START);
1461
1462 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf);
1463
1464 #ifdef DEVICE_POLLING
1465 if ((ifp->if_flags & IFF_POLLING) == 0)
1466 #endif
1467 /* enable interrupts */
1468 NFE_WRITE(sc, NFE_IRQ_MASK, sc->sc_irq_enable);
1469
1470 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
1471
1472 ifp->if_flags |= IFF_RUNNING;
1473 ifp->if_flags &= ~IFF_OACTIVE;
1474
1475 /*
1476 * If we had stuff in the tx ring before its all cleaned out now
1477 * so we are not going to get an interrupt, jump-start any pending
1478 * output.
1479 */
1480 if_devstart(ifp);
1481 }
1482
1483 static void
1484 nfe_stop(struct nfe_softc *sc)
1485 {
1486 struct ifnet *ifp = &sc->arpcom.ac_if;
1487
1488 callout_stop(&sc->sc_tick_ch);
1489
1490 ifp->if_timer = 0;
1491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1492
1493 /*
1494 * Are NFE_TX_CTL and NFE_RX_CTL polled by the chip microcontroller
1495 * or do they directly reset/terminate the DMA hardware? Nobody
1496 * knows.
1497 *
1498 * Add two delays:
1499 *
1500 * (1) Delay before zeroing out NFE_TX_CTL. This seems to help a
1501 * watchdog timeout that occurs after a stop/init sequence. I am
1502 * theorizing that a TX KICK occuring just prior to a reinit (e.g.
1503 * due to dhclient) is queueing an interrupt to the microcontroller
1504 * which gets delayed until after we clear the control registers
1505 * down below, resulting in mass confusion. TX KICK is clearly
1506 * hardware aided whereas the other bits in the control register
1507 * are more likely to be polled by the microcontroller.
1508 *
1509 * (2) Delay after zeroing out TX and RX CTL registers, under the
1510 * assumption that primary DMA is initiated and terminated by
1511 * the microcontroller and not hardware (and anyway, one can hardly
1512 * expect the DMA engine to just instantly stop!). We don't want
1513 * to rip the rings out from under it before it has had a chance to
1514 * actually stop!
1515 */
1516 DELAY(1000);
1517
1518 /* Abort Tx */
1519 NFE_WRITE(sc, NFE_TX_CTL, 0);
1520
1521 /* Disable Rx */
1522 NFE_WRITE(sc, NFE_RX_CTL, 0);
1523
1524 /* Disable interrupts */
1525 NFE_WRITE(sc, NFE_IRQ_MASK, 0);
1526
1527 DELAY(1000);
1528
1529 /* Reset Tx and Rx rings */
1530 nfe_reset_tx_ring(sc, &sc->txq);
1531 nfe_reset_rx_ring(sc, &sc->rxq);
1532 }
1533
1534 static int
1535 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1536 {
1537 int i, j, error, descsize;
1538 void **desc;
1539
1540 if (sc->sc_flags & NFE_40BIT_ADDR) {
1541 desc = (void **)&ring->desc64;
1542 descsize = sizeof(struct nfe_desc64);
1543 } else {
1544 desc = (void **)&ring->desc32;
1545 descsize = sizeof(struct nfe_desc32);
1546 }
1547
1548 ring->jbuf = kmalloc(sizeof(struct nfe_jbuf) * NFE_JPOOL_COUNT,
1549 M_DEVBUF, M_WAITOK | M_ZERO);
1550 ring->data = kmalloc(sizeof(struct nfe_rx_data) * sc->sc_rx_ring_count,
1551 M_DEVBUF, M_WAITOK | M_ZERO);
1552
1553 ring->bufsz = MCLBYTES;
1554 ring->cur = ring->next = 0;
1555
1556 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1557 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1558 NULL, NULL,
1559 sc->sc_rx_ring_count * descsize, 1,
1560 sc->sc_rx_ring_count * descsize,
1561 0, &ring->tag);
1562 if (error) {
1563 if_printf(&sc->arpcom.ac_if,
1564 "could not create desc RX DMA tag\n");
1565 return error;
1566 }
1567
1568 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1569 &ring->map);
1570 if (error) {
1571 if_printf(&sc->arpcom.ac_if,
1572 "could not allocate RX desc DMA memory\n");
1573 bus_dma_tag_destroy(ring->tag);
1574 ring->tag = NULL;
1575 return error;
1576 }
1577
1578 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1579 sc->sc_rx_ring_count * descsize,
1580 nfe_ring_dma_addr, &ring->physaddr,
1581 BUS_DMA_WAITOK);
1582 if (error) {
1583 if_printf(&sc->arpcom.ac_if,
1584 "could not load RX desc DMA map\n");
1585 bus_dmamem_free(ring->tag, *desc, ring->map);
1586 bus_dma_tag_destroy(ring->tag);
1587 ring->tag = NULL;
1588 return error;
1589 }
1590
1591 if (sc->sc_flags & NFE_JUMBO_SUP) {
1592 error = nfe_jpool_alloc(sc, ring);
1593 if (error) {
1594 if_printf(&sc->arpcom.ac_if,
1595 "could not allocate jumbo frames\n");
1596 return error;
1597 }
1598 }
1599
1600 error = bus_dma_tag_create(NULL, 1, 0,
1601 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1602 NULL, NULL,
1603 MCLBYTES, 1, MCLBYTES,
1604 0, &ring->data_tag);
1605 if (error) {
1606 if_printf(&sc->arpcom.ac_if,
1607 "could not create RX mbuf DMA tag\n");
1608 return error;
1609 }
1610
1611 /* Create a spare RX mbuf DMA map */
1612 error = bus_dmamap_create(ring->data_tag, 0, &ring->data_tmpmap);
1613 if (error) {
1614 if_printf(&sc->arpcom.ac_if,
1615 "could not create spare RX mbuf DMA map\n");
1616 bus_dma_tag_destroy(ring->data_tag);
1617 ring->data_tag = NULL;
1618 return error;
1619 }
1620
1621 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1622 error = bus_dmamap_create(ring->data_tag, 0,
1623 &ring->data[i].map);
1624 if (error) {
1625 if_printf(&sc->arpcom.ac_if,
1626 "could not create %dth RX mbuf DMA mapn", i);
1627 goto fail;
1628 }
1629 }
1630 return 0;
1631 fail:
1632 for (j = 0; j < i; ++j)
1633 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1634 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1635 bus_dma_tag_destroy(ring->data_tag);
1636 ring->data_tag = NULL;
1637 return error;
1638 }
1639
1640 static void
1641 nfe_reset_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1642 {
1643 int i;
1644
1645 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1646 struct nfe_rx_data *data = &ring->data[i];
1647
1648 if (data->m != NULL) {
1649 if ((sc->sc_flags & NFE_USE_JUMBO) == 0)
1650 bus_dmamap_unload(ring->data_tag, data->map);
1651 m_freem(data->m);
1652 data->m = NULL;
1653 }
1654 }
1655 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1656
1657 ring->cur = ring->next = 0;
1658 }
1659
1660 static int
1661 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1662 {
1663 int i;
1664
1665 for (i = 0; i < sc->sc_rx_ring_count; ++i) {
1666 int error;
1667
1668 /* XXX should use a function pointer */
1669 if (sc->sc_flags & NFE_USE_JUMBO)
1670 error = nfe_newbuf_jumbo(sc, ring, i, 1);
1671 else
1672 error = nfe_newbuf_std(sc, ring, i, 1);
1673 if (error) {
1674 if_printf(&sc->arpcom.ac_if,
1675 "could not allocate RX buffer\n");
1676 return error;
1677 }
1678
1679 nfe_set_ready_rxdesc(sc, ring, i);
1680 }
1681 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1682
1683 return 0;
1684 }
1685
1686 static void
1687 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1688 {
1689 if (ring->data_tag != NULL) {
1690 struct nfe_rx_data *data;
1691 int i;
1692
1693 for (i = 0; i < sc->sc_rx_ring_count; i++) {
1694 data = &ring->data[i];
1695
1696 if (data->m != NULL) {
1697 bus_dmamap_unload(ring->data_tag, data->map);
1698 m_freem(data->m);
1699 }
1700 bus_dmamap_destroy(ring->data_tag, data->map);
1701 }
1702 bus_dmamap_destroy(ring->data_tag, ring->data_tmpmap);
1703 bus_dma_tag_destroy(ring->data_tag);
1704 }
1705
1706 nfe_jpool_free(sc, ring);
1707
1708 if (ring->jbuf != NULL)
1709 kfree(ring->jbuf, M_DEVBUF);
1710 if (ring->data != NULL)
1711 kfree(ring->data, M_DEVBUF);
1712
1713 if (ring->tag != NULL) {
1714 void *desc;
1715
1716 if (sc->sc_flags & NFE_40BIT_ADDR)
1717 desc = ring->desc64;
1718 else
1719 desc = ring->desc32;
1720
1721 bus_dmamap_unload(ring->tag, ring->map);
1722 bus_dmamem_free(ring->tag, desc, ring->map);
1723 bus_dma_tag_destroy(ring->tag);
1724 }
1725 }
1726
1727 static struct nfe_jbuf *
1728 nfe_jalloc(struct nfe_softc *sc)
1729 {
1730 struct ifnet *ifp = &sc->arpcom.ac_if;
1731 struct nfe_jbuf *jbuf;
1732
1733 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1734
1735 jbuf = SLIST_FIRST(&sc->rxq.jfreelist);
1736 if (jbuf != NULL) {
1737 SLIST_REMOVE_HEAD(&sc->rxq.jfreelist, jnext);
1738 jbuf->inuse = 1;
1739 } else {
1740 if_printf(ifp, "no free jumbo buffer\n");
1741 }
1742
1743 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1744
1745 return jbuf;
1746 }
1747
1748 static void
1749 nfe_jfree(void *arg)
1750 {
1751 struct nfe_jbuf *jbuf = arg;
1752 struct nfe_softc *sc = jbuf->sc;
1753 struct nfe_rx_ring *ring = jbuf->ring;
1754
1755 if (&ring->jbuf[jbuf->slot] != jbuf)
1756 panic("%s: free wrong jumbo buffer\n", __func__);
1757 else if (jbuf->inuse == 0)
1758 panic("%s: jumbo buffer already freed\n", __func__);
1759
1760 lwkt_serialize_enter(&sc->sc_jbuf_serializer);
1761 atomic_subtract_int(&jbuf->inuse, 1);
1762 if (jbuf->inuse == 0)
1763 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1764 lwkt_serialize_exit(&sc->sc_jbuf_serializer);
1765 }
1766
1767 static void
1768 nfe_jref(void *arg)
1769 {
1770 struct nfe_jbuf *jbuf = arg;
1771 struct nfe_rx_ring *ring = jbuf->ring;
1772
1773 if (&ring->jbuf[jbuf->slot] != jbuf)
1774 panic("%s: ref wrong jumbo buffer\n", __func__);
1775 else if (jbuf->inuse == 0)
1776 panic("%s: jumbo buffer already freed\n", __func__);
1777
1778 atomic_add_int(&jbuf->inuse, 1);
1779 }
1780
1781 static int
1782 nfe_jpool_alloc(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1783 {
1784 struct nfe_jbuf *jbuf;
1785 bus_addr_t physaddr;
1786 caddr_t buf;
1787 int i, error;
1788
1789 /*
1790 * Allocate a big chunk of DMA'able memory.
1791 */
1792 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1793 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1794 NULL, NULL,
1795 NFE_JPOOL_SIZE, 1, NFE_JPOOL_SIZE,
1796 0, &ring->jtag);
1797 if (error) {
1798 if_printf(&sc->arpcom.ac_if,
1799 "could not create jumbo DMA tag\n");
1800 return error;
1801 }
1802
1803 error = bus_dmamem_alloc(ring->jtag, (void **)&ring->jpool,
1804 BUS_DMA_WAITOK, &ring->jmap);
1805 if (error) {
1806 if_printf(&sc->arpcom.ac_if,
1807 "could not allocate jumbo DMA memory\n");
1808 bus_dma_tag_destroy(ring->jtag);
1809 ring->jtag = NULL;
1810 return error;
1811 }
1812
1813 error = bus_dmamap_load(ring->jtag, ring->jmap, ring->jpool,
1814 NFE_JPOOL_SIZE, nfe_ring_dma_addr, &physaddr,
1815 BUS_DMA_WAITOK);
1816 if (error) {
1817 if_printf(&sc->arpcom.ac_if,
1818 "could not load jumbo DMA map\n");
1819 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1820 bus_dma_tag_destroy(ring->jtag);
1821 ring->jtag = NULL;
1822 return error;
1823 }
1824
1825 /* ..and split it into 9KB chunks */
1826 SLIST_INIT(&ring->jfreelist);
1827
1828 buf = ring->jpool;
1829 for (i = 0; i < NFE_JPOOL_COUNT; i++) {
1830 jbuf = &ring->jbuf[i];
1831
1832 jbuf->sc = sc;
1833 jbuf->ring = ring;
1834 jbuf->inuse = 0;
1835 jbuf->slot = i;
1836 jbuf->buf = buf;
1837 jbuf->physaddr = physaddr;
1838
1839 SLIST_INSERT_HEAD(&ring->jfreelist, jbuf, jnext);
1840
1841 buf += NFE_JBYTES;
1842 physaddr += NFE_JBYTES;
1843 }
1844
1845 return 0;
1846 }
1847
1848 static void
1849 nfe_jpool_free(struct nfe_softc *sc, struct nfe_rx_ring *ring)
1850 {
1851 if (ring->jtag != NULL) {
1852 bus_dmamap_unload(ring->jtag, ring->jmap);
1853 bus_dmamem_free(ring->jtag, ring->jpool, ring->jmap);
1854 bus_dma_tag_destroy(ring->jtag);
1855 }
1856 }
1857
1858 static int
1859 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1860 {
1861 int i, j, error, descsize;
1862 void **desc;
1863
1864 if (sc->sc_flags & NFE_40BIT_ADDR) {
1865 desc = (void **)&ring->desc64;
1866 descsize = sizeof(struct nfe_desc64);
1867 } else {
1868 desc = (void **)&ring->desc32;
1869 descsize = sizeof(struct nfe_desc32);
1870 }
1871
1872 ring->queued = 0;
1873 ring->cur = ring->next = 0;
1874
1875 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1876 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1877 NULL, NULL,
1878 NFE_TX_RING_COUNT * descsize, 1,
1879 NFE_TX_RING_COUNT * descsize,
1880 0, &ring->tag);
1881 if (error) {
1882 if_printf(&sc->arpcom.ac_if,
1883 "could not create TX desc DMA map\n");
1884 return error;
1885 }
1886
1887 error = bus_dmamem_alloc(ring->tag, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1888 &ring->map);
1889 if (error) {
1890 if_printf(&sc->arpcom.ac_if,
1891 "could not allocate TX desc DMA memory\n");
1892 bus_dma_tag_destroy(ring->tag);
1893 ring->tag = NULL;
1894 return error;
1895 }
1896
1897 error = bus_dmamap_load(ring->tag, ring->map, *desc,
1898 NFE_TX_RING_COUNT * descsize,
1899 nfe_ring_dma_addr, &ring->physaddr,
1900 BUS_DMA_WAITOK);
1901 if (error) {
1902 if_printf(&sc->arpcom.ac_if,
1903 "could not load TX desc DMA map\n");
1904 bus_dmamem_free(ring->tag, *desc, ring->map);
1905 bus_dma_tag_destroy(ring->tag);
1906 ring->tag = NULL;
1907 return error;
1908 }
1909
1910 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0,
1911 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1912 NULL, NULL,
1913 NFE_JBYTES * NFE_MAX_SCATTER,
1914 NFE_MAX_SCATTER, NFE_JBYTES,
1915 0, &ring->data_tag);
1916 if (error) {
1917 if_printf(&sc->arpcom.ac_if,
1918 "could not create TX buf DMA tag\n");
1919 return error;
1920 }
1921
1922 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1923 error = bus_dmamap_create(ring->data_tag, 0,
1924 &ring->data[i].map);
1925 if (error) {
1926 if_printf(&sc->arpcom.ac_if,
1927 "could not create %dth TX buf DMA map\n", i);
1928 goto fail;
1929 }
1930 }
1931
1932 return 0;
1933 fail:
1934 for (j = 0; j < i; ++j)
1935 bus_dmamap_destroy(ring->data_tag, ring->data[i].map);
1936 bus_dma_tag_destroy(ring->data_tag);
1937 ring->data_tag = NULL;
1938 return error;
1939 }
1940
1941 static void
1942 nfe_reset_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1943 {
1944 int i;
1945
1946 for (i = 0; i < NFE_TX_RING_COUNT; i++) {
1947 struct nfe_tx_data *data = &ring->data[i];
1948
1949 if (sc->sc_flags & NFE_40BIT_ADDR)
1950 ring->desc64[i].flags = 0;
1951 else
1952 ring->desc32[i].flags = 0;
1953
1954 if (data->m != NULL) {
1955 bus_dmamap_sync(ring->data_tag, data->map,
1956 BUS_DMASYNC_POSTWRITE);
1957 bus_dmamap_unload(ring->data_tag, data->map);
1958 m_freem(data->m);
1959 data->m = NULL;
1960 }
1961 }
1962 bus_dmamap_sync(ring->tag, ring->map, BUS_DMASYNC_PREWRITE);
1963
1964 ring->queued = 0;
1965 ring->cur = ring->next = 0;
1966 }
1967
1968 static int
1969 nfe_init_tx_ring(struct nfe_softc *sc __unused,
1970 struct nfe_tx_ring *ring __unused)
1971 {
1972 return 0;
1973 }
1974
1975 static void
1976 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring)
1977 {
1978 if (ring->data_tag != NULL) {
1979 struct nfe_tx_data *data;
1980 int i;
1981
1982 for (i = 0; i < NFE_TX_RING_COUNT; ++i) {
1983 data = &ring->data[i];
1984
1985 if (data->m != NULL) {
1986 bus_dmamap_unload(ring->data_tag, data->map);
1987 m_freem(data->m);
1988 }
1989 bus_dmamap_destroy(ring->data_tag, data->map);
1990 }
1991
1992 bus_dma_tag_destroy(ring->data_tag);
1993 }
1994
1995 if (ring->tag != NULL) {
1996 void *desc;
1997
1998 if (sc->sc_flags & NFE_40BIT_ADDR)
1999 desc = ring->desc64;
2000 else
2001 desc = ring->desc32;
2002
2003 bus_dmamap_unload(ring->tag, ring->map);
2004 bus_dmamem_free(ring->tag, desc, ring->map);
2005 bus_dma_tag_destroy(ring->tag);
2006 }
2007 }
2008
2009 static int
2010 nfe_ifmedia_upd(struct ifnet *ifp)
2011 {
2012 struct nfe_softc *sc = ifp->if_softc;
2013 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2014
2015 if (mii->mii_instance != 0) {
2016 struct mii_softc *miisc;
2017
2018 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2019 mii_phy_reset(miisc);
2020 }
2021 mii_mediachg(mii);
2022
2023 return 0;
2024 }
2025
2026 static void
2027 nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2028 {
2029 struct nfe_softc *sc = ifp->if_softc;
2030 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2031
2032 mii_pollstat(mii);
2033 ifmr->ifm_status = mii->mii_media_status;
2034 ifmr->ifm_active = mii->mii_media_active;
2035 }
2036
2037 static void
2038 nfe_setmulti(struct nfe_softc *sc)
2039 {
2040 struct ifnet *ifp = &sc->arpcom.ac_if;
2041 struct ifmultiaddr *ifma;
2042 uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN];
2043 uint32_t filter = NFE_RXFILTER_MAGIC;
2044 int i;
2045
2046 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) {
2047 bzero(addr, ETHER_ADDR_LEN);
2048 bzero(mask, ETHER_ADDR_LEN);
2049 goto done;
2050 }
2051
2052 bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN);
2053 bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN);
2054
2055 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2056 caddr_t maddr;
2057
2058 if (ifma->ifma_addr->sa_family != AF_LINK)
2059 continue;
2060
2061 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2062 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2063 addr[i] &= maddr[i];
2064 mask[i] &= ~maddr[i];
2065 }
2066 }
2067
2068 for (i = 0; i < ETHER_ADDR_LEN; i++)
2069 mask[i] |= addr[i];
2070
2071 done:
2072 addr[0] |= 0x01; /* make sure multicast bit is set */
2073
2074 NFE_WRITE(sc, NFE_MULTIADDR_HI,
2075 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2076 NFE_WRITE(sc, NFE_MULTIADDR_LO,
2077 addr[5] << 8 | addr[4]);
2078 NFE_WRITE(sc, NFE_MULTIMASK_HI,
2079 mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]);
2080 NFE_WRITE(sc, NFE_MULTIMASK_LO,
2081 mask[5] << 8 | mask[4]);
2082
2083 filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PROMISC : NFE_U2M;
2084 NFE_WRITE(sc, NFE_RXFILTER, filter);
2085 }
2086
2087 static void
2088 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr)
2089 {
2090 uint32_t tmp;
2091
2092 tmp = NFE_READ(sc, NFE_MACADDR_LO);
2093 addr[0] = (tmp >> 8) & 0xff;
2094 addr[1] = (tmp & 0xff);
2095
2096 tmp = NFE_READ(sc, NFE_MACADDR_HI);
2097 addr[2] = (tmp >> 24) & 0xff;
2098 addr[3] = (tmp >> 16) & 0xff;
2099 addr[4] = (tmp >> 8) & 0xff;
2100 addr[5] = (tmp & 0xff);
2101 }
2102
2103 static void
2104 nfe_set_macaddr(struct nfe_softc *sc, const uint8_t *addr)
2105 {
2106 NFE_WRITE(sc, NFE_MACADDR_LO,
2107 addr[5] << 8 | addr[4]);
2108 NFE_WRITE(sc, NFE_MACADDR_HI,
2109 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
2110 }
2111
2112 static void
2113 nfe_tick(void *arg)
2114 {
2115 struct nfe_softc *sc = arg;
2116 struct ifnet *ifp = &sc->arpcom.ac_if;
2117 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2118
2119 lwkt_serialize_enter(ifp->if_serializer);
2120
2121 mii_tick(mii);
2122 callout_reset(&sc->sc_tick_ch, hz, nfe_tick, sc);
2123
2124 lwkt_serialize_exit(ifp->if_serializer);
2125 }
2126
2127 static void
2128 nfe_ring_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2129 {
2130 if (error)
2131 return;
2132
2133 KASSERT(nseg == 1, ("too many segments, should be 1\n"));
2134
2135 *((uint32_t *)arg) = seg->ds_addr;
2136 }
2137
2138 static void
2139 nfe_buf_dma_addr(void *arg, bus_dma_segment_t *segs, int nsegs,
2140 bus_size_t mapsz __unused, int error)
2141 {
2142 struct nfe_dma_ctx *ctx = arg;
2143 int i;
2144
2145 if (error)
2146 return;
2147
2148 KASSERT(nsegs <= ctx->nsegs,
2149 ("too many segments(%d), should be <= %d\n",
2150 nsegs, ctx->nsegs));
2151
2152 ctx->nsegs = nsegs;
2153 for (i = 0; i < nsegs; ++i)
2154 ctx->segs[i] = segs[i];
2155 }
2156
2157 static int
2158 nfe_newbuf_std(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2159 int wait)
2160 {
2161 struct nfe_rx_data *data = &ring->data[idx];
2162 struct nfe_dma_ctx ctx;
2163 bus_dma_segment_t seg;
2164 bus_dmamap_t map;
2165 struct mbuf *m;
2166 int error;
2167
2168 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2169 if (m == NULL)
2170 return ENOBUFS;
2171 m->m_len = m->m_pkthdr.len = MCLBYTES;
2172
2173 ctx.nsegs = 1;
2174 ctx.segs = &seg;
2175 error = bus_dmamap_load_mbuf(ring->data_tag, ring->data_tmpmap,
2176 m, nfe_buf_dma_addr, &ctx,
2177 wait ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2178 if (error) {
2179 m_freem(m);
2180 if_printf(&sc->arpcom.ac_if, "could map RX mbuf %d\n", error);
2181 return error;
2182 }
2183
2184 /* Unload originally mapped mbuf */
2185 bus_dmamap_unload(ring->data_tag, data->map);
2186
2187 /* Swap this DMA map with tmp DMA map */
2188 map = data->map;
2189 data->map = ring->data_tmpmap;
2190 ring->data_tmpmap = map;
2191
2192 /* Caller is assumed to have collected the old mbuf */
2193 data->m = m;
2194
2195 nfe_set_paddr_rxdesc(sc, ring, idx, seg.ds_addr);
2196
2197 bus_dmamap_sync(ring->data_tag, data->map, BUS_DMASYNC_PREREAD);
2198 return 0;
2199 }
2200
2201 static int
2202 nfe_newbuf_jumbo(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2203 int wait)
2204 {
2205 struct nfe_rx_data *data = &ring->data[idx];
2206 struct nfe_jbuf *jbuf;
2207 struct mbuf *m;
2208
2209 MGETHDR(m, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2210 if (m == NULL)
2211 return ENOBUFS;
2212
2213 jbuf = nfe_jalloc(sc);
2214 if (jbuf == NULL) {
2215 m_freem(m);
2216 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
2217 "-- packet dropped!\n");
2218 return ENOBUFS;
2219 }
2220
2221 m->m_ext.ext_arg = jbuf;
2222 m->m_ext.ext_buf = jbuf->buf;
2223 m->m_ext.ext_free = nfe_jfree;
2224 m->m_ext.ext_ref = nfe_jref;
2225 m->m_ext.ext_size = NFE_JBYTES;
2226
2227 m->m_data = m->m_ext.ext_buf;
2228 m->m_flags |= M_EXT;
2229 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2230
2231 /* Caller is assumed to have collected the old mbuf */
2232 data->m = m;
2233
2234 nfe_set_paddr_rxdesc(sc, ring, idx, jbuf->physaddr);
2235
2236 bus_dmamap_sync(ring->jtag, ring->jmap, BUS_DMASYNC_PREREAD);
2237 return 0;
2238 }
2239
2240 static void
2241 nfe_set_paddr_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx,
2242 bus_addr_t physaddr)
2243 {
2244 if (sc->sc_flags & NFE_40BIT_ADDR) {
2245 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2246
2247 #if defined(__LP64__)
2248 desc64->physaddr[0] = htole32(physaddr >> 32);
2249 #endif
2250 desc64->physaddr[1] = htole32(physaddr & 0xffffffff);
2251 } else {
2252 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2253
2254 desc32->physaddr = htole32(physaddr);
2255 }
2256 }
2257
2258 static void
2259 nfe_set_ready_rxdesc(struct nfe_softc *sc, struct nfe_rx_ring *ring, int idx)
2260 {
2261 if (sc->sc_flags & NFE_40BIT_ADDR) {
2262 struct nfe_desc64 *desc64 = &ring->desc64[idx];
2263
2264 desc64->length = htole16(ring->bufsz);
2265 desc64->flags = htole16(NFE_RX_READY);
2266 } else {
2267 struct nfe_desc32 *desc32 = &ring->desc32[idx];
2268
2269 desc32->length = htole16(ring->bufsz);
2270 desc32->flags = htole16(NFE_RX_READY);
2271 }
2272 }
2273
2274 static int
2275 nfe_sysctl_imtime(SYSCTL_HANDLER_ARGS)
2276 {
2277 struct nfe_softc *sc = arg1;
2278 struct ifnet *ifp = &sc->arpcom.ac_if;
2279 int error, v;
2280
2281 lwkt_serialize_enter(ifp->if_serializer);
2282
2283 v = sc->sc_imtime;
2284 error = sysctl_handle_int(oidp, &v, 0, req);
2285 if (error || req->newptr == NULL)
2286 goto back;
2287 if (v == 0) {
2288 error = EINVAL;
2289 goto back;
2290 }
2291
2292 if (sc->sc_imtime != v) {
2293 int old_imtime = sc->sc_imtime;
2294
2295 sc->sc_imtime = v;
2296 sc->sc_irq_enable = NFE_IRQ_ENABLE(sc);
2297
2298 if ((ifp->if_flags & (IFF_POLLING | IFF_RUNNING))
2299 == IFF_RUNNING) {
2300 if (old_imtime > 0 && sc->sc_imtime > 0) {
2301 NFE_WRITE(sc, NFE_IMTIMER,
2302 NFE_IMTIME(sc->sc_imtime));
2303 } else if ((old_imtime * sc->sc_imtime) < 0) {
2304 ifp->if_init(sc);
2305 }
2306 }
2307 }
2308 back:
2309 lwkt_serialize_exit(ifp->if_serializer);
2310 return error;
2311 }
DragonFly BSD