sys/dev/atm/en/midwayvar.h

   1 /*      $NetBSD: midwayvar.h,v 1.10 1997/03/20 21:34:46 chuck Exp $     */
   2 /* $DragonFly: src/sys/dev/atm/en/midwayvar.h,v 1.6 2006/09/09 18:54:36 dillon Exp $*/
   3
   4 /*
   5  *
   6  * Copyright (c) 1996 Charles D. Cranor and Washington University.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by Charles D. Cranor and
  20  *      Washington University.
  21  * 4. The name of the author may not be used to endorse or promote products
  22  *    derived from this software without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  25  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  26  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  27  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  33  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 /*
  37  * m i d w a y v a r . h
  38  *
  39  * we define the en_softc here so that bus specific modules can allocate
  40  * it as the first item in their softc.   note that BSD-required
  41  * "struct en_device" is in the mid_softc!
  42  *
  43  * author: Chuck Cranor <chuck@ccrc.wustl.edu>
  44  */
  45
  46 /*
  47  * params needed to determine softc size
  48  */
  49
  50 #ifndef EN_NTX
  51 #define EN_NTX          8       /* number of tx bufs to use */
  52 #endif
  53 #ifndef EN_TXSZ
  54 #define EN_TXSZ         32      /* trasmit buf size in KB */
  55 #endif
  56 #ifndef EN_RXSZ
  57 #define EN_RXSZ         32      /* recv buf size in KB */
  58 #endif
  59 #define EN_MAXNRX       ((2048-(EN_NTX*EN_TXSZ))/EN_RXSZ)
  60                                 /* largest possible NRX (depends on RAM size) */
  61
  62
  63 #define EN_INTR_TYPE void
  64 #define EN_INTR_RET(X) return
  65 #define EN_IOCTL_CMDT u_long
  66
  67 struct en_device {
  68   char dv_xname[IFNAMSIZ];
  69 };
  70
  71 #define DV_IFNET 1
  72
  73 struct cfdriver {
  74   int zero;
  75   char *name;
  76   int one;
  77   int cd_ndevs;
  78   void *cd_devs[NEN];
  79 };
  80
  81 /*
  82  * softc
  83  */
  84
  85 struct en_softc {
  86   /* bsd glue */
  87   struct en_device sc_dev;              /* system device */
  88   struct ifnet enif;            /* network ifnet handle */
  89
  90   /* bus glue */
  91   bus_space_tag_t en_memt;      /* for EN_READ/EN_WRITE */
  92   bus_space_handle_t en_base;   /* base of en card */
  93   bus_size_t en_obmemsz;        /* size of en card (bytes) */
  94   void (*en_busreset) (void *);
  95                                 /* bus specific reset function */
  96
  97   /* serv list */
  98   u_int32_t hwslistp;           /* hw pointer to service list (byte offset) */
  99   u_int16_t swslist[MID_SL_N];  /* software service list (see en_service()) */
 100   u_int16_t swsl_head,          /* ends of swslist (index into swslist) */
 101             swsl_tail;
 102   u_int32_t swsl_size;          /* # of items in swsl */
 103
 104
 105   /* xmit dma */
 106   u_int32_t dtq[MID_DTQ_N];     /* sw copy of dma q (see ENIDQ macros) */
 107   u_int32_t dtq_free;           /* # of dtq's free */
 108   u_int32_t dtq_us;             /* software copy of our pointer (byte offset) */
 109   u_int32_t dtq_chip;           /* chip's pointer (byte offset) */
 110   u_int32_t need_dtqs;          /* true if we ran out of DTQs */
 111
 112   /* recv dma */
 113   u_int32_t drq[MID_DRQ_N];     /* sw copy of dma q (see ENIDQ macros) */
 114   u_int32_t drq_free;           /* # of drq's free */
 115   u_int32_t drq_us;             /* software copy of our pointer (byte offset) */
 116   u_int32_t drq_chip;           /* chip's pointer (byte offset) */
 117   u_int32_t need_drqs;          /* true if we ran out of DRQs */
 118
 119   /* xmit buf ctrl. (per channel) */
 120   struct {
 121     u_int32_t mbsize;           /* # mbuf bytes we are using (max=TXHIWAT) */
 122     u_int32_t bfree;            /* # free bytes in buffer (not dma or xmit) */
 123     u_int32_t start, stop;      /* ends of buffer area (byte offset) */
 124     u_int32_t cur;              /* next free area (byte offset) */
 125     u_int32_t nref;             /* # of VCs using this channel */
 126     struct ifqueue indma;       /* mbufs being dma'd now */
 127     struct ifqueue q;           /* mbufs waiting for dma now */
 128   } txslot[MID_NTX_CH];
 129
 130   /* xmit vc ctrl. (per vc) */
 131   u_int8_t txspeed[MID_N_VC];   /* speed of tx on a VC */
 132   u_int8_t txvc2slot[MID_N_VC]; /* map VC to slot */
 133
 134   /* recv vc ctrl. (per vc).   maps VC number to recv slot */
 135   u_int16_t rxvc2slot[MID_N_VC];
 136   int en_nrx;                   /* # of active rx slots */
 137
 138   /* recv buf ctrl. (per recv slot) */
 139   struct {
 140     void *rxhand;               /* recv. handle if doing direct delivery */
 141     u_int32_t mode;             /* saved copy of mode info */
 142     u_int32_t start, stop;      /* ends of my buffer area */
 143     u_int32_t cur;              /* where I am at */
 144     u_int16_t atm_vci;          /* backpointer to VCI */
 145     u_int8_t atm_flags;         /* copy of atm_flags from atm_ph */
 146     u_int8_t oth_flags;         /* other flags */
 147     u_int32_t raw_threshold;    /* for raw mode */
 148     struct ifqueue indma;       /* mbufs being dma'd now */
 149     struct ifqueue q;           /* mbufs waiting for dma now */
 150   } rxslot[EN_MAXNRX];          /* recv info */
 151
 152   u_int8_t macaddr[6];          /* card unique mac address */
 153
 154   /* stats */
 155   u_int32_t vtrash;             /* sw copy of counter */
 156   u_int32_t otrash;             /* sw copy of counter */
 157   u_int32_t ttrash;             /* # of RBD's with T bit set */
 158   u_int32_t mfix;               /* # of times we had to call mfix */
 159   u_int32_t mfixfail;           /* # of times mfix failed */
 160   u_int32_t headbyte;           /* # of times we used BYTE DMA at front */
 161   u_int32_t tailbyte;           /* # of times we used BYTE DMA at end */
 162   u_int32_t tailflush;          /* # of times we had to FLUSH out DMA bytes */
 163   u_int32_t txmbovr;            /* # of times we dropped due to mbsize */
 164   u_int32_t dmaovr;             /* tx dma overflow count */
 165   u_int32_t txoutspace;         /* out of space in xmit buffer */
 166   u_int32_t txdtqout;           /* out of DTQs */
 167   u_int32_t launch;             /* total # of launches */
 168   u_int32_t lheader;            /* # of launches without OB header */
 169   u_int32_t ltail;              /* # of launches without OB tail */
 170   u_int32_t hwpull;             /* # of pulls off hardware service list */
 171   u_int32_t swadd;              /* # of pushes on sw service list */
 172   u_int32_t rxqnotus;           /* # of times we pull from rx q, but fail */
 173   u_int32_t rxqus;              /* # of good pulls from rx q */
 174   u_int32_t rxoutboth;          /* # of times out of mbufs and DRQs */
 175   u_int32_t rxdrqout;           /* # of times out of DRQs */
 176   u_int32_t rxmbufout;          /* # of time out of mbufs */
 177
 178   /* random stuff */
 179   u_int32_t ipl;                /* sbus interrupt lvl (1 on pci?) */
 180   u_int8_t bestburstcode;       /* code of best burst we can use */
 181   u_int8_t bestburstlen;        /* length of best burst (bytes) */
 182   u_int8_t bestburstshift;      /* (x >> shift) == (x / bestburstlen) */
 183   u_int8_t bestburstmask;       /* bits to check if not multiple of burst */
 184   u_int8_t alburst;             /* align dma bursts? */
 185   u_int8_t is_adaptec;          /* adaptec version of midway? */
 186 };
 187
 188 /*
 189  * exported functions
 190  */
 191
 192 void    en_attach (struct en_softc *);
 193 EN_INTR_TYPE    en_intr (void *);
 194 void    en_reset (struct en_softc *);