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Add lapic_init() to map local apic
[dragonfly.git] / sys / platform / pc64 / x86_64 / mp_machdep.c
blob10575dc7b29a17de3e119f4fd0ab1e23e92e5236
1 /*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
27 */
28
29 #include "opt_cpu.h"
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
39
40 #include <sys/mplock2.h>
41
42 #include <vm/vm.h>
43 #include <vm/vm_param.h>
44 #include <vm/pmap.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
47 #include <sys/lock.h>
48 #include <vm/vm_map.h>
49 #include <sys/user.h>
50 #ifdef GPROF
51 #include <sys/gmon.h>
52 #endif
53
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
68
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
70
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
74
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
78
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
83
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
87
88
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
91 char signature[4];
92 u_int32_t pap;
93 u_char length;
94 u_char spec_rev;
95 u_char checksum;
96 u_char mpfb1;
97 u_char mpfb2;
98 u_char mpfb3;
99 u_char mpfb4;
100 u_char mpfb5;
101 } *mpfps_t;
102
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
105 char signature[4];
106 u_short base_table_length;
107 u_char spec_rev;
108 u_char checksum;
109 u_char oem_id[8];
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
113 u_short entry_count;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
117 u_char reserved;
118 } *mpcth_t;
119
120
121 typedef struct PROCENTRY {
122 u_char type;
123 u_char apic_id;
124 u_char apic_version;
125 u_char cpu_flags;
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
128 u_int32_t reserved1;
129 u_int32_t reserved2;
130 } *proc_entry_ptr;
131
132 typedef struct BUSENTRY {
133 u_char type;
134 u_char bus_id;
135 char bus_type[6];
136 } *bus_entry_ptr;
137
138 typedef struct IOAPICENTRY {
139 u_char type;
140 u_char apic_id;
141 u_char apic_version;
142 u_char apic_flags;
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
145
146 typedef struct INTENTRY {
147 u_char type;
148 u_char int_type;
149 u_short int_flags;
150 u_char src_bus_id;
151 u_char src_bus_irq;
152 u_char dst_apic_id;
153 u_char dst_apic_int;
154 } *int_entry_ptr;
155
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
158 u_char type;
159 u_char length;
160 char name[16];
161 } basetable_entry;
162
163 struct mptable_pos {
164 mpfps_t mp_fps;
165 mpcth_t mp_cth;
166 vm_size_t mp_cth_mapsz;
167 };
168
169 typedef int (*mptable_iter_func)(void *, const void *, int);
170
171 /*
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 *
176 */
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
180
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
188
189 #define CHECK_PRINT(S); \
190 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
191 (S), \
192 CHECK_READ(0x34), \
193 CHECK_READ(0x35), \
194 CHECK_READ(0x36), \
195 CHECK_READ(0x37), \
196 CHECK_READ(0x38), \
197 CHECK_READ(0x39));
198
199 #else /* CHECK_POINTS */
200
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
203
204 #endif /* CHECK_POINTS */
205
206 /*
207 * Values to send to the POST hardware.
208 */
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
212
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
216
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
220
221 #define MP_ANNOUNCE_POST 0x19
222
223 static int need_hyperthreading_fixup;
224 static u_int logical_cpus;
225 u_int logical_cpus_mask;
226
227 static int madt_probe_test;
228 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
229
230 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
231 int current_postcode;
232
233 /** XXX FIXME: what system files declare these??? */
234 extern struct region_descriptor r_gdt, r_idt;
235
236 int mp_naps; /* # of Applications processors */
237 #ifdef APIC_IO
238 static int mp_nbusses; /* # of busses */
239 int mp_napics; /* # of IO APICs */
240 #endif
241 static vm_offset_t cpu_apic_address;
242 #ifdef APIC_IO
243 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
244 u_int32_t *io_apic_versions;
245 #endif
246 extern int nkpt;
247
248 u_int32_t cpu_apic_versions[MAXCPU];
249 int64_t tsc0_offset;
250 extern int64_t tsc_offsets[];
251
252 extern u_long ebda_addr;
253
254 #ifdef APIC_IO
255 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
256 #endif
257
258 /*
259 * APIC ID logical/physical mapping structures.
260 * We oversize these to simplify boot-time config.
261 */
262 int cpu_num_to_apic_id[NAPICID];
263 #ifdef APIC_IO
264 int io_num_to_apic_id[NAPICID];
265 #endif
266 int apic_id_to_logical[NAPICID];
267
268 /* AP uses this during bootstrap. Do not staticize. */
269 char *bootSTK;
270 static int bootAP;
271
272 /*
273 * SMP page table page. Setup by locore to point to a page table
274 * page from which we allocate per-cpu privatespace areas io_apics,
275 * and so forth.
276 */
277
278 #define IO_MAPPING_START_INDEX \
279 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
280
281 extern pt_entry_t *SMPpt;
282
283 struct pcb stoppcbs[MAXCPU];
284
285 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
286
287 static basetable_entry basetable_entry_types[] =
288 {
289 {0, 20, "Processor"},
290 {1, 8, "Bus"},
291 {2, 8, "I/O APIC"},
292 {3, 8, "I/O INT"},
293 {4, 8, "Local INT"}
294 };
295
296 /*
297 * Local data and functions.
298 */
299
300 static u_int boot_address;
301 static u_int base_memory;
302 static int mp_finish;
303
304 static void mp_enable(u_int boot_addr);
305
306 static int mptable_iterate_entries(const mpcth_t,
307 mptable_iter_func, void *);
308 static int mptable_probe(void);
309 static int mptable_check(vm_paddr_t);
310 static long mptable_search_sig(u_int32_t target, int count);
311 static void mptable_hyperthread_fixup(u_int id_mask);
312 static void mptable_pass1(struct mptable_pos *);
313 static int mptable_pass2(struct mptable_pos *);
314 static void mptable_default(int type);
315 static void mptable_fix(void);
316 static int mptable_map(struct mptable_pos *, vm_paddr_t);
317 static void mptable_unmap(struct mptable_pos *);
318 static void mptable_lapic_enumerate(struct mptable_pos *);
319
320 #ifdef APIC_IO
321 static void setup_apic_irq_mapping(void);
322 static int apic_int_is_bus_type(int intr, int bus_type);
323 #endif
324 static int start_all_aps(u_int boot_addr);
325 #if 0
326 static void install_ap_tramp(u_int boot_addr);
327 #endif
328 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
329 static void lapic_init(vm_offset_t);
330 static int smitest(void);
331
332 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
333 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
334 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
335 static u_int bootMP_size;
336
337 /*
338 * Calculate usable address in base memory for AP trampoline code.
339 */
340 u_int
341 mp_bootaddress(u_int basemem)
342 {
343 POSTCODE(MP_BOOTADDRESS_POST);
344
345 base_memory = basemem;
346
347 bootMP_size = mptramp_end - mptramp_start;
348 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
349 if (((basemem * 1024) - boot_address) < bootMP_size)
350 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
351 /* 3 levels of page table pages */
352 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
353
354 return mptramp_pagetables;
355 }
356
357
358 /*
359 * Look for an Intel MP spec table (ie, SMP capable hardware).
360 */
361 static int
362 mptable_probe(void)
363 {
364 long x;
365 u_int32_t target;
366
367 /*
368 * Make sure our SMPpt[] page table is big enough to hold all the
369 * mappings we need.
370 */
371 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
372
373 POSTCODE(MP_PROBE_POST);
374
375 /* see if EBDA exists */
376 if (ebda_addr != 0) {
377 /* search first 1K of EBDA */
378 target = (u_int32_t)ebda_addr;
379 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
380 return x;
381 } else {
382 /* last 1K of base memory, effective 'top of base' passed in */
383 target = (u_int32_t)(base_memory - 0x400);
384 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
385 return x;
386 }
387
388 /* search the BIOS */
389 target = (u_int32_t)BIOS_BASE;
390 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
391 return x;
392
393 /* nothing found */
394 return 0;
395 }
396
397 struct mptable_check_cbarg {
398 int cpu_count;
399 int found_bsp;
400 };
401
402 static int
403 mptable_check_callback(void *xarg, const void *pos, int type)
404 {
405 const struct PROCENTRY *ent;
406 struct mptable_check_cbarg *arg = xarg;
407
408 if (type != 0)
409 return 0;
410 ent = pos;
411
412 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
413 return 0;
414 arg->cpu_count++;
415
416 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
417 if (arg->found_bsp) {
418 kprintf("more than one BSP in base MP table\n");
419 return EINVAL;
420 }
421 arg->found_bsp = 1;
422 }
423 return 0;
424 }
425
426 static int
427 mptable_check(vm_paddr_t mpfps_paddr)
428 {
429 struct mptable_pos mpt;
430 struct mptable_check_cbarg arg;
431 mpcth_t cth;
432 int error;
433
434 if (mpfps_paddr == 0)
435 return EOPNOTSUPP;
436
437 error = mptable_map(&mpt, mpfps_paddr);
438 if (error)
439 return error;
440
441 if (mpt.mp_fps->mpfb1 != 0)
442 goto done;
443
444 error = EINVAL;
445
446 cth = mpt.mp_cth;
447 if (cth == NULL)
448 goto done;
449 if (cth->apic_address == 0)
450 goto done;
451
452 bzero(&arg, sizeof(arg));
453 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
454 if (!error) {
455 if (arg.cpu_count == 0) {
456 kprintf("MP table contains no processor entries\n");
457 error = EINVAL;
458 } else if (!arg.found_bsp) {
459 kprintf("MP table does not contains BSP entry\n");
460 error = EINVAL;
461 }
462 }
463 done:
464 mptable_unmap(&mpt);
465 return error;
466 }
467
468 static int
469 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
470 {
471 int count, total_size;
472 const void *position;
473
474 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
475 total_size = cth->base_table_length - sizeof(struct MPCTH);
476 position = (const uint8_t *)cth + sizeof(struct MPCTH);
477 count = cth->entry_count;
478
479 while (count--) {
480 int type, error;
481
482 KKASSERT(total_size >= 0);
483 if (total_size == 0) {
484 kprintf("invalid base MP table, "
485 "entry count and length mismatch\n");
486 return EINVAL;
487 }
488
489 type = *(const uint8_t *)position;
490 switch (type) {
491 case 0: /* processor_entry */
492 case 1: /* bus_entry */
493 case 2: /* io_apic_entry */
494 case 3: /* int_entry */
495 case 4: /* int_entry */
496 break;
497 default:
498 kprintf("unknown base MP table entry type %d\n", type);
499 return EINVAL;
500 }
501
502 if (total_size < basetable_entry_types[type].length) {
503 kprintf("invalid base MP table length, "
504 "does not contain all entries\n");
505 return EINVAL;
506 }
507 total_size -= basetable_entry_types[type].length;
508
509 error = func(arg, position, type);
510 if (error)
511 return error;
512
513 position = (const uint8_t *)position +
514 basetable_entry_types[type].length;
515 }
516 return 0;
517 }
518
519
520 /*
521 * Startup the SMP processors.
522 */
523 void
524 mp_start(void)
525 {
526 POSTCODE(MP_START_POST);
527 mp_enable(boot_address);
528 }
529
530
531 /*
532 * Print various information about the SMP system hardware and setup.
533 */
534 void
535 mp_announce(void)
536 {
537 int x;
538
539 POSTCODE(MP_ANNOUNCE_POST);
540
541 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
542 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
543 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
544 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
545 for (x = 1; x <= mp_naps; ++x) {
546 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
547 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
548 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
549 }
550
551 #if defined(APIC_IO)
552 for (x = 0; x < mp_napics; ++x) {
553 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
554 kprintf(", version: 0x%08x", io_apic_versions[x]);
555 kprintf(", at 0x%08lx\n", io_apic_address[x]);
556 }
557 #else
558 kprintf(" Warning: APIC I/O disabled\n");
559 #endif /* APIC_IO */
560 }
561
562 /*
563 * AP cpu's call this to sync up protected mode.
564 *
565 * WARNING! %gs is not set up on entry. This routine sets up %gs.
566 */
567 void
568 init_secondary(void)
569 {
570 int gsel_tss;
571 int x, myid = bootAP;
572 u_int64_t msr, cr0;
573 struct mdglobaldata *md;
574 struct privatespace *ps;
575
576 ps = &CPU_prvspace[myid];
577
578 gdt_segs[GPROC0_SEL].ssd_base =
579 (long) &ps->mdglobaldata.gd_common_tss;
580 ps->mdglobaldata.mi.gd_prvspace = ps;
581
582 /* We fill the 32-bit segment descriptors */
583 for (x = 0; x < NGDT; x++) {
584 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
585 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
586 }
587 /* And now a 64-bit one */
588 ssdtosyssd(&gdt_segs[GPROC0_SEL],
589 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
590
591 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
592 r_gdt.rd_base = (long) &gdt[myid * NGDT];
593 lgdt(&r_gdt); /* does magic intra-segment return */
594
595 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
596 wrmsr(MSR_FSBASE, 0); /* User value */
597 wrmsr(MSR_GSBASE, (u_int64_t)ps);
598 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
599
600 lidt(&r_idt);
601
602 #if 0
603 lldt(_default_ldt);
604 mdcpu->gd_currentldt = _default_ldt;
605 #endif
606
607 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
608 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
609
610 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
611
612 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
613 #if 0 /* JG XXX */
614 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
615 #endif
616 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
617 md->gd_common_tssd = *md->gd_tss_gdt;
618 #if 0 /* JG XXX */
619 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
620 #endif
621 ltr(gsel_tss);
622
623 /*
624 * Set to a known state:
625 * Set by mpboot.s: CR0_PG, CR0_PE
626 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
627 */
628 cr0 = rcr0();
629 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
630 load_cr0(cr0);
631
632 /* Set up the fast syscall stuff */
633 msr = rdmsr(MSR_EFER) | EFER_SCE;
634 wrmsr(MSR_EFER, msr);
635 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
636 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
637 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
638 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
639 wrmsr(MSR_STAR, msr);
640 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
641
642 pmap_set_opt(); /* PSE/4MB pages, etc */
643 #if JGXXX
644 /* Initialize the PAT MSR. */
645 pmap_init_pat();
646 #endif
647
648 /* set up CPU registers and state */
649 cpu_setregs();
650
651 /* set up SSE/NX registers */
652 initializecpu();
653
654 /* set up FPU state on the AP */
655 npxinit(__INITIAL_NPXCW__);
656
657 /* disable the APIC, just to be SURE */
658 lapic->svr &= ~APIC_SVR_ENABLE;
659
660 /* data returned to BSP */
661 cpu_apic_versions[0] = lapic->version;
662 }
663
664 /*******************************************************************
665 * local functions and data
666 */
667
668 /*
669 * start the SMP system
670 */
671 static void
672 mp_enable(u_int boot_addr)
673 {
674 int x;
675 #if defined(APIC_IO)
676 int apic;
677 u_int ux;
678 #endif /* APIC_IO */
679 vm_paddr_t mpfps_paddr;
680
681 POSTCODE(MP_ENABLE_POST);
682
683 if (madt_probe_test) {
684 mpfps_paddr = 0;
685 } else {
686 mpfps_paddr = mptable_probe();
687 if (mptable_check(mpfps_paddr))
688 mpfps_paddr = 0;
689 }
690
691 if (mpfps_paddr) {
692 struct mptable_pos mpt;
693
694 mptable_map(&mpt, mpfps_paddr);
695
696 mptable_lapic_enumerate(&mpt);
697 KKASSERT(lapic);
698
699 /*
700 * We can safely map physical memory into SMPpt after
701 * mptable_pass1() completes.
702 */
703 mptable_pass1(&mpt);
704
705 /*
706 * Examine the MP table for needed info
707 */
708 x = mptable_pass2(&mpt);
709
710 mptable_unmap(&mpt);
711
712 /*
713 * Can't process default configs till the
714 * CPU APIC is pmapped
715 */
716 if (x)
717 mptable_default(x);
718
719 /* post scan cleanup */
720 mptable_fix();
721
722 } else {
723 vm_paddr_t madt_paddr;
724 vm_offset_t lapic_addr;
725 int bsp_apic_id;
726
727 madt_paddr = madt_probe();
728 if (madt_paddr == 0)
729 panic("mp_enable: madt_probe failed\n");
730
731 lapic_addr = madt_pass1(madt_paddr);
732 if (lapic_addr == 0)
733 panic("mp_enable: no local apic (madt)!\n");
734
735 lapic_init(lapic_addr);
736
737 bsp_apic_id = (lapic->id & 0xff000000) >> 24;
738 if (madt_pass2(madt_paddr, bsp_apic_id))
739 panic("mp_enable: madt_pass2 failed\n");
740 }
741
742 #if defined(APIC_IO)
743
744 setup_apic_irq_mapping();
745
746 /* fill the LOGICAL io_apic_versions table */
747 for (apic = 0; apic < mp_napics; ++apic) {
748 ux = io_apic_read(apic, IOAPIC_VER);
749 io_apic_versions[apic] = ux;
750 io_apic_set_id(apic, IO_TO_ID(apic));
751 }
752
753 /* program each IO APIC in the system */
754 for (apic = 0; apic < mp_napics; ++apic)
755 if (io_apic_setup(apic) < 0)
756 panic("IO APIC setup failure");
757
758 #endif /* APIC_IO */
759
760 /*
761 * These are required for SMP operation
762 */
763
764 /* install a 'Spurious INTerrupt' vector */
765 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
766 SDT_SYSIGT, SEL_KPL, 0);
767
768 /* install an inter-CPU IPI for TLB invalidation */
769 setidt(XINVLTLB_OFFSET, Xinvltlb,
770 SDT_SYSIGT, SEL_KPL, 0);
771
772 /* install an inter-CPU IPI for IPIQ messaging */
773 setidt(XIPIQ_OFFSET, Xipiq,
774 SDT_SYSIGT, SEL_KPL, 0);
775
776 /* install a timer vector */
777 setidt(XTIMER_OFFSET, Xtimer,
778 SDT_SYSIGT, SEL_KPL, 0);
779
780 /* install an inter-CPU IPI for CPU stop/restart */
781 setidt(XCPUSTOP_OFFSET, Xcpustop,
782 SDT_SYSIGT, SEL_KPL, 0);
783
784 /* start each Application Processor */
785 start_all_aps(boot_addr);
786 }
787
788
789 /*
790 * look for the MP spec signature
791 */
792
793 /* string defined by the Intel MP Spec as identifying the MP table */
794 #define MP_SIG 0x5f504d5f /* _MP_ */
795 #define NEXT(X) ((X) += 4)
796 static long
797 mptable_search_sig(u_int32_t target, int count)
798 {
799 vm_size_t map_size;
800 u_int32_t *addr;
801 int x, ret;
802
803 KKASSERT(target != 0);
804
805 map_size = count * sizeof(u_int32_t);
806 addr = pmap_mapdev((vm_paddr_t)target, map_size);
807
808 ret = 0;
809 for (x = 0; x < count; NEXT(x)) {
810 if (addr[x] == MP_SIG) {
811 /* make array index a byte index */
812 ret = target + (x * sizeof(u_int32_t));
813 break;
814 }
815 }
816
817 pmap_unmapdev((vm_offset_t)addr, map_size);
818 return ret;
819 }
820
821
822 typedef struct BUSDATA {
823 u_char bus_id;
824 enum busTypes bus_type;
825 } bus_datum;
826
827 typedef struct INTDATA {
828 u_char int_type;
829 u_short int_flags;
830 u_char src_bus_id;
831 u_char src_bus_irq;
832 u_char dst_apic_id;
833 u_char dst_apic_int;
834 u_char int_vector;
835 } io_int, local_int;
836
837 typedef struct BUSTYPENAME {
838 u_char type;
839 char name[7];
840 } bus_type_name;
841
842 #ifdef APIC_IO
843
844 static bus_type_name bus_type_table[] =
845 {
846 {CBUS, "CBUS"},
847 {CBUSII, "CBUSII"},
848 {EISA, "EISA"},
849 {MCA, "MCA"},
850 {UNKNOWN_BUSTYPE, "---"},
851 {ISA, "ISA"},
852 {MCA, "MCA"},
853 {UNKNOWN_BUSTYPE, "---"},
854 {UNKNOWN_BUSTYPE, "---"},
855 {UNKNOWN_BUSTYPE, "---"},
856 {UNKNOWN_BUSTYPE, "---"},
857 {UNKNOWN_BUSTYPE, "---"},
858 {PCI, "PCI"},
859 {UNKNOWN_BUSTYPE, "---"},
860 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"},
862 {UNKNOWN_BUSTYPE, "---"},
863 {XPRESS, "XPRESS"},
864 {UNKNOWN_BUSTYPE, "---"}
865 };
866
867 /* from MP spec v1.4, table 5-1 */
868 static int default_data[7][5] =
869 {
870 /* nbus, id0, type0, id1, type1 */
871 {1, 0, ISA, 255, 255},
872 {1, 0, EISA, 255, 255},
873 {1, 0, EISA, 255, 255},
874 {1, 0, MCA, 255, 255},
875 {2, 0, ISA, 1, PCI},
876 {2, 0, EISA, 1, PCI},
877 {2, 0, MCA, 1, PCI}
878 };
879
880 /* the bus data */
881 static bus_datum *bus_data;
882
883 /* the IO INT data, one entry per possible APIC INTerrupt */
884 static io_int *io_apic_ints;
885 static int nintrs;
886
887 #endif
888
889 static int processor_entry (const struct PROCENTRY *entry, int cpu);
890 #ifdef APIC_IO
891 static int bus_entry (bus_entry_ptr entry, int bus);
892 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
893 static int int_entry (int_entry_ptr entry, int intr);
894 static int lookup_bus_type (char *name);
895 #endif
896
897
898 /*
899 * 1st pass on motherboard's Intel MP specification table.
900 *
901 * determines:
902 * io_apic_address[N]
903 * mp_nbusses
904 * mp_napics
905 * nintrs
906 */
907 static void
908 mptable_pass1(struct mptable_pos *mpt)
909 {
910 #ifdef APIC_IO
911 int x;
912 #endif
913 mpfps_t fps;
914 mpcth_t cth;
915 int totalSize;
916 void* position;
917 int count;
918 int type;
919
920 POSTCODE(MPTABLE_PASS1_POST);
921
922 fps = mpt->mp_fps;
923 KKASSERT(fps != NULL);
924
925 #ifdef APIC_IO
926 /* clear various tables */
927 for (x = 0; x < NAPICID; ++x) {
928 io_apic_address[x] = ~0; /* IO APIC address table */
929 }
930 #endif
931
932 #ifdef APIC_IO
933 mp_nbusses = 0;
934 mp_napics = 0;
935 nintrs = 0;
936 #endif
937
938 /* check for use of 'default' configuration */
939 if (fps->mpfb1 != 0) {
940 #ifdef APIC_IO
941 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
942 mp_nbusses = default_data[fps->mpfb1 - 1][0];
943 mp_napics = 1;
944 nintrs = 16;
945 #endif /* APIC_IO */
946 }
947 else {
948 cth = mpt->mp_cth;
949 KKASSERT(cth != NULL);
950
951 /* walk the table, recording info of interest */
952 totalSize = cth->base_table_length - sizeof(struct MPCTH);
953 position = (u_char *) cth + sizeof(struct MPCTH);
954 count = cth->entry_count;
955
956 while (count--) {
957 switch (type = *(u_char *) position) {
958 case 0: /* processor_entry */
959 break;
960 case 1: /* bus_entry */
961 #ifdef APIC_IO
962 ++mp_nbusses;
963 #endif
964 break;
965 case 2: /* io_apic_entry */
966 #ifdef APIC_IO
967 if (((io_apic_entry_ptr)position)->apic_flags
968 & IOAPICENTRY_FLAG_EN)
969 io_apic_address[mp_napics++] =
970 (vm_offset_t)((io_apic_entry_ptr)
971 position)->apic_address;
972 #endif
973 break;
974 case 3: /* int_entry */
975 #ifdef APIC_IO
976 ++nintrs;
977 #endif
978 break;
979 case 4: /* int_entry */
980 break;
981 default:
982 panic("mpfps Base Table HOSED!");
983 /* NOTREACHED */
984 }
985
986 totalSize -= basetable_entry_types[type].length;
987 position = (uint8_t *)position +
988 basetable_entry_types[type].length;
989 }
990 }
991 }
992
993
994 /*
995 * 2nd pass on motherboard's Intel MP specification table.
996 *
997 * sets:
998 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
999 * IO_TO_ID(N), logical IO to APIC ID table
1000 * bus_data[N]
1001 * io_apic_ints[N]
1002 */
1003 static int
1004 mptable_pass2(struct mptable_pos *mpt)
1005 {
1006 int x;
1007 mpfps_t fps;
1008 mpcth_t cth;
1009 int totalSize;
1010 void* position;
1011 int count;
1012 int type;
1013 int apic, bus, intr;
1014 #ifdef APIC_IO
1015 int i;
1016 #endif
1017
1018 POSTCODE(MPTABLE_PASS2_POST);
1019
1020 fps = mpt->mp_fps;
1021 KKASSERT(fps != NULL);
1022
1023 #ifdef APIC_IO
1024 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1025 M_DEVBUF, M_WAITOK);
1026 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1027 M_DEVBUF, M_WAITOK | M_ZERO);
1028 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1029 M_DEVBUF, M_WAITOK);
1030 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1031 M_DEVBUF, M_WAITOK);
1032 #endif
1033
1034 #ifdef APIC_IO
1035 for (i = 0; i < mp_napics; i++) {
1036 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1037 }
1038 #endif
1039
1040 /* clear various tables */
1041 for (x = 0; x < NAPICID; ++x) {
1042 #ifdef APIC_IO
1043 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1044 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1045 #endif
1046 }
1047
1048 #ifdef APIC_IO
1049 /* clear bus data table */
1050 for (x = 0; x < mp_nbusses; ++x)
1051 bus_data[x].bus_id = 0xff;
1052
1053 /* clear IO APIC INT table */
1054 for (x = 0; x < (nintrs + 1); ++x) {
1055 io_apic_ints[x].int_type = 0xff;
1056 io_apic_ints[x].int_vector = 0xff;
1057 }
1058 #endif
1059
1060 /* record whether PIC or virtual-wire mode */
1061 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1062
1063 /* check for use of 'default' configuration */
1064 if (fps->mpfb1 != 0)
1065 return fps->mpfb1; /* return default configuration type */
1066
1067 cth = mpt->mp_cth;
1068 KKASSERT(cth != NULL);
1069
1070 /* walk the table, recording info of interest */
1071 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1072 position = (u_char *) cth + sizeof(struct MPCTH);
1073 count = cth->entry_count;
1074 apic = bus = intr = 0;
1075
1076 while (count--) {
1077 switch (type = *(u_char *) position) {
1078 case 0:
1079 break;
1080 case 1:
1081 #ifdef APIC_IO
1082 if (bus_entry(position, bus))
1083 ++bus;
1084 #endif
1085 break;
1086 case 2:
1087 #ifdef APIC_IO
1088 if (io_apic_entry(position, apic))
1089 ++apic;
1090 #endif
1091 break;
1092 case 3:
1093 #ifdef APIC_IO
1094 if (int_entry(position, intr))
1095 ++intr;
1096 #endif
1097 break;
1098 case 4:
1099 /* int_entry(position); */
1100 break;
1101 default:
1102 panic("mpfps Base Table HOSED!");
1103 /* NOTREACHED */
1104 }
1105
1106 totalSize -= basetable_entry_types[type].length;
1107 position = (uint8_t *)position + basetable_entry_types[type].length;
1108 }
1109
1110 /* report fact that its NOT a default configuration */
1111 return 0;
1112 }
1113
1114
1115 /*
1116 * Check if we should perform a hyperthreading "fix-up" to
1117 * enumerate any logical CPU's that aren't already listed
1118 * in the table.
1119 *
1120 * XXX: We assume that all of the physical CPUs in the
1121 * system have the same number of logical CPUs.
1122 *
1123 * XXX: We assume that APIC ID's are allocated such that
1124 * the APIC ID's for a physical processor are aligned
1125 * with the number of logical CPU's in the processor.
1126 */
1127 static void
1128 mptable_hyperthread_fixup(u_int id_mask)
1129 {
1130 int i, id, lcpus_max;
1131
1132 if ((cpu_feature & CPUID_HTT) == 0)
1133 return;
1134
1135 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1136 if (lcpus_max <= 1)
1137 return;
1138
1139 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1140 /*
1141 * INSTRUCTION SET REFERENCE, A-M (#253666)
1142 * Page 3-181, Table 3-20
1143 * "The nearest power-of-2 integer that is not smaller
1144 * than EBX[23:16] is the number of unique initial APIC
1145 * IDs reserved for addressing different logical
1146 * processors in a physical package."
1147 */
1148 for (i = 0; ; ++i) {
1149 if ((1 << i) >= lcpus_max) {
1150 lcpus_max = 1 << i;
1151 break;
1152 }
1153 }
1154 }
1155
1156 if (mp_naps == lcpus_max) {
1157 /* We have nothing to fix */
1158 return;
1159 } else if (mp_naps == 1) {
1160 /* XXX this may be incorrect */
1161 logical_cpus = lcpus_max;
1162 } else {
1163 int cur, prev, dist;
1164
1165 /*
1166 * Calculate the distances between two nearest
1167 * APIC IDs. If all such distances are same,
1168 * then it is the number of missing cpus that
1169 * we are going to fill later.
1170 */
1171 dist = cur = prev = -1;
1172 for (id = 0; id < MAXCPU; ++id) {
1173 if ((id_mask & 1 << id) == 0)
1174 continue;
1175
1176 cur = id;
1177 if (prev >= 0) {
1178 int new_dist = cur - prev;
1179
1180 if (dist < 0)
1181 dist = new_dist;
1182
1183 /*
1184 * Make sure that all distances
1185 * between two nearest APIC IDs
1186 * are same.
1187 */
1188 if (dist != new_dist)
1189 return;
1190 }
1191 prev = cur;
1192 }
1193 if (dist == 1)
1194 return;
1195
1196 /* Must be power of 2 */
1197 if (dist & (dist - 1))
1198 return;
1199
1200 /* Can't exceed CPU package capacity */
1201 if (dist > lcpus_max)
1202 logical_cpus = lcpus_max;
1203 else
1204 logical_cpus = dist;
1205 }
1206
1207 /*
1208 * For each APIC ID of a CPU that is set in the mask,
1209 * scan the other candidate APIC ID's for this
1210 * physical processor. If any of those ID's are
1211 * already in the table, then kill the fixup.
1212 */
1213 for (id = 0; id < MAXCPU; id++) {
1214 if ((id_mask & 1 << id) == 0)
1215 continue;
1216 /* First, make sure we are on a logical_cpus boundary. */
1217 if (id % logical_cpus != 0)
1218 return;
1219 for (i = id + 1; i < id + logical_cpus; i++)
1220 if ((id_mask & 1 << i) != 0)
1221 return;
1222 }
1223
1224 /*
1225 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1226 * mp_naps right now.
1227 */
1228 need_hyperthreading_fixup = 1;
1229 mp_naps *= logical_cpus;
1230 }
1231
1232 static int
1233 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1234 {
1235 mpfps_t fps = NULL;
1236 mpcth_t cth = NULL;
1237 vm_size_t cth_mapsz = 0;
1238
1239 bzero(mpt, sizeof(*mpt));
1240
1241 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1242 if (fps->pap != 0) {
1243 /*
1244 * Map configuration table header to get
1245 * the base table size
1246 */
1247 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1248 cth_mapsz = cth->base_table_length;
1249 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1250
1251 if (cth_mapsz < sizeof(*cth)) {
1252 kprintf("invalid base MP table length %d\n",
1253 (int)cth_mapsz);
1254 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1255 return EINVAL;
1256 }
1257
1258 /*
1259 * Map the base table
1260 */
1261 cth = pmap_mapdev(fps->pap, cth_mapsz);
1262 }
1263
1264 mpt->mp_fps = fps;
1265 mpt->mp_cth = cth;
1266 mpt->mp_cth_mapsz = cth_mapsz;
1267
1268 return 0;
1269 }
1270
1271 static void
1272 mptable_unmap(struct mptable_pos *mpt)
1273 {
1274 if (mpt->mp_cth != NULL) {
1275 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1276 mpt->mp_cth = NULL;
1277 mpt->mp_cth_mapsz = 0;
1278 }
1279 if (mpt->mp_fps != NULL) {
1280 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1281 mpt->mp_fps = NULL;
1282 }
1283 }
1284
1285 #ifdef APIC_IO
1286
1287 void
1288 assign_apic_irq(int apic, int intpin, int irq)
1289 {
1290 int x;
1291
1292 if (int_to_apicintpin[irq].ioapic != -1)
1293 panic("assign_apic_irq: inconsistent table");
1294
1295 int_to_apicintpin[irq].ioapic = apic;
1296 int_to_apicintpin[irq].int_pin = intpin;
1297 int_to_apicintpin[irq].apic_address = ioapic[apic];
1298 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1299
1300 for (x = 0; x < nintrs; x++) {
1301 if ((io_apic_ints[x].int_type == 0 ||
1302 io_apic_ints[x].int_type == 3) &&
1303 io_apic_ints[x].int_vector == 0xff &&
1304 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1305 io_apic_ints[x].dst_apic_int == intpin)
1306 io_apic_ints[x].int_vector = irq;
1307 }
1308 }
1309
1310 void
1311 revoke_apic_irq(int irq)
1312 {
1313 int x;
1314 int oldapic;
1315 int oldintpin;
1316
1317 if (int_to_apicintpin[irq].ioapic == -1)
1318 panic("revoke_apic_irq: inconsistent table");
1319
1320 oldapic = int_to_apicintpin[irq].ioapic;
1321 oldintpin = int_to_apicintpin[irq].int_pin;
1322
1323 int_to_apicintpin[irq].ioapic = -1;
1324 int_to_apicintpin[irq].int_pin = 0;
1325 int_to_apicintpin[irq].apic_address = NULL;
1326 int_to_apicintpin[irq].redirindex = 0;
1327
1328 for (x = 0; x < nintrs; x++) {
1329 if ((io_apic_ints[x].int_type == 0 ||
1330 io_apic_ints[x].int_type == 3) &&
1331 io_apic_ints[x].int_vector != 0xff &&
1332 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1333 io_apic_ints[x].dst_apic_int == oldintpin)
1334 io_apic_ints[x].int_vector = 0xff;
1335 }
1336 }
1337
1338 /*
1339 * Allocate an IRQ
1340 */
1341 static void
1342 allocate_apic_irq(int intr)
1343 {
1344 int apic;
1345 int intpin;
1346 int irq;
1347
1348 if (io_apic_ints[intr].int_vector != 0xff)
1349 return; /* Interrupt handler already assigned */
1350
1351 if (io_apic_ints[intr].int_type != 0 &&
1352 (io_apic_ints[intr].int_type != 3 ||
1353 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1354 io_apic_ints[intr].dst_apic_int == 0)))
1355 return; /* Not INT or ExtInt on != (0, 0) */
1356
1357 irq = 0;
1358 while (irq < APIC_INTMAPSIZE &&
1359 int_to_apicintpin[irq].ioapic != -1)
1360 irq++;
1361
1362 if (irq >= APIC_INTMAPSIZE)
1363 return; /* No free interrupt handlers */
1364
1365 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1366 intpin = io_apic_ints[intr].dst_apic_int;
1367
1368 assign_apic_irq(apic, intpin, irq);
1369 }
1370
1371
1372 static void
1373 swap_apic_id(int apic, int oldid, int newid)
1374 {
1375 int x;
1376 int oapic;
1377
1378
1379 if (oldid == newid)
1380 return; /* Nothing to do */
1381
1382 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1383 apic, oldid, newid);
1384
1385 /* Swap physical APIC IDs in interrupt entries */
1386 for (x = 0; x < nintrs; x++) {
1387 if (io_apic_ints[x].dst_apic_id == oldid)
1388 io_apic_ints[x].dst_apic_id = newid;
1389 else if (io_apic_ints[x].dst_apic_id == newid)
1390 io_apic_ints[x].dst_apic_id = oldid;
1391 }
1392
1393 /* Swap physical APIC IDs in IO_TO_ID mappings */
1394 for (oapic = 0; oapic < mp_napics; oapic++)
1395 if (IO_TO_ID(oapic) == newid)
1396 break;
1397
1398 if (oapic < mp_napics) {
1399 kprintf("Changing APIC ID for IO APIC #%d from "
1400 "%d to %d in MP table\n",
1401 oapic, newid, oldid);
1402 IO_TO_ID(oapic) = oldid;
1403 }
1404 IO_TO_ID(apic) = newid;
1405 }
1406
1407
1408 static void
1409 fix_id_to_io_mapping(void)
1410 {
1411 int x;
1412
1413 for (x = 0; x < NAPICID; x++)
1414 ID_TO_IO(x) = -1;
1415
1416 for (x = 0; x <= mp_naps; x++)
1417 if (CPU_TO_ID(x) < NAPICID)
1418 ID_TO_IO(CPU_TO_ID(x)) = x;
1419
1420 for (x = 0; x < mp_napics; x++)
1421 if (IO_TO_ID(x) < NAPICID)
1422 ID_TO_IO(IO_TO_ID(x)) = x;
1423 }
1424
1425
1426 static int
1427 first_free_apic_id(void)
1428 {
1429 int freeid, x;
1430
1431 for (freeid = 0; freeid < NAPICID; freeid++) {
1432 for (x = 0; x <= mp_naps; x++)
1433 if (CPU_TO_ID(x) == freeid)
1434 break;
1435 if (x <= mp_naps)
1436 continue;
1437 for (x = 0; x < mp_napics; x++)
1438 if (IO_TO_ID(x) == freeid)
1439 break;
1440 if (x < mp_napics)
1441 continue;
1442 return freeid;
1443 }
1444 return freeid;
1445 }
1446
1447
1448 static int
1449 io_apic_id_acceptable(int apic, int id)
1450 {
1451 int cpu; /* Logical CPU number */
1452 int oapic; /* Logical IO APIC number for other IO APIC */
1453
1454 if (id >= NAPICID)
1455 return 0; /* Out of range */
1456
1457 for (cpu = 0; cpu <= mp_naps; cpu++)
1458 if (CPU_TO_ID(cpu) == id)
1459 return 0; /* Conflict with CPU */
1460
1461 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1462 if (IO_TO_ID(oapic) == id)
1463 return 0; /* Conflict with other APIC */
1464
1465 return 1; /* ID is acceptable for IO APIC */
1466 }
1467
1468 static
1469 io_int *
1470 io_apic_find_int_entry(int apic, int pin)
1471 {
1472 int x;
1473
1474 /* search each of the possible INTerrupt sources */
1475 for (x = 0; x < nintrs; ++x) {
1476 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1477 (pin == io_apic_ints[x].dst_apic_int))
1478 return (&io_apic_ints[x]);
1479 }
1480 return NULL;
1481 }
1482
1483 #endif
1484
1485 /*
1486 * parse an Intel MP specification table
1487 */
1488 static void
1489 mptable_fix(void)
1490 {
1491 #ifdef APIC_IO
1492 int x;
1493 int id;
1494 int apic; /* IO APIC unit number */
1495 int freeid; /* Free physical APIC ID */
1496 int physid; /* Current physical IO APIC ID */
1497 io_int *io14;
1498 int bus_0 = 0; /* Stop GCC warning */
1499 int bus_pci = 0; /* Stop GCC warning */
1500 int num_pci_bus;
1501
1502 /*
1503 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1504 * did it wrong. The MP spec says that when more than 1 PCI bus
1505 * exists the BIOS must begin with bus entries for the PCI bus and use
1506 * actual PCI bus numbering. This implies that when only 1 PCI bus
1507 * exists the BIOS can choose to ignore this ordering, and indeed many
1508 * MP motherboards do ignore it. This causes a problem when the PCI
1509 * sub-system makes requests of the MP sub-system based on PCI bus
1510 * numbers. So here we look for the situation and renumber the
1511 * busses and associated INTs in an effort to "make it right".
1512 */
1513
1514 /* find bus 0, PCI bus, count the number of PCI busses */
1515 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1516 if (bus_data[x].bus_id == 0) {
1517 bus_0 = x;
1518 }
1519 if (bus_data[x].bus_type == PCI) {
1520 ++num_pci_bus;
1521 bus_pci = x;
1522 }
1523 }
1524 /*
1525 * bus_0 == slot of bus with ID of 0
1526 * bus_pci == slot of last PCI bus encountered
1527 */
1528
1529 /* check the 1 PCI bus case for sanity */
1530 /* if it is number 0 all is well */
1531 if (num_pci_bus == 1 &&
1532 bus_data[bus_pci].bus_id != 0) {
1533
1534 /* mis-numbered, swap with whichever bus uses slot 0 */
1535
1536 /* swap the bus entry types */
1537 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1538 bus_data[bus_0].bus_type = PCI;
1539
1540 /* swap each relavant INTerrupt entry */
1541 id = bus_data[bus_pci].bus_id;
1542 for (x = 0; x < nintrs; ++x) {
1543 if (io_apic_ints[x].src_bus_id == id) {
1544 io_apic_ints[x].src_bus_id = 0;
1545 }
1546 else if (io_apic_ints[x].src_bus_id == 0) {
1547 io_apic_ints[x].src_bus_id = id;
1548 }
1549 }
1550 }
1551
1552 /* Assign IO APIC IDs.
1553 *
1554 * First try the existing ID. If a conflict is detected, try
1555 * the ID in the MP table. If a conflict is still detected, find
1556 * a free id.
1557 *
1558 * We cannot use the ID_TO_IO table before all conflicts has been
1559 * resolved and the table has been corrected.
1560 */
1561 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1562
1563 /* First try to use the value set by the BIOS */
1564 physid = io_apic_get_id(apic);
1565 if (io_apic_id_acceptable(apic, physid)) {
1566 if (IO_TO_ID(apic) != physid)
1567 swap_apic_id(apic, IO_TO_ID(apic), physid);
1568 continue;
1569 }
1570
1571 /* Then check if the value in the MP table is acceptable */
1572 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1573 continue;
1574
1575 /* Last resort, find a free APIC ID and use it */
1576 freeid = first_free_apic_id();
1577 if (freeid >= NAPICID)
1578 panic("No free physical APIC IDs found");
1579
1580 if (io_apic_id_acceptable(apic, freeid)) {
1581 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1582 continue;
1583 }
1584 panic("Free physical APIC ID not usable");
1585 }
1586 fix_id_to_io_mapping();
1587
1588 /* detect and fix broken Compaq MP table */
1589 if (apic_int_type(0, 0) == -1) {
1590 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1591 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1592 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1593 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1594 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1595 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1596 nintrs++;
1597 } else if (apic_int_type(0, 0) == 0) {
1598 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1599 for (x = 0; x < nintrs; ++x)
1600 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1601 (0 == io_apic_ints[x].dst_apic_int)) {
1602 io_apic_ints[x].int_type = 3;
1603 io_apic_ints[x].int_vector = 0xff;
1604 break;
1605 }
1606 }
1607
1608 /*
1609 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1610 * controllers universally come in pairs. If IRQ 14 is specified
1611 * as an ISA interrupt, then IRQ 15 had better be too.
1612 *
1613 * [ Shuttle XPC / AMD Athlon X2 ]
1614 * The MPTable is missing an entry for IRQ 15. Note that the
1615 * ACPI table has an entry for both 14 and 15.
1616 */
1617 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1618 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1619 io14 = io_apic_find_int_entry(0, 14);
1620 io_apic_ints[nintrs] = *io14;
1621 io_apic_ints[nintrs].src_bus_irq = 15;
1622 io_apic_ints[nintrs].dst_apic_int = 15;
1623 nintrs++;
1624 }
1625 #endif
1626 }
1627
1628 #ifdef APIC_IO
1629
1630 /* Assign low level interrupt handlers */
1631 static void
1632 setup_apic_irq_mapping(void)
1633 {
1634 int x;
1635 int int_vector;
1636
1637 /* Clear array */
1638 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1639 int_to_apicintpin[x].ioapic = -1;
1640 int_to_apicintpin[x].int_pin = 0;
1641 int_to_apicintpin[x].apic_address = NULL;
1642 int_to_apicintpin[x].redirindex = 0;
1643 }
1644
1645 /* First assign ISA/EISA interrupts */
1646 for (x = 0; x < nintrs; x++) {
1647 int_vector = io_apic_ints[x].src_bus_irq;
1648 if (int_vector < APIC_INTMAPSIZE &&
1649 io_apic_ints[x].int_vector == 0xff &&
1650 int_to_apicintpin[int_vector].ioapic == -1 &&
1651 (apic_int_is_bus_type(x, ISA) ||
1652 apic_int_is_bus_type(x, EISA)) &&
1653 io_apic_ints[x].int_type == 0) {
1654 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1655 io_apic_ints[x].dst_apic_int,
1656 int_vector);
1657 }
1658 }
1659
1660 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1661 for (x = 0; x < nintrs; x++) {
1662 if (io_apic_ints[x].dst_apic_int == 0 &&
1663 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1664 io_apic_ints[x].int_vector == 0xff &&
1665 int_to_apicintpin[0].ioapic == -1 &&
1666 io_apic_ints[x].int_type == 3) {
1667 assign_apic_irq(0, 0, 0);
1668 break;
1669 }
1670 }
1671
1672 /* Assign PCI interrupts */
1673 for (x = 0; x < nintrs; ++x) {
1674 if (io_apic_ints[x].int_type == 0 &&
1675 io_apic_ints[x].int_vector == 0xff &&
1676 apic_int_is_bus_type(x, PCI))
1677 allocate_apic_irq(x);
1678 }
1679 }
1680
1681 #endif
1682
1683 void
1684 mp_set_cpuids(int cpu_id, int apic_id)
1685 {
1686 CPU_TO_ID(cpu_id) = apic_id;
1687 ID_TO_CPU(apic_id) = cpu_id;
1688 }
1689
1690 static int
1691 processor_entry(const struct PROCENTRY *entry, int cpu)
1692 {
1693 KKASSERT(cpu > 0);
1694
1695 /* check for usability */
1696 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1697 return 0;
1698
1699 if(entry->apic_id >= NAPICID)
1700 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1701 /* check for BSP flag */
1702 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1703 mp_set_cpuids(0, entry->apic_id);
1704 return 0; /* its already been counted */
1705 }
1706
1707 /* add another AP to list, if less than max number of CPUs */
1708 else if (cpu < MAXCPU) {
1709 mp_set_cpuids(cpu, entry->apic_id);
1710 return 1;
1711 }
1712
1713 return 0;
1714 }
1715
1716 #ifdef APIC_IO
1717
1718 static int
1719 bus_entry(bus_entry_ptr entry, int bus)
1720 {
1721 int x;
1722 char c, name[8];
1723
1724 /* encode the name into an index */
1725 for (x = 0; x < 6; ++x) {
1726 if ((c = entry->bus_type[x]) == ' ')
1727 break;
1728 name[x] = c;
1729 }
1730 name[x] = '\0';
1731
1732 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1733 panic("unknown bus type: '%s'", name);
1734
1735 bus_data[bus].bus_id = entry->bus_id;
1736 bus_data[bus].bus_type = x;
1737
1738 return 1;
1739 }
1740
1741 static int
1742 io_apic_entry(io_apic_entry_ptr entry, int apic)
1743 {
1744 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1745 return 0;
1746
1747 IO_TO_ID(apic) = entry->apic_id;
1748 if (entry->apic_id < NAPICID)
1749 ID_TO_IO(entry->apic_id) = apic;
1750
1751 return 1;
1752 }
1753
1754 static int
1755 lookup_bus_type(char *name)
1756 {
1757 int x;
1758
1759 for (x = 0; x < MAX_BUSTYPE; ++x)
1760 if (strcmp(bus_type_table[x].name, name) == 0)
1761 return bus_type_table[x].type;
1762
1763 return UNKNOWN_BUSTYPE;
1764 }
1765
1766 static int
1767 int_entry(int_entry_ptr entry, int intr)
1768 {
1769 int apic;
1770
1771 io_apic_ints[intr].int_type = entry->int_type;
1772 io_apic_ints[intr].int_flags = entry->int_flags;
1773 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1774 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1775 if (entry->dst_apic_id == 255) {
1776 /* This signal goes to all IO APICS. Select an IO APIC
1777 with sufficient number of interrupt pins */
1778 for (apic = 0; apic < mp_napics; apic++)
1779 if (((io_apic_read(apic, IOAPIC_VER) &
1780 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1781 entry->dst_apic_int)
1782 break;
1783 if (apic < mp_napics)
1784 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1785 else
1786 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1787 } else
1788 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1789 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1790
1791 return 1;
1792 }
1793
1794 static int
1795 apic_int_is_bus_type(int intr, int bus_type)
1796 {
1797 int bus;
1798
1799 for (bus = 0; bus < mp_nbusses; ++bus)
1800 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1801 && ((int) bus_data[bus].bus_type == bus_type))
1802 return 1;
1803
1804 return 0;
1805 }
1806
1807 /*
1808 * Given a traditional ISA INT mask, return an APIC mask.
1809 */
1810 u_int
1811 isa_apic_mask(u_int isa_mask)
1812 {
1813 int isa_irq;
1814 int apic_pin;
1815
1816 #if defined(SKIP_IRQ15_REDIRECT)
1817 if (isa_mask == (1 << 15)) {
1818 kprintf("skipping ISA IRQ15 redirect\n");
1819 return isa_mask;
1820 }
1821 #endif /* SKIP_IRQ15_REDIRECT */
1822
1823 isa_irq = ffs(isa_mask); /* find its bit position */
1824 if (isa_irq == 0) /* doesn't exist */
1825 return 0;
1826 --isa_irq; /* make it zero based */
1827
1828 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1829 if (apic_pin == -1)
1830 return 0;
1831
1832 return (1 << apic_pin); /* convert pin# to a mask */
1833 }
1834
1835 /*
1836 * Determine which APIC pin an ISA/EISA INT is attached to.
1837 */
1838 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1839 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1840 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1841 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1842
1843 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1844 int
1845 isa_apic_irq(int isa_irq)
1846 {
1847 int intr;
1848
1849 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1850 if (INTTYPE(intr) == 0) { /* standard INT */
1851 if (SRCBUSIRQ(intr) == isa_irq) {
1852 if (apic_int_is_bus_type(intr, ISA) ||
1853 apic_int_is_bus_type(intr, EISA)) {
1854 if (INTIRQ(intr) == 0xff)
1855 return -1; /* unassigned */
1856 return INTIRQ(intr); /* found */
1857 }
1858 }
1859 }
1860 }
1861 return -1; /* NOT found */
1862 }
1863
1864
1865 /*
1866 * Determine which APIC pin a PCI INT is attached to.
1867 */
1868 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1869 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1870 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1871 int
1872 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1873 {
1874 int intr;
1875
1876 --pciInt; /* zero based */
1877
1878 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1879 if ((INTTYPE(intr) == 0) /* standard INT */
1880 && (SRCBUSID(intr) == pciBus)
1881 && (SRCBUSDEVICE(intr) == pciDevice)
1882 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1883 if (apic_int_is_bus_type(intr, PCI)) {
1884 if (INTIRQ(intr) == 0xff) {
1885 kprintf("IOAPIC: pci_apic_irq() "
1886 "failed\n");
1887 return -1; /* unassigned */
1888 }
1889 return INTIRQ(intr); /* exact match */
1890 }
1891 }
1892 }
1893
1894 return -1; /* NOT found */
1895 }
1896
1897 int
1898 next_apic_irq(int irq)
1899 {
1900 int intr, ointr;
1901 int bus, bustype;
1902
1903 bus = 0;
1904 bustype = 0;
1905 for (intr = 0; intr < nintrs; intr++) {
1906 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1907 continue;
1908 bus = SRCBUSID(intr);
1909 bustype = apic_bus_type(bus);
1910 if (bustype != ISA &&
1911 bustype != EISA &&
1912 bustype != PCI)
1913 continue;
1914 break;
1915 }
1916 if (intr >= nintrs) {
1917 return -1;
1918 }
1919 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1920 if (INTTYPE(ointr) != 0)
1921 continue;
1922 if (bus != SRCBUSID(ointr))
1923 continue;
1924 if (bustype == PCI) {
1925 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1926 continue;
1927 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1928 continue;
1929 }
1930 if (bustype == ISA || bustype == EISA) {
1931 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1932 continue;
1933 }
1934 if (INTPIN(intr) == INTPIN(ointr))
1935 continue;
1936 break;
1937 }
1938 if (ointr >= nintrs) {
1939 return -1;
1940 }
1941 return INTIRQ(ointr);
1942 }
1943 #undef SRCBUSLINE
1944 #undef SRCBUSDEVICE
1945 #undef SRCBUSID
1946 #undef SRCBUSIRQ
1947
1948 #undef INTPIN
1949 #undef INTIRQ
1950 #undef INTAPIC
1951 #undef INTTYPE
1952
1953 #endif
1954
1955 /*
1956 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1957 *
1958 * XXX FIXME:
1959 * Exactly what this means is unclear at this point. It is a solution
1960 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1961 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1962 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1963 * option.
1964 */
1965 int
1966 undirect_isa_irq(int rirq)
1967 {
1968 #if defined(READY)
1969 if (bootverbose)
1970 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1971 /** FIXME: tickle the MB redirector chip */
1972 return /* XXX */;
1973 #else
1974 if (bootverbose)
1975 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1976 return 0;
1977 #endif /* READY */
1978 }
1979
1980
1981 /*
1982 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1983 */
1984 int
1985 undirect_pci_irq(int rirq)
1986 {
1987 #if defined(READY)
1988 if (bootverbose)
1989 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1990
1991 /** FIXME: tickle the MB redirector chip */
1992 return /* XXX */;
1993 #else
1994 if (bootverbose)
1995 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1996 rirq);
1997 return 0;
1998 #endif /* READY */
1999 }
2000
2001
2002 #ifdef APIC_IO
2003
2004 /*
2005 * given a bus ID, return:
2006 * the bus type if found
2007 * -1 if NOT found
2008 */
2009 int
2010 apic_bus_type(int id)
2011 {
2012 int x;
2013
2014 for (x = 0; x < mp_nbusses; ++x)
2015 if (bus_data[x].bus_id == id)
2016 return bus_data[x].bus_type;
2017
2018 return -1;
2019 }
2020
2021 /*
2022 * given a LOGICAL APIC# and pin#, return:
2023 * the associated src bus ID if found
2024 * -1 if NOT found
2025 */
2026 int
2027 apic_src_bus_id(int apic, int pin)
2028 {
2029 int x;
2030
2031 /* search each of the possible INTerrupt sources */
2032 for (x = 0; x < nintrs; ++x)
2033 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2034 (pin == io_apic_ints[x].dst_apic_int))
2035 return (io_apic_ints[x].src_bus_id);
2036
2037 return -1; /* NOT found */
2038 }
2039
2040 /*
2041 * given a LOGICAL APIC# and pin#, return:
2042 * the associated src bus IRQ if found
2043 * -1 if NOT found
2044 */
2045 int
2046 apic_src_bus_irq(int apic, int pin)
2047 {
2048 int x;
2049
2050 for (x = 0; x < nintrs; x++)
2051 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2052 (pin == io_apic_ints[x].dst_apic_int))
2053 return (io_apic_ints[x].src_bus_irq);
2054
2055 return -1; /* NOT found */
2056 }
2057
2058
2059 /*
2060 * given a LOGICAL APIC# and pin#, return:
2061 * the associated INTerrupt type if found
2062 * -1 if NOT found
2063 */
2064 int
2065 apic_int_type(int apic, int pin)
2066 {
2067 int x;
2068
2069 /* search each of the possible INTerrupt sources */
2070 for (x = 0; x < nintrs; ++x) {
2071 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2072 (pin == io_apic_ints[x].dst_apic_int))
2073 return (io_apic_ints[x].int_type);
2074 }
2075 return -1; /* NOT found */
2076 }
2077
2078 /*
2079 * Return the IRQ associated with an APIC pin
2080 */
2081 int
2082 apic_irq(int apic, int pin)
2083 {
2084 int x;
2085 int res;
2086
2087 for (x = 0; x < nintrs; ++x) {
2088 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2089 (pin == io_apic_ints[x].dst_apic_int)) {
2090 res = io_apic_ints[x].int_vector;
2091 if (res == 0xff)
2092 return -1;
2093 if (apic != int_to_apicintpin[res].ioapic)
2094 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2095 if (pin != int_to_apicintpin[res].int_pin)
2096 panic("apic_irq inconsistent table (2)");
2097 return res;
2098 }
2099 }
2100 return -1;
2101 }
2102
2103
2104 /*
2105 * given a LOGICAL APIC# and pin#, return:
2106 * the associated trigger mode if found
2107 * -1 if NOT found
2108 */
2109 int
2110 apic_trigger(int apic, int pin)
2111 {
2112 int x;
2113
2114 /* search each of the possible INTerrupt sources */
2115 for (x = 0; x < nintrs; ++x)
2116 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2117 (pin == io_apic_ints[x].dst_apic_int))
2118 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2119
2120 return -1; /* NOT found */
2121 }
2122
2123
2124 /*
2125 * given a LOGICAL APIC# and pin#, return:
2126 * the associated 'active' level if found
2127 * -1 if NOT found
2128 */
2129 int
2130 apic_polarity(int apic, int pin)
2131 {
2132 int x;
2133
2134 /* search each of the possible INTerrupt sources */
2135 for (x = 0; x < nintrs; ++x)
2136 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2137 (pin == io_apic_ints[x].dst_apic_int))
2138 return (io_apic_ints[x].int_flags & 0x03);
2139
2140 return -1; /* NOT found */
2141 }
2142
2143 #endif
2144
2145 /*
2146 * set data according to MP defaults
2147 * FIXME: probably not complete yet...
2148 */
2149 static void
2150 mptable_default(int type)
2151 {
2152 #if defined(APIC_IO)
2153 int io_apic_id;
2154 int pin;
2155 #endif /* APIC_IO */
2156
2157 #if 0
2158 kprintf(" MP default config type: %d\n", type);
2159 switch (type) {
2160 case 1:
2161 kprintf(" bus: ISA, APIC: 82489DX\n");
2162 break;
2163 case 2:
2164 kprintf(" bus: EISA, APIC: 82489DX\n");
2165 break;
2166 case 3:
2167 kprintf(" bus: EISA, APIC: 82489DX\n");
2168 break;
2169 case 4:
2170 kprintf(" bus: MCA, APIC: 82489DX\n");
2171 break;
2172 case 5:
2173 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2174 break;
2175 case 6:
2176 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2177 break;
2178 case 7:
2179 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2180 break;
2181 default:
2182 kprintf(" future type\n");
2183 break;
2184 /* NOTREACHED */
2185 }
2186 #endif /* 0 */
2187
2188 #if defined(APIC_IO)
2189 /* one and only IO APIC */
2190 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2191
2192 /*
2193 * sanity check, refer to MP spec section 3.6.6, last paragraph
2194 * necessary as some hardware isn't properly setting up the IO APIC
2195 */
2196 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2197 if (io_apic_id != 2) {
2198 #else
2199 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2200 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2201 io_apic_set_id(0, 2);
2202 io_apic_id = 2;
2203 }
2204 IO_TO_ID(0) = io_apic_id;
2205 ID_TO_IO(io_apic_id) = 0;
2206 #endif /* APIC_IO */
2207
2208 /* fill out bus entries */
2209 switch (type) {
2210 case 1:
2211 case 2:
2212 case 3:
2213 case 4:
2214 case 5:
2215 case 6:
2216 case 7:
2217 #ifdef APIC_IO
2218 bus_data[0].bus_id = default_data[type - 1][1];
2219 bus_data[0].bus_type = default_data[type - 1][2];
2220 bus_data[1].bus_id = default_data[type - 1][3];
2221 bus_data[1].bus_type = default_data[type - 1][4];
2222 #endif
2223 break;
2224
2225 /* case 4: case 7: MCA NOT supported */
2226 default: /* illegal/reserved */
2227 panic("BAD default MP config: %d", type);
2228 /* NOTREACHED */
2229 }
2230
2231 #if defined(APIC_IO)
2232 /* general cases from MP v1.4, table 5-2 */
2233 for (pin = 0; pin < 16; ++pin) {
2234 io_apic_ints[pin].int_type = 0;
2235 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2236 io_apic_ints[pin].src_bus_id = 0;
2237 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2238 io_apic_ints[pin].dst_apic_id = io_apic_id;
2239 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2240 }
2241
2242 /* special cases from MP v1.4, table 5-2 */
2243 if (type == 2) {
2244 io_apic_ints[2].int_type = 0xff; /* N/C */
2245 io_apic_ints[13].int_type = 0xff; /* N/C */
2246 #if !defined(APIC_MIXED_MODE)
2247 /** FIXME: ??? */
2248 panic("sorry, can't support type 2 default yet");
2249 #endif /* APIC_MIXED_MODE */
2250 }
2251 else
2252 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2253
2254 if (type == 7)
2255 io_apic_ints[0].int_type = 0xff; /* N/C */
2256 else
2257 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2258 #endif /* APIC_IO */
2259 }
2260
2261 /*
2262 * Map a physical memory address representing I/O into KVA. The I/O
2263 * block is assumed not to cross a page boundary.
2264 */
2265 void *
2266 permanent_io_mapping(vm_paddr_t pa)
2267 {
2268 KKASSERT(pa < 0x100000000LL);
2269
2270 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2271 }
2272
2273 /*
2274 * start each AP in our list
2275 */
2276 static int
2277 start_all_aps(u_int boot_addr)
2278 {
2279 vm_offset_t va = boot_address + KERNBASE;
2280 u_int64_t *pt4, *pt3, *pt2;
2281 int x, i, pg;
2282 int shift;
2283 int smicount;
2284 int smibest;
2285 int smilast;
2286 u_char mpbiosreason;
2287 u_long mpbioswarmvec;
2288 struct mdglobaldata *gd;
2289 struct privatespace *ps;
2290
2291 POSTCODE(START_ALL_APS_POST);
2292
2293 /* Initialize BSP's local APIC */
2294 apic_initialize(TRUE);
2295
2296 /* install the AP 1st level boot code */
2297 pmap_kenter(va, boot_address);
2298 cpu_invlpg((void *)va); /* JG XXX */
2299 bcopy(mptramp_start, (void *)va, bootMP_size);
2300
2301 /* Locate the page tables, they'll be below the trampoline */
2302 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2303 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2304 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2305
2306 /* Create the initial 1GB replicated page tables */
2307 for (i = 0; i < 512; i++) {
2308 /* Each slot of the level 4 pages points to the same level 3 page */
2309 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2310 pt4[i] |= PG_V | PG_RW | PG_U;
2311
2312 /* Each slot of the level 3 pages points to the same level 2 page */
2313 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2314 pt3[i] |= PG_V | PG_RW | PG_U;
2315
2316 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2317 pt2[i] = i * (2 * 1024 * 1024);
2318 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2319 }
2320
2321 /* save the current value of the warm-start vector */
2322 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2323 outb(CMOS_REG, BIOS_RESET);
2324 mpbiosreason = inb(CMOS_DATA);
2325
2326 /* setup a vector to our boot code */
2327 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2328 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2329 outb(CMOS_REG, BIOS_RESET);
2330 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2331
2332 /*
2333 * If we have a TSC we can figure out the SMI interrupt rate.
2334 * The SMI does not necessarily use a constant rate. Spend
2335 * up to 250ms trying to figure it out.
2336 */
2337 smibest = 0;
2338 if (cpu_feature & CPUID_TSC) {
2339 set_apic_timer(275000);
2340 smilast = read_apic_timer();
2341 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2342 smicount = smitest();
2343 if (smibest == 0 || smilast - smicount < smibest)
2344 smibest = smilast - smicount;
2345 smilast = smicount;
2346 }
2347 if (smibest > 250000)
2348 smibest = 0;
2349 if (smibest) {
2350 smibest = smibest * (int64_t)1000000 /
2351 get_apic_timer_frequency();
2352 }
2353 }
2354 if (smibest)
2355 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2356 1000000 / smibest, smibest);
2357
2358 /* start each AP */
2359 for (x = 1; x <= mp_naps; ++x) {
2360
2361 /* This is a bit verbose, it will go away soon. */
2362
2363 /* first page of AP's private space */
2364 pg = x * x86_64_btop(sizeof(struct privatespace));
2365
2366 /* allocate new private data page(s) */
2367 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2368 MDGLOBALDATA_BASEALLOC_SIZE);
2369
2370 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2371 bzero(gd, sizeof(*gd));
2372 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2373
2374 /* prime data page for it to use */
2375 mi_gdinit(&gd->mi, x);
2376 cpu_gdinit(gd, x);
2377 gd->gd_CMAP1 = &SMPpt[pg + 0];
2378 gd->gd_CMAP2 = &SMPpt[pg + 1];
2379 gd->gd_CMAP3 = &SMPpt[pg + 2];
2380 gd->gd_PMAP1 = &SMPpt[pg + 3];
2381 gd->gd_CADDR1 = ps->CPAGE1;
2382 gd->gd_CADDR2 = ps->CPAGE2;
2383 gd->gd_CADDR3 = ps->CPAGE3;
2384 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2385 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2386 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2387
2388 /* setup a vector to our boot code */
2389 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2390 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2391 outb(CMOS_REG, BIOS_RESET);
2392 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2393
2394 /*
2395 * Setup the AP boot stack
2396 */
2397 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2398 bootAP = x;
2399
2400 /* attempt to start the Application Processor */
2401 CHECK_INIT(99); /* setup checkpoints */
2402 if (!start_ap(gd, boot_addr, smibest)) {
2403 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2404 CHECK_PRINT("trace"); /* show checkpoints */
2405 /* better panic as the AP may be running loose */
2406 kprintf("panic y/n? [y] ");
2407 if (cngetc() != 'n')
2408 panic("bye-bye");
2409 }
2410 CHECK_PRINT("trace"); /* show checkpoints */
2411
2412 /* record its version info */
2413 cpu_apic_versions[x] = cpu_apic_versions[0];
2414 }
2415
2416 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2417 ncpus = x;
2418
2419 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2420 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2421 ;
2422 --shift;
2423 ncpus2_shift = shift;
2424 ncpus2 = 1 << shift;
2425 ncpus2_mask = ncpus2 - 1;
2426
2427 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2428 if ((1 << shift) < ncpus)
2429 ++shift;
2430 ncpus_fit = 1 << shift;
2431 ncpus_fit_mask = ncpus_fit - 1;
2432
2433 /* build our map of 'other' CPUs */
2434 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2435 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2436 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2437
2438 /* fill in our (BSP) APIC version */
2439 cpu_apic_versions[0] = lapic->version;
2440
2441 /* restore the warmstart vector */
2442 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2443 outb(CMOS_REG, BIOS_RESET);
2444 outb(CMOS_DATA, mpbiosreason);
2445
2446 /*
2447 * NOTE! The idlestack for the BSP was setup by locore. Finish
2448 * up, clean out the P==V mapping we did earlier.
2449 */
2450 pmap_set_opt();
2451
2452 /* number of APs actually started */
2453 return ncpus - 1;
2454 }
2455
2456
2457 /*
2458 * load the 1st level AP boot code into base memory.
2459 */
2460
2461 /* targets for relocation */
2462 extern void bigJump(void);
2463 extern void bootCodeSeg(void);
2464 extern void bootDataSeg(void);
2465 extern void MPentry(void);
2466 extern u_int MP_GDT;
2467 extern u_int mp_gdtbase;
2468
2469 #if 0
2470
2471 static void
2472 install_ap_tramp(u_int boot_addr)
2473 {
2474 int x;
2475 int size = *(int *) ((u_long) & bootMP_size);
2476 u_char *src = (u_char *) ((u_long) bootMP);
2477 u_char *dst = (u_char *) boot_addr + KERNBASE;
2478 u_int boot_base = (u_int) bootMP;
2479 u_int8_t *dst8;
2480 u_int16_t *dst16;
2481 u_int32_t *dst32;
2482
2483 POSTCODE(INSTALL_AP_TRAMP_POST);
2484
2485 for (x = 0; x < size; ++x)
2486 *dst++ = *src++;
2487
2488 /*
2489 * modify addresses in code we just moved to basemem. unfortunately we
2490 * need fairly detailed info about mpboot.s for this to work. changes
2491 * to mpboot.s might require changes here.
2492 */
2493
2494 /* boot code is located in KERNEL space */
2495 dst = (u_char *) boot_addr + KERNBASE;
2496
2497 /* modify the lgdt arg */
2498 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2499 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2500
2501 /* modify the ljmp target for MPentry() */
2502 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2503 *dst32 = ((u_int) MPentry - KERNBASE);
2504
2505 /* modify the target for boot code segment */
2506 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2507 dst8 = (u_int8_t *) (dst16 + 1);
2508 *dst16 = (u_int) boot_addr & 0xffff;
2509 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2510
2511 /* modify the target for boot data segment */
2512 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2513 dst8 = (u_int8_t *) (dst16 + 1);
2514 *dst16 = (u_int) boot_addr & 0xffff;
2515 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2516 }
2517
2518 #endif
2519
2520 /*
2521 * This function starts the AP (application processor) identified
2522 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2523 * to accomplish this. This is necessary because of the nuances
2524 * of the different hardware we might encounter. It ain't pretty,
2525 * but it seems to work.
2526 *
2527 * NOTE: eventually an AP gets to ap_init(), which is called just
2528 * before the AP goes into the LWKT scheduler's idle loop.
2529 */
2530 static int
2531 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2532 {
2533 int physical_cpu;
2534 int vector;
2535 u_long icr_lo, icr_hi;
2536
2537 POSTCODE(START_AP_POST);
2538
2539 /* get the PHYSICAL APIC ID# */
2540 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2541
2542 /* calculate the vector */
2543 vector = (boot_addr >> 12) & 0xff;
2544
2545 /* We don't want anything interfering */
2546 cpu_disable_intr();
2547
2548 /* Make sure the target cpu sees everything */
2549 wbinvd();
2550
2551 /*
2552 * Try to detect when a SMI has occurred, wait up to 200ms.
2553 *
2554 * If a SMI occurs during an AP reset but before we issue
2555 * the STARTUP command, the AP may brick. To work around
2556 * this problem we hold off doing the AP startup until
2557 * after we have detected the SMI. Hopefully another SMI
2558 * will not occur before we finish the AP startup.
2559 *
2560 * Retries don't seem to help. SMIs have a window of opportunity
2561 * and if USB->legacy keyboard emulation is enabled in the BIOS
2562 * the interrupt rate can be quite high.
2563 *
2564 * NOTE: Don't worry about the L1 cache load, it might bloat
2565 * ldelta a little but ndelta will be so huge when the SMI
2566 * occurs the detection logic will still work fine.
2567 */
2568 if (smibest) {
2569 set_apic_timer(200000);
2570 smitest();
2571 }
2572
2573 /*
2574 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2575 * and running the target CPU. OR this INIT IPI might be latched (P5
2576 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2577 * ignored.
2578 *
2579 * see apic/apicreg.h for icr bit definitions.
2580 *
2581 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2582 */
2583
2584 /*
2585 * Setup the address for the target AP. We can setup
2586 * icr_hi once and then just trigger operations with
2587 * icr_lo.
2588 */
2589 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2590 icr_hi |= (physical_cpu << 24);
2591 icr_lo = lapic->icr_lo & 0xfff00000;
2592 lapic->icr_hi = icr_hi;
2593
2594 /*
2595 * Do an INIT IPI: assert RESET
2596 *
2597 * Use edge triggered mode to assert INIT
2598 */
2599 lapic->icr_lo = icr_lo | 0x00004500;
2600 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2601 /* spin */ ;
2602
2603 /*
2604 * The spec calls for a 10ms delay but we may have to use a
2605 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2606 * interrupt. We have other loops here too and dividing by 2
2607 * doesn't seem to be enough even after subtracting 350us,
2608 * so we divide by 4.
2609 *
2610 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2611 * interrupt was detected we use the full 10ms.
2612 */
2613 if (smibest == 0)
2614 u_sleep(10000);
2615 else if (smibest < 150 * 4 + 350)
2616 u_sleep(150);
2617 else if ((smibest - 350) / 4 < 10000)
2618 u_sleep((smibest - 350) / 4);
2619 else
2620 u_sleep(10000);
2621
2622 /*
2623 * Do an INIT IPI: deassert RESET
2624 *
2625 * Use level triggered mode to deassert. It is unclear
2626 * why we need to do this.
2627 */
2628 lapic->icr_lo = icr_lo | 0x00008500;
2629 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2630 /* spin */ ;
2631 u_sleep(150); /* wait 150us */
2632
2633 /*
2634 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2635 * latched, (P5 bug) this 1st STARTUP would then terminate
2636 * immediately, and the previously started INIT IPI would continue. OR
2637 * the previous INIT IPI has already run. and this STARTUP IPI will
2638 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2639 * will run.
2640 */
2641 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2642 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2643 /* spin */ ;
2644 u_sleep(200); /* wait ~200uS */
2645
2646 /*
2647 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2648 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2649 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2650 * recognized after hardware RESET or INIT IPI.
2651 */
2652 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2653 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2654 /* spin */ ;
2655
2656 /* Resume normal operation */
2657 cpu_enable_intr();
2658
2659 /* wait for it to start, see ap_init() */
2660 set_apic_timer(5000000);/* == 5 seconds */
2661 while (read_apic_timer()) {
2662 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2663 return 1; /* return SUCCESS */
2664 }
2665
2666 return 0; /* return FAILURE */
2667 }
2668
2669 static
2670 int
2671 smitest(void)
2672 {
2673 int64_t ltsc;
2674 int64_t ntsc;
2675 int64_t ldelta;
2676 int64_t ndelta;
2677 int count;
2678
2679 ldelta = 0;
2680 ndelta = 0;
2681 while (read_apic_timer()) {
2682 ltsc = rdtsc();
2683 for (count = 0; count < 100; ++count)
2684 ntsc = rdtsc(); /* force loop to occur */
2685 if (ldelta) {
2686 ndelta = ntsc - ltsc;
2687 if (ldelta > ndelta)
2688 ldelta = ndelta;
2689 if (ndelta > ldelta * 2)
2690 break;
2691 } else {
2692 ldelta = ntsc - ltsc;
2693 }
2694 }
2695 return(read_apic_timer());
2696 }
2697
2698 /*
2699 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2700 *
2701 * If for some reason we were unable to start all cpus we cannot safely
2702 * use broadcast IPIs.
2703 */
2704 void
2705 smp_invltlb(void)
2706 {
2707 #ifdef SMP
2708 if (smp_startup_mask == smp_active_mask) {
2709 all_but_self_ipi(XINVLTLB_OFFSET);
2710 } else {
2711 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2712 APIC_DELMODE_FIXED);
2713 }
2714 #endif
2715 }
2716
2717 /*
2718 * When called the executing CPU will send an IPI to all other CPUs
2719 * requesting that they halt execution.
2720 *
2721 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2722 *
2723 * - Signals all CPUs in map to stop.
2724 * - Waits for each to stop.
2725 *
2726 * Returns:
2727 * -1: error
2728 * 0: NA
2729 * 1: ok
2730 *
2731 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2732 * from executing at same time.
2733 */
2734 int
2735 stop_cpus(u_int map)
2736 {
2737 map &= smp_active_mask;
2738
2739 /* send the Xcpustop IPI to all CPUs in map */
2740 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2741
2742 while ((stopped_cpus & map) != map)
2743 /* spin */ ;
2744
2745 return 1;
2746 }
2747
2748
2749 /*
2750 * Called by a CPU to restart stopped CPUs.
2751 *
2752 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2753 *
2754 * - Signals all CPUs in map to restart.
2755 * - Waits for each to restart.
2756 *
2757 * Returns:
2758 * -1: error
2759 * 0: NA
2760 * 1: ok
2761 */
2762 int
2763 restart_cpus(u_int map)
2764 {
2765 /* signal other cpus to restart */
2766 started_cpus = map & smp_active_mask;
2767
2768 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2769 /* spin */ ;
2770
2771 return 1;
2772 }
2773
2774 /*
2775 * This is called once the mpboot code has gotten us properly relocated
2776 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2777 * and when it returns the scheduler will call the real cpu_idle() main
2778 * loop for the idlethread. Interrupts are disabled on entry and should
2779 * remain disabled at return.
2780 */
2781 void
2782 ap_init(void)
2783 {
2784 u_int apic_id;
2785
2786 /*
2787 * Adjust smp_startup_mask to signal the BSP that we have started
2788 * up successfully. Note that we do not yet hold the BGL. The BSP
2789 * is waiting for our signal.
2790 *
2791 * We can't set our bit in smp_active_mask yet because we are holding
2792 * interrupts physically disabled and remote cpus could deadlock
2793 * trying to send us an IPI.
2794 */
2795 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2796 cpu_mfence();
2797
2798 /*
2799 * Interlock for finalization. Wait until mp_finish is non-zero,
2800 * then get the MP lock.
2801 *
2802 * Note: We are in a critical section.
2803 *
2804 * Note: We have to synchronize td_mpcount to our desired MP state
2805 * before calling cpu_try_mplock().
2806 *
2807 * Note: we are the idle thread, we can only spin.
2808 *
2809 * Note: The load fence is memory volatile and prevents the compiler
2810 * from improperly caching mp_finish, and the cpu from improperly
2811 * caching it.
2812 */
2813 while (mp_finish == 0)
2814 cpu_lfence();
2815 ++curthread->td_mpcount;
2816 while (cpu_try_mplock() == 0)
2817 ;
2818
2819 if (cpu_feature & CPUID_TSC) {
2820 /*
2821 * The BSP is constantly updating tsc0_offset, figure out the
2822 * relative difference to synchronize ktrdump.
2823 */
2824 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2825 }
2826
2827 /* BSP may have changed PTD while we're waiting for the lock */
2828 cpu_invltlb();
2829
2830 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2831 lidt(&r_idt);
2832 #endif
2833
2834 /* Build our map of 'other' CPUs. */
2835 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2836
2837 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2838
2839 /* A quick check from sanity claus */
2840 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2841 if (mycpu->gd_cpuid != apic_id) {
2842 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2843 kprintf("SMP: apic_id = %d\n", apic_id);
2844 #if JGXXX
2845 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2846 #endif
2847 panic("cpuid mismatch! boom!!");
2848 }
2849
2850 /* Initialize AP's local APIC for irq's */
2851 apic_initialize(FALSE);
2852
2853 /* Set memory range attributes for this CPU to match the BSP */
2854 mem_range_AP_init();
2855
2856 /*
2857 * Once we go active we must process any IPIQ messages that may
2858 * have been queued, because no actual IPI will occur until we
2859 * set our bit in the smp_active_mask. If we don't the IPI
2860 * message interlock could be left set which would also prevent
2861 * further IPIs.
2862 *
2863 * The idle loop doesn't expect the BGL to be held and while
2864 * lwkt_switch() normally cleans things up this is a special case
2865 * because we returning almost directly into the idle loop.
2866 *
2867 * The idle thread is never placed on the runq, make sure
2868 * nothing we've done put it there.
2869 */
2870 KKASSERT(curthread->td_mpcount == 1);
2871 smp_active_mask |= 1 << mycpu->gd_cpuid;
2872
2873 /*
2874 * Enable interrupts here. idle_restore will also do it, but
2875 * doing it here lets us clean up any strays that got posted to
2876 * the CPU during the AP boot while we are still in a critical
2877 * section.
2878 */
2879 __asm __volatile("sti; pause; pause"::);
2880 mdcpu->gd_fpending = 0;
2881
2882 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2883 lwkt_process_ipiq();
2884
2885 /*
2886 * Releasing the mp lock lets the BSP finish up the SMP init
2887 */
2888 rel_mplock();
2889 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2890 }
2891
2892 /*
2893 * Get SMP fully working before we start initializing devices.
2894 */
2895 static
2896 void
2897 ap_finish(void)
2898 {
2899 mp_finish = 1;
2900 if (bootverbose)
2901 kprintf("Finish MP startup\n");
2902 if (cpu_feature & CPUID_TSC)
2903 tsc0_offset = rdtsc();
2904 tsc_offsets[0] = 0;
2905 rel_mplock();
2906 while (smp_active_mask != smp_startup_mask) {
2907 cpu_lfence();
2908 if (cpu_feature & CPUID_TSC)
2909 tsc0_offset = rdtsc();
2910 }
2911 while (try_mplock() == 0)
2912 ;
2913 if (bootverbose)
2914 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2915 }
2916
2917 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2918
2919 void
2920 cpu_send_ipiq(int dcpu)
2921 {
2922 if ((1 << dcpu) & smp_active_mask)
2923 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2924 }
2925
2926 #if 0 /* single_apic_ipi_passive() not working yet */
2927 /*
2928 * Returns 0 on failure, 1 on success
2929 */
2930 int
2931 cpu_send_ipiq_passive(int dcpu)
2932 {
2933 int r = 0;
2934 if ((1 << dcpu) & smp_active_mask) {
2935 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2936 APIC_DELMODE_FIXED);
2937 }
2938 return(r);
2939 }
2940 #endif
2941
2942 struct mptable_lapic_cbarg1 {
2943 int cpu_count;
2944 u_int id_mask;
2945 };
2946
2947 static int
2948 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2949 {
2950 const struct PROCENTRY *ent;
2951 struct mptable_lapic_cbarg1 *arg = xarg;
2952
2953 if (type != 0)
2954 return 0;
2955 ent = pos;
2956
2957 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2958 return 0;
2959
2960 arg->cpu_count++;
2961 arg->id_mask |= 1 << ent->apic_id;
2962 return 0;
2963 }
2964
2965 struct mptable_lapic_cbarg2 {
2966 int cpu;
2967 int found_bsp;
2968 };
2969
2970 static int
2971 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2972 {
2973 const struct PROCENTRY *ent;
2974 struct mptable_lapic_cbarg2 *arg = xarg;
2975
2976 if (type != 0)
2977 return 0;
2978 ent = pos;
2979
2980 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2981 KKASSERT(!arg->found_bsp);
2982 arg->found_bsp = 1;
2983 }
2984
2985 if (processor_entry(ent, arg->cpu))
2986 arg->cpu++;
2987
2988 if (need_hyperthreading_fixup) {
2989 struct PROCENTRY proc;
2990 int i;
2991
2992 /*
2993 * Create fake mptable processor entries
2994 * and feed them to processor_entry() to
2995 * enumerate the logical CPUs.
2996 */
2997 bzero(&proc, sizeof(proc));
2998 proc.type = 0;
2999 proc.cpu_flags = PROCENTRY_FLAG_EN;
3000 proc.apic_id = ent->apic_id;
3001
3002 for (i = 1; i < logical_cpus; i++) {
3003 proc.apic_id++;
3004 processor_entry(&proc, arg->cpu);
3005 logical_cpus_mask |= (1 << arg->cpu);
3006 arg->cpu++;
3007 }
3008 }
3009 return 0;
3010 }
3011
3012 /*
3013 * Configure:
3014 * cpu_apic_address (common to all CPUs)
3015 * mp_naps
3016 * need_hyperthreading_fixup
3017 * logical_cpus
3018 * logical_cpus_mask
3019 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
3020 * CPU_TO_ID(N), logical CPU to APIC ID table
3021 */
3022 static void
3023 mptable_lapic_enumerate(struct mptable_pos *mpt)
3024 {
3025 mpfps_t fps;
3026 int error;
3027 vm_offset_t lapic_addr;
3028
3029 fps = mpt->mp_fps;
3030 KKASSERT(fps != NULL);
3031
3032 /* init everything to empty */
3033 mp_naps = 0;
3034
3035 /* check for use of 'default' configuration */
3036 if (fps->mpfb1 != 0) {
3037 /* use default addresses */
3038 lapic_addr = DEFAULT_APIC_BASE;
3039
3040 /* fill in with defaults */
3041 mp_naps = 1; /* exclude BSP */
3042 } else {
3043 struct mptable_lapic_cbarg1 arg;
3044 mpcth_t cth;
3045
3046 cth = mpt->mp_cth;
3047 KKASSERT(cth != NULL);
3048
3049 lapic_addr = (vm_offset_t)cth->apic_address;
3050 KKASSERT(lapic_addr != 0);
3051
3052 bzero(&arg, sizeof(arg));
3053 error = mptable_iterate_entries(cth,
3054 mptable_lapic_pass1_callback, &arg);
3055 if (error)
3056 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3057
3058 KKASSERT(arg.cpu_count != 0);
3059 mp_naps = arg.cpu_count;
3060
3061 /* Qualify the numbers */
3062 if (mp_naps > MAXCPU) {
3063 kprintf("Warning: only using %d of %d available CPUs!\n",
3064 MAXCPU, mp_naps);
3065 mp_naps = MAXCPU;
3066 }
3067
3068 /* See if we need to fixup HT logical CPUs. */
3069 mptable_hyperthread_fixup(arg.id_mask);
3070
3071 /* Qualify the numbers again, after hyperthreading fixup */
3072 if (mp_naps > MAXCPU) {
3073 kprintf("Warning: only using %d of %d available CPUs!\n",
3074 MAXCPU, mp_naps);
3075 mp_naps = MAXCPU;
3076 }
3077
3078 --mp_naps; /* subtract the BSP */
3079 }
3080
3081 lapic_init(lapic_addr);
3082
3083 if (fps->mpfb1 != 0) {
3084 int ap_cpu_id, boot_cpu_id;
3085
3086 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
3087 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
3088
3089 /* BSP */
3090 CPU_TO_ID(0) = boot_cpu_id;
3091 ID_TO_CPU(boot_cpu_id) = 0;
3092
3093 /* one and only AP */
3094 CPU_TO_ID(1) = ap_cpu_id;
3095 ID_TO_CPU(ap_cpu_id) = 1;
3096 } else {
3097 struct mptable_lapic_cbarg2 arg;
3098
3099 bzero(&arg, sizeof(arg));
3100 arg.cpu = 1;
3101
3102 error = mptable_iterate_entries(mpt->mp_cth,
3103 mptable_lapic_pass2_callback, &arg);
3104 if (error)
3105 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3106 KKASSERT(arg.found_bsp);
3107 }
3108 }
3109
3110 static void
3111 lapic_init(vm_offset_t lapic_addr)
3112 {
3113 /*
3114 * lapic not mapped yet (pmap_init is called too late)
3115 */
3116 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
3117
3118 #if 0
3119 /* Local apic is mapped on last page */
3120 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
3121 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
3122 #endif
3123
3124 /* Just for printing */
3125 cpu_apic_address = lapic_addr;
3126 }
DragonFly BSD