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ahci - Add workarounds for Marvell 88SE9215
[dragonfly.git] / sys / dev / disk / ahci / ahci_attach.c
blob07c5d2ce261337e013cb7d66cee2d0e5a001fd23
1 /*
2 * (MPSAFE)
3 *
4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 *
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
20 *
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 *
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
52 */
53
54 #include "ahci.h"
55
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_nvidia_mcp_attach(device_t);
59 static int ahci_pci_attach(device_t);
60 static int ahci_pci_detach(device_t);
61
62 static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
74 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" },
75 { 0, 0,
76 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
77 };
78
79 struct ahci_pciid {
80 uint16_t ahci_vid;
81 uint16_t ahci_did;
82 int ahci_rev;
83 };
84
85 static const struct ahci_pciid ahci_msi_blacklist[] = {
86 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 },
87 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 },
88
89 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 },
90 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 },
91
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 },
93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 },
95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 },
97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 },
98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 },
99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 },
100
101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 },
103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 },
105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 },
107 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 },
108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 }
109 };
110
111 static int ahci_msi_enable = 1;
112 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable);
113
114 /*
115 * Match during probe and attach. The device does not yet have a softc.
116 */
117 const struct ahci_device *
118 ahci_lookup_device(device_t dev)
119 {
120 const struct ahci_device *ad;
121 u_int16_t vendor = pci_get_vendor(dev);
122 u_int16_t product = pci_get_device(dev);
123 u_int8_t class = pci_get_class(dev);
124 u_int8_t subclass = pci_get_subclass(dev);
125 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
126 int is_ahci;
127
128 /*
129 * Generally speaking if the pci device does not identify as
130 * AHCI we skip it.
131 */
132 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
133 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
134 is_ahci = 1;
135 } else {
136 is_ahci = 0;
137 }
138
139 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
140 if (ad->ad_vendor == vendor && ad->ad_product == product)
141 return (ad);
142 }
143
144 /*
145 * Last ad is the default match if the PCI device matches SATA.
146 */
147 if (is_ahci == 0)
148 ad = NULL;
149 return (ad);
150 }
151
152 /*
153 * Attach functions. They all eventually fall through to ahci_pci_attach().
154 */
155 static int
156 ahci_vt8251_attach(device_t dev)
157 {
158 struct ahci_softc *sc = device_get_softc(dev);
159
160 sc->sc_flags |= AHCI_F_NO_NCQ;
161 return (ahci_pci_attach(dev));
162 }
163
164 static int
165 ahci_ati_sb600_attach(device_t dev)
166 {
167 struct ahci_softc *sc = device_get_softc(dev);
168 pcireg_t magic;
169 u_int8_t subclass = pci_get_subclass(dev);
170 u_int8_t revid;
171
172 if (subclass == PCIS_STORAGE_IDE) {
173 revid = pci_read_config(dev, PCIR_REVID, 1);
174 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
175 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
176 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
177 pci_write_config(dev, PCIR_REVID,
178 (PCIC_STORAGE << 24) |
179 (PCIS_STORAGE_SATA << 16) |
180 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
181 revid, 4);
182 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
183 }
184
185 sc->sc_flags |= AHCI_F_IGN_FR;
186 return (ahci_pci_attach(dev));
187 }
188
189 static int
190 ahci_nvidia_mcp_attach(device_t dev)
191 {
192 struct ahci_softc *sc = device_get_softc(dev);
193
194 sc->sc_flags |= AHCI_F_IGN_FR;
195 return (ahci_pci_attach(dev));
196 }
197
198 static int
199 ahci_pci_attach(device_t dev)
200 {
201 struct ahci_softc *sc = device_get_softc(dev);
202 struct ahci_port *ap;
203 const char *gen;
204 uint16_t vid, did;
205 u_int32_t pi, reg;
206 u_int32_t cap, cap2;
207 u_int32_t chip;
208 u_int irq_flags;
209 bus_addr_t addr;
210 int i, error, msi_enable, rev, fbs;
211 char revbuf[32];
212
213 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
214 device_printf(dev, "BIOS disabled PCI interrupt, "
215 "re-enabling\n");
216 pci_write_config(dev, PCIR_COMMAND,
217 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
218 }
219
220 /*
221 * Chip quirks. Sigh. The AHCI spec is not in the least confusing
222 * when it comes to how the FR and CR bits work, but some AHCI
223 * chipsets (aka Marvell) either don't have the bits at all or they
224 * implement them poorly.
225 */
226 chip = ((uint16_t)pci_get_device(dev) << 16) |
227 (uint16_t)pci_get_vendor(dev);
228
229 switch(chip) {
230 case 0x91721b4b:
231 device_printf(dev,
232 "Enable 88SE9172 workarounds for broken chip\n");
233 sc->sc_flags |= AHCI_F_IGN_FR;
234 sc->sc_flags |= AHCI_F_IGN_CR;
235 break;
236 case 0x92151b4b:
237 device_printf(dev,
238 "Enable 88SE9215 workarounds for broken chip\n");
239 sc->sc_flags |= AHCI_F_IGN_FR;
240 sc->sc_flags |= AHCI_F_IGN_CR;
241 break;
242 case 0x92301b4b:
243 device_printf(dev,
244 "Enable 88SE9230 workarounds for broken chip\n");
245 sc->sc_flags |= AHCI_F_CYCLE_FR;
246 break;
247 }
248
249 sc->sc_dev = dev;
250
251 /*
252 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
253 */
254 msi_enable = ahci_msi_enable;
255
256 vid = pci_get_vendor(dev);
257 did = pci_get_device(dev);
258 rev = pci_get_revid(dev);
259 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) {
260 const struct ahci_pciid *id = &ahci_msi_blacklist[i];
261
262 if (vid == id->ahci_vid && did == id->ahci_did) {
263 if (id->ahci_rev < 0 || id->ahci_rev == rev) {
264 msi_enable = 0;
265 break;
266 }
267 }
268 }
269
270 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable,
271 &sc->sc_rid_irq, &irq_flags);
272
273 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
274 irq_flags);
275 if (sc->sc_irq == NULL) {
276 device_printf(dev, "unable to map interrupt\n");
277 ahci_pci_detach(dev);
278 return (ENXIO);
279 }
280
281 /*
282 * When mapping the register window store the tag and handle
283 * separately so we can use the tag with per-port bus handle
284 * sub-spaces.
285 */
286 sc->sc_rid_regs = PCIR_BAR(5);
287 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
288 &sc->sc_rid_regs, RF_ACTIVE);
289 if (sc->sc_regs == NULL) {
290 device_printf(dev, "unable to map registers\n");
291 ahci_pci_detach(dev);
292 return (ENXIO);
293 }
294 sc->sc_iot = rman_get_bustag(sc->sc_regs);
295 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
296
297 /*
298 * Initialize the chipset and then set the interrupt vector up
299 */
300 error = ahci_init(sc);
301 if (error) {
302 ahci_pci_detach(dev);
303 return (ENXIO);
304 }
305
306 /*
307 * Get the AHCI capabilities and max number of concurrent
308 * command tags and set up the DMA tags. Adjust the saved
309 * sc_cap according to override flags.
310 */
311 cap = ahci_read(sc, AHCI_REG_CAP);
312 if (sc->sc_flags & AHCI_F_NO_NCQ)
313 cap &= ~AHCI_REG_CAP_SNCQ;
314 if (sc->sc_flags & AHCI_F_FORCE_FBSS)
315 cap |= AHCI_REG_CAP_FBSS;
316 if (sc->sc_flags & AHCI_F_FORCE_SCLO)
317 cap |= AHCI_REG_CAP_SCLO;
318 sc->sc_cap = cap;
319
320 /*
321 * We assume at least 4 commands.
322 */
323 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
324 if (sc->sc_ncmds < 4) {
325 device_printf(dev, "NCS must probe a value >= 4\n");
326 ahci_pci_detach(dev);
327 return (ENXIO);
328 }
329
330 addr = (cap & AHCI_REG_CAP_S64A) ?
331 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
332
333 /*
334 * DMA tags for allocation of DMA memory buffers, lists, and so
335 * forth. These are typically per-port.
336 *
337 * When FIS-based switching is supported we need a rfis for
338 * each target (4K total). The spec also requires 4K alignment
339 * for this case.
340 */
341 fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1;
342 error = 0;
343
344 sc->sc_rfis_size = sizeof(struct ahci_rfis) * fbs;
345
346 error += bus_dma_tag_create(
347 NULL, /* parent tag */
348 sc->sc_rfis_size, /* alignment */
349 PAGE_SIZE, /* boundary */
350 addr, /* loaddr? */
351 BUS_SPACE_MAXADDR, /* hiaddr */
352 NULL, /* filter */
353 NULL, /* filterarg */
354 sc->sc_rfis_size, /* [max]size */
355 1, /* maxsegs */
356 sc->sc_rfis_size, /* maxsegsz */
357 0, /* flags */
358 &sc->sc_tag_rfis); /* return tag */
359
360 sc->sc_cmdlist_size = sc->sc_ncmds * sizeof(struct ahci_cmd_hdr);
361
362 error += bus_dma_tag_create(
363 NULL, /* parent tag */
364 32, /* alignment */
365 4096 * 1024, /* boundary */
366 addr, /* loaddr? */
367 BUS_SPACE_MAXADDR, /* hiaddr */
368 NULL, /* filter */
369 NULL, /* filterarg */
370 sc->sc_cmdlist_size,
371 1, /* maxsegs */
372 sc->sc_cmdlist_size,
373 0, /* flags */
374 &sc->sc_tag_cmdh); /* return tag */
375
376 /*
377 * NOTE: ahci_cmd_table is sized to a power of 2
378 */
379 error += bus_dma_tag_create(
380 NULL, /* parent tag */
381 sizeof(struct ahci_cmd_table), /* alignment */
382 4096 * 1024, /* boundary */
383 addr, /* loaddr? */
384 BUS_SPACE_MAXADDR, /* hiaddr */
385 NULL, /* filter */
386 NULL, /* filterarg */
387 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
388 1, /* maxsegs */
389 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
390 0, /* flags */
391 &sc->sc_tag_cmdt); /* return tag */
392
393 /*
394 * The data tag is used for later dmamaps and not immediately
395 * allocated.
396 */
397 error += bus_dma_tag_create(
398 NULL, /* parent tag */
399 4, /* alignment */
400 0, /* boundary */
401 addr, /* loaddr? */
402 BUS_SPACE_MAXADDR, /* hiaddr */
403 NULL, /* filter */
404 NULL, /* filterarg */
405 4096 * 1024, /* maxiosize */
406 AHCI_MAX_PRDT, /* maxsegs */
407 65536, /* maxsegsz */
408 0, /* flags */
409 &sc->sc_tag_data); /* return tag */
410
411 if (error) {
412 device_printf(dev, "unable to create dma tags\n");
413 ahci_pci_detach(dev);
414 return (ENXIO);
415 }
416
417 switch (cap & AHCI_REG_CAP_ISS) {
418 case AHCI_REG_CAP_ISS_G1:
419 gen = "1 (1.5Gbps)";
420 break;
421 case AHCI_REG_CAP_ISS_G2:
422 gen = "2 (3Gbps)";
423 break;
424 case AHCI_REG_CAP_ISS_G3:
425 gen = "3 (6Gbps)";
426 break;
427 default:
428 gen = "unknown";
429 break;
430 }
431
432 /* check the revision */
433 reg = ahci_read(sc, AHCI_REG_VS);
434
435 if (reg & 0x0000FF) {
436 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d.%d",
437 (reg >> 16), (uint8_t)(reg >> 8), (uint8_t)reg);
438 } else {
439 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d",
440 (reg >> 16), (uint8_t)(reg >> 8));
441 }
442 sc->sc_vers = reg;
443
444 if (reg >= AHCI_REG_VS_1_3) {
445 cap2 = ahci_read(sc, AHCI_REG_CAP2);
446 device_printf(dev,
447 "%s cap 0x%b cap2 0x%b, %d ports, "
448 "%d tags/port, gen %s\n",
449 revbuf,
450 cap, AHCI_FMT_CAP,
451 cap2, AHCI_FMT_CAP2,
452 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
453 } else {
454 cap2 = 0;
455 device_printf(dev,
456 "%s cap 0x%b, %d ports, "
457 "%d tags/port, gen %s\n",
458 revbuf,
459 cap, AHCI_FMT_CAP,
460 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
461 }
462 sc->sc_cap2 = cap2;
463
464 pi = ahci_read(sc, AHCI_REG_PI);
465 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
466 DEVNAME(sc), pi);
467
468 sc->sc_ipm_disable = AHCI_PREG_SCTL_IPM_NOPARTIAL |
469 AHCI_PREG_SCTL_IPM_NOSLUMBER;
470 if (sc->sc_cap2 & AHCI_REG_CAP2_SDS)
471 sc->sc_ipm_disable |= AHCI_PREG_SCTL_IPM_NODEVSLP;
472
473 #ifdef AHCI_COALESCE
474 /* Naive coalescing support - enable for all ports. */
475 if (cap & AHCI_REG_CAP_CCCS) {
476 u_int16_t ccc_timeout = 20;
477 u_int8_t ccc_numcomplete = 12;
478 u_int32_t ccc_ctl;
479
480 /* disable coalescing during reconfiguration. */
481 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
482 ccc_ctl &= ~0x00000001;
483 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
484
485 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
486 if (pi & sc->sc_ccc_mask) {
487 /* A conflict with the implemented port list? */
488 printf("%s: coalescing interrupt/implemented port list "
489 "conflict, PI: %08x, ccc_mask: %08x\n",
490 DEVNAME(sc), pi, sc->sc_ccc_mask);
491 sc->sc_ccc_mask = 0;
492 goto noccc;
493 }
494
495 /* ahci_port_start will enable each port when it starts. */
496 sc->sc_ccc_ports = pi;
497 sc->sc_ccc_ports_cur = 0;
498
499 /* program thresholds and enable overall coalescing. */
500 ccc_ctl &= ~0xffffff00;
501 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
502 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
503 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
504 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
505 }
506 noccc:
507 #endif
508 /*
509 * Allocate per-port resources
510 *
511 * Ignore attach errors, leave the port intact for
512 * rescan and continue the loop.
513 *
514 * All ports are attached in parallel but the CAM scan-bus
515 * is held up until all ports are attached so we get a deterministic
516 * order.
517 */
518 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
519 if ((pi & (1 << i)) == 0) {
520 /* dont allocate stuff if the port isnt implemented */
521 continue;
522 }
523 error = ahci_port_alloc(sc, i);
524 }
525
526 /*
527 * Setup the interrupt vector and enable interrupts. Note that
528 * since the irq may be shared we do not set it up until we are
529 * ready to go.
530 */
531 if (error == 0) {
532 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
533 ahci_intr, sc,
534 &sc->sc_irq_handle, NULL);
535 }
536
537 if (error) {
538 device_printf(dev, "unable to install interrupt\n");
539 ahci_pci_detach(dev);
540 return (ENXIO);
541 }
542
543 /*
544 * Before marking the sc as good, which allows the interrupt
545 * subsystem to operate on the ports, wait for all the port threads
546 * to get past their initial pre-probe init. Otherwise an interrupt
547 * may try to process the port before it has been initialized.
548 */
549 for (i = 0; i < AHCI_MAX_PORTS; i++) {
550 if ((ap = sc->sc_ports[i]) != NULL) {
551 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
552 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
553 }
554 }
555
556 /*
557 * Master interrupt enable, and call ahci_intr() in case we race
558 * our AHCI_F_INT_GOOD flag.
559 */
560 crit_enter();
561 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
562 sc->sc_flags |= AHCI_F_INT_GOOD;
563 crit_exit();
564 ahci_intr(sc);
565
566 /*
567 * All ports are probing in parallel. Wait for them to finish
568 * and then issue the cam attachment and bus scan serially so
569 * the 'da' assignments are deterministic.
570 */
571 for (i = 0; i < AHCI_MAX_PORTS; i++) {
572 if ((ap = sc->sc_ports[i]) != NULL) {
573 while (ap->ap_signal & AP_SIGF_INIT)
574 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
575 ahci_os_lock_port(ap);
576 if (ahci_cam_attach(ap) == 0) {
577 ahci_cam_changed(ap, NULL, -1);
578 ahci_os_unlock_port(ap);
579 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
580 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
581 }
582 } else {
583 ahci_os_unlock_port(ap);
584 }
585 }
586 }
587
588 return(0);
589 }
590
591 /*
592 * Device unload / detachment
593 */
594 static int
595 ahci_pci_detach(device_t dev)
596 {
597 struct ahci_softc *sc = device_get_softc(dev);
598 struct ahci_port *ap;
599 int i;
600
601 /*
602 * Disable the controller and de-register the interrupt, if any.
603 *
604 * XXX interlock last interrupt?
605 */
606 sc->sc_flags &= ~AHCI_F_INT_GOOD;
607 if (sc->sc_regs)
608 ahci_write(sc, AHCI_REG_GHC, 0);
609
610 if (sc->sc_irq_handle) {
611 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
612 sc->sc_irq_handle = NULL;
613 }
614
615 /*
616 * Free port structures and DMA memory
617 */
618 for (i = 0; i < AHCI_MAX_PORTS; i++) {
619 ap = sc->sc_ports[i];
620 if (ap) {
621 ahci_cam_detach(ap);
622 ahci_port_free(sc, i);
623 }
624 }
625
626 /*
627 * Clean up the bus space
628 */
629 if (sc->sc_irq) {
630 bus_release_resource(dev, SYS_RES_IRQ,
631 sc->sc_rid_irq, sc->sc_irq);
632 sc->sc_irq = NULL;
633 }
634
635 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI)
636 pci_release_msi(dev);
637
638 if (sc->sc_regs) {
639 bus_release_resource(dev, SYS_RES_MEMORY,
640 sc->sc_rid_regs, sc->sc_regs);
641 sc->sc_regs = NULL;
642 }
643
644 if (sc->sc_tag_rfis) {
645 bus_dma_tag_destroy(sc->sc_tag_rfis);
646 sc->sc_tag_rfis = NULL;
647 }
648 if (sc->sc_tag_cmdh) {
649 bus_dma_tag_destroy(sc->sc_tag_cmdh);
650 sc->sc_tag_cmdh = NULL;
651 }
652 if (sc->sc_tag_cmdt) {
653 bus_dma_tag_destroy(sc->sc_tag_cmdt);
654 sc->sc_tag_cmdt = NULL;
655 }
656 if (sc->sc_tag_data) {
657 bus_dma_tag_destroy(sc->sc_tag_data);
658 sc->sc_tag_data = NULL;
659 }
660
661 return (0);
662 }
DragonFly BSD