1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi_drm/i915_drm.h>
34 #include <uapi_drm/drm_fourcc.h>
37 #include <linux/io-mapping.h>
38 #include <linux/i2c.h>
39 #include <linux/i2c-algo-bit.h>
40 #include <linux/backlight.h>
41 #include <linux/hashtable.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
51 #include "i915_params.h"
54 #include "intel_bios.h"
55 #include "intel_dpll_mgr.h"
56 #include "intel_guc.h"
57 #include "intel_lrc.h"
58 #include "intel_ringbuffer.h"
61 #include "i915_gem_gtt.h"
62 #include "i915_gem_render_state.h"
64 #define CONFIG_DRM_FBDEV_EMULATION 1
65 #define CONFIG_DRM_I915_KMS 1
66 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1
70 /* General customization:
73 #define DRIVER_NAME "i915"
74 #define DRIVER_DESC "Intel Graphics"
75 #define DRIVER_DATE "20160425"
78 /* Many gcc seem to no see through this and fall over :( */
80 #define WARN_ON(x) ({ \
81 bool __i915_warn_cond = (x); \
82 if (__builtin_constant_p(__i915_warn_cond)) \
83 BUILD_BUG_ON(__i915_warn_cond); \
84 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
86 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
90 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
92 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
93 (long) (x), __func__);
95 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
96 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
97 * which may not necessarily be a user visible problem. This will either
98 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
99 * enable distros and users to tailor their preferred amount of i915 abrt
102 #define I915_STATE_WARN(condition, format...) ({ \
103 int __ret_warn_on = !!(condition); \
104 if (unlikely(__ret_warn_on)) \
105 if (!WARN(i915.verbose_state_checks, format)) \
107 unlikely(__ret_warn_on); \
110 #define I915_STATE_WARN_ON(x) \
111 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
113 bool __i915_inject_load_failure(const char *func
, int line
);
114 #define i915_inject_load_failure() \
115 __i915_inject_load_failure(__func__, __LINE__)
117 static inline const char *yesno(bool v
)
119 return v
? "yes" : "no";
122 static inline const char *onoff(bool v
)
124 return v
? "on" : "off";
133 I915_MAX_PIPES
= _PIPE_EDP
135 #define pipe_name(p) ((p) + 'A')
147 static inline const char *transcoder_name(enum transcoder transcoder
)
149 switch (transcoder
) {
158 case TRANSCODER_DSI_A
:
160 case TRANSCODER_DSI_C
:
167 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
169 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
173 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
174 * number of planes per CRTC. Not all platforms really have this many planes,
175 * which means some arrays of size I915_MAX_PLANES may have unused entries
176 * between the topmost sprite plane and the cursor plane.
185 #define plane_name(p) ((p) + 'A')
187 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
197 #define port_name(p) ((p) + 'A')
199 #define I915_NUM_PHYS_VLV 2
211 enum intel_display_power_domain
{
215 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
216 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
217 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
218 POWER_DOMAIN_TRANSCODER_A
,
219 POWER_DOMAIN_TRANSCODER_B
,
220 POWER_DOMAIN_TRANSCODER_C
,
221 POWER_DOMAIN_TRANSCODER_EDP
,
222 POWER_DOMAIN_TRANSCODER_DSI_A
,
223 POWER_DOMAIN_TRANSCODER_DSI_C
,
224 POWER_DOMAIN_PORT_DDI_A_LANES
,
225 POWER_DOMAIN_PORT_DDI_B_LANES
,
226 POWER_DOMAIN_PORT_DDI_C_LANES
,
227 POWER_DOMAIN_PORT_DDI_D_LANES
,
228 POWER_DOMAIN_PORT_DDI_E_LANES
,
229 POWER_DOMAIN_PORT_DSI
,
230 POWER_DOMAIN_PORT_CRT
,
231 POWER_DOMAIN_PORT_OTHER
,
240 POWER_DOMAIN_MODESET
,
246 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
247 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
248 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
249 #define POWER_DOMAIN_TRANSCODER(tran) \
250 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
251 (tran) + POWER_DOMAIN_TRANSCODER_A)
255 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
267 #define for_each_hpd_pin(__pin) \
268 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
270 struct i915_hotplug
{
271 struct work_struct hotplug_work
;
274 unsigned long last_jiffies
;
279 HPD_MARK_DISABLED
= 2
281 } stats
[HPD_NUM_PINS
];
283 struct delayed_work reenable_work
;
285 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
288 struct work_struct dig_port_work
;
290 struct work_struct poll_init_work
;
294 * if we get a HPD irq from DP and a HPD irq from non-DP
295 * the non-DP HPD could block the workqueue on a mode config
296 * mutex getting, that userspace may have taken. However
297 * userspace is waiting on the DP workqueue to run which is
298 * blocked behind the non-DP one.
300 struct workqueue_struct
*dp_wq
;
303 #define I915_GEM_GPU_DOMAINS \
304 (I915_GEM_DOMAIN_RENDER | \
305 I915_GEM_DOMAIN_SAMPLER | \
306 I915_GEM_DOMAIN_COMMAND | \
307 I915_GEM_DOMAIN_INSTRUCTION | \
308 I915_GEM_DOMAIN_VERTEX)
310 #define for_each_pipe(__dev_priv, __p) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
312 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
313 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
314 for_each_if ((__mask) & (1 << (__p)))
315 #define for_each_plane(__dev_priv, __pipe, __p) \
317 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
319 #define for_each_sprite(__dev_priv, __p, __s) \
321 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
324 #define for_each_port_masked(__port, __ports_mask) \
325 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
326 for_each_if ((__ports_mask) & (1 << (__port)))
328 #define for_each_crtc(dev, crtc) \
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
331 #define for_each_intel_plane(dev, intel_plane) \
332 list_for_each_entry(intel_plane, \
333 &dev->mode_config.plane_list, \
336 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
337 list_for_each_entry(intel_plane, \
338 &(dev)->mode_config.plane_list, \
340 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
342 #define for_each_intel_crtc(dev, intel_crtc) \
343 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
345 #define for_each_intel_encoder(dev, intel_encoder) \
346 list_for_each_entry(intel_encoder, \
347 &(dev)->mode_config.encoder_list, \
350 #define for_each_intel_connector(dev, intel_connector) \
351 list_for_each_entry(intel_connector, \
352 &dev->mode_config.connector_list, \
355 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
356 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
357 for_each_if ((intel_encoder)->base.crtc == (__crtc))
359 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
360 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
361 for_each_if ((intel_connector)->base.encoder == (__encoder))
363 #define for_each_power_domain(domain, mask) \
364 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
365 for_each_if ((1 << (domain)) & (mask))
367 struct drm_i915_private
;
368 struct i915_mm_struct
;
369 struct i915_mmu_object
;
371 struct drm_i915_file_private
{
372 struct drm_i915_private
*dev_priv
;
373 struct drm_file
*file
;
376 struct spinlock lock
;
377 struct list_head request_list
;
378 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
379 * chosen to prevent the CPU getting more than a frame ahead of the GPU
380 * (when using lax throttling for the frontbuffer). We also use it to
381 * offer free GPU waitboosts for severely congested workloads.
383 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
385 struct idr context_idr
;
387 struct intel_rps_client
{
388 struct list_head link
;
392 unsigned int bsd_ring
;
395 /* Used by dp and fdi links */
396 struct intel_link_m_n
{
404 void intel_link_compute_m_n(int bpp
, int nlanes
,
405 int pixel_clock
, int link_clock
,
406 struct intel_link_m_n
*m_n
);
408 /* Interface history:
411 * 1.2: Add Power Management
412 * 1.3: Add vblank support
413 * 1.4: Fix cmdbuffer path, add heap destroy
414 * 1.5: Add vblank pipe configuration
415 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
416 * - Support vertical blank on secondary display pipe
418 #define DRIVER_MAJOR 1
419 #define DRIVER_MINOR 6
420 #define DRIVER_PATCHLEVEL 0
422 #define WATCH_LISTS 0
424 struct opregion_header
;
425 struct opregion_acpi
;
426 struct opregion_swsci
;
427 struct opregion_asle
;
429 struct intel_opregion
{
430 struct opregion_header
*header
;
431 struct opregion_acpi
*acpi
;
432 struct opregion_swsci
*swsci
;
433 u32 swsci_gbda_sub_functions
;
434 u32 swsci_sbcb_sub_functions
;
435 struct opregion_asle
*asle
;
440 struct work_struct asle_work
;
442 #define OPREGION_SIZE (8*1024)
444 struct intel_overlay
;
445 struct intel_overlay_error_state
;
447 #define I915_FENCE_REG_NONE -1
448 #define I915_MAX_NUM_FENCES 32
449 /* 32 fences + sign bit for FENCE_REG_NONE */
450 #define I915_MAX_NUM_FENCE_BITS 6
452 struct drm_i915_fence_reg
{
453 struct list_head lru_list
;
454 struct drm_i915_gem_object
*obj
;
458 struct sdvo_device_mapping
{
467 struct intel_display_error_state
;
469 struct drm_i915_error_state
{
478 /* Generic register state */
486 u32 error
; /* gen6+ */
487 u32 err_int
; /* gen7 */
488 u32 fault_data0
; /* gen8, gen9 */
489 u32 fault_data1
; /* gen8, gen9 */
495 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
496 u64 fence
[I915_MAX_NUM_FENCES
];
497 struct intel_overlay_error_state
*overlay
;
498 struct intel_display_error_state
*display
;
499 struct drm_i915_error_object
*semaphore_obj
;
501 struct drm_i915_error_ring
{
503 /* Software tracked state */
506 enum intel_ring_hangcheck_action hangcheck_action
;
509 /* our own tracking of ring head and tail */
514 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
533 u32 rc_psmi
; /* sleep state */
534 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
536 struct drm_i915_error_object
{
540 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
542 struct drm_i915_error_object
*wa_ctx
;
544 struct drm_i915_error_request
{
559 char comm
[TASK_COMM_LEN
];
560 } ring
[I915_NUM_ENGINES
];
562 struct drm_i915_error_buffer
{
565 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
569 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
577 } **active_bo
, **pinned_bo
;
579 u32
*active_bo_count
, *pinned_bo_count
;
583 struct intel_connector
;
584 struct intel_encoder
;
585 struct intel_crtc_state
;
586 struct intel_initial_plane_config
;
591 struct drm_i915_display_funcs
{
592 int (*get_display_clock_speed
)(struct drm_device
*dev
);
593 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
594 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
595 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
596 struct intel_crtc
*intel_crtc
,
597 struct intel_crtc_state
*newstate
);
598 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
599 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
600 void (*update_wm
)(struct drm_crtc
*crtc
);
601 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
602 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
603 /* Returns the active state of the crtc, and if the crtc is active,
604 * fills out the pipe-config with the hw state. */
605 bool (*get_pipe_config
)(struct intel_crtc
*,
606 struct intel_crtc_state
*);
607 void (*get_initial_plane_config
)(struct intel_crtc
*,
608 struct intel_initial_plane_config
*);
609 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
610 struct intel_crtc_state
*crtc_state
);
611 void (*crtc_enable
)(struct drm_crtc
*crtc
);
612 void (*crtc_disable
)(struct drm_crtc
*crtc
);
613 void (*audio_codec_enable
)(struct drm_connector
*connector
,
614 struct intel_encoder
*encoder
,
615 const struct drm_display_mode
*adjusted_mode
);
616 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
617 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
618 void (*init_clock_gating
)(struct drm_device
*dev
);
619 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
620 struct drm_framebuffer
*fb
,
621 struct drm_i915_gem_object
*obj
,
622 struct drm_i915_gem_request
*req
,
624 void (*hpd_irq_setup
)(struct drm_device
*dev
);
625 /* clock updates for mode set */
627 /* render clock increase/decrease */
628 /* display clock increase/decrease */
629 /* pll clock increase/decrease */
631 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
632 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
635 enum forcewake_domain_id
{
636 FW_DOMAIN_ID_RENDER
= 0,
637 FW_DOMAIN_ID_BLITTER
,
643 enum forcewake_domains
{
644 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
645 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
646 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
647 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
652 #define FW_REG_READ (1)
653 #define FW_REG_WRITE (2)
655 enum forcewake_domains
656 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
657 i915_reg_t reg
, unsigned int op
);
659 struct intel_uncore_funcs
{
660 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
661 enum forcewake_domains domains
);
662 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
663 enum forcewake_domains domains
);
665 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
666 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
667 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
668 u64 (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
670 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
671 uint8_t val
, bool trace
);
672 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
673 uint16_t val
, bool trace
);
674 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
675 uint32_t val
, bool trace
);
676 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
677 u64 val
, bool trace
);
680 struct intel_uncore
{
681 struct lock lock
; /** lock is also taken in irq contexts. */
683 struct intel_uncore_funcs funcs
;
686 enum forcewake_domains fw_domains
;
688 struct intel_uncore_forcewake_domain
{
689 struct drm_i915_private
*i915
;
690 enum forcewake_domain_id id
;
691 enum forcewake_domains mask
;
693 struct hrtimer timer
;
700 } fw_domain
[FW_DOMAIN_ID_COUNT
];
702 int unclaimed_mmio_check
;
705 /* Iterate over initialised fw domains */
706 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
707 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
708 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
710 for_each_if ((mask__) & (domain__)->mask)
712 #define for_each_fw_domain(domain__, dev_priv__) \
713 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
715 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
716 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
717 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
720 struct work_struct work
;
722 uint32_t *dmc_payload
;
723 uint32_t dmc_fw_size
;
726 i915_reg_t mmioaddr
[8];
727 uint32_t mmiodata
[8];
729 uint32_t allowed_dc_mask
;
732 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
733 func(is_mobile) sep \
736 func(is_i945gm) sep \
738 func(need_gfx_hws) sep \
740 func(is_pineview) sep \
741 func(is_broadwater) sep \
742 func(is_crestline) sep \
743 func(is_ivybridge) sep \
744 func(is_valleyview) sep \
745 func(is_cherryview) sep \
746 func(is_haswell) sep \
747 func(is_skylake) sep \
748 func(is_broxton) sep \
749 func(is_kabylake) sep \
750 func(is_preliminary) sep \
752 func(has_pipe_cxsr) sep \
753 func(has_hotplug) sep \
754 func(cursor_needs_physical) sep \
755 func(has_overlay) sep \
756 func(overlay_needs_physical) sep \
757 func(supports_tv) sep \
759 func(has_snoop) sep \
763 #define DEFINE_FLAG(name) u8 name:1
764 #define SEP_SEMICOLON ;
766 struct intel_device_info
{
767 u32 display_mmio_offset
;
770 u8 num_sprites
[I915_MAX_PIPES
];
772 u8 ring_mask
; /* Rings supported by the HW */
773 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
774 /* Register offsets for the various display pipes and transcoders */
775 int pipe_offsets
[I915_MAX_TRANSCODERS
];
776 int trans_offsets
[I915_MAX_TRANSCODERS
];
777 int palette_offsets
[I915_MAX_PIPES
];
778 int cursor_offsets
[I915_MAX_PIPES
];
780 /* Slice/subslice/EU info */
783 u8 subslice_per_slice
;
786 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
789 u8 has_subslice_pg
:1;
793 u16 degamma_lut_size
;
801 enum i915_cache_level
{
803 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
804 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
805 caches, eg sampler/render caches, and the
806 large Last-Level-Cache. LLC is coherent with
807 the CPU, but L3 is only visible to the GPU. */
808 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
811 struct i915_ctx_hang_stats
{
812 /* This context had batch pending when hang was declared */
813 unsigned batch_pending
;
815 /* This context had batch active when hang was declared */
816 unsigned batch_active
;
818 /* Time when this context was last blamed for a GPU reset */
819 unsigned long guilty_ts
;
821 /* If the contexts causes a second GPU hang within this time,
822 * it is permanently banned from submitting any more work.
824 unsigned long ban_period_seconds
;
826 /* This context is banned to submit more work */
830 /* This must match up with the value previously used for execbuf2.rsvd1. */
831 #define DEFAULT_CONTEXT_HANDLE 0
833 #define CONTEXT_NO_ZEROMAP (1<<0)
835 * struct intel_context - as the name implies, represents a context.
836 * @ref: reference count.
837 * @user_handle: userspace tracking identity for this context.
838 * @remap_slice: l3 row remapping information.
839 * @flags: context specific flags:
840 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
841 * @file_priv: filp associated with this context (NULL for global default
843 * @hang_stats: information about the role of this context in possible GPU
845 * @ppgtt: virtual memory space used by this context.
846 * @legacy_hw_ctx: render context backing object and whether it is correctly
847 * initialized (legacy ring submission mechanism only).
848 * @link: link in the global list of contexts.
850 * Contexts are memory images used by the hardware to store copies of their
853 struct intel_context
{
857 struct drm_i915_private
*i915
;
859 struct drm_i915_file_private
*file_priv
;
860 struct i915_ctx_hang_stats hang_stats
;
861 struct i915_hw_ppgtt
*ppgtt
;
863 /* Legacy ring buffer submission */
865 struct drm_i915_gem_object
*rcs_state
;
871 struct drm_i915_gem_object
*state
;
872 struct intel_ringbuffer
*ringbuf
;
874 struct i915_vma
*lrc_vma
;
876 uint32_t *lrc_reg_state
;
877 } engine
[I915_NUM_ENGINES
];
879 struct list_head link
;
891 /* This is always the inner lock when overlapping with struct_mutex and
892 * it's the outer lock when overlapping with stolen_lock. */
895 unsigned int possible_framebuffer_bits
;
896 unsigned int busy_bits
;
897 unsigned int visible_pipes_mask
;
898 struct intel_crtc
*crtc
;
900 struct drm_mm_node compressed_fb
;
901 struct drm_mm_node
*compressed_llb
;
908 struct intel_fbc_state_cache
{
910 unsigned int mode_flags
;
911 uint32_t hsw_bdw_pixel_rate
;
915 unsigned int rotation
;
923 uint32_t pixel_format
;
926 unsigned int tiling_mode
;
930 struct intel_fbc_reg_params
{
934 unsigned int fence_y_offset
;
939 uint32_t pixel_format
;
947 struct intel_fbc_work
{
949 u32 scheduled_vblank
;
950 struct work_struct work
;
953 const char *no_fbc_reason
;
957 * HIGH_RR is the highest eDP panel refresh rate read from EDID
958 * LOW_RR is the lowest eDP panel refresh rate found from EDID
959 * parsing for same resolution.
961 enum drrs_refresh_rate_type
{
964 DRRS_MAX_RR
, /* RR count */
967 enum drrs_support_type
{
968 DRRS_NOT_SUPPORTED
= 0,
969 STATIC_DRRS_SUPPORT
= 1,
970 SEAMLESS_DRRS_SUPPORT
= 2
976 struct delayed_work work
;
978 unsigned busy_frontbuffer_bits
;
979 enum drrs_refresh_rate_type refresh_rate_type
;
980 enum drrs_support_type type
;
987 struct intel_dp
*enabled
;
989 struct delayed_work work
;
990 unsigned busy_frontbuffer_bits
;
997 PCH_NONE
= 0, /* No PCH present */
998 PCH_IBX
, /* Ibexpeak PCH */
999 PCH_CPT
, /* Cougarpoint PCH */
1000 PCH_LPT
, /* Lynxpoint PCH */
1001 PCH_SPT
, /* Sunrisepoint PCH */
1002 PCH_KBP
, /* Kabypoint PCH */
1006 enum intel_sbi_destination
{
1011 #define QUIRK_PIPEA_FORCE (1<<0)
1012 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1013 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1014 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1015 #define QUIRK_PIPEB_FORCE (1<<4)
1016 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1019 struct intel_fbc_work
;
1021 struct intel_gmbus
{
1022 struct i2c_adapter adapter
;
1023 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1026 i915_reg_t gpio_reg
;
1027 struct i2c_algo_bit_data bit_algo
;
1028 struct drm_i915_private
*dev_priv
;
1031 struct i915_suspend_saved_registers
{
1034 u32 savePP_ON_DELAYS
;
1035 u32 savePP_OFF_DELAYS
;
1040 u32 saveFBC_CONTROL
;
1041 u32 saveCACHE_MODE_0
;
1042 u32 saveMI_ARB_STATE
;
1046 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1047 u32 savePCH_PORT_HOTPLUG
;
1051 struct vlv_s0ix_state
{
1058 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1059 u32 media_max_req_count
;
1060 u32 gfx_max_req_count
;
1086 u32 rp_down_timeout
;
1092 /* Display 1 CZ domain */
1097 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1099 /* GT SA CZ domain */
1106 /* Display 2 CZ domain */
1110 u32 clock_gate_dis2
;
1113 struct intel_rps_ei
{
1119 struct intel_gen6_power_mgmt
{
1121 * work, interrupts_enabled and pm_iir are protected by
1122 * dev_priv->irq_lock
1124 struct work_struct work
;
1125 bool interrupts_enabled
;
1128 /* Frequencies are stored in potentially platform dependent multiples.
1129 * In other words, *_freq needs to be multiplied by X to be interesting.
1130 * Soft limits are those which are used for the dynamic reclocking done
1131 * by the driver (raise frequencies under heavy loads, and lower for
1132 * lighter loads). Hard limits are those imposed by the hardware.
1134 * A distinction is made for overclocking, which is never enabled by
1135 * default, and is considered to be above the hard limit if it's
1138 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1139 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1140 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1141 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1142 u8 min_freq
; /* AKA RPn. Minimum frequency */
1143 u8 idle_freq
; /* Frequency to request when we are idle */
1144 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1145 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1146 u8 rp0_freq
; /* Non-overclocked max frequency. */
1147 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1149 u8 up_threshold
; /* Current %busy required to uplock */
1150 u8 down_threshold
; /* Current %busy required to downclock */
1153 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1155 struct lock client_lock
;
1156 struct list_head clients
;
1160 struct delayed_work delayed_resume_work
;
1163 struct intel_rps_client semaphores
, mmioflips
;
1165 /* manual wa residency calculations */
1166 struct intel_rps_ei up_ei
, down_ei
;
1169 * Protects RPS/RC6 register access and PCU communication.
1170 * Must be taken after struct_mutex if nested. Note that
1171 * this lock may be held for long periods of time when
1172 * talking to hw - so only take it when talking to hw!
1174 struct lock hw_lock
;
1177 /* defined intel_pm.c */
1178 extern struct lock mchdev_lock
;
1180 struct intel_ilk_power_mgmt
{
1188 unsigned long last_time1
;
1189 unsigned long chipset_power
;
1192 unsigned long gfx_power
;
1199 struct drm_i915_private
;
1200 struct i915_power_well
;
1202 struct i915_power_well_ops
{
1204 * Synchronize the well's hw state to match the current sw state, for
1205 * example enable/disable it based on the current refcount. Called
1206 * during driver init and resume time, possibly after first calling
1207 * the enable/disable handlers.
1209 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1210 struct i915_power_well
*power_well
);
1212 * Enable the well and resources that depend on it (for example
1213 * interrupts located on the well). Called after the 0->1 refcount
1216 void (*enable
)(struct drm_i915_private
*dev_priv
,
1217 struct i915_power_well
*power_well
);
1219 * Disable the well and resources that depend on it. Called after
1220 * the 1->0 refcount transition.
1222 void (*disable
)(struct drm_i915_private
*dev_priv
,
1223 struct i915_power_well
*power_well
);
1224 /* Returns the hw enabled state. */
1225 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1226 struct i915_power_well
*power_well
);
1229 /* Power well structure for haswell */
1230 struct i915_power_well
{
1233 /* power well enable/disable usage count */
1235 /* cached hw enabled state */
1237 unsigned long domains
;
1239 const struct i915_power_well_ops
*ops
;
1242 struct i915_power_domains
{
1244 * Power wells needed for initialization at driver init and suspend
1245 * time are on. They are kept on until after the first modeset.
1249 int power_well_count
;
1252 int domain_use_count
[POWER_DOMAIN_NUM
];
1253 struct i915_power_well
*power_wells
;
1256 #define MAX_L3_SLICES 2
1257 struct intel_l3_parity
{
1258 u32
*remap_info
[MAX_L3_SLICES
];
1259 struct work_struct error_work
;
1263 struct i915_gem_mm
{
1264 /** Memory allocator for GTT stolen memory */
1265 struct drm_mm stolen
;
1266 /** Protects the usage of the GTT stolen memory allocator. This is
1267 * always the inner lock when overlapping with struct_mutex. */
1268 struct lock stolen_lock
;
1270 /** List of all objects in gtt_space. Used to restore gtt
1271 * mappings on resume */
1272 struct list_head bound_list
;
1274 * List of objects which are not bound to the GTT (thus
1275 * are idle and not used by the GPU) but still have
1276 * (presumably uncached) pages still attached.
1278 struct list_head unbound_list
;
1280 /** Usable portion of the GTT for GEM */
1281 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1283 /** PPGTT used for aliasing the PPGTT with the GTT */
1284 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1286 struct notifier_block oom_notifier
;
1287 struct notifier_block vmap_notifier
;
1289 struct shrinker shrinker
;
1291 bool shrinker_no_lock_stealing
;
1293 /** LRU list of objects with fence regs on them. */
1294 struct list_head fence_list
;
1297 * We leave the user IRQ off as much as possible,
1298 * but this means that requests will finish and never
1299 * be retired once the system goes idle. Set a timer to
1300 * fire periodically while the ring is running. When it
1301 * fires, go retire requests.
1303 struct delayed_work retire_work
;
1306 * When we detect an idle GPU, we want to turn on
1307 * powersaving features. So once we see that there
1308 * are no more requests outstanding and no more
1309 * arrive within a small period of time, we fire
1310 * off the idle_work.
1312 struct delayed_work idle_work
;
1315 * Are we in a non-interruptible section of code like
1321 * Is the GPU currently considered idle, or busy executing userspace
1322 * requests? Whilst idle, we attempt to power down the hardware and
1323 * display clocks. In order to reduce the effect on performance, there
1324 * is a slight delay before we do so.
1328 /* the indicator for dispatch video commands on two BSD rings */
1329 unsigned int bsd_ring_dispatch_index
;
1331 /** Bit 6 swizzling required for X tiling */
1332 uint32_t bit_6_swizzle_x
;
1333 /** Bit 6 swizzling required for Y tiling */
1334 uint32_t bit_6_swizzle_y
;
1336 /* accounting, useful for userland debugging */
1337 struct spinlock object_stat_lock
;
1338 size_t object_memory
;
1342 struct drm_i915_error_state_buf
{
1343 struct drm_i915_private
*i915
;
1352 struct i915_error_state_file_priv
{
1353 struct drm_device
*dev
;
1354 struct drm_i915_error_state
*error
;
1357 struct i915_gpu_error
{
1358 /* For hangcheck timer */
1359 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1360 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1361 /* Hang gpu twice in this window and your context gets banned */
1362 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1364 struct workqueue_struct
*hangcheck_wq
;
1365 struct delayed_work hangcheck_work
;
1367 /* For reset and error_state handling. */
1369 /* Protected by the above dev->gpu_error.lock. */
1370 struct drm_i915_error_state
*first_error
;
1372 unsigned long missed_irq_rings
;
1375 * State variable controlling the reset flow and count
1377 * This is a counter which gets incremented when reset is triggered,
1378 * and again when reset has been handled. So odd values (lowest bit set)
1379 * means that reset is in progress and even values that
1380 * (reset_counter >> 1):th reset was successfully completed.
1382 * If reset is not completed succesfully, the I915_WEDGE bit is
1383 * set meaning that hardware is terminally sour and there is no
1384 * recovery. All waiters on the reset_queue will be woken when
1387 * This counter is used by the wait_seqno code to notice that reset
1388 * event happened and it needs to restart the entire ioctl (since most
1389 * likely the seqno it waited for won't ever signal anytime soon).
1391 * This is important for lock-free wait paths, where no contended lock
1392 * naturally enforces the correct ordering between the bail-out of the
1393 * waiter and the gpu reset work code.
1395 atomic_t reset_counter
;
1397 #define I915_RESET_IN_PROGRESS_FLAG 1
1398 #define I915_WEDGED (1 << 31)
1401 * Waitqueue to signal when the reset has completed. Used by clients
1402 * that wait for dev_priv->mm.wedged to settle.
1404 wait_queue_head_t reset_queue
;
1406 /* Userspace knobs for gpu hang simulation;
1407 * combines both a ring mask, and extra flags
1410 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1411 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1413 /* For missed irq/seqno simulation. */
1414 unsigned int test_irq_rings
;
1417 enum modeset_restore
{
1418 MODESET_ON_LID_OPEN
,
1423 #define DP_AUX_A 0x40
1424 #define DP_AUX_B 0x10
1425 #define DP_AUX_C 0x20
1426 #define DP_AUX_D 0x30
1428 #define DDC_PIN_B 0x05
1429 #define DDC_PIN_C 0x04
1430 #define DDC_PIN_D 0x06
1432 struct ddi_vbt_port_info
{
1434 * This is an index in the HDMI/DVI DDI buffer translation table.
1435 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1436 * populate this field.
1438 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1439 uint8_t hdmi_level_shift
;
1441 uint8_t supports_dvi
:1;
1442 uint8_t supports_hdmi
:1;
1443 uint8_t supports_dp
:1;
1445 uint8_t alternate_aux_channel
;
1446 uint8_t alternate_ddc_pin
;
1448 uint8_t dp_boost_level
;
1449 uint8_t hdmi_boost_level
;
1452 enum psr_lines_to_wait
{
1453 PSR_0_LINES_TO_WAIT
= 0,
1455 PSR_4_LINES_TO_WAIT
,
1459 struct intel_vbt_data
{
1460 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1461 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1464 unsigned int int_tv_support
:1;
1465 unsigned int lvds_dither
:1;
1466 unsigned int lvds_vbt
:1;
1467 unsigned int int_crt_support
:1;
1468 unsigned int lvds_use_ssc
:1;
1469 unsigned int display_clock_mode
:1;
1470 unsigned int fdi_rx_polarity_inverted
:1;
1471 unsigned int panel_type
:4;
1473 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1475 enum drrs_support_type drrs_type
;
1486 struct edp_power_seq pps
;
1491 bool require_aux_wakeup
;
1493 enum psr_lines_to_wait lines_to_wait
;
1494 int tp1_wakeup_time
;
1495 int tp2_tp3_wakeup_time
;
1501 bool active_low_pwm
;
1502 u8 min_brightness
; /* min_brightness/255 of max */
1508 struct mipi_config
*config
;
1509 struct mipi_pps_data
*pps
;
1513 const u8
*sequence
[MIPI_SEQ_MAX
];
1519 union child_device_config
*child_dev
;
1521 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1522 struct sdvo_device_mapping sdvo_mappings
[2];
1525 enum intel_ddb_partitioning
{
1527 INTEL_DDB_PART_5_6
, /* IVB+ */
1530 struct intel_wm_level
{
1538 struct ilk_wm_values
{
1539 uint32_t wm_pipe
[3];
1541 uint32_t wm_lp_spr
[3];
1542 uint32_t wm_linetime
[3];
1544 enum intel_ddb_partitioning partitioning
;
1547 struct vlv_pipe_wm
{
1558 struct vlv_wm_values
{
1559 struct vlv_pipe_wm pipe
[3];
1560 struct vlv_sr_wm sr
;
1570 struct skl_ddb_entry
{
1571 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1574 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1576 return entry
->end
- entry
->start
;
1579 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1580 const struct skl_ddb_entry
*e2
)
1582 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1588 struct skl_ddb_allocation
{
1589 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1590 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1591 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1594 struct skl_wm_values
{
1595 bool dirty
[I915_MAX_PIPES
];
1596 struct skl_ddb_allocation ddb
;
1597 uint32_t wm_linetime
[I915_MAX_PIPES
];
1598 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1599 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1602 struct skl_wm_level
{
1603 bool plane_en
[I915_MAX_PLANES
];
1604 uint16_t plane_res_b
[I915_MAX_PLANES
];
1605 uint8_t plane_res_l
[I915_MAX_PLANES
];
1609 * This struct helps tracking the state needed for runtime PM, which puts the
1610 * device in PCI D3 state. Notice that when this happens, nothing on the
1611 * graphics device works, even register access, so we don't get interrupts nor
1614 * Every piece of our code that needs to actually touch the hardware needs to
1615 * either call intel_runtime_pm_get or call intel_display_power_get with the
1616 * appropriate power domain.
1618 * Our driver uses the autosuspend delay feature, which means we'll only really
1619 * suspend if we stay with zero refcount for a certain amount of time. The
1620 * default value is currently very conservative (see intel_runtime_pm_enable), but
1621 * it can be changed with the standard runtime PM files from sysfs.
1623 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1624 * goes back to false exactly before we reenable the IRQs. We use this variable
1625 * to check if someone is trying to enable/disable IRQs while they're supposed
1626 * to be disabled. This shouldn't happen and we'll print some error messages in
1629 * For more, read the Documentation/power/runtime_pm.txt.
1631 struct i915_runtime_pm
{
1632 atomic_t wakeref_count
;
1633 atomic_t atomic_seq
;
1638 enum intel_pipe_crc_source
{
1639 INTEL_PIPE_CRC_SOURCE_NONE
,
1640 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1641 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1642 INTEL_PIPE_CRC_SOURCE_PF
,
1643 INTEL_PIPE_CRC_SOURCE_PIPE
,
1644 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1645 INTEL_PIPE_CRC_SOURCE_TV
,
1646 INTEL_PIPE_CRC_SOURCE_DP_B
,
1647 INTEL_PIPE_CRC_SOURCE_DP_C
,
1648 INTEL_PIPE_CRC_SOURCE_DP_D
,
1649 INTEL_PIPE_CRC_SOURCE_AUTO
,
1650 INTEL_PIPE_CRC_SOURCE_MAX
,
1653 struct intel_pipe_crc_entry
{
1658 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1659 struct intel_pipe_crc
{
1660 struct spinlock lock
;
1661 bool opened
; /* exclusive access to the result file */
1662 struct intel_pipe_crc_entry
*entries
;
1663 enum intel_pipe_crc_source source
;
1665 wait_queue_head_t wq
;
1668 struct i915_frontbuffer_tracking
{
1672 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1679 struct i915_wa_reg
{
1682 /* bitmask representing WA bits */
1687 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1688 * allowing it for RCS as we don't foresee any requirement of having
1689 * a whitelist for other engines. When it is really required for
1690 * other engines then the limit need to be increased.
1692 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1694 struct i915_workarounds
{
1695 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1697 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1700 struct i915_virtual_gpu
{
1704 struct i915_execbuffer_params
{
1705 struct drm_device
*dev
;
1706 struct drm_file
*file
;
1707 uint32_t dispatch_flags
;
1708 uint32_t args_batch_start_offset
;
1709 uint64_t batch_obj_vm_offset
;
1710 struct intel_engine_cs
*engine
;
1711 struct drm_i915_gem_object
*batch_obj
;
1712 struct intel_context
*ctx
;
1713 struct drm_i915_gem_request
*request
;
1716 /* used in computing the new watermarks state */
1717 struct intel_wm_config
{
1718 unsigned int num_pipes_active
;
1719 bool sprites_enabled
;
1720 bool sprites_scaled
;
1723 struct drm_i915_private
{
1724 struct drm_device
*dev
;
1725 struct kmem_cache
*objects
;
1726 struct kmem_cache
*vmas
;
1727 struct kmem_cache
*requests
;
1729 struct intel_device_info info
;
1731 int relative_constants_mode
;
1735 struct intel_uncore uncore
;
1737 struct i915_virtual_gpu vgpu
;
1739 struct intel_guc guc
;
1741 struct intel_csr csr
;
1743 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1745 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1746 * controller on different i2c buses. */
1747 struct lock gmbus_mutex
;
1750 * Base address of the gmbus and gpio block.
1752 uint32_t gpio_mmio_base
;
1754 /* MMIO base address for MIPI regs */
1755 uint32_t mipi_mmio_base
;
1757 uint32_t psr_mmio_base
;
1759 wait_queue_head_t gmbus_wait_queue
;
1761 struct pci_dev
*bridge_dev
;
1762 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1763 struct drm_i915_gem_object
*semaphore_obj
;
1764 uint32_t last_seqno
, next_seqno
;
1766 struct drm_dma_handle
*status_page_dmah
;
1767 struct resource
*mch_res
;
1770 /* protects the irq masks */
1771 struct lock irq_lock
;
1773 /* protects the mmio flip data */
1774 struct spinlock mmio_flip_lock
;
1776 bool display_irqs_enabled
;
1778 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1779 struct pm_qos_request pm_qos
;
1781 /* Sideband mailbox protection */
1782 struct lock sb_lock
;
1784 /** Cached value of IMR to avoid reads in updating the bitfield */
1787 u32 de_irq_mask
[I915_MAX_PIPES
];
1792 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1794 struct i915_hotplug hotplug
;
1795 struct intel_fbc fbc
;
1796 struct i915_drrs drrs
;
1797 struct intel_opregion opregion
;
1798 struct intel_vbt_data vbt
;
1800 bool preserve_bios_swizzle
;
1803 struct intel_overlay
*overlay
;
1805 /* backlight registers and fields in struct intel_panel */
1806 struct lock backlight_lock
;
1809 bool no_aux_handshake
;
1811 /* protects panel power sequencer state */
1812 struct lock pps_mutex
;
1814 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1815 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1817 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1818 unsigned int skl_boot_cdclk
;
1819 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1820 unsigned int max_dotclk_freq
;
1821 unsigned int rawclk_freq
;
1822 unsigned int hpll_freq
;
1823 unsigned int czclk_freq
;
1826 * wq - Driver workqueue for GEM.
1828 * NOTE: Work items scheduled here are not allowed to grab any modeset
1829 * locks, for otherwise the flushing done in the pageflip code will
1830 * result in deadlocks.
1832 struct workqueue_struct
*wq
;
1834 /* Display functions */
1835 struct drm_i915_display_funcs display
;
1837 /* PCH chipset type */
1838 enum intel_pch pch_type
;
1839 unsigned short pch_id
;
1841 unsigned long quirks
;
1843 enum modeset_restore modeset_restore
;
1844 struct lock modeset_restore_lock
;
1845 struct drm_atomic_state
*modeset_restore_state
;
1847 struct list_head vm_list
; /* Global list of all address spaces */
1848 struct i915_ggtt ggtt
; /* VM representing the global address space */
1850 struct i915_gem_mm mm
;
1851 DECLARE_HASHTABLE(mm_structs
, 7);
1852 struct lock mm_lock
;
1854 /* Kernel Modesetting */
1856 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1857 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1858 wait_queue_head_t pending_flip_queue
;
1860 #ifdef CONFIG_DEBUG_FS
1861 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1864 /* dpll and cdclk state is protected by connection_mutex */
1865 int num_shared_dpll
;
1866 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1867 const struct intel_dpll_mgr
*dpll_mgr
;
1870 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1871 * Must be global rather than per dpll, because on some platforms
1872 * plls share registers.
1874 struct lock dpll_lock
;
1876 unsigned int active_crtcs
;
1877 unsigned int min_pixclk
[I915_MAX_PIPES
];
1879 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1881 struct i915_workarounds workarounds
;
1883 struct i915_frontbuffer_tracking fb_tracking
;
1887 bool mchbar_need_disable
;
1889 struct intel_l3_parity l3_parity
;
1891 /* Cannot be determined by PCIID. You must always read a register. */
1894 /* gen6+ rps state */
1895 struct intel_gen6_power_mgmt rps
;
1897 /* ilk-only ips/rps state. Everything in here is protected by the global
1898 * mchdev_lock in intel_pm.c */
1899 struct intel_ilk_power_mgmt ips
;
1901 struct i915_power_domains power_domains
;
1903 struct i915_psr psr
;
1905 struct i915_gpu_error gpu_error
;
1907 struct drm_i915_gem_object
*vlv_pctx
;
1909 #ifdef CONFIG_DRM_FBDEV_EMULATION
1910 /* list of fbdev register on this device */
1911 struct intel_fbdev
*fbdev
;
1912 struct work_struct fbdev_suspend_work
;
1915 struct drm_property
*broadcast_rgb_property
;
1916 struct drm_property
*force_audio_property
;
1918 /* hda/i915 audio component */
1919 struct i915_audio_component
*audio_component
;
1920 bool audio_component_registered
;
1922 * av_mutex - mutex for audio/video sync
1925 struct lock av_mutex
;
1927 uint32_t hw_context_size
;
1928 struct list_head context_list
;
1932 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1933 u32 chv_phy_control
;
1935 * Shadows for CHV DPLL_MD regs to keep the state
1936 * checker somewhat working in the presence hardware
1937 * crappiness (can't read out DPLL_MD for pipes B & C).
1939 u32 chv_dpll_md
[I915_MAX_PIPES
];
1943 bool suspended_to_idle
;
1944 struct i915_suspend_saved_registers regfile
;
1945 struct vlv_s0ix_state vlv_s0ix_state
;
1949 * Raw watermark latency values:
1950 * in 0.1us units for WM0,
1951 * in 0.5us units for WM1+.
1954 uint16_t pri_latency
[5];
1956 uint16_t spr_latency
[5];
1958 uint16_t cur_latency
[5];
1960 * Raw watermark memory latency values
1961 * for SKL for all 8 levels
1964 uint16_t skl_latency
[8];
1966 /* Committed wm config */
1967 struct intel_wm_config config
;
1970 * The skl_wm_values structure is a bit too big for stack
1971 * allocation, so we keep the staging struct where we store
1972 * intermediate results here instead.
1974 struct skl_wm_values skl_results
;
1976 /* current hardware state */
1978 struct ilk_wm_values hw
;
1979 struct skl_wm_values skl_hw
;
1980 struct vlv_wm_values vlv
;
1986 * Should be held around atomic WM register writing; also
1987 * protects * intel_crtc->wm.active and
1988 * cstate->wm.need_postvbl_update.
1990 struct lock wm_mutex
;
1993 struct i915_runtime_pm pm
;
1995 uint32_t bios_vgacntr
;
1997 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1999 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
2000 struct drm_i915_gem_execbuffer2
*args
,
2001 struct list_head
*vmas
);
2002 int (*init_engines
)(struct drm_device
*dev
);
2003 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2004 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2007 struct intel_context
*kernel_context
;
2009 /* perform PHY state sanity checks? */
2010 bool chv_phy_assert
[2];
2012 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2015 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2016 * will be rejected. Instead look for a better place.
2020 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2022 return dev
->dev_private
;
2025 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2027 return to_i915(device_get_softc(dev
->bsddev
));
2030 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2032 return container_of(guc
, struct drm_i915_private
, guc
);
2035 /* Simple iterator over all initialised engines */
2036 #define for_each_engine(engine__, dev_priv__) \
2037 for ((engine__) = &(dev_priv__)->engine[0]; \
2038 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2040 for_each_if (intel_engine_initialized(engine__))
2042 /* Iterator with engine_id */
2043 #define for_each_engine_id(engine__, dev_priv__, id__) \
2044 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2045 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2047 for_each_if (((id__) = (engine__)->id, \
2048 intel_engine_initialized(engine__)))
2050 /* Iterator over subset of engines selected by mask */
2051 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2052 for ((engine__) = &(dev_priv__)->engine[0]; \
2053 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2055 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2056 intel_engine_initialized(engine__))
2058 enum hdmi_force_audio
{
2059 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2060 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2061 HDMI_AUDIO_AUTO
, /* trust EDID */
2062 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2065 #define I915_GTT_OFFSET_NONE ((u32)-1)
2067 struct drm_i915_gem_object_ops
{
2069 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2071 /* Interface between the GEM object and its backing storage.
2072 * get_pages() is called once prior to the use of the associated set
2073 * of pages before to binding them into the GTT, and put_pages() is
2074 * called after we no longer need them. As we expect there to be
2075 * associated cost with migrating pages between the backing storage
2076 * and making them available for the GPU (e.g. clflush), we may hold
2077 * onto the pages after they are no longer referenced by the GPU
2078 * in case they may be used again shortly (for example migrating the
2079 * pages to a different memory domain within the GTT). put_pages()
2080 * will therefore most likely be called when the object itself is
2081 * being released or under memory pressure (where we attempt to
2082 * reap pages for the shrinker).
2084 int (*get_pages
)(struct drm_i915_gem_object
*);
2085 void (*put_pages
)(struct drm_i915_gem_object
*);
2087 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2088 void (*release
)(struct drm_i915_gem_object
*);
2092 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2093 * considered to be the frontbuffer for the given plane interface-wise. This
2094 * doesn't mean that the hw necessarily already scans it out, but that any
2095 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2097 * We have one bit per pipe and per scanout plane type.
2099 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2100 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2101 #define INTEL_FRONTBUFFER_BITS \
2102 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2103 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2104 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2105 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2106 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2107 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2108 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2109 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2110 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2111 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2112 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2114 struct drm_i915_gem_object
{
2115 struct drm_gem_object base
;
2117 const struct drm_i915_gem_object_ops
*ops
;
2119 /** List of VMAs backed by this object */
2120 struct list_head vma_list
;
2122 /** Stolen memory for this object, instead of being backed by shmem. */
2123 struct drm_mm_node
*stolen
;
2124 struct list_head global_list
;
2126 struct list_head engine_list
[I915_NUM_ENGINES
];
2127 /** Used in execbuf to temporarily hold a ref */
2128 struct list_head obj_exec_link
;
2130 struct list_head batch_pool_link
;
2133 * This is set if the object is on the active lists (has pending
2134 * rendering and so a non-zero seqno), and is not set if it i s on
2135 * inactive (ready to be unbound) list.
2137 unsigned int active
:I915_NUM_ENGINES
;
2140 * This is set if the object has been written to since last bound
2143 unsigned int dirty
:1;
2146 * Fence register bits (if any) for this object. Will be set
2147 * as needed when mapped into the GTT.
2148 * Protected by dev->struct_mutex.
2150 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2153 * Advice: are the backing pages purgeable?
2155 unsigned int madv
:2;
2158 * Current tiling mode for the object.
2160 unsigned int tiling_mode
:2;
2162 * Whether the tiling parameters for the currently associated fence
2163 * register have changed. Note that for the purposes of tracking
2164 * tiling changes we also treat the unfenced register, the register
2165 * slot that the object occupies whilst it executes a fenced
2166 * command (such as BLT on gen2/3), as a "fence".
2168 unsigned int fence_dirty
:1;
2171 * Is the object at the current location in the gtt mappable and
2172 * fenceable? Used to avoid costly recalculations.
2174 unsigned int map_and_fenceable
:1;
2177 * Whether the current gtt mapping needs to be mappable (and isn't just
2178 * mappable by accident). Track pin and fault separate for a more
2179 * accurate mappable working set.
2181 unsigned int fault_mappable
:1;
2184 * Is the object to be mapped as read-only to the GPU
2185 * Only honoured if hardware has relevant pte bit
2187 unsigned long gt_ro
:1;
2188 unsigned int cache_level
:3;
2189 unsigned int cache_dirty
:1;
2191 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2193 unsigned int pin_display
;
2195 struct sg_table
*pages
;
2196 int pages_pin_count
;
2198 struct scatterlist
*sg
;
2203 /** Breadcrumb of last rendering to the buffer.
2204 * There can only be one writer, but we allow for multiple readers.
2205 * If there is a writer that necessarily implies that all other
2206 * read requests are complete - but we may only be lazily clearing
2207 * the read requests. A read request is naturally the most recent
2208 * request on a ring, so we may have two different write and read
2209 * requests on one ring where the write request is older than the
2210 * read request. This allows for the CPU to read from an active
2211 * buffer by only waiting for the write to complete.
2213 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2214 struct drm_i915_gem_request
*last_write_req
;
2215 /** Breadcrumb of last fenced GPU access to the buffer. */
2216 struct drm_i915_gem_request
*last_fenced_req
;
2218 /** Current tiling stride for the object, if it's tiled. */
2221 /** References from framebuffers, locks out tiling changes. */
2222 unsigned long framebuffer_references
;
2224 /** Record of address bit 17 of each page at last unbind. */
2225 unsigned long *bit_17
;
2228 /** for phy allocated objects */
2229 struct drm_dma_handle
*phys_handle
;
2231 struct i915_gem_userptr
{
2233 unsigned read_only
:1;
2234 unsigned workers
:4;
2235 #define I915_GEM_USERPTR_MAX_WORKERS 15
2237 struct i915_mm_struct
*mm
;
2238 struct i915_mmu_object
*mmu_object
;
2239 struct work_struct
*work
;
2243 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2245 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2246 struct drm_i915_gem_object
*new,
2247 unsigned frontbuffer_bits
);
2250 * Request queue structure.
2252 * The request queue allows us to note sequence numbers that have been emitted
2253 * and may be associated with active buffers to be retired.
2255 * By keeping this list, we can avoid having to do questionable sequence
2256 * number comparisons on buffer last_read|write_seqno. It also allows an
2257 * emission time to be associated with the request for tracking how far ahead
2258 * of the GPU the submission is.
2260 * The requests are reference counted, so upon creation they should have an
2261 * initial reference taken using kref_init
2263 struct drm_i915_gem_request
{
2266 /** On Which ring this request was generated */
2267 struct drm_i915_private
*i915
;
2268 struct intel_engine_cs
*engine
;
2269 unsigned reset_counter
;
2271 /** GEM sequence number associated with the previous request,
2272 * when the HWS breadcrumb is equal to this the GPU is processing
2277 /** GEM sequence number associated with this request,
2278 * when the HWS breadcrumb is equal or greater than this the GPU
2279 * has finished processing this request.
2283 /** Position in the ringbuffer of the start of the request */
2287 * Position in the ringbuffer of the start of the postfix.
2288 * This is required to calculate the maximum available ringbuffer
2289 * space without overwriting the postfix.
2293 /** Position in the ringbuffer of the end of the whole request */
2297 * Context and ring buffer related to this request
2298 * Contexts are refcounted, so when this request is associated with a
2299 * context, we must increment the context's refcount, to guarantee that
2300 * it persists while any request is linked to it. Requests themselves
2301 * are also refcounted, so the request will only be freed when the last
2302 * reference to it is dismissed, and the code in
2303 * i915_gem_request_free() will then decrement the refcount on the
2306 struct intel_context
*ctx
;
2307 struct intel_ringbuffer
*ringbuf
;
2309 /** Batch buffer related to this request if any (used for
2310 error state dump only) */
2311 struct drm_i915_gem_object
*batch_obj
;
2313 /** Time at which this request was emitted, in jiffies. */
2314 unsigned long emitted_jiffies
;
2316 /** global list entry for this request */
2317 struct list_head list
;
2319 struct drm_i915_file_private
*file_priv
;
2320 /** file_priv list entry for this request */
2321 struct list_head client_list
;
2323 /** process identifier submitting this request */
2327 * The ELSP only accepts two elements at a time, so we queue
2328 * context/tail pairs on a given queue (ring->execlist_queue) until the
2329 * hardware is available. The queue serves a double purpose: we also use
2330 * it to keep track of the up to 2 contexts currently in the hardware
2331 * (usually one in execution and the other queued up by the GPU): We
2332 * only remove elements from the head of the queue when the hardware
2333 * informs us that an element has been completed.
2335 * All accesses to the queue are mediated by a spinlock
2336 * (ring->execlist_lock).
2339 /** Execlist link in the submission queue.*/
2340 struct list_head execlist_link
;
2342 /** Execlists no. of times this request has been sent to the ELSP */
2347 struct drm_i915_gem_request
* __must_check
2348 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2349 struct intel_context
*ctx
);
2350 void i915_gem_request_free(struct kref
*req_ref
);
2351 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2352 struct drm_file
*file
);
2354 static inline uint32_t
2355 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2357 return req
? req
->seqno
: 0;
2360 static inline struct intel_engine_cs
*
2361 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2363 return req
? req
->engine
: NULL
;
2366 static inline struct drm_i915_gem_request
*
2367 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2370 kref_get(&req
->ref
);
2375 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2377 WARN_ON(!mutex_is_locked(&req
->engine
->dev
->struct_mutex
));
2378 kref_put(&req
->ref
, i915_gem_request_free
);
2382 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2384 struct drm_device
*dev
;
2389 dev
= req
->engine
->dev
;
2390 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2391 mutex_unlock(&dev
->struct_mutex
);
2394 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2395 struct drm_i915_gem_request
*src
)
2398 i915_gem_request_reference(src
);
2401 i915_gem_request_unreference(*pdst
);
2407 * XXX: i915_gem_request_completed should be here but currently needs the
2408 * definition of i915_seqno_passed() which is below. It will be moved in
2409 * a later patch when the call to i915_seqno_passed() is obsoleted...
2413 * A command that requires special handling by the command parser.
2415 struct drm_i915_cmd_descriptor
{
2417 * Flags describing how the command parser processes the command.
2419 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2420 * a length mask if not set
2421 * CMD_DESC_SKIP: The command is allowed but does not follow the
2422 * standard length encoding for the opcode range in
2424 * CMD_DESC_REJECT: The command is never allowed
2425 * CMD_DESC_REGISTER: The command should be checked against the
2426 * register whitelist for the appropriate ring
2427 * CMD_DESC_MASTER: The command is allowed if the submitting process
2431 #define CMD_DESC_FIXED (1<<0)
2432 #define CMD_DESC_SKIP (1<<1)
2433 #define CMD_DESC_REJECT (1<<2)
2434 #define CMD_DESC_REGISTER (1<<3)
2435 #define CMD_DESC_BITMASK (1<<4)
2436 #define CMD_DESC_MASTER (1<<5)
2439 * The command's unique identification bits and the bitmask to get them.
2440 * This isn't strictly the opcode field as defined in the spec and may
2441 * also include type, subtype, and/or subop fields.
2449 * The command's length. The command is either fixed length (i.e. does
2450 * not include a length field) or has a length field mask. The flag
2451 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2452 * a length mask. All command entries in a command table must include
2453 * length information.
2461 * Describes where to find a register address in the command to check
2462 * against the ring's register whitelist. Only valid if flags has the
2463 * CMD_DESC_REGISTER bit set.
2465 * A non-zero step value implies that the command may access multiple
2466 * registers in sequence (e.g. LRI), in that case step gives the
2467 * distance in dwords between individual offset fields.
2475 #define MAX_CMD_DESC_BITMASKS 3
2477 * Describes command checks where a particular dword is masked and
2478 * compared against an expected value. If the command does not match
2479 * the expected value, the parser rejects it. Only valid if flags has
2480 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2483 * If the check specifies a non-zero condition_mask then the parser
2484 * only performs the check when the bits specified by condition_mask
2491 u32 condition_offset
;
2493 } bits
[MAX_CMD_DESC_BITMASKS
];
2497 * A table of commands requiring special handling by the command parser.
2499 * Each ring has an array of tables. Each table consists of an array of command
2500 * descriptors, which must be sorted with command opcodes in ascending order.
2502 struct drm_i915_cmd_table
{
2503 const struct drm_i915_cmd_descriptor
*table
;
2507 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2508 #define __I915__(p) ({ \
2509 const struct drm_i915_private *__p; \
2510 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2511 __p = (const struct drm_i915_private *)p; \
2512 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2513 __p = to_i915((const struct drm_device *)p); \
2516 #define INTEL_INFO(p) (&__I915__(p)->info)
2517 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2518 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2519 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2521 #define REVID_FOREVER 0xff
2523 * Return true if revision is in range [since,until] inclusive.
2525 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2527 #define IS_REVID(p, since, until) \
2528 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2530 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2531 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2532 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2533 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2534 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2535 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2536 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2537 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2538 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2539 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2540 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2541 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2542 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2543 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2544 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2545 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2546 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2547 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2548 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2549 INTEL_DEVID(dev) == 0x0152 || \
2550 INTEL_DEVID(dev) == 0x015a)
2551 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2552 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2553 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2554 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2555 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2556 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2557 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2558 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2559 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2560 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2561 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2562 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2563 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2564 (INTEL_DEVID(dev) & 0xf) == 0xe))
2565 /* ULX machines are also considered ULT. */
2566 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2567 (INTEL_DEVID(dev) & 0xf) == 0xe)
2568 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2569 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2570 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2571 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2572 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2573 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2574 /* ULX machines are also considered ULT. */
2575 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2576 INTEL_DEVID(dev) == 0x0A1E)
2577 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2578 INTEL_DEVID(dev) == 0x1913 || \
2579 INTEL_DEVID(dev) == 0x1916 || \
2580 INTEL_DEVID(dev) == 0x1921 || \
2581 INTEL_DEVID(dev) == 0x1926)
2582 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2583 INTEL_DEVID(dev) == 0x1915 || \
2584 INTEL_DEVID(dev) == 0x191E)
2585 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2586 INTEL_DEVID(dev) == 0x5913 || \
2587 INTEL_DEVID(dev) == 0x5916 || \
2588 INTEL_DEVID(dev) == 0x5921 || \
2589 INTEL_DEVID(dev) == 0x5926)
2590 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2591 INTEL_DEVID(dev) == 0x5915 || \
2592 INTEL_DEVID(dev) == 0x591E)
2593 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2594 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2595 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2596 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2598 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2600 #define SKL_REVID_A0 0x0
2601 #define SKL_REVID_B0 0x1
2602 #define SKL_REVID_C0 0x2
2603 #define SKL_REVID_D0 0x3
2604 #define SKL_REVID_E0 0x4
2605 #define SKL_REVID_F0 0x5
2606 #define SKL_REVID_G0 0x6
2607 #define SKL_REVID_H0 0x7
2609 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2611 #define BXT_REVID_A0 0x0
2612 #define BXT_REVID_A1 0x1
2613 #define BXT_REVID_B0 0x3
2614 #define BXT_REVID_C0 0x9
2616 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2618 #define KBL_REVID_A0 0x0
2619 #define KBL_REVID_B0 0x1
2620 #define KBL_REVID_C0 0x2
2621 #define KBL_REVID_D0 0x3
2622 #define KBL_REVID_E0 0x4
2624 #define IS_KBL_REVID(p, since, until) \
2625 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2628 * The genX designation typically refers to the render engine, so render
2629 * capability related checks should use IS_GEN, while display and other checks
2630 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2633 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2634 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2635 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2636 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2637 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2638 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2639 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2640 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2642 #define RENDER_RING (1<<RCS)
2643 #define BSD_RING (1<<VCS)
2644 #define BLT_RING (1<<BCS)
2645 #define VEBOX_RING (1<<VECS)
2646 #define BSD2_RING (1<<VCS2)
2647 #define ALL_ENGINES (~0)
2649 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2650 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2651 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2652 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2653 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2654 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2655 #define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
2656 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2658 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2660 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2661 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2662 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2663 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2664 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2666 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2667 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2669 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2670 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2672 /* WaRsDisableCoarsePowerGating:skl,bxt */
2673 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2674 IS_SKL_GT3(dev) || \
2678 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2679 * even when in MSI mode. This results in spurious interrupt warnings if the
2680 * legacy irq no. is shared with another device. The kernel then disables that
2681 * interrupt source and so prevents the other device from working properly.
2683 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2684 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2686 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2687 * rows, which changed the alignment requirements and fence programming.
2689 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2691 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2692 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2694 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2695 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2696 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2698 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2700 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2701 INTEL_INFO(dev)->gen >= 9)
2703 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2704 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2705 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2706 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2707 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2708 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2709 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2710 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2711 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2712 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2713 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2715 #define HAS_CSR(dev) (IS_GEN9(dev))
2717 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2718 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2720 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2721 INTEL_INFO(dev)->gen >= 8)
2723 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2724 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2727 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2728 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2729 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2730 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2731 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2732 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2733 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2734 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2735 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2736 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2737 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2738 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2740 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2741 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2742 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2743 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2744 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2745 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2746 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2747 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2748 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2749 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2751 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2752 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2754 /* DPF == dynamic parity feature */
2755 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2756 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2758 #define GT_FREQUENCY_MULTIPLIER 50
2759 #define GEN9_FREQ_SCALER 3
2761 #include "i915_trace.h"
2763 extern const struct drm_ioctl_desc i915_ioctls
[];
2764 extern int i915_max_ioctl
;
2766 extern int i915_suspend_switcheroo(device_t kdev
);
2767 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2771 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2772 const char *fmt
, ...);
2774 #define i915_report_error(dev_priv, fmt, ...) \
2775 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2777 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2778 extern int i915_driver_unload(struct drm_device
*);
2779 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2780 extern void i915_driver_lastclose(struct drm_device
* dev
);
2781 extern void i915_driver_preclose(struct drm_device
*dev
,
2782 struct drm_file
*file
);
2783 extern void i915_driver_postclose(struct drm_device
*dev
,
2784 struct drm_file
*file
);
2785 #ifdef CONFIG_COMPAT
2786 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2789 extern int intel_gpu_reset(struct drm_device
*dev
, u32 engine_mask
);
2790 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2791 extern int i915_reset(struct drm_device
*dev
);
2792 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2793 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2794 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2795 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2796 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2797 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2798 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2800 /* intel_hotplug.c */
2801 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2802 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2803 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2804 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2805 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2806 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2807 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2810 void i915_queue_hangcheck(struct drm_device
*dev
);
2812 void i915_handle_error(struct drm_device
*dev
, u32 engine_mask
,
2813 const char *fmt
, ...);
2815 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2816 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2817 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2819 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2820 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2821 bool restore_forcewake
);
2822 extern void intel_uncore_init(struct drm_device
*dev
);
2823 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2824 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2825 extern void intel_uncore_fini(struct drm_device
*dev
);
2826 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2827 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2828 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2829 enum forcewake_domains domains
);
2830 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2831 enum forcewake_domains domains
);
2832 /* Like above but the caller must manage the uncore.lock itself.
2833 * Must be used with I915_READ_FW and friends.
2835 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2836 enum forcewake_domains domains
);
2837 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2838 enum forcewake_domains domains
);
2839 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2841 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2842 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2844 return to_i915(dev
)->vgpu
.active
;
2848 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2852 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
,
2855 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2856 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2857 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2860 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2861 uint32_t interrupt_mask
,
2862 uint32_t enabled_irq_mask
);
2864 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2866 ilk_update_display_irq(dev_priv
, bits
, bits
);
2869 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2871 ilk_update_display_irq(dev_priv
, bits
, 0);
2873 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2874 enum i915_pipe pipe
,
2875 uint32_t interrupt_mask
,
2876 uint32_t enabled_irq_mask
);
2877 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2878 enum i915_pipe pipe
, uint32_t bits
)
2880 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2882 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2883 enum i915_pipe pipe
, uint32_t bits
)
2885 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2887 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2888 uint32_t interrupt_mask
,
2889 uint32_t enabled_irq_mask
);
2891 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2893 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2896 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2898 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2903 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2904 struct drm_file
*file_priv
);
2905 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2906 struct drm_file
*file_priv
);
2907 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2908 struct drm_file
*file_priv
);
2909 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2910 struct drm_file
*file_priv
);
2911 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2912 struct drm_file
*file_priv
);
2913 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2914 struct drm_file
*file_priv
);
2915 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2916 struct drm_file
*file_priv
);
2917 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2918 struct drm_i915_gem_request
*req
);
2919 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2920 struct drm_i915_gem_execbuffer2
*args
,
2921 struct list_head
*vmas
);
2922 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2923 struct drm_file
*file_priv
);
2924 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2925 struct drm_file
*file_priv
);
2926 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2927 struct drm_file
*file_priv
);
2928 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2929 struct drm_file
*file
);
2930 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2931 struct drm_file
*file
);
2932 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2933 struct drm_file
*file_priv
);
2934 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2935 struct drm_file
*file_priv
);
2936 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2937 struct drm_file
*file_priv
);
2938 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2939 struct drm_file
*file_priv
);
2940 int i915_gem_init_userptr(struct drm_device
*dev
);
2941 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2942 struct drm_file
*file
);
2943 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2944 struct drm_file
*file_priv
);
2945 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2946 struct drm_file
*file_priv
);
2947 void i915_gem_load_init(struct drm_device
*dev
);
2948 void i915_gem_load_cleanup(struct drm_device
*dev
);
2949 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2950 void *i915_gem_object_alloc(struct drm_device
*dev
);
2951 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2952 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2953 const struct drm_i915_gem_object_ops
*ops
);
2954 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2956 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2957 struct drm_device
*dev
, const void *data
, size_t size
);
2958 void i915_gem_free_object(struct drm_gem_object
*obj
);
2959 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2961 /* Flags used by pin/bind&friends. */
2962 #define PIN_MAPPABLE (1<<0)
2963 #define PIN_NONBLOCK (1<<1)
2964 #define PIN_GLOBAL (1<<2)
2965 #define PIN_OFFSET_BIAS (1<<3)
2966 #define PIN_USER (1<<4)
2967 #define PIN_UPDATE (1<<5)
2968 #define PIN_ZONE_4G (1<<6)
2969 #define PIN_HIGH (1<<7)
2970 #define PIN_OFFSET_FIXED (1<<8)
2971 #define PIN_OFFSET_MASK (~4095)
2973 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2974 struct i915_address_space
*vm
,
2978 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2979 const struct i915_ggtt_view
*view
,
2983 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2985 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
2986 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2988 * BEWARE: Do not use the function below unless you can _absolutely_
2989 * _guarantee_ VMA in question is _not in use_ anywhere.
2991 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2992 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2993 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2994 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2996 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2997 int *needs_clflush
);
2999 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3001 static inline int __sg_page_count(struct scatterlist
*sg
)
3003 return sg
->length
>> PAGE_SHIFT
;
3007 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3009 static inline struct page
*
3010 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3012 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3015 if (n
< obj
->get_page
.last
) {
3016 obj
->get_page
.sg
= obj
->pages
->sgl
;
3017 obj
->get_page
.last
= 0;
3020 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3021 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3023 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3024 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3028 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3031 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3033 BUG_ON(obj
->pages
== NULL
);
3034 obj
->pages_pin_count
++;
3037 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3039 BUG_ON(obj
->pages_pin_count
== 0);
3040 obj
->pages_pin_count
--;
3044 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3045 * @obj - the object to map into kernel address space
3047 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3048 * pages and then returns a contiguous mapping of the backing storage into
3049 * the kernel address space.
3051 * The caller must hold the struct_mutex, and is responsible for calling
3052 * i915_gem_object_unpin_map() when the mapping is no longer required.
3054 * Returns the pointer through which to access the mapped object, or an
3055 * ERR_PTR() on error.
3057 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3060 * i915_gem_object_unpin_map - releases an earlier mapping
3061 * @obj - the object to unmap
3063 * After pinning the object and mapping its pages, once you are finished
3064 * with your access, call i915_gem_object_unpin_map() to release the pin
3065 * upon the mapping. Once the pin count reaches zero, that mapping may be
3068 * The caller must hold the struct_mutex.
3070 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3072 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3073 i915_gem_object_unpin_pages(obj
);
3076 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3077 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3078 struct intel_engine_cs
*to
,
3079 struct drm_i915_gem_request
**to_req
);
3080 void i915_vma_move_to_active(struct i915_vma
*vma
,
3081 struct drm_i915_gem_request
*req
);
3082 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3083 struct drm_device
*dev
,
3084 struct drm_mode_create_dumb
*args
);
3085 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3086 uint32_t handle
, uint64_t *offset
);
3088 * Returns true if seq1 is later than seq2.
3091 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3093 return (int32_t)(seq1
- seq2
) >= 0;
3096 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
3097 bool lazy_coherency
)
3099 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3100 req
->engine
->irq_seqno_barrier(req
->engine
);
3101 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3102 req
->previous_seqno
);
3105 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
3106 bool lazy_coherency
)
3108 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3109 req
->engine
->irq_seqno_barrier(req
->engine
);
3110 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3114 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
3115 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3117 struct drm_i915_gem_request
*
3118 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3120 bool i915_gem_retire_requests(struct drm_device
*dev
);
3121 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3123 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3125 return atomic_read(&error
->reset_counter
);
3128 static inline bool __i915_reset_in_progress(u32 reset
)
3130 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3133 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3135 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3138 static inline bool __i915_terminally_wedged(u32 reset
)
3140 return unlikely(reset
& I915_WEDGED
);
3143 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3145 return __i915_reset_in_progress(i915_reset_counter(error
));
3148 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3150 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3153 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3155 return __i915_terminally_wedged(i915_reset_counter(error
));
3158 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3160 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3163 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3165 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3166 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3169 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3171 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3172 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3175 void i915_gem_reset(struct drm_device
*dev
);
3176 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3177 int __must_check
i915_gem_init(struct drm_device
*dev
);
3178 int i915_gem_init_engines(struct drm_device
*dev
);
3179 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3180 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
3181 void i915_gem_init_swizzling(struct drm_device
*dev
);
3182 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3183 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3184 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3185 void __i915_add_request(struct drm_i915_gem_request
*req
,
3186 struct drm_i915_gem_object
*batch_obj
,
3188 #define i915_add_request(req) \
3189 __i915_add_request(req, NULL, true)
3190 #define i915_add_request_no_flush(req) \
3191 __i915_add_request(req, NULL, false)
3192 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3195 struct intel_rps_client
*rps
);
3196 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3197 int i915_gem_fault(vm_object_t vm_obj
, vm_ooffset_t offset
, int prot
, vm_page_t
*mres
);
3199 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3202 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3205 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3207 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3209 const struct i915_ggtt_view
*view
);
3210 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3211 const struct i915_ggtt_view
*view
);
3212 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3214 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3215 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3218 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3220 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3221 int tiling_mode
, bool fenced
);
3223 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3224 enum i915_cache_level cache_level
);
3227 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3228 struct dma_buf
*dma_buf
);
3230 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3231 struct drm_gem_object
*gem_obj
, int flags
);
3234 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3235 const struct i915_ggtt_view
*view
);
3236 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3237 struct i915_address_space
*vm
);
3239 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3241 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3244 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3245 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3246 const struct i915_ggtt_view
*view
);
3247 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3248 struct i915_address_space
*vm
);
3250 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3251 struct i915_address_space
*vm
);
3253 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3254 struct i915_address_space
*vm
);
3256 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3257 const struct i915_ggtt_view
*view
);
3260 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3261 struct i915_address_space
*vm
);
3263 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3264 const struct i915_ggtt_view
*view
);
3266 static inline struct i915_vma
*
3267 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3269 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3271 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3273 /* Some GGTT VM helpers */
3274 static inline struct i915_hw_ppgtt
*
3275 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3277 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3281 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3283 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3286 static inline unsigned long
3287 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3289 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3290 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3292 return i915_gem_obj_size(obj
, &ggtt
->base
);
3295 static inline int __must_check
3296 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3300 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3301 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3303 return i915_gem_object_pin(obj
, &ggtt
->base
,
3304 alignment
, flags
| PIN_GLOBAL
);
3308 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3310 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3313 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3314 const struct i915_ggtt_view
*view
);
3316 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3318 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3321 /* i915_gem_fence.c */
3322 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3323 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3325 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3326 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3328 void i915_gem_restore_fences(struct drm_device
*dev
);
3330 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3331 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3332 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3334 /* i915_gem_context.c */
3335 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3336 void i915_gem_context_fini(struct drm_device
*dev
);
3337 void i915_gem_context_reset(struct drm_device
*dev
);
3338 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3339 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3340 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3341 int i915_switch_context(struct drm_i915_gem_request
*req
);
3342 struct intel_context
*
3343 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3344 void i915_gem_context_free(struct kref
*ctx_ref
);
3345 struct drm_i915_gem_object
*
3346 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3347 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3349 kref_get(&ctx
->ref
);
3352 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3354 kref_put(&ctx
->ref
, i915_gem_context_free
);
3357 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3359 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3362 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3363 struct drm_file
*file
);
3364 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3365 struct drm_file
*file
);
3366 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3367 struct drm_file
*file_priv
);
3368 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3369 struct drm_file
*file_priv
);
3371 /* i915_gem_evict.c */
3372 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3373 struct i915_address_space
*vm
,
3376 unsigned cache_level
,
3377 unsigned long start
,
3380 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3381 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3383 /* belongs in i915_gem_gtt.h */
3384 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3386 if (INTEL_INFO(dev
)->gen
< 6)
3387 intel_gtt_chipset_flush();
3390 /* i915_gem_stolen.c */
3391 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3392 struct drm_mm_node
*node
, u64 size
,
3393 unsigned alignment
);
3394 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3395 struct drm_mm_node
*node
, u64 size
,
3396 unsigned alignment
, u64 start
,
3398 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3399 struct drm_mm_node
*node
);
3400 int i915_gem_init_stolen(struct drm_device
*dev
);
3401 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3402 struct drm_i915_gem_object
*
3403 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3404 struct drm_i915_gem_object
*
3405 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3410 /* i915_gem_shrinker.c */
3411 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3412 unsigned long target
,
3414 #define I915_SHRINK_PURGEABLE 0x1
3415 #define I915_SHRINK_UNBOUND 0x2
3416 #define I915_SHRINK_BOUND 0x4
3417 #define I915_SHRINK_ACTIVE 0x8
3418 #define I915_SHRINK_VMAPS 0x10
3419 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3420 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3421 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3424 /* i915_gem_tiling.c */
3425 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3427 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3429 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3430 obj
->tiling_mode
!= I915_TILING_NONE
;
3433 /* i915_gem_debug.c */
3435 int i915_verify_lists(struct drm_device
*dev
);
3437 #define i915_verify_lists(dev) 0
3440 /* i915_debugfs.c */
3441 int i915_debugfs_init(struct drm_minor
*minor
);
3442 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3443 #ifdef CONFIG_DEBUG_FS
3444 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3445 void intel_display_crc_init(struct drm_device
*dev
);
3447 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3449 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3452 /* i915_gpu_error.c */
3454 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3455 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3456 const struct i915_error_state_file_priv
*error
);
3457 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3458 struct drm_i915_private
*i915
,
3459 size_t count
, loff_t pos
);
3460 static inline void i915_error_state_buf_release(
3461 struct drm_i915_error_state_buf
*eb
)
3465 void i915_capture_error_state(struct drm_device
*dev
, u32 engine_mask
,
3466 const char *error_msg
);
3467 void i915_error_state_get(struct drm_device
*dev
,
3468 struct i915_error_state_file_priv
*error_priv
);
3469 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3470 void i915_destroy_error_state(struct drm_device
*dev
);
3472 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3473 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3475 /* i915_cmd_parser.c */
3476 int i915_cmd_parser_get_version(void);
3477 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3478 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3479 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3480 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3481 struct drm_i915_gem_object
*batch_obj
,
3482 struct drm_i915_gem_object
*shadow_batch_obj
,
3483 u32 batch_start_offset
,
3487 /* i915_suspend.c */
3488 extern int i915_save_state(struct drm_device
*dev
);
3489 extern int i915_restore_state(struct drm_device
*dev
);
3492 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3493 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3496 extern int intel_setup_gmbus(struct drm_device
*dev
);
3497 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3498 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3501 extern struct i2c_adapter
*
3502 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3503 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3504 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3505 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3507 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3509 extern void intel_i2c_reset(struct drm_device
*dev
);
3512 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3513 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3514 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3515 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3516 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3517 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3518 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3519 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3520 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3523 /* intel_opregion.c */
3525 extern int intel_opregion_setup(struct drm_device
*dev
);
3526 extern void intel_opregion_init(struct drm_device
*dev
);
3527 extern void intel_opregion_fini(struct drm_device
*dev
);
3528 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3529 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3531 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3533 extern int intel_opregion_get_panel_type(struct drm_device
*dev
);
3535 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3536 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3537 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3538 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3540 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3545 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3549 static inline int intel_opregion_get_panel_type(struct drm_device
*dev
)
3557 extern void intel_register_dsm_handler(void);
3558 extern void intel_unregister_dsm_handler(void);
3560 static inline void intel_register_dsm_handler(void) { return; }
3561 static inline void intel_unregister_dsm_handler(void) { return; }
3562 #endif /* CONFIG_ACPI */
3565 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3566 extern void intel_modeset_init(struct drm_device
*dev
);
3567 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3568 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3569 extern void intel_connector_unregister(struct intel_connector
*);
3570 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3571 extern void intel_display_resume(struct drm_device
*dev
);
3572 extern void i915_redisable_vga(struct drm_device
*dev
);
3573 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3574 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3575 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3576 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3577 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3579 extern void intel_detect_pch(struct drm_device
*dev
);
3580 extern int intel_enable_rc6(const struct drm_device
*dev
);
3582 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3583 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3584 struct drm_file
*file
);
3585 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3586 struct drm_file
*file
);
3588 struct intel_device_info
*i915_get_device_id(int device
);
3591 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3592 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3593 struct intel_overlay_error_state
*error
);
3595 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3596 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3597 struct drm_device
*dev
,
3598 struct intel_display_error_state
*error
);
3600 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3601 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3603 /* intel_sideband.c */
3604 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3605 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3606 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3607 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3608 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3609 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3610 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3611 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3612 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3613 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3614 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3615 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
);
3616 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum i915_pipe pipe
, int reg
, u32 val
);
3617 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3618 enum intel_sbi_destination destination
);
3619 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3620 enum intel_sbi_destination destination
);
3621 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3622 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3624 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3625 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3627 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3628 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3630 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3631 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3632 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3633 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3635 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3636 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3637 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3638 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3640 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3641 * will be implemented using 2 32-bit writes in an arbitrary order with
3642 * an arbitrary delay between them. This can cause the hardware to
3643 * act upon the intermediate value, possibly leading to corruption and
3644 * machine death. You have been warned.
3646 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3647 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3649 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3650 u32 upper, lower, old_upper, loop = 0; \
3651 upper = I915_READ(upper_reg); \
3653 old_upper = upper; \
3654 lower = I915_READ(lower_reg); \
3655 upper = I915_READ(upper_reg); \
3656 } while (upper != old_upper && loop++ < 2); \
3657 (u64)upper << 32 | lower; })
3659 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3660 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3662 #define __raw_read(x, s) \
3663 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3666 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3669 #define __raw_write(x, s) \
3670 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3671 i915_reg_t reg, uint##x##_t val) \
3673 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3688 /* These are untraced mmio-accessors that are only valid to be used inside
3689 * criticial sections inside IRQ handlers where forcewake is explicitly
3691 * Think twice, and think again, before using these.
3692 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3693 * intel_uncore_forcewake_irqunlock().
3695 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3696 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3697 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3699 /* "Broadcast RGB" property */
3700 #define INTEL_BROADCAST_RGB_AUTO 0
3701 #define INTEL_BROADCAST_RGB_FULL 1
3702 #define INTEL_BROADCAST_RGB_LIMITED 2
3704 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3706 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3707 return VLV_VGACNTRL
;
3708 else if (INTEL_INFO(dev
)->gen
>= 5)
3709 return CPU_VGACNTRL
;
3714 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3716 unsigned long j
= msecs_to_jiffies(m
);
3718 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3721 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3723 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3726 static inline unsigned long
3727 timespec_to_jiffies_timeout(const struct timespec
*value
)
3729 unsigned long j
= timespec_to_jiffies(value
);
3731 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3735 * If you need to wait X milliseconds between events A and B, but event B
3736 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3737 * when event A happened, then just before event B you call this function and
3738 * pass the timestamp as the first argument, and X as the second argument.
3741 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3743 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3746 * Don't re-read the value of "jiffies" every time since it may change
3747 * behind our back and break the math.
3749 tmp_jiffies
= jiffies
;
3750 target_jiffies
= timestamp_jiffies
+
3751 msecs_to_jiffies_timeout(to_wait_ms
);
3753 if (time_after(target_jiffies
, tmp_jiffies
)) {
3754 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3756 while (remaining_jiffies
)
3758 schedule_timeout_uninterruptible(remaining_jiffies
);
3760 msleep(jiffies_to_msecs(remaining_jiffies
));
3765 static inline void i915_trace_irq_get(struct intel_engine_cs
*engine
,
3766 struct drm_i915_gem_request
*req
)
3768 if (engine
->trace_irq_req
== NULL
&& engine
->irq_get(engine
))
3769 i915_gem_request_assign(&engine
->trace_irq_req
, req
);