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MPSAFE locking for the ahc/ahd drivers using lockmgr locks.
[dragonfly.git] / sys / dev / disk / aic7xxx / aic7xxx_pci.c
blobfc841db40b371bba653e962c81a32cefded0e9c5
1 /*
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
43 *
44 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.35 2005/09/22 05:11:35 gibbs Exp $
45 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx_pci.c,v 1.14 2008/02/09 18:13:13 pavalos Exp $
46 */
47
48 #ifdef __linux__
49 #include "aic7xxx_osm.h"
50 #include "aic7xxx_inline.h"
51 #include "aic7xxx_93cx6.h"
52 #else
53 #include "aic7xxx_osm.h"
54 #include "aic7xxx_inline.h"
55 #include "aic7xxx_93cx6.h"
56 #endif
57
58 static __inline uint64_t
59 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
60 {
61 uint64_t id;
62
63 id = subvendor
64 | (subdevice << 16)
65 | ((uint64_t)vendor << 32)
66 | ((uint64_t)device << 48);
67
68 return (id);
69 }
70
71 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
72 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
73 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
74 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
75 #define ID_9005_SISL_ID 0x0005900500000000ull
76 #define ID_AIC7850 0x5078900400000000ull
77 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
78 #define ID_AIC7855 0x5578900400000000ull
79 #define ID_AIC7859 0x3860900400000000ull
80 #define ID_AHA_2930CU 0x3860900438699004ull
81 #define ID_AIC7860 0x6078900400000000ull
82 #define ID_AIC7860C 0x6078900478609004ull
83 #define ID_AHA_1480A 0x6075900400000000ull
84 #define ID_AHA_2940AU_0 0x6178900400000000ull
85 #define ID_AHA_2940AU_1 0x6178900478619004ull
86 #define ID_AHA_2940AU_CN 0x2178900478219004ull
87 #define ID_AHA_2930C_VAR 0x6038900438689004ull
88
89 #define ID_AIC7870 0x7078900400000000ull
90 #define ID_AHA_2940 0x7178900400000000ull
91 #define ID_AHA_3940 0x7278900400000000ull
92 #define ID_AHA_398X 0x7378900400000000ull
93 #define ID_AHA_2944 0x7478900400000000ull
94 #define ID_AHA_3944 0x7578900400000000ull
95 #define ID_AHA_4944 0x7678900400000000ull
96
97 #define ID_AIC7880 0x8078900400000000ull
98 #define ID_AIC7880_B 0x8078900478809004ull
99 #define ID_AHA_2940U 0x8178900400000000ull
100 #define ID_AHA_3940U 0x8278900400000000ull
101 #define ID_AHA_2944U 0x8478900400000000ull
102 #define ID_AHA_3944U 0x8578900400000000ull
103 #define ID_AHA_398XU 0x8378900400000000ull
104 #define ID_AHA_4944U 0x8678900400000000ull
105 #define ID_AHA_2940UB 0x8178900478819004ull
106 #define ID_AHA_2930U 0x8878900478889004ull
107 #define ID_AHA_2940U_PRO 0x8778900478879004ull
108 #define ID_AHA_2940U_CN 0x0078900478009004ull
109
110 #define ID_AIC7895 0x7895900478959004ull
111 #define ID_AIC7895_ARO 0x7890900478939004ull
112 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
113 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
114 #define ID_AHA_3940AU 0x7895900478929004ull
115 #define ID_AHA_3944AU 0x7895900478949004ull
116
117 #define ID_AIC7890 0x001F9005000F9005ull
118 #define ID_AIC7890_ARO 0x00139005000F9005ull
119 #define ID_AAA_131U2 0x0013900500039005ull
120 #define ID_AHA_2930U2 0x0011900501819005ull
121 #define ID_AHA_2940U2B 0x00109005A1009005ull
122 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
123 #define ID_AHA_2940U2 0x00109005A1809005ull
124 #define ID_AHA_2950U2B 0x00109005E1009005ull
125
126 #define ID_AIC7892 0x008F9005FFFF9005ull
127 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
128 #define ID_AHA_29160 0x00809005E2A09005ull
129 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
130 #define ID_AHA_29160N 0x0080900562A09005ull
131 #define ID_AHA_29160C 0x0080900562209005ull
132 #define ID_AHA_29160B 0x00809005E2209005ull
133 #define ID_AHA_19160B 0x0081900562A19005ull
134 #define ID_AHA_2915_30LP 0x0082900502109005ull
135
136 #define ID_AIC7896 0x005F9005FFFF9005ull
137 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
138 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
139 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
140 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
141 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
142
143 #define ID_AIC7899 0x00CF9005FFFF9005ull
144 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
145 #define ID_AHA_3960D 0x00C09005F6209005ull
146 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
147
148 #define ID_AIC7810 0x1078900400000000ull
149 #define ID_AIC7815 0x7815900400000000ull
150
151 #define DEVID_9005_TYPE(id) ((id) & 0xF)
152 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
153 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
154 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
155 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
156
157 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
158 #define DEVID_9005_MAXRATE_U160 0x0
159 #define DEVID_9005_MAXRATE_ULTRA2 0x1
160 #define DEVID_9005_MAXRATE_ULTRA 0x2
161 #define DEVID_9005_MAXRATE_FAST 0x3
162
163 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
164
165 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
166 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
167
168 #define SUBID_9005_TYPE(id) ((id) & 0xF)
169 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
170 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
171 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
172 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
173
174 #define SUBID_9005_TYPE_KNOWN(id) \
175 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
176 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
177 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
178 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
179
180 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
181 #define SUBID_9005_MAXRATE_ULTRA2 0x0
182 #define SUBID_9005_MAXRATE_ULTRA 0x1
183 #define SUBID_9005_MAXRATE_U160 0x2
184 #define SUBID_9005_MAXRATE_RESERVED 0x3
185
186 #define SUBID_9005_SEEPTYPE(id) \
187 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
188 ? ((id) & 0xC0) >> 6 \
189 : ((id) & 0x300) >> 8)
190 #define SUBID_9005_SEEPTYPE_NONE 0x0
191 #define SUBID_9005_SEEPTYPE_1K 0x1
192 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
193 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
194 #define SUBID_9005_AUTOTERM(id) \
195 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
196 ? (((id) & 0x400) >> 10) == 0 \
197 : (((id) & 0x40) >> 6) == 0)
198
199 #define SUBID_9005_NUMCHAN(id) \
200 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
201 ? ((id) & 0x300) >> 8 \
202 : ((id) & 0xC00) >> 10)
203
204 #define SUBID_9005_LEGACYCONN(id) \
205 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
206 ? 0 \
207 : ((id) & 0x80) >> 7)
208
209 #define SUBID_9005_MFUNCENB(id) \
210 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
211 ? ((id) & 0x800) >> 11 \
212 : ((id) & 0x1000) >> 12)
213 /*
214 * Informational only. Should use chip register to be
215 * certain, but may be use in identification strings.
216 */
217 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
218 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
219 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
220
221 static ahc_device_setup_t ahc_aic785X_setup;
222 static ahc_device_setup_t ahc_aic7860_setup;
223 static ahc_device_setup_t ahc_apa1480_setup;
224 static ahc_device_setup_t ahc_aic7870_setup;
225 static ahc_device_setup_t ahc_aha394X_setup;
226 static ahc_device_setup_t ahc_aha494X_setup;
227 static ahc_device_setup_t ahc_aha398X_setup;
228 static ahc_device_setup_t ahc_aic7880_setup;
229 static ahc_device_setup_t ahc_aha2940Pro_setup;
230 static ahc_device_setup_t ahc_aha394XU_setup;
231 static ahc_device_setup_t ahc_aha398XU_setup;
232 static ahc_device_setup_t ahc_aic7890_setup;
233 static ahc_device_setup_t ahc_aic7892_setup;
234 static ahc_device_setup_t ahc_aic7895_setup;
235 static ahc_device_setup_t ahc_aic7896_setup;
236 static ahc_device_setup_t ahc_aic7899_setup;
237 static ahc_device_setup_t ahc_aha29160C_setup;
238 static ahc_device_setup_t ahc_raid_setup;
239 static ahc_device_setup_t ahc_aha394XX_setup;
240 static ahc_device_setup_t ahc_aha494XX_setup;
241 static ahc_device_setup_t ahc_aha398XX_setup;
242
243 struct ahc_pci_identity ahc_pci_ident_table [] =
244 {
245 /* aic7850 based controllers */
246 {
247 ID_AHA_2902_04_10_15_20C_30C,
248 ID_ALL_MASK,
249 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
250 ahc_aic785X_setup
251 },
252 /* aic7860 based controllers */
253 {
254 ID_AHA_2930CU,
255 ID_ALL_MASK,
256 "Adaptec 2930CU SCSI adapter",
257 ahc_aic7860_setup
258 },
259 {
260 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
261 ID_DEV_VENDOR_MASK,
262 "Adaptec 1480A Ultra SCSI adapter",
263 ahc_apa1480_setup
264 },
265 {
266 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
267 ID_DEV_VENDOR_MASK,
268 "Adaptec 2940A Ultra SCSI adapter",
269 ahc_aic7860_setup
270 },
271 {
272 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
273 ID_DEV_VENDOR_MASK,
274 "Adaptec 2940A/CN Ultra SCSI adapter",
275 ahc_aic7860_setup
276 },
277 {
278 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
279 ID_DEV_VENDOR_MASK,
280 "Adaptec 2930C Ultra SCSI adapter (VAR)",
281 ahc_aic7860_setup
282 },
283 /* aic7870 based controllers */
284 {
285 ID_AHA_2940,
286 ID_ALL_MASK,
287 "Adaptec 2940 SCSI adapter",
288 ahc_aic7870_setup
289 },
290 {
291 ID_AHA_3940,
292 ID_ALL_MASK,
293 "Adaptec 3940 SCSI adapter",
294 ahc_aha394X_setup
295 },
296 {
297 ID_AHA_398X,
298 ID_ALL_MASK,
299 "Adaptec 398X SCSI RAID adapter",
300 ahc_aha398X_setup
301 },
302 {
303 ID_AHA_2944,
304 ID_ALL_MASK,
305 "Adaptec 2944 SCSI adapter",
306 ahc_aic7870_setup
307 },
308 {
309 ID_AHA_3944,
310 ID_ALL_MASK,
311 "Adaptec 3944 SCSI adapter",
312 ahc_aha394X_setup
313 },
314 {
315 ID_AHA_4944,
316 ID_ALL_MASK,
317 "Adaptec 4944 SCSI adapter",
318 ahc_aha494X_setup
319 },
320 /* aic7880 based controllers */
321 {
322 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
323 ID_DEV_VENDOR_MASK,
324 "Adaptec 2940 Ultra SCSI adapter",
325 ahc_aic7880_setup
326 },
327 {
328 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
329 ID_DEV_VENDOR_MASK,
330 "Adaptec 3940 Ultra SCSI adapter",
331 ahc_aha394XU_setup
332 },
333 {
334 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
335 ID_DEV_VENDOR_MASK,
336 "Adaptec 2944 Ultra SCSI adapter",
337 ahc_aic7880_setup
338 },
339 {
340 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
341 ID_DEV_VENDOR_MASK,
342 "Adaptec 3944 Ultra SCSI adapter",
343 ahc_aha394XU_setup
344 },
345 {
346 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
347 ID_DEV_VENDOR_MASK,
348 "Adaptec 398X Ultra SCSI RAID adapter",
349 ahc_aha398XU_setup
350 },
351 {
352 /*
353 * XXX Don't know the slot numbers
354 * so we can't identify channels
355 */
356 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
357 ID_DEV_VENDOR_MASK,
358 "Adaptec 4944 Ultra SCSI adapter",
359 ahc_aic7880_setup
360 },
361 {
362 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
363 ID_DEV_VENDOR_MASK,
364 "Adaptec 2930 Ultra SCSI adapter",
365 ahc_aic7880_setup
366 },
367 {
368 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
369 ID_DEV_VENDOR_MASK,
370 "Adaptec 2940 Pro Ultra SCSI adapter",
371 ahc_aha2940Pro_setup
372 },
373 {
374 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
375 ID_DEV_VENDOR_MASK,
376 "Adaptec 2940/CN Ultra SCSI adapter",
377 ahc_aic7880_setup
378 },
379 /* Ignore all SISL (AAC on MB) based controllers. */
380 {
381 ID_9005_SISL_ID,
382 ID_9005_SISL_MASK,
383 NULL,
384 NULL
385 },
386 /* aic7890 based controllers */
387 {
388 ID_AHA_2930U2,
389 ID_ALL_MASK,
390 "Adaptec 2930 Ultra2 SCSI adapter",
391 ahc_aic7890_setup
392 },
393 {
394 ID_AHA_2940U2B,
395 ID_ALL_MASK,
396 "Adaptec 2940B Ultra2 SCSI adapter",
397 ahc_aic7890_setup
398 },
399 {
400 ID_AHA_2940U2_OEM,
401 ID_ALL_MASK,
402 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
403 ahc_aic7890_setup
404 },
405 {
406 ID_AHA_2940U2,
407 ID_ALL_MASK,
408 "Adaptec 2940 Ultra2 SCSI adapter",
409 ahc_aic7890_setup
410 },
411 {
412 ID_AHA_2950U2B,
413 ID_ALL_MASK,
414 "Adaptec 2950 Ultra2 SCSI adapter",
415 ahc_aic7890_setup
416 },
417 {
418 ID_AIC7890_ARO,
419 ID_ALL_MASK,
420 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
421 ahc_aic7890_setup
422 },
423 {
424 ID_AAA_131U2,
425 ID_ALL_MASK,
426 "Adaptec AAA-131 Ultra2 RAID adapter",
427 ahc_aic7890_setup
428 },
429 /* aic7892 based controllers */
430 {
431 ID_AHA_29160,
432 ID_ALL_MASK,
433 "Adaptec 29160 Ultra160 SCSI adapter",
434 ahc_aic7892_setup
435 },
436 {
437 ID_AHA_29160_CPQ,
438 ID_ALL_MASK,
439 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
440 ahc_aic7892_setup
441 },
442 {
443 ID_AHA_29160N,
444 ID_ALL_MASK,
445 "Adaptec 29160N Ultra160 SCSI adapter",
446 ahc_aic7892_setup
447 },
448 {
449 ID_AHA_29160C,
450 ID_ALL_MASK,
451 "Adaptec 29160C Ultra160 SCSI adapter",
452 ahc_aha29160C_setup
453 },
454 {
455 ID_AHA_29160B,
456 ID_ALL_MASK,
457 "Adaptec 29160B Ultra160 SCSI adapter",
458 ahc_aic7892_setup
459 },
460 {
461 ID_AHA_19160B,
462 ID_ALL_MASK,
463 "Adaptec 19160B Ultra160 SCSI adapter",
464 ahc_aic7892_setup
465 },
466 {
467 ID_AIC7892_ARO,
468 ID_ALL_MASK,
469 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
470 ahc_aic7892_setup
471 },
472 {
473 ID_AHA_2915_30LP,
474 ID_ALL_MASK,
475 "Adaptec 2915/30LP Ultra160 SCSI adapter",
476 ahc_aic7892_setup
477 },
478 /* aic7895 based controllers */
479 {
480 ID_AHA_2940U_DUAL,
481 ID_ALL_MASK,
482 "Adaptec 2940/DUAL Ultra SCSI adapter",
483 ahc_aic7895_setup
484 },
485 {
486 ID_AHA_3940AU,
487 ID_ALL_MASK,
488 "Adaptec 3940A Ultra SCSI adapter",
489 ahc_aic7895_setup
490 },
491 {
492 ID_AHA_3944AU,
493 ID_ALL_MASK,
494 "Adaptec 3944A Ultra SCSI adapter",
495 ahc_aic7895_setup
496 },
497 {
498 ID_AIC7895_ARO,
499 ID_AIC7895_ARO_MASK,
500 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
501 ahc_aic7895_setup
502 },
503 /* aic7896/97 based controllers */
504 {
505 ID_AHA_3950U2B_0,
506 ID_ALL_MASK,
507 "Adaptec 3950B Ultra2 SCSI adapter",
508 ahc_aic7896_setup
509 },
510 {
511 ID_AHA_3950U2B_1,
512 ID_ALL_MASK,
513 "Adaptec 3950B Ultra2 SCSI adapter",
514 ahc_aic7896_setup
515 },
516 {
517 ID_AHA_3950U2D_0,
518 ID_ALL_MASK,
519 "Adaptec 3950D Ultra2 SCSI adapter",
520 ahc_aic7896_setup
521 },
522 {
523 ID_AHA_3950U2D_1,
524 ID_ALL_MASK,
525 "Adaptec 3950D Ultra2 SCSI adapter",
526 ahc_aic7896_setup
527 },
528 {
529 ID_AIC7896_ARO,
530 ID_ALL_MASK,
531 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
532 ahc_aic7896_setup
533 },
534 /* aic7899 based controllers */
535 {
536 ID_AHA_3960D,
537 ID_ALL_MASK,
538 "Adaptec 3960D Ultra160 SCSI adapter",
539 ahc_aic7899_setup
540 },
541 {
542 ID_AHA_3960D_CPQ,
543 ID_ALL_MASK,
544 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
545 ahc_aic7899_setup
546 },
547 {
548 ID_AIC7899_ARO,
549 ID_ALL_MASK,
550 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
551 ahc_aic7899_setup
552 },
553 /* Generic chip probes for devices we don't know 'exactly' */
554 {
555 ID_AIC7850 & ID_DEV_VENDOR_MASK,
556 ID_DEV_VENDOR_MASK,
557 "Adaptec aic7850 SCSI adapter",
558 ahc_aic785X_setup
559 },
560 {
561 ID_AIC7855 & ID_DEV_VENDOR_MASK,
562 ID_DEV_VENDOR_MASK,
563 "Adaptec aic7855 SCSI adapter",
564 ahc_aic785X_setup
565 },
566 {
567 ID_AIC7859 & ID_DEV_VENDOR_MASK,
568 ID_DEV_VENDOR_MASK,
569 "Adaptec aic7859 SCSI adapter",
570 ahc_aic7860_setup
571 },
572 {
573 ID_AIC7860 & ID_DEV_VENDOR_MASK,
574 ID_DEV_VENDOR_MASK,
575 "Adaptec aic7860 Ultra SCSI adapter",
576 ahc_aic7860_setup
577 },
578 {
579 ID_AIC7870 & ID_DEV_VENDOR_MASK,
580 ID_DEV_VENDOR_MASK,
581 "Adaptec aic7870 SCSI adapter",
582 ahc_aic7870_setup
583 },
584 {
585 ID_AIC7880 & ID_DEV_VENDOR_MASK,
586 ID_DEV_VENDOR_MASK,
587 "Adaptec aic7880 Ultra SCSI adapter",
588 ahc_aic7880_setup
589 },
590 {
591 ID_AIC7890 & ID_9005_GENERIC_MASK,
592 ID_9005_GENERIC_MASK,
593 "Adaptec aic7890/91 Ultra2 SCSI adapter",
594 ahc_aic7890_setup
595 },
596 {
597 ID_AIC7892 & ID_9005_GENERIC_MASK,
598 ID_9005_GENERIC_MASK,
599 "Adaptec aic7892 Ultra160 SCSI adapter",
600 ahc_aic7892_setup
601 },
602 {
603 ID_AIC7895 & ID_DEV_VENDOR_MASK,
604 ID_DEV_VENDOR_MASK,
605 "Adaptec aic7895 Ultra SCSI adapter",
606 ahc_aic7895_setup
607 },
608 {
609 ID_AIC7896 & ID_9005_GENERIC_MASK,
610 ID_9005_GENERIC_MASK,
611 "Adaptec aic7896/97 Ultra2 SCSI adapter",
612 ahc_aic7896_setup
613 },
614 {
615 ID_AIC7899 & ID_9005_GENERIC_MASK,
616 ID_9005_GENERIC_MASK,
617 "Adaptec aic7899 Ultra160 SCSI adapter",
618 ahc_aic7899_setup
619 },
620 {
621 ID_AIC7810 & ID_DEV_VENDOR_MASK,
622 ID_DEV_VENDOR_MASK,
623 "Adaptec aic7810 RAID memory controller",
624 ahc_raid_setup
625 },
626 {
627 ID_AIC7815 & ID_DEV_VENDOR_MASK,
628 ID_DEV_VENDOR_MASK,
629 "Adaptec aic7815 RAID memory controller",
630 ahc_raid_setup
631 }
632 };
633
634 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
635
636 #define AHC_394X_SLOT_CHANNEL_A 4
637 #define AHC_394X_SLOT_CHANNEL_B 5
638
639 #define AHC_398X_SLOT_CHANNEL_A 4
640 #define AHC_398X_SLOT_CHANNEL_B 8
641 #define AHC_398X_SLOT_CHANNEL_C 12
642
643 #define AHC_494X_SLOT_CHANNEL_A 4
644 #define AHC_494X_SLOT_CHANNEL_B 5
645 #define AHC_494X_SLOT_CHANNEL_C 6
646 #define AHC_494X_SLOT_CHANNEL_D 7
647
648 #define DEVCONFIG 0x40
649 #define PCIERRGENDIS 0x80000000ul
650 #define SCBSIZE32 0x00010000ul /* aic789X only */
651 #define REXTVALID 0x00001000ul /* ultra cards only */
652 #define MPORTMODE 0x00000400ul /* aic7870+ only */
653 #define RAMPSM 0x00000200ul /* aic7870+ only */
654 #define VOLSENSE 0x00000100ul
655 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
656 #define SCBRAMSEL 0x00000080ul
657 #define MRDCEN 0x00000040ul
658 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
659 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
660 #define BERREN 0x00000008ul
661 #define DACEN 0x00000004ul
662 #define STPWLEVEL 0x00000002ul
663 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
664
665 #define CSIZE_LATTIME 0x0c
666 #define CACHESIZE 0x0000003ful /* only 5 bits */
667 #define LATTIME 0x0000ff00ul
668
669 /* PCI STATUS definitions */
670 #define DPE 0x80
671 #define SSE 0x40
672 #define RMA 0x20
673 #define RTA 0x10
674 #define STA 0x08
675 #define DPR 0x01
676
677 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
678 uint16_t subvendor, uint16_t subdevice);
679 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
680 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
681 int pcheck, int fast, int large);
682 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
683 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
684 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
685 struct seeprom_config *sc);
686 static void configure_termination(struct ahc_softc *ahc,
687 struct seeprom_descriptor *sd,
688 u_int adapter_control,
689 u_int *sxfrctl1);
690
691 static void ahc_new_term_detect(struct ahc_softc *ahc,
692 int *enableSEC_low,
693 int *enableSEC_high,
694 int *enablePRI_low,
695 int *enablePRI_high,
696 int *eeprom_present);
697 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
698 int *internal68_present,
699 int *externalcable_present,
700 int *eeprom_present);
701 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
702 int *externalcable_present,
703 int *eeprom_present);
704 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
705 static uint8_t read_brdctl(struct ahc_softc *ahc);
706 static void ahc_pci_intr(struct ahc_softc *ahc);
707 static int ahc_pci_chip_init(struct ahc_softc *ahc);
708 static int ahc_pci_suspend(struct ahc_softc *ahc);
709 static int ahc_pci_resume(struct ahc_softc *ahc);
710
711 static int
712 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
713 uint16_t subdevice, uint16_t subvendor)
714 {
715 int result;
716
717 /* Default to invalid. */
718 result = 0;
719 if (vendor == 0x9005
720 && subvendor == 0x9005
721 && subdevice != device
722 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
723
724 switch (SUBID_9005_TYPE(subdevice)) {
725 case SUBID_9005_TYPE_MB:
726 break;
727 case SUBID_9005_TYPE_CARD:
728 case SUBID_9005_TYPE_LCCARD:
729 /*
730 * Currently only trust Adaptec cards to
731 * get the sub device info correct.
732 */
733 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
734 result = 1;
735 break;
736 case SUBID_9005_TYPE_RAID:
737 break;
738 default:
739 break;
740 }
741 }
742 return (result);
743 }
744
745 struct ahc_pci_identity *
746 ahc_find_pci_device(aic_dev_softc_t pci)
747 {
748 uint64_t full_id;
749 uint16_t device;
750 uint16_t vendor;
751 uint16_t subdevice;
752 uint16_t subvendor;
753 struct ahc_pci_identity *entry;
754 u_int i;
755
756 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
757 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
758 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
759 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
760 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
761
762 /*
763 * If the second function is not hooked up, ignore it.
764 * Unfortunately, not all MB vendors implement the
765 * subdevice ID as per the Adaptec spec, so do our best
766 * to sanity check it prior to accepting the subdevice
767 * ID as valid.
768 */
769 if (aic_get_pci_function(pci) > 0
770 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice)
771 && SUBID_9005_MFUNCENB(subdevice) == 0)
772 return (NULL);
773
774 for (i = 0; i < ahc_num_pci_devs; i++) {
775 entry = &ahc_pci_ident_table[i];
776 if (entry->full_id == (full_id & entry->id_mask)) {
777 /* Honor exclusion entries. */
778 if (entry->name == NULL)
779 return (NULL);
780 return (entry);
781 }
782 }
783 return (NULL);
784 }
785
786 int
787 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
788 {
789 u_int command;
790 u_int our_id;
791 u_int sxfrctl1;
792 u_int scsiseq;
793 u_int dscommand0;
794 uint32_t devconfig;
795 int error;
796 uint8_t sblkctl;
797
798 our_id = 0;
799 error = entry->setup(ahc);
800 if (error != 0)
801 return (error);
802 ahc->chip |= AHC_PCI;
803 ahc->description = entry->name;
804
805 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
806
807 error = ahc_pci_map_registers(ahc);
808 if (error != 0)
809 return (error);
810
811 /*
812 * Before we continue probing the card, ensure that
813 * its interrupts are *disabled*. We don't want
814 * a misstep to hang the machine in an interrupt
815 * storm.
816 */
817 ahc_intr_enable(ahc, FALSE);
818
819 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
820
821 /*
822 * If we need to support high memory, enable dual
823 * address cycles. This bit must be set to enable
824 * high address bit generation even if we are on a
825 * 64bit bus (PCI64BIT set in devconfig).
826 */
827 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
828
829 if (bootverbose)
830 kprintf("%s: Enabling 39Bit Addressing\n",
831 ahc_name(ahc));
832 devconfig |= DACEN;
833 }
834
835 /* Ensure that pci error generation, a test feature, is disabled. */
836 devconfig |= PCIERRGENDIS;
837
838 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
839
840 /* Ensure busmastering is enabled */
841 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
842 command |= PCIM_CMD_BUSMASTEREN;
843
844 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
845
846 /* On all PCI adapters, we allow SCB paging */
847 ahc->flags |= AHC_PAGESCBS;
848
849 error = ahc_softc_init(ahc);
850 if (error != 0)
851 return (error);
852
853 /*
854 * Disable PCI parity error checking. Users typically
855 * do this to work around broken PCI chipsets that get
856 * the parity timing wrong and thus generate lots of spurious
857 * errors. The chip only allows us to disable *all* parity
858 * error reporting when doing this, so CIO bus, scb ram, and
859 * scratch ram parity errors will be ignored too.
860 */
861 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
862 ahc->seqctl |= FAILDIS;
863
864 ahc->bus_intr = ahc_pci_intr;
865 ahc->bus_chip_init = ahc_pci_chip_init;
866 ahc->bus_suspend = ahc_pci_suspend;
867 ahc->bus_resume = ahc_pci_resume;
868
869 /* Remeber how the card was setup in case there is no SEEPROM */
870 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
871 ahc_pause(ahc);
872 if ((ahc->features & AHC_ULTRA2) != 0)
873 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
874 else
875 our_id = ahc_inb(ahc, SCSIID) & OID;
876 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
877 scsiseq = ahc_inb(ahc, SCSISEQ);
878 } else {
879 sxfrctl1 = STPWEN;
880 our_id = 7;
881 scsiseq = 0;
882 }
883
884 error = ahc_reset(ahc, /*reinit*/FALSE);
885 if (error != 0)
886 return (ENXIO);
887
888 if ((ahc->features & AHC_DT) != 0) {
889 u_int sfunct;
890
891 /* Perform ALT-Mode Setup */
892 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
893 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
894 ahc_outb(ahc, OPTIONMODE,
895 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
896 ahc_outb(ahc, SFUNCT, sfunct);
897
898 /* Normal mode setup */
899 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
900 |TARGCRCENDEN);
901 }
902
903 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
904 dscommand0 |= MPARCKEN|CACHETHEN;
905 if ((ahc->features & AHC_ULTRA2) != 0) {
906
907 /*
908 * DPARCKEN doesn't work correctly on
909 * some MBs so don't use it.
910 */
911 dscommand0 &= ~DPARCKEN;
912 }
913
914 /*
915 * Handle chips that must have cache line
916 * streaming (dis/en)abled.
917 */
918 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
919 dscommand0 |= CACHETHEN;
920
921 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
922 dscommand0 &= ~CACHETHEN;
923
924 ahc_outb(ahc, DSCOMMAND0, dscommand0);
925
926 ahc->pci_cachesize =
927 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
928 /*bytes*/1) & CACHESIZE;
929 ahc->pci_cachesize *= 4;
930
931 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
932 && ahc->pci_cachesize == 4) {
933
934 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
935 0, /*bytes*/1);
936 ahc->pci_cachesize = 0;
937 }
938
939 /*
940 * We cannot perform ULTRA speeds without the presense
941 * of the external precision resistor.
942 */
943 if ((ahc->features & AHC_ULTRA) != 0) {
944 uint32_t devconfig;
945
946 devconfig = aic_pci_read_config(ahc->dev_softc,
947 DEVCONFIG, /*bytes*/4);
948 if ((devconfig & REXTVALID) == 0)
949 ahc->features &= ~AHC_ULTRA;
950 }
951
952 /* See if we have a SEEPROM and perform auto-term */
953 check_extport(ahc, &sxfrctl1);
954
955 /*
956 * Take the LED out of diagnostic mode
957 */
958 sblkctl = ahc_inb(ahc, SBLKCTL);
959 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
960
961 if ((ahc->features & AHC_ULTRA2) != 0) {
962 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
963 } else {
964 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
965 }
966
967 if (ahc->flags & AHC_USEDEFAULTS) {
968 /*
969 * PCI Adapter default setup
970 * Should only be used if the adapter does not have
971 * a SEEPROM.
972 */
973 /* See if someone else set us up already */
974 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
975 && scsiseq != 0) {
976 kprintf("%s: Using left over BIOS settings\n",
977 ahc_name(ahc));
978 ahc->flags &= ~AHC_USEDEFAULTS;
979 ahc->flags |= AHC_BIOS_ENABLED;
980 } else {
981 /*
982 * Assume only one connector and always turn
983 * on termination.
984 */
985 our_id = 0x07;
986 sxfrctl1 = STPWEN;
987 }
988 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
989
990 ahc->our_id = our_id;
991 }
992
993 /*
994 * Take a look to see if we have external SRAM.
995 * We currently do not attempt to use SRAM that is
996 * shared among multiple controllers.
997 */
998 ahc_probe_ext_scbram(ahc);
999
1000 /*
1001 * Record our termination setting for the
1002 * generic initialization routine.
1003 */
1004 if ((sxfrctl1 & STPWEN) != 0)
1005 ahc->flags |= AHC_TERM_ENB_A;
1006
1007 /*
1008 * Save chip register configuration data for chip resets
1009 * that occur during runtime and resume events.
1010 */
1011 ahc->bus_softc.pci_softc.devconfig =
1012 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1013 ahc->bus_softc.pci_softc.command =
1014 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1015 ahc->bus_softc.pci_softc.csize_lattime =
1016 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1017 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1018 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1019 if ((ahc->features & AHC_DT) != 0) {
1020 u_int sfunct;
1021
1022 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1023 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1024 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1025 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1026 ahc_outb(ahc, SFUNCT, sfunct);
1027 ahc->bus_softc.pci_softc.crccontrol1 =
1028 ahc_inb(ahc, CRCCONTROL1);
1029 }
1030 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1031 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1032
1033 if ((ahc->features & AHC_ULTRA2) != 0)
1034 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1035
1036 /* Core initialization */
1037 error = ahc_init(ahc);
1038 if (error != 0)
1039 return (error);
1040
1041 /*
1042 * Allow interrupts now that we are completely setup.
1043 */
1044 error = ahc_pci_map_int(ahc);
1045 if (error != 0)
1046 return (error);
1047
1048 ahc_lock(ahc);
1049 /*
1050 * Link this softc in with all other ahc instances.
1051 */
1052 ahc_softc_insert(ahc);
1053 ahc_unlock(ahc);
1054 return (0);
1055 }
1056
1057 /*
1058 * Test for the presense of external sram in an
1059 * "unshared" configuration.
1060 */
1061 static int
1062 ahc_ext_scbram_present(struct ahc_softc *ahc)
1063 {
1064 u_int chip;
1065 int ramps;
1066 int single_user;
1067 uint32_t devconfig;
1068
1069 chip = ahc->chip & AHC_CHIPID_MASK;
1070 devconfig = aic_pci_read_config(ahc->dev_softc,
1071 DEVCONFIG, /*bytes*/4);
1072 single_user = (devconfig & MPORTMODE) != 0;
1073
1074 if ((ahc->features & AHC_ULTRA2) != 0)
1075 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1076 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1077 /*
1078 * External SCBRAM arbitration is flakey
1079 * on these chips. Unfortunately this means
1080 * we don't use the extra SCB ram space on the
1081 * 3940AUW.
1082 */
1083 ramps = 0;
1084 else if (chip >= AHC_AIC7870)
1085 ramps = (devconfig & RAMPSM) != 0;
1086 else
1087 ramps = 0;
1088
1089 if (ramps && single_user)
1090 return (1);
1091 return (0);
1092 }
1093
1094 /*
1095 * Enable external scbram.
1096 */
1097 static void
1098 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1099 int fast, int large)
1100 {
1101 uint32_t devconfig;
1102
1103 if (ahc->features & AHC_MULTI_FUNC) {
1104 /*
1105 * Set the SCB Base addr (highest address bit)
1106 * depending on which channel we are.
1107 */
1108 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1109 }
1110
1111 ahc->flags &= ~AHC_LSCBS_ENABLED;
1112 if (large)
1113 ahc->flags |= AHC_LSCBS_ENABLED;
1114 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1115 if ((ahc->features & AHC_ULTRA2) != 0) {
1116 u_int dscommand0;
1117
1118 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1119 if (enable)
1120 dscommand0 &= ~INTSCBRAMSEL;
1121 else
1122 dscommand0 |= INTSCBRAMSEL;
1123 if (large)
1124 dscommand0 &= ~USCBSIZE32;
1125 else
1126 dscommand0 |= USCBSIZE32;
1127 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1128 } else {
1129 if (fast)
1130 devconfig &= ~EXTSCBTIME;
1131 else
1132 devconfig |= EXTSCBTIME;
1133 if (enable)
1134 devconfig &= ~SCBRAMSEL;
1135 else
1136 devconfig |= SCBRAMSEL;
1137 if (large)
1138 devconfig &= ~SCBSIZE32;
1139 else
1140 devconfig |= SCBSIZE32;
1141 }
1142 if (pcheck)
1143 devconfig |= EXTSCBPEN;
1144 else
1145 devconfig &= ~EXTSCBPEN;
1146
1147 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1148 }
1149
1150 /*
1151 * Take a look to see if we have external SRAM.
1152 * We currently do not attempt to use SRAM that is
1153 * shared among multiple controllers.
1154 */
1155 static void
1156 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1157 {
1158 int num_scbs;
1159 int test_num_scbs;
1160 int enable;
1161 int pcheck;
1162 int fast;
1163 int large;
1164
1165 enable = FALSE;
1166 pcheck = FALSE;
1167 fast = FALSE;
1168 large = FALSE;
1169 num_scbs = 0;
1170
1171 if (ahc_ext_scbram_present(ahc) == 0)
1172 goto done;
1173
1174 /*
1175 * Probe for the best parameters to use.
1176 */
1177 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1178 num_scbs = ahc_probe_scbs(ahc);
1179 if (num_scbs == 0) {
1180 /* The SRAM wasn't really present. */
1181 goto done;
1182 }
1183 enable = TRUE;
1184
1185 /*
1186 * Clear any outstanding parity error
1187 * and ensure that parity error reporting
1188 * is enabled.
1189 */
1190 ahc_outb(ahc, SEQCTL, 0);
1191 ahc_outb(ahc, CLRINT, CLRPARERR);
1192 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1193
1194 /* Now see if we can do parity */
1195 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1196 num_scbs = ahc_probe_scbs(ahc);
1197 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1198 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1199 pcheck = TRUE;
1200
1201 /* Clear any resulting parity error */
1202 ahc_outb(ahc, CLRINT, CLRPARERR);
1203 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1204
1205 /* Now see if we can do fast timing */
1206 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1207 test_num_scbs = ahc_probe_scbs(ahc);
1208 if (test_num_scbs == num_scbs
1209 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1210 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1211 fast = TRUE;
1212
1213 /*
1214 * See if we can use large SCBs and still maintain
1215 * the same overall count of SCBs.
1216 */
1217 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1218 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1219 test_num_scbs = ahc_probe_scbs(ahc);
1220 if (test_num_scbs >= num_scbs) {
1221 large = TRUE;
1222 num_scbs = test_num_scbs;
1223 if (num_scbs >= 64) {
1224 /*
1225 * We have enough space to move the
1226 * "busy targets table" into SCB space
1227 * and make it qualify all the way to the
1228 * lun level.
1229 */
1230 ahc->flags |= AHC_SCB_BTT;
1231 }
1232 }
1233 }
1234 done:
1235 /*
1236 * Disable parity error reporting until we
1237 * can load instruction ram.
1238 */
1239 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1240 /* Clear any latched parity error */
1241 ahc_outb(ahc, CLRINT, CLRPARERR);
1242 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1243 if (bootverbose && enable) {
1244 kprintf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1245 ahc_name(ahc), fast ? "fast" : "slow",
1246 pcheck ? ", parity checking enabled" : "",
1247 large ? 64 : 32);
1248 }
1249 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1250 }
1251
1252 /*
1253 * Perform some simple tests that should catch situations where
1254 * our registers are invalidly mapped.
1255 */
1256 int
1257 ahc_pci_test_register_access(struct ahc_softc *ahc)
1258 {
1259 int error;
1260 u_int status1;
1261 uint32_t cmd;
1262 uint8_t hcntrl;
1263
1264 error = EIO;
1265
1266 /*
1267 * Enable PCI error interrupt status, but suppress NMIs
1268 * generated by SERR raised due to target aborts.
1269 */
1270 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1271 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1272 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1273
1274 /*
1275 * First a simple test to see if any
1276 * registers can be read. Reading
1277 * HCNTRL has no side effects and has
1278 * at least one bit that is guaranteed to
1279 * be zero so it is a good register to
1280 * use for this test.
1281 */
1282 hcntrl = ahc_inb(ahc, HCNTRL);
1283
1284 if (hcntrl == 0xFF)
1285 goto fail;
1286
1287 if ((hcntrl & CHIPRST) != 0) {
1288 /*
1289 * The chip has not been initialized since
1290 * PCI/EISA/VLB bus reset. Don't trust
1291 * "left over BIOS data".
1292 */
1293 ahc->flags |= AHC_NO_BIOS_INIT;
1294 }
1295
1296 /*
1297 * Next create a situation where write combining
1298 * or read prefetching could be initiated by the
1299 * CPU or host bridge. Our device does not support
1300 * either, so look for data corruption and/or flagged
1301 * PCI errors. First pause without causing another
1302 * chip reset.
1303 */
1304 hcntrl &= ~CHIPRST;
1305 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1306 while (ahc_is_paused(ahc) == 0)
1307 ;
1308
1309 /* Clear any PCI errors that occurred before our driver attached. */
1310 status1 = aic_pci_read_config(ahc->dev_softc,
1311 PCIR_STATUS + 1, /*bytes*/1);
1312 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1313 status1, /*bytes*/1);
1314 ahc_outb(ahc, CLRINT, CLRPARERR);
1315
1316 ahc_outb(ahc, SEQCTL, PERRORDIS);
1317 ahc_outb(ahc, SCBPTR, 0);
1318 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1319 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1320 goto fail;
1321
1322 status1 = aic_pci_read_config(ahc->dev_softc,
1323 PCIR_STATUS + 1, /*bytes*/1);
1324 if ((status1 & STA) != 0)
1325 goto fail;
1326
1327 error = 0;
1328
1329 fail:
1330 /* Silently clear any latched errors. */
1331 status1 = aic_pci_read_config(ahc->dev_softc,
1332 PCIR_STATUS + 1, /*bytes*/1);
1333 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1334 status1, /*bytes*/1);
1335 ahc_outb(ahc, CLRINT, CLRPARERR);
1336 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1337 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1338 return (error);
1339 }
1340
1341 /*
1342 * Check the external port logic for a serial eeprom
1343 * and termination/cable detection contrls.
1344 */
1345 static void
1346 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1347 {
1348 struct seeprom_descriptor sd;
1349 struct seeprom_config *sc;
1350 int have_seeprom;
1351 int have_autoterm;
1352
1353 sd.sd_ahc = ahc;
1354 sd.sd_control_offset = SEECTL;
1355 sd.sd_status_offset = SEECTL;
1356 sd.sd_dataout_offset = SEECTL;
1357 sc = ahc->seep_config;
1358
1359 /*
1360 * For some multi-channel devices, the c46 is simply too
1361 * small to work. For the other controller types, we can
1362 * get our information from either SEEPROM type. Set the
1363 * type to start our probe with accordingly.
1364 */
1365 if (ahc->flags & AHC_LARGE_SEEPROM)
1366 sd.sd_chip = C56_66;
1367 else
1368 sd.sd_chip = C46;
1369
1370 sd.sd_MS = SEEMS;
1371 sd.sd_RDY = SEERDY;
1372 sd.sd_CS = SEECS;
1373 sd.sd_CK = SEECK;
1374 sd.sd_DO = SEEDO;
1375 sd.sd_DI = SEEDI;
1376
1377 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1378 if (have_seeprom) {
1379
1380 if (bootverbose)
1381 kprintf("%s: Reading SEEPROM...", ahc_name(ahc));
1382
1383 for (;;) {
1384 u_int start_addr;
1385
1386 start_addr = 32 * (ahc->channel - 'A');
1387
1388 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1389 start_addr,
1390 sizeof(*sc)/2);
1391
1392 if (have_seeprom)
1393 have_seeprom = ahc_verify_cksum(sc);
1394
1395 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1396 if (bootverbose) {
1397 if (have_seeprom == 0)
1398 kprintf ("checksum error\n");
1399 else
1400 kprintf ("done.\n");
1401 }
1402 break;
1403 }
1404 sd.sd_chip = C56_66;
1405 }
1406 ahc_release_seeprom(&sd);
1407
1408 /* Remember the SEEPROM type for later */
1409 if (sd.sd_chip == C56_66)
1410 ahc->flags |= AHC_LARGE_SEEPROM;
1411 }
1412
1413 if (!have_seeprom) {
1414 /*
1415 * Pull scratch ram settings and treat them as
1416 * if they are the contents of an seeprom if
1417 * the 'ADPT' signature is found in SCB2.
1418 * We manually compose the data as 16bit values
1419 * to avoid endian issues.
1420 */
1421 ahc_outb(ahc, SCBPTR, 2);
1422 if (ahc_inb(ahc, SCB_BASE) == 'A'
1423 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1424 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1425 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1426 uint16_t *sc_data;
1427 int i;
1428
1429 sc_data = (uint16_t *)sc;
1430 for (i = 0; i < 32; i++, sc_data++) {
1431 int j;
1432
1433 j = i * 2;
1434 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1435 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1436 }
1437 have_seeprom = ahc_verify_cksum(sc);
1438 if (have_seeprom)
1439 ahc->flags |= AHC_SCB_CONFIG_USED;
1440 }
1441 /*
1442 * Clear any SCB parity errors in case this data and
1443 * its associated parity was not initialized by the BIOS
1444 */
1445 ahc_outb(ahc, CLRINT, CLRPARERR);
1446 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1447 }
1448
1449 if (!have_seeprom) {
1450 if (bootverbose)
1451 kprintf("%s: No SEEPROM available.\n", ahc_name(ahc));
1452 ahc->flags |= AHC_USEDEFAULTS;
1453 kfree(ahc->seep_config, M_DEVBUF);
1454 ahc->seep_config = NULL;
1455 sc = NULL;
1456 } else {
1457 ahc_parse_pci_eeprom(ahc, sc);
1458 }
1459
1460 /*
1461 * Cards that have the external logic necessary to talk to
1462 * a SEEPROM, are almost certain to have the remaining logic
1463 * necessary for auto-termination control. This assumption
1464 * hasn't failed yet...
1465 */
1466 have_autoterm = have_seeprom;
1467
1468 /*
1469 * Some low-cost chips have SEEPROM and auto-term control built
1470 * in, instead of using a GAL. They can tell us directly
1471 * if the termination logic is enabled.
1472 */
1473 if ((ahc->features & AHC_SPIOCAP) != 0) {
1474 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1475 have_autoterm = FALSE;
1476 }
1477
1478 if (have_autoterm) {
1479 ahc->flags |= AHC_HAS_TERM_LOGIC;
1480 ahc_acquire_seeprom(ahc, &sd);
1481 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1482 ahc_release_seeprom(&sd);
1483 } else if (have_seeprom) {
1484 *sxfrctl1 &= ~STPWEN;
1485 if ((sc->adapter_control & CFSTERM) != 0)
1486 *sxfrctl1 |= STPWEN;
1487 if (bootverbose)
1488 kprintf("%s: Low byte termination %sabled\n",
1489 ahc_name(ahc),
1490 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1491 }
1492 }
1493
1494 static void
1495 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1496 {
1497 /*
1498 * Put the data we've collected down into SRAM
1499 * where ahc_init will find it.
1500 */
1501 int i;
1502 int max_targ = sc->max_targets & CFMAXTARG;
1503 u_int scsi_conf;
1504 uint16_t discenable;
1505 uint16_t ultraenb;
1506
1507 discenable = 0;
1508 ultraenb = 0;
1509 if ((sc->adapter_control & CFULTRAEN) != 0) {
1510 /*
1511 * Determine if this adapter has a "newstyle"
1512 * SEEPROM format.
1513 */
1514 for (i = 0; i < max_targ; i++) {
1515 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1516 ahc->flags |= AHC_NEWEEPROM_FMT;
1517 break;
1518 }
1519 }
1520 }
1521
1522 for (i = 0; i < max_targ; i++) {
1523 u_int scsirate;
1524 uint16_t target_mask;
1525
1526 target_mask = 0x01 << i;
1527 if (sc->device_flags[i] & CFDISC)
1528 discenable |= target_mask;
1529 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1530 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1531 ultraenb |= target_mask;
1532 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1533 ultraenb |= target_mask;
1534 }
1535 if ((sc->device_flags[i] & CFXFER) == 0x04
1536 && (ultraenb & target_mask) != 0) {
1537 /* Treat 10MHz as a non-ultra speed */
1538 sc->device_flags[i] &= ~CFXFER;
1539 ultraenb &= ~target_mask;
1540 }
1541 if ((ahc->features & AHC_ULTRA2) != 0) {
1542 u_int offset;
1543
1544 if (sc->device_flags[i] & CFSYNCH)
1545 offset = MAX_OFFSET_ULTRA2;
1546 else
1547 offset = 0;
1548 ahc_outb(ahc, TARG_OFFSET + i, offset);
1549
1550 /*
1551 * The ultra enable bits contain the
1552 * high bit of the ultra2 sync rate
1553 * field.
1554 */
1555 scsirate = (sc->device_flags[i] & CFXFER)
1556 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1557 if (sc->device_flags[i] & CFWIDEB)
1558 scsirate |= WIDEXFER;
1559 } else {
1560 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1561 if (sc->device_flags[i] & CFSYNCH)
1562 scsirate |= SOFS;
1563 if (sc->device_flags[i] & CFWIDEB)
1564 scsirate |= WIDEXFER;
1565 }
1566 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1567 }
1568 ahc->our_id = sc->brtime_id & CFSCSIID;
1569
1570 scsi_conf = (ahc->our_id & 0x7);
1571 if (sc->adapter_control & CFSPARITY)
1572 scsi_conf |= ENSPCHK;
1573 if (sc->adapter_control & CFRESETB)
1574 scsi_conf |= RESET_SCSI;
1575
1576 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1577
1578 if (sc->bios_control & CFEXTEND)
1579 ahc->flags |= AHC_EXTENDED_TRANS_A;
1580
1581 if (sc->bios_control & CFBIOSEN)
1582 ahc->flags |= AHC_BIOS_ENABLED;
1583 if (ahc->features & AHC_ULTRA
1584 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1585 /* Should we enable Ultra mode? */
1586 if (!(sc->adapter_control & CFULTRAEN))
1587 /* Treat us as a non-ultra card */
1588 ultraenb = 0;
1589 }
1590
1591 if (sc->signature == CFSIGNATURE
1592 || sc->signature == CFSIGNATURE2) {
1593 uint32_t devconfig;
1594
1595 /* Honor the STPWLEVEL settings */
1596 devconfig = aic_pci_read_config(ahc->dev_softc,
1597 DEVCONFIG, /*bytes*/4);
1598 devconfig &= ~STPWLEVEL;
1599 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1600 devconfig |= STPWLEVEL;
1601 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1602 devconfig, /*bytes*/4);
1603 }
1604 /* Set SCSICONF info */
1605 ahc_outb(ahc, SCSICONF, scsi_conf);
1606 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1607 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1608 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1609 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1610 }
1611
1612 static void
1613 configure_termination(struct ahc_softc *ahc,
1614 struct seeprom_descriptor *sd,
1615 u_int adapter_control,
1616 u_int *sxfrctl1)
1617 {
1618 uint8_t brddat;
1619
1620 brddat = 0;
1621
1622 /*
1623 * Update the settings in sxfrctl1 to match the
1624 * termination settings
1625 */
1626 *sxfrctl1 = 0;
1627
1628 /*
1629 * SEECS must be on for the GALS to latch
1630 * the data properly. Be sure to leave MS
1631 * on or we will release the seeprom.
1632 */
1633 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1634 if ((adapter_control & CFAUTOTERM) != 0
1635 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1636 int internal50_present;
1637 int internal68_present;
1638 int externalcable_present;
1639 int eeprom_present;
1640 int enableSEC_low;
1641 int enableSEC_high;
1642 int enablePRI_low;
1643 int enablePRI_high;
1644 int sum;
1645
1646 enableSEC_low = 0;
1647 enableSEC_high = 0;
1648 enablePRI_low = 0;
1649 enablePRI_high = 0;
1650 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1651 ahc_new_term_detect(ahc, &enableSEC_low,
1652 &enableSEC_high,
1653 &enablePRI_low,
1654 &enablePRI_high,
1655 &eeprom_present);
1656 if ((adapter_control & CFSEAUTOTERM) == 0) {
1657 if (bootverbose)
1658 kprintf("%s: Manual SE Termination\n",
1659 ahc_name(ahc));
1660 enableSEC_low = (adapter_control & CFSELOWTERM);
1661 enableSEC_high =
1662 (adapter_control & CFSEHIGHTERM);
1663 }
1664 if ((adapter_control & CFAUTOTERM) == 0) {
1665 if (bootverbose)
1666 kprintf("%s: Manual LVD Termination\n",
1667 ahc_name(ahc));
1668 enablePRI_low = (adapter_control & CFSTERM);
1669 enablePRI_high = (adapter_control & CFWSTERM);
1670 }
1671 /* Make the table calculations below happy */
1672 internal50_present = 0;
1673 internal68_present = 1;
1674 externalcable_present = 1;
1675 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1676 aic785X_cable_detect(ahc, &internal50_present,
1677 &externalcable_present,
1678 &eeprom_present);
1679 /* Can never support a wide connector. */
1680 internal68_present = 0;
1681 } else {
1682 aic787X_cable_detect(ahc, &internal50_present,
1683 &internal68_present,
1684 &externalcable_present,
1685 &eeprom_present);
1686 }
1687
1688 if ((ahc->features & AHC_WIDE) == 0)
1689 internal68_present = 0;
1690
1691 if (bootverbose
1692 && (ahc->features & AHC_ULTRA2) == 0) {
1693 kprintf("%s: internal 50 cable %s present",
1694 ahc_name(ahc),
1695 internal50_present ? "is":"not");
1696
1697 if ((ahc->features & AHC_WIDE) != 0)
1698 kprintf(", internal 68 cable %s present",
1699 internal68_present ? "is":"not");
1700 kprintf("\n%s: external cable %s present\n",
1701 ahc_name(ahc),
1702 externalcable_present ? "is":"not");
1703 }
1704 if (bootverbose)
1705 kprintf("%s: BIOS eeprom %s present\n",
1706 ahc_name(ahc), eeprom_present ? "is" : "not");
1707
1708 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1709 /*
1710 * The 50 pin connector is a separate bus,
1711 * so force it to always be terminated.
1712 * In the future, perform current sensing
1713 * to determine if we are in the middle of
1714 * a properly terminated bus.
1715 */
1716 internal50_present = 0;
1717 }
1718
1719 /*
1720 * Now set the termination based on what
1721 * we found.
1722 * Flash Enable = BRDDAT7
1723 * Secondary High Term Enable = BRDDAT6
1724 * Secondary Low Term Enable = BRDDAT5 (7890)
1725 * Primary High Term Enable = BRDDAT4 (7890)
1726 */
1727 if ((ahc->features & AHC_ULTRA2) == 0
1728 && (internal50_present != 0)
1729 && (internal68_present != 0)
1730 && (externalcable_present != 0)) {
1731 kprintf("%s: Illegal cable configuration!!. "
1732 "Only two connectors on the "
1733 "adapter may be used at a "
1734 "time!\n", ahc_name(ahc));
1735
1736 /*
1737 * Pretend there are no cables in the hope
1738 * that having all of the termination on
1739 * gives us a more stable bus.
1740 */
1741 internal50_present = 0;
1742 internal68_present = 0;
1743 externalcable_present = 0;
1744 }
1745
1746 if ((ahc->features & AHC_WIDE) != 0
1747 && ((externalcable_present == 0)
1748 || (internal68_present == 0)
1749 || (enableSEC_high != 0))) {
1750 brddat |= BRDDAT6;
1751 if (bootverbose) {
1752 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1753 kprintf("%s: 68 pin termination "
1754 "Enabled\n", ahc_name(ahc));
1755 else
1756 kprintf("%s: %sHigh byte termination "
1757 "Enabled\n", ahc_name(ahc),
1758 enableSEC_high ? "Secondary "
1759 : "");
1760 }
1761 }
1762
1763 sum = internal50_present + internal68_present
1764 + externalcable_present;
1765 if (sum < 2 || (enableSEC_low != 0)) {
1766 if ((ahc->features & AHC_ULTRA2) != 0)
1767 brddat |= BRDDAT5;
1768 else
1769 *sxfrctl1 |= STPWEN;
1770 if (bootverbose) {
1771 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1772 kprintf("%s: 50 pin termination "
1773 "Enabled\n", ahc_name(ahc));
1774 else
1775 kprintf("%s: %sLow byte termination "
1776 "Enabled\n", ahc_name(ahc),
1777 enableSEC_low ? "Secondary "
1778 : "");
1779 }
1780 }
1781
1782 if (enablePRI_low != 0) {
1783 *sxfrctl1 |= STPWEN;
1784 if (bootverbose)
1785 kprintf("%s: Primary Low Byte termination "
1786 "Enabled\n", ahc_name(ahc));
1787 }
1788
1789 /*
1790 * Setup STPWEN before setting up the rest of
1791 * the termination per the tech note on the U160 cards.
1792 */
1793 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1794
1795 if (enablePRI_high != 0) {
1796 brddat |= BRDDAT4;
1797 if (bootverbose)
1798 kprintf("%s: Primary High Byte "
1799 "termination Enabled\n",
1800 ahc_name(ahc));
1801 }
1802
1803 write_brdctl(ahc, brddat);
1804
1805 } else {
1806 if ((adapter_control & CFSTERM) != 0) {
1807 *sxfrctl1 |= STPWEN;
1808
1809 if (bootverbose)
1810 kprintf("%s: %sLow byte termination Enabled\n",
1811 ahc_name(ahc),
1812 (ahc->features & AHC_ULTRA2) ? "Primary "
1813 : "");
1814 }
1815
1816 if ((adapter_control & CFWSTERM) != 0
1817 && (ahc->features & AHC_WIDE) != 0) {
1818 brddat |= BRDDAT6;
1819 if (bootverbose)
1820 kprintf("%s: %sHigh byte termination Enabled\n",
1821 ahc_name(ahc),
1822 (ahc->features & AHC_ULTRA2)
1823 ? "Secondary " : "");
1824 }
1825
1826 /*
1827 * Setup STPWEN before setting up the rest of
1828 * the termination per the tech note on the U160 cards.
1829 */
1830 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1831
1832 if ((ahc->features & AHC_WIDE) != 0)
1833 write_brdctl(ahc, brddat);
1834 }
1835 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1836 }
1837
1838 static void
1839 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1840 int *enableSEC_high, int *enablePRI_low,
1841 int *enablePRI_high, int *eeprom_present)
1842 {
1843 uint8_t brdctl;
1844
1845 /*
1846 * BRDDAT7 = Eeprom
1847 * BRDDAT6 = Enable Secondary High Byte termination
1848 * BRDDAT5 = Enable Secondary Low Byte termination
1849 * BRDDAT4 = Enable Primary high byte termination
1850 * BRDDAT3 = Enable Primary low byte termination
1851 */
1852 brdctl = read_brdctl(ahc);
1853 *eeprom_present = brdctl & BRDDAT7;
1854 *enableSEC_high = (brdctl & BRDDAT6);
1855 *enableSEC_low = (brdctl & BRDDAT5);
1856 *enablePRI_high = (brdctl & BRDDAT4);
1857 *enablePRI_low = (brdctl & BRDDAT3);
1858 }
1859
1860 static void
1861 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1862 int *internal68_present, int *externalcable_present,
1863 int *eeprom_present)
1864 {
1865 uint8_t brdctl;
1866
1867 /*
1868 * First read the status of our cables.
1869 * Set the rom bank to 0 since the
1870 * bank setting serves as a multiplexor
1871 * for the cable detection logic.
1872 * BRDDAT5 controls the bank switch.
1873 */
1874 write_brdctl(ahc, 0);
1875
1876 /*
1877 * Now read the state of the internal
1878 * connectors. BRDDAT6 is INT50 and
1879 * BRDDAT7 is INT68.
1880 */
1881 brdctl = read_brdctl(ahc);
1882 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1883 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1884
1885 /*
1886 * Set the rom bank to 1 and determine
1887 * the other signals.
1888 */
1889 write_brdctl(ahc, BRDDAT5);
1890
1891 /*
1892 * Now read the state of the external
1893 * connectors. BRDDAT6 is EXT68 and
1894 * BRDDAT7 is EPROMPS.
1895 */
1896 brdctl = read_brdctl(ahc);
1897 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1898 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1899 }
1900
1901 static void
1902 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1903 int *externalcable_present, int *eeprom_present)
1904 {
1905 uint8_t brdctl;
1906 uint8_t spiocap;
1907
1908 spiocap = ahc_inb(ahc, SPIOCAP);
1909 spiocap &= ~SOFTCMDEN;
1910 spiocap |= EXT_BRDCTL;
1911 ahc_outb(ahc, SPIOCAP, spiocap);
1912 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1913 ahc_flush_device_writes(ahc);
1914 aic_delay(500);
1915 ahc_outb(ahc, BRDCTL, 0);
1916 ahc_flush_device_writes(ahc);
1917 aic_delay(500);
1918 brdctl = ahc_inb(ahc, BRDCTL);
1919 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1920 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1921 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1922 }
1923
1924 int
1925 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1926 {
1927 int wait;
1928
1929 if ((ahc->features & AHC_SPIOCAP) != 0
1930 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1931 return (0);
1932
1933 /*
1934 * Request access of the memory port. When access is
1935 * granted, SEERDY will go high. We use a 1 second
1936 * timeout which should be near 1 second more than
1937 * is needed. Reason: after the chip reset, there
1938 * should be no contention.
1939 */
1940 SEEPROM_OUTB(sd, sd->sd_MS);
1941 wait = 1000; /* 1 second timeout in msec */
1942 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1943 aic_delay(1000); /* delay 1 msec */
1944 }
1945 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1946 SEEPROM_OUTB(sd, 0);
1947 return (0);
1948 }
1949 return(1);
1950 }
1951
1952 void
1953 ahc_release_seeprom(struct seeprom_descriptor *sd)
1954 {
1955 /* Release access to the memory port and the serial EEPROM. */
1956 SEEPROM_OUTB(sd, 0);
1957 }
1958
1959 static void
1960 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1961 {
1962 uint8_t brdctl;
1963
1964 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1965 brdctl = BRDSTB;
1966 if (ahc->channel == 'B')
1967 brdctl |= BRDCS;
1968 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1969 brdctl = 0;
1970 } else {
1971 brdctl = BRDSTB|BRDCS;
1972 }
1973 ahc_outb(ahc, BRDCTL, brdctl);
1974 ahc_flush_device_writes(ahc);
1975 brdctl |= value;
1976 ahc_outb(ahc, BRDCTL, brdctl);
1977 ahc_flush_device_writes(ahc);
1978 if ((ahc->features & AHC_ULTRA2) != 0)
1979 brdctl |= BRDSTB_ULTRA2;
1980 else
1981 brdctl &= ~BRDSTB;
1982 ahc_outb(ahc, BRDCTL, brdctl);
1983 ahc_flush_device_writes(ahc);
1984 if ((ahc->features & AHC_ULTRA2) != 0)
1985 brdctl = 0;
1986 else
1987 brdctl &= ~BRDCS;
1988 ahc_outb(ahc, BRDCTL, brdctl);
1989 }
1990
1991 static uint8_t
1992 read_brdctl(struct ahc_softc *ahc)
1993 {
1994 uint8_t brdctl;
1995 uint8_t value;
1996
1997 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1998 brdctl = BRDRW;
1999 if (ahc->channel == 'B')
2000 brdctl |= BRDCS;
2001 } else if ((ahc->features & AHC_ULTRA2) != 0) {
2002 brdctl = BRDRW_ULTRA2;
2003 } else {
2004 brdctl = BRDRW|BRDCS;
2005 }
2006 ahc_outb(ahc, BRDCTL, brdctl);
2007 ahc_flush_device_writes(ahc);
2008 value = ahc_inb(ahc, BRDCTL);
2009 ahc_outb(ahc, BRDCTL, 0);
2010 return (value);
2011 }
2012
2013 static void
2014 ahc_pci_intr(struct ahc_softc *ahc)
2015 {
2016 u_int error;
2017 u_int status1;
2018
2019 error = ahc_inb(ahc, ERROR);
2020 if ((error & PCIERRSTAT) == 0)
2021 return;
2022
2023 status1 = aic_pci_read_config(ahc->dev_softc,
2024 PCIR_STATUS + 1, /*bytes*/1);
2025
2026 if ((status1 & ~DPE) != 0
2027 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2028 kprintf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2029 ahc_name(ahc),
2030 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2031 }
2032
2033 if (status1 & DPE
2034 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2035 ahc->pci_target_perr_count++;
2036 kprintf("%s: Data Parity Error Detected during address "
2037 "or write data phase\n", ahc_name(ahc));
2038 }
2039 if (status1 & SSE) {
2040 kprintf("%s: Signal System Error Detected\n", ahc_name(ahc));
2041 }
2042 if (status1 & RMA) {
2043 kprintf("%s: Received a Master Abort\n", ahc_name(ahc));
2044 }
2045 if (status1 & RTA) {
2046 kprintf("%s: Received a Target Abort\n", ahc_name(ahc));
2047 }
2048 if (status1 & STA) {
2049 kprintf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2050 }
2051 if (status1 & DPR) {
2052 kprintf("%s: Data Parity Error has been reported via PERR#\n",
2053 ahc_name(ahc));
2054 }
2055
2056 /* Clear latched errors. */
2057 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2058 status1, /*bytes*/1);
2059
2060 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2061 kprintf("%s: Latched PCIERR interrupt with "
2062 "no status bits set\n", ahc_name(ahc));
2063 } else {
2064 ahc_outb(ahc, CLRINT, CLRPARERR);
2065 }
2066
2067 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2068 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2069 kprintf(
2070 "%s: WARNING WARNING WARNING WARNING\n"
2071 "%s: Too many PCI parity errors observed as a target.\n"
2072 "%s: Some device on this PCI bus is generating bad parity.\n"
2073 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2074 "%s: PCI parity error checking has been disabled.\n"
2075 "%s: WARNING WARNING WARNING WARNING\n",
2076 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2077 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2078 ahc_name(ahc));
2079 ahc->seqctl |= FAILDIS;
2080 ahc->flags |= AHC_DISABLE_PCI_PERR;
2081 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2082 }
2083 ahc_unpause(ahc);
2084 }
2085
2086 static int
2087 ahc_pci_chip_init(struct ahc_softc *ahc)
2088 {
2089 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2090 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2091 if ((ahc->features & AHC_DT) != 0) {
2092 u_int sfunct;
2093
2094 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2095 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2096 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2097 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2098 ahc_outb(ahc, SFUNCT, sfunct);
2099 ahc_outb(ahc, CRCCONTROL1,
2100 ahc->bus_softc.pci_softc.crccontrol1);
2101 }
2102 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2103 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2104
2105 if ((ahc->features & AHC_ULTRA2) != 0)
2106 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2107
2108 return (ahc_chip_init(ahc));
2109 }
2110
2111 static int
2112 ahc_pci_suspend(struct ahc_softc *ahc)
2113 {
2114 return (ahc_suspend(ahc));
2115 }
2116
2117 static int
2118 ahc_pci_resume(struct ahc_softc *ahc)
2119 {
2120
2121 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2122
2123 /*
2124 * We assume that the OS has restored our register
2125 * mappings, etc. Just update the config space registers
2126 * that the OS doesn't know about and rely on our chip
2127 * reset handler to handle the rest.
2128 */
2129 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2130 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2131 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2132 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2133 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2134 ahc->bus_softc.pci_softc.csize_lattime,
2135 /*bytes*/1);
2136 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2137 struct seeprom_descriptor sd;
2138 u_int sxfrctl1;
2139
2140 sd.sd_ahc = ahc;
2141 sd.sd_control_offset = SEECTL;
2142 sd.sd_status_offset = SEECTL;
2143 sd.sd_dataout_offset = SEECTL;
2144
2145 ahc_acquire_seeprom(ahc, &sd);
2146 configure_termination(ahc, &sd,
2147 ahc->seep_config->adapter_control,
2148 &sxfrctl1);
2149 ahc_release_seeprom(&sd);
2150 }
2151 return (ahc_resume(ahc));
2152 }
2153
2154 static int
2155 ahc_aic785X_setup(struct ahc_softc *ahc)
2156 {
2157 aic_dev_softc_t pci;
2158 uint8_t rev;
2159
2160 pci = ahc->dev_softc;
2161 ahc->channel = 'A';
2162 ahc->chip = AHC_AIC7850;
2163 ahc->features = AHC_AIC7850_FE;
2164 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2165 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2166 if (rev >= 1)
2167 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2168 ahc->instruction_ram_size = 512;
2169 return (0);
2170 }
2171
2172 static int
2173 ahc_aic7860_setup(struct ahc_softc *ahc)
2174 {
2175 aic_dev_softc_t pci;
2176 uint8_t rev;
2177
2178 pci = ahc->dev_softc;
2179 ahc->channel = 'A';
2180 ahc->chip = AHC_AIC7860;
2181 ahc->features = AHC_AIC7860_FE;
2182 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2183 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2184 if (rev >= 1)
2185 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2186 ahc->instruction_ram_size = 512;
2187 return (0);
2188 }
2189
2190 static int
2191 ahc_apa1480_setup(struct ahc_softc *ahc)
2192 {
2193 int error;
2194
2195 error = ahc_aic7860_setup(ahc);
2196 if (error != 0)
2197 return (error);
2198 ahc->features |= AHC_REMOVABLE;
2199 return (0);
2200 }
2201
2202 static int
2203 ahc_aic7870_setup(struct ahc_softc *ahc)
2204 {
2205
2206 ahc->channel = 'A';
2207 ahc->chip = AHC_AIC7870;
2208 ahc->features = AHC_AIC7870_FE;
2209 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2210 ahc->instruction_ram_size = 512;
2211 return (0);
2212 }
2213
2214 static int
2215 ahc_aha394X_setup(struct ahc_softc *ahc)
2216 {
2217 int error;
2218
2219 error = ahc_aic7870_setup(ahc);
2220 if (error == 0)
2221 error = ahc_aha394XX_setup(ahc);
2222 return (error);
2223 }
2224
2225 static int
2226 ahc_aha398X_setup(struct ahc_softc *ahc)
2227 {
2228 int error;
2229
2230 error = ahc_aic7870_setup(ahc);
2231 if (error == 0)
2232 error = ahc_aha398XX_setup(ahc);
2233 return (error);
2234 }
2235
2236 static int
2237 ahc_aha494X_setup(struct ahc_softc *ahc)
2238 {
2239 int error;
2240
2241 error = ahc_aic7870_setup(ahc);
2242 if (error == 0)
2243 error = ahc_aha494XX_setup(ahc);
2244 return (error);
2245 }
2246
2247 static int
2248 ahc_aic7880_setup(struct ahc_softc *ahc)
2249 {
2250 aic_dev_softc_t pci;
2251 uint8_t rev;
2252
2253 pci = ahc->dev_softc;
2254 ahc->channel = 'A';
2255 ahc->chip = AHC_AIC7880;
2256 ahc->features = AHC_AIC7880_FE;
2257 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2258 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2259 if (rev >= 1) {
2260 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2261 } else {
2262 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2263 }
2264 ahc->instruction_ram_size = 512;
2265 return (0);
2266 }
2267
2268 static int
2269 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2270 {
2271
2272 ahc->flags |= AHC_INT50_SPEEDFLEX;
2273 return (ahc_aic7880_setup(ahc));
2274 }
2275
2276 static int
2277 ahc_aha394XU_setup(struct ahc_softc *ahc)
2278 {
2279 int error;
2280
2281 error = ahc_aic7880_setup(ahc);
2282 if (error == 0)
2283 error = ahc_aha394XX_setup(ahc);
2284 return (error);
2285 }
2286
2287 static int
2288 ahc_aha398XU_setup(struct ahc_softc *ahc)
2289 {
2290 int error;
2291
2292 error = ahc_aic7880_setup(ahc);
2293 if (error == 0)
2294 error = ahc_aha398XX_setup(ahc);
2295 return (error);
2296 }
2297
2298 static int
2299 ahc_aic7890_setup(struct ahc_softc *ahc)
2300 {
2301 aic_dev_softc_t pci;
2302 uint8_t rev;
2303
2304 pci = ahc->dev_softc;
2305 ahc->channel = 'A';
2306 ahc->chip = AHC_AIC7890;
2307 ahc->features = AHC_AIC7890_FE;
2308 ahc->flags |= AHC_NEWEEPROM_FMT;
2309 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2310 if (rev == 0)
2311 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2312 ahc->instruction_ram_size = 768;
2313 return (0);
2314 }
2315
2316 static int
2317 ahc_aic7892_setup(struct ahc_softc *ahc)
2318 {
2319
2320 ahc->channel = 'A';
2321 ahc->chip = AHC_AIC7892;
2322 ahc->features = AHC_AIC7892_FE;
2323 ahc->flags |= AHC_NEWEEPROM_FMT;
2324 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2325 ahc->instruction_ram_size = 1024;
2326 return (0);
2327 }
2328
2329 static int
2330 ahc_aic7895_setup(struct ahc_softc *ahc)
2331 {
2332 aic_dev_softc_t pci;
2333 uint8_t rev;
2334
2335 pci = ahc->dev_softc;
2336 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2337 /*
2338 * The 'C' revision of the aic7895 has a few additional features.
2339 */
2340 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2341 if (rev >= 4) {
2342 ahc->chip = AHC_AIC7895C;
2343 ahc->features = AHC_AIC7895C_FE;
2344 } else {
2345 u_int command;
2346
2347 ahc->chip = AHC_AIC7895;
2348 ahc->features = AHC_AIC7895_FE;
2349
2350 /*
2351 * The BIOS disables the use of MWI transactions
2352 * since it does not have the MWI bug work around
2353 * we have. Disabling MWI reduces performance, so
2354 * turn it on again.
2355 */
2356 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2357 command |= PCIM_CMD_MWRICEN;
2358 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2359 ahc->bugs |= AHC_PCI_MWI_BUG;
2360 }
2361 /*
2362 * XXX Does CACHETHEN really not work??? What about PCI retry?
2363 * on C level chips. Need to test, but for now, play it safe.
2364 */
2365 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2366 | AHC_CACHETHEN_BUG;
2367
2368 #if 0
2369 uint32_t devconfig;
2370
2371 /*
2372 * Cachesize must also be zero due to stray DAC
2373 * problem when sitting behind some bridges.
2374 */
2375 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2376 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2377 devconfig |= MRDCEN;
2378 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2379 #endif
2380 ahc->flags |= AHC_NEWEEPROM_FMT;
2381 ahc->instruction_ram_size = 512;
2382 return (0);
2383 }
2384
2385 static int
2386 ahc_aic7896_setup(struct ahc_softc *ahc)
2387 {
2388 aic_dev_softc_t pci;
2389
2390 pci = ahc->dev_softc;
2391 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2392 ahc->chip = AHC_AIC7896;
2393 ahc->features = AHC_AIC7896_FE;
2394 ahc->flags |= AHC_NEWEEPROM_FMT;
2395 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2396 ahc->instruction_ram_size = 768;
2397 return (0);
2398 }
2399
2400 static int
2401 ahc_aic7899_setup(struct ahc_softc *ahc)
2402 {
2403 aic_dev_softc_t pci;
2404
2405 pci = ahc->dev_softc;
2406 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2407 ahc->chip = AHC_AIC7899;
2408 ahc->features = AHC_AIC7899_FE;
2409 ahc->flags |= AHC_NEWEEPROM_FMT;
2410 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2411 ahc->instruction_ram_size = 1024;
2412 return (0);
2413 }
2414
2415 static int
2416 ahc_aha29160C_setup(struct ahc_softc *ahc)
2417 {
2418 int error;
2419
2420 error = ahc_aic7899_setup(ahc);
2421 if (error != 0)
2422 return (error);
2423 ahc->features |= AHC_REMOVABLE;
2424 return (0);
2425 }
2426
2427 static int
2428 ahc_raid_setup(struct ahc_softc *ahc)
2429 {
2430 kprintf("RAID functionality unsupported\n");
2431 return (ENXIO);
2432 }
2433
2434 static int
2435 ahc_aha394XX_setup(struct ahc_softc *ahc)
2436 {
2437 aic_dev_softc_t pci;
2438
2439 pci = ahc->dev_softc;
2440 switch (aic_get_pci_slot(pci)) {
2441 case AHC_394X_SLOT_CHANNEL_A:
2442 ahc->channel = 'A';
2443 break;
2444 case AHC_394X_SLOT_CHANNEL_B:
2445 ahc->channel = 'B';
2446 break;
2447 default:
2448 kprintf("adapter at unexpected slot %d\n"
2449 "unable to map to a channel\n",
2450 aic_get_pci_slot(pci));
2451 ahc->channel = 'A';
2452 }
2453 return (0);
2454 }
2455
2456 static int
2457 ahc_aha398XX_setup(struct ahc_softc *ahc)
2458 {
2459 aic_dev_softc_t pci;
2460
2461 pci = ahc->dev_softc;
2462 switch (aic_get_pci_slot(pci)) {
2463 case AHC_398X_SLOT_CHANNEL_A:
2464 ahc->channel = 'A';
2465 break;
2466 case AHC_398X_SLOT_CHANNEL_B:
2467 ahc->channel = 'B';
2468 break;
2469 case AHC_398X_SLOT_CHANNEL_C:
2470 ahc->channel = 'C';
2471 break;
2472 default:
2473 kprintf("adapter at unexpected slot %d\n"
2474 "unable to map to a channel\n",
2475 aic_get_pci_slot(pci));
2476 ahc->channel = 'A';
2477 break;
2478 }
2479 ahc->flags |= AHC_LARGE_SEEPROM;
2480 return (0);
2481 }
2482
2483 static int
2484 ahc_aha494XX_setup(struct ahc_softc *ahc)
2485 {
2486 aic_dev_softc_t pci;
2487
2488 pci = ahc->dev_softc;
2489 switch (aic_get_pci_slot(pci)) {
2490 case AHC_494X_SLOT_CHANNEL_A:
2491 ahc->channel = 'A';
2492 break;
2493 case AHC_494X_SLOT_CHANNEL_B:
2494 ahc->channel = 'B';
2495 break;
2496 case AHC_494X_SLOT_CHANNEL_C:
2497 ahc->channel = 'C';
2498 break;
2499 case AHC_494X_SLOT_CHANNEL_D:
2500 ahc->channel = 'D';
2501 break;
2502 default:
2503 kprintf("adapter at unexpected slot %d\n"
2504 "unable to map to a channel\n",
2505 aic_get_pci_slot(pci));
2506 ahc->channel = 'A';
2507 }
2508 ahc->flags |= AHC_LARGE_SEEPROM;
2509 return (0);
2510 }
DragonFly BSD