2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic79xx.c,v 1.40 2007/04/19 18:53:52 scottl Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx.c,v 1.30 2008/02/09 18:13:13 pavalos Exp $
46 #include "aic79xx_osm.h"
47 #include "aic79xx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 /******************************** Globals *************************************/
51 struct ahd_softc_tailq ahd_tailq
= TAILQ_HEAD_INITIALIZER(ahd_tailq
);
52 uint32_t ahd_attach_to_HostRAID_controllers
= 1;
54 /***************************** Lookup Tables **********************************/
55 char *ahd_chip_names
[] =
62 static const u_int num_chip_names
= NUM_ELEMENTS(ahd_chip_names
);
65 * Hardware error codes.
67 struct ahd_hard_error_entry
{
72 static struct ahd_hard_error_entry ahd_hard_errors
[] = {
73 { DSCTMOUT
, "Discard Timer has timed out" },
74 { ILLOPCODE
, "Illegal Opcode in sequencer program" },
75 { SQPARERR
, "Sequencer Parity Error" },
76 { DPARERR
, "Data-path Parity Error" },
77 { MPARERR
, "Scratch or SCB Memory Parity Error" },
78 { CIOPARERR
, "CIOBUS Parity Error" },
80 static const u_int num_errors
= NUM_ELEMENTS(ahd_hard_errors
);
82 static struct ahd_phase_table_entry ahd_phase_table
[] =
84 { P_DATAOUT
, MSG_NOOP
, "in Data-out phase" },
85 { P_DATAIN
, MSG_INITIATOR_DET_ERR
, "in Data-in phase" },
86 { P_DATAOUT_DT
, MSG_NOOP
, "in DT Data-out phase" },
87 { P_DATAIN_DT
, MSG_INITIATOR_DET_ERR
, "in DT Data-in phase" },
88 { P_COMMAND
, MSG_NOOP
, "in Command phase" },
89 { P_MESGOUT
, MSG_NOOP
, "in Message-out phase" },
90 { P_STATUS
, MSG_INITIATOR_DET_ERR
, "in Status phase" },
91 { P_MESGIN
, MSG_PARITY_ERROR
, "in Message-in phase" },
92 { P_BUSFREE
, MSG_NOOP
, "while idle" },
93 { 0, MSG_NOOP
, "in unknown phase" }
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
100 static const u_int num_phases
= NUM_ELEMENTS(ahd_phase_table
) - 1;
102 /* Our Sequencer Program */
103 #include "aic79xx_seq.h"
105 /**************************** Function Declarations ***************************/
106 static void ahd_handle_transmission_error(struct ahd_softc
*ahd
);
107 static void ahd_handle_lqiphase_error(struct ahd_softc
*ahd
,
109 static int ahd_handle_pkt_busfree(struct ahd_softc
*ahd
,
111 static int ahd_handle_nonpkt_busfree(struct ahd_softc
*ahd
);
112 static void ahd_handle_proto_violation(struct ahd_softc
*ahd
);
113 static void ahd_force_renegotiation(struct ahd_softc
*ahd
,
114 struct ahd_devinfo
*devinfo
);
116 static struct ahd_tmode_tstate
*
117 ahd_alloc_tstate(struct ahd_softc
*ahd
,
118 u_int scsi_id
, char channel
);
119 #ifdef AHD_TARGET_MODE
120 static void ahd_free_tstate(struct ahd_softc
*ahd
,
121 u_int scsi_id
, char channel
, int force
);
123 static void ahd_devlimited_syncrate(struct ahd_softc
*ahd
,
124 struct ahd_initiator_tinfo
*,
128 static void ahd_update_neg_table(struct ahd_softc
*ahd
,
129 struct ahd_devinfo
*devinfo
,
130 struct ahd_transinfo
*tinfo
);
131 static void ahd_update_pending_scbs(struct ahd_softc
*ahd
);
132 static void ahd_fetch_devinfo(struct ahd_softc
*ahd
,
133 struct ahd_devinfo
*devinfo
);
134 static void ahd_scb_devinfo(struct ahd_softc
*ahd
,
135 struct ahd_devinfo
*devinfo
,
137 static void ahd_setup_initiator_msgout(struct ahd_softc
*ahd
,
138 struct ahd_devinfo
*devinfo
,
140 static void ahd_build_transfer_msg(struct ahd_softc
*ahd
,
141 struct ahd_devinfo
*devinfo
);
142 static void ahd_construct_sdtr(struct ahd_softc
*ahd
,
143 struct ahd_devinfo
*devinfo
,
144 u_int period
, u_int offset
);
145 static void ahd_construct_wdtr(struct ahd_softc
*ahd
,
146 struct ahd_devinfo
*devinfo
,
148 static void ahd_construct_ppr(struct ahd_softc
*ahd
,
149 struct ahd_devinfo
*devinfo
,
150 u_int period
, u_int offset
,
151 u_int bus_width
, u_int ppr_options
);
152 static void ahd_clear_msg_state(struct ahd_softc
*ahd
);
153 static void ahd_handle_message_phase(struct ahd_softc
*ahd
);
159 static int ahd_sent_msg(struct ahd_softc
*ahd
, ahd_msgtype type
,
160 u_int msgval
, int full
);
161 static int ahd_parse_msg(struct ahd_softc
*ahd
,
162 struct ahd_devinfo
*devinfo
);
163 static int ahd_handle_msg_reject(struct ahd_softc
*ahd
,
164 struct ahd_devinfo
*devinfo
);
165 static void ahd_handle_ign_wide_residue(struct ahd_softc
*ahd
,
166 struct ahd_devinfo
*devinfo
);
167 static void ahd_reinitialize_dataptrs(struct ahd_softc
*ahd
);
168 static void ahd_handle_devreset(struct ahd_softc
*ahd
,
169 struct ahd_devinfo
*devinfo
,
170 u_int lun
, cam_status status
,
171 char *message
, int verbose_level
);
172 #ifdef AHD_TARGET_MODE
173 static void ahd_setup_target_msgin(struct ahd_softc
*ahd
,
174 struct ahd_devinfo
*devinfo
,
178 static u_int
ahd_sglist_size(struct ahd_softc
*ahd
);
179 static u_int
ahd_sglist_allocsize(struct ahd_softc
*ahd
);
180 static bus_dmamap_callback_t
182 static void ahd_initialize_hscbs(struct ahd_softc
*ahd
);
183 static int ahd_init_scbdata(struct ahd_softc
*ahd
);
184 static void ahd_fini_scbdata(struct ahd_softc
*ahd
);
185 static void ahd_setup_iocell_workaround(struct ahd_softc
*ahd
);
186 static void ahd_iocell_first_selection(struct ahd_softc
*ahd
);
187 static void ahd_add_col_list(struct ahd_softc
*ahd
,
188 struct scb
*scb
, u_int col_idx
);
189 static void ahd_rem_col_list(struct ahd_softc
*ahd
,
191 static void ahd_chip_init(struct ahd_softc
*ahd
);
192 static void ahd_qinfifo_requeue(struct ahd_softc
*ahd
,
193 struct scb
*prev_scb
,
195 static int ahd_qinfifo_count(struct ahd_softc
*ahd
);
196 static int ahd_search_scb_list(struct ahd_softc
*ahd
, int target
,
197 char channel
, int lun
, u_int tag
,
198 role_t role
, uint32_t status
,
199 ahd_search_action action
,
200 u_int
*list_head
, u_int
*list_tail
,
202 static void ahd_stitch_tid_list(struct ahd_softc
*ahd
,
203 u_int tid_prev
, u_int tid_cur
,
205 static void ahd_add_scb_to_free_list(struct ahd_softc
*ahd
,
207 static u_int
ahd_rem_wscb(struct ahd_softc
*ahd
, u_int scbid
,
208 u_int prev
, u_int next
, u_int tid
);
209 static void ahd_reset_current_bus(struct ahd_softc
*ahd
);
210 static ahd_callback_t ahd_reset_poll
;
211 static ahd_callback_t ahd_stat_timer
;
213 static void ahd_dumpseq(struct ahd_softc
*ahd
);
215 static void ahd_loadseq(struct ahd_softc
*ahd
);
216 static int ahd_check_patch(struct ahd_softc
*ahd
,
217 struct patch
**start_patch
,
218 u_int start_instr
, u_int
*skip_addr
);
219 static u_int
ahd_resolve_seqaddr(struct ahd_softc
*ahd
,
221 static void ahd_download_instr(struct ahd_softc
*ahd
,
222 u_int instrptr
, uint8_t *dconsts
);
223 static int ahd_probe_stack_size(struct ahd_softc
*ahd
);
224 static int ahd_other_scb_timeout(struct ahd_softc
*ahd
,
226 struct scb
*other_scb
);
227 static int ahd_scb_active_in_fifo(struct ahd_softc
*ahd
,
229 static void ahd_run_data_fifo(struct ahd_softc
*ahd
,
232 #ifdef AHD_TARGET_MODE
233 static void ahd_queue_lstate_event(struct ahd_softc
*ahd
,
234 struct ahd_tmode_lstate
*lstate
,
238 static void ahd_update_scsiid(struct ahd_softc
*ahd
,
240 static int ahd_handle_target_cmd(struct ahd_softc
*ahd
,
241 struct target_cmd
*cmd
);
244 /******************************** Private Inlines *****************************/
245 static __inline
void ahd_assert_atn(struct ahd_softc
*ahd
);
246 static __inline
int ahd_currently_packetized(struct ahd_softc
*ahd
);
247 static __inline
int ahd_set_active_fifo(struct ahd_softc
*ahd
);
250 ahd_assert_atn(struct ahd_softc
*ahd
)
252 ahd_outb(ahd
, SCSISIGO
, ATNO
);
256 * Determine if the current connection has a packetized
257 * agreement. This does not necessarily mean that we
258 * are currently in a packetized transfer. We could
259 * just as easily be sending or receiving a message.
262 ahd_currently_packetized(struct ahd_softc
*ahd
)
264 ahd_mode_state saved_modes
;
267 saved_modes
= ahd_save_modes(ahd
);
268 if ((ahd
->bugs
& AHD_PKTIZED_STATUS_BUG
) != 0) {
270 * The packetized bit refers to the last
271 * connection, not the current one. Check
272 * for non-zero LQISTATE instead.
274 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
275 packetized
= ahd_inb(ahd
, LQISTATE
) != 0;
277 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
278 packetized
= ahd_inb(ahd
, LQISTAT2
) & PACKETIZED
;
280 ahd_restore_modes(ahd
, saved_modes
);
285 ahd_set_active_fifo(struct ahd_softc
*ahd
)
289 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
290 active_fifo
= ahd_inb(ahd
, DFFSTAT
) & CURRFIFO
;
291 switch (active_fifo
) {
294 ahd_set_modes(ahd
, active_fifo
, active_fifo
);
301 /************************* Sequencer Execution Control ************************/
303 * Restart the sequencer program from address zero
306 ahd_restart(struct ahd_softc
*ahd
)
311 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
313 /* No more pending messages */
314 ahd_clear_msg_state(ahd
);
315 ahd_outb(ahd
, SCSISIGO
, 0); /* De-assert BSY */
316 ahd_outb(ahd
, MSG_OUT
, MSG_NOOP
); /* No message to send */
317 ahd_outb(ahd
, SXFRCTL1
, ahd_inb(ahd
, SXFRCTL1
) & ~BITBUCKET
);
318 ahd_outb(ahd
, SEQINTCTL
, 0);
319 ahd_outb(ahd
, LASTPHASE
, P_BUSFREE
);
320 ahd_outb(ahd
, SEQ_FLAGS
, 0);
321 ahd_outb(ahd
, SAVED_SCSIID
, 0xFF);
322 ahd_outb(ahd
, SAVED_LUN
, 0xFF);
325 * Ensure that the sequencer's idea of TQINPOS
326 * matches our own. The sequencer increments TQINPOS
327 * only after it sees a DMA complete and a reset could
328 * occur before the increment leaving the kernel to believe
329 * the command arrived but the sequencer to not.
331 ahd_outb(ahd
, TQINPOS
, ahd
->tqinfifonext
);
333 /* Always allow reselection */
334 ahd_outb(ahd
, SCSISEQ1
,
335 ahd_inb(ahd
, SCSISEQ_TEMPLATE
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
336 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
339 * Clear any pending sequencer interrupt. It is no
340 * longer relevant since we're resetting the Program
343 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
345 ahd_outb(ahd
, SEQCTL0
, FASTMODE
|SEQRESET
);
350 ahd_clear_fifo(struct ahd_softc
*ahd
, u_int fifo
)
352 ahd_mode_state saved_modes
;
355 if ((ahd_debug
& AHD_SHOW_FIFOS
) != 0)
356 kprintf("%s: Clearing FIFO %d\n", ahd_name(ahd
), fifo
);
358 saved_modes
= ahd_save_modes(ahd
);
359 ahd_set_modes(ahd
, fifo
, fifo
);
360 ahd_outb(ahd
, DFFSXFRCTL
, RSTCHN
|CLRSHCNT
);
361 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0)
362 ahd_outb(ahd
, CCSGCTL
, CCSGRESET
);
363 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
364 ahd_outb(ahd
, SG_STATE
, 0);
365 ahd_restore_modes(ahd
, saved_modes
);
368 /************************* Input/Output Queues ********************************/
370 * Flush and completed commands that are sitting in the command
371 * complete queues down on the chip but have yet to be dma'ed back up.
374 ahd_flush_qoutfifo(struct ahd_softc
*ahd
)
377 ahd_mode_state saved_modes
;
383 saved_modes
= ahd_save_modes(ahd
);
386 * Flush the good status FIFO for completed packetized commands.
388 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
389 saved_scbptr
= ahd_get_scbptr(ahd
);
390 while ((ahd_inb(ahd
, LQISTAT2
) & LQIGSAVAIL
) != 0) {
394 scbid
= ahd_inw(ahd
, GSFIFO
);
395 scb
= ahd_lookup_scb(ahd
, scbid
);
397 kprintf("%s: Warning - GSFIFO SCB %d invalid\n",
398 ahd_name(ahd
), scbid
);
402 * Determine if this transaction is still active in
403 * any FIFO. If it is, we must flush that FIFO to
404 * the host before completing the command.
408 for (i
= 0; i
< 2; i
++) {
409 /* Toggle to the other mode. */
411 ahd_set_modes(ahd
, fifo_mode
, fifo_mode
);
413 if (ahd_scb_active_in_fifo(ahd
, scb
) == 0)
416 ahd_run_data_fifo(ahd
, scb
);
419 * Running this FIFO may cause a CFG4DATA for
420 * this same transaction to assert in the other
421 * FIFO or a new snapshot SAVEPTRS interrupt
422 * in this FIFO. Even running a FIFO may not
423 * clear the transaction if we are still waiting
424 * for data to drain to the host. We must loop
425 * until the transaction is not active in either
426 * FIFO just to be sure. Reset our loop counter
427 * so we will visit both FIFOs again before
428 * declaring this transaction finished. We
429 * also delay a bit so that status has a chance
430 * to change before we look at this FIFO again.
435 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
436 ahd_set_scbptr(ahd
, scbid
);
437 if ((ahd_inb_scbram(ahd
, SCB_SGPTR
) & SG_LIST_NULL
) == 0
438 && ((ahd_inb_scbram(ahd
, SCB_SGPTR
) & SG_FULL_RESID
) != 0
439 || (ahd_inb_scbram(ahd
, SCB_RESIDUAL_SGPTR
)
440 & SG_LIST_NULL
) != 0)) {
444 * The transfer completed with a residual.
445 * Place this SCB on the complete DMA list
446 * so that we update our in-core copy of the
447 * SCB before completing the command.
449 ahd_outb(ahd
, SCB_SCSI_STATUS
, 0);
450 ahd_outb(ahd
, SCB_SGPTR
,
451 ahd_inb_scbram(ahd
, SCB_SGPTR
)
453 ahd_outw(ahd
, SCB_TAG
, scbid
);
454 ahd_outw(ahd
, SCB_NEXT_COMPLETE
, SCB_LIST_NULL
);
455 comp_head
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
456 if (SCBID_IS_NULL(comp_head
)) {
457 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, scbid
);
458 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, scbid
);
462 tail
= ahd_inw(ahd
, COMPLETE_DMA_SCB_TAIL
);
463 ahd_set_scbptr(ahd
, tail
);
464 ahd_outw(ahd
, SCB_NEXT_COMPLETE
, scbid
);
465 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, scbid
);
466 ahd_set_scbptr(ahd
, scbid
);
469 ahd_complete_scb(ahd
, scb
);
471 ahd_set_scbptr(ahd
, saved_scbptr
);
474 * Setup for command channel portion of flush.
476 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
479 * Wait for any inprogress DMA to complete and clear DMA state
480 * if this if for an SCB in the qinfifo.
482 while (((ccscbctl
= ahd_inb(ahd
, CCSCBCTL
)) & (CCARREN
|CCSCBEN
)) != 0) {
484 if ((ccscbctl
& (CCSCBDIR
|CCARREN
)) == (CCSCBDIR
|CCARREN
)) {
485 if ((ccscbctl
& ARRDONE
) != 0)
487 } else if ((ccscbctl
& CCSCBDONE
) != 0)
492 * We leave the sequencer to cleanup in the case of DMA's to
493 * update the qoutfifo. In all other cases (DMA's to the
494 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
495 * we disable the DMA engine so that the sequencer will not
496 * attempt to handle the DMA completion.
498 if ((ccscbctl
& CCSCBDIR
) != 0 || (ccscbctl
& ARRDONE
) != 0)
499 ahd_outb(ahd
, CCSCBCTL
, ccscbctl
& ~(CCARREN
|CCSCBEN
));
502 * Complete any SCBs that just finished
503 * being DMA'ed into the qoutfifo.
505 ahd_run_qoutfifo(ahd
);
507 saved_scbptr
= ahd_get_scbptr(ahd
);
509 * Manually update/complete any completed SCBs that are waiting to be
510 * DMA'ed back up to the host.
512 scbid
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
513 while (!SCBID_IS_NULL(scbid
)) {
517 ahd_set_scbptr(ahd
, scbid
);
518 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
519 scb
= ahd_lookup_scb(ahd
, scbid
);
521 kprintf("%s: Warning - DMA-up and complete "
522 "SCB %d invalid\n", ahd_name(ahd
), scbid
);
525 hscb_ptr
= (uint8_t *)scb
->hscb
;
526 for (i
= 0; i
< sizeof(struct hardware_scb
); i
++)
527 *hscb_ptr
++ = ahd_inb_scbram(ahd
, SCB_BASE
+ i
);
529 ahd_complete_scb(ahd
, scb
);
532 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, SCB_LIST_NULL
);
533 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, SCB_LIST_NULL
);
535 scbid
= ahd_inw(ahd
, COMPLETE_ON_QFREEZE_HEAD
);
536 while (!SCBID_IS_NULL(scbid
)) {
538 ahd_set_scbptr(ahd
, scbid
);
539 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
540 scb
= ahd_lookup_scb(ahd
, scbid
);
542 kprintf("%s: Warning - Complete Qfrz SCB %d invalid\n",
543 ahd_name(ahd
), scbid
);
547 ahd_complete_scb(ahd
, scb
);
550 ahd_outw(ahd
, COMPLETE_ON_QFREEZE_HEAD
, SCB_LIST_NULL
);
552 scbid
= ahd_inw(ahd
, COMPLETE_SCB_HEAD
);
553 while (!SCBID_IS_NULL(scbid
)) {
555 ahd_set_scbptr(ahd
, scbid
);
556 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
557 scb
= ahd_lookup_scb(ahd
, scbid
);
559 kprintf("%s: Warning - Complete SCB %d invalid\n",
560 ahd_name(ahd
), scbid
);
564 ahd_complete_scb(ahd
, scb
);
567 ahd_outw(ahd
, COMPLETE_SCB_HEAD
, SCB_LIST_NULL
);
572 ahd_set_scbptr(ahd
, saved_scbptr
);
573 ahd_restore_modes(ahd
, saved_modes
);
574 ahd
->flags
|= AHD_UPDATE_PEND_CMDS
;
578 * Determine if an SCB for a packetized transaction
579 * is active in a FIFO.
582 ahd_scb_active_in_fifo(struct ahd_softc
*ahd
, struct scb
*scb
)
586 * The FIFO is only active for our transaction if
587 * the SCBPTR matches the SCB's ID and the firmware
588 * has installed a handler for the FIFO or we have
589 * a pending SAVEPTRS or CFG4DATA interrupt.
591 if (ahd_get_scbptr(ahd
) != SCB_GET_TAG(scb
)
592 || ((ahd_inb(ahd
, LONGJMP_ADDR
+1) & INVALID_ADDR
) != 0
593 && (ahd_inb(ahd
, SEQINTSRC
) & (CFG4DATA
|SAVEPTRS
)) == 0))
600 * Run a data fifo to completion for a transaction we know
601 * has completed across the SCSI bus (good status has been
602 * received). We are already set to the correct FIFO mode
603 * on entry to this routine.
605 * This function attempts to operate exactly as the firmware
606 * would when running this FIFO. Care must be taken to update
607 * this routine any time the firmware's FIFO algorithm is
611 ahd_run_data_fifo(struct ahd_softc
*ahd
, struct scb
*scb
)
615 seqintsrc
= ahd_inb(ahd
, SEQINTSRC
);
616 if ((seqintsrc
& CFG4DATA
) != 0) {
621 * Clear full residual flag.
623 sgptr
= ahd_inl_scbram(ahd
, SCB_SGPTR
) & ~SG_FULL_RESID
;
624 ahd_outb(ahd
, SCB_SGPTR
, sgptr
);
627 * Load datacnt and address.
629 datacnt
= ahd_inl_scbram(ahd
, SCB_DATACNT
);
630 if ((datacnt
& AHD_DMA_LAST_SEG
) != 0) {
632 ahd_outb(ahd
, SG_STATE
, 0);
634 ahd_outb(ahd
, SG_STATE
, LOADING_NEEDED
);
635 ahd_outq(ahd
, HADDR
, ahd_inq_scbram(ahd
, SCB_DATAPTR
));
636 ahd_outl(ahd
, HCNT
, datacnt
& AHD_SG_LEN_MASK
);
637 ahd_outb(ahd
, SG_CACHE_PRE
, sgptr
);
638 ahd_outb(ahd
, DFCNTRL
, PRELOADEN
|SCSIEN
|HDMAEN
);
641 * Initialize Residual Fields.
643 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+3, datacnt
>> 24);
644 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
& SG_PTR_MASK
);
647 * Mark the SCB as having a FIFO in use.
649 ahd_outb(ahd
, SCB_FIFO_USE_COUNT
,
650 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
) + 1);
653 * Install a "fake" handler for this FIFO.
655 ahd_outw(ahd
, LONGJMP_ADDR
, 0);
658 * Notify the hardware that we have satisfied
659 * this sequencer interrupt.
661 ahd_outb(ahd
, CLRSEQINTSRC
, CLRCFG4DATA
);
662 } else if ((seqintsrc
& SAVEPTRS
) != 0) {
666 if ((ahd_inb(ahd
, LONGJMP_ADDR
+1)&INVALID_ADDR
) != 0) {
668 * Snapshot Save Pointers. All that
669 * is necessary to clear the snapshot
676 * Disable S/G fetch so the DMA engine
677 * is available to future users.
679 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0)
680 ahd_outb(ahd
, CCSGCTL
, 0);
681 ahd_outb(ahd
, SG_STATE
, 0);
684 * Flush the data FIFO. Strickly only
685 * necessary for Rev A parts.
687 ahd_outb(ahd
, DFCNTRL
, ahd_inb(ahd
, DFCNTRL
) | FIFOFLUSH
);
690 * Calculate residual.
692 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
693 resid
= ahd_inl(ahd
, SHCNT
);
694 resid
|= ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+3) << 24;
695 ahd_outl(ahd
, SCB_RESIDUAL_DATACNT
, resid
);
696 if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & LAST_SEG
) == 0) {
698 * Must back up to the correct S/G element.
699 * Typically this just means resetting our
700 * low byte to the offset in the SG_CACHE,
701 * but if we wrapped, we have to correct
702 * the other bytes of the sgptr too.
704 if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & 0x80) != 0
705 && (sgptr
& 0x80) == 0)
708 sgptr
|= ahd_inb(ahd
, SG_CACHE_SHADOW
)
710 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
711 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+ 3, 0);
712 } else if ((resid
& AHD_SG_LEN_MASK
) == 0) {
713 ahd_outb(ahd
, SCB_RESIDUAL_SGPTR
,
714 sgptr
| SG_LIST_NULL
);
719 ahd_outq(ahd
, SCB_DATAPTR
, ahd_inq(ahd
, SHADDR
));
720 ahd_outl(ahd
, SCB_DATACNT
, resid
);
721 ahd_outl(ahd
, SCB_SGPTR
, sgptr
);
722 ahd_outb(ahd
, CLRSEQINTSRC
, CLRSAVEPTRS
);
723 ahd_outb(ahd
, SEQIMODE
,
724 ahd_inb(ahd
, SEQIMODE
) | ENSAVEPTRS
);
726 * If the data is to the SCSI bus, we are
727 * done, otherwise wait for FIFOEMP.
729 if ((ahd_inb(ahd
, DFCNTRL
) & DIRECTION
) != 0)
731 } else if ((ahd_inb(ahd
, SG_STATE
) & LOADING_NEEDED
) != 0) {
738 * Disable S/G fetch so the DMA engine
739 * is available to future users. We won't
740 * be using the DMA engine to load segments.
742 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0) {
743 ahd_outb(ahd
, CCSGCTL
, 0);
744 ahd_outb(ahd
, SG_STATE
, LOADING_NEEDED
);
748 * Wait for the DMA engine to notice that the
749 * host transfer is enabled and that there is
750 * space in the S/G FIFO for new segments before
751 * loading more segments.
753 if ((ahd_inb(ahd
, DFSTATUS
) & PRELOAD_AVAIL
) != 0
754 && (ahd_inb(ahd
, DFCNTRL
) & HDMAENACK
) != 0) {
757 * Determine the offset of the next S/G
760 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
761 sgptr
&= SG_PTR_MASK
;
762 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
763 struct ahd_dma64_seg
*sg
;
765 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
766 data_addr
= sg
->addr
;
768 sgptr
+= sizeof(*sg
);
770 struct ahd_dma_seg
*sg
;
772 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
773 data_addr
= sg
->len
& AHD_SG_HIGH_ADDR_MASK
;
775 data_addr
|= sg
->addr
;
777 sgptr
+= sizeof(*sg
);
781 * Update residual information.
783 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+3, data_len
>> 24);
784 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
789 if (data_len
& AHD_DMA_LAST_SEG
) {
791 ahd_outb(ahd
, SG_STATE
, 0);
793 ahd_outq(ahd
, HADDR
, data_addr
);
794 ahd_outl(ahd
, HCNT
, data_len
& AHD_SG_LEN_MASK
);
795 ahd_outb(ahd
, SG_CACHE_PRE
, sgptr
& 0xFF);
798 * Advertise the segment to the hardware.
800 dfcntrl
= ahd_inb(ahd
, DFCNTRL
)|PRELOADEN
|HDMAEN
;
801 if ((ahd
->features
& AHD_NEW_DFCNTRL_OPTS
) != 0) {
803 * Use SCSIENWRDIS so that SCSIEN
804 * is never modified by this
807 dfcntrl
|= SCSIENWRDIS
;
809 ahd_outb(ahd
, DFCNTRL
, dfcntrl
);
811 } else if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & LAST_SEG_DONE
) != 0) {
814 * Transfer completed to the end of SG list
815 * and has flushed to the host.
817 ahd_outb(ahd
, SCB_SGPTR
,
818 ahd_inb_scbram(ahd
, SCB_SGPTR
) | SG_LIST_NULL
);
820 } else if ((ahd_inb(ahd
, DFSTATUS
) & FIFOEMP
) != 0) {
823 * Clear any handler for this FIFO, decrement
824 * the FIFO use count for the SCB, and release
827 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
828 ahd_outb(ahd
, SCB_FIFO_USE_COUNT
,
829 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
) - 1);
830 ahd_outb(ahd
, DFFSXFRCTL
, CLRCHN
);
835 * Look for entries in the QoutFIFO that have completed.
836 * The valid_tag completion field indicates the validity
837 * of the entry - the valid value toggles each time through
838 * the queue. We use the sg_status field in the completion
839 * entry to avoid referencing the hscb if the completion
840 * occurred with no errors and no residual. sg_status is
841 * a copy of the first byte (little endian) of the sgptr
845 ahd_run_qoutfifo(struct ahd_softc
*ahd
)
847 struct ahd_completion
*completion
;
851 if ((ahd
->flags
& AHD_RUNNING_QOUTFIFO
) != 0)
852 panic("ahd_run_qoutfifo recursion");
853 ahd
->flags
|= AHD_RUNNING_QOUTFIFO
;
854 ahd_sync_qoutfifo(ahd
, BUS_DMASYNC_POSTREAD
);
856 completion
= &ahd
->qoutfifo
[ahd
->qoutfifonext
];
858 if (completion
->valid_tag
!= ahd
->qoutfifonext_valid_tag
)
861 scb_index
= aic_le16toh(completion
->tag
);
862 scb
= ahd_lookup_scb(ahd
, scb_index
);
864 kprintf("%s: WARNING no command for scb %d "
865 "(cmdcmplt)\nQOUTPOS = %d\n",
866 ahd_name(ahd
), scb_index
,
868 ahd_dump_card_state(ahd
);
869 } else if ((completion
->sg_status
& SG_STATUS_VALID
) != 0) {
870 ahd_handle_scb_status(ahd
, scb
);
875 ahd
->qoutfifonext
= (ahd
->qoutfifonext
+1) & (AHD_QOUT_SIZE
-1);
876 if (ahd
->qoutfifonext
== 0)
877 ahd
->qoutfifonext_valid_tag
^= QOUTFIFO_ENTRY_VALID
;
879 ahd
->flags
&= ~AHD_RUNNING_QOUTFIFO
;
882 /************************* Interrupt Handling *********************************/
884 ahd_handle_hwerrint(struct ahd_softc
*ahd
)
887 * Some catastrophic hardware error has occurred.
888 * Print it for the user and disable the controller.
893 error
= ahd_inb(ahd
, ERROR
);
894 for (i
= 0; i
< num_errors
; i
++) {
895 if ((error
& ahd_hard_errors
[i
].error
) != 0)
896 kprintf("%s: hwerrint, %s\n",
897 ahd_name(ahd
), ahd_hard_errors
[i
].errmesg
);
900 ahd_dump_card_state(ahd
);
903 /* Tell everyone that this HBA is no longer available */
904 ahd_abort_scbs(ahd
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
905 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, ROLE_UNKNOWN
,
908 /* Tell the system that this controller has gone away. */
913 ahd_handle_seqint(struct ahd_softc
*ahd
, u_int intstat
)
918 * Save the sequencer interrupt code and clear the SEQINT
919 * bit. We will unpause the sequencer, if appropriate,
920 * after servicing the request.
922 seqintcode
= ahd_inb(ahd
, SEQINTCODE
);
923 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
924 if ((ahd
->bugs
& AHD_INTCOLLISION_BUG
) != 0) {
926 * Unpause the sequencer and let it clear
927 * SEQINT by writing NO_SEQINT to it. This
928 * will cause the sequencer to be paused again,
929 * which is the expected state of this routine.
932 while (!ahd_is_paused(ahd
))
934 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
936 ahd_update_modes(ahd
);
938 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
939 kprintf("%s: Handle Seqint Called for code %d\n",
940 ahd_name(ahd
), seqintcode
);
942 switch (seqintcode
) {
943 case ENTERING_NONPACK
:
948 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
949 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
950 scbid
= ahd_get_scbptr(ahd
);
951 scb
= ahd_lookup_scb(ahd
, scbid
);
954 * Somehow need to know if this
955 * is from a selection or reselection.
956 * From that, we can determine target
957 * ID so we at least have an I_T nexus.
960 ahd_outb(ahd
, SAVED_SCSIID
, scb
->hscb
->scsiid
);
961 ahd_outb(ahd
, SAVED_LUN
, scb
->hscb
->lun
);
962 ahd_outb(ahd
, SEQ_FLAGS
, 0x0);
964 if ((ahd_inb(ahd
, LQISTAT2
) & LQIPHASE_OUTPKT
) != 0
965 && (ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0) {
967 * Phase change after read stream with
968 * CRC error with P0 asserted on last
972 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0)
973 kprintf("%s: Assuming LQIPHASE_NLQ with "
974 "P0 assertion\n", ahd_name(ahd
));
978 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0)
979 kprintf("%s: Entering NONPACK\n", ahd_name(ahd
));
984 kprintf("%s: Invalid Sequencer interrupt occurred.\n",
986 ahd_dump_card_state(ahd
);
987 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
994 scbid
= ahd_get_scbptr(ahd
);
995 scb
= ahd_lookup_scb(ahd
, scbid
);
997 ahd_print_path(ahd
, scb
);
999 kprintf("%s: ", ahd_name(ahd
));
1000 kprintf("SCB %d Packetized Status Overrun", scbid
);
1001 ahd_dump_card_state(ahd
);
1002 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1005 case CFG4ISTAT_INTR
:
1010 scbid
= ahd_get_scbptr(ahd
);
1011 scb
= ahd_lookup_scb(ahd
, scbid
);
1013 ahd_dump_card_state(ahd
);
1014 kprintf("CFG4ISTAT: Free SCB %d referenced", scbid
);
1015 panic("For safety");
1017 ahd_outq(ahd
, HADDR
, scb
->sense_busaddr
);
1018 ahd_outw(ahd
, HCNT
, AHD_SENSE_BUFSIZE
);
1019 ahd_outb(ahd
, HCNT
+ 2, 0);
1020 ahd_outb(ahd
, SG_CACHE_PRE
, SG_LAST_SEG
);
1021 ahd_outb(ahd
, DFCNTRL
, PRELOADEN
|SCSIEN
|HDMAEN
);
1028 bus_phase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1029 kprintf("%s: ILLEGAL_PHASE 0x%x\n",
1030 ahd_name(ahd
), bus_phase
);
1032 switch (bus_phase
) {
1040 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1041 kprintf("%s: Issued Bus Reset.\n", ahd_name(ahd
));
1045 struct ahd_devinfo devinfo
;
1047 struct ahd_initiator_tinfo
*targ_info
;
1048 struct ahd_tmode_tstate
*tstate
;
1049 struct ahd_transinfo
*tinfo
;
1053 * If a target takes us into the command phase
1054 * assume that it has been externally reset and
1055 * has thus lost our previous packetized negotiation
1056 * agreement. Since we have not sent an identify
1057 * message and may not have fully qualified the
1058 * connection, we change our command to TUR, assert
1059 * ATN and ABORT the task when we go to message in
1060 * phase. The OSM will see the REQUEUE_REQUEST
1061 * status and retry the command.
1063 scbid
= ahd_get_scbptr(ahd
);
1064 scb
= ahd_lookup_scb(ahd
, scbid
);
1066 kprintf("Invalid phase with no valid SCB. "
1067 "Resetting bus.\n");
1068 ahd_reset_channel(ahd
, 'A',
1069 /*Initiate Reset*/TRUE
);
1072 ahd_compile_devinfo(&devinfo
, SCB_GET_OUR_ID(scb
),
1073 SCB_GET_TARGET(ahd
, scb
),
1075 SCB_GET_CHANNEL(ahd
, scb
),
1077 targ_info
= ahd_fetch_transinfo(ahd
,
1082 tinfo
= &targ_info
->curr
;
1083 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
1084 AHD_TRANS_ACTIVE
, /*paused*/TRUE
);
1085 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0,
1086 /*offset*/0, /*ppr_options*/0,
1087 AHD_TRANS_ACTIVE
, /*paused*/TRUE
);
1088 ahd_outb(ahd
, SCB_CDB_STORE
, 0);
1089 ahd_outb(ahd
, SCB_CDB_STORE
+1, 0);
1090 ahd_outb(ahd
, SCB_CDB_STORE
+2, 0);
1091 ahd_outb(ahd
, SCB_CDB_STORE
+3, 0);
1092 ahd_outb(ahd
, SCB_CDB_STORE
+4, 0);
1093 ahd_outb(ahd
, SCB_CDB_STORE
+5, 0);
1094 ahd_outb(ahd
, SCB_CDB_LEN
, 6);
1095 scb
->hscb
->control
&= ~(TAG_ENB
|SCB_TAG_TYPE
);
1096 scb
->hscb
->control
|= MK_MESSAGE
;
1097 ahd_outb(ahd
, SCB_CONTROL
, scb
->hscb
->control
);
1098 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1099 ahd_outb(ahd
, SAVED_SCSIID
, scb
->hscb
->scsiid
);
1101 * The lun is 0, regardless of the SCB's lun
1102 * as we have not sent an identify message.
1104 ahd_outb(ahd
, SAVED_LUN
, 0);
1105 ahd_outb(ahd
, SEQ_FLAGS
, 0);
1106 ahd_assert_atn(ahd
);
1107 scb
->flags
&= ~SCB_PACKETIZED
;
1108 scb
->flags
|= SCB_ABORT
|SCB_CMDPHASE_ABORT
;
1109 ahd_freeze_devq(ahd
, scb
);
1110 aic_set_transaction_status(scb
, CAM_REQUEUE_REQ
);
1111 aic_freeze_scb(scb
);
1114 * Allow the sequencer to continue with
1115 * non-pack processing.
1117 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1118 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOPHACHGINPKT
);
1119 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0) {
1120 ahd_outb(ahd
, CLRLQOINT1
, 0);
1123 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1124 ahd_print_path(ahd
, scb
);
1125 kprintf("Unexpected command phase from "
1126 "packetized target\n");
1140 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1141 kprintf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd
),
1142 ahd_inb(ahd
, MODE_PTR
));
1145 scb_index
= ahd_get_scbptr(ahd
);
1146 scb
= ahd_lookup_scb(ahd
, scb_index
);
1149 * Attempt to transfer to an SCB that is
1152 ahd_assert_atn(ahd
);
1153 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1154 ahd
->msgout_buf
[0] = MSG_ABORT_TASK
;
1155 ahd
->msgout_len
= 1;
1156 ahd
->msgout_index
= 0;
1157 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
1159 * Clear status received flag to prevent any
1160 * attempt to complete this bogus SCB.
1162 ahd_outb(ahd
, SCB_CONTROL
,
1163 ahd_inb_scbram(ahd
, SCB_CONTROL
)
1168 case DUMP_CARD_STATE
:
1170 ahd_dump_card_state(ahd
);
1176 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1177 kprintf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1178 "SG_CACHE_SHADOW = 0x%x\n",
1179 ahd_name(ahd
), ahd_inb(ahd
, DFCNTRL
),
1180 ahd_inb(ahd
, SG_CACHE_SHADOW
));
1183 ahd_reinitialize_dataptrs(ahd
);
1188 struct ahd_devinfo devinfo
;
1191 * The sequencer has encountered a message phase
1192 * that requires host assistance for completion.
1193 * While handling the message phase(s), we will be
1194 * notified by the sequencer after each byte is
1195 * transfered so we can track bus phase changes.
1197 * If this is the first time we've seen a HOST_MSG_LOOP
1198 * interrupt, initialize the state of the host message
1201 ahd_fetch_devinfo(ahd
, &devinfo
);
1202 if (ahd
->msg_type
== MSG_TYPE_NONE
) {
1207 bus_phase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1208 if (bus_phase
!= P_MESGIN
1209 && bus_phase
!= P_MESGOUT
) {
1210 kprintf("ahd_intr: HOST_MSG_LOOP bad "
1211 "phase 0x%x\n", bus_phase
);
1213 * Probably transitioned to bus free before
1214 * we got here. Just punt the message.
1216 ahd_dump_card_state(ahd
);
1217 ahd_clear_intstat(ahd
);
1222 scb_index
= ahd_get_scbptr(ahd
);
1223 scb
= ahd_lookup_scb(ahd
, scb_index
);
1224 if (devinfo
.role
== ROLE_INITIATOR
) {
1225 if (bus_phase
== P_MESGOUT
)
1226 ahd_setup_initiator_msgout(ahd
,
1231 MSG_TYPE_INITIATOR_MSGIN
;
1232 ahd
->msgin_index
= 0;
1235 #ifdef AHD_TARGET_MODE
1237 if (bus_phase
== P_MESGOUT
) {
1239 MSG_TYPE_TARGET_MSGOUT
;
1240 ahd
->msgin_index
= 0;
1243 ahd_setup_target_msgin(ahd
,
1250 ahd_handle_message_phase(ahd
);
1255 /* Ensure we don't leave the selection hardware on */
1256 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
1257 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
1259 kprintf("%s:%c:%d: no active SCB for reconnecting "
1260 "target - issuing BUS DEVICE RESET\n",
1261 ahd_name(ahd
), 'A', ahd_inb(ahd
, SELID
) >> 4);
1262 kprintf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1263 "REG0 == 0x%x ACCUM = 0x%x\n",
1264 ahd_inb(ahd
, SAVED_SCSIID
), ahd_inb(ahd
, SAVED_LUN
),
1265 ahd_inw(ahd
, REG0
), ahd_inb(ahd
, ACCUM
));
1266 kprintf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1268 ahd_inb(ahd
, SEQ_FLAGS
), ahd_get_scbptr(ahd
),
1269 ahd_find_busy_tcl(ahd
,
1270 BUILD_TCL(ahd_inb(ahd
, SAVED_SCSIID
),
1271 ahd_inb(ahd
, SAVED_LUN
))),
1272 ahd_inw(ahd
, SINDEX
));
1273 kprintf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1274 "SCB_CONTROL == 0x%x\n",
1275 ahd_inb(ahd
, SELID
), ahd_inb_scbram(ahd
, SCB_SCSIID
),
1276 ahd_inb_scbram(ahd
, SCB_LUN
),
1277 ahd_inb_scbram(ahd
, SCB_CONTROL
));
1278 kprintf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1279 ahd_inb(ahd
, SCSIBUS
), ahd_inb(ahd
, SCSISIGI
));
1280 kprintf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd
, SXFRCTL0
));
1281 kprintf("SEQCTL0 == 0x%x\n", ahd_inb(ahd
, SEQCTL0
));
1282 ahd_dump_card_state(ahd
);
1283 ahd
->msgout_buf
[0] = MSG_BUS_DEV_RESET
;
1284 ahd
->msgout_len
= 1;
1285 ahd
->msgout_index
= 0;
1286 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
1287 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1288 ahd_assert_atn(ahd
);
1291 case PROTO_VIOLATION
:
1293 ahd_handle_proto_violation(ahd
);
1298 struct ahd_devinfo devinfo
;
1300 ahd_fetch_devinfo(ahd
, &devinfo
);
1301 ahd_handle_ign_wide_residue(ahd
, &devinfo
);
1308 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1309 kprintf("%s:%c:%d: unknown scsi bus phase %x, "
1310 "lastphase = 0x%x. Attempting to continue\n",
1312 SCSIID_TARGET(ahd
, ahd_inb(ahd
, SAVED_SCSIID
)),
1313 lastphase
, ahd_inb(ahd
, SCSISIGI
));
1316 case MISSED_BUSFREE
:
1320 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1321 kprintf("%s:%c:%d: Missed busfree. "
1322 "Lastphase = 0x%x, Curphase = 0x%x\n",
1324 SCSIID_TARGET(ahd
, ahd_inb(ahd
, SAVED_SCSIID
)),
1325 lastphase
, ahd_inb(ahd
, SCSISIGI
));
1332 * When the sequencer detects an overrun, it
1333 * places the controller in "BITBUCKET" mode
1334 * and allows the target to complete its transfer.
1335 * Unfortunately, none of the counters get updated
1336 * when the controller is in this mode, so we have
1337 * no way of knowing how large the overrun was.
1345 scbindex
= ahd_get_scbptr(ahd
);
1346 scb
= ahd_lookup_scb(ahd
, scbindex
);
1348 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1349 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1350 ahd_print_path(ahd
, scb
);
1351 kprintf("data overrun detected %s. Tag == 0x%x.\n",
1352 ahd_lookup_phase_entry(lastphase
)->phasemsg
,
1354 ahd_print_path(ahd
, scb
);
1355 kprintf("%s seen Data Phase. Length = %ld. "
1357 ahd_inb(ahd
, SEQ_FLAGS
) & DPHASE
1358 ? "Have" : "Haven't",
1359 aic_get_transfer_length(scb
), scb
->sg_count
);
1360 ahd_dump_sglist(scb
);
1365 * Set this and it will take effect when the
1366 * target does a command complete.
1368 ahd_freeze_devq(ahd
, scb
);
1369 aic_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
1370 aic_freeze_scb(scb
);
1375 struct ahd_devinfo devinfo
;
1379 ahd_fetch_devinfo(ahd
, &devinfo
);
1380 kprintf("%s:%c:%d:%d: Attempt to issue message failed\n",
1381 ahd_name(ahd
), devinfo
.channel
, devinfo
.target
,
1383 scbid
= ahd_get_scbptr(ahd
);
1384 scb
= ahd_lookup_scb(ahd
, scbid
);
1386 && (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
1388 * Ensure that we didn't put a second instance of this
1389 * SCB into the QINFIFO.
1391 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
1392 SCB_GET_CHANNEL(ahd
, scb
),
1393 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
1394 ROLE_INITIATOR
, /*status*/0,
1396 ahd_outb(ahd
, SCB_CONTROL
,
1397 ahd_inb_scbram(ahd
, SCB_CONTROL
) & ~MK_MESSAGE
);
1400 case TASKMGMT_FUNC_COMPLETE
:
1405 scbid
= ahd_get_scbptr(ahd
);
1406 scb
= ahd_lookup_scb(ahd
, scbid
);
1412 ahd_print_path(ahd
, scb
);
1413 kprintf("Task Management Func 0x%x Complete\n",
1414 scb
->hscb
->task_management
);
1415 lun
= CAM_LUN_WILDCARD
;
1416 tag
= SCB_LIST_NULL
;
1418 switch (scb
->hscb
->task_management
) {
1419 case SIU_TASKMGMT_ABORT_TASK
:
1420 tag
= SCB_GET_TAG(scb
);
1421 case SIU_TASKMGMT_ABORT_TASK_SET
:
1422 case SIU_TASKMGMT_CLEAR_TASK_SET
:
1423 lun
= scb
->hscb
->lun
;
1424 error
= CAM_REQ_ABORTED
;
1425 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
),
1426 'A', lun
, tag
, ROLE_INITIATOR
,
1429 case SIU_TASKMGMT_LUN_RESET
:
1430 lun
= scb
->hscb
->lun
;
1431 case SIU_TASKMGMT_TARGET_RESET
:
1433 struct ahd_devinfo devinfo
;
1435 ahd_scb_devinfo(ahd
, &devinfo
, scb
);
1436 error
= CAM_BDR_SENT
;
1437 ahd_handle_devreset(ahd
, &devinfo
, lun
,
1439 lun
!= CAM_LUN_WILDCARD
1442 /*verbose_level*/0);
1446 panic("Unexpected TaskMgmt Func\n");
1452 case TASKMGMT_CMD_CMPLT_OKAY
:
1458 * An ABORT TASK TMF failed to be delivered before
1459 * the targeted command completed normally.
1461 scbid
= ahd_get_scbptr(ahd
);
1462 scb
= ahd_lookup_scb(ahd
, scbid
);
1465 * Remove the second instance of this SCB from
1466 * the QINFIFO if it is still there.
1468 ahd_print_path(ahd
, scb
);
1469 kprintf("SCB completes before TMF\n");
1471 * Handle losing the race. Wait until any
1472 * current selection completes. We will then
1473 * set the TMF back to zero in this SCB so that
1474 * the sequencer doesn't bother to issue another
1475 * sequencer interrupt for its completion.
1477 while ((ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) != 0
1478 && (ahd_inb(ahd
, SSTAT0
) & SELDO
) == 0
1479 && (ahd_inb(ahd
, SSTAT1
) & SELTO
) == 0)
1481 ahd_outb(ahd
, SCB_TASK_MANAGEMENT
, 0);
1482 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
1483 SCB_GET_CHANNEL(ahd
, scb
),
1484 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
1485 ROLE_INITIATOR
, /*status*/0,
1494 kprintf("%s: Tracepoint %d\n", ahd_name(ahd
),
1495 seqintcode
- TRACEPOINT0
);
1500 ahd_handle_hwerrint(ahd
);
1503 kprintf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd
),
1508 * The sequencer is paused immediately on
1509 * a SEQINT, so we should restart it when
1516 ahd_handle_scsiint(struct ahd_softc
*ahd
, u_int intstat
)
1527 ahd_update_modes(ahd
);
1528 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1530 status3
= ahd_inb(ahd
, SSTAT3
) & (NTRAMPERR
|OSRAMPERR
);
1531 status0
= ahd_inb(ahd
, SSTAT0
) & (IOERR
|OVERRUN
|SELDI
|SELDO
);
1532 status
= ahd_inb(ahd
, SSTAT1
) & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
1533 lqistat1
= ahd_inb(ahd
, LQISTAT1
);
1534 lqostat0
= ahd_inb(ahd
, LQOSTAT0
);
1535 busfreetime
= ahd_inb(ahd
, SSTAT2
) & BUSFREETIME
;
1536 if ((status0
& (SELDI
|SELDO
)) != 0) {
1539 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
1540 simode0
= ahd_inb(ahd
, SIMODE0
);
1541 status0
&= simode0
& (IOERR
|OVERRUN
|SELDI
|SELDO
);
1542 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1544 scbid
= ahd_get_scbptr(ahd
);
1545 scb
= ahd_lookup_scb(ahd
, scbid
);
1547 && (ahd_inb(ahd
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
1550 if ((status0
& IOERR
) != 0) {
1553 now_lvd
= ahd_inb(ahd
, SBLKCTL
) & ENAB40
;
1554 kprintf("%s: Transceiver State Has Changed to %s mode\n",
1555 ahd_name(ahd
), now_lvd
? "LVD" : "SE");
1556 ahd_outb(ahd
, CLRSINT0
, CLRIOERR
);
1558 * A change in I/O mode is equivalent to a bus reset.
1560 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1562 ahd_setup_iocell_workaround(ahd
);
1564 } else if ((status0
& OVERRUN
) != 0) {
1566 kprintf("%s: SCSI offset overrun detected. Resetting bus.\n",
1568 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1569 } else if ((status
& SCSIRSTI
) != 0) {
1571 kprintf("%s: Someone reset channel A\n", ahd_name(ahd
));
1572 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/FALSE
);
1573 } else if ((status
& SCSIPERR
) != 0) {
1575 /* Make sure the sequencer is in a safe location. */
1576 ahd_clear_critical_section(ahd
);
1578 ahd_handle_transmission_error(ahd
);
1579 } else if (lqostat0
!= 0) {
1581 kprintf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd
), lqostat0
);
1582 ahd_outb(ahd
, CLRLQOINT0
, lqostat0
);
1583 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0)
1584 ahd_outb(ahd
, CLRLQOINT1
, 0);
1585 } else if ((status
& SELTO
) != 0) {
1588 /* Stop the selection */
1589 ahd_outb(ahd
, SCSISEQ0
, 0);
1591 /* Make sure the sequencer is in a safe location. */
1592 ahd_clear_critical_section(ahd
);
1594 /* No more pending messages */
1595 ahd_clear_msg_state(ahd
);
1597 /* Clear interrupt state */
1598 ahd_outb(ahd
, CLRSINT1
, CLRSELTIMEO
|CLRBUSFREE
|CLRSCSIPERR
);
1601 * Although the driver does not care about the
1602 * 'Selection in Progress' status bit, the busy
1603 * LED does. SELINGO is only cleared by a successful
1604 * selection, so we must manually clear it to insure
1605 * the LED turns off just in case no future successful
1606 * selections occur (e.g. no devices on the bus).
1608 ahd_outb(ahd
, CLRSINT0
, CLRSELINGO
);
1610 scbid
= ahd_inw(ahd
, WAITING_TID_HEAD
);
1611 scb
= ahd_lookup_scb(ahd
, scbid
);
1613 kprintf("%s: ahd_intr - referenced scb not "
1614 "valid during SELTO scb(0x%x)\n",
1615 ahd_name(ahd
), scbid
);
1616 ahd_dump_card_state(ahd
);
1618 struct ahd_devinfo devinfo
;
1620 if ((ahd_debug
& AHD_SHOW_SELTO
) != 0) {
1621 ahd_print_path(ahd
, scb
);
1622 kprintf("Saw Selection Timeout for SCB 0x%x\n",
1626 ahd_scb_devinfo(ahd
, &devinfo
, scb
);
1627 aic_set_transaction_status(scb
, CAM_SEL_TIMEOUT
);
1628 ahd_freeze_devq(ahd
, scb
);
1631 * Cancel any pending transactions on the device
1632 * now that it seems to be missing. This will
1633 * also revert us to async/narrow transfers until
1634 * we can renegotiate with the device.
1636 ahd_handle_devreset(ahd
, &devinfo
,
1639 "Selection Timeout",
1640 /*verbose_level*/1);
1642 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1643 ahd_iocell_first_selection(ahd
);
1645 } else if ((status0
& (SELDI
|SELDO
)) != 0) {
1647 ahd_iocell_first_selection(ahd
);
1649 } else if (status3
!= 0) {
1650 kprintf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1651 ahd_name(ahd
), status3
);
1652 ahd_outb(ahd
, CLRSINT3
, status3
);
1653 } else if ((lqistat1
& (LQIPHASE_LQ
|LQIPHASE_NLQ
)) != 0) {
1655 /* Make sure the sequencer is in a safe location. */
1656 ahd_clear_critical_section(ahd
);
1658 ahd_handle_lqiphase_error(ahd
, lqistat1
);
1659 } else if ((lqistat1
& LQICRCI_NLQ
) != 0) {
1661 * This status can be delayed during some
1662 * streaming operations. The SCSIPHASE
1663 * handler has already dealt with this case
1664 * so just clear the error.
1666 ahd_outb(ahd
, CLRLQIINT1
, CLRLQICRCI_NLQ
);
1667 } else if ((status
& BUSFREE
) != 0
1668 || (lqistat1
& LQOBUSFREE
) != 0) {
1676 * Clear our selection hardware as soon as possible.
1677 * We may have an entry in the waiting Q for this target,
1678 * that is affected by this busfree and we don't want to
1679 * go about selecting the target while we handle the event.
1681 ahd_outb(ahd
, SCSISEQ0
, 0);
1683 /* Make sure the sequencer is in a safe location. */
1684 ahd_clear_critical_section(ahd
);
1687 * Determine what we were up to at the time of
1690 mode
= AHD_MODE_SCSI
;
1691 busfreetime
= ahd_inb(ahd
, SSTAT2
) & BUSFREETIME
;
1692 lqostat1
= ahd_inb(ahd
, LQOSTAT1
);
1693 switch (busfreetime
) {
1700 mode
= busfreetime
== BUSFREE_DFF0
1701 ? AHD_MODE_DFF0
: AHD_MODE_DFF1
;
1702 ahd_set_modes(ahd
, mode
, mode
);
1703 scbid
= ahd_get_scbptr(ahd
);
1704 scb
= ahd_lookup_scb(ahd
, scbid
);
1706 kprintf("%s: Invalid SCB %d in DFF%d "
1707 "during unexpected busfree\n",
1708 ahd_name(ahd
), scbid
, mode
);
1711 packetized
= (scb
->flags
& SCB_PACKETIZED
) != 0;
1721 packetized
= (lqostat1
& LQOBUSFREE
) != 0;
1723 && ahd_inb(ahd
, LASTPHASE
) == P_BUSFREE
1724 && (ahd_inb(ahd
, SSTAT0
) & SELDI
) == 0
1725 && ((ahd_inb(ahd
, SSTAT0
) & SELDO
) == 0
1726 || (ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) == 0))
1728 * Assume packetized if we are not
1729 * on the bus in a non-packetized
1730 * capacity and any pending selection
1731 * was a packetized selection.
1738 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
1739 kprintf("Saw Busfree. Busfreetime = 0x%x.\n",
1743 * Busfrees that occur in non-packetized phases are
1744 * handled by the nonpkt_busfree handler.
1746 if (packetized
&& ahd_inb(ahd
, LASTPHASE
) == P_BUSFREE
) {
1747 restart
= ahd_handle_pkt_busfree(ahd
, busfreetime
);
1750 restart
= ahd_handle_nonpkt_busfree(ahd
);
1753 * Clear the busfree interrupt status. The setting of
1754 * the interrupt is a pulse, so in a perfect world, we
1755 * would not need to muck with the ENBUSFREE logic. This
1756 * would ensure that if the bus moves on to another
1757 * connection, busfree protection is still in force. If
1758 * BUSFREEREV is broken, however, we must manually clear
1759 * the ENBUSFREE if the busfree occurred during a non-pack
1760 * connection so that we don't get false positives during
1761 * future, packetized, connections.
1763 ahd_outb(ahd
, CLRSINT1
, CLRBUSFREE
);
1765 && (ahd
->bugs
& AHD_BUSFREEREV_BUG
) != 0)
1766 ahd_outb(ahd
, SIMODE1
,
1767 ahd_inb(ahd
, SIMODE1
) & ~ENBUSFREE
);
1770 ahd_clear_fifo(ahd
, mode
);
1772 ahd_clear_msg_state(ahd
);
1773 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1780 kprintf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1781 ahd_name(ahd
), status
);
1782 ahd_dump_card_state(ahd
);
1783 ahd_clear_intstat(ahd
);
1789 ahd_handle_transmission_error(struct ahd_softc
*ahd
)
1803 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1804 lqistat1
= ahd_inb(ahd
, LQISTAT1
) & ~(LQIPHASE_LQ
|LQIPHASE_NLQ
);
1805 lqistat2
= ahd_inb(ahd
, LQISTAT2
);
1806 if ((lqistat1
& (LQICRCI_NLQ
|LQICRCI_LQ
)) == 0
1807 && (ahd
->bugs
& AHD_NLQICRC_DELAYED_BUG
) != 0) {
1810 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
1811 lqistate
= ahd_inb(ahd
, LQISTATE
);
1812 if ((lqistate
>= 0x1E && lqistate
<= 0x24)
1813 || (lqistate
== 0x29)) {
1815 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1816 kprintf("%s: NLQCRC found via LQISTATE\n",
1820 lqistat1
|= LQICRCI_NLQ
;
1822 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1825 ahd_outb(ahd
, CLRLQIINT1
, lqistat1
);
1826 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1827 curphase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1828 perrdiag
= ahd_inb(ahd
, PERRDIAG
);
1829 msg_out
= MSG_INITIATOR_DET_ERR
;
1830 ahd_outb(ahd
, CLRSINT1
, CLRSCSIPERR
);
1833 * Try to find the SCB associated with this error.
1837 || (lqistat1
& LQICRCI_NLQ
) != 0) {
1838 if ((lqistat1
& (LQICRCI_NLQ
|LQIOVERI_NLQ
)) != 0)
1839 ahd_set_active_fifo(ahd
);
1840 scbid
= ahd_get_scbptr(ahd
);
1841 scb
= ahd_lookup_scb(ahd
, scbid
);
1842 if (scb
!= NULL
&& SCB_IS_SILENT(scb
))
1847 if (silent
== FALSE
) {
1848 kprintf("%s: Transmission error detected\n", ahd_name(ahd
));
1849 ahd_lqistat1_print(lqistat1
, &cur_col
, 50);
1850 ahd_lastphase_print(lastphase
, &cur_col
, 50);
1851 ahd_scsisigi_print(curphase
, &cur_col
, 50);
1852 ahd_perrdiag_print(perrdiag
, &cur_col
, 50);
1854 ahd_dump_card_state(ahd
);
1857 if ((lqistat1
& (LQIOVERI_LQ
|LQIOVERI_NLQ
)) != 0) {
1858 if (silent
== FALSE
) {
1859 kprintf("%s: Gross protocol error during incoming "
1860 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1861 ahd_name(ahd
), lqistat1
);
1863 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1865 } else if ((lqistat1
& LQICRCI_LQ
) != 0) {
1867 * A CRC error has been detected on an incoming LQ.
1868 * The bus is currently hung on the last ACK.
1869 * Hit LQIRETRY to release the last ack, and
1870 * wait for the sequencer to determine that ATNO
1871 * is asserted while in message out to take us
1872 * to our host message loop. No NONPACKREQ or
1873 * LQIPHASE type errors will occur in this
1874 * scenario. After this first LQIRETRY, the LQI
1875 * manager will be in ISELO where it will
1876 * happily sit until another packet phase begins.
1877 * Unexpected bus free detection is enabled
1878 * through any phases that occur after we release
1879 * this last ack until the LQI manager sees a
1880 * packet phase. This implies we may have to
1881 * ignore a perfectly valid "unexected busfree"
1882 * after our "initiator detected error" message is
1883 * sent. A busfree is the expected response after
1884 * we tell the target that it's L_Q was corrupted.
1885 * (SPI4R09 10.7.3.3.3)
1887 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
1888 kprintf("LQIRetry for LQICRCI_LQ to release ACK\n");
1889 } else if ((lqistat1
& LQICRCI_NLQ
) != 0) {
1891 * We detected a CRC error in a NON-LQ packet.
1892 * The hardware has varying behavior in this situation
1893 * depending on whether this packet was part of a
1897 * The hardware has already acked the complete packet.
1898 * If the target honors our outstanding ATN condition,
1899 * we should be (or soon will be) in MSGOUT phase.
1900 * This will trigger the LQIPHASE_LQ status bit as the
1901 * hardware was expecting another LQ. Unexpected
1902 * busfree detection is enabled. Once LQIPHASE_LQ is
1903 * true (first entry into host message loop is much
1904 * the same), we must clear LQIPHASE_LQ and hit
1905 * LQIRETRY so the hardware is ready to handle
1906 * a future LQ. NONPACKREQ will not be asserted again
1907 * once we hit LQIRETRY until another packet is
1908 * processed. The target may either go busfree
1909 * or start another packet in response to our message.
1911 * Read Streaming P0 asserted:
1912 * If we raise ATN and the target completes the entire
1913 * stream (P0 asserted during the last packet), the
1914 * hardware will ack all data and return to the ISTART
1915 * state. When the target reponds to our ATN condition,
1916 * LQIPHASE_LQ will be asserted. We should respond to
1917 * this with an LQIRETRY to prepare for any future
1918 * packets. NONPACKREQ will not be asserted again
1919 * once we hit LQIRETRY until another packet is
1920 * processed. The target may either go busfree or
1921 * start another packet in response to our message.
1922 * Busfree detection is enabled.
1924 * Read Streaming P0 not asserted:
1925 * If we raise ATN and the target transitions to
1926 * MSGOUT in or after a packet where P0 is not
1927 * asserted, the hardware will assert LQIPHASE_NLQ.
1928 * We should respond to the LQIPHASE_NLQ with an
1929 * LQIRETRY. Should the target stay in a non-pkt
1930 * phase after we send our message, the hardware
1931 * will assert LQIPHASE_LQ. Recovery is then just as
1932 * listed above for the read streaming with P0 asserted.
1933 * Busfree detection is enabled.
1935 if (silent
== FALSE
)
1936 kprintf("LQICRC_NLQ\n");
1938 kprintf("%s: No SCB valid for LQICRC_NLQ. "
1939 "Resetting bus\n", ahd_name(ahd
));
1940 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1943 } else if ((lqistat1
& LQIBADLQI
) != 0) {
1944 kprintf("Need to handle BADLQI!\n");
1945 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1947 } else if ((perrdiag
& (PARITYERR
|PREVPHASE
)) == PARITYERR
) {
1948 if ((curphase
& ~P_DATAIN_DT
) != 0) {
1949 /* Ack the byte. So we can continue. */
1950 if (silent
== FALSE
)
1951 kprintf("Acking %s to clear perror\n",
1952 ahd_lookup_phase_entry(curphase
)->phasemsg
);
1953 ahd_inb(ahd
, SCSIDAT
);
1956 if (curphase
== P_MESGIN
)
1957 msg_out
= MSG_PARITY_ERROR
;
1961 * We've set the hardware to assert ATN if we
1962 * get a parity error on "in" phases, so all we
1963 * need to do is stuff the message buffer with
1964 * the appropriate message. "In" phases have set
1965 * mesg_out to something other than MSG_NOP.
1967 ahd
->send_msg_perror
= msg_out
;
1968 if (scb
!= NULL
&& msg_out
== MSG_INITIATOR_DET_ERR
)
1969 scb
->flags
|= SCB_TRANSMISSION_ERROR
;
1970 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1971 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1976 ahd_handle_lqiphase_error(struct ahd_softc
*ahd
, u_int lqistat1
)
1979 * Clear the sources of the interrupts.
1981 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1982 ahd_outb(ahd
, CLRLQIINT1
, lqistat1
);
1985 * If the "illegal" phase changes were in response
1986 * to our ATN to flag a CRC error, AND we ended up
1987 * on packet boundaries, clear the error, restart the
1988 * LQI manager as appropriate, and go on our merry
1989 * way toward sending the message. Otherwise, reset
1990 * the bus to clear the error.
1992 ahd_set_active_fifo(ahd
);
1993 if ((ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0
1994 && (ahd_inb(ahd
, MDFFSTAT
) & DLZERO
) != 0) {
1995 if ((lqistat1
& LQIPHASE_LQ
) != 0) {
1996 kprintf("LQIRETRY for LQIPHASE_LQ\n");
1997 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
1998 } else if ((lqistat1
& LQIPHASE_NLQ
) != 0) {
1999 kprintf("LQIRETRY for LQIPHASE_NLQ\n");
2000 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
2002 panic("ahd_handle_lqiphase_error: No phase errors\n");
2003 ahd_dump_card_state(ahd
);
2004 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2007 kprintf("Reseting Channel for LQI Phase error\n");
2008 ahd_dump_card_state(ahd
);
2009 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
2014 * Packetized unexpected or expected busfree.
2015 * Entered in mode based on busfreetime.
2018 ahd_handle_pkt_busfree(struct ahd_softc
*ahd
, u_int busfreetime
)
2022 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
2023 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
2024 lqostat1
= ahd_inb(ahd
, LQOSTAT1
);
2025 if ((lqostat1
& LQOBUSFREE
) != 0) {
2034 * The LQO manager detected an unexpected busfree
2037 * 1) During an outgoing LQ.
2038 * 2) After an outgoing LQ but before the first
2039 * REQ of the command packet.
2040 * 3) During an outgoing command packet.
2042 * In all cases, CURRSCB is pointing to the
2043 * SCB that encountered the failure. Clean
2044 * up the queue, clear SELDO and LQOBUSFREE,
2045 * and allow the sequencer to restart the select
2046 * out at its lesure.
2048 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2049 scbid
= ahd_inw(ahd
, CURRSCB
);
2050 scb
= ahd_lookup_scb(ahd
, scbid
);
2052 panic("SCB not valid during LQOBUSFREE");
2056 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOBUSFREE
);
2057 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0)
2058 ahd_outb(ahd
, CLRLQOINT1
, 0);
2059 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
2060 ahd_flush_device_writes(ahd
);
2061 ahd_outb(ahd
, CLRSINT0
, CLRSELDO
);
2064 * Return the LQO manager to its idle loop. It will
2065 * not do this automatically if the busfree occurs
2066 * after the first REQ of either the LQ or command
2067 * packet or between the LQ and command packet.
2069 ahd_outb(ahd
, LQCTL2
, ahd_inb(ahd
, LQCTL2
) | LQOTOIDLE
);
2072 * Update the waiting for selection queue so
2073 * we restart on the correct SCB.
2075 waiting_h
= ahd_inw(ahd
, WAITING_TID_HEAD
);
2076 saved_scbptr
= ahd_get_scbptr(ahd
);
2077 if (waiting_h
!= scbid
) {
2079 ahd_outw(ahd
, WAITING_TID_HEAD
, scbid
);
2080 waiting_t
= ahd_inw(ahd
, WAITING_TID_TAIL
);
2081 if (waiting_t
== waiting_h
) {
2082 ahd_outw(ahd
, WAITING_TID_TAIL
, scbid
);
2083 next
= SCB_LIST_NULL
;
2085 ahd_set_scbptr(ahd
, waiting_h
);
2086 next
= ahd_inw_scbram(ahd
, SCB_NEXT2
);
2088 ahd_set_scbptr(ahd
, scbid
);
2089 ahd_outw(ahd
, SCB_NEXT2
, next
);
2091 ahd_set_scbptr(ahd
, saved_scbptr
);
2092 if (scb
->crc_retry_count
< AHD_MAX_LQ_CRC_ERRORS
) {
2093 if (SCB_IS_SILENT(scb
) == FALSE
) {
2094 ahd_print_path(ahd
, scb
);
2095 kprintf("Probable outgoing LQ CRC error. "
2096 "Retrying command\n");
2098 scb
->crc_retry_count
++;
2100 aic_set_transaction_status(scb
, CAM_UNCOR_PARITY
);
2101 aic_freeze_scb(scb
);
2102 ahd_freeze_devq(ahd
, scb
);
2104 /* Return unpausing the sequencer. */
2106 } else if ((ahd_inb(ahd
, PERRDIAG
) & PARITYERR
) != 0) {
2108 * Ignore what are really parity errors that
2109 * occur on the last REQ of a free running
2110 * clock prior to going busfree. Some drives
2111 * do not properly active negate just before
2112 * going busfree resulting in a parity glitch.
2114 ahd_outb(ahd
, CLRSINT1
, CLRSCSIPERR
|CLRBUSFREE
);
2116 if ((ahd_debug
& AHD_SHOW_MASKED_ERRORS
) != 0)
2117 kprintf("%s: Parity on last REQ detected "
2118 "during busfree phase.\n",
2121 /* Return unpausing the sequencer. */
2124 if (ahd
->src_mode
!= AHD_MODE_SCSI
) {
2128 scbid
= ahd_get_scbptr(ahd
);
2129 scb
= ahd_lookup_scb(ahd
, scbid
);
2130 ahd_print_path(ahd
, scb
);
2131 kprintf("Unexpected PKT busfree condition\n");
2132 ahd_dump_card_state(ahd
);
2133 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
), 'A',
2134 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
2135 ROLE_INITIATOR
, CAM_UNEXP_BUSFREE
);
2137 /* Return restarting the sequencer. */
2140 kprintf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd
));
2141 ahd_dump_card_state(ahd
);
2142 /* Restart the sequencer. */
2147 * Non-packetized unexpected or expected busfree.
2150 ahd_handle_nonpkt_busfree(struct ahd_softc
*ahd
)
2152 struct ahd_devinfo devinfo
;
2158 u_int initiator_role_id
;
2164 * Look at what phase we were last in. If its message out,
2165 * chances are pretty good that the busfree was in response
2166 * to one of our abort requests.
2168 lastphase
= ahd_inb(ahd
, LASTPHASE
);
2169 saved_scsiid
= ahd_inb(ahd
, SAVED_SCSIID
);
2170 saved_lun
= ahd_inb(ahd
, SAVED_LUN
);
2171 target
= SCSIID_TARGET(ahd
, saved_scsiid
);
2172 initiator_role_id
= SCSIID_OUR_ID(saved_scsiid
);
2173 ahd_compile_devinfo(&devinfo
, initiator_role_id
,
2174 target
, saved_lun
, 'A', ROLE_INITIATOR
);
2177 scbid
= ahd_get_scbptr(ahd
);
2178 scb
= ahd_lookup_scb(ahd
, scbid
);
2180 && (ahd_inb(ahd
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
2183 ppr_busfree
= (ahd
->msg_flags
& MSG_FLAG_EXPECT_PPR_BUSFREE
) != 0;
2184 if (lastphase
== P_MESGOUT
) {
2187 tag
= SCB_LIST_NULL
;
2188 if (ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_ABORT_TAG
, TRUE
)
2189 || ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_ABORT
, TRUE
)) {
2194 ahd_print_devinfo(ahd
, &devinfo
);
2195 kprintf("Abort for unidentified "
2196 "connection completed.\n");
2197 /* restart the sequencer. */
2200 sent_msg
= ahd
->msgout_buf
[ahd
->msgout_index
- 1];
2201 ahd_print_path(ahd
, scb
);
2202 kprintf("SCB %d - Abort%s Completed.\n",
2204 sent_msg
== MSG_ABORT_TAG
? "" : " Tag");
2206 if (sent_msg
== MSG_ABORT_TAG
)
2207 tag
= SCB_GET_TAG(scb
);
2209 if ((scb
->flags
& SCB_CMDPHASE_ABORT
) != 0) {
2211 * This abort is in response to an
2212 * unexpected switch to command phase
2213 * for a packetized connection. Since
2214 * the identify message was never sent,
2215 * "saved lun" is 0. We really want to
2216 * abort only the SCB that encountered
2217 * this error, which could have a different
2218 * lun. The SCB will be retried so the OS
2219 * will see the UA after renegotiating to
2222 tag
= SCB_GET_TAG(scb
);
2223 saved_lun
= scb
->hscb
->lun
;
2225 found
= ahd_abort_scbs(ahd
, target
, 'A', saved_lun
,
2226 tag
, ROLE_INITIATOR
,
2228 kprintf("found == 0x%x\n", found
);
2230 } else if (ahd_sent_msg(ahd
, AHDMSG_1B
,
2231 MSG_BUS_DEV_RESET
, TRUE
)) {
2232 #if defined(__DragonFly__) || defined(__FreeBSD__)
2234 * Don't mark the user's request for this BDR
2235 * as completing with CAM_BDR_SENT. CAM3
2236 * specifies CAM_REQ_CMP.
2239 && scb
->io_ctx
->ccb_h
.func_code
== XPT_RESET_DEV
2240 && ahd_match_scb(ahd
, scb
, target
, 'A',
2241 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
2243 aic_set_transaction_status(scb
, CAM_REQ_CMP
);
2245 ahd_handle_devreset(ahd
, &devinfo
, CAM_LUN_WILDCARD
,
2246 CAM_BDR_SENT
, "Bus Device Reset",
2247 /*verbose_level*/0);
2249 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, FALSE
)
2250 && ppr_busfree
== 0) {
2251 struct ahd_initiator_tinfo
*tinfo
;
2252 struct ahd_tmode_tstate
*tstate
;
2257 * If the previous negotiation was packetized,
2258 * this could be because the device has been
2259 * reset without our knowledge. Force our
2260 * current negotiation to async and retry the
2261 * negotiation. Otherwise retry the command
2262 * with non-ppr negotiation.
2265 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2266 kprintf("PPR negotiation rejected busfree.\n");
2268 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
.channel
,
2270 devinfo
.target
, &tstate
);
2271 if ((tinfo
->curr
.ppr_options
& MSG_EXT_PPR_IU_REQ
)!=0) {
2272 ahd_set_width(ahd
, &devinfo
,
2273 MSG_EXT_WDTR_BUS_8_BIT
,
2276 ahd_set_syncrate(ahd
, &devinfo
,
2277 /*period*/0, /*offset*/0,
2282 * The expect PPR busfree handler below
2283 * will effect the retry and necessary
2287 tinfo
->curr
.transport_version
= 2;
2288 tinfo
->goal
.transport_version
= 2;
2289 tinfo
->goal
.ppr_options
= 0;
2291 * Remove any SCBs in the waiting for selection
2292 * queue that may also be for this target so
2293 * that command ordering is preserved.
2295 ahd_freeze_devq(ahd
, scb
);
2296 ahd_qinfifo_requeue_tail(ahd
, scb
);
2299 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, FALSE
)
2300 && ppr_busfree
== 0) {
2302 * Negotiation Rejected. Go-narrow and
2306 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2307 kprintf("WDTR negotiation rejected busfree.\n");
2309 ahd_set_width(ahd
, &devinfo
,
2310 MSG_EXT_WDTR_BUS_8_BIT
,
2311 AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
2314 * Remove any SCBs in the waiting for selection
2315 * queue that may also be for this target so that
2316 * command ordering is preserved.
2318 ahd_freeze_devq(ahd
, scb
);
2319 ahd_qinfifo_requeue_tail(ahd
, scb
);
2321 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, FALSE
)
2322 && ppr_busfree
== 0) {
2324 * Negotiation Rejected. Go-async and
2328 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2329 kprintf("SDTR negotiation rejected busfree.\n");
2331 ahd_set_syncrate(ahd
, &devinfo
,
2332 /*period*/0, /*offset*/0,
2334 AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
2337 * Remove any SCBs in the waiting for selection
2338 * queue that may also be for this target so that
2339 * command ordering is preserved.
2341 ahd_freeze_devq(ahd
, scb
);
2342 ahd_qinfifo_requeue_tail(ahd
, scb
);
2344 } else if ((ahd
->msg_flags
& MSG_FLAG_EXPECT_IDE_BUSFREE
) != 0
2345 && ahd_sent_msg(ahd
, AHDMSG_1B
,
2346 MSG_INITIATOR_DET_ERR
, TRUE
)) {
2349 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2350 kprintf("Expected IDE Busfree\n");
2353 } else if ((ahd
->msg_flags
& MSG_FLAG_EXPECT_QASREJ_BUSFREE
)
2354 && ahd_sent_msg(ahd
, AHDMSG_1B
,
2355 MSG_MESSAGE_REJECT
, TRUE
)) {
2358 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2359 kprintf("Expected QAS Reject Busfree\n");
2366 * The busfree required flag is honored at the end of
2367 * the message phases. We check it last in case we
2368 * had to send some other message that caused a busfree.
2371 && (lastphase
== P_MESGIN
|| lastphase
== P_MESGOUT
)
2372 && ((ahd
->msg_flags
& MSG_FLAG_EXPECT_PPR_BUSFREE
) != 0)) {
2374 ahd_freeze_devq(ahd
, scb
);
2375 aic_set_transaction_status(scb
, CAM_REQUEUE_REQ
);
2376 aic_freeze_scb(scb
);
2377 if ((ahd
->msg_flags
& MSG_FLAG_IU_REQ_CHANGED
) != 0) {
2378 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
),
2379 SCB_GET_CHANNEL(ahd
, scb
),
2380 SCB_GET_LUN(scb
), SCB_LIST_NULL
,
2381 ROLE_INITIATOR
, CAM_REQ_ABORTED
);
2384 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2385 kprintf("PPR Negotiation Busfree.\n");
2391 if (printerror
!= 0) {
2398 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
2399 tag
= SCB_GET_TAG(scb
);
2401 tag
= SCB_LIST_NULL
;
2402 ahd_print_path(ahd
, scb
);
2403 aborted
= ahd_abort_scbs(ahd
, target
, 'A',
2404 SCB_GET_LUN(scb
), tag
,
2409 * We had not fully identified this connection,
2410 * so we cannot abort anything.
2412 kprintf("%s: ", ahd_name(ahd
));
2414 kprintf("Unexpected busfree %s, %d SCBs aborted, "
2415 "PRGMCNT == 0x%x\n",
2416 ahd_lookup_phase_entry(lastphase
)->phasemsg
,
2418 ahd_inw(ahd
, PRGMCNT
));
2419 ahd_dump_card_state(ahd
);
2420 if (lastphase
!= P_BUSFREE
)
2421 ahd_force_renegotiation(ahd
, &devinfo
);
2423 /* Always restart the sequencer. */
2428 ahd_handle_proto_violation(struct ahd_softc
*ahd
)
2430 struct ahd_devinfo devinfo
;
2438 ahd_fetch_devinfo(ahd
, &devinfo
);
2439 scbid
= ahd_get_scbptr(ahd
);
2440 scb
= ahd_lookup_scb(ahd
, scbid
);
2441 seq_flags
= ahd_inb(ahd
, SEQ_FLAGS
);
2442 curphase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
2443 lastphase
= ahd_inb(ahd
, LASTPHASE
);
2444 if ((seq_flags
& NOT_IDENTIFIED
) != 0) {
2447 * The reconnecting target either did not send an
2448 * identify message, or did, but we didn't find an SCB
2451 ahd_print_devinfo(ahd
, &devinfo
);
2452 kprintf("Target did not send an IDENTIFY message. "
2453 "LASTPHASE = 0x%x.\n", lastphase
);
2455 } else if (scb
== NULL
) {
2457 * We don't seem to have an SCB active for this
2458 * transaction. Print an error and reset the bus.
2460 ahd_print_devinfo(ahd
, &devinfo
);
2461 kprintf("No SCB found during protocol violation\n");
2462 goto proto_violation_reset
;
2464 aic_set_transaction_status(scb
, CAM_SEQUENCE_FAIL
);
2465 if ((seq_flags
& NO_CDB_SENT
) != 0) {
2466 ahd_print_path(ahd
, scb
);
2467 kprintf("No or incomplete CDB sent to device.\n");
2468 } else if ((ahd_inb_scbram(ahd
, SCB_CONTROL
)
2469 & STATUS_RCVD
) == 0) {
2471 * The target never bothered to provide status to
2472 * us prior to completing the command. Since we don't
2473 * know the disposition of this command, we must attempt
2474 * to abort it. Assert ATN and prepare to send an abort
2477 ahd_print_path(ahd
, scb
);
2478 kprintf("Completed command without status.\n");
2480 ahd_print_path(ahd
, scb
);
2481 kprintf("Unknown protocol violation.\n");
2482 ahd_dump_card_state(ahd
);
2485 if ((lastphase
& ~P_DATAIN_DT
) == 0
2486 || lastphase
== P_COMMAND
) {
2487 proto_violation_reset
:
2489 * Target either went directly to data
2490 * phase or didn't respond to our ATN.
2491 * The only safe thing to do is to blow
2492 * it away with a bus reset.
2494 found
= ahd_reset_channel(ahd
, 'A', TRUE
);
2495 kprintf("%s: Issued Channel %c Bus Reset. "
2496 "%d SCBs aborted\n", ahd_name(ahd
), 'A', found
);
2499 * Leave the selection hardware off in case
2500 * this abort attempt will affect yet to
2503 ahd_outb(ahd
, SCSISEQ0
,
2504 ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
2505 ahd_assert_atn(ahd
);
2506 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
2508 ahd_print_devinfo(ahd
, &devinfo
);
2509 ahd
->msgout_buf
[0] = MSG_ABORT_TASK
;
2510 ahd
->msgout_len
= 1;
2511 ahd
->msgout_index
= 0;
2512 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2514 ahd_print_path(ahd
, scb
);
2515 scb
->flags
|= SCB_ABORT
;
2517 kprintf("Protocol violation %s. Attempting to abort.\n",
2518 ahd_lookup_phase_entry(curphase
)->phasemsg
);
2523 * Force renegotiation to occur the next time we initiate
2524 * a command to the current device.
2527 ahd_force_renegotiation(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
2529 struct ahd_initiator_tinfo
*targ_info
;
2530 struct ahd_tmode_tstate
*tstate
;
2533 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
2534 ahd_print_devinfo(ahd
, devinfo
);
2535 kprintf("Forcing renegotiation\n");
2538 targ_info
= ahd_fetch_transinfo(ahd
,
2540 devinfo
->our_scsiid
,
2543 ahd_update_neg_request(ahd
, devinfo
, tstate
,
2544 targ_info
, AHD_NEG_IF_NON_ASYNC
);
2547 #define AHD_MAX_STEPS 2000
2549 ahd_clear_critical_section(struct ahd_softc
*ahd
)
2551 ahd_mode_state saved_modes
;
2563 if (ahd
->num_critical_sections
== 0)
2576 saved_modes
= ahd_save_modes(ahd
);
2582 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2583 seqaddr
= ahd_inw(ahd
, CURADDR
);
2585 cs
= ahd
->critical_sections
;
2586 for (i
= 0; i
< ahd
->num_critical_sections
; i
++, cs
++) {
2588 if (cs
->begin
< seqaddr
&& cs
->end
>= seqaddr
)
2592 if (i
== ahd
->num_critical_sections
)
2595 if (steps
> AHD_MAX_STEPS
) {
2596 kprintf("%s: Infinite loop in critical section\n"
2597 "%s: First Instruction 0x%x now 0x%x\n",
2598 ahd_name(ahd
), ahd_name(ahd
), first_instr
,
2600 ahd_dump_card_state(ahd
);
2601 panic("critical section loop");
2606 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
2607 kprintf("%s: Single stepping at 0x%x\n", ahd_name(ahd
),
2610 if (stepping
== FALSE
) {
2612 first_instr
= seqaddr
;
2613 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
2614 simode0
= ahd_inb(ahd
, SIMODE0
);
2615 simode3
= ahd_inb(ahd
, SIMODE3
);
2616 lqimode0
= ahd_inb(ahd
, LQIMODE0
);
2617 lqimode1
= ahd_inb(ahd
, LQIMODE1
);
2618 lqomode0
= ahd_inb(ahd
, LQOMODE0
);
2619 lqomode1
= ahd_inb(ahd
, LQOMODE1
);
2620 ahd_outb(ahd
, SIMODE0
, 0);
2621 ahd_outb(ahd
, SIMODE3
, 0);
2622 ahd_outb(ahd
, LQIMODE0
, 0);
2623 ahd_outb(ahd
, LQIMODE1
, 0);
2624 ahd_outb(ahd
, LQOMODE0
, 0);
2625 ahd_outb(ahd
, LQOMODE1
, 0);
2626 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2627 simode1
= ahd_inb(ahd
, SIMODE1
);
2629 * We don't clear ENBUSFREE. Unfortunately
2630 * we cannot re-enable busfree detection within
2631 * the current connection, so we must leave it
2632 * on while single stepping.
2634 ahd_outb(ahd
, SIMODE1
, simode1
& ENBUSFREE
);
2635 ahd_outb(ahd
, SEQCTL0
, ahd_inb(ahd
, SEQCTL0
) | STEP
);
2638 ahd_outb(ahd
, CLRSINT1
, CLRBUSFREE
);
2639 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2640 ahd_set_modes(ahd
, ahd
->saved_src_mode
, ahd
->saved_dst_mode
);
2641 ahd_outb(ahd
, HCNTRL
, ahd
->unpause
);
2642 while (!ahd_is_paused(ahd
))
2644 ahd_update_modes(ahd
);
2647 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
2648 ahd_outb(ahd
, SIMODE0
, simode0
);
2649 ahd_outb(ahd
, SIMODE3
, simode3
);
2650 ahd_outb(ahd
, LQIMODE0
, lqimode0
);
2651 ahd_outb(ahd
, LQIMODE1
, lqimode1
);
2652 ahd_outb(ahd
, LQOMODE0
, lqomode0
);
2653 ahd_outb(ahd
, LQOMODE1
, lqomode1
);
2654 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2655 ahd_outb(ahd
, SEQCTL0
, ahd_inb(ahd
, SEQCTL0
) & ~STEP
);
2656 ahd_outb(ahd
, SIMODE1
, simode1
);
2658 * SCSIINT seems to glitch occassionally when
2659 * the interrupt masks are restored. Clear SCSIINT
2660 * one more time so that only persistent errors
2661 * are seen as a real interrupt.
2663 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2665 ahd_restore_modes(ahd
, saved_modes
);
2669 * Clear any pending interrupt status.
2672 ahd_clear_intstat(struct ahd_softc
*ahd
)
2674 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
2675 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
2676 /* Clear any interrupt conditions this may have caused */
2677 ahd_outb(ahd
, CLRLQIINT0
, CLRLQIATNQAS
|CLRLQICRCT1
|CLRLQICRCT2
2678 |CLRLQIBADLQT
|CLRLQIATNLQ
|CLRLQIATNCMD
);
2679 ahd_outb(ahd
, CLRLQIINT1
, CLRLQIPHASE_LQ
|CLRLQIPHASE_NLQ
|CLRLIQABORT
2680 |CLRLQICRCI_LQ
|CLRLQICRCI_NLQ
|CLRLQIBADLQI
2681 |CLRLQIOVERI_LQ
|CLRLQIOVERI_NLQ
|CLRNONPACKREQ
);
2682 ahd_outb(ahd
, CLRLQOINT0
, CLRLQOTARGSCBPERR
|CLRLQOSTOPT2
|CLRLQOATNLQ
2683 |CLRLQOATNPKT
|CLRLQOTCRC
);
2684 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOINITSCBPERR
|CLRLQOSTOPI2
|CLRLQOBADQAS
2685 |CLRLQOBUSFREE
|CLRLQOPHACHGINPKT
);
2686 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0) {
2687 ahd_outb(ahd
, CLRLQOINT0
, 0);
2688 ahd_outb(ahd
, CLRLQOINT1
, 0);
2690 ahd_outb(ahd
, CLRSINT3
, CLRNTRAMPERR
|CLROSRAMPERR
);
2691 ahd_outb(ahd
, CLRSINT1
, CLRSELTIMEO
|CLRATNO
|CLRSCSIRSTI
2692 |CLRBUSFREE
|CLRSCSIPERR
|CLRREQINIT
);
2693 ahd_outb(ahd
, CLRSINT0
, CLRSELDO
|CLRSELDI
|CLRSELINGO
2694 |CLRIOERR
|CLROVERRUN
);
2695 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2698 /**************************** Debugging Routines ******************************/
2700 uint32_t ahd_debug
= AHD_DEBUG_OPTS
;
2703 ahd_print_scb(struct scb
*scb
)
2705 struct hardware_scb
*hscb
;
2709 kprintf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2715 kprintf("Shared Data: ");
2716 for (i
= 0; i
< sizeof(hscb
->shared_data
.idata
.cdb
); i
++)
2717 kprintf("%#02x", hscb
->shared_data
.idata
.cdb
[i
]);
2718 kprintf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2719 (uint32_t)((aic_le64toh(hscb
->dataptr
) >> 32) & 0xFFFFFFFF),
2720 (uint32_t)(aic_le64toh(hscb
->dataptr
) & 0xFFFFFFFF),
2721 aic_le32toh(hscb
->datacnt
),
2722 aic_le32toh(hscb
->sgptr
),
2724 ahd_dump_sglist(scb
);
2728 ahd_dump_sglist(struct scb
*scb
)
2732 if (scb
->sg_count
> 0) {
2733 if ((scb
->ahd_softc
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
2734 struct ahd_dma64_seg
*sg_list
;
2736 sg_list
= (struct ahd_dma64_seg
*)scb
->sg_list
;
2737 for (i
= 0; i
< scb
->sg_count
; i
++) {
2741 addr
= aic_le64toh(sg_list
[i
].addr
);
2742 len
= aic_le32toh(sg_list
[i
].len
);
2743 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2745 (uint32_t)((addr
>> 32) & 0xFFFFFFFF),
2746 (uint32_t)(addr
& 0xFFFFFFFF),
2747 sg_list
[i
].len
& AHD_SG_LEN_MASK
,
2748 (sg_list
[i
].len
& AHD_DMA_LAST_SEG
)
2752 struct ahd_dma_seg
*sg_list
;
2754 sg_list
= (struct ahd_dma_seg
*)scb
->sg_list
;
2755 for (i
= 0; i
< scb
->sg_count
; i
++) {
2758 len
= aic_le32toh(sg_list
[i
].len
);
2759 kprintf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2761 (len
& AHD_SG_HIGH_ADDR_MASK
) >> 24,
2762 aic_le32toh(sg_list
[i
].addr
),
2763 len
& AHD_SG_LEN_MASK
,
2764 len
& AHD_DMA_LAST_SEG
? " Last" : "");
2770 /************************* Transfer Negotiation *******************************/
2772 * Allocate per target mode instance (ID we respond to as a target)
2773 * transfer negotiation data structures.
2775 static struct ahd_tmode_tstate
*
2776 ahd_alloc_tstate(struct ahd_softc
*ahd
, u_int scsi_id
, char channel
)
2778 struct ahd_tmode_tstate
*master_tstate
;
2779 struct ahd_tmode_tstate
*tstate
;
2782 master_tstate
= ahd
->enabled_targets
[ahd
->our_id
];
2783 if (ahd
->enabled_targets
[scsi_id
] != NULL
2784 && ahd
->enabled_targets
[scsi_id
] != master_tstate
)
2785 panic("%s: ahd_alloc_tstate - Target already allocated",
2787 tstate
= kmalloc(sizeof(*tstate
), M_DEVBUF
, M_INTWAIT
);
2790 * If we have allocated a master tstate, copy user settings from
2791 * the master tstate (taken from SRAM or the EEPROM) for this
2792 * channel, but reset our current and goal settings to async/narrow
2793 * until an initiator talks to us.
2795 if (master_tstate
!= NULL
) {
2796 memcpy(tstate
, master_tstate
, sizeof(*tstate
));
2797 memset(tstate
->enabled_luns
, 0, sizeof(tstate
->enabled_luns
));
2798 for (i
= 0; i
< 16; i
++) {
2799 memset(&tstate
->transinfo
[i
].curr
, 0,
2800 sizeof(tstate
->transinfo
[i
].curr
));
2801 memset(&tstate
->transinfo
[i
].goal
, 0,
2802 sizeof(tstate
->transinfo
[i
].goal
));
2805 memset(tstate
, 0, sizeof(*tstate
));
2806 ahd
->enabled_targets
[scsi_id
] = tstate
;
2810 #ifdef AHD_TARGET_MODE
2812 * Free per target mode instance (ID we respond to as a target)
2813 * transfer negotiation data structures.
2816 ahd_free_tstate(struct ahd_softc
*ahd
, u_int scsi_id
, char channel
, int force
)
2818 struct ahd_tmode_tstate
*tstate
;
2821 * Don't clean up our "master" tstate.
2822 * It has our default user settings.
2824 if (scsi_id
== ahd
->our_id
2828 tstate
= ahd
->enabled_targets
[scsi_id
];
2830 kfree(tstate
, M_DEVBUF
);
2831 ahd
->enabled_targets
[scsi_id
] = NULL
;
2836 * Called when we have an active connection to a target on the bus,
2837 * this function finds the nearest period to the input period limited
2838 * by the capabilities of the bus connectivity of and sync settings for
2842 ahd_devlimited_syncrate(struct ahd_softc
*ahd
,
2843 struct ahd_initiator_tinfo
*tinfo
,
2844 u_int
*period
, u_int
*ppr_options
, role_t role
)
2846 struct ahd_transinfo
*transinfo
;
2849 if ((ahd_inb(ahd
, SBLKCTL
) & ENAB40
) != 0
2850 && (ahd_inb(ahd
, SSTAT2
) & EXP_ACTIVE
) == 0) {
2851 maxsync
= AHD_SYNCRATE_PACED
;
2853 maxsync
= AHD_SYNCRATE_ULTRA
;
2854 /* Can't do DT related options on an SE bus */
2855 *ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
2858 * Never allow a value higher than our current goal
2859 * period otherwise we may allow a target initiated
2860 * negotiation to go above the limit as set by the
2861 * user. In the case of an initiator initiated
2862 * sync negotiation, we limit based on the user
2863 * setting. This allows the system to still accept
2864 * incoming negotiations even if target initiated
2865 * negotiation is not performed.
2867 if (role
== ROLE_TARGET
)
2868 transinfo
= &tinfo
->user
;
2870 transinfo
= &tinfo
->goal
;
2871 *ppr_options
&= (transinfo
->ppr_options
|MSG_EXT_PPR_PCOMP_EN
);
2872 if (transinfo
->width
== MSG_EXT_WDTR_BUS_8_BIT
) {
2873 maxsync
= MAX(maxsync
, AHD_SYNCRATE_ULTRA2
);
2874 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
2876 if (transinfo
->period
== 0) {
2880 *period
= MAX(*period
, transinfo
->period
);
2881 ahd_find_syncrate(ahd
, period
, ppr_options
, maxsync
);
2886 * Look up the valid period to SCSIRATE conversion in our table.
2887 * Return the period and offset that should be sent to the target
2888 * if this was the beginning of an SDTR.
2891 ahd_find_syncrate(struct ahd_softc
*ahd
, u_int
*period
,
2892 u_int
*ppr_options
, u_int maxsync
)
2894 if (*period
< maxsync
)
2897 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0
2898 && *period
> AHD_SYNCRATE_MIN_DT
)
2899 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
2901 if (*period
> AHD_SYNCRATE_MIN
)
2904 /* Honor PPR option conformance rules. */
2905 if (*period
> AHD_SYNCRATE_PACED
)
2906 *ppr_options
&= ~MSG_EXT_PPR_RTI
;
2908 if ((*ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0)
2909 *ppr_options
&= (MSG_EXT_PPR_DT_REQ
|MSG_EXT_PPR_QAS_REQ
);
2911 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0)
2912 *ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
2914 /* Skip all PACED only entries if IU is not available */
2915 if ((*ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0
2916 && *period
< AHD_SYNCRATE_DT
)
2917 *period
= AHD_SYNCRATE_DT
;
2919 /* Skip all DT only entries if DT is not available */
2920 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
2921 && *period
< AHD_SYNCRATE_ULTRA2
)
2922 *period
= AHD_SYNCRATE_ULTRA2
;
2926 * Truncate the given synchronous offset to a value the
2927 * current adapter type and syncrate are capable of.
2930 ahd_validate_offset(struct ahd_softc
*ahd
,
2931 struct ahd_initiator_tinfo
*tinfo
,
2932 u_int period
, u_int
*offset
, int wide
,
2937 /* Limit offset to what we can do */
2940 else if (period
<= AHD_SYNCRATE_PACED
) {
2941 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0)
2942 maxoffset
= MAX_OFFSET_PACED_BUG
;
2944 maxoffset
= MAX_OFFSET_PACED
;
2946 maxoffset
= MAX_OFFSET_NON_PACED
;
2947 *offset
= MIN(*offset
, maxoffset
);
2948 if (tinfo
!= NULL
) {
2949 if (role
== ROLE_TARGET
)
2950 *offset
= MIN(*offset
, tinfo
->user
.offset
);
2952 *offset
= MIN(*offset
, tinfo
->goal
.offset
);
2957 * Truncate the given transfer width parameter to a value the
2958 * current adapter type is capable of.
2961 ahd_validate_width(struct ahd_softc
*ahd
, struct ahd_initiator_tinfo
*tinfo
,
2962 u_int
*bus_width
, role_t role
)
2964 switch (*bus_width
) {
2966 if (ahd
->features
& AHD_WIDE
) {
2968 *bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
2972 case MSG_EXT_WDTR_BUS_8_BIT
:
2973 *bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
2976 if (tinfo
!= NULL
) {
2977 if (role
== ROLE_TARGET
)
2978 *bus_width
= MIN(tinfo
->user
.width
, *bus_width
);
2980 *bus_width
= MIN(tinfo
->goal
.width
, *bus_width
);
2985 * Update the bitmask of targets for which the controller should
2986 * negotiate with at the next convenient oportunity. This currently
2987 * means the next time we send the initial identify messages for
2988 * a new transaction.
2991 ahd_update_neg_request(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
2992 struct ahd_tmode_tstate
*tstate
,
2993 struct ahd_initiator_tinfo
*tinfo
, ahd_neg_type neg_type
)
2995 u_int auto_negotiate_orig
;
2997 auto_negotiate_orig
= tstate
->auto_negotiate
;
2998 if (neg_type
== AHD_NEG_ALWAYS
) {
3000 * Force our "current" settings to be
3001 * unknown so that unless a bus reset
3002 * occurs the need to renegotiate is
3003 * recorded persistently.
3005 if ((ahd
->features
& AHD_WIDE
) != 0)
3006 tinfo
->curr
.width
= AHD_WIDTH_UNKNOWN
;
3007 tinfo
->curr
.period
= AHD_PERIOD_UNKNOWN
;
3008 tinfo
->curr
.offset
= AHD_OFFSET_UNKNOWN
;
3010 if (tinfo
->curr
.period
!= tinfo
->goal
.period
3011 || tinfo
->curr
.width
!= tinfo
->goal
.width
3012 || tinfo
->curr
.offset
!= tinfo
->goal
.offset
3013 || tinfo
->curr
.ppr_options
!= tinfo
->goal
.ppr_options
3014 || (neg_type
== AHD_NEG_IF_NON_ASYNC
3015 && (tinfo
->goal
.offset
!= 0
3016 || tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
3017 || tinfo
->goal
.ppr_options
!= 0)))
3018 tstate
->auto_negotiate
|= devinfo
->target_mask
;
3020 tstate
->auto_negotiate
&= ~devinfo
->target_mask
;
3022 return (auto_negotiate_orig
!= tstate
->auto_negotiate
);
3026 * Update the user/goal/curr tables of synchronous negotiation
3027 * parameters as well as, in the case of a current or active update,
3028 * any data structures on the host controller. In the case of an
3029 * active update, the specified target is currently talking to us on
3030 * the bus, so the transfer parameter update must take effect
3034 ahd_set_syncrate(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3035 u_int period
, u_int offset
, u_int ppr_options
,
3036 u_int type
, int paused
)
3038 struct ahd_initiator_tinfo
*tinfo
;
3039 struct ahd_tmode_tstate
*tstate
;
3046 active
= (type
& AHD_TRANS_ACTIVE
) == AHD_TRANS_ACTIVE
;
3049 if (period
== 0 || offset
== 0) {
3054 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3055 devinfo
->target
, &tstate
);
3057 if ((type
& AHD_TRANS_USER
) != 0) {
3058 tinfo
->user
.period
= period
;
3059 tinfo
->user
.offset
= offset
;
3060 tinfo
->user
.ppr_options
= ppr_options
;
3063 if ((type
& AHD_TRANS_GOAL
) != 0) {
3064 tinfo
->goal
.period
= period
;
3065 tinfo
->goal
.offset
= offset
;
3066 tinfo
->goal
.ppr_options
= ppr_options
;
3069 old_period
= tinfo
->curr
.period
;
3070 old_offset
= tinfo
->curr
.offset
;
3071 old_ppr
= tinfo
->curr
.ppr_options
;
3073 if ((type
& AHD_TRANS_CUR
) != 0
3074 && (old_period
!= period
3075 || old_offset
!= offset
3076 || old_ppr
!= ppr_options
)) {
3080 tinfo
->curr
.period
= period
;
3081 tinfo
->curr
.offset
= offset
;
3082 tinfo
->curr
.ppr_options
= ppr_options
;
3084 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3085 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
3090 kprintf("%s: target %d synchronous with "
3091 "period = 0x%x, offset = 0x%x",
3092 ahd_name(ahd
), devinfo
->target
,
3095 if ((ppr_options
& MSG_EXT_PPR_RD_STRM
) != 0) {
3099 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0) {
3100 kprintf("%s", options
? "|DT" : "(DT");
3103 if ((ppr_options
& MSG_EXT_PPR_IU_REQ
) != 0) {
3104 kprintf("%s", options
? "|IU" : "(IU");
3107 if ((ppr_options
& MSG_EXT_PPR_RTI
) != 0) {
3108 kprintf("%s", options
? "|RTI" : "(RTI");
3111 if ((ppr_options
& MSG_EXT_PPR_QAS_REQ
) != 0) {
3112 kprintf("%s", options
? "|QAS" : "(QAS");
3120 kprintf("%s: target %d using "
3121 "asynchronous transfers%s\n",
3122 ahd_name(ahd
), devinfo
->target
,
3123 (ppr_options
& MSG_EXT_PPR_QAS_REQ
) != 0
3129 * Always refresh the neg-table to handle the case of the
3130 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3131 * We will always renegotiate in that case if this is a
3132 * packetized request. Also manage the busfree expected flag
3133 * from this common routine so that we catch changes due to
3134 * WDTR or SDTR messages.
3136 if ((type
& AHD_TRANS_CUR
) != 0) {
3139 ahd_update_neg_table(ahd
, devinfo
, &tinfo
->curr
);
3142 if (ahd
->msg_type
!= MSG_TYPE_NONE
) {
3143 if ((old_ppr
& MSG_EXT_PPR_IU_REQ
)
3144 != (ppr_options
& MSG_EXT_PPR_IU_REQ
)) {
3146 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3147 ahd_print_devinfo(ahd
, devinfo
);
3148 kprintf("Expecting IU Change busfree\n");
3151 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
3152 | MSG_FLAG_IU_REQ_CHANGED
;
3154 if ((old_ppr
& MSG_EXT_PPR_IU_REQ
) != 0) {
3156 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3157 kprintf("PPR with IU_REQ outstanding\n");
3159 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
;
3164 update_needed
+= ahd_update_neg_request(ahd
, devinfo
, tstate
,
3165 tinfo
, AHD_NEG_TO_GOAL
);
3167 if (update_needed
&& active
)
3168 ahd_update_pending_scbs(ahd
);
3172 * Update the user/goal/curr tables of wide negotiation
3173 * parameters as well as, in the case of a current or active update,
3174 * any data structures on the host controller. In the case of an
3175 * active update, the specified target is currently talking to us on
3176 * the bus, so the transfer parameter update must take effect
3180 ahd_set_width(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3181 u_int width
, u_int type
, int paused
)
3183 struct ahd_initiator_tinfo
*tinfo
;
3184 struct ahd_tmode_tstate
*tstate
;
3189 active
= (type
& AHD_TRANS_ACTIVE
) == AHD_TRANS_ACTIVE
;
3191 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3192 devinfo
->target
, &tstate
);
3194 if ((type
& AHD_TRANS_USER
) != 0)
3195 tinfo
->user
.width
= width
;
3197 if ((type
& AHD_TRANS_GOAL
) != 0)
3198 tinfo
->goal
.width
= width
;
3200 oldwidth
= tinfo
->curr
.width
;
3201 if ((type
& AHD_TRANS_CUR
) != 0 && oldwidth
!= width
) {
3205 tinfo
->curr
.width
= width
;
3206 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3207 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
3209 kprintf("%s: target %d using %dbit transfers\n",
3210 ahd_name(ahd
), devinfo
->target
,
3211 8 * (0x01 << width
));
3215 if ((type
& AHD_TRANS_CUR
) != 0) {
3218 ahd_update_neg_table(ahd
, devinfo
, &tinfo
->curr
);
3223 update_needed
+= ahd_update_neg_request(ahd
, devinfo
, tstate
,
3224 tinfo
, AHD_NEG_TO_GOAL
);
3225 if (update_needed
&& active
)
3226 ahd_update_pending_scbs(ahd
);
3231 * Update the current state of tagged queuing for a given target.
3234 ahd_set_tags(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3237 ahd_platform_set_tags(ahd
, devinfo
, alg
);
3238 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3239 devinfo
->lun
, AC_TRANSFER_NEG
, &alg
);
3243 ahd_update_neg_table(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3244 struct ahd_transinfo
*tinfo
)
3246 ahd_mode_state saved_modes
;
3251 u_int saved_negoaddr
;
3252 uint8_t iocell_opts
[sizeof(ahd
->iocell_opts
)];
3254 saved_modes
= ahd_save_modes(ahd
);
3255 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3257 saved_negoaddr
= ahd_inb(ahd
, NEGOADDR
);
3258 ahd_outb(ahd
, NEGOADDR
, devinfo
->target
);
3259 period
= tinfo
->period
;
3260 offset
= tinfo
->offset
;
3261 memcpy(iocell_opts
, ahd
->iocell_opts
, sizeof(ahd
->iocell_opts
));
3262 ppr_opts
= tinfo
->ppr_options
& (MSG_EXT_PPR_QAS_REQ
|MSG_EXT_PPR_DT_REQ
3263 |MSG_EXT_PPR_IU_REQ
|MSG_EXT_PPR_RTI
);
3266 period
= AHD_SYNCRATE_ASYNC
;
3267 if (period
== AHD_SYNCRATE_160
) {
3269 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0) {
3271 * When the SPI4 spec was finalized, PACE transfers
3272 * was not made a configurable option in the PPR
3273 * message. Instead it is assumed to be enabled for
3274 * any syncrate faster than 80MHz. Nevertheless,
3275 * Harpoon2A4 allows this to be configurable.
3277 * Harpoon2A4 also assumes at most 2 data bytes per
3278 * negotiated REQ/ACK offset. Paced transfers take
3279 * 4, so we must adjust our offset.
3281 ppr_opts
|= PPROPT_PACE
;
3285 * Harpoon2A assumed that there would be a
3286 * fallback rate between 160MHz and 80Mhz,
3287 * so 7 is used as the period factor rather
3288 * than 8 for 160MHz.
3290 period
= AHD_SYNCRATE_REVA_160
;
3292 if ((tinfo
->ppr_options
& MSG_EXT_PPR_PCOMP_EN
) == 0)
3293 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &=
3297 * Precomp should be disabled for non-paced transfers.
3299 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &= ~AHD_PRECOMP_MASK
;
3301 if ((ahd
->features
& AHD_NEW_IOCELL_OPTS
) != 0
3302 && (ppr_opts
& MSG_EXT_PPR_DT_REQ
) != 0
3303 && (ppr_opts
& MSG_EXT_PPR_IU_REQ
) == 0) {
3305 * Slow down our CRC interval to be
3306 * compatible with non-packetized
3307 * U160 devices that can't handle a
3308 * CRC at full speed.
3310 con_opts
|= ENSLOWCRC
;
3313 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0) {
3315 * On H2A4, revert to a slower slewrate
3316 * on non-paced transfers.
3318 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &=
3323 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_PRECOMP_SLEW
);
3324 ahd_outb(ahd
, ANNEXDAT
, iocell_opts
[AHD_PRECOMP_SLEW_INDEX
]);
3325 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_AMPLITUDE
);
3326 ahd_outb(ahd
, ANNEXDAT
, iocell_opts
[AHD_AMPLITUDE_INDEX
]);
3328 ahd_outb(ahd
, NEGPERIOD
, period
);
3329 ahd_outb(ahd
, NEGPPROPTS
, ppr_opts
);
3330 ahd_outb(ahd
, NEGOFFSET
, offset
);
3332 if (tinfo
->width
== MSG_EXT_WDTR_BUS_16_BIT
)
3333 con_opts
|= WIDEXFER
;
3336 * During packetized transfers, the target will
3337 * give us the oportunity to send command packets
3338 * without us asserting attention.
3340 if ((tinfo
->ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0)
3341 con_opts
|= ENAUTOATNO
;
3342 ahd_outb(ahd
, NEGCONOPTS
, con_opts
);
3343 ahd_outb(ahd
, NEGOADDR
, saved_negoaddr
);
3344 ahd_restore_modes(ahd
, saved_modes
);
3348 * When the transfer settings for a connection change, setup for
3349 * negotiation in pending SCBs to effect the change as quickly as
3350 * possible. We also cancel any negotiations that are scheduled
3351 * for inflight SCBs that have not been started yet.
3354 ahd_update_pending_scbs(struct ahd_softc
*ahd
)
3356 struct scb
*pending_scb
;
3357 int pending_scb_count
;
3360 ahd_mode_state saved_modes
;
3363 * Traverse the pending SCB list and ensure that all of the
3364 * SCBs there have the proper settings. We can only safely
3365 * clear the negotiation required flag (setting requires the
3366 * execution queue to be modified) and this is only possible
3367 * if we are not already attempting to select out for this
3368 * SCB. For this reason, all callers only call this routine
3369 * if we are changing the negotiation settings for the currently
3370 * active transaction on the bus.
3372 pending_scb_count
= 0;
3373 LIST_FOREACH(pending_scb
, &ahd
->pending_scbs
, pending_links
) {
3374 struct ahd_devinfo devinfo
;
3375 struct ahd_initiator_tinfo
*tinfo
;
3376 struct ahd_tmode_tstate
*tstate
;
3378 ahd_scb_devinfo(ahd
, &devinfo
, pending_scb
);
3379 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
.channel
,
3381 devinfo
.target
, &tstate
);
3382 if ((tstate
->auto_negotiate
& devinfo
.target_mask
) == 0
3383 && (pending_scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0) {
3384 pending_scb
->flags
&= ~SCB_AUTO_NEGOTIATE
;
3385 pending_scb
->hscb
->control
&= ~MK_MESSAGE
;
3387 ahd_sync_scb(ahd
, pending_scb
,
3388 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
3389 pending_scb_count
++;
3392 if (pending_scb_count
== 0)
3395 if (ahd_is_paused(ahd
)) {
3403 * Force the sequencer to reinitialize the selection for
3404 * the command at the head of the execution queue if it
3405 * has already been setup. The negotiation changes may
3406 * effect whether we select-out with ATN. It is only
3407 * safe to clear ENSELO when the bus is not free and no
3408 * selection is in progres or completed.
3410 saved_modes
= ahd_save_modes(ahd
);
3411 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3412 if ((ahd_inb(ahd
, SCSISIGI
) & BSYI
) != 0
3413 && (ahd_inb(ahd
, SSTAT0
) & (SELDO
|SELINGO
)) == 0)
3414 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
3415 saved_scbptr
= ahd_get_scbptr(ahd
);
3416 /* Ensure that the hscbs down on the card match the new information */
3417 LIST_FOREACH(pending_scb
, &ahd
->pending_scbs
, pending_links
) {
3421 scb_tag
= SCB_GET_TAG(pending_scb
);
3422 ahd_set_scbptr(ahd
, scb_tag
);
3423 control
= ahd_inb_scbram(ahd
, SCB_CONTROL
);
3424 control
&= ~MK_MESSAGE
;
3425 control
|= pending_scb
->hscb
->control
& MK_MESSAGE
;
3426 ahd_outb(ahd
, SCB_CONTROL
, control
);
3428 ahd_set_scbptr(ahd
, saved_scbptr
);
3429 ahd_restore_modes(ahd
, saved_modes
);
3435 /**************************** Pathing Information *****************************/
3437 ahd_fetch_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3439 ahd_mode_state saved_modes
;
3444 saved_modes
= ahd_save_modes(ahd
);
3445 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3447 if (ahd_inb(ahd
, SSTAT0
) & TARGET
)
3450 role
= ROLE_INITIATOR
;
3452 if (role
== ROLE_TARGET
3453 && (ahd_inb(ahd
, SEQ_FLAGS
) & CMDPHASE_PENDING
) != 0) {
3454 /* We were selected, so pull our id from TARGIDIN */
3455 our_id
= ahd_inb(ahd
, TARGIDIN
) & OID
;
3456 } else if (role
== ROLE_TARGET
)
3457 our_id
= ahd_inb(ahd
, TOWNID
);
3459 our_id
= ahd_inb(ahd
, IOWNID
);
3461 saved_scsiid
= ahd_inb(ahd
, SAVED_SCSIID
);
3462 ahd_compile_devinfo(devinfo
,
3464 SCSIID_TARGET(ahd
, saved_scsiid
),
3465 ahd_inb(ahd
, SAVED_LUN
),
3466 SCSIID_CHANNEL(ahd
, saved_scsiid
),
3468 ahd_restore_modes(ahd
, saved_modes
);
3472 ahd_print_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3474 kprintf("%s:%c:%d:%d: ", ahd_name(ahd
), 'A',
3475 devinfo
->target
, devinfo
->lun
);
3478 struct ahd_phase_table_entry
*
3479 ahd_lookup_phase_entry(int phase
)
3481 struct ahd_phase_table_entry
*entry
;
3482 struct ahd_phase_table_entry
*last_entry
;
3485 * num_phases doesn't include the default entry which
3486 * will be returned if the phase doesn't match.
3488 last_entry
= &ahd_phase_table
[num_phases
];
3489 for (entry
= ahd_phase_table
; entry
< last_entry
; entry
++) {
3490 if (phase
== entry
->phase
)
3497 ahd_compile_devinfo(struct ahd_devinfo
*devinfo
, u_int our_id
, u_int target
,
3498 u_int lun
, char channel
, role_t role
)
3500 devinfo
->our_scsiid
= our_id
;
3501 devinfo
->target
= target
;
3503 devinfo
->target_offset
= target
;
3504 devinfo
->channel
= channel
;
3505 devinfo
->role
= role
;
3507 devinfo
->target_offset
+= 8;
3508 devinfo
->target_mask
= (0x01 << devinfo
->target_offset
);
3512 ahd_scb_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3518 our_id
= SCSIID_OUR_ID(scb
->hscb
->scsiid
);
3519 role
= ROLE_INITIATOR
;
3520 if ((scb
->hscb
->control
& TARGET_SCB
) != 0)
3522 ahd_compile_devinfo(devinfo
, our_id
, SCB_GET_TARGET(ahd
, scb
),
3523 SCB_GET_LUN(scb
), SCB_GET_CHANNEL(ahd
, scb
), role
);
3527 /************************ Message Phase Processing ****************************/
3529 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3530 * or enters the initial message out phase, we are interrupted. Fill our
3531 * outgoing message buffer with the appropriate message and beging handing
3532 * the message phase(s) manually.
3535 ahd_setup_initiator_msgout(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3539 * To facilitate adding multiple messages together,
3540 * each routine should increment the index and len
3541 * variables instead of setting them explicitly.
3543 ahd
->msgout_index
= 0;
3544 ahd
->msgout_len
= 0;
3546 if (ahd_currently_packetized(ahd
))
3547 ahd
->msg_flags
|= MSG_FLAG_PACKETIZED
;
3549 if (ahd
->send_msg_perror
3550 && ahd_inb(ahd
, MSG_OUT
) == HOST_MSG
) {
3551 ahd
->msgout_buf
[ahd
->msgout_index
++] = ahd
->send_msg_perror
;
3553 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3555 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3556 kprintf("Setting up for Parity Error delivery\n");
3559 } else if (scb
== NULL
) {
3560 kprintf("%s: WARNING. No pending message for "
3561 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd
));
3562 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_NOOP
;
3564 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3568 if ((scb
->flags
& SCB_DEVICE_RESET
) == 0
3569 && (scb
->flags
& SCB_PACKETIZED
) == 0
3570 && ahd_inb(ahd
, MSG_OUT
) == MSG_IDENTIFYFLAG
) {
3573 identify_msg
= MSG_IDENTIFYFLAG
| SCB_GET_LUN(scb
);
3574 if ((scb
->hscb
->control
& DISCENB
) != 0)
3575 identify_msg
|= MSG_IDENTIFY_DISCFLAG
;
3576 ahd
->msgout_buf
[ahd
->msgout_index
++] = identify_msg
;
3579 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
3580 ahd
->msgout_buf
[ahd
->msgout_index
++] =
3581 scb
->hscb
->control
& (TAG_ENB
|SCB_TAG_TYPE
);
3582 ahd
->msgout_buf
[ahd
->msgout_index
++] = SCB_GET_TAG(scb
);
3583 ahd
->msgout_len
+= 2;
3587 if (scb
->flags
& SCB_DEVICE_RESET
) {
3588 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_BUS_DEV_RESET
;
3590 ahd_print_path(ahd
, scb
);
3591 kprintf("Bus Device Reset Message Sent\n");
3593 * Clear our selection hardware in advance of
3594 * the busfree. We may have an entry in the waiting
3595 * Q for this target, and we don't want to go about
3596 * selecting while we handle the busfree and blow it
3599 ahd_outb(ahd
, SCSISEQ0
, 0);
3600 } else if ((scb
->flags
& SCB_ABORT
) != 0) {
3602 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
3603 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_ABORT_TAG
;
3605 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_ABORT
;
3608 ahd_print_path(ahd
, scb
);
3609 kprintf("Abort%s Message Sent\n",
3610 (scb
->hscb
->control
& TAG_ENB
) != 0 ? " Tag" : "");
3612 * Clear our selection hardware in advance of
3613 * the busfree. We may have an entry in the waiting
3614 * Q for this target, and we don't want to go about
3615 * selecting while we handle the busfree and blow it
3618 ahd_outb(ahd
, SCSISEQ0
, 0);
3619 } else if ((scb
->flags
& (SCB_AUTO_NEGOTIATE
|SCB_NEGOTIATE
)) != 0) {
3620 ahd_build_transfer_msg(ahd
, devinfo
);
3622 * Clear our selection hardware in advance of potential
3623 * PPR IU status change busfree. We may have an entry in
3624 * the waiting Q for this target, and we don't want to go
3625 * about selecting while we handle the busfree and blow
3628 ahd_outb(ahd
, SCSISEQ0
, 0);
3630 kprintf("ahd_intr: AWAITING_MSG for an SCB that "
3631 "does not have a waiting message\n");
3632 kprintf("SCSIID = %x, target_mask = %x\n", scb
->hscb
->scsiid
,
3633 devinfo
->target_mask
);
3634 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3635 "SCB flags = %x", SCB_GET_TAG(scb
), scb
->hscb
->control
,
3636 ahd_inb_scbram(ahd
, SCB_CONTROL
), ahd_inb(ahd
, MSG_OUT
),
3641 * Clear the MK_MESSAGE flag from the SCB so we aren't
3642 * asked to send this message again.
3644 ahd_outb(ahd
, SCB_CONTROL
,
3645 ahd_inb_scbram(ahd
, SCB_CONTROL
) & ~MK_MESSAGE
);
3646 scb
->hscb
->control
&= ~MK_MESSAGE
;
3647 ahd
->msgout_index
= 0;
3648 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3652 * Build an appropriate transfer negotiation message for the
3653 * currently active target.
3656 ahd_build_transfer_msg(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3659 * We need to initiate transfer negotiations.
3660 * If our current and goal settings are identical,
3661 * we want to renegotiate due to a check condition.
3663 struct ahd_initiator_tinfo
*tinfo
;
3664 struct ahd_tmode_tstate
*tstate
;
3672 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3673 devinfo
->target
, &tstate
);
3675 * Filter our period based on the current connection.
3676 * If we can't perform DT transfers on this segment (not in LVD
3677 * mode for instance), then our decision to issue a PPR message
3680 period
= tinfo
->goal
.period
;
3681 offset
= tinfo
->goal
.offset
;
3682 ppr_options
= tinfo
->goal
.ppr_options
;
3683 /* Target initiated PPR is not allowed in the SCSI spec */
3684 if (devinfo
->role
== ROLE_TARGET
)
3686 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
3687 &ppr_options
, devinfo
->role
);
3688 dowide
= tinfo
->curr
.width
!= tinfo
->goal
.width
;
3689 dosync
= tinfo
->curr
.offset
!= offset
|| tinfo
->curr
.period
!= period
;
3691 * Only use PPR if we have options that need it, even if the device
3692 * claims to support it. There might be an expander in the way
3695 doppr
= ppr_options
!= 0;
3697 if (!dowide
&& !dosync
&& !doppr
) {
3698 dowide
= tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
;
3699 dosync
= tinfo
->goal
.offset
!= 0;
3702 if (!dowide
&& !dosync
&& !doppr
) {
3704 * Force async with a WDTR message if we have a wide bus,
3705 * or just issue an SDTR with a 0 offset.
3707 if ((ahd
->features
& AHD_WIDE
) != 0)
3713 ahd_print_devinfo(ahd
, devinfo
);
3714 kprintf("Ensuring async\n");
3717 /* Target initiated PPR is not allowed in the SCSI spec */
3718 if (devinfo
->role
== ROLE_TARGET
)
3722 * Both the PPR message and SDTR message require the
3723 * goal syncrate to be limited to what the target device
3724 * is capable of handling (based on whether an LVD->SE
3725 * expander is on the bus), so combine these two cases.
3726 * Regardless, guarantee that if we are using WDTR and SDTR
3727 * messages that WDTR comes first.
3729 if (doppr
|| (dosync
&& !dowide
)) {
3731 offset
= tinfo
->goal
.offset
;
3732 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
3733 doppr
? tinfo
->goal
.width
3734 : tinfo
->curr
.width
,
3737 ahd_construct_ppr(ahd
, devinfo
, period
, offset
,
3738 tinfo
->goal
.width
, ppr_options
);
3740 ahd_construct_sdtr(ahd
, devinfo
, period
, offset
);
3743 ahd_construct_wdtr(ahd
, devinfo
, tinfo
->goal
.width
);
3748 * Build a synchronous negotiation message in our message
3749 * buffer based on the input parameters.
3752 ahd_construct_sdtr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3753 u_int period
, u_int offset
)
3756 period
= AHD_ASYNC_XFER_PERIOD
;
3757 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXTENDED
;
3758 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_SDTR_LEN
;
3759 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_SDTR
;
3760 ahd
->msgout_buf
[ahd
->msgout_index
++] = period
;
3761 ahd
->msgout_buf
[ahd
->msgout_index
++] = offset
;
3762 ahd
->msgout_len
+= 5;
3764 kprintf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3765 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
3766 devinfo
->lun
, period
, offset
);
3771 * Build a wide negotiateion message in our message
3772 * buffer based on the input parameters.
3775 ahd_construct_wdtr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3778 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXTENDED
;
3779 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_WDTR_LEN
;
3780 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_WDTR
;
3781 ahd
->msgout_buf
[ahd
->msgout_index
++] = bus_width
;
3782 ahd
->msgout_len
+= 4;
3784 kprintf("(%s:%c:%d:%d): Sending WDTR %x\n",
3785 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
3786 devinfo
->lun
, bus_width
);
3791 * Build a parallel protocol request message in our message
3792 * buffer based on the input parameters.
3795 ahd_construct_ppr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3796 u_int period
, u_int offset
, u_int bus_width
,
3800 * Always request precompensation from
3801 * the other target if we are running
3802 * at paced syncrates.
3804 if (period
<= AHD_SYNCRATE_PACED
)
3805 ppr_options
|= MSG_EXT_PPR_PCOMP_EN
;
3807 period
= AHD_ASYNC_XFER_PERIOD
;
3808 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXTENDED
;
3809 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_PPR_LEN
;
3810 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_EXT_PPR
;
3811 ahd
->msgout_buf
[ahd
->msgout_index
++] = period
;
3812 ahd
->msgout_buf
[ahd
->msgout_index
++] = 0;
3813 ahd
->msgout_buf
[ahd
->msgout_index
++] = offset
;
3814 ahd
->msgout_buf
[ahd
->msgout_index
++] = bus_width
;
3815 ahd
->msgout_buf
[ahd
->msgout_index
++] = ppr_options
;
3816 ahd
->msgout_len
+= 8;
3818 kprintf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3819 "offset %x, ppr_options %x\n", ahd_name(ahd
),
3820 devinfo
->channel
, devinfo
->target
, devinfo
->lun
,
3821 bus_width
, period
, offset
, ppr_options
);
3826 * Clear any active message state.
3829 ahd_clear_msg_state(struct ahd_softc
*ahd
)
3831 ahd_mode_state saved_modes
;
3833 saved_modes
= ahd_save_modes(ahd
);
3834 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3835 ahd
->send_msg_perror
= 0;
3836 ahd
->msg_flags
= MSG_FLAG_NONE
;
3837 ahd
->msgout_len
= 0;
3838 ahd
->msgin_index
= 0;
3839 ahd
->msg_type
= MSG_TYPE_NONE
;
3840 if ((ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0) {
3842 * The target didn't care to respond to our
3843 * message request, so clear ATN.
3845 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3847 ahd_outb(ahd
, MSG_OUT
, MSG_NOOP
);
3848 ahd_outb(ahd
, SEQ_FLAGS2
,
3849 ahd_inb(ahd
, SEQ_FLAGS2
) & ~TARGET_MSG_PENDING
);
3850 ahd_restore_modes(ahd
, saved_modes
);
3854 * Manual message loop handler.
3857 ahd_handle_message_phase(struct ahd_softc
*ahd
)
3859 struct ahd_devinfo devinfo
;
3863 ahd_fetch_devinfo(ahd
, &devinfo
);
3864 end_session
= FALSE
;
3865 bus_phase
= ahd_inb(ahd
, LASTPHASE
);
3867 if ((ahd_inb(ahd
, LQISTAT2
) & LQIPHASE_OUTPKT
) != 0) {
3868 kprintf("LQIRETRY for LQIPHASE_OUTPKT\n");
3869 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
3872 switch (ahd
->msg_type
) {
3873 case MSG_TYPE_INITIATOR_MSGOUT
:
3879 if (ahd
->msgout_len
== 0 && ahd
->send_msg_perror
== 0)
3880 panic("HOST_MSG_LOOP interrupt with no active message");
3883 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3884 ahd_print_devinfo(ahd
, &devinfo
);
3885 kprintf("INITIATOR_MSG_OUT");
3888 phasemis
= bus_phase
!= P_MESGOUT
;
3891 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3892 kprintf(" PHASEMIS %s\n",
3893 ahd_lookup_phase_entry(bus_phase
)
3897 if (bus_phase
== P_MESGIN
) {
3899 * Change gears and see if
3900 * this messages is of interest to
3901 * us or should be passed back to
3904 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3905 ahd
->send_msg_perror
= 0;
3906 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGIN
;
3907 ahd
->msgin_index
= 0;
3914 if (ahd
->send_msg_perror
) {
3915 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3916 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
3918 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3919 kprintf(" byte 0x%x\n", ahd
->send_msg_perror
);
3922 * If we are notifying the target of a CRC error
3923 * during packetized operations, the target is
3924 * within its rights to acknowledge our message
3927 if ((ahd
->msg_flags
& MSG_FLAG_PACKETIZED
) != 0
3928 && ahd
->send_msg_perror
== MSG_INITIATOR_DET_ERR
)
3929 ahd
->msg_flags
|= MSG_FLAG_EXPECT_IDE_BUSFREE
;
3931 ahd_outb(ahd
, RETURN_2
, ahd
->send_msg_perror
);
3932 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_WRITE
);
3936 msgdone
= ahd
->msgout_index
== ahd
->msgout_len
;
3939 * The target has requested a retry.
3940 * Re-assert ATN, reset our message index to
3943 ahd
->msgout_index
= 0;
3944 ahd_assert_atn(ahd
);
3947 lastbyte
= ahd
->msgout_index
== (ahd
->msgout_len
- 1);
3949 /* Last byte is signified by dropping ATN */
3950 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3954 * Clear our interrupt status and present
3955 * the next byte on the bus.
3957 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
3959 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3960 kprintf(" byte 0x%x\n",
3961 ahd
->msgout_buf
[ahd
->msgout_index
]);
3963 ahd_outb(ahd
, RETURN_2
, ahd
->msgout_buf
[ahd
->msgout_index
++]);
3964 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_WRITE
);
3967 case MSG_TYPE_INITIATOR_MSGIN
:
3973 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3974 ahd_print_devinfo(ahd
, &devinfo
);
3975 kprintf("INITIATOR_MSG_IN");
3978 phasemis
= bus_phase
!= P_MESGIN
;
3981 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3982 kprintf(" PHASEMIS %s\n",
3983 ahd_lookup_phase_entry(bus_phase
)
3987 ahd
->msgin_index
= 0;
3988 if (bus_phase
== P_MESGOUT
3989 && (ahd
->send_msg_perror
!= 0
3990 || (ahd
->msgout_len
!= 0
3991 && ahd
->msgout_index
== 0))) {
3992 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3999 /* Pull the byte in without acking it */
4000 ahd
->msgin_buf
[ahd
->msgin_index
] = ahd_inb(ahd
, SCSIBUS
);
4002 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
4003 kprintf(" byte 0x%x\n",
4004 ahd
->msgin_buf
[ahd
->msgin_index
]);
4007 message_done
= ahd_parse_msg(ahd
, &devinfo
);
4011 * Clear our incoming message buffer in case there
4012 * is another message following this one.
4014 ahd
->msgin_index
= 0;
4017 * If this message illicited a response,
4018 * assert ATN so the target takes us to the
4019 * message out phase.
4021 if (ahd
->msgout_len
!= 0) {
4023 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
4024 ahd_print_devinfo(ahd
, &devinfo
);
4025 kprintf("Asserting ATN for response\n");
4028 ahd_assert_atn(ahd
);
4033 if (message_done
== MSGLOOP_TERMINATED
) {
4037 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
4038 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_READ
);
4042 case MSG_TYPE_TARGET_MSGIN
:
4048 * By default, the message loop will continue.
4050 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_TARG
);
4052 if (ahd
->msgout_len
== 0)
4053 panic("Target MSGIN with no active message");
4056 * If we interrupted a mesgout session, the initiator
4057 * will not know this until our first REQ. So, we
4058 * only honor mesgout requests after we've sent our
4061 if ((ahd_inb(ahd
, SCSISIGI
) & ATNI
) != 0
4062 && ahd
->msgout_index
> 0)
4063 msgout_request
= TRUE
;
4065 msgout_request
= FALSE
;
4067 if (msgout_request
) {
4070 * Change gears and see if
4071 * this messages is of interest to
4072 * us or should be passed back to
4075 ahd
->msg_type
= MSG_TYPE_TARGET_MSGOUT
;
4076 ahd_outb(ahd
, SCSISIGO
, P_MESGOUT
| BSYO
);
4077 ahd
->msgin_index
= 0;
4078 /* Dummy read to REQ for first byte */
4079 ahd_inb(ahd
, SCSIDAT
);
4080 ahd_outb(ahd
, SXFRCTL0
,
4081 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4085 msgdone
= ahd
->msgout_index
== ahd
->msgout_len
;
4087 ahd_outb(ahd
, SXFRCTL0
,
4088 ahd_inb(ahd
, SXFRCTL0
) & ~SPIOEN
);
4094 * Present the next byte on the bus.
4096 ahd_outb(ahd
, SXFRCTL0
, ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4097 ahd_outb(ahd
, SCSIDAT
, ahd
->msgout_buf
[ahd
->msgout_index
++]);
4100 case MSG_TYPE_TARGET_MSGOUT
:
4106 * By default, the message loop will continue.
4108 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_TARG
);
4111 * The initiator signals that this is
4112 * the last byte by dropping ATN.
4114 lastbyte
= (ahd_inb(ahd
, SCSISIGI
) & ATNI
) == 0;
4117 * Read the latched byte, but turn off SPIOEN first
4118 * so that we don't inadvertently cause a REQ for the
4121 ahd_outb(ahd
, SXFRCTL0
, ahd_inb(ahd
, SXFRCTL0
) & ~SPIOEN
);
4122 ahd
->msgin_buf
[ahd
->msgin_index
] = ahd_inb(ahd
, SCSIDAT
);
4123 msgdone
= ahd_parse_msg(ahd
, &devinfo
);
4124 if (msgdone
== MSGLOOP_TERMINATED
) {
4126 * The message is *really* done in that it caused
4127 * us to go to bus free. The sequencer has already
4128 * been reset at this point, so pull the ejection
4137 * XXX Read spec about initiator dropping ATN too soon
4138 * and use msgdone to detect it.
4140 if (msgdone
== MSGLOOP_MSGCOMPLETE
) {
4141 ahd
->msgin_index
= 0;
4144 * If this message illicited a response, transition
4145 * to the Message in phase and send it.
4147 if (ahd
->msgout_len
!= 0) {
4148 ahd_outb(ahd
, SCSISIGO
, P_MESGIN
| BSYO
);
4149 ahd_outb(ahd
, SXFRCTL0
,
4150 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4151 ahd
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
4152 ahd
->msgin_index
= 0;
4160 /* Ask for the next byte. */
4161 ahd_outb(ahd
, SXFRCTL0
,
4162 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4168 panic("Unknown REQINIT message type");
4172 if ((ahd
->msg_flags
& MSG_FLAG_PACKETIZED
) != 0) {
4173 kprintf("%s: Returning to Idle Loop\n",
4175 ahd_clear_msg_state(ahd
);
4178 * Perform the equivalent of a clear_target_state.
4180 ahd_outb(ahd
, LASTPHASE
, P_BUSFREE
);
4181 ahd_outb(ahd
, SEQ_FLAGS
, NOT_IDENTIFIED
|NO_CDB_SENT
);
4182 ahd_outb(ahd
, SEQCTL0
, FASTMODE
|SEQRESET
);
4184 ahd_clear_msg_state(ahd
);
4185 ahd_outb(ahd
, RETURN_1
, EXIT_MSG_LOOP
);
4191 * See if we sent a particular extended message to the target.
4192 * If "full" is true, return true only if the target saw the full
4193 * message. If "full" is false, return true if the target saw at
4194 * least the first byte of the message.
4197 ahd_sent_msg(struct ahd_softc
*ahd
, ahd_msgtype type
, u_int msgval
, int full
)
4205 while (index
< ahd
->msgout_len
) {
4206 if (ahd
->msgout_buf
[index
] == MSG_EXTENDED
) {
4209 end_index
= index
+ 1 + ahd
->msgout_buf
[index
+ 1];
4210 if (ahd
->msgout_buf
[index
+2] == msgval
4211 && type
== AHDMSG_EXT
) {
4214 if (ahd
->msgout_index
> end_index
)
4216 } else if (ahd
->msgout_index
> index
)
4220 } else if (ahd
->msgout_buf
[index
] >= MSG_SIMPLE_TASK
4221 && ahd
->msgout_buf
[index
] <= MSG_IGN_WIDE_RESIDUE
) {
4223 /* Skip tag type and tag id or residue param*/
4226 /* Single byte message */
4227 if (type
== AHDMSG_1B
4228 && ahd
->msgout_index
> index
4229 && (ahd
->msgout_buf
[index
] == msgval
4230 || ((ahd
->msgout_buf
[index
] & MSG_IDENTIFYFLAG
) != 0
4231 && msgval
== MSG_IDENTIFYFLAG
)))
4243 * Wait for a complete incoming message, parse it, and respond accordingly.
4246 ahd_parse_msg(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4248 struct ahd_initiator_tinfo
*tinfo
;
4249 struct ahd_tmode_tstate
*tstate
;
4254 done
= MSGLOOP_IN_PROG
;
4257 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
4258 devinfo
->target
, &tstate
);
4261 * Parse as much of the message as is available,
4262 * rejecting it if we don't support it. When
4263 * the entire message is available and has been
4264 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4265 * that we have parsed an entire message.
4267 * In the case of extended messages, we accept the length
4268 * byte outright and perform more checking once we know the
4269 * extended message type.
4271 switch (ahd
->msgin_buf
[0]) {
4272 case MSG_DISCONNECT
:
4273 case MSG_SAVEDATAPOINTER
:
4274 case MSG_CMDCOMPLETE
:
4275 case MSG_RESTOREPOINTERS
:
4276 case MSG_IGN_WIDE_RESIDUE
:
4278 * End our message loop as these are messages
4279 * the sequencer handles on its own.
4281 done
= MSGLOOP_TERMINATED
;
4283 case MSG_MESSAGE_REJECT
:
4284 response
= ahd_handle_msg_reject(ahd
, devinfo
);
4287 done
= MSGLOOP_MSGCOMPLETE
;
4291 /* Wait for enough of the message to begin validation */
4292 if (ahd
->msgin_index
< 2)
4294 switch (ahd
->msgin_buf
[2]) {
4302 if (ahd
->msgin_buf
[1] != MSG_EXT_SDTR_LEN
) {
4308 * Wait until we have both args before validating
4309 * and acting on this message.
4311 * Add one to MSG_EXT_SDTR_LEN to account for
4312 * the extended message preamble.
4314 if (ahd
->msgin_index
< (MSG_EXT_SDTR_LEN
+ 1))
4317 period
= ahd
->msgin_buf
[3];
4319 saved_offset
= offset
= ahd
->msgin_buf
[4];
4320 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
4321 &ppr_options
, devinfo
->role
);
4322 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
4323 tinfo
->curr
.width
, devinfo
->role
);
4325 kprintf("(%s:%c:%d:%d): Received "
4326 "SDTR period %x, offset %x\n\t"
4327 "Filtered to period %x, offset %x\n",
4328 ahd_name(ahd
), devinfo
->channel
,
4329 devinfo
->target
, devinfo
->lun
,
4330 ahd
->msgin_buf
[3], saved_offset
,
4333 ahd_set_syncrate(ahd
, devinfo
, period
,
4334 offset
, ppr_options
,
4335 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4339 * See if we initiated Sync Negotiation
4340 * and didn't have to fall down to async
4343 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, TRUE
)) {
4345 if (saved_offset
!= offset
) {
4346 /* Went too low - force async */
4351 * Send our own SDTR in reply
4354 && devinfo
->role
== ROLE_INITIATOR
) {
4355 kprintf("(%s:%c:%d:%d): Target "
4357 ahd_name(ahd
), devinfo
->channel
,
4358 devinfo
->target
, devinfo
->lun
);
4360 ahd
->msgout_index
= 0;
4361 ahd
->msgout_len
= 0;
4362 ahd_construct_sdtr(ahd
, devinfo
,
4364 ahd
->msgout_index
= 0;
4367 done
= MSGLOOP_MSGCOMPLETE
;
4374 u_int sending_reply
;
4376 sending_reply
= FALSE
;
4377 if (ahd
->msgin_buf
[1] != MSG_EXT_WDTR_LEN
) {
4383 * Wait until we have our arg before validating
4384 * and acting on this message.
4386 * Add one to MSG_EXT_WDTR_LEN to account for
4387 * the extended message preamble.
4389 if (ahd
->msgin_index
< (MSG_EXT_WDTR_LEN
+ 1))
4392 bus_width
= ahd
->msgin_buf
[3];
4393 saved_width
= bus_width
;
4394 ahd_validate_width(ahd
, tinfo
, &bus_width
,
4397 kprintf("(%s:%c:%d:%d): Received WDTR "
4398 "%x filtered to %x\n",
4399 ahd_name(ahd
), devinfo
->channel
,
4400 devinfo
->target
, devinfo
->lun
,
4401 saved_width
, bus_width
);
4404 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, TRUE
)) {
4406 * Don't send a WDTR back to the
4407 * target, since we asked first.
4408 * If the width went higher than our
4409 * request, reject it.
4411 if (saved_width
> bus_width
) {
4413 kprintf("(%s:%c:%d:%d): requested %dBit "
4414 "transfers. Rejecting...\n",
4415 ahd_name(ahd
), devinfo
->channel
,
4416 devinfo
->target
, devinfo
->lun
,
4417 8 * (0x01 << bus_width
));
4422 * Send our own WDTR in reply
4425 && devinfo
->role
== ROLE_INITIATOR
) {
4426 kprintf("(%s:%c:%d:%d): Target "
4428 ahd_name(ahd
), devinfo
->channel
,
4429 devinfo
->target
, devinfo
->lun
);
4431 ahd
->msgout_index
= 0;
4432 ahd
->msgout_len
= 0;
4433 ahd_construct_wdtr(ahd
, devinfo
, bus_width
);
4434 ahd
->msgout_index
= 0;
4436 sending_reply
= TRUE
;
4439 * After a wide message, we are async, but
4440 * some devices don't seem to honor this portion
4441 * of the spec. Force a renegotiation of the
4442 * sync component of our transfer agreement even
4443 * if our goal is async. By updating our width
4444 * after forcing the negotiation, we avoid
4445 * renegotiating for width.
4447 ahd_update_neg_request(ahd
, devinfo
, tstate
,
4448 tinfo
, AHD_NEG_ALWAYS
);
4449 ahd_set_width(ahd
, devinfo
, bus_width
,
4450 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4452 if (sending_reply
== FALSE
&& reject
== FALSE
) {
4455 * We will always have an SDTR to send.
4457 ahd
->msgout_index
= 0;
4458 ahd
->msgout_len
= 0;
4459 ahd_build_transfer_msg(ahd
, devinfo
);
4460 ahd
->msgout_index
= 0;
4463 done
= MSGLOOP_MSGCOMPLETE
;
4474 u_int saved_ppr_options
;
4476 if (ahd
->msgin_buf
[1] != MSG_EXT_PPR_LEN
) {
4482 * Wait until we have all args before validating
4483 * and acting on this message.
4485 * Add one to MSG_EXT_PPR_LEN to account for
4486 * the extended message preamble.
4488 if (ahd
->msgin_index
< (MSG_EXT_PPR_LEN
+ 1))
4491 period
= ahd
->msgin_buf
[3];
4492 offset
= ahd
->msgin_buf
[5];
4493 bus_width
= ahd
->msgin_buf
[6];
4494 saved_width
= bus_width
;
4495 ppr_options
= ahd
->msgin_buf
[7];
4497 * According to the spec, a DT only
4498 * period factor with no DT option
4499 * set implies async.
4501 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
4504 saved_ppr_options
= ppr_options
;
4505 saved_offset
= offset
;
4508 * Transfer options are only available if we
4509 * are negotiating wide.
4512 ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
4514 ahd_validate_width(ahd
, tinfo
, &bus_width
,
4516 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
4517 &ppr_options
, devinfo
->role
);
4518 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
4519 bus_width
, devinfo
->role
);
4521 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, TRUE
)) {
4523 * If we are unable to do any of the
4524 * requested options (we went too low),
4525 * then we'll have to reject the message.
4527 if (saved_width
> bus_width
4528 || saved_offset
!= offset
4529 || saved_ppr_options
!= ppr_options
) {
4537 if (devinfo
->role
!= ROLE_TARGET
)
4538 kprintf("(%s:%c:%d:%d): Target "
4540 ahd_name(ahd
), devinfo
->channel
,
4541 devinfo
->target
, devinfo
->lun
);
4543 kprintf("(%s:%c:%d:%d): Initiator "
4545 ahd_name(ahd
), devinfo
->channel
,
4546 devinfo
->target
, devinfo
->lun
);
4547 ahd
->msgout_index
= 0;
4548 ahd
->msgout_len
= 0;
4549 ahd_construct_ppr(ahd
, devinfo
, period
, offset
,
4550 bus_width
, ppr_options
);
4551 ahd
->msgout_index
= 0;
4555 kprintf("(%s:%c:%d:%d): Received PPR width %x, "
4556 "period %x, offset %x,options %x\n"
4557 "\tFiltered to width %x, period %x, "
4558 "offset %x, options %x\n",
4559 ahd_name(ahd
), devinfo
->channel
,
4560 devinfo
->target
, devinfo
->lun
,
4561 saved_width
, ahd
->msgin_buf
[3],
4562 saved_offset
, saved_ppr_options
,
4563 bus_width
, period
, offset
, ppr_options
);
4565 ahd_set_width(ahd
, devinfo
, bus_width
,
4566 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4568 ahd_set_syncrate(ahd
, devinfo
, period
,
4569 offset
, ppr_options
,
4570 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4573 done
= MSGLOOP_MSGCOMPLETE
;
4577 /* Unknown extended message. Reject it. */
4583 #ifdef AHD_TARGET_MODE
4584 case MSG_BUS_DEV_RESET
:
4585 ahd_handle_devreset(ahd
, devinfo
, CAM_LUN_WILDCARD
,
4587 "Bus Device Reset Received",
4588 /*verbose_level*/0);
4590 done
= MSGLOOP_TERMINATED
;
4594 case MSG_CLEAR_QUEUE
:
4598 /* Target mode messages */
4599 if (devinfo
->role
!= ROLE_TARGET
) {
4603 tag
= SCB_LIST_NULL
;
4604 if (ahd
->msgin_buf
[0] == MSG_ABORT_TAG
)
4605 tag
= ahd_inb(ahd
, INITIATOR_TAG
);
4606 ahd_abort_scbs(ahd
, devinfo
->target
, devinfo
->channel
,
4607 devinfo
->lun
, tag
, ROLE_TARGET
,
4610 tstate
= ahd
->enabled_targets
[devinfo
->our_scsiid
];
4611 if (tstate
!= NULL
) {
4612 struct ahd_tmode_lstate
* lstate
;
4614 lstate
= tstate
->enabled_luns
[devinfo
->lun
];
4615 if (lstate
!= NULL
) {
4616 ahd_queue_lstate_event(ahd
, lstate
,
4617 devinfo
->our_scsiid
,
4620 ahd_send_lstate_events(ahd
, lstate
);
4624 done
= MSGLOOP_TERMINATED
;
4628 case MSG_QAS_REQUEST
:
4630 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
4631 kprintf("%s: QAS request. SCSISIGI == 0x%x\n",
4632 ahd_name(ahd
), ahd_inb(ahd
, SCSISIGI
));
4634 ahd
->msg_flags
|= MSG_FLAG_EXPECT_QASREJ_BUSFREE
;
4636 case MSG_TERM_IO_PROC
:
4644 * Setup to reject the message.
4646 ahd
->msgout_index
= 0;
4647 ahd
->msgout_len
= 1;
4648 ahd
->msgout_buf
[0] = MSG_MESSAGE_REJECT
;
4649 done
= MSGLOOP_MSGCOMPLETE
;
4653 if (done
!= MSGLOOP_IN_PROG
&& !response
)
4654 /* Clear the outgoing message buffer */
4655 ahd
->msgout_len
= 0;
4661 * Process a message reject message.
4664 ahd_handle_msg_reject(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4667 * What we care about here is if we had an
4668 * outstanding SDTR or WDTR message for this
4669 * target. If we did, this is a signal that
4670 * the target is refusing negotiation.
4673 struct ahd_initiator_tinfo
*tinfo
;
4674 struct ahd_tmode_tstate
*tstate
;
4679 scb_index
= ahd_get_scbptr(ahd
);
4680 scb
= ahd_lookup_scb(ahd
, scb_index
);
4681 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
,
4682 devinfo
->our_scsiid
,
4683 devinfo
->target
, &tstate
);
4684 /* Might be necessary */
4685 last_msg
= ahd_inb(ahd
, LAST_MSG
);
4687 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, /*full*/FALSE
)) {
4688 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, /*full*/TRUE
)
4689 && tinfo
->goal
.period
<= AHD_SYNCRATE_PACED
) {
4691 * Target may not like our SPI-4 PPR Options.
4692 * Attempt to negotiate 80MHz which will turn
4693 * off these options.
4696 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4697 "Trying simple U160 PPR\n",
4698 ahd_name(ahd
), devinfo
->channel
,
4699 devinfo
->target
, devinfo
->lun
);
4701 tinfo
->goal
.period
= AHD_SYNCRATE_DT
;
4702 tinfo
->goal
.ppr_options
&= MSG_EXT_PPR_IU_REQ
4703 | MSG_EXT_PPR_QAS_REQ
4704 | MSG_EXT_PPR_DT_REQ
;
4707 * Target does not support the PPR message.
4708 * Attempt to negotiate SPI-2 style.
4711 kprintf("(%s:%c:%d:%d): PPR Rejected. "
4712 "Trying WDTR/SDTR\n",
4713 ahd_name(ahd
), devinfo
->channel
,
4714 devinfo
->target
, devinfo
->lun
);
4716 tinfo
->goal
.ppr_options
= 0;
4717 tinfo
->curr
.transport_version
= 2;
4718 tinfo
->goal
.transport_version
= 2;
4720 ahd
->msgout_index
= 0;
4721 ahd
->msgout_len
= 0;
4722 ahd_build_transfer_msg(ahd
, devinfo
);
4723 ahd
->msgout_index
= 0;
4725 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, /*full*/FALSE
)) {
4727 /* note 8bit xfers */
4728 kprintf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4729 "8bit transfers\n", ahd_name(ahd
),
4730 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
4731 ahd_set_width(ahd
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
4732 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4735 * No need to clear the sync rate. If the target
4736 * did not accept the command, our syncrate is
4737 * unaffected. If the target started the negotiation,
4738 * but rejected our response, we already cleared the
4739 * sync rate before sending our WDTR.
4741 if (tinfo
->goal
.offset
!= tinfo
->curr
.offset
) {
4743 /* Start the sync negotiation */
4744 ahd
->msgout_index
= 0;
4745 ahd
->msgout_len
= 0;
4746 ahd_build_transfer_msg(ahd
, devinfo
);
4747 ahd
->msgout_index
= 0;
4750 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, /*full*/FALSE
)) {
4751 /* note asynch xfers and clear flag */
4752 ahd_set_syncrate(ahd
, devinfo
, /*period*/0,
4753 /*offset*/0, /*ppr_options*/0,
4754 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4756 kprintf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4757 "Using asynchronous transfers\n",
4758 ahd_name(ahd
), devinfo
->channel
,
4759 devinfo
->target
, devinfo
->lun
);
4760 } else if ((scb
->hscb
->control
& MSG_SIMPLE_TASK
) != 0) {
4764 tag_type
= (scb
->hscb
->control
& MSG_SIMPLE_TASK
);
4766 if (tag_type
== MSG_SIMPLE_TASK
) {
4767 kprintf("(%s:%c:%d:%d): refuses tagged commands. "
4768 "Performing non-tagged I/O\n", ahd_name(ahd
),
4769 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
4770 ahd_set_tags(ahd
, devinfo
, AHD_QUEUE_NONE
);
4773 kprintf("(%s:%c:%d:%d): refuses %s tagged commands. "
4774 "Performing simple queue tagged I/O only\n",
4775 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
4776 devinfo
->lun
, tag_type
== MSG_ORDERED_TASK
4777 ? "ordered" : "head of queue");
4778 ahd_set_tags(ahd
, devinfo
, AHD_QUEUE_BASIC
);
4783 * Resend the identify for this CCB as the target
4784 * may believe that the selection is invalid otherwise.
4786 ahd_outb(ahd
, SCB_CONTROL
,
4787 ahd_inb_scbram(ahd
, SCB_CONTROL
) & mask
);
4788 scb
->hscb
->control
&= mask
;
4789 aic_set_transaction_tag(scb
, /*enabled*/FALSE
,
4790 /*type*/MSG_SIMPLE_TASK
);
4791 ahd_outb(ahd
, MSG_OUT
, MSG_IDENTIFYFLAG
);
4792 ahd_assert_atn(ahd
);
4793 ahd_busy_tcl(ahd
, BUILD_TCL(scb
->hscb
->scsiid
, devinfo
->lun
),
4797 * Requeue all tagged commands for this target
4798 * currently in our posession so they can be
4799 * converted to untagged commands.
4801 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
4802 SCB_GET_CHANNEL(ahd
, scb
),
4803 SCB_GET_LUN(scb
), /*tag*/SCB_LIST_NULL
,
4804 ROLE_INITIATOR
, CAM_REQUEUE_REQ
,
4806 } else if (ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_IDENTIFYFLAG
, TRUE
)) {
4808 * Most likely the device believes that we had
4809 * previously negotiated packetized.
4811 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
4812 | MSG_FLAG_IU_REQ_CHANGED
;
4814 ahd_force_renegotiation(ahd
, devinfo
);
4815 ahd
->msgout_index
= 0;
4816 ahd
->msgout_len
= 0;
4817 ahd_build_transfer_msg(ahd
, devinfo
);
4818 ahd
->msgout_index
= 0;
4822 * Otherwise, we ignore it.
4824 kprintf("%s:%c:%d: Message reject for %x -- ignored\n",
4825 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
4832 * Process an ingnore wide residue message.
4835 ahd_handle_ign_wide_residue(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4840 scb_index
= ahd_get_scbptr(ahd
);
4841 scb
= ahd_lookup_scb(ahd
, scb_index
);
4843 * XXX Actually check data direction in the sequencer?
4844 * Perhaps add datadir to some spare bits in the hscb?
4846 if ((ahd_inb(ahd
, SEQ_FLAGS
) & DPHASE
) == 0
4847 || aic_get_transfer_dir(scb
) != CAM_DIR_IN
) {
4849 * Ignore the message if we haven't
4850 * seen an appropriate data phase yet.
4854 * If the residual occurred on the last
4855 * transfer and the transfer request was
4856 * expected to end on an odd count, do
4857 * nothing. Otherwise, subtract a byte
4858 * and update the residual count accordingly.
4862 sgptr
= ahd_inb_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
4863 if ((sgptr
& SG_LIST_NULL
) != 0
4864 && (ahd_inb_scbram(ahd
, SCB_TASK_ATTRIBUTE
)
4865 & SCB_XFERLEN_ODD
) != 0) {
4867 * If the residual occurred on the last
4868 * transfer and the transfer request was
4869 * expected to end on an odd count, do
4877 /* Pull in the rest of the sgptr */
4878 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
4879 data_cnt
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_DATACNT
);
4880 if ((sgptr
& SG_LIST_NULL
) != 0) {
4882 * The residual data count is not updated
4883 * for the command run to completion case.
4884 * Explicitly zero the count.
4886 data_cnt
&= ~AHD_SG_LEN_MASK
;
4888 data_addr
= ahd_inq(ahd
, SHADDR
);
4891 sgptr
&= SG_PTR_MASK
;
4892 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
4893 struct ahd_dma64_seg
*sg
;
4895 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
4898 * The residual sg ptr points to the next S/G
4899 * to load so we must go back one.
4902 sglen
= aic_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
4903 if (sg
!= scb
->sg_list
4904 && sglen
< (data_cnt
& AHD_SG_LEN_MASK
)) {
4907 sglen
= aic_le32toh(sg
->len
);
4909 * Preserve High Address and SG_LIST
4910 * bits while setting the count to 1.
4912 data_cnt
= 1|(sglen
&(~AHD_SG_LEN_MASK
));
4913 data_addr
= aic_le64toh(sg
->addr
)
4914 + (sglen
& AHD_SG_LEN_MASK
)
4918 * Increment sg so it points to the
4922 sgptr
= ahd_sg_virt_to_bus(ahd
, scb
,
4926 struct ahd_dma_seg
*sg
;
4928 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
4931 * The residual sg ptr points to the next S/G
4932 * to load so we must go back one.
4935 sglen
= aic_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
4936 if (sg
!= scb
->sg_list
4937 && sglen
< (data_cnt
& AHD_SG_LEN_MASK
)) {
4940 sglen
= aic_le32toh(sg
->len
);
4942 * Preserve High Address and SG_LIST
4943 * bits while setting the count to 1.
4945 data_cnt
= 1|(sglen
&(~AHD_SG_LEN_MASK
));
4946 data_addr
= aic_le32toh(sg
->addr
)
4947 + (sglen
& AHD_SG_LEN_MASK
)
4951 * Increment sg so it points to the
4955 sgptr
= ahd_sg_virt_to_bus(ahd
, scb
,
4960 * Toggle the "oddness" of the transfer length
4961 * to handle this mid-transfer ignore wide
4962 * residue. This ensures that the oddness is
4963 * correct for subsequent data transfers.
4965 ahd_outb(ahd
, SCB_TASK_ATTRIBUTE
,
4966 ahd_inb_scbram(ahd
, SCB_TASK_ATTRIBUTE
)
4969 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
4970 ahd_outl(ahd
, SCB_RESIDUAL_DATACNT
, data_cnt
);
4972 * The FIFO's pointers will be updated if/when the
4973 * sequencer re-enters a data phase.
4981 * Reinitialize the data pointers for the active transfer
4982 * based on its current residual.
4985 ahd_reinitialize_dataptrs(struct ahd_softc
*ahd
)
4988 ahd_mode_state saved_modes
;
4995 AHD_ASSERT_MODES(ahd
, AHD_MODE_DFF0_MSK
|AHD_MODE_DFF1_MSK
,
4996 AHD_MODE_DFF0_MSK
|AHD_MODE_DFF1_MSK
);
4998 scb_index
= ahd_get_scbptr(ahd
);
4999 scb
= ahd_lookup_scb(ahd
, scb_index
);
5002 * Release and reacquire the FIFO so we
5003 * have a clean slate.
5005 ahd_outb(ahd
, DFFSXFRCTL
, CLRCHN
);
5007 while (--wait
&& !(ahd_inb(ahd
, MDFFSTAT
) & FIFOFREE
))
5010 ahd_print_path(ahd
, scb
);
5011 kprintf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5012 ahd_outb(ahd
, DFFSXFRCTL
, RSTCHN
|CLRSHCNT
);
5014 saved_modes
= ahd_save_modes(ahd
);
5015 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5016 ahd_outb(ahd
, DFFSTAT
,
5017 ahd_inb(ahd
, DFFSTAT
)
5018 | (saved_modes
== 0x11 ? CURRFIFO_1
: CURRFIFO_0
));
5021 * Determine initial values for data_addr and data_cnt
5022 * for resuming the data phase.
5024 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
5025 sgptr
&= SG_PTR_MASK
;
5027 resid
= (ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+ 2) << 16)
5028 | (ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+ 1) << 8)
5029 | ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
);
5031 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
5032 struct ahd_dma64_seg
*sg
;
5034 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
5036 /* The residual sg_ptr always points to the next sg */
5039 dataptr
= aic_le64toh(sg
->addr
)
5040 + (aic_le32toh(sg
->len
) & AHD_SG_LEN_MASK
)
5042 ahd_outl(ahd
, HADDR
+ 4, dataptr
>> 32);
5044 struct ahd_dma_seg
*sg
;
5046 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
5048 /* The residual sg_ptr always points to the next sg */
5051 dataptr
= aic_le32toh(sg
->addr
)
5052 + (aic_le32toh(sg
->len
) & AHD_SG_LEN_MASK
)
5054 ahd_outb(ahd
, HADDR
+ 4,
5055 (aic_le32toh(sg
->len
) & ~AHD_SG_LEN_MASK
) >> 24);
5057 ahd_outl(ahd
, HADDR
, dataptr
);
5058 ahd_outb(ahd
, HCNT
+ 2, resid
>> 16);
5059 ahd_outb(ahd
, HCNT
+ 1, resid
>> 8);
5060 ahd_outb(ahd
, HCNT
, resid
);
5064 * Handle the effects of issuing a bus device reset message.
5067 ahd_handle_devreset(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
5068 u_int lun
, cam_status status
, char *message
,
5071 #ifdef AHD_TARGET_MODE
5072 struct ahd_tmode_tstate
* tstate
;
5076 found
= ahd_abort_scbs(ahd
, devinfo
->target
, devinfo
->channel
,
5077 lun
, SCB_LIST_NULL
, devinfo
->role
,
5080 #ifdef AHD_TARGET_MODE
5082 * Send an immediate notify ccb to all target mord peripheral
5083 * drivers affected by this action.
5085 tstate
= ahd
->enabled_targets
[devinfo
->our_scsiid
];
5086 if (tstate
!= NULL
) {
5090 if (lun
!= CAM_LUN_WILDCARD
) {
5092 max_lun
= AHD_NUM_LUNS
- 1;
5097 for (cur_lun
<= max_lun
; cur_lun
++) {
5098 struct ahd_tmode_lstate
* lstate
;
5100 lstate
= tstate
->enabled_luns
[cur_lun
];
5104 ahd_queue_lstate_event(ahd
, lstate
, devinfo
->our_scsiid
,
5105 MSG_BUS_DEV_RESET
, /*arg*/0);
5106 ahd_send_lstate_events(ahd
, lstate
);
5112 * Go back to async/narrow transfers and renegotiate.
5114 ahd_set_width(ahd
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
5115 AHD_TRANS_CUR
, /*paused*/TRUE
);
5116 ahd_set_syncrate(ahd
, devinfo
, /*period*/0, /*offset*/0,
5117 /*ppr_options*/0, AHD_TRANS_CUR
,
5120 if (status
!= CAM_SEL_TIMEOUT
)
5121 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
5122 lun
, AC_SENT_BDR
, NULL
);
5125 && (verbose_level
<= bootverbose
))
5126 kprintf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd
),
5127 message
, devinfo
->channel
, devinfo
->target
, found
);
5130 #ifdef AHD_TARGET_MODE
5132 ahd_setup_target_msgin(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
5137 * To facilitate adding multiple messages together,
5138 * each routine should increment the index and len
5139 * variables instead of setting them explicitly.
5141 ahd
->msgout_index
= 0;
5142 ahd
->msgout_len
= 0;
5144 if (scb
!= NULL
&& (scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0)
5145 ahd_build_transfer_msg(ahd
, devinfo
);
5147 panic("ahd_intr: AWAITING target message with no message");
5149 ahd
->msgout_index
= 0;
5150 ahd
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
5153 /**************************** Initialization **********************************/
5155 ahd_sglist_size(struct ahd_softc
*ahd
)
5157 bus_size_t list_size
;
5159 list_size
= sizeof(struct ahd_dma_seg
) * AHD_NSEG
;
5160 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
5161 list_size
= sizeof(struct ahd_dma64_seg
) * AHD_NSEG
;
5166 * Calculate the optimum S/G List allocation size. S/G elements used
5167 * for a given transaction must be physically contiguous. Assume the
5168 * OS will allocate full pages to us, so it doesn't make sense to request
5172 ahd_sglist_allocsize(struct ahd_softc
*ahd
)
5174 bus_size_t sg_list_increment
;
5175 bus_size_t sg_list_size
;
5176 bus_size_t max_list_size
;
5177 bus_size_t best_list_size
;
5179 /* Start out with the minimum required for AHD_NSEG. */
5180 sg_list_increment
= ahd_sglist_size(ahd
);
5181 sg_list_size
= sg_list_increment
;
5183 /* Get us as close as possible to a page in size. */
5184 while ((sg_list_size
+ sg_list_increment
) <= PAGE_SIZE
)
5185 sg_list_size
+= sg_list_increment
;
5188 * Try to reduce the amount of wastage by allocating
5191 best_list_size
= sg_list_size
;
5192 max_list_size
= roundup(sg_list_increment
, PAGE_SIZE
);
5193 if (max_list_size
< 4 * PAGE_SIZE
)
5194 max_list_size
= 4 * PAGE_SIZE
;
5195 if (max_list_size
> (AHD_SCB_MAX_ALLOC
* sg_list_increment
))
5196 max_list_size
= (AHD_SCB_MAX_ALLOC
* sg_list_increment
);
5197 while ((sg_list_size
+ sg_list_increment
) <= max_list_size
5198 && (sg_list_size
% PAGE_SIZE
) != 0) {
5200 bus_size_t best_mod
;
5202 sg_list_size
+= sg_list_increment
;
5203 new_mod
= sg_list_size
% PAGE_SIZE
;
5204 best_mod
= best_list_size
% PAGE_SIZE
;
5205 if (new_mod
> best_mod
|| new_mod
== 0) {
5206 best_list_size
= sg_list_size
;
5209 return (best_list_size
);
5213 * Allocate a controller structure for a new device
5214 * and perform initial initializion.
5217 ahd_alloc(void *platform_arg
, char *name
)
5219 struct ahd_softc
*ahd
;
5221 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5222 ahd
= kmalloc(sizeof(*ahd
), M_DEVBUF
, M_INTWAIT
);
5224 ahd
= device_get_softc((device_t
)platform_arg
);
5226 memset(ahd
, 0, sizeof(*ahd
));
5227 ahd
->seep_config
= kmalloc(sizeof(*ahd
->seep_config
),M_DEVBUF
,M_INTWAIT
);
5228 LIST_INIT(&ahd
->pending_scbs
);
5229 LIST_INIT(&ahd
->timedout_scbs
);
5230 /* We don't know our unit number until the OSM sets it */
5233 ahd
->description
= NULL
;
5234 ahd
->bus_description
= NULL
;
5236 ahd
->chip
= AHD_NONE
;
5237 ahd
->features
= AHD_FENONE
;
5238 ahd
->bugs
= AHD_BUGNONE
;
5239 ahd
->flags
= AHD_SPCHK_ENB_A
|AHD_RESET_BUS_A
|AHD_TERM_ENB_A
5240 | AHD_EXTENDED_TRANS_A
|AHD_STPWLEVEL_A
;
5241 aic_timer_init(&ahd
->reset_timer
);
5242 aic_timer_init(&ahd
->stat_timer
);
5243 ahd
->int_coalescing_timer
= AHD_INT_COALESCING_TIMER_DEFAULT
;
5244 ahd
->int_coalescing_maxcmds
= AHD_INT_COALESCING_MAXCMDS_DEFAULT
;
5245 ahd
->int_coalescing_mincmds
= AHD_INT_COALESCING_MINCMDS_DEFAULT
;
5246 ahd
->int_coalescing_threshold
= AHD_INT_COALESCING_THRESHOLD_DEFAULT
;
5247 ahd
->int_coalescing_stop_threshold
=
5248 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT
;
5250 if (ahd_platform_alloc(ahd
, platform_arg
) != 0) {
5256 if ((ahd_debug
& AHD_SHOW_MEMORY
) != 0) {
5257 kprintf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5258 ahd_name(ahd
), (u_int
)sizeof(struct scb
),
5259 (u_int
)sizeof(struct hardware_scb
));
5266 ahd_softc_init(struct ahd_softc
*ahd
)
5275 ahd_softc_insert(struct ahd_softc
*ahd
)
5277 struct ahd_softc
*list_ahd
;
5279 #if AIC_PCI_CONFIG > 0
5281 * Second Function PCI devices need to inherit some
5282 * settings from function 0.
5284 if ((ahd
->features
& AHD_MULTI_FUNC
) != 0) {
5285 TAILQ_FOREACH(list_ahd
, &ahd_tailq
, links
) {
5286 aic_dev_softc_t list_pci
;
5287 aic_dev_softc_t pci
;
5289 list_pci
= list_ahd
->dev_softc
;
5290 pci
= ahd
->dev_softc
;
5291 if (aic_get_pci_slot(list_pci
) == aic_get_pci_slot(pci
)
5292 && aic_get_pci_bus(list_pci
) == aic_get_pci_bus(pci
)) {
5293 struct ahd_softc
*master
;
5294 struct ahd_softc
*slave
;
5296 if (aic_get_pci_function(list_pci
) == 0) {
5303 slave
->flags
&= ~AHD_BIOS_ENABLED
;
5305 master
->flags
& AHD_BIOS_ENABLED
;
5313 * Insertion sort into our list of softcs.
5315 list_ahd
= TAILQ_FIRST(&ahd_tailq
);
5316 while (list_ahd
!= NULL
5317 && ahd_softc_comp(ahd
, list_ahd
) <= 0)
5318 list_ahd
= TAILQ_NEXT(list_ahd
, links
);
5319 if (list_ahd
!= NULL
)
5320 TAILQ_INSERT_BEFORE(list_ahd
, ahd
, links
);
5322 TAILQ_INSERT_TAIL(&ahd_tailq
, ahd
, links
);
5327 ahd_set_unit(struct ahd_softc
*ahd
, int unit
)
5333 ahd_set_name(struct ahd_softc
*ahd
, char *name
)
5335 if (ahd
->name
!= NULL
)
5336 kfree(ahd
->name
, M_DEVBUF
);
5341 ahd_free(struct ahd_softc
*ahd
)
5345 ahd_terminate_recovery_thread(ahd
);
5346 switch (ahd
->init_level
) {
5352 aic_dmamap_unload(ahd
, ahd
->shared_data_dmat
,
5353 ahd
->shared_data_map
.dmamap
);
5356 aic_dmamem_free(ahd
, ahd
->shared_data_dmat
, ahd
->qoutfifo
,
5357 ahd
->shared_data_map
.dmamap
);
5358 aic_dmamap_destroy(ahd
, ahd
->shared_data_dmat
,
5359 ahd
->shared_data_map
.dmamap
);
5362 aic_dma_tag_destroy(ahd
, ahd
->shared_data_dmat
);
5365 aic_dma_tag_destroy(ahd
, ahd
->buffer_dmat
);
5373 aic_dma_tag_destroy(ahd
, ahd
->parent_dmat
);
5375 ahd_platform_free(ahd
);
5376 ahd_fini_scbdata(ahd
);
5377 for (i
= 0; i
< AHD_NUM_TARGETS
; i
++) {
5378 struct ahd_tmode_tstate
*tstate
;
5380 tstate
= ahd
->enabled_targets
[i
];
5381 if (tstate
!= NULL
) {
5382 #ifdef AHD_TARGET_MODE
5385 for (j
= 0; j
< AHD_NUM_LUNS
; j
++) {
5386 struct ahd_tmode_lstate
*lstate
;
5388 lstate
= tstate
->enabled_luns
[j
];
5389 if (lstate
!= NULL
) {
5390 xpt_free_path(lstate
->path
);
5391 kfree(lstate
, M_DEVBUF
);
5395 kfree(tstate
, M_DEVBUF
);
5398 #ifdef AHD_TARGET_MODE
5399 if (ahd
->black_hole
!= NULL
) {
5400 xpt_free_path(ahd
->black_hole
->path
);
5401 kfree(ahd
->black_hole
, M_DEVBUF
);
5404 if (ahd
->name
!= NULL
)
5405 kfree(ahd
->name
, M_DEVBUF
);
5406 if (ahd
->seep_config
!= NULL
)
5407 kfree(ahd
->seep_config
, M_DEVBUF
);
5408 if (ahd
->saved_stack
!= NULL
)
5409 kfree(ahd
->saved_stack
, M_DEVBUF
);
5410 #if !defined(__DragonFly__) && !defined(__FreeBSD__)
5411 kfree(ahd
, M_DEVBUF
);
5417 ahd_shutdown(void *arg
)
5419 struct ahd_softc
*ahd
;
5421 ahd
= (struct ahd_softc
*)arg
;
5424 * Stop periodic timer callbacks.
5426 aic_timer_stop(&ahd
->reset_timer
);
5427 aic_timer_stop(&ahd
->stat_timer
);
5429 /* This will reset most registers to 0, but not all */
5430 ahd_reset(ahd
, /*reinit*/FALSE
);
5434 * Reset the controller and record some information about it
5435 * that is only available just after a reset. If "reinit" is
5436 * non-zero, this reset occured after initial configuration
5437 * and the caller requests that the chip be fully reinitialized
5438 * to a runable state. Chip interrupts are *not* enabled after
5439 * a reinitialization. The caller must enable interrupts via
5440 * ahd_intr_enable().
5443 ahd_reset(struct ahd_softc
*ahd
, int reinit
)
5450 * Preserve the value of the SXFRCTL1 register for all channels.
5451 * It contains settings that affect termination and we don't want
5452 * to disturb the integrity of the bus.
5455 ahd_update_modes(ahd
);
5456 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5457 sxfrctl1
= ahd_inb(ahd
, SXFRCTL1
);
5459 cmd
= aic_pci_read_config(ahd
->dev_softc
, PCIR_COMMAND
, /*bytes*/2);
5460 if ((ahd
->bugs
& AHD_PCIX_CHIPRST_BUG
) != 0) {
5465 * During the assertion of CHIPRST, the chip
5466 * does not disable its parity logic prior to
5467 * the start of the reset. This may cause a
5468 * parity error to be detected and thus a
5469 * spurious SERR or PERR assertion. Disble
5470 * PERR and SERR responses during the CHIPRST.
5472 mod_cmd
= cmd
& ~(PCIM_CMD_PERRESPEN
|PCIM_CMD_SERRESPEN
);
5473 aic_pci_write_config(ahd
->dev_softc
, PCIR_COMMAND
,
5474 mod_cmd
, /*bytes*/2);
5476 ahd_outb(ahd
, HCNTRL
, CHIPRST
| ahd
->pause
);
5479 * Ensure that the reset has finished. We delay 1000us
5480 * prior to reading the register to make sure the chip
5481 * has sufficiently completed its reset to handle register
5487 } while (--wait
&& !(ahd_inb(ahd
, HCNTRL
) & CHIPRSTACK
));
5490 kprintf("%s: WARNING - Failed chip reset! "
5491 "Trying to initialize anyway.\n", ahd_name(ahd
));
5493 ahd_outb(ahd
, HCNTRL
, ahd
->pause
);
5495 if ((ahd
->bugs
& AHD_PCIX_CHIPRST_BUG
) != 0) {
5497 * Clear any latched PCI error status and restore
5498 * previous SERR and PERR response enables.
5500 aic_pci_write_config(ahd
->dev_softc
, PCIR_STATUS
+ 1,
5502 aic_pci_write_config(ahd
->dev_softc
, PCIR_COMMAND
,
5507 * Mode should be SCSI after a chip reset, but lets
5508 * set it just to be safe. We touch the MODE_PTR
5509 * register directly so as to bypass the lazy update
5510 * code in ahd_set_modes().
5512 ahd_known_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5513 ahd_outb(ahd
, MODE_PTR
,
5514 ahd_build_mode_state(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
));
5519 * We must always initialize STPWEN to 1 before we
5520 * restore the saved values. STPWEN is initialized
5521 * to a tri-state condition which can only be cleared
5524 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
|STPWEN
);
5525 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
);
5527 /* Determine chip configuration */
5528 ahd
->features
&= ~AHD_WIDE
;
5529 if ((ahd_inb(ahd
, SBLKCTL
) & SELWIDE
) != 0)
5530 ahd
->features
|= AHD_WIDE
;
5533 * If a recovery action has forced a chip reset,
5534 * re-initialize the chip to our liking.
5543 * Determine the number of SCBs available on the controller
5546 ahd_probe_scbs(struct ahd_softc
*ahd
) {
5549 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
5550 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
5551 for (i
= 0; i
< AHD_SCB_MAX
; i
++) {
5554 ahd_set_scbptr(ahd
, i
);
5555 ahd_outw(ahd
, SCB_BASE
, i
);
5556 for (j
= 2; j
< 64; j
++)
5557 ahd_outb(ahd
, SCB_BASE
+j
, 0);
5558 /* Start out life as unallocated (needing an abort) */
5559 ahd_outb(ahd
, SCB_CONTROL
, MK_MESSAGE
);
5560 if (ahd_inw_scbram(ahd
, SCB_BASE
) != i
)
5562 ahd_set_scbptr(ahd
, 0);
5563 if (ahd_inw_scbram(ahd
, SCB_BASE
) != 0)
5570 ahd_dmamap_cb(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
5574 baddr
= (bus_addr_t
*)arg
;
5575 *baddr
= segs
->ds_addr
;
5579 ahd_initialize_hscbs(struct ahd_softc
*ahd
)
5583 for (i
= 0; i
< ahd
->scb_data
.maxhscbs
; i
++) {
5584 ahd_set_scbptr(ahd
, i
);
5586 /* Clear the control byte. */
5587 ahd_outb(ahd
, SCB_CONTROL
, 0);
5589 /* Set the next pointer */
5590 ahd_outw(ahd
, SCB_NEXT
, SCB_LIST_NULL
);
5595 ahd_init_scbdata(struct ahd_softc
*ahd
)
5597 struct scb_data
*scb_data
;
5600 scb_data
= &ahd
->scb_data
;
5601 TAILQ_INIT(&scb_data
->free_scbs
);
5602 for (i
= 0; i
< AHD_NUM_TARGETS
* AHD_NUM_LUNS_NONPKT
; i
++)
5603 LIST_INIT(&scb_data
->free_scb_lists
[i
]);
5604 LIST_INIT(&scb_data
->any_dev_free_scb_list
);
5605 SLIST_INIT(&scb_data
->hscb_maps
);
5606 SLIST_INIT(&scb_data
->sg_maps
);
5607 SLIST_INIT(&scb_data
->sense_maps
);
5609 /* Determine the number of hardware SCBs and initialize them */
5610 scb_data
->maxhscbs
= ahd_probe_scbs(ahd
);
5611 if (scb_data
->maxhscbs
== 0) {
5612 kprintf("%s: No SCB space found\n", ahd_name(ahd
));
5616 ahd_initialize_hscbs(ahd
);
5619 * Create our DMA tags. These tags define the kinds of device
5620 * accessible memory allocations and memory mappings we will
5621 * need to perform during normal operation.
5623 * Unless we need to further restrict the allocation, we rely
5624 * on the restrictions of the parent dmat, hence the common
5625 * use of MAXADDR and MAXSIZE.
5628 /* DMA tag for our hardware scb structures */
5629 if (aic_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
5630 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5631 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5632 /*highaddr*/BUS_SPACE_MAXADDR
,
5633 /*filter*/NULL
, /*filterarg*/NULL
,
5634 PAGE_SIZE
, /*nsegments*/1,
5635 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5636 /*flags*/0, &scb_data
->hscb_dmat
) != 0) {
5640 scb_data
->init_level
++;
5642 /* DMA tag for our S/G structures. */
5643 if (aic_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/8,
5644 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5645 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5646 /*highaddr*/BUS_SPACE_MAXADDR
,
5647 /*filter*/NULL
, /*filterarg*/NULL
,
5648 ahd_sglist_allocsize(ahd
), /*nsegments*/1,
5649 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5650 /*flags*/0, &scb_data
->sg_dmat
) != 0) {
5654 if ((ahd_debug
& AHD_SHOW_MEMORY
) != 0)
5655 kprintf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd
),
5656 ahd_sglist_allocsize(ahd
));
5659 scb_data
->init_level
++;
5661 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5662 if (aic_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
5663 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5664 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5665 /*highaddr*/BUS_SPACE_MAXADDR
,
5666 /*filter*/NULL
, /*filterarg*/NULL
,
5667 PAGE_SIZE
, /*nsegments*/1,
5668 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5669 /*flags*/0, &scb_data
->sense_dmat
) != 0) {
5673 scb_data
->init_level
++;
5675 /* Perform initial CCB allocation */
5676 while (ahd_alloc_scbs(ahd
) != 0)
5679 if (scb_data
->numscbs
== 0) {
5680 kprintf("%s: ahd_init_scbdata - "
5681 "Unable to allocate initial scbs\n",
5687 * Note that we were successful
5697 ahd_find_scb_by_tag(struct ahd_softc
*ahd
, u_int tag
)
5702 * Look on the pending list.
5704 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
5705 if (SCB_GET_TAG(scb
) == tag
)
5710 * Then on all of the collision free lists.
5712 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
5713 struct scb
*list_scb
;
5717 if (SCB_GET_TAG(list_scb
) == tag
)
5719 list_scb
= LIST_NEXT(list_scb
, collision_links
);
5724 * And finally on the generic free list.
5726 LIST_FOREACH(scb
, &ahd
->scb_data
.any_dev_free_scb_list
, links
.le
) {
5727 if (SCB_GET_TAG(scb
) == tag
)
5735 ahd_fini_scbdata(struct ahd_softc
*ahd
)
5737 struct scb_data
*scb_data
;
5739 scb_data
= &ahd
->scb_data
;
5740 if (scb_data
== NULL
)
5743 switch (scb_data
->init_level
) {
5747 struct map_node
*sns_map
;
5749 while ((sns_map
= SLIST_FIRST(&scb_data
->sense_maps
)) != NULL
) {
5750 SLIST_REMOVE_HEAD(&scb_data
->sense_maps
, links
);
5751 aic_dmamap_unload(ahd
, scb_data
->sense_dmat
,
5753 aic_dmamem_free(ahd
, scb_data
->sense_dmat
,
5754 sns_map
->vaddr
, sns_map
->dmamap
);
5755 kfree(sns_map
, M_DEVBUF
);
5757 aic_dma_tag_destroy(ahd
, scb_data
->sense_dmat
);
5762 struct map_node
*sg_map
;
5764 while ((sg_map
= SLIST_FIRST(&scb_data
->sg_maps
)) != NULL
) {
5765 SLIST_REMOVE_HEAD(&scb_data
->sg_maps
, links
);
5766 aic_dmamap_unload(ahd
, scb_data
->sg_dmat
,
5768 aic_dmamem_free(ahd
, scb_data
->sg_dmat
,
5769 sg_map
->vaddr
, sg_map
->dmamap
);
5770 kfree(sg_map
, M_DEVBUF
);
5772 aic_dma_tag_destroy(ahd
, scb_data
->sg_dmat
);
5777 struct map_node
*hscb_map
;
5779 while ((hscb_map
= SLIST_FIRST(&scb_data
->hscb_maps
)) != NULL
) {
5780 SLIST_REMOVE_HEAD(&scb_data
->hscb_maps
, links
);
5781 aic_dmamap_unload(ahd
, scb_data
->hscb_dmat
,
5783 aic_dmamem_free(ahd
, scb_data
->hscb_dmat
,
5784 hscb_map
->vaddr
, hscb_map
->dmamap
);
5785 kfree(hscb_map
, M_DEVBUF
);
5787 aic_dma_tag_destroy(ahd
, scb_data
->hscb_dmat
);
5800 * DSP filter Bypass must be enabled until the first selection
5801 * after a change in bus mode (Razor #491 and #493).
5804 ahd_setup_iocell_workaround(struct ahd_softc
*ahd
)
5806 ahd_mode_state saved_modes
;
5808 saved_modes
= ahd_save_modes(ahd
);
5809 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
5810 ahd_outb(ahd
, DSPDATACTL
, ahd_inb(ahd
, DSPDATACTL
)
5811 | BYPASSENAB
| RCVROFFSTDIS
| XMITOFFSTDIS
);
5812 ahd_outb(ahd
, SIMODE0
, ahd_inb(ahd
, SIMODE0
) | (ENSELDO
|ENSELDI
));
5814 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5815 kprintf("%s: Setting up iocell workaround\n", ahd_name(ahd
));
5817 ahd_restore_modes(ahd
, saved_modes
);
5818 ahd
->flags
&= ~AHD_HAD_FIRST_SEL
;
5822 ahd_iocell_first_selection(struct ahd_softc
*ahd
)
5824 ahd_mode_state saved_modes
;
5827 if ((ahd
->flags
& AHD_HAD_FIRST_SEL
) != 0)
5829 saved_modes
= ahd_save_modes(ahd
);
5830 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5831 sblkctl
= ahd_inb(ahd
, SBLKCTL
);
5832 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
5834 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5835 kprintf("%s: iocell first selection\n", ahd_name(ahd
));
5837 if ((sblkctl
& ENAB40
) != 0) {
5838 ahd_outb(ahd
, DSPDATACTL
,
5839 ahd_inb(ahd
, DSPDATACTL
) & ~BYPASSENAB
);
5841 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5842 kprintf("%s: BYPASS now disabled\n", ahd_name(ahd
));
5845 ahd_outb(ahd
, SIMODE0
, ahd_inb(ahd
, SIMODE0
) & ~(ENSELDO
|ENSELDI
));
5846 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
5847 ahd_restore_modes(ahd
, saved_modes
);
5848 ahd
->flags
|= AHD_HAD_FIRST_SEL
;
5851 /*************************** SCB Management ***********************************/
5853 ahd_add_col_list(struct ahd_softc
*ahd
, struct scb
*scb
, u_int col_idx
)
5855 struct scb_list
*free_list
;
5856 struct scb_tailq
*free_tailq
;
5857 struct scb
*first_scb
;
5859 scb
->flags
|= SCB_ON_COL_LIST
;
5860 AHD_SET_SCB_COL_IDX(scb
, col_idx
);
5861 free_list
= &ahd
->scb_data
.free_scb_lists
[col_idx
];
5862 free_tailq
= &ahd
->scb_data
.free_scbs
;
5863 first_scb
= LIST_FIRST(free_list
);
5864 if (first_scb
!= NULL
) {
5865 LIST_INSERT_AFTER(first_scb
, scb
, collision_links
);
5867 LIST_INSERT_HEAD(free_list
, scb
, collision_links
);
5868 TAILQ_INSERT_TAIL(free_tailq
, scb
, links
.tqe
);
5873 ahd_rem_col_list(struct ahd_softc
*ahd
, struct scb
*scb
)
5875 struct scb_list
*free_list
;
5876 struct scb_tailq
*free_tailq
;
5877 struct scb
*first_scb
;
5880 scb
->flags
&= ~SCB_ON_COL_LIST
;
5881 col_idx
= AHD_GET_SCB_COL_IDX(ahd
, scb
);
5882 free_list
= &ahd
->scb_data
.free_scb_lists
[col_idx
];
5883 free_tailq
= &ahd
->scb_data
.free_scbs
;
5884 first_scb
= LIST_FIRST(free_list
);
5885 if (first_scb
== scb
) {
5886 struct scb
*next_scb
;
5889 * Maintain order in the collision free
5890 * lists for fairness if this device has
5891 * other colliding tags active.
5893 next_scb
= LIST_NEXT(scb
, collision_links
);
5894 if (next_scb
!= NULL
) {
5895 TAILQ_INSERT_AFTER(free_tailq
, scb
,
5896 next_scb
, links
.tqe
);
5898 TAILQ_REMOVE(free_tailq
, scb
, links
.tqe
);
5900 LIST_REMOVE(scb
, collision_links
);
5904 * Get a free scb. If there are none, see if we can allocate a new SCB.
5907 ahd_get_scb(struct ahd_softc
*ahd
, u_int col_idx
)
5914 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
5915 if (AHD_GET_SCB_COL_IDX(ahd
, scb
) != col_idx
) {
5916 ahd_rem_col_list(ahd
, scb
);
5920 if ((scb
= LIST_FIRST(&ahd
->scb_data
.any_dev_free_scb_list
)) == NULL
) {
5924 if (ahd_alloc_scbs(ahd
) == 0)
5928 LIST_REMOVE(scb
, links
.le
);
5929 if (col_idx
!= AHD_NEVER_COL_IDX
5930 && (scb
->col_scb
!= NULL
)
5931 && (scb
->col_scb
->flags
& SCB_ACTIVE
) == 0) {
5932 LIST_REMOVE(scb
->col_scb
, links
.le
);
5933 ahd_add_col_list(ahd
, scb
->col_scb
, col_idx
);
5936 scb
->flags
|= SCB_ACTIVE
;
5941 * Return an SCB resource to the free list.
5944 ahd_free_scb(struct ahd_softc
*ahd
, struct scb
*scb
)
5947 /* Clean up for the next user */
5948 scb
->flags
= SCB_FLAG_NONE
;
5949 scb
->hscb
->control
= 0;
5950 ahd
->scb_data
.scbindex
[SCB_GET_TAG(scb
)] = NULL
;
5952 if (scb
->col_scb
== NULL
) {
5955 * No collision possible. Just free normally.
5957 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5959 } else if ((scb
->col_scb
->flags
& SCB_ON_COL_LIST
) != 0) {
5962 * The SCB we might have collided with is on
5963 * a free collision list. Put both SCBs on
5966 ahd_rem_col_list(ahd
, scb
->col_scb
);
5967 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5969 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5970 scb
->col_scb
, links
.le
);
5971 } else if ((scb
->col_scb
->flags
5972 & (SCB_PACKETIZED
|SCB_ACTIVE
)) == SCB_ACTIVE
5973 && (scb
->col_scb
->hscb
->control
& TAG_ENB
) != 0) {
5976 * The SCB we might collide with on the next allocation
5977 * is still active in a non-packetized, tagged, context.
5978 * Put us on the SCB collision list.
5980 ahd_add_col_list(ahd
, scb
,
5981 AHD_GET_SCB_COL_IDX(ahd
, scb
->col_scb
));
5984 * The SCB we might collide with on the next allocation
5985 * is either active in a packetized context, or free.
5986 * Since we can't collide, put this SCB on the generic
5989 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5993 aic_platform_scb_free(ahd
, scb
);
5997 ahd_alloc_scbs(struct ahd_softc
*ahd
)
5999 struct scb_data
*scb_data
;
6000 struct scb
*next_scb
;
6001 struct hardware_scb
*hscb
;
6002 struct map_node
*hscb_map
;
6003 struct map_node
*sg_map
;
6004 struct map_node
*sense_map
;
6006 uint8_t *sense_data
;
6007 bus_addr_t hscb_busaddr
;
6008 bus_addr_t sg_busaddr
;
6009 bus_addr_t sense_busaddr
;
6013 scb_data
= &ahd
->scb_data
;
6014 if (scb_data
->numscbs
>= AHD_SCB_MAX_ALLOC
)
6015 /* Can't allocate any more */
6018 if (scb_data
->scbs_left
!= 0) {
6021 offset
= (PAGE_SIZE
/ sizeof(*hscb
)) - scb_data
->scbs_left
;
6022 hscb_map
= SLIST_FIRST(&scb_data
->hscb_maps
);
6023 hscb
= &((struct hardware_scb
*)hscb_map
->vaddr
)[offset
];
6024 hscb_busaddr
= hscb_map
->busaddr
+ (offset
* sizeof(*hscb
));
6026 hscb_map
= kmalloc(sizeof(*hscb_map
), M_DEVBUF
, M_INTWAIT
);
6028 /* Allocate the next batch of hardware SCBs */
6029 if (aic_dmamem_alloc(ahd
, scb_data
->hscb_dmat
,
6030 (void **)&hscb_map
->vaddr
,
6031 BUS_DMA_NOWAIT
, &hscb_map
->dmamap
) != 0) {
6032 kfree(hscb_map
, M_DEVBUF
);
6036 SLIST_INSERT_HEAD(&scb_data
->hscb_maps
, hscb_map
, links
);
6038 aic_dmamap_load(ahd
, scb_data
->hscb_dmat
, hscb_map
->dmamap
,
6039 hscb_map
->vaddr
, PAGE_SIZE
, ahd_dmamap_cb
,
6040 &hscb_map
->busaddr
, /*flags*/0);
6042 hscb
= (struct hardware_scb
*)hscb_map
->vaddr
;
6043 hscb_busaddr
= hscb_map
->busaddr
;
6044 scb_data
->scbs_left
= PAGE_SIZE
/ sizeof(*hscb
);
6047 if (scb_data
->sgs_left
!= 0) {
6050 offset
= ((ahd_sglist_allocsize(ahd
) / ahd_sglist_size(ahd
))
6051 - scb_data
->sgs_left
) * ahd_sglist_size(ahd
);
6052 sg_map
= SLIST_FIRST(&scb_data
->sg_maps
);
6053 segs
= sg_map
->vaddr
+ offset
;
6054 sg_busaddr
= sg_map
->busaddr
+ offset
;
6056 sg_map
= kmalloc(sizeof(*sg_map
), M_DEVBUF
, M_INTWAIT
);
6058 /* Allocate the next batch of S/G lists */
6059 if (aic_dmamem_alloc(ahd
, scb_data
->sg_dmat
,
6060 (void **)&sg_map
->vaddr
,
6061 BUS_DMA_NOWAIT
, &sg_map
->dmamap
) != 0) {
6062 kfree(sg_map
, M_DEVBUF
);
6066 SLIST_INSERT_HEAD(&scb_data
->sg_maps
, sg_map
, links
);
6068 aic_dmamap_load(ahd
, scb_data
->sg_dmat
, sg_map
->dmamap
,
6069 sg_map
->vaddr
, ahd_sglist_allocsize(ahd
),
6070 ahd_dmamap_cb
, &sg_map
->busaddr
, /*flags*/0);
6072 segs
= sg_map
->vaddr
;
6073 sg_busaddr
= sg_map
->busaddr
;
6074 scb_data
->sgs_left
=
6075 ahd_sglist_allocsize(ahd
) / ahd_sglist_size(ahd
);
6077 if (ahd_debug
& AHD_SHOW_MEMORY
)
6078 kprintf("Mapped SG data\n");
6082 if (scb_data
->sense_left
!= 0) {
6085 offset
= PAGE_SIZE
- (AHD_SENSE_BUFSIZE
* scb_data
->sense_left
);
6086 sense_map
= SLIST_FIRST(&scb_data
->sense_maps
);
6087 sense_data
= sense_map
->vaddr
+ offset
;
6088 sense_busaddr
= sense_map
->busaddr
+ offset
;
6090 sense_map
= kmalloc(sizeof(*sense_map
), M_DEVBUF
, M_INTWAIT
);
6092 /* Allocate the next batch of sense buffers */
6093 if (aic_dmamem_alloc(ahd
, scb_data
->sense_dmat
,
6094 (void **)&sense_map
->vaddr
,
6095 BUS_DMA_NOWAIT
, &sense_map
->dmamap
) != 0) {
6096 kfree(sense_map
, M_DEVBUF
);
6100 SLIST_INSERT_HEAD(&scb_data
->sense_maps
, sense_map
, links
);
6102 aic_dmamap_load(ahd
, scb_data
->sense_dmat
, sense_map
->dmamap
,
6103 sense_map
->vaddr
, PAGE_SIZE
, ahd_dmamap_cb
,
6104 &sense_map
->busaddr
, /*flags*/0);
6106 sense_data
= sense_map
->vaddr
;
6107 sense_busaddr
= sense_map
->busaddr
;
6108 scb_data
->sense_left
= PAGE_SIZE
/ AHD_SENSE_BUFSIZE
;
6110 if (ahd_debug
& AHD_SHOW_MEMORY
)
6111 kprintf("Mapped sense data\n");
6115 newcount
= MIN(scb_data
->sense_left
, scb_data
->scbs_left
);
6116 newcount
= MIN(newcount
, scb_data
->sgs_left
);
6117 newcount
= MIN(newcount
, (AHD_SCB_MAX_ALLOC
- scb_data
->numscbs
));
6118 scb_data
->sense_left
-= newcount
;
6119 scb_data
->scbs_left
-= newcount
;
6120 scb_data
->sgs_left
-= newcount
;
6121 for (i
= 0; i
< newcount
; i
++) {
6122 struct scb_platform_data
*pdata
;
6128 next_scb
= kmalloc(sizeof(*next_scb
), M_DEVBUF
, M_INTWAIT
);
6129 pdata
= kmalloc(sizeof(*pdata
), M_DEVBUF
, M_INTWAIT
);
6130 next_scb
->platform_data
= pdata
;
6131 next_scb
->hscb_map
= hscb_map
;
6132 next_scb
->sg_map
= sg_map
;
6133 next_scb
->sense_map
= sense_map
;
6134 next_scb
->sg_list
= segs
;
6135 next_scb
->sense_data
= sense_data
;
6136 next_scb
->sense_busaddr
= sense_busaddr
;
6137 memset(hscb
, 0, sizeof(*hscb
));
6138 next_scb
->hscb
= hscb
;
6139 hscb
->hscb_busaddr
= aic_htole32(hscb_busaddr
);
6142 * The sequencer always starts with the second entry.
6143 * The first entry is embedded in the scb.
6145 next_scb
->sg_list_busaddr
= sg_busaddr
;
6146 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
6147 next_scb
->sg_list_busaddr
6148 += sizeof(struct ahd_dma64_seg
);
6150 next_scb
->sg_list_busaddr
+= sizeof(struct ahd_dma_seg
);
6151 next_scb
->ahd_softc
= ahd
;
6152 next_scb
->flags
= SCB_FLAG_NONE
;
6154 error
= aic_dmamap_create(ahd
, ahd
->buffer_dmat
, /*flags*/0,
6157 kfree(next_scb
, M_DEVBUF
);
6158 kfree(pdata
, M_DEVBUF
);
6162 next_scb
->hscb
->tag
= aic_htole16(scb_data
->numscbs
);
6163 col_tag
= scb_data
->numscbs
^ 0x100;
6164 next_scb
->col_scb
= ahd_find_scb_by_tag(ahd
, col_tag
);
6165 if (next_scb
->col_scb
!= NULL
)
6166 next_scb
->col_scb
->col_scb
= next_scb
;
6167 aic_timer_init(&next_scb
->io_timer
);
6168 ahd_free_scb(ahd
, next_scb
);
6170 hscb_busaddr
+= sizeof(*hscb
);
6171 segs
+= ahd_sglist_size(ahd
);
6172 sg_busaddr
+= ahd_sglist_size(ahd
);
6173 sense_data
+= AHD_SENSE_BUFSIZE
;
6174 sense_busaddr
+= AHD_SENSE_BUFSIZE
;
6175 scb_data
->numscbs
++;
6181 ahd_controller_info(struct ahd_softc
*ahd
, char *buf
)
6187 len
= ksprintf(buf
, "%s: ",
6188 ahd_chip_names
[ahd
->chip
& AHD_CHIPID_MASK
]);
6191 speed
= "Ultra320 ";
6192 if ((ahd
->features
& AHD_WIDE
) != 0) {
6197 len
= ksprintf(buf
, "%s%sChannel %c, SCSI Id=%d, ",
6198 speed
, type
, ahd
->channel
, ahd
->our_id
);
6201 ksprintf(buf
, "%s, %d SCBs", ahd
->bus_description
,
6202 ahd
->scb_data
.maxhscbs
);
6205 static const char *channel_strings
[] = {
6212 static const char *termstat_strings
[] = {
6213 "Terminated Correctly",
6220 * Start the board, ready for normal operation
6223 ahd_init(struct ahd_softc
*ahd
)
6225 uint8_t *next_vaddr
;
6226 bus_addr_t next_baddr
;
6227 size_t driver_data_size
;
6231 uint8_t current_sensing
;
6234 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
6236 ahd
->stack_size
= ahd_probe_stack_size(ahd
);
6237 ahd
->saved_stack
= kmalloc(ahd
->stack_size
* sizeof(uint16_t),
6238 M_DEVBUF
, M_WAITOK
);
6241 * Verify that the compiler hasn't over-agressively
6242 * padded important structures.
6244 if (sizeof(struct hardware_scb
) != 64)
6245 panic("Hardware SCB size is incorrect");
6248 if ((ahd_debug
& AHD_DEBUG_SEQUENCER
) != 0)
6249 ahd
->flags
|= AHD_SEQUENCER_DEBUG
;
6253 * Default to allowing initiator operations.
6255 ahd
->flags
|= AHD_INITIATORROLE
;
6258 * Only allow target mode features if this unit has them enabled.
6260 if ((AHD_TMODE_ENABLE
& (0x1 << ahd
->unit
)) == 0)
6261 ahd
->features
&= ~AHD_TARGETMODE
;
6264 /* DMA tag for mapping buffers into device visible space. */
6265 if (aic_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
6266 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
6267 /*lowaddr*/ahd
->flags
& AHD_39BIT_ADDRESSING
6268 ? (bus_addr_t
)0x7FFFFFFFFFULL
6269 : BUS_SPACE_MAXADDR_32BIT
,
6270 /*highaddr*/BUS_SPACE_MAXADDR
,
6271 /*filter*/NULL
, /*filterarg*/NULL
,
6272 /*maxsize*/(AHD_NSEG
- 1) * PAGE_SIZE
,
6273 /*nsegments*/AHD_NSEG
,
6274 /*maxsegsz*/AHD_MAXTRANSFER_SIZE
,
6275 /*flags*/BUS_DMA_ALLOCNOW
,
6276 &ahd
->buffer_dmat
) != 0) {
6284 * DMA tag for our command fifos and other data in system memory
6285 * the card's sequencer must be able to access. For initiator
6286 * roles, we need to allocate space for the qoutfifo. When providing
6287 * for the target mode role, we must additionally provide space for
6288 * the incoming target command fifo.
6290 driver_data_size
= AHD_SCB_MAX
* sizeof(*ahd
->qoutfifo
)
6291 + sizeof(struct hardware_scb
);
6292 if ((ahd
->features
& AHD_TARGETMODE
) != 0)
6293 driver_data_size
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6294 if ((ahd
->bugs
& AHD_PKT_BITBUCKET_BUG
) != 0)
6295 driver_data_size
+= PKT_OVERRUN_BUFSIZE
;
6296 if (aic_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
6297 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
6298 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
6299 /*highaddr*/BUS_SPACE_MAXADDR
,
6300 /*filter*/NULL
, /*filterarg*/NULL
,
6303 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
6304 /*flags*/0, &ahd
->shared_data_dmat
) != 0) {
6310 /* Allocation of driver data */
6311 if (aic_dmamem_alloc(ahd
, ahd
->shared_data_dmat
,
6312 (void **)&ahd
->shared_data_map
.vaddr
,
6314 &ahd
->shared_data_map
.dmamap
) != 0) {
6320 /* And permanently map it in */
6321 aic_dmamap_load(ahd
, ahd
->shared_data_dmat
, ahd
->shared_data_map
.dmamap
,
6322 ahd
->shared_data_map
.vaddr
, driver_data_size
,
6323 ahd_dmamap_cb
, &ahd
->shared_data_map
.busaddr
,
6325 ahd
->qoutfifo
= (struct ahd_completion
*)ahd
->shared_data_map
.vaddr
;
6326 next_vaddr
= (uint8_t *)&ahd
->qoutfifo
[AHD_QOUT_SIZE
];
6327 next_baddr
= ahd
->shared_data_map
.busaddr
6328 + AHD_QOUT_SIZE
*sizeof(struct ahd_completion
);
6329 if ((ahd
->features
& AHD_TARGETMODE
) != 0) {
6330 ahd
->targetcmds
= (struct target_cmd
*)next_vaddr
;
6331 next_vaddr
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6332 next_baddr
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6335 if ((ahd
->bugs
& AHD_PKT_BITBUCKET_BUG
) != 0) {
6336 ahd
->overrun_buf
= next_vaddr
;
6337 next_vaddr
+= PKT_OVERRUN_BUFSIZE
;
6338 next_baddr
+= PKT_OVERRUN_BUFSIZE
;
6342 * We need one SCB to serve as the "next SCB". Since the
6343 * tag identifier in this SCB will never be used, there is
6344 * no point in using a valid HSCB tag from an SCB pulled from
6345 * the standard free pool. So, we allocate this "sentinel"
6346 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6348 ahd
->next_queued_hscb
= (struct hardware_scb
*)next_vaddr
;
6349 ahd
->next_queued_hscb_map
= &ahd
->shared_data_map
;
6350 ahd
->next_queued_hscb
->hscb_busaddr
= aic_htole32(next_baddr
);
6354 /* Allocate SCB data now that buffer_dmat is initialized */
6355 if (ahd_init_scbdata(ahd
) != 0)
6358 if ((ahd
->flags
& AHD_INITIATORROLE
) == 0)
6359 ahd
->flags
&= ~AHD_RESET_BUS_A
;
6362 * Before committing these settings to the chip, give
6363 * the OSM one last chance to modify our configuration.
6365 ahd_platform_init(ahd
);
6367 /* Bring up the chip. */
6370 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
6372 if ((ahd
->flags
& AHD_CURRENT_SENSING
) == 0)
6376 * Verify termination based on current draw and
6377 * warn user if the bus is over/under terminated.
6379 error
= ahd_write_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
,
6382 kprintf("%s: current sensing timeout 1\n", ahd_name(ahd
));
6385 for (i
= 20, fstat
= FLX_FSTAT_BUSY
;
6386 (fstat
& FLX_FSTAT_BUSY
) != 0 && i
; i
--) {
6387 error
= ahd_read_flexport(ahd
, FLXADDR_FLEXSTAT
, &fstat
);
6389 kprintf("%s: current sensing timeout 2\n",
6395 kprintf("%s: Timedout during current-sensing test\n",
6400 /* Latch Current Sensing status. */
6401 error
= ahd_read_flexport(ahd
, FLXADDR_CURRENT_STAT
, ¤t_sensing
);
6403 kprintf("%s: current sensing timeout 3\n", ahd_name(ahd
));
6407 /* Diable current sensing. */
6408 ahd_write_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
, 0);
6411 if ((ahd_debug
& AHD_SHOW_TERMCTL
) != 0) {
6412 kprintf("%s: current_sensing == 0x%x\n",
6413 ahd_name(ahd
), current_sensing
);
6417 for (i
= 0; i
< 4; i
++, current_sensing
>>= FLX_CSTAT_SHIFT
) {
6420 term_stat
= (current_sensing
& FLX_CSTAT_MASK
);
6421 switch (term_stat
) {
6422 case FLX_CSTAT_OVER
:
6423 case FLX_CSTAT_UNDER
:
6425 case FLX_CSTAT_INVALID
:
6426 case FLX_CSTAT_OKAY
:
6427 if (warn_user
== 0 && bootverbose
== 0)
6429 kprintf("%s: %s Channel %s\n", ahd_name(ahd
),
6430 channel_strings
[i
], termstat_strings
[term_stat
]);
6435 kprintf("%s: WARNING. Termination is not configured correctly.\n"
6436 "%s: WARNING. SCSI bus operations may FAIL.\n",
6437 ahd_name(ahd
), ahd_name(ahd
));
6441 aic_timer_reset(&ahd
->stat_timer
, AHD_STAT_UPDATE_MS
,
6442 ahd_stat_timer
, ahd
);
6447 * (Re)initialize chip state after a chip reset.
6450 ahd_chip_init(struct ahd_softc
*ahd
)
6454 u_int scsiseq_template
;
6459 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6461 * Take the LED out of diagnostic mode
6463 ahd_outb(ahd
, SBLKCTL
, ahd_inb(ahd
, SBLKCTL
) & ~(DIAGLEDEN
|DIAGLEDON
));
6466 * Return HS_MAILBOX to its default value.
6468 ahd
->hs_mailbox
= 0;
6469 ahd_outb(ahd
, HS_MAILBOX
, 0);
6471 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6472 ahd_outb(ahd
, IOWNID
, ahd
->our_id
);
6473 ahd_outb(ahd
, TOWNID
, ahd
->our_id
);
6474 sxfrctl1
= (ahd
->flags
& AHD_TERM_ENB_A
) != 0 ? STPWEN
: 0;
6475 sxfrctl1
|= (ahd
->flags
& AHD_SPCHK_ENB_A
) != 0 ? ENSPCHK
: 0;
6476 if ((ahd
->bugs
& AHD_LONG_SETIMO_BUG
)
6477 && (ahd
->seltime
!= STIMESEL_MIN
)) {
6479 * The selection timer duration is twice as long
6480 * as it should be. Halve it by adding "1" to
6481 * the user specified setting.
6483 sxfrctl1
|= ahd
->seltime
+ STIMESEL_BUG_ADJ
;
6485 sxfrctl1
|= ahd
->seltime
;
6488 ahd_outb(ahd
, SXFRCTL0
, DFON
);
6489 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
|ahd
->seltime
|ENSTIMER
|ACTNEGEN
);
6490 ahd_outb(ahd
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
6493 * Now that termination is set, wait for up
6494 * to 500ms for our transceivers to settle. If
6495 * the adapter does not have a cable attached,
6496 * the transceivers may never settle, so don't
6497 * complain if we fail here.
6500 (ahd_inb(ahd
, SBLKCTL
) & (ENAB40
|ENAB20
)) == 0 && wait
;
6504 /* Clear any false bus resets due to the transceivers settling */
6505 ahd_outb(ahd
, CLRSINT1
, CLRSCSIRSTI
);
6506 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
6508 /* Initialize mode specific S/G state. */
6509 for (i
= 0; i
< 2; i
++) {
6510 ahd_set_modes(ahd
, AHD_MODE_DFF0
+ i
, AHD_MODE_DFF0
+ i
);
6511 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
6512 ahd_outb(ahd
, SG_STATE
, 0);
6513 ahd_outb(ahd
, CLRSEQINTSRC
, 0xFF);
6514 ahd_outb(ahd
, SEQIMODE
,
6515 ENSAVEPTRS
|ENCFG4DATA
|ENCFG4ISTAT
6516 |ENCFG4TSTAT
|ENCFG4ICMD
|ENCFG4TCMD
);
6519 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
6520 ahd_outb(ahd
, DSCOMMAND0
, ahd_inb(ahd
, DSCOMMAND0
)|MPARCKEN
|CACHETHEN
);
6521 ahd_outb(ahd
, DFF_THRSH
, RD_DFTHRSH_75
|WR_DFTHRSH_75
);
6522 ahd_outb(ahd
, SIMODE0
, ENIOERR
|ENOVERRUN
);
6523 ahd_outb(ahd
, SIMODE3
, ENNTRAMPERR
|ENOSRAMPERR
);
6524 if ((ahd
->bugs
& AHD_BUSFREEREV_BUG
) != 0) {
6525 ahd_outb(ahd
, OPTIONMODE
, AUTOACKEN
|AUTO_MSGOUT_DE
);
6527 ahd_outb(ahd
, OPTIONMODE
, AUTOACKEN
|BUSFREEREV
|AUTO_MSGOUT_DE
);
6529 ahd_outb(ahd
, SCSCHKN
, CURRFIFODEF
|WIDERESEN
|SHVALIDSTDIS
);
6530 if ((ahd
->chip
& AHD_BUS_MASK
) == AHD_PCIX
)
6532 * Do not issue a target abort when a split completion
6533 * error occurs. Let our PCIX interrupt handler deal
6534 * with it instead. H2A4 Razor #625
6536 ahd_outb(ahd
, PCIXCTL
, ahd_inb(ahd
, PCIXCTL
) | SPLTSTADIS
);
6538 if ((ahd
->bugs
& AHD_LQOOVERRUN_BUG
) != 0)
6539 ahd_outb(ahd
, LQOSCSCTL
, LQONOCHKOVER
);
6542 * Tweak IOCELL settings.
6544 if ((ahd
->flags
& AHD_HP_BOARD
) != 0) {
6545 for (i
= 0; i
< NUMDSPS
; i
++) {
6546 ahd_outb(ahd
, DSPSELECT
, i
);
6547 ahd_outb(ahd
, WRTBIASCTL
, WRTBIASCTL_HP_DEFAULT
);
6550 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
6551 kprintf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd
),
6552 WRTBIASCTL_HP_DEFAULT
);
6555 ahd_setup_iocell_workaround(ahd
);
6558 * Enable LQI Manager interrupts.
6560 ahd_outb(ahd
, LQIMODE1
, ENLQIPHASE_LQ
|ENLQIPHASE_NLQ
|ENLIQABORT
6561 | ENLQICRCI_LQ
|ENLQICRCI_NLQ
|ENLQIBADLQI
6562 | ENLQIOVERI_LQ
|ENLQIOVERI_NLQ
);
6563 ahd_outb(ahd
, LQOMODE0
, ENLQOATNLQ
|ENLQOATNPKT
|ENLQOTCRC
);
6565 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6566 * manually for the command phase at the start of a packetized
6567 * selection case. ENLQOBUSFREE should be made redundant by
6568 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6569 * events fail to assert the BUSFREE interrupt so we must
6570 * also enable LQOBUSFREE interrupts.
6572 ahd_outb(ahd
, LQOMODE1
, ENLQOBUSFREE
);
6575 * Setup sequencer interrupt handlers.
6577 ahd_outw(ahd
, INTVEC1_ADDR
, ahd_resolve_seqaddr(ahd
, LABEL_seq_isr
));
6578 ahd_outw(ahd
, INTVEC2_ADDR
, ahd_resolve_seqaddr(ahd
, LABEL_timer_isr
));
6581 * Setup SCB Offset registers.
6583 if ((ahd
->bugs
& AHD_PKT_LUN_BUG
) != 0) {
6584 ahd_outb(ahd
, LUNPTR
, offsetof(struct hardware_scb
,
6587 ahd_outb(ahd
, LUNPTR
, offsetof(struct hardware_scb
, lun
));
6589 ahd_outb(ahd
, CMDLENPTR
, offsetof(struct hardware_scb
, cdb_len
));
6590 ahd_outb(ahd
, ATTRPTR
, offsetof(struct hardware_scb
, task_attribute
));
6591 ahd_outb(ahd
, FLAGPTR
, offsetof(struct hardware_scb
, task_management
));
6592 ahd_outb(ahd
, CMDPTR
, offsetof(struct hardware_scb
,
6593 shared_data
.idata
.cdb
));
6594 ahd_outb(ahd
, QNEXTPTR
,
6595 offsetof(struct hardware_scb
, next_hscb_busaddr
));
6596 ahd_outb(ahd
, ABRTBITPTR
, MK_MESSAGE_BIT_OFFSET
);
6597 ahd_outb(ahd
, ABRTBYTEPTR
, offsetof(struct hardware_scb
, control
));
6598 if ((ahd
->bugs
& AHD_PKT_LUN_BUG
) != 0) {
6599 ahd_outb(ahd
, LUNLEN
,
6600 sizeof(ahd
->next_queued_hscb
->pkt_long_lun
) - 1);
6602 ahd_outb(ahd
, LUNLEN
, LUNLEN_SINGLE_LEVEL_LUN
);
6604 ahd_outb(ahd
, CDBLIMIT
, SCB_CDB_LEN_PTR
- 1);
6605 ahd_outb(ahd
, MAXCMD
, 0xFF);
6606 ahd_outb(ahd
, SCBAUTOPTR
,
6607 AUSCBPTR_EN
| offsetof(struct hardware_scb
, tag
));
6609 /* We haven't been enabled for target mode yet. */
6610 ahd_outb(ahd
, MULTARGID
, 0);
6611 ahd_outb(ahd
, MULTARGID
+ 1, 0);
6613 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6614 /* Initialize the negotiation table. */
6615 if ((ahd
->features
& AHD_NEW_IOCELL_OPTS
) == 0) {
6617 * Clear the spare bytes in the neg table to avoid
6618 * spurious parity errors.
6620 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6621 ahd_outb(ahd
, NEGOADDR
, target
);
6622 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_PER_DEV0
);
6623 for (i
= 0; i
< AHD_NUM_PER_DEV_ANNEXCOLS
; i
++)
6624 ahd_outb(ahd
, ANNEXDAT
, 0);
6627 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6628 struct ahd_devinfo devinfo
;
6629 struct ahd_initiator_tinfo
*tinfo
;
6630 struct ahd_tmode_tstate
*tstate
;
6632 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6634 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6635 target
, CAM_LUN_WILDCARD
,
6636 'A', ROLE_INITIATOR
);
6637 ahd_update_neg_table(ahd
, &devinfo
, &tinfo
->curr
);
6640 ahd_outb(ahd
, CLRSINT3
, NTRAMPERR
|OSRAMPERR
);
6641 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
6643 #ifdef NEEDS_MORE_TESTING
6645 * Always enable abort on incoming L_Qs if this feature is
6646 * supported. We use this to catch invalid SCB references.
6648 if ((ahd
->bugs
& AHD_ABORT_LQI_BUG
) == 0)
6649 ahd_outb(ahd
, LQCTL1
, ABORTPENDING
);
6652 ahd_outb(ahd
, LQCTL1
, 0);
6654 /* All of our queues are empty */
6655 ahd
->qoutfifonext
= 0;
6656 ahd
->qoutfifonext_valid_tag
= QOUTFIFO_ENTRY_VALID
;
6657 ahd_outb(ahd
, QOUTFIFO_ENTRY_VALID_TAG
, QOUTFIFO_ENTRY_VALID
);
6658 for (i
= 0; i
< AHD_QOUT_SIZE
; i
++)
6659 ahd
->qoutfifo
[i
].valid_tag
= 0;
6660 ahd_sync_qoutfifo(ahd
, BUS_DMASYNC_PREREAD
);
6662 ahd
->qinfifonext
= 0;
6663 for (i
= 0; i
< AHD_QIN_SIZE
; i
++)
6664 ahd
->qinfifo
[i
] = SCB_LIST_NULL
;
6666 if ((ahd
->features
& AHD_TARGETMODE
) != 0) {
6667 /* All target command blocks start out invalid. */
6668 for (i
= 0; i
< AHD_TMODE_CMDS
; i
++)
6669 ahd
->targetcmds
[i
].cmd_valid
= 0;
6670 ahd_sync_tqinfifo(ahd
, BUS_DMASYNC_PREREAD
);
6671 ahd
->tqinfifonext
= 1;
6672 ahd_outb(ahd
, KERNEL_TQINPOS
, ahd
->tqinfifonext
- 1);
6673 ahd_outb(ahd
, TQINPOS
, ahd
->tqinfifonext
);
6676 /* Initialize Scratch Ram. */
6677 ahd_outb(ahd
, SEQ_FLAGS
, 0);
6678 ahd_outb(ahd
, SEQ_FLAGS2
, 0);
6680 /* We don't have any waiting selections */
6681 ahd_outw(ahd
, WAITING_TID_HEAD
, SCB_LIST_NULL
);
6682 ahd_outw(ahd
, WAITING_TID_TAIL
, SCB_LIST_NULL
);
6683 ahd_outw(ahd
, MK_MESSAGE_SCB
, SCB_LIST_NULL
);
6684 ahd_outw(ahd
, MK_MESSAGE_SCSIID
, 0xFF);
6685 for (i
= 0; i
< AHD_NUM_TARGETS
; i
++)
6686 ahd_outw(ahd
, WAITING_SCB_TAILS
+ (2 * i
), SCB_LIST_NULL
);
6689 * Nobody is waiting to be DMAed into the QOUTFIFO.
6691 ahd_outw(ahd
, COMPLETE_SCB_HEAD
, SCB_LIST_NULL
);
6692 ahd_outw(ahd
, COMPLETE_SCB_DMAINPROG_HEAD
, SCB_LIST_NULL
);
6693 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, SCB_LIST_NULL
);
6694 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, SCB_LIST_NULL
);
6695 ahd_outw(ahd
, COMPLETE_ON_QFREEZE_HEAD
, SCB_LIST_NULL
);
6698 * The Freeze Count is 0.
6700 ahd
->qfreeze_cnt
= 0;
6701 ahd_outw(ahd
, QFREEZE_COUNT
, 0);
6702 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, 0);
6705 * Tell the sequencer where it can find our arrays in memory.
6707 busaddr
= ahd
->shared_data_map
.busaddr
;
6708 ahd_outl(ahd
, SHARED_DATA_ADDR
, busaddr
);
6709 ahd_outl(ahd
, QOUTFIFO_NEXT_ADDR
, busaddr
);
6712 * Setup the allowed SCSI Sequences based on operational mode.
6713 * If we are a target, we'll enable select in operations once
6714 * we've had a lun enabled.
6716 scsiseq_template
= ENAUTOATNP
;
6717 if ((ahd
->flags
& AHD_INITIATORROLE
) != 0)
6718 scsiseq_template
|= ENRSELI
;
6719 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq_template
);
6721 /* There are no busy SCBs yet. */
6722 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6725 for (lun
= 0; lun
< AHD_NUM_LUNS_NONPKT
; lun
++)
6726 ahd_unbusy_tcl(ahd
, BUILD_TCL_RAW(target
, 'A', lun
));
6730 * Initialize the group code to command length table.
6731 * Vendor Unique codes are set to 0 so we only capture
6732 * the first byte of the cdb. These can be overridden
6733 * when target mode is enabled.
6735 ahd_outb(ahd
, CMDSIZE_TABLE
, 5);
6736 ahd_outb(ahd
, CMDSIZE_TABLE
+ 1, 9);
6737 ahd_outb(ahd
, CMDSIZE_TABLE
+ 2, 9);
6738 ahd_outb(ahd
, CMDSIZE_TABLE
+ 3, 0);
6739 ahd_outb(ahd
, CMDSIZE_TABLE
+ 4, 15);
6740 ahd_outb(ahd
, CMDSIZE_TABLE
+ 5, 11);
6741 ahd_outb(ahd
, CMDSIZE_TABLE
+ 6, 0);
6742 ahd_outb(ahd
, CMDSIZE_TABLE
+ 7, 0);
6744 /* Tell the sequencer of our initial queue positions */
6745 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
6746 ahd_outb(ahd
, QOFF_CTLSTA
, SCB_QSIZE_512
);
6747 ahd
->qinfifonext
= 0;
6748 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
6749 ahd_set_hescb_qoff(ahd
, 0);
6750 ahd_set_snscb_qoff(ahd
, 0);
6751 ahd_set_sescb_qoff(ahd
, 0);
6752 ahd_set_sdscb_qoff(ahd
, 0);
6755 * Tell the sequencer which SCB will be the next one it receives.
6757 busaddr
= aic_le32toh(ahd
->next_queued_hscb
->hscb_busaddr
);
6758 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
6761 * Default to coalescing disabled.
6763 ahd_outw(ahd
, INT_COALESCING_CMDCOUNT
, 0);
6764 ahd_outw(ahd
, CMDS_PENDING
, 0);
6765 ahd_update_coalescing_values(ahd
, ahd
->int_coalescing_timer
,
6766 ahd
->int_coalescing_maxcmds
,
6767 ahd
->int_coalescing_mincmds
);
6768 ahd_enable_coalescing(ahd
, FALSE
);
6771 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6775 * Setup default device and controller settings.
6776 * This should only be called if our probe has
6777 * determined that no configuration data is available.
6780 ahd_default_config(struct ahd_softc
*ahd
)
6787 * Allocate a tstate to house information for our
6788 * initiator presence on the bus as well as the user
6789 * data for any target mode initiator.
6791 if (ahd_alloc_tstate(ahd
, ahd
->our_id
, 'A') == NULL
) {
6792 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6793 "Failing attach\n", ahd_name(ahd
));
6797 for (targ
= 0; targ
< AHD_NUM_TARGETS
; targ
++) {
6798 struct ahd_devinfo devinfo
;
6799 struct ahd_initiator_tinfo
*tinfo
;
6800 struct ahd_tmode_tstate
*tstate
;
6801 uint16_t target_mask
;
6803 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6806 * We support SPC2 and SPI4.
6808 tinfo
->user
.protocol_version
= 4;
6809 tinfo
->user
.transport_version
= 4;
6811 target_mask
= 0x01 << targ
;
6812 ahd
->user_discenable
|= target_mask
;
6813 tstate
->discenable
|= target_mask
;
6814 ahd
->user_tagenable
|= target_mask
;
6815 #ifdef AHD_FORCE_160
6816 tinfo
->user
.period
= AHD_SYNCRATE_DT
;
6818 tinfo
->user
.period
= AHD_SYNCRATE_160
;
6820 tinfo
->user
.offset
= MAX_OFFSET
;
6821 tinfo
->user
.ppr_options
= MSG_EXT_PPR_RD_STRM
6822 | MSG_EXT_PPR_WR_FLOW
6823 | MSG_EXT_PPR_HOLD_MCS
6824 | MSG_EXT_PPR_IU_REQ
6825 | MSG_EXT_PPR_QAS_REQ
6826 | MSG_EXT_PPR_DT_REQ
;
6827 if ((ahd
->features
& AHD_RTI
) != 0)
6828 tinfo
->user
.ppr_options
|= MSG_EXT_PPR_RTI
;
6830 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
6833 * Start out Async/Narrow/Untagged and with
6834 * conservative protocol support.
6836 tinfo
->goal
.protocol_version
= 2;
6837 tinfo
->goal
.transport_version
= 2;
6838 tinfo
->curr
.protocol_version
= 2;
6839 tinfo
->curr
.transport_version
= 2;
6840 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6841 targ
, CAM_LUN_WILDCARD
,
6842 'A', ROLE_INITIATOR
);
6843 tstate
->tagenable
&= ~target_mask
;
6844 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6845 AHD_TRANS_CUR
|AHD_TRANS_GOAL
, /*paused*/TRUE
);
6846 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0, /*offset*/0,
6847 /*ppr_options*/0, AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
6854 * Parse device configuration information.
6857 ahd_parse_cfgdata(struct ahd_softc
*ahd
, struct seeprom_config
*sc
)
6862 max_targ
= sc
->max_targets
& CFMAXTARG
;
6863 ahd
->our_id
= sc
->brtime_id
& CFSCSIID
;
6866 * Allocate a tstate to house information for our
6867 * initiator presence on the bus as well as the user
6868 * data for any target mode initiator.
6870 if (ahd_alloc_tstate(ahd
, ahd
->our_id
, 'A') == NULL
) {
6871 kprintf("%s: unable to allocate ahd_tmode_tstate. "
6872 "Failing attach\n", ahd_name(ahd
));
6876 for (targ
= 0; targ
< max_targ
; targ
++) {
6877 struct ahd_devinfo devinfo
;
6878 struct ahd_initiator_tinfo
*tinfo
;
6879 struct ahd_transinfo
*user_tinfo
;
6880 struct ahd_tmode_tstate
*tstate
;
6881 uint16_t target_mask
;
6883 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6885 user_tinfo
= &tinfo
->user
;
6888 * We support SPC2 and SPI4.
6890 tinfo
->user
.protocol_version
= 4;
6891 tinfo
->user
.transport_version
= 4;
6893 target_mask
= 0x01 << targ
;
6894 ahd
->user_discenable
&= ~target_mask
;
6895 tstate
->discenable
&= ~target_mask
;
6896 ahd
->user_tagenable
&= ~target_mask
;
6897 if (sc
->device_flags
[targ
] & CFDISC
) {
6898 tstate
->discenable
|= target_mask
;
6899 ahd
->user_discenable
|= target_mask
;
6900 ahd
->user_tagenable
|= target_mask
;
6903 * Cannot be packetized without disconnection.
6905 sc
->device_flags
[targ
] &= ~CFPACKETIZED
;
6908 user_tinfo
->ppr_options
= 0;
6909 user_tinfo
->period
= (sc
->device_flags
[targ
] & CFXFER
);
6910 if (user_tinfo
->period
< CFXFER_ASYNC
) {
6911 if (user_tinfo
->period
<= AHD_PERIOD_10MHz
)
6912 user_tinfo
->ppr_options
|= MSG_EXT_PPR_DT_REQ
;
6913 user_tinfo
->offset
= MAX_OFFSET
;
6915 user_tinfo
->offset
= 0;
6916 user_tinfo
->period
= AHD_ASYNC_XFER_PERIOD
;
6918 #ifdef AHD_FORCE_160
6919 if (user_tinfo
->period
<= AHD_SYNCRATE_160
)
6920 user_tinfo
->period
= AHD_SYNCRATE_DT
;
6923 if ((sc
->device_flags
[targ
] & CFPACKETIZED
) != 0) {
6924 user_tinfo
->ppr_options
|= MSG_EXT_PPR_RD_STRM
6925 | MSG_EXT_PPR_WR_FLOW
6926 | MSG_EXT_PPR_HOLD_MCS
6927 | MSG_EXT_PPR_IU_REQ
;
6928 if ((ahd
->features
& AHD_RTI
) != 0)
6929 user_tinfo
->ppr_options
|= MSG_EXT_PPR_RTI
;
6932 if ((sc
->device_flags
[targ
] & CFQAS
) != 0)
6933 user_tinfo
->ppr_options
|= MSG_EXT_PPR_QAS_REQ
;
6935 if ((sc
->device_flags
[targ
] & CFWIDEB
) != 0)
6936 user_tinfo
->width
= MSG_EXT_WDTR_BUS_16_BIT
;
6938 user_tinfo
->width
= MSG_EXT_WDTR_BUS_8_BIT
;
6940 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
6941 kprintf("(%d): %x:%x:%x:%x\n", targ
, user_tinfo
->width
,
6942 user_tinfo
->period
, user_tinfo
->offset
,
6943 user_tinfo
->ppr_options
);
6946 * Start out Async/Narrow/Untagged and with
6947 * conservative protocol support.
6949 tstate
->tagenable
&= ~target_mask
;
6950 tinfo
->goal
.protocol_version
= 2;
6951 tinfo
->goal
.transport_version
= 2;
6952 tinfo
->curr
.protocol_version
= 2;
6953 tinfo
->curr
.transport_version
= 2;
6954 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6955 targ
, CAM_LUN_WILDCARD
,
6956 'A', ROLE_INITIATOR
);
6957 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6958 AHD_TRANS_CUR
|AHD_TRANS_GOAL
, /*paused*/TRUE
);
6959 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0, /*offset*/0,
6960 /*ppr_options*/0, AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
6964 ahd
->flags
&= ~AHD_SPCHK_ENB_A
;
6965 if (sc
->bios_control
& CFSPARITY
)
6966 ahd
->flags
|= AHD_SPCHK_ENB_A
;
6968 ahd
->flags
&= ~AHD_RESET_BUS_A
;
6969 if (sc
->bios_control
& CFRESETB
)
6970 ahd
->flags
|= AHD_RESET_BUS_A
;
6972 ahd
->flags
&= ~AHD_EXTENDED_TRANS_A
;
6973 if (sc
->bios_control
& CFEXTEND
)
6974 ahd
->flags
|= AHD_EXTENDED_TRANS_A
;
6976 ahd
->flags
&= ~AHD_BIOS_ENABLED
;
6977 if ((sc
->bios_control
& CFBIOSSTATE
) == CFBS_ENABLED
)
6978 ahd
->flags
|= AHD_BIOS_ENABLED
;
6980 ahd
->flags
&= ~AHD_STPWLEVEL_A
;
6981 if ((sc
->adapter_control
& CFSTPWLEVEL
) != 0)
6982 ahd
->flags
|= AHD_STPWLEVEL_A
;
6988 * Parse device configuration information.
6991 ahd_parse_vpddata(struct ahd_softc
*ahd
, struct vpd_config
*vpd
)
6995 error
= ahd_verify_vpd_cksum(vpd
);
6998 if ((vpd
->bios_flags
& VPDBOOTHOST
) != 0)
6999 ahd
->flags
|= AHD_BOOT_CHANNEL
;
7004 ahd_intr_enable(struct ahd_softc
*ahd
, int enable
)
7008 hcntrl
= ahd_inb(ahd
, HCNTRL
);
7010 ahd
->pause
&= ~INTEN
;
7011 ahd
->unpause
&= ~INTEN
;
7014 ahd
->pause
|= INTEN
;
7015 ahd
->unpause
|= INTEN
;
7017 ahd_outb(ahd
, HCNTRL
, hcntrl
);
7021 ahd_update_coalescing_values(struct ahd_softc
*ahd
, u_int timer
, u_int maxcmds
,
7024 if (timer
> AHD_TIMER_MAX_US
)
7025 timer
= AHD_TIMER_MAX_US
;
7026 ahd
->int_coalescing_timer
= timer
;
7028 if (maxcmds
> AHD_INT_COALESCING_MAXCMDS_MAX
)
7029 maxcmds
= AHD_INT_COALESCING_MAXCMDS_MAX
;
7030 if (mincmds
> AHD_INT_COALESCING_MINCMDS_MAX
)
7031 mincmds
= AHD_INT_COALESCING_MINCMDS_MAX
;
7032 ahd
->int_coalescing_maxcmds
= maxcmds
;
7033 ahd_outw(ahd
, INT_COALESCING_TIMER
, timer
/ AHD_TIMER_US_PER_TICK
);
7034 ahd_outb(ahd
, INT_COALESCING_MAXCMDS
, -maxcmds
);
7035 ahd_outb(ahd
, INT_COALESCING_MINCMDS
, -mincmds
);
7039 ahd_enable_coalescing(struct ahd_softc
*ahd
, int enable
)
7042 ahd
->hs_mailbox
&= ~ENINT_COALESCE
;
7044 ahd
->hs_mailbox
|= ENINT_COALESCE
;
7045 ahd_outb(ahd
, HS_MAILBOX
, ahd
->hs_mailbox
);
7046 ahd_flush_device_writes(ahd
);
7047 ahd_run_qoutfifo(ahd
);
7051 * Ensure that the card is paused in a location
7052 * outside of all critical sections and that all
7053 * pending work is completed prior to returning.
7054 * This routine should only be called from outside
7055 * an interrupt context.
7058 ahd_pause_and_flushwork(struct ahd_softc
*ahd
)
7064 ahd
->flags
|= AHD_ALL_INTERRUPTS
;
7067 * Freeze the outgoing selections. We do this only
7068 * until we are safely paused without further selections
7072 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
7073 ahd_outb(ahd
, SEQ_FLAGS2
, ahd_inb(ahd
, SEQ_FLAGS2
) | SELECTOUT_QFROZEN
);
7078 * Give the sequencer some time to service
7079 * any active selections.
7085 intstat
= ahd_inb(ahd
, INTSTAT
);
7086 if ((intstat
& INT_PEND
) == 0) {
7087 ahd_clear_critical_section(ahd
);
7088 intstat
= ahd_inb(ahd
, INTSTAT
);
7091 && (intstat
!= 0xFF || (ahd
->features
& AHD_REMOVABLE
) == 0)
7092 && ((intstat
& INT_PEND
) != 0
7093 || (ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) != 0
7094 || (ahd_inb(ahd
, SSTAT0
) & (SELDO
|SELINGO
)) != 0));
7096 if (maxloops
== 0) {
7097 kprintf("Infinite interrupt loop, INTSTAT = %x",
7098 ahd_inb(ahd
, INTSTAT
));
7101 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
7103 ahd_flush_qoutfifo(ahd
);
7105 ahd_platform_flushwork(ahd
);
7106 ahd
->flags
&= ~AHD_ALL_INTERRUPTS
;
7110 ahd_suspend(struct ahd_softc
*ahd
)
7113 ahd_pause_and_flushwork(ahd
);
7115 if (LIST_FIRST(&ahd
->pending_scbs
) != NULL
) {
7124 ahd_resume(struct ahd_softc
*ahd
)
7127 ahd_reset(ahd
, /*reinit*/TRUE
);
7128 ahd_intr_enable(ahd
, TRUE
);
7133 /************************** Busy Target Table *********************************/
7135 * Set SCBPTR to the SCB that contains the busy
7136 * table entry for TCL. Return the offset into
7137 * the SCB that contains the entry for TCL.
7138 * saved_scbid is dereferenced and set to the
7139 * scbid that should be restored once manipualtion
7140 * of the TCL entry is complete.
7142 static __inline u_int
7143 ahd_index_busy_tcl(struct ahd_softc
*ahd
, u_int
*saved_scbid
, u_int tcl
)
7146 * Index to the SCB that contains the busy entry.
7148 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7149 *saved_scbid
= ahd_get_scbptr(ahd
);
7150 ahd_set_scbptr(ahd
, TCL_LUN(tcl
)
7151 | ((TCL_TARGET_OFFSET(tcl
) & 0xC) << 4));
7154 * And now calculate the SCB offset to the entry.
7155 * Each entry is 2 bytes wide, hence the
7156 * multiplication by 2.
7158 return (((TCL_TARGET_OFFSET(tcl
) & 0x3) << 1) + SCB_DISCONNECTED_LISTS
);
7162 * Return the untagged transaction id for a given target/channel lun.
7165 ahd_find_busy_tcl(struct ahd_softc
*ahd
, u_int tcl
)
7171 scb_offset
= ahd_index_busy_tcl(ahd
, &saved_scbptr
, tcl
);
7172 scbid
= ahd_inw_scbram(ahd
, scb_offset
);
7173 ahd_set_scbptr(ahd
, saved_scbptr
);
7178 ahd_busy_tcl(struct ahd_softc
*ahd
, u_int tcl
, u_int scbid
)
7183 scb_offset
= ahd_index_busy_tcl(ahd
, &saved_scbptr
, tcl
);
7184 ahd_outw(ahd
, scb_offset
, scbid
);
7185 ahd_set_scbptr(ahd
, saved_scbptr
);
7188 /************************** SCB and SCB queue management **********************/
7190 ahd_match_scb(struct ahd_softc
*ahd
, struct scb
*scb
, int target
,
7191 char channel
, int lun
, u_int tag
, role_t role
)
7193 int targ
= SCB_GET_TARGET(ahd
, scb
);
7194 char chan
= SCB_GET_CHANNEL(ahd
, scb
);
7195 int slun
= SCB_GET_LUN(scb
);
7198 match
= ((chan
== channel
) || (channel
== ALL_CHANNELS
));
7200 match
= ((targ
== target
) || (target
== CAM_TARGET_WILDCARD
));
7202 match
= ((lun
== slun
) || (lun
== CAM_LUN_WILDCARD
));
7204 #ifdef AHD_TARGET_MODE
7207 group
= XPT_FC_GROUP(scb
->io_ctx
->ccb_h
.func_code
);
7208 if (role
== ROLE_INITIATOR
) {
7209 match
= (group
!= XPT_FC_GROUP_TMODE
)
7210 && ((tag
== SCB_GET_TAG(scb
))
7211 || (tag
== SCB_LIST_NULL
));
7212 } else if (role
== ROLE_TARGET
) {
7213 match
= (group
== XPT_FC_GROUP_TMODE
)
7214 && ((tag
== scb
->io_ctx
->csio
.tag_id
)
7215 || (tag
== SCB_LIST_NULL
));
7217 #else /* !AHD_TARGET_MODE */
7218 match
= ((tag
== SCB_GET_TAG(scb
)) || (tag
== SCB_LIST_NULL
));
7219 #endif /* AHD_TARGET_MODE */
7226 ahd_freeze_devq(struct ahd_softc
*ahd
, struct scb
*scb
)
7232 target
= SCB_GET_TARGET(ahd
, scb
);
7233 lun
= SCB_GET_LUN(scb
);
7234 channel
= SCB_GET_CHANNEL(ahd
, scb
);
7236 ahd_search_qinfifo(ahd
, target
, channel
, lun
,
7237 /*tag*/SCB_LIST_NULL
, ROLE_UNKNOWN
,
7238 CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
7240 ahd_platform_freeze_devq(ahd
, scb
);
7244 ahd_qinfifo_requeue_tail(struct ahd_softc
*ahd
, struct scb
*scb
)
7246 struct scb
*prev_scb
;
7247 ahd_mode_state saved_modes
;
7249 saved_modes
= ahd_save_modes(ahd
);
7250 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7252 if (ahd_qinfifo_count(ahd
) != 0) {
7256 prev_pos
= AHD_QIN_WRAP(ahd
->qinfifonext
- 1);
7257 prev_tag
= ahd
->qinfifo
[prev_pos
];
7258 prev_scb
= ahd_lookup_scb(ahd
, prev_tag
);
7260 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7261 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
7262 ahd_restore_modes(ahd
, saved_modes
);
7266 ahd_qinfifo_requeue(struct ahd_softc
*ahd
, struct scb
*prev_scb
,
7269 if (prev_scb
== NULL
) {
7272 busaddr
= aic_le32toh(scb
->hscb
->hscb_busaddr
);
7273 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
7275 prev_scb
->hscb
->next_hscb_busaddr
= scb
->hscb
->hscb_busaddr
;
7276 ahd_sync_scb(ahd
, prev_scb
,
7277 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
7279 ahd
->qinfifo
[AHD_QIN_WRAP(ahd
->qinfifonext
)] = SCB_GET_TAG(scb
);
7281 scb
->hscb
->next_hscb_busaddr
= ahd
->next_queued_hscb
->hscb_busaddr
;
7282 ahd_sync_scb(ahd
, scb
, BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
7286 ahd_qinfifo_count(struct ahd_softc
*ahd
)
7290 u_int wrap_qinfifonext
;
7292 AHD_ASSERT_MODES(ahd
, AHD_MODE_CCHAN_MSK
, AHD_MODE_CCHAN_MSK
);
7293 qinpos
= ahd_get_snscb_qoff(ahd
);
7294 wrap_qinpos
= AHD_QIN_WRAP(qinpos
);
7295 wrap_qinfifonext
= AHD_QIN_WRAP(ahd
->qinfifonext
);
7296 if (wrap_qinfifonext
>= wrap_qinpos
)
7297 return (wrap_qinfifonext
- wrap_qinpos
);
7299 return (wrap_qinfifonext
7300 + NUM_ELEMENTS(ahd
->qinfifo
) - wrap_qinpos
);
7304 ahd_reset_cmds_pending(struct ahd_softc
*ahd
)
7307 ahd_mode_state saved_modes
;
7310 saved_modes
= ahd_save_modes(ahd
);
7311 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7314 * Don't count any commands as outstanding that the
7315 * sequencer has already marked for completion.
7317 ahd_flush_qoutfifo(ahd
);
7320 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
7323 ahd_outw(ahd
, CMDS_PENDING
, pending_cmds
- ahd_qinfifo_count(ahd
));
7324 ahd_restore_modes(ahd
, saved_modes
);
7325 ahd
->flags
&= ~AHD_UPDATE_PEND_CMDS
;
7329 ahd_done_with_status(struct ahd_softc
*ahd
, struct scb
*scb
, uint32_t status
)
7334 ostat
= aic_get_transaction_status(scb
);
7335 if (ostat
== CAM_REQ_INPROG
)
7336 aic_set_transaction_status(scb
, status
);
7337 cstat
= aic_get_transaction_status(scb
);
7338 if (cstat
!= CAM_REQ_CMP
)
7339 aic_freeze_scb(scb
);
7344 ahd_search_qinfifo(struct ahd_softc
*ahd
, int target
, char channel
,
7345 int lun
, u_int tag
, role_t role
, uint32_t status
,
7346 ahd_search_action action
)
7349 struct scb
*mk_msg_scb
;
7350 struct scb
*prev_scb
;
7351 ahd_mode_state saved_modes
;
7364 /* Must be in CCHAN mode */
7365 saved_modes
= ahd_save_modes(ahd
);
7366 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7369 * Halt any pending SCB DMA. The sequencer will reinitiate
7370 * this dma if the qinfifo is not empty once we unpause.
7372 if ((ahd_inb(ahd
, CCSCBCTL
) & (CCARREN
|CCSCBEN
|CCSCBDIR
))
7373 == (CCARREN
|CCSCBEN
|CCSCBDIR
)) {
7374 ahd_outb(ahd
, CCSCBCTL
,
7375 ahd_inb(ahd
, CCSCBCTL
) & ~(CCARREN
|CCSCBEN
));
7376 while ((ahd_inb(ahd
, CCSCBCTL
) & (CCARREN
|CCSCBEN
)) != 0)
7379 /* Determine sequencer's position in the qinfifo. */
7380 qintail
= AHD_QIN_WRAP(ahd
->qinfifonext
);
7381 qinstart
= ahd_get_snscb_qoff(ahd
);
7382 qinpos
= AHD_QIN_WRAP(qinstart
);
7386 if (action
== SEARCH_PRINT
) {
7387 kprintf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7388 qinstart
, ahd
->qinfifonext
);
7392 * Start with an empty queue. Entries that are not chosen
7393 * for removal will be re-added to the queue as we go.
7395 ahd
->qinfifonext
= qinstart
;
7396 busaddr
= aic_le32toh(ahd
->next_queued_hscb
->hscb_busaddr
);
7397 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
7399 while (qinpos
!= qintail
) {
7400 scb
= ahd_lookup_scb(ahd
, ahd
->qinfifo
[qinpos
]);
7402 kprintf("qinpos = %d, SCB index = %d\n",
7403 qinpos
, ahd
->qinfifo
[qinpos
]);
7407 if (ahd_match_scb(ahd
, scb
, target
, channel
, lun
, tag
, role
)) {
7409 * We found an scb that needs to be acted on.
7413 case SEARCH_COMPLETE
:
7414 if ((scb
->flags
& SCB_ACTIVE
) == 0)
7415 kprintf("Inactive SCB in qinfifo\n");
7416 ahd_done_with_status(ahd
, scb
, status
);
7421 kprintf(" 0x%x", ahd
->qinfifo
[qinpos
]);
7424 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7429 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7432 qinpos
= AHD_QIN_WRAP(qinpos
+1);
7435 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
7437 if (action
== SEARCH_PRINT
)
7438 kprintf("\nWAITING_TID_QUEUES:\n");
7441 * Search waiting for selection lists. We traverse the
7442 * list of "their ids" waiting for selection and, if
7443 * appropriate, traverse the SCBs of each "their id"
7444 * looking for matches.
7446 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7447 seq_flags2
= ahd_inb(ahd
, SEQ_FLAGS2
);
7448 if ((seq_flags2
& PENDING_MK_MESSAGE
) != 0) {
7449 scbid
= ahd_inw(ahd
, MK_MESSAGE_SCB
);
7450 mk_msg_scb
= ahd_lookup_scb(ahd
, scbid
);
7453 savedscbptr
= ahd_get_scbptr(ahd
);
7454 tid_next
= ahd_inw(ahd
, WAITING_TID_HEAD
);
7455 tid_prev
= SCB_LIST_NULL
;
7457 for (scbid
= tid_next
; !SCBID_IS_NULL(scbid
); scbid
= tid_next
) {
7462 if (targets
> AHD_NUM_TARGETS
)
7463 panic("TID LIST LOOP");
7465 if (scbid
>= ahd
->scb_data
.numscbs
) {
7466 kprintf("%s: Waiting TID List inconsistency. "
7467 "SCB index == 0x%x, yet numscbs == 0x%x.",
7468 ahd_name(ahd
), scbid
, ahd
->scb_data
.numscbs
);
7469 ahd_dump_card_state(ahd
);
7470 panic("for safety");
7472 scb
= ahd_lookup_scb(ahd
, scbid
);
7474 kprintf("%s: SCB = 0x%x Not Active!\n",
7475 ahd_name(ahd
), scbid
);
7476 panic("Waiting TID List traversal\n");
7478 ahd_set_scbptr(ahd
, scbid
);
7479 tid_next
= ahd_inw_scbram(ahd
, SCB_NEXT2
);
7480 if (ahd_match_scb(ahd
, scb
, target
, channel
, CAM_LUN_WILDCARD
,
7481 SCB_LIST_NULL
, ROLE_UNKNOWN
) == 0) {
7487 * We found a list of scbs that needs to be searched.
7489 if (action
== SEARCH_PRINT
)
7490 kprintf(" %d ( ", SCB_GET_TARGET(ahd
, scb
));
7492 found
+= ahd_search_scb_list(ahd
, target
, channel
,
7493 lun
, tag
, role
, status
,
7494 action
, &tid_head
, &tid_tail
,
7495 SCB_GET_TARGET(ahd
, scb
));
7497 * Check any MK_MESSAGE SCB that is still waiting to
7498 * enter this target's waiting for selection queue.
7500 if (mk_msg_scb
!= NULL
7501 && ahd_match_scb(ahd
, mk_msg_scb
, target
, channel
,
7505 * We found an scb that needs to be acted on.
7509 case SEARCH_COMPLETE
:
7510 if ((mk_msg_scb
->flags
& SCB_ACTIVE
) == 0)
7511 kprintf("Inactive SCB pending MK_MSG\n");
7512 ahd_done_with_status(ahd
, mk_msg_scb
, status
);
7518 kprintf("Removing MK_MSG scb\n");
7521 * Reset our tail to the tail of the
7522 * main per-target list.
7524 tail_offset
= WAITING_SCB_TAILS
7525 + (2 * SCB_GET_TARGET(ahd
, mk_msg_scb
));
7526 ahd_outw(ahd
, tail_offset
, tid_tail
);
7528 seq_flags2
&= ~PENDING_MK_MESSAGE
;
7529 ahd_outb(ahd
, SEQ_FLAGS2
, seq_flags2
);
7530 ahd_outw(ahd
, CMDS_PENDING
,
7531 ahd_inw(ahd
, CMDS_PENDING
)-1);
7536 kprintf(" 0x%x", SCB_GET_TAG(scb
));
7543 if (mk_msg_scb
!= NULL
7544 && SCBID_IS_NULL(tid_head
)
7545 && ahd_match_scb(ahd
, scb
, target
, channel
, CAM_LUN_WILDCARD
,
7546 SCB_LIST_NULL
, ROLE_UNKNOWN
)) {
7549 * When removing the last SCB for a target
7550 * queue with a pending MK_MESSAGE scb, we
7551 * must queue the MK_MESSAGE scb.
7553 kprintf("Queueing mk_msg_scb\n");
7554 tid_head
= ahd_inw(ahd
, MK_MESSAGE_SCB
);
7555 seq_flags2
&= ~PENDING_MK_MESSAGE
;
7556 ahd_outb(ahd
, SEQ_FLAGS2
, seq_flags2
);
7559 if (tid_head
!= scbid
)
7560 ahd_stitch_tid_list(ahd
, tid_prev
, tid_head
, tid_next
);
7561 if (!SCBID_IS_NULL(tid_head
))
7562 tid_prev
= tid_head
;
7563 if (action
== SEARCH_PRINT
)
7567 /* Restore saved state. */
7568 ahd_set_scbptr(ahd
, savedscbptr
);
7569 ahd_restore_modes(ahd
, saved_modes
);
7574 ahd_search_scb_list(struct ahd_softc
*ahd
, int target
, char channel
,
7575 int lun
, u_int tag
, role_t role
, uint32_t status
,
7576 ahd_search_action action
, u_int
*list_head
,
7577 u_int
*list_tail
, u_int tid
)
7585 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7587 prev
= SCB_LIST_NULL
;
7589 *list_tail
= SCB_LIST_NULL
;
7590 for (scbid
= next
; !SCBID_IS_NULL(scbid
); scbid
= next
) {
7591 if (scbid
>= ahd
->scb_data
.numscbs
) {
7592 kprintf("%s:SCB List inconsistency. "
7593 "SCB == 0x%x, yet numscbs == 0x%x.",
7594 ahd_name(ahd
), scbid
, ahd
->scb_data
.numscbs
);
7595 ahd_dump_card_state(ahd
);
7596 panic("for safety");
7598 scb
= ahd_lookup_scb(ahd
, scbid
);
7600 kprintf("%s: SCB = %d Not Active!\n",
7601 ahd_name(ahd
), scbid
);
7602 panic("Waiting List traversal\n");
7604 ahd_set_scbptr(ahd
, scbid
);
7606 next
= ahd_inw_scbram(ahd
, SCB_NEXT
);
7607 if (ahd_match_scb(ahd
, scb
, target
, channel
,
7608 lun
, SCB_LIST_NULL
, role
) == 0) {
7614 case SEARCH_COMPLETE
:
7615 if ((scb
->flags
& SCB_ACTIVE
) == 0)
7616 kprintf("Inactive SCB in Waiting List\n");
7617 ahd_done_with_status(ahd
, scb
, status
);
7620 ahd_rem_wscb(ahd
, scbid
, prev
, next
, tid
);
7622 if (SCBID_IS_NULL(prev
))
7626 kprintf("0x%x ", scbid
);
7631 if (found
> AHD_SCB_MAX
)
7632 panic("SCB LIST LOOP");
7634 if (action
== SEARCH_COMPLETE
7635 || action
== SEARCH_REMOVE
)
7636 ahd_outw(ahd
, CMDS_PENDING
, ahd_inw(ahd
, CMDS_PENDING
) - found
);
7641 ahd_stitch_tid_list(struct ahd_softc
*ahd
, u_int tid_prev
,
7642 u_int tid_cur
, u_int tid_next
)
7644 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7646 if (SCBID_IS_NULL(tid_cur
)) {
7648 /* Bypass current TID list */
7649 if (SCBID_IS_NULL(tid_prev
)) {
7650 ahd_outw(ahd
, WAITING_TID_HEAD
, tid_next
);
7652 ahd_set_scbptr(ahd
, tid_prev
);
7653 ahd_outw(ahd
, SCB_NEXT2
, tid_next
);
7655 if (SCBID_IS_NULL(tid_next
))
7656 ahd_outw(ahd
, WAITING_TID_TAIL
, tid_prev
);
7659 /* Stitch through tid_cur */
7660 if (SCBID_IS_NULL(tid_prev
)) {
7661 ahd_outw(ahd
, WAITING_TID_HEAD
, tid_cur
);
7663 ahd_set_scbptr(ahd
, tid_prev
);
7664 ahd_outw(ahd
, SCB_NEXT2
, tid_cur
);
7666 ahd_set_scbptr(ahd
, tid_cur
);
7667 ahd_outw(ahd
, SCB_NEXT2
, tid_next
);
7669 if (SCBID_IS_NULL(tid_next
))
7670 ahd_outw(ahd
, WAITING_TID_TAIL
, tid_cur
);
7675 * Manipulate the waiting for selection list and return the
7676 * scb that follows the one that we remove.
7679 ahd_rem_wscb(struct ahd_softc
*ahd
, u_int scbid
,
7680 u_int prev
, u_int next
, u_int tid
)
7684 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7685 if (!SCBID_IS_NULL(prev
)) {
7686 ahd_set_scbptr(ahd
, prev
);
7687 ahd_outw(ahd
, SCB_NEXT
, next
);
7691 * SCBs that have MK_MESSAGE set in them may
7692 * cause the tail pointer to be updated without
7693 * setting the next pointer of the previous tail.
7694 * Only clear the tail if the removed SCB was
7697 tail_offset
= WAITING_SCB_TAILS
+ (2 * tid
);
7698 if (SCBID_IS_NULL(next
)
7699 && ahd_inw(ahd
, tail_offset
) == scbid
)
7700 ahd_outw(ahd
, tail_offset
, prev
);
7702 ahd_add_scb_to_free_list(ahd
, scbid
);
7707 * Add the SCB as selected by SCBPTR onto the on chip list of
7708 * free hardware SCBs. This list is empty/unused if we are not
7709 * performing SCB paging.
7712 ahd_add_scb_to_free_list(struct ahd_softc
*ahd
, u_int scbid
)
7714 /* XXX Need some other mechanism to designate "free". */
7716 * Invalidate the tag so that our abort
7717 * routines don't think it's active.
7718 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7722 /******************************** Error Handling ******************************/
7724 * Abort all SCBs that match the given description (target/channel/lun/tag),
7725 * setting their status to the passed in status if the status has not already
7726 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7727 * is paused before it is called.
7730 ahd_abort_scbs(struct ahd_softc
*ahd
, int target
, char channel
,
7731 int lun
, u_int tag
, role_t role
, uint32_t status
)
7734 struct scb
*scbp_next
;
7740 ahd_mode_state saved_modes
;
7742 /* restore this when we're done */
7743 saved_modes
= ahd_save_modes(ahd
);
7744 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7746 found
= ahd_search_qinfifo(ahd
, target
, channel
, lun
, SCB_LIST_NULL
,
7747 role
, CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
7750 * Clean out the busy target table for any untagged commands.
7754 if (target
!= CAM_TARGET_WILDCARD
) {
7761 if (lun
== CAM_LUN_WILDCARD
) {
7763 maxlun
= AHD_NUM_LUNS_NONPKT
;
7764 } else if (lun
>= AHD_NUM_LUNS_NONPKT
) {
7765 minlun
= maxlun
= 0;
7771 if (role
!= ROLE_TARGET
) {
7772 for (;i
< maxtarget
; i
++) {
7773 for (j
= minlun
;j
< maxlun
; j
++) {
7777 tcl
= BUILD_TCL_RAW(i
, 'A', j
);
7778 scbid
= ahd_find_busy_tcl(ahd
, tcl
);
7779 scbp
= ahd_lookup_scb(ahd
, scbid
);
7781 || ahd_match_scb(ahd
, scbp
, target
, channel
,
7782 lun
, tag
, role
) == 0)
7784 ahd_unbusy_tcl(ahd
, BUILD_TCL_RAW(i
, 'A', j
));
7790 * Don't abort commands that have already completed,
7791 * but haven't quite made it up to the host yet.
7793 ahd_flush_qoutfifo(ahd
);
7796 * Go through the pending CCB list and look for
7797 * commands for this target that are still active.
7798 * These are other tagged commands that were
7799 * disconnected when the reset occurred.
7801 scbp_next
= LIST_FIRST(&ahd
->pending_scbs
);
7802 while (scbp_next
!= NULL
) {
7804 scbp_next
= LIST_NEXT(scbp
, pending_links
);
7805 if (ahd_match_scb(ahd
, scbp
, target
, channel
, lun
, tag
, role
)) {
7808 ostat
= aic_get_transaction_status(scbp
);
7809 if (ostat
== CAM_REQ_INPROG
)
7810 aic_set_transaction_status(scbp
, status
);
7811 if (aic_get_transaction_status(scbp
) != CAM_REQ_CMP
)
7812 aic_freeze_scb(scbp
);
7813 if ((scbp
->flags
& SCB_ACTIVE
) == 0)
7814 kprintf("Inactive SCB on pending list\n");
7815 ahd_done(ahd
, scbp
);
7819 ahd_restore_modes(ahd
, saved_modes
);
7820 ahd_platform_abort_scbs(ahd
, target
, channel
, lun
, tag
, role
, status
);
7821 ahd
->flags
|= AHD_UPDATE_PEND_CMDS
;
7826 ahd_reset_current_bus(struct ahd_softc
*ahd
)
7830 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7831 ahd_outb(ahd
, SIMODE1
, ahd_inb(ahd
, SIMODE1
) & ~ENSCSIRST
);
7832 scsiseq
= ahd_inb(ahd
, SCSISEQ0
) & ~(ENSELO
|ENARBO
|SCSIRSTO
);
7833 ahd_outb(ahd
, SCSISEQ0
, scsiseq
| SCSIRSTO
);
7834 ahd_flush_device_writes(ahd
);
7835 aic_delay(AHD_BUSRESET_DELAY
);
7836 /* Turn off the bus reset */
7837 ahd_outb(ahd
, SCSISEQ0
, scsiseq
);
7838 ahd_flush_device_writes(ahd
);
7839 aic_delay(AHD_BUSRESET_DELAY
);
7840 if ((ahd
->bugs
& AHD_SCSIRST_BUG
) != 0) {
7843 * Certain chip state is not cleared for
7844 * SCSI bus resets that we initiate, so
7845 * we must reset the chip.
7847 ahd_reset(ahd
, /*reinit*/TRUE
);
7848 ahd_intr_enable(ahd
, /*enable*/TRUE
);
7849 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7852 ahd_clear_intstat(ahd
);
7856 ahd_reset_channel(struct ahd_softc
*ahd
, char channel
, int initiate_reset
)
7858 struct ahd_devinfo devinfo
;
7866 ahd
->pending_device
= NULL
;
7868 ahd_compile_devinfo(&devinfo
,
7869 CAM_TARGET_WILDCARD
,
7870 CAM_TARGET_WILDCARD
,
7872 channel
, ROLE_UNKNOWN
);
7875 /* Make sure the sequencer is in a safe location. */
7876 ahd_clear_critical_section(ahd
);
7878 #ifdef AHD_TARGET_MODE
7879 if ((ahd
->flags
& AHD_TARGETROLE
) != 0) {
7880 ahd_run_tqinfifo(ahd
, /*paused*/TRUE
);
7883 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7886 * Disable selections so no automatic hardware
7887 * functions will modify chip state.
7889 ahd_outb(ahd
, SCSISEQ0
, 0);
7890 ahd_outb(ahd
, SCSISEQ1
, 0);
7893 * Safely shut down our DMA engines. Always start with
7894 * the FIFO that is not currently active (if any are
7895 * actively connected).
7897 next_fifo
= fifo
= ahd_inb(ahd
, DFFSTAT
) & CURRFIFO
;
7898 if (next_fifo
> CURRFIFO_1
)
7899 /* If disconneced, arbitrarily start with FIFO1. */
7900 next_fifo
= fifo
= 0;
7902 next_fifo
^= CURRFIFO_1
;
7903 ahd_set_modes(ahd
, next_fifo
, next_fifo
);
7904 ahd_outb(ahd
, DFCNTRL
,
7905 ahd_inb(ahd
, DFCNTRL
) & ~(SCSIEN
|HDMAEN
));
7906 while ((ahd_inb(ahd
, DFCNTRL
) & HDMAENACK
) != 0)
7909 * Set CURRFIFO to the now inactive channel.
7911 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7912 ahd_outb(ahd
, DFFSTAT
, next_fifo
);
7913 } while (next_fifo
!= fifo
);
7916 * Reset the bus if we are initiating this reset
7918 ahd_clear_msg_state(ahd
);
7919 ahd_outb(ahd
, SIMODE1
,
7920 ahd_inb(ahd
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
));
7923 ahd_reset_current_bus(ahd
);
7925 ahd_clear_intstat(ahd
);
7928 * Clean up all the state information for the
7929 * pending transactions on this bus.
7931 found
= ahd_abort_scbs(ahd
, CAM_TARGET_WILDCARD
, channel
,
7932 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
7933 ROLE_UNKNOWN
, CAM_SCSI_BUS_RESET
);
7936 * Cleanup anything left in the FIFOs.
7938 ahd_clear_fifo(ahd
, 0);
7939 ahd_clear_fifo(ahd
, 1);
7942 * Revert to async/narrow transfers until we renegotiate.
7944 max_scsiid
= (ahd
->features
& AHD_WIDE
) ? 15 : 7;
7945 for (target
= 0; target
<= max_scsiid
; target
++) {
7947 if (ahd
->enabled_targets
[target
] == NULL
)
7949 for (initiator
= 0; initiator
<= max_scsiid
; initiator
++) {
7950 struct ahd_devinfo devinfo
;
7952 ahd_compile_devinfo(&devinfo
, target
, initiator
,
7955 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
7956 AHD_TRANS_CUR
, /*paused*/TRUE
);
7957 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0,
7958 /*offset*/0, /*ppr_options*/0,
7959 AHD_TRANS_CUR
, /*paused*/TRUE
);
7963 #ifdef AHD_TARGET_MODE
7964 max_scsiid
= (ahd
->features
& AHD_WIDE
) ? 15 : 7;
7967 * Send an immediate notify ccb to all target more peripheral
7968 * drivers affected by this action.
7970 for (target
= 0; target
<= max_scsiid
; target
++) {
7971 struct ahd_tmode_tstate
* tstate
;
7974 tstate
= ahd
->enabled_targets
[target
];
7977 for (lun
= 0; lun
< AHD_NUM_LUNS
; lun
++) {
7978 struct ahd_tmode_lstate
* lstate
;
7980 lstate
= tstate
->enabled_luns
[lun
];
7984 ahd_queue_lstate_event(ahd
, lstate
, CAM_TARGET_WILDCARD
,
7985 EVENT_TYPE_BUS_RESET
, /*arg*/0);
7986 ahd_send_lstate_events(ahd
, lstate
);
7990 /* Notify the XPT that a bus reset occurred */
7991 ahd_send_async(ahd
, devinfo
.channel
, CAM_TARGET_WILDCARD
,
7992 CAM_LUN_WILDCARD
, AC_BUS_RESET
, NULL
);
7995 * Freeze the SIMQ until our poller can determine that
7996 * the bus reset has really gone away. We set the initial
7997 * timer to 0 to have the check performed as soon as possible
7998 * from the timer context.
8000 if ((ahd
->flags
& AHD_RESET_POLL_ACTIVE
) == 0) {
8001 ahd
->flags
|= AHD_RESET_POLL_ACTIVE
;
8002 aic_freeze_simq(ahd
);
8003 aic_timer_reset(&ahd
->reset_timer
, 0, ahd_reset_poll
, ahd
);
8009 #define AHD_RESET_POLL_MS 1
8011 ahd_reset_poll(void *arg
)
8013 struct ahd_softc
*ahd
= (struct ahd_softc
*)arg
;
8018 ahd_update_modes(ahd
);
8019 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
8020 ahd_outb(ahd
, CLRSINT1
, CLRSCSIRSTI
);
8021 if ((ahd_inb(ahd
, SSTAT1
) & SCSIRSTI
) != 0) {
8022 aic_timer_reset(&ahd
->reset_timer
, AHD_RESET_POLL_MS
,
8023 ahd_reset_poll
, ahd
);
8029 /* Reset is now low. Complete chip reinitialization. */
8030 ahd_outb(ahd
, SIMODE1
, ahd_inb(ahd
, SIMODE1
) | ENSCSIRST
);
8031 scsiseq1
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
8032 ahd_outb(ahd
, SCSISEQ1
, scsiseq1
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
8034 ahd
->flags
&= ~AHD_RESET_POLL_ACTIVE
;
8035 aic_release_simq(ahd
);
8039 /**************************** Statistics Processing ***************************/
8041 ahd_stat_timer(void *arg
)
8043 struct ahd_softc
*ahd
= (struct ahd_softc
*)arg
;
8047 enint_coal
= ahd
->hs_mailbox
& ENINT_COALESCE
;
8048 if (ahd
->cmdcmplt_total
> ahd
->int_coalescing_threshold
)
8049 enint_coal
|= ENINT_COALESCE
;
8050 else if (ahd
->cmdcmplt_total
< ahd
->int_coalescing_stop_threshold
)
8051 enint_coal
&= ~ENINT_COALESCE
;
8053 if (enint_coal
!= (ahd
->hs_mailbox
& ENINT_COALESCE
)) {
8054 ahd_enable_coalescing(ahd
, enint_coal
);
8056 if ((ahd_debug
& AHD_SHOW_INT_COALESCING
) != 0)
8057 kprintf("%s: Interrupt coalescing "
8058 "now %sabled. Cmds %d\n",
8060 (enint_coal
& ENINT_COALESCE
) ? "en" : "dis",
8061 ahd
->cmdcmplt_total
);
8065 ahd
->cmdcmplt_bucket
= (ahd
->cmdcmplt_bucket
+1) & (AHD_STAT_BUCKETS
-1);
8066 ahd
->cmdcmplt_total
-= ahd
->cmdcmplt_counts
[ahd
->cmdcmplt_bucket
];
8067 ahd
->cmdcmplt_counts
[ahd
->cmdcmplt_bucket
] = 0;
8068 aic_timer_reset(&ahd
->stat_timer
, AHD_STAT_UPDATE_MS
,
8069 ahd_stat_timer
, ahd
);
8073 /****************************** Status Processing *****************************/
8075 ahd_handle_scb_status(struct ahd_softc
*ahd
, struct scb
*scb
)
8077 if (scb
->hscb
->shared_data
.istatus
.scsi_status
!= 0) {
8078 ahd_handle_scsi_status(ahd
, scb
);
8080 ahd_calc_residual(ahd
, scb
);
8086 ahd_handle_scsi_status(struct ahd_softc
*ahd
, struct scb
*scb
)
8088 struct hardware_scb
*hscb
;
8092 * The sequencer freezes its select-out queue
8093 * anytime a SCSI status error occurs. We must
8094 * handle the error and increment our qfreeze count
8095 * to allow the sequencer to continue. We don't
8096 * bother clearing critical sections here since all
8097 * operations are on data structures that the sequencer
8098 * is not touching once the queue is frozen.
8102 if (ahd_is_paused(ahd
)) {
8109 /* Freeze the queue until the client sees the error. */
8110 ahd_freeze_devq(ahd
, scb
);
8111 aic_freeze_scb(scb
);
8113 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
8118 /* Don't want to clobber the original sense code */
8119 if ((scb
->flags
& SCB_SENSE
) != 0) {
8121 * Clear the SCB_SENSE Flag and perform
8122 * a normal command completion.
8124 scb
->flags
&= ~SCB_SENSE
;
8125 aic_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
8129 aic_set_transaction_status(scb
, CAM_SCSI_STATUS_ERROR
);
8130 aic_set_scsi_status(scb
, hscb
->shared_data
.istatus
.scsi_status
);
8131 switch (hscb
->shared_data
.istatus
.scsi_status
) {
8132 case STATUS_PKT_SENSE
:
8134 struct scsi_status_iu_header
*siu
;
8136 ahd_sync_sense(ahd
, scb
, BUS_DMASYNC_POSTREAD
);
8137 siu
= (struct scsi_status_iu_header
*)scb
->sense_data
;
8138 aic_set_scsi_status(scb
, siu
->status
);
8140 if ((ahd_debug
& AHD_SHOW_SENSE
) != 0) {
8141 ahd_print_path(ahd
, scb
);
8142 kprintf("SCB 0x%x Received PKT Status of 0x%x\n",
8143 SCB_GET_TAG(scb
), siu
->status
);
8144 kprintf("\tflags = 0x%x, sense len = 0x%x, "
8146 siu
->flags
, scsi_4btoul(siu
->sense_length
),
8147 scsi_4btoul(siu
->pkt_failures_length
));
8150 if ((siu
->flags
& SIU_RSPVALID
) != 0) {
8151 ahd_print_path(ahd
, scb
);
8152 if (scsi_4btoul(siu
->pkt_failures_length
) < 4) {
8153 kprintf("Unable to parse pkt_failures\n");
8156 switch (SIU_PKTFAIL_CODE(siu
)) {
8158 kprintf("No packet failure found\n");
8160 case SIU_PFC_CIU_FIELDS_INVALID
:
8161 kprintf("Invalid Command IU Field\n");
8163 case SIU_PFC_TMF_NOT_SUPPORTED
:
8164 kprintf("TMF not supportd\n");
8166 case SIU_PFC_TMF_FAILED
:
8167 kprintf("TMF failed\n");
8169 case SIU_PFC_INVALID_TYPE_CODE
:
8170 kprintf("Invalid L_Q Type code\n");
8172 case SIU_PFC_ILLEGAL_REQUEST
:
8173 kprintf("Illegal request\n");
8178 if (siu
->status
== SCSI_STATUS_OK
)
8179 aic_set_transaction_status(scb
,
8182 if ((siu
->flags
& SIU_SNSVALID
) != 0) {
8183 scb
->flags
|= SCB_PKT_SENSE
;
8185 if ((ahd_debug
& AHD_SHOW_SENSE
) != 0)
8186 kprintf("Sense data available\n");
8192 case SCSI_STATUS_CMD_TERMINATED
:
8193 case SCSI_STATUS_CHECK_COND
:
8195 struct ahd_devinfo devinfo
;
8196 struct ahd_dma_seg
*sg
;
8197 struct scsi_sense
*sc
;
8198 struct ahd_initiator_tinfo
*targ_info
;
8199 struct ahd_tmode_tstate
*tstate
;
8200 struct ahd_transinfo
*tinfo
;
8202 if (ahd_debug
& AHD_SHOW_SENSE
) {
8203 ahd_print_path(ahd
, scb
);
8204 kprintf("SCB %d: requests Check Status\n",
8209 if (aic_perform_autosense(scb
) == 0)
8212 ahd_compile_devinfo(&devinfo
, SCB_GET_OUR_ID(scb
),
8213 SCB_GET_TARGET(ahd
, scb
),
8215 SCB_GET_CHANNEL(ahd
, scb
),
8217 targ_info
= ahd_fetch_transinfo(ahd
,
8222 tinfo
= &targ_info
->curr
;
8224 sc
= (struct scsi_sense
*)hscb
->shared_data
.idata
.cdb
;
8226 * Save off the residual if there is one.
8228 ahd_update_residual(ahd
, scb
);
8230 if (ahd_debug
& AHD_SHOW_SENSE
) {
8231 ahd_print_path(ahd
, scb
);
8232 kprintf("Sending Sense\n");
8236 sg
= ahd_sg_setup(ahd
, scb
, sg
, ahd_get_sense_bufaddr(ahd
, scb
),
8237 aic_get_sense_bufsize(ahd
, scb
),
8239 sc
->opcode
= REQUEST_SENSE
;
8241 if (tinfo
->protocol_version
<= SCSI_REV_2
8242 && SCB_GET_LUN(scb
) < 8)
8243 sc
->byte2
= SCB_GET_LUN(scb
) << 5;
8246 sc
->length
= aic_get_sense_bufsize(ahd
, scb
);
8250 * We can't allow the target to disconnect.
8251 * This will be an untagged transaction and
8252 * having the target disconnect will make this
8253 * transaction indestinguishable from outstanding
8254 * tagged transactions.
8259 * This request sense could be because the
8260 * the device lost power or in some other
8261 * way has lost our transfer negotiations.
8262 * Renegotiate if appropriate. Unit attention
8263 * errors will be reported before any data
8266 if (aic_get_residual(scb
) == aic_get_transfer_length(scb
)) {
8267 ahd_update_neg_request(ahd
, &devinfo
,
8269 AHD_NEG_IF_NON_ASYNC
);
8271 if (tstate
->auto_negotiate
& devinfo
.target_mask
) {
8272 hscb
->control
|= MK_MESSAGE
;
8274 ~(SCB_NEGOTIATE
|SCB_ABORT
|SCB_DEVICE_RESET
);
8275 scb
->flags
|= SCB_AUTO_NEGOTIATE
;
8277 hscb
->cdb_len
= sizeof(*sc
);
8278 ahd_setup_data_scb(ahd
, scb
);
8279 scb
->flags
|= SCB_SENSE
;
8280 ahd_queue_scb(ahd
, scb
);
8282 * Ensure we have enough time to actually
8283 * retrieve the sense, but only schedule
8284 * the timer if we are not in recovery or
8285 * this is a recovery SCB that is allowed
8286 * to have an active timer.
8288 if (ahd
->scb_data
.recovery_scbs
== 0
8289 || (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
8290 aic_scb_timer_reset(scb
, 5 * 1000);
8293 case SCSI_STATUS_OK
:
8294 kprintf("%s: Interrupted for staus of 0???\n",
8304 * Calculate the residual for a just completed SCB.
8307 ahd_calc_residual(struct ahd_softc
*ahd
, struct scb
*scb
)
8309 struct hardware_scb
*hscb
;
8310 struct initiator_status
*spkt
;
8312 uint32_t resid_sgptr
;
8318 * SG_STATUS_VALID clear in sgptr.
8319 * 2) Transferless command
8320 * 3) Never performed any transfers.
8321 * sgptr has SG_FULL_RESID set.
8322 * 4) No residual but target did not
8323 * save data pointers after the
8324 * last transfer, so sgptr was
8326 * 5) We have a partial residual.
8327 * Use residual_sgptr to determine
8332 sgptr
= aic_le32toh(hscb
->sgptr
);
8333 if ((sgptr
& SG_STATUS_VALID
) == 0)
8336 sgptr
&= ~SG_STATUS_VALID
;
8338 if ((sgptr
& SG_LIST_NULL
) != 0)
8343 * Residual fields are the same in both
8344 * target and initiator status packets,
8345 * so we can always use the initiator fields
8346 * regardless of the role for this SCB.
8348 spkt
= &hscb
->shared_data
.istatus
;
8349 resid_sgptr
= aic_le32toh(spkt
->residual_sgptr
);
8350 if ((sgptr
& SG_FULL_RESID
) != 0) {
8352 resid
= aic_get_transfer_length(scb
);
8353 } else if ((resid_sgptr
& SG_LIST_NULL
) != 0) {
8356 } else if ((resid_sgptr
& SG_OVERRUN_RESID
) != 0) {
8357 ahd_print_path(ahd
, scb
);
8358 kprintf("data overrun detected Tag == 0x%x.\n",
8360 ahd_freeze_devq(ahd
, scb
);
8361 aic_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
8362 aic_freeze_scb(scb
);
8364 } else if ((resid_sgptr
& ~SG_PTR_MASK
) != 0) {
8365 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr
);
8368 struct ahd_dma_seg
*sg
;
8371 * Remainder of the SG where the transfer
8374 resid
= aic_le32toh(spkt
->residual_datacnt
) & AHD_SG_LEN_MASK
;
8375 sg
= ahd_sg_bus_to_virt(ahd
, scb
, resid_sgptr
& SG_PTR_MASK
);
8377 /* The residual sg_ptr always points to the next sg */
8381 * Add up the contents of all residual
8382 * SG segments that are after the SG where
8383 * the transfer stopped.
8385 while ((aic_le32toh(sg
->len
) & AHD_DMA_LAST_SEG
) == 0) {
8387 resid
+= aic_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
8390 if ((scb
->flags
& SCB_SENSE
) == 0)
8391 aic_set_residual(scb
, resid
);
8393 aic_set_sense_residual(scb
, resid
);
8396 if ((ahd_debug
& AHD_SHOW_MISC
) != 0) {
8397 ahd_print_path(ahd
, scb
);
8398 kprintf("Handled %sResidual of %d bytes\n",
8399 (scb
->flags
& SCB_SENSE
) ? "Sense " : "", resid
);
8404 /******************************* Target Mode **********************************/
8405 #ifdef AHD_TARGET_MODE
8407 * Add a target mode event to this lun's queue
8410 ahd_queue_lstate_event(struct ahd_softc
*ahd
, struct ahd_tmode_lstate
*lstate
,
8411 u_int initiator_id
, u_int event_type
, u_int event_arg
)
8413 struct ahd_tmode_event
*event
;
8416 xpt_freeze_devq(lstate
->path
, /*count*/1);
8417 if (lstate
->event_w_idx
>= lstate
->event_r_idx
)
8418 pending
= lstate
->event_w_idx
- lstate
->event_r_idx
;
8420 pending
= AHD_TMODE_EVENT_BUFFER_SIZE
+ 1
8421 - (lstate
->event_r_idx
- lstate
->event_w_idx
);
8423 if (event_type
== EVENT_TYPE_BUS_RESET
8424 || event_type
== MSG_BUS_DEV_RESET
) {
8426 * Any earlier events are irrelevant, so reset our buffer.
8427 * This has the effect of allowing us to deal with reset
8428 * floods (an external device holding down the reset line)
8429 * without losing the event that is really interesting.
8431 lstate
->event_r_idx
= 0;
8432 lstate
->event_w_idx
= 0;
8433 xpt_release_devq(lstate
->path
, pending
, /*runqueue*/FALSE
);
8436 if (pending
== AHD_TMODE_EVENT_BUFFER_SIZE
) {
8437 xpt_print_path(lstate
->path
);
8438 kprintf("immediate event %x:%x lost\n",
8439 lstate
->event_buffer
[lstate
->event_r_idx
].event_type
,
8440 lstate
->event_buffer
[lstate
->event_r_idx
].event_arg
);
8441 lstate
->event_r_idx
++;
8442 if (lstate
->event_r_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8443 lstate
->event_r_idx
= 0;
8444 xpt_release_devq(lstate
->path
, /*count*/1, /*runqueue*/FALSE
);
8447 event
= &lstate
->event_buffer
[lstate
->event_w_idx
];
8448 event
->initiator_id
= initiator_id
;
8449 event
->event_type
= event_type
;
8450 event
->event_arg
= event_arg
;
8451 lstate
->event_w_idx
++;
8452 if (lstate
->event_w_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8453 lstate
->event_w_idx
= 0;
8457 * Send any target mode events queued up waiting
8458 * for immediate notify resources.
8461 ahd_send_lstate_events(struct ahd_softc
*ahd
, struct ahd_tmode_lstate
*lstate
)
8463 struct ccb_hdr
*ccbh
;
8464 struct ccb_immed_notify
*inot
;
8466 while (lstate
->event_r_idx
!= lstate
->event_w_idx
8467 && (ccbh
= SLIST_FIRST(&lstate
->immed_notifies
)) != NULL
) {
8468 struct ahd_tmode_event
*event
;
8470 event
= &lstate
->event_buffer
[lstate
->event_r_idx
];
8471 SLIST_REMOVE_HEAD(&lstate
->immed_notifies
, sim_links
.sle
);
8472 inot
= (struct ccb_immed_notify
*)ccbh
;
8473 switch (event
->event_type
) {
8474 case EVENT_TYPE_BUS_RESET
:
8475 ccbh
->status
= CAM_SCSI_BUS_RESET
|CAM_DEV_QFRZN
;
8478 ccbh
->status
= CAM_MESSAGE_RECV
|CAM_DEV_QFRZN
;
8479 inot
->message_args
[0] = event
->event_type
;
8480 inot
->message_args
[1] = event
->event_arg
;
8483 inot
->initiator_id
= event
->initiator_id
;
8484 inot
->sense_len
= 0;
8485 xpt_done((union ccb
*)inot
);
8486 lstate
->event_r_idx
++;
8487 if (lstate
->event_r_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8488 lstate
->event_r_idx
= 0;
8493 /******************** Sequencer Program Patching/Download *********************/
8497 ahd_dumpseq(struct ahd_softc
* ahd
)
8504 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
8505 ahd_outw(ahd
, PRGMCNT
, 0);
8506 for (i
= 0; i
< max_prog
; i
++) {
8507 uint8_t ins_bytes
[4];
8509 ahd_insb(ahd
, SEQRAM
, ins_bytes
, 4);
8510 kprintf("0x%08x\n", ins_bytes
[0] << 24
8511 | ins_bytes
[1] << 16
8519 ahd_loadseq(struct ahd_softc
*ahd
)
8521 struct cs cs_table
[num_critical_sections
];
8522 u_int begin_set
[num_critical_sections
];
8523 u_int end_set
[num_critical_sections
];
8524 struct patch
*cur_patch
;
8530 u_int sg_prefetch_cnt
;
8531 u_int sg_prefetch_cnt_limit
;
8532 u_int sg_prefetch_align
;
8534 u_int cacheline_mask
;
8535 uint8_t download_consts
[DOWNLOAD_CONST_COUNT
];
8538 kprintf("%s: Downloading Sequencer Program...",
8541 #if DOWNLOAD_CONST_COUNT != 8
8542 #error "Download Const Mismatch"
8545 * Start out with 0 critical sections
8546 * that apply to this firmware load.
8550 memset(begin_set
, 0, sizeof(begin_set
));
8551 memset(end_set
, 0, sizeof(end_set
));
8554 * Setup downloadable constant table.
8556 * The computation for the S/G prefetch variables is
8557 * a bit complicated. We would like to always fetch
8558 * in terms of cachelined sized increments. However,
8559 * if the cacheline is not an even multiple of the
8560 * SG element size or is larger than our SG RAM, using
8561 * just the cache size might leave us with only a portion
8562 * of an SG element at the tail of a prefetch. If the
8563 * cacheline is larger than our S/G prefetch buffer less
8564 * the size of an SG element, we may round down to a cacheline
8565 * that doesn't contain any or all of the S/G of interest
8566 * within the bounds of our S/G ram. Provide variables to
8567 * the sequencer that will allow it to handle these edge
8570 /* Start by aligning to the nearest cacheline. */
8571 sg_prefetch_align
= ahd
->pci_cachesize
;
8572 if (sg_prefetch_align
== 0)
8573 sg_prefetch_align
= 8;
8574 /* Round down to the nearest power of 2. */
8575 while (powerof2(sg_prefetch_align
) == 0)
8576 sg_prefetch_align
--;
8578 cacheline_mask
= sg_prefetch_align
- 1;
8581 * If the cacheline boundary is greater than half our prefetch RAM
8582 * we risk not being able to fetch even a single complete S/G
8583 * segment if we align to that boundary.
8585 if (sg_prefetch_align
> CCSGADDR_MAX
/2)
8586 sg_prefetch_align
= CCSGADDR_MAX
/2;
8587 /* Start by fetching a single cacheline. */
8588 sg_prefetch_cnt
= sg_prefetch_align
;
8590 * Increment the prefetch count by cachelines until
8591 * at least one S/G element will fit.
8593 sg_size
= sizeof(struct ahd_dma_seg
);
8594 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
8595 sg_size
= sizeof(struct ahd_dma64_seg
);
8596 while (sg_prefetch_cnt
< sg_size
)
8597 sg_prefetch_cnt
+= sg_prefetch_align
;
8599 * If the cacheline is not an even multiple of
8600 * the S/G size, we may only get a partial S/G when
8601 * we align. Add a cacheline if this is the case.
8603 if ((sg_prefetch_align
% sg_size
) != 0
8604 && (sg_prefetch_cnt
< CCSGADDR_MAX
))
8605 sg_prefetch_cnt
+= sg_prefetch_align
;
8607 * Lastly, compute a value that the sequencer can use
8608 * to determine if the remainder of the CCSGRAM buffer
8609 * has a full S/G element in it.
8611 sg_prefetch_cnt_limit
= -(sg_prefetch_cnt
- sg_size
+ 1);
8612 download_consts
[SG_PREFETCH_CNT
] = sg_prefetch_cnt
;
8613 download_consts
[SG_PREFETCH_CNT_LIMIT
] = sg_prefetch_cnt_limit
;
8614 download_consts
[SG_PREFETCH_ALIGN_MASK
] = ~(sg_prefetch_align
- 1);
8615 download_consts
[SG_PREFETCH_ADDR_MASK
] = (sg_prefetch_align
- 1);
8616 download_consts
[SG_SIZEOF
] = sg_size
;
8617 download_consts
[PKT_OVERRUN_BUFOFFSET
] =
8618 (ahd
->overrun_buf
- (uint8_t *)ahd
->qoutfifo
) / 256;
8619 download_consts
[SCB_TRANSFER_SIZE
] = SCB_TRANSFER_SIZE_1BYTE_LUN
;
8620 download_consts
[CACHELINE_MASK
] = cacheline_mask
;
8621 cur_patch
= patches
;
8624 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
8625 ahd_outw(ahd
, PRGMCNT
, 0);
8627 for (i
= 0; i
< sizeof(seqprog
)/4; i
++) {
8628 if (ahd_check_patch(ahd
, &cur_patch
, i
, &skip_addr
) == 0) {
8630 * Don't download this instruction as it
8631 * is in a patch that was removed.
8636 * Move through the CS table until we find a CS
8637 * that might apply to this instruction.
8639 for (; cur_cs
< num_critical_sections
; cur_cs
++) {
8640 if (critical_sections
[cur_cs
].end
<= i
) {
8641 if (begin_set
[cs_count
] == TRUE
8642 && end_set
[cs_count
] == FALSE
) {
8643 cs_table
[cs_count
].end
= downloaded
;
8644 end_set
[cs_count
] = TRUE
;
8649 if (critical_sections
[cur_cs
].begin
<= i
8650 && begin_set
[cs_count
] == FALSE
) {
8651 cs_table
[cs_count
].begin
= downloaded
;
8652 begin_set
[cs_count
] = TRUE
;
8656 ahd_download_instr(ahd
, i
, download_consts
);
8660 ahd
->num_critical_sections
= cs_count
;
8661 if (cs_count
!= 0) {
8662 cs_count
*= sizeof(struct cs
);
8663 ahd
->critical_sections
= kmalloc(cs_count
, M_DEVBUF
, M_INTWAIT
);
8664 memcpy(ahd
->critical_sections
, cs_table
, cs_count
);
8666 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
);
8669 kprintf(" %d instructions downloaded\n", downloaded
);
8670 kprintf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8671 ahd_name(ahd
), ahd
->features
, ahd
->bugs
, ahd
->flags
);
8676 ahd_check_patch(struct ahd_softc
*ahd
, struct patch
**start_patch
,
8677 u_int start_instr
, u_int
*skip_addr
)
8679 struct patch
*cur_patch
;
8680 struct patch
*last_patch
;
8683 num_patches
= sizeof(patches
)/sizeof(struct patch
);
8684 last_patch
= &patches
[num_patches
];
8685 cur_patch
= *start_patch
;
8687 while (cur_patch
< last_patch
&& start_instr
== cur_patch
->begin
) {
8689 if (cur_patch
->patch_func(ahd
) == 0) {
8691 /* Start rejecting code */
8692 *skip_addr
= start_instr
+ cur_patch
->skip_instr
;
8693 cur_patch
+= cur_patch
->skip_patch
;
8695 /* Accepted this patch. Advance to the next
8696 * one and wait for our intruction pointer to
8703 *start_patch
= cur_patch
;
8704 if (start_instr
< *skip_addr
)
8705 /* Still skipping */
8712 ahd_resolve_seqaddr(struct ahd_softc
*ahd
, u_int address
)
8714 struct patch
*cur_patch
;
8720 cur_patch
= patches
;
8723 for (i
= 0; i
< address
;) {
8725 ahd_check_patch(ahd
, &cur_patch
, i
, &skip_addr
);
8727 if (skip_addr
> i
) {
8730 end_addr
= MIN(address
, skip_addr
);
8731 address_offset
+= end_addr
- i
;
8737 return (address
- address_offset
);
8741 ahd_download_instr(struct ahd_softc
*ahd
, u_int instrptr
, uint8_t *dconsts
)
8743 union ins_formats instr
;
8744 struct ins_format1
*fmt1_ins
;
8745 struct ins_format3
*fmt3_ins
;
8749 * The firmware is always compiled into a little endian format.
8751 instr
.integer
= aic_le32toh(*(uint32_t*)&seqprog
[instrptr
* 4]);
8753 fmt1_ins
= &instr
.format1
;
8756 /* Pull the opcode */
8757 opcode
= instr
.format1
.opcode
;
8768 fmt3_ins
= &instr
.format3
;
8769 fmt3_ins
->address
= ahd_resolve_seqaddr(ahd
, fmt3_ins
->address
);
8778 if (fmt1_ins
->parity
!= 0) {
8779 fmt1_ins
->immediate
= dconsts
[fmt1_ins
->immediate
];
8781 fmt1_ins
->parity
= 0;
8787 /* Calculate odd parity for the instruction */
8788 for (i
= 0, count
= 0; i
< 31; i
++) {
8792 if ((instr
.integer
& mask
) != 0)
8795 if ((count
& 0x01) == 0)
8796 instr
.format1
.parity
= 1;
8798 /* The sequencer is a little endian cpu */
8799 instr
.integer
= aic_htole32(instr
.integer
);
8800 ahd_outsb(ahd
, SEQRAM
, instr
.bytes
, 4);
8804 panic("Unknown opcode encountered in seq program");
8810 ahd_probe_stack_size(struct ahd_softc
*ahd
)
8819 * We avoid using 0 as a pattern to avoid
8820 * confusion if the stack implementation
8821 * "back-fills" with zeros when "poping'
8824 for (i
= 1; i
<= last_probe
+1; i
++) {
8825 ahd_outb(ahd
, STACK
, i
& 0xFF);
8826 ahd_outb(ahd
, STACK
, (i
>> 8) & 0xFF);
8830 for (i
= last_probe
+1; i
> 0; i
--) {
8833 stack_entry
= ahd_inb(ahd
, STACK
)
8834 |(ahd_inb(ahd
, STACK
) << 8);
8835 if (stack_entry
!= i
)
8841 return (last_probe
);
8845 ahd_dump_all_cards_state(void)
8847 struct ahd_softc
*list_ahd
;
8849 TAILQ_FOREACH(list_ahd
, &ahd_tailq
, links
) {
8850 ahd_dump_card_state(list_ahd
);
8855 ahd_print_register(ahd_reg_parse_entry_t
*table
, u_int num_entries
,
8856 const char *name
, u_int address
, u_int value
,
8857 u_int
*cur_column
, u_int wrap_point
)
8863 if (cur_column
== NULL
) {
8865 cur_column
= &dummy_column
;
8868 if (cur_column
!= NULL
&& *cur_column
>= wrap_point
) {
8872 printed
= kprintf("%s[0x%x]", name
, value
);
8873 if (table
== NULL
) {
8874 printed
+= kprintf(" ");
8875 *cur_column
+= printed
;
8879 while (printed_mask
!= 0xFF) {
8882 for (entry
= 0; entry
< num_entries
; entry
++) {
8883 if (((value
& table
[entry
].mask
)
8884 != table
[entry
].value
)
8885 || ((printed_mask
& table
[entry
].mask
)
8886 == table
[entry
].mask
))
8889 printed
+= kprintf("%s%s",
8890 printed_mask
== 0 ? ":(" : "|",
8892 printed_mask
|= table
[entry
].mask
;
8896 if (entry
>= num_entries
)
8899 if (printed_mask
!= 0)
8900 printed
+= kprintf(") ");
8902 printed
+= kprintf(" ");
8903 *cur_column
+= printed
;
8908 ahd_dump_card_state(struct ahd_softc
*ahd
)
8911 ahd_mode_state saved_modes
;
8915 u_int saved_scb_index
;
8919 if (ahd_is_paused(ahd
)) {
8925 saved_modes
= ahd_save_modes(ahd
);
8926 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
8927 kprintf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8928 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8930 ahd_inw(ahd
, CURADDR
),
8931 ahd_build_mode_state(ahd
, ahd
->saved_src_mode
,
8932 ahd
->saved_dst_mode
));
8934 kprintf("Card was paused\n");
8936 if (ahd_check_cmdcmpltqueues(ahd
))
8937 kprintf("Completions are pending\n");
8940 * Mode independent registers.
8943 ahd_intstat_print(ahd_inb(ahd
, INTSTAT
), &cur_col
, 50);
8944 ahd_seloid_print(ahd_inb(ahd
, SELOID
), &cur_col
, 50);
8945 ahd_selid_print(ahd_inb(ahd
, SELID
), &cur_col
, 50);
8946 ahd_hs_mailbox_print(ahd_inb(ahd
, LOCAL_HS_MAILBOX
), &cur_col
, 50);
8947 ahd_intctl_print(ahd_inb(ahd
, INTCTL
), &cur_col
, 50);
8948 ahd_seqintstat_print(ahd_inb(ahd
, SEQINTSTAT
), &cur_col
, 50);
8949 ahd_saved_mode_print(ahd_inb(ahd
, SAVED_MODE
), &cur_col
, 50);
8950 ahd_dffstat_print(ahd_inb(ahd
, DFFSTAT
), &cur_col
, 50);
8951 ahd_scsisigi_print(ahd_inb(ahd
, SCSISIGI
), &cur_col
, 50);
8952 ahd_scsiphase_print(ahd_inb(ahd
, SCSIPHASE
), &cur_col
, 50);
8953 ahd_scsibus_print(ahd_inb(ahd
, SCSIBUS
), &cur_col
, 50);
8954 ahd_lastphase_print(ahd_inb(ahd
, LASTPHASE
), &cur_col
, 50);
8955 ahd_scsiseq0_print(ahd_inb(ahd
, SCSISEQ0
), &cur_col
, 50);
8956 ahd_scsiseq1_print(ahd_inb(ahd
, SCSISEQ1
), &cur_col
, 50);
8957 ahd_seqctl0_print(ahd_inb(ahd
, SEQCTL0
), &cur_col
, 50);
8958 ahd_seqintctl_print(ahd_inb(ahd
, SEQINTCTL
), &cur_col
, 50);
8959 ahd_seq_flags_print(ahd_inb(ahd
, SEQ_FLAGS
), &cur_col
, 50);
8960 ahd_seq_flags2_print(ahd_inb(ahd
, SEQ_FLAGS2
), &cur_col
, 50);
8961 ahd_qfreeze_count_print(ahd_inw(ahd
, QFREEZE_COUNT
), &cur_col
, 50);
8962 ahd_kernel_qfreeze_count_print(ahd_inw(ahd
, KERNEL_QFREEZE_COUNT
),
8964 ahd_mk_message_scb_print(ahd_inw(ahd
, MK_MESSAGE_SCB
), &cur_col
, 50);
8965 ahd_mk_message_scsiid_print(ahd_inb(ahd
, MK_MESSAGE_SCSIID
),
8967 ahd_sstat0_print(ahd_inb(ahd
, SSTAT0
), &cur_col
, 50);
8968 ahd_sstat1_print(ahd_inb(ahd
, SSTAT1
), &cur_col
, 50);
8969 ahd_sstat2_print(ahd_inb(ahd
, SSTAT2
), &cur_col
, 50);
8970 ahd_sstat3_print(ahd_inb(ahd
, SSTAT3
), &cur_col
, 50);
8971 ahd_perrdiag_print(ahd_inb(ahd
, PERRDIAG
), &cur_col
, 50);
8972 ahd_simode1_print(ahd_inb(ahd
, SIMODE1
), &cur_col
, 50);
8973 ahd_lqistat0_print(ahd_inb(ahd
, LQISTAT0
), &cur_col
, 50);
8974 ahd_lqistat1_print(ahd_inb(ahd
, LQISTAT1
), &cur_col
, 50);
8975 ahd_lqistat2_print(ahd_inb(ahd
, LQISTAT2
), &cur_col
, 50);
8976 ahd_lqostat0_print(ahd_inb(ahd
, LQOSTAT0
), &cur_col
, 50);
8977 ahd_lqostat1_print(ahd_inb(ahd
, LQOSTAT1
), &cur_col
, 50);
8978 ahd_lqostat2_print(ahd_inb(ahd
, LQOSTAT2
), &cur_col
, 50);
8980 kprintf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8981 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8982 ahd
->scb_data
.numscbs
, ahd_inw(ahd
, CMDS_PENDING
),
8983 ahd_inw(ahd
, LASTSCB
), ahd_inw(ahd
, CURRSCB
),
8984 ahd_inw(ahd
, NEXTSCB
));
8987 ahd_search_qinfifo(ahd
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
8988 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
8989 ROLE_UNKNOWN
, /*status*/0, SEARCH_PRINT
);
8990 saved_scb_index
= ahd_get_scbptr(ahd
);
8991 kprintf("Pending list:");
8993 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
8994 if (i
++ > AHD_SCB_MAX
)
8996 cur_col
= kprintf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb
),
8997 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
));
8998 ahd_set_scbptr(ahd
, SCB_GET_TAG(scb
));
8999 ahd_scb_control_print(ahd_inb_scbram(ahd
, SCB_CONTROL
),
9001 ahd_scb_scsiid_print(ahd_inb_scbram(ahd
, SCB_SCSIID
),
9004 kprintf("\nTotal %d\n", i
);
9006 kprintf("Kernel Free SCB lists: ");
9008 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
9009 struct scb
*list_scb
;
9011 kprintf("\n COLIDX[%d]: ", AHD_GET_SCB_COL_IDX(ahd
, scb
));
9014 kprintf("%d ", SCB_GET_TAG(list_scb
));
9015 list_scb
= LIST_NEXT(list_scb
, collision_links
);
9016 } while (list_scb
&& i
++ < AHD_SCB_MAX
);
9019 kprintf("\n Any Device: ");
9020 LIST_FOREACH(scb
, &ahd
->scb_data
.any_dev_free_scb_list
, links
.le
) {
9021 if (i
++ > AHD_SCB_MAX
)
9023 kprintf("%d ", SCB_GET_TAG(scb
));
9027 kprintf("Sequencer Complete DMA-inprog list: ");
9028 scb_index
= ahd_inw(ahd
, COMPLETE_SCB_DMAINPROG_HEAD
);
9030 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
9031 ahd_set_scbptr(ahd
, scb_index
);
9032 kprintf("%d ", scb_index
);
9033 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
9037 kprintf("Sequencer Complete list: ");
9038 scb_index
= ahd_inw(ahd
, COMPLETE_SCB_HEAD
);
9040 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
9041 ahd_set_scbptr(ahd
, scb_index
);
9042 kprintf("%d ", scb_index
);
9043 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
9048 kprintf("Sequencer DMA-Up and Complete list: ");
9049 scb_index
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
9051 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
9052 ahd_set_scbptr(ahd
, scb_index
);
9053 kprintf("%d ", scb_index
);
9054 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
9057 kprintf("Sequencer On QFreeze and Complete list: ");
9058 scb_index
= ahd_inw(ahd
, COMPLETE_ON_QFREEZE_HEAD
);
9060 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
9061 ahd_set_scbptr(ahd
, scb_index
);
9062 kprintf("%d ", scb_index
);
9063 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
9066 ahd_set_scbptr(ahd
, saved_scb_index
);
9067 dffstat
= ahd_inb(ahd
, DFFSTAT
);
9068 for (i
= 0; i
< 2; i
++) {
9070 struct scb
*fifo_scb
;
9074 ahd_set_modes(ahd
, AHD_MODE_DFF0
+ i
, AHD_MODE_DFF0
+ i
);
9075 fifo_scbptr
= ahd_get_scbptr(ahd
);
9076 kprintf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9078 (dffstat
& (FIFO0FREE
<< i
)) ? "Free" : "Active",
9079 ahd_inw(ahd
, LONGJMP_ADDR
), fifo_scbptr
);
9081 ahd_seqimode_print(ahd_inb(ahd
, SEQIMODE
), &cur_col
, 50);
9082 ahd_seqintsrc_print(ahd_inb(ahd
, SEQINTSRC
), &cur_col
, 50);
9083 ahd_dfcntrl_print(ahd_inb(ahd
, DFCNTRL
), &cur_col
, 50);
9084 ahd_dfstatus_print(ahd_inb(ahd
, DFSTATUS
), &cur_col
, 50);
9085 ahd_sg_cache_shadow_print(ahd_inb(ahd
, SG_CACHE_SHADOW
),
9087 ahd_sg_state_print(ahd_inb(ahd
, SG_STATE
), &cur_col
, 50);
9088 ahd_dffsxfrctl_print(ahd_inb(ahd
, DFFSXFRCTL
), &cur_col
, 50);
9089 ahd_soffcnt_print(ahd_inb(ahd
, SOFFCNT
), &cur_col
, 50);
9090 ahd_mdffstat_print(ahd_inb(ahd
, MDFFSTAT
), &cur_col
, 50);
9095 cur_col
+= kprintf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9096 ahd_inl(ahd
, SHADDR
+4),
9097 ahd_inl(ahd
, SHADDR
),
9098 (ahd_inb(ahd
, SHCNT
)
9099 | (ahd_inb(ahd
, SHCNT
+ 1) << 8)
9100 | (ahd_inb(ahd
, SHCNT
+ 2) << 16)));
9105 cur_col
+= kprintf("HADDR = 0x%x%x, HCNT = 0x%x ",
9106 ahd_inl(ahd
, HADDR
+4),
9107 ahd_inl(ahd
, HADDR
),
9109 | (ahd_inb(ahd
, HCNT
+ 1) << 8)
9110 | (ahd_inb(ahd
, HCNT
+ 2) << 16)));
9111 ahd_ccsgctl_print(ahd_inb(ahd
, CCSGCTL
), &cur_col
, 50);
9113 if ((ahd_debug
& AHD_SHOW_SG
) != 0) {
9114 fifo_scb
= ahd_lookup_scb(ahd
, fifo_scbptr
);
9115 if (fifo_scb
!= NULL
)
9116 ahd_dump_sglist(fifo_scb
);
9120 kprintf("\nLQIN: ");
9121 for (i
= 0; i
< 20; i
++)
9122 kprintf("0x%x ", ahd_inb(ahd
, LQIN
+ i
));
9124 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
9125 kprintf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9126 ahd_name(ahd
), ahd_inb(ahd
, LQISTATE
), ahd_inb(ahd
, LQOSTATE
),
9127 ahd_inb(ahd
, OPTIONMODE
));
9128 kprintf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9129 ahd_name(ahd
), ahd_inb(ahd
, OS_SPACE_CNT
),
9130 ahd_inb(ahd
, MAXCMDCNT
));
9131 kprintf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9132 ahd_name(ahd
), ahd_inb(ahd
, SAVED_SCSIID
),
9133 ahd_inb(ahd
, SAVED_LUN
));
9134 ahd_simode0_print(ahd_inb(ahd
, SIMODE0
), &cur_col
, 50);
9136 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
9138 ahd_ccscbctl_print(ahd_inb(ahd
, CCSCBCTL
), &cur_col
, 50);
9140 ahd_set_modes(ahd
, ahd
->saved_src_mode
, ahd
->saved_dst_mode
);
9141 kprintf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9142 ahd_name(ahd
), ahd_inw(ahd
, REG0
), ahd_inw(ahd
, SINDEX
),
9143 ahd_inw(ahd
, DINDEX
));
9144 kprintf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9145 ahd_name(ahd
), ahd_get_scbptr(ahd
),
9146 ahd_inw_scbram(ahd
, SCB_NEXT
),
9147 ahd_inw_scbram(ahd
, SCB_NEXT2
));
9148 kprintf("CDB %x %x %x %x %x %x\n",
9149 ahd_inb_scbram(ahd
, SCB_CDB_STORE
),
9150 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+1),
9151 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+2),
9152 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+3),
9153 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+4),
9154 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+5));
9156 for (i
= 0; i
< ahd
->stack_size
; i
++) {
9157 ahd
->saved_stack
[i
] =
9158 ahd_inb(ahd
, STACK
)|(ahd_inb(ahd
, STACK
) << 8);
9159 kprintf(" 0x%x", ahd
->saved_stack
[i
]);
9161 for (i
= ahd
->stack_size
-1; i
>= 0; i
--) {
9162 ahd_outb(ahd
, STACK
, ahd
->saved_stack
[i
] & 0xFF);
9163 ahd_outb(ahd
, STACK
, (ahd
->saved_stack
[i
] >> 8) & 0xFF);
9165 kprintf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9166 ahd_platform_dump_card_state(ahd
);
9167 ahd_restore_modes(ahd
, saved_modes
);
9173 ahd_dump_scbs(struct ahd_softc
*ahd
)
9175 ahd_mode_state saved_modes
;
9176 u_int saved_scb_index
;
9179 saved_modes
= ahd_save_modes(ahd
);
9180 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
9181 saved_scb_index
= ahd_get_scbptr(ahd
);
9182 for (i
= 0; i
< AHD_SCB_MAX
; i
++) {
9183 ahd_set_scbptr(ahd
, i
);
9185 kprintf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9186 ahd_inb_scbram(ahd
, SCB_CONTROL
),
9187 ahd_inb_scbram(ahd
, SCB_SCSIID
),
9188 ahd_inw_scbram(ahd
, SCB_NEXT
),
9189 ahd_inw_scbram(ahd
, SCB_NEXT2
),
9190 ahd_inl_scbram(ahd
, SCB_SGPTR
),
9191 ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
));
9194 ahd_set_scbptr(ahd
, saved_scb_index
);
9195 ahd_restore_modes(ahd
, saved_modes
);
9199 /*************************** Timeout Handling *********************************/
9201 ahd_timeout(struct scb
*scb
)
9203 struct ahd_softc
*ahd
;
9205 ahd
= scb
->ahd_softc
;
9206 if ((scb
->flags
& SCB_ACTIVE
) != 0) {
9207 if ((scb
->flags
& SCB_TIMEDOUT
) == 0) {
9208 LIST_INSERT_HEAD(&ahd
->timedout_scbs
, scb
,
9210 scb
->flags
|= SCB_TIMEDOUT
;
9212 ahd_wakeup_recovery_thread(ahd
);
9217 * ahd_recover_commands determines if any of the commands that have currently
9218 * timedout are the root cause for this timeout. Innocent commands are given
9219 * a new timeout while we wait for the command executing on the bus to timeout.
9220 * This routine is invoked from a thread context so we are allowed to sleep.
9221 * Our lock is not held on entry.
9224 ahd_recover_commands(struct ahd_softc
*ahd
)
9227 struct scb
*active_scb
;
9230 u_int active_scbptr
;
9234 * Pause the controller and manually flush any
9235 * commands that have just completed but that our
9236 * interrupt handler has yet to see.
9238 was_paused
= ahd_is_paused(ahd
);
9240 kprintf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd
),
9241 was_paused
? "" : "not ");
9242 ahd_dump_card_state(ahd
);
9244 ahd_pause_and_flushwork(ahd
);
9246 if (LIST_EMPTY(&ahd
->timedout_scbs
) != 0) {
9248 * The timedout commands have already
9249 * completed. This typically means
9250 * that either the timeout value was on
9251 * the hairy edge of what the device
9252 * requires or - more likely - interrupts
9253 * are not happening.
9255 kprintf("%s: Timedout SCBs already complete. "
9256 "Interrupts may not be functioning.\n", ahd_name(ahd
));
9262 * Determine identity of SCB acting on the bus.
9263 * This test only catches non-packetized transactions.
9264 * Due to the fleeting nature of packetized operations,
9265 * we can't easily determine that a packetized operation
9268 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
9269 last_phase
= ahd_inb(ahd
, LASTPHASE
);
9270 active_scbptr
= ahd_get_scbptr(ahd
);
9272 if (last_phase
!= P_BUSFREE
9273 || (ahd_inb(ahd
, SEQ_FLAGS
) & NOT_IDENTIFIED
) == 0)
9274 active_scb
= ahd_lookup_scb(ahd
, active_scbptr
);
9276 while ((scb
= LIST_FIRST(&ahd
->timedout_scbs
)) != NULL
) {
9281 target
= SCB_GET_TARGET(ahd
, scb
);
9282 channel
= SCB_GET_CHANNEL(ahd
, scb
);
9283 lun
= SCB_GET_LUN(scb
);
9285 ahd_print_path(ahd
, scb
);
9286 kprintf("SCB %d - timed out\n", SCB_GET_TAG(scb
));
9288 if (scb
->flags
& (SCB_DEVICE_RESET
|SCB_ABORT
)) {
9290 * Been down this road before.
9291 * Do a full bus reset.
9293 aic_set_transaction_status(scb
, CAM_CMD_TIMEOUT
);
9295 found
= ahd_reset_channel(ahd
, channel
,
9296 /*Initiate Reset*/TRUE
);
9297 kprintf("%s: Issued Channel %c Bus Reset. "
9298 "%d SCBs aborted\n", ahd_name(ahd
), channel
,
9304 * Remove the command from the timedout list in
9305 * preparation for requeing it.
9307 LIST_REMOVE(scb
, timedout_links
);
9308 scb
->flags
&= ~SCB_TIMEDOUT
;
9310 if (active_scb
!= NULL
) {
9312 if (active_scb
!= scb
) {
9315 * If the active SCB is not us, assume that
9316 * the active SCB has a longer timeout than
9317 * the timedout SCB, and wait for the active
9318 * SCB to timeout. As a safeguard, only
9319 * allow this deferral to continue if some
9320 * untimed-out command is outstanding.
9322 if (ahd_other_scb_timeout(ahd
, scb
,
9329 * We're active on the bus, so assert ATN
9330 * and hope that the target responds.
9332 ahd_set_recoveryscb(ahd
, active_scb
);
9333 active_scb
->flags
|= SCB_RECOVERY_SCB
|SCB_DEVICE_RESET
;
9334 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
9335 ahd_outb(ahd
, SCSISIGO
, last_phase
|ATNO
);
9336 ahd_print_path(ahd
, active_scb
);
9337 kprintf("BDR message in message buffer\n");
9338 aic_scb_timer_reset(scb
, 2 * 1000);
9340 } else if (last_phase
!= P_BUSFREE
9341 && ahd_inb(ahd
, SCSIPHASE
) == 0) {
9343 * SCB is not identified, there
9344 * is no pending REQ, and the sequencer
9345 * has not seen a busfree. Looks like
9346 * a stuck connection waiting to
9347 * go busfree. Reset the bus.
9349 kprintf("%s: Connection stuck awaiting busfree or "
9350 "Identify Msg.\n", ahd_name(ahd
));
9352 } else if (ahd_search_qinfifo(ahd
, target
, channel
, lun
,
9354 ROLE_INITIATOR
, /*status*/0,
9355 SEARCH_COUNT
) > 0) {
9358 * We haven't even gone out on the bus
9359 * yet, so the timeout must be due to
9360 * some other command. Reset the timer
9363 if (ahd_other_scb_timeout(ahd
, scb
, NULL
) == 0)
9367 * This SCB is for a disconnected transaction
9368 * and we haven't found a better candidate on
9369 * the bus to explain this timeout.
9371 ahd_set_recoveryscb(ahd
, scb
);
9374 * Actually re-queue this SCB in an attempt
9375 * to select the device before it reconnects.
9376 * In either case (selection or reselection),
9377 * we will now issue a target reset to the
9380 scb
->flags
|= SCB_DEVICE_RESET
;
9381 scb
->hscb
->cdb_len
= 0;
9382 scb
->hscb
->task_attribute
= 0;
9383 scb
->hscb
->task_management
= SIU_TASKMGMT_ABORT_TASK
;
9385 ahd_set_scbptr(ahd
, SCB_GET_TAG(scb
));
9386 if ((scb
->flags
& SCB_PACKETIZED
) != 0) {
9388 * Mark the SCB has having an outstanding
9389 * task management function. Should the command
9390 * complete normally before the task management
9391 * function can be sent, the host will be
9392 * notified to abort our requeued SCB.
9394 ahd_outb(ahd
, SCB_TASK_MANAGEMENT
,
9395 scb
->hscb
->task_management
);
9398 * If non-packetized, set the MK_MESSAGE control
9399 * bit indicating that we desire to send a
9400 * message. We also set the disconnected flag
9401 * since there is no guarantee that our SCB
9402 * control byte matches the version on the
9403 * card. We don't want the sequencer to abort
9404 * the command thinking an unsolicited
9405 * reselection occurred.
9407 scb
->hscb
->control
|= MK_MESSAGE
|DISCONNECTED
;
9410 * The sequencer will never re-reference the
9411 * in-core SCB. To make sure we are notified
9412 * during reslection, set the MK_MESSAGE flag in
9413 * the card's copy of the SCB.
9415 ahd_outb(ahd
, SCB_CONTROL
,
9416 ahd_inb(ahd
, SCB_CONTROL
)|MK_MESSAGE
);
9420 * Clear out any entries in the QINFIFO first
9421 * so we are the next SCB for this target
9424 ahd_search_qinfifo(ahd
, target
, channel
, lun
,
9425 SCB_LIST_NULL
, ROLE_INITIATOR
,
9426 CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
9427 ahd_qinfifo_requeue_tail(ahd
, scb
);
9428 ahd_set_scbptr(ahd
, active_scbptr
);
9429 ahd_print_path(ahd
, scb
);
9430 kprintf("Queuing a BDR SCB\n");
9431 aic_scb_timer_reset(scb
, 2 * 1000);
9437 * Any remaining SCBs were not the "culprit", so remove
9438 * them from the timeout list. The timer for these commands
9439 * will be reset once the recovery SCB completes.
9441 while ((scb
= LIST_FIRST(&ahd
->timedout_scbs
)) != NULL
) {
9443 LIST_REMOVE(scb
, timedout_links
);
9444 scb
->flags
&= ~SCB_TIMEDOUT
;
9451 * Re-schedule a timeout for the passed in SCB if we determine that some
9452 * other SCB is in the process of recovery or an SCB with a longer
9453 * timeout is still pending. Limit our search to just "other_scb"
9454 * if it is non-NULL.
9457 ahd_other_scb_timeout(struct ahd_softc
*ahd
, struct scb
*scb
,
9458 struct scb
*other_scb
)
9463 ahd_print_path(ahd
, scb
);
9464 kprintf("Other SCB Timeout%s",
9465 (scb
->flags
& SCB_OTHERTCL_TIMEOUT
) != 0
9466 ? " again\n" : "\n");
9468 newtimeout
= aic_get_timeout(scb
);
9469 scb
->flags
|= SCB_OTHERTCL_TIMEOUT
;
9471 if (other_scb
!= NULL
) {
9472 if ((other_scb
->flags
9473 & (SCB_OTHERTCL_TIMEOUT
|SCB_TIMEDOUT
)) == 0
9474 || (other_scb
->flags
& SCB_RECOVERY_SCB
) != 0) {
9476 newtimeout
= MAX(aic_get_timeout(other_scb
),
9480 LIST_FOREACH(other_scb
, &ahd
->pending_scbs
, pending_links
) {
9481 if ((other_scb
->flags
9482 & (SCB_OTHERTCL_TIMEOUT
|SCB_TIMEDOUT
)) == 0
9483 || (other_scb
->flags
& SCB_RECOVERY_SCB
) != 0) {
9485 newtimeout
= MAX(aic_get_timeout(other_scb
),
9492 aic_scb_timer_reset(scb
, newtimeout
);
9494 ahd_print_path(ahd
, scb
);
9495 kprintf("No other SCB worth waiting for...\n");
9498 return (found
!= 0);
9501 /**************************** Flexport Logic **********************************/
9503 * Read count 16bit words from 16bit word address start_addr from the
9504 * SEEPROM attached to the controller, into buf, using the controller's
9505 * SEEPROM reading state machine. Optionally treat the data as a byte
9506 * stream in terms of byte order.
9509 ahd_read_seeprom(struct ahd_softc
*ahd
, uint16_t *buf
,
9510 u_int start_addr
, u_int count
, int bytestream
)
9517 * If we never make it through the loop even once,
9518 * we were passed invalid arguments.
9521 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9522 end_addr
= start_addr
+ count
;
9523 for (cur_addr
= start_addr
; cur_addr
< end_addr
; cur_addr
++) {
9525 ahd_outb(ahd
, SEEADR
, cur_addr
);
9526 ahd_outb(ahd
, SEECTL
, SEEOP_READ
| SEESTART
);
9528 error
= ahd_wait_seeprom(ahd
);
9531 if (bytestream
!= 0) {
9532 uint8_t *bytestream_ptr
;
9534 bytestream_ptr
= (uint8_t *)buf
;
9535 *bytestream_ptr
++ = ahd_inb(ahd
, SEEDAT
);
9536 *bytestream_ptr
= ahd_inb(ahd
, SEEDAT
+1);
9539 * ahd_inw() already handles machine byte order.
9541 *buf
= ahd_inw(ahd
, SEEDAT
);
9549 * Write count 16bit words from buf, into SEEPROM attache to the
9550 * controller starting at 16bit word address start_addr, using the
9551 * controller's SEEPROM writing state machine.
9554 ahd_write_seeprom(struct ahd_softc
*ahd
, uint16_t *buf
,
9555 u_int start_addr
, u_int count
)
9562 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9565 /* Place the chip into write-enable mode */
9566 ahd_outb(ahd
, SEEADR
, SEEOP_EWEN_ADDR
);
9567 ahd_outb(ahd
, SEECTL
, SEEOP_EWEN
| SEESTART
);
9568 error
= ahd_wait_seeprom(ahd
);
9573 * Write the data. If we don't get throught the loop at
9574 * least once, the arguments were invalid.
9577 end_addr
= start_addr
+ count
;
9578 for (cur_addr
= start_addr
; cur_addr
< end_addr
; cur_addr
++) {
9579 ahd_outw(ahd
, SEEDAT
, *buf
++);
9580 ahd_outb(ahd
, SEEADR
, cur_addr
);
9581 ahd_outb(ahd
, SEECTL
, SEEOP_WRITE
| SEESTART
);
9583 retval
= ahd_wait_seeprom(ahd
);
9591 ahd_outb(ahd
, SEEADR
, SEEOP_EWDS_ADDR
);
9592 ahd_outb(ahd
, SEECTL
, SEEOP_EWDS
| SEESTART
);
9593 error
= ahd_wait_seeprom(ahd
);
9600 * Wait ~100us for the serial eeprom to satisfy our request.
9603 ahd_wait_seeprom(struct ahd_softc
*ahd
)
9608 while ((ahd_inb(ahd
, SEESTAT
) & (SEEARBACK
|SEEBUSY
)) != 0 && --cnt
)
9617 * Validate the two checksums in the per_channel
9618 * vital product data struct.
9621 ahd_verify_vpd_cksum(struct vpd_config
*vpd
)
9628 vpdarray
= (uint8_t *)vpd
;
9629 maxaddr
= offsetof(struct vpd_config
, vpd_checksum
);
9631 for (i
= offsetof(struct vpd_config
, resource_type
); i
< maxaddr
; i
++)
9632 checksum
= checksum
+ vpdarray
[i
];
9634 || (-checksum
& 0xFF) != vpd
->vpd_checksum
)
9638 maxaddr
= offsetof(struct vpd_config
, checksum
);
9639 for (i
= offsetof(struct vpd_config
, default_target_flags
);
9641 checksum
= checksum
+ vpdarray
[i
];
9643 || (-checksum
& 0xFF) != vpd
->checksum
)
9649 ahd_verify_cksum(struct seeprom_config
*sc
)
9656 maxaddr
= (sizeof(*sc
)/2) - 1;
9658 scarray
= (uint16_t *)sc
;
9660 for (i
= 0; i
< maxaddr
; i
++)
9661 checksum
= checksum
+ scarray
[i
];
9663 || (checksum
& 0xFFFF) != sc
->checksum
) {
9671 ahd_acquire_seeprom(struct ahd_softc
*ahd
)
9674 * We should be able to determine the SEEPROM type
9675 * from the flexport logic, but unfortunately not
9676 * all implementations have this logic and there is
9677 * no programatic method for determining if the logic
9685 error
= ahd_read_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
, &seetype
);
9687 || ((seetype
& FLX_ROMSTAT_SEECFG
) == FLX_ROMSTAT_SEE_NONE
))
9694 ahd_release_seeprom(struct ahd_softc
*ahd
)
9696 /* Currently a no-op */
9700 ahd_write_flexport(struct ahd_softc
*ahd
, u_int addr
, u_int value
)
9704 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9706 panic("ahd_write_flexport: address out of range");
9707 ahd_outb(ahd
, BRDCTL
, BRDEN
|(addr
<< 3));
9708 error
= ahd_wait_flexport(ahd
);
9711 ahd_outb(ahd
, BRDDAT
, value
);
9712 ahd_flush_device_writes(ahd
);
9713 ahd_outb(ahd
, BRDCTL
, BRDSTB
|BRDEN
|(addr
<< 3));
9714 ahd_flush_device_writes(ahd
);
9715 ahd_outb(ahd
, BRDCTL
, BRDEN
|(addr
<< 3));
9716 ahd_flush_device_writes(ahd
);
9717 ahd_outb(ahd
, BRDCTL
, 0);
9718 ahd_flush_device_writes(ahd
);
9723 ahd_read_flexport(struct ahd_softc
*ahd
, u_int addr
, uint8_t *value
)
9727 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9729 panic("ahd_read_flexport: address out of range");
9730 ahd_outb(ahd
, BRDCTL
, BRDRW
|BRDEN
|(addr
<< 3));
9731 error
= ahd_wait_flexport(ahd
);
9734 *value
= ahd_inb(ahd
, BRDDAT
);
9735 ahd_outb(ahd
, BRDCTL
, 0);
9736 ahd_flush_device_writes(ahd
);
9741 * Wait at most 2 seconds for flexport arbitration to succeed.
9744 ahd_wait_flexport(struct ahd_softc
*ahd
)
9748 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9749 cnt
= 1000000 * 2 / 5;
9750 while ((ahd_inb(ahd
, BRDCTL
) & FLXARBACK
) == 0 && --cnt
)
9758 /************************* Target Mode ****************************************/
9759 #ifdef AHD_TARGET_MODE
9761 ahd_find_tmode_devs(struct ahd_softc
*ahd
, struct cam_sim
*sim
, union ccb
*ccb
,
9762 struct ahd_tmode_tstate
**tstate
,
9763 struct ahd_tmode_lstate
**lstate
,
9764 int notfound_failure
)
9767 if ((ahd
->features
& AHD_TARGETMODE
) == 0)
9768 return (CAM_REQ_INVALID
);
9771 * Handle the 'black hole' device that sucks up
9772 * requests to unattached luns on enabled targets.
9774 if (ccb
->ccb_h
.target_id
== CAM_TARGET_WILDCARD
9775 && ccb
->ccb_h
.target_lun
== CAM_LUN_WILDCARD
) {
9777 *lstate
= ahd
->black_hole
;
9781 max_id
= (ahd
->features
& AHD_WIDE
) ? 15 : 7;
9782 if (ccb
->ccb_h
.target_id
> max_id
)
9783 return (CAM_TID_INVALID
);
9785 if (ccb
->ccb_h
.target_lun
>= AHD_NUM_LUNS
)
9786 return (CAM_LUN_INVALID
);
9788 *tstate
= ahd
->enabled_targets
[ccb
->ccb_h
.target_id
];
9790 if (*tstate
!= NULL
)
9792 (*tstate
)->enabled_luns
[ccb
->ccb_h
.target_lun
];
9795 if (notfound_failure
!= 0 && *lstate
== NULL
)
9796 return (CAM_PATH_INVALID
);
9798 return (CAM_REQ_CMP
);
9802 ahd_handle_en_lun(struct ahd_softc
*ahd
, struct cam_sim
*sim
, union ccb
*ccb
)
9805 struct ahd_tmode_tstate
*tstate
;
9806 struct ahd_tmode_lstate
*lstate
;
9807 struct ccb_en_lun
*cel
;
9815 status
= ahd_find_tmode_devs(ahd
, sim
, ccb
, &tstate
, &lstate
,
9816 /*notfound_failure*/FALSE
);
9818 if (status
!= CAM_REQ_CMP
) {
9819 ccb
->ccb_h
.status
= status
;
9823 if ((ahd
->features
& AHD_MULTIROLE
) != 0) {
9826 our_id
= ahd
->our_id
;
9827 if (ccb
->ccb_h
.target_id
!= our_id
) {
9828 if ((ahd
->features
& AHD_MULTI_TID
) != 0
9829 && (ahd
->flags
& AHD_INITIATORROLE
) != 0) {
9831 * Only allow additional targets if
9832 * the initiator role is disabled.
9833 * The hardware cannot handle a re-select-in
9834 * on the initiator id during a re-select-out
9835 * on a different target id.
9837 status
= CAM_TID_INVALID
;
9838 } else if ((ahd
->flags
& AHD_INITIATORROLE
) != 0
9839 || ahd
->enabled_luns
> 0) {
9841 * Only allow our target id to change
9842 * if the initiator role is not configured
9843 * and there are no enabled luns which
9844 * are attached to the currently registered
9847 status
= CAM_TID_INVALID
;
9852 if (status
!= CAM_REQ_CMP
) {
9853 ccb
->ccb_h
.status
= status
;
9858 * We now have an id that is valid.
9859 * If we aren't in target mode, switch modes.
9861 if ((ahd
->flags
& AHD_TARGETROLE
) == 0
9862 && ccb
->ccb_h
.target_id
!= CAM_TARGET_WILDCARD
) {
9863 kprintf("Configuring Target Mode\n");
9864 if (LIST_FIRST(&ahd
->pending_scbs
) != NULL
) {
9865 ccb
->ccb_h
.status
= CAM_BUSY
;
9868 ahd
->flags
|= AHD_TARGETROLE
;
9869 if ((ahd
->features
& AHD_MULTIROLE
) == 0)
9870 ahd
->flags
&= ~AHD_INITIATORROLE
;
9876 target
= ccb
->ccb_h
.target_id
;
9877 lun
= ccb
->ccb_h
.target_lun
;
9878 channel
= SIM_CHANNEL(ahd
, sim
);
9879 target_mask
= 0x01 << target
;
9883 if (cel
->enable
!= 0) {
9886 /* Are we already enabled?? */
9887 if (lstate
!= NULL
) {
9888 xpt_print_path(ccb
->ccb_h
.path
);
9889 kprintf("Lun already enabled\n");
9890 ccb
->ccb_h
.status
= CAM_LUN_ALRDY_ENA
;
9894 if (cel
->grp6_len
!= 0
9895 || cel
->grp7_len
!= 0) {
9897 * Don't (yet?) support vendor
9898 * specific commands.
9900 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
9901 kprintf("Non-zero Group Codes\n");
9907 * Setup our data structures.
9909 if (target
!= CAM_TARGET_WILDCARD
&& tstate
== NULL
) {
9910 tstate
= ahd_alloc_tstate(ahd
, target
, channel
);
9911 if (tstate
== NULL
) {
9912 xpt_print_path(ccb
->ccb_h
.path
);
9913 kprintf("Couldn't allocate tstate\n");
9914 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
9918 lstate
= kmalloc(sizeof(*lstate
), M_DEVBUF
, M_INTWAIT
| M_ZERO
);
9919 status
= xpt_create_path(&lstate
->path
, /*periph*/NULL
,
9920 xpt_path_path_id(ccb
->ccb_h
.path
),
9921 xpt_path_target_id(ccb
->ccb_h
.path
),
9922 xpt_path_lun_id(ccb
->ccb_h
.path
));
9923 if (status
!= CAM_REQ_CMP
) {
9924 kfree(lstate
, M_DEVBUF
);
9925 xpt_print_path(ccb
->ccb_h
.path
);
9926 kprintf("Couldn't allocate path\n");
9927 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
9930 SLIST_INIT(&lstate
->accept_tios
);
9931 SLIST_INIT(&lstate
->immed_notifies
);
9933 if (target
!= CAM_TARGET_WILDCARD
) {
9934 tstate
->enabled_luns
[lun
] = lstate
;
9935 ahd
->enabled_luns
++;
9937 if ((ahd
->features
& AHD_MULTI_TID
) != 0) {
9940 targid_mask
= ahd_inw(ahd
, TARGID
);
9941 targid_mask
|= target_mask
;
9942 ahd_outw(ahd
, TARGID
, targid_mask
);
9943 ahd_update_scsiid(ahd
, targid_mask
);
9948 channel
= SIM_CHANNEL(ahd
, sim
);
9949 our_id
= SIM_SCSI_ID(ahd
, sim
);
9952 * This can only happen if selections
9955 if (target
!= our_id
) {
9960 sblkctl
= ahd_inb(ahd
, SBLKCTL
);
9961 cur_channel
= (sblkctl
& SELBUSB
)
9963 if ((ahd
->features
& AHD_TWIN
) == 0)
9965 swap
= cur_channel
!= channel
;
9966 ahd
->our_id
= target
;
9969 ahd_outb(ahd
, SBLKCTL
,
9972 ahd_outb(ahd
, SCSIID
, target
);
9975 ahd_outb(ahd
, SBLKCTL
, sblkctl
);
9979 ahd
->black_hole
= lstate
;
9980 /* Allow select-in operations */
9981 if (ahd
->black_hole
!= NULL
&& ahd
->enabled_luns
> 0) {
9982 scsiseq1
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
9984 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq1
);
9985 scsiseq1
= ahd_inb(ahd
, SCSISEQ1
);
9987 ahd_outb(ahd
, SCSISEQ1
, scsiseq1
);
9990 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
9991 xpt_print_path(ccb
->ccb_h
.path
);
9992 kprintf("Lun now enabled for target mode\n");
9997 if (lstate
== NULL
) {
9998 ccb
->ccb_h
.status
= CAM_LUN_INVALID
;
10002 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
10003 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
10004 struct ccb_hdr
*ccbh
;
10006 ccbh
= &scb
->io_ctx
->ccb_h
;
10007 if (ccbh
->func_code
== XPT_CONT_TARGET_IO
10008 && !xpt_path_comp(ccbh
->path
, ccb
->ccb_h
.path
)){
10009 kprintf("CTIO pending\n");
10010 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
10015 if (SLIST_FIRST(&lstate
->accept_tios
) != NULL
) {
10016 kprintf("ATIOs pending\n");
10017 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
10020 if (SLIST_FIRST(&lstate
->immed_notifies
) != NULL
) {
10021 kprintf("INOTs pending\n");
10022 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
10025 if (ccb
->ccb_h
.status
!= CAM_REQ_CMP
) {
10029 xpt_print_path(ccb
->ccb_h
.path
);
10030 kprintf("Target mode disabled\n");
10031 xpt_free_path(lstate
->path
);
10032 kfree(lstate
, M_DEVBUF
);
10035 /* Can we clean up the target too? */
10036 if (target
!= CAM_TARGET_WILDCARD
) {
10037 tstate
->enabled_luns
[lun
] = NULL
;
10038 ahd
->enabled_luns
--;
10039 for (empty
= 1, i
= 0; i
< 8; i
++)
10040 if (tstate
->enabled_luns
[i
] != NULL
) {
10046 ahd_free_tstate(ahd
, target
, channel
,
10048 if (ahd
->features
& AHD_MULTI_TID
) {
10051 targid_mask
= ahd_inw(ahd
, TARGID
);
10052 targid_mask
&= ~target_mask
;
10053 ahd_outw(ahd
, TARGID
, targid_mask
);
10054 ahd_update_scsiid(ahd
, targid_mask
);
10059 ahd
->black_hole
= NULL
;
10062 * We can't allow selections without
10063 * our black hole device.
10067 if (ahd
->enabled_luns
== 0) {
10068 /* Disallow select-in */
10071 scsiseq1
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
10072 scsiseq1
&= ~ENSELI
;
10073 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq1
);
10074 scsiseq1
= ahd_inb(ahd
, SCSISEQ1
);
10075 scsiseq1
&= ~ENSELI
;
10076 ahd_outb(ahd
, SCSISEQ1
, scsiseq1
);
10078 if ((ahd
->features
& AHD_MULTIROLE
) == 0) {
10079 kprintf("Configuring Initiator Mode\n");
10080 ahd
->flags
&= ~AHD_TARGETROLE
;
10081 ahd
->flags
|= AHD_INITIATORROLE
;
10086 * Unpaused. The extra unpause
10087 * that follows is harmless.
10097 ahd_update_scsiid(struct ahd_softc
*ahd
, u_int targid_mask
)
10103 if ((ahd
->features
& AHD_MULTI_TID
) == 0)
10104 panic("ahd_update_scsiid called on non-multitid unit\n");
10107 * Since we will rely on the TARGID mask
10108 * for selection enables, ensure that OID
10109 * in SCSIID is not set to some other ID
10110 * that we don't want to allow selections on.
10112 if ((ahd
->features
& AHD_ULTRA2
) != 0)
10113 scsiid
= ahd_inb(ahd
, SCSIID_ULTRA2
);
10115 scsiid
= ahd_inb(ahd
, SCSIID
);
10116 scsiid_mask
= 0x1 << (scsiid
& OID
);
10117 if ((targid_mask
& scsiid_mask
) == 0) {
10120 /* ffs counts from 1 */
10121 our_id
= ffs(targid_mask
);
10123 our_id
= ahd
->our_id
;
10129 if ((ahd
->features
& AHD_ULTRA2
) != 0)
10130 ahd_outb(ahd
, SCSIID_ULTRA2
, scsiid
);
10132 ahd_outb(ahd
, SCSIID
, scsiid
);
10137 ahd_run_tqinfifo(struct ahd_softc
*ahd
, int paused
)
10139 struct target_cmd
*cmd
;
10141 ahd_sync_tqinfifo(ahd
, BUS_DMASYNC_POSTREAD
);
10142 while ((cmd
= &ahd
->targetcmds
[ahd
->tqinfifonext
])->cmd_valid
!= 0) {
10145 * Only advance through the queue if we
10146 * have the resources to process the command.
10148 if (ahd_handle_target_cmd(ahd
, cmd
) != 0)
10151 cmd
->cmd_valid
= 0;
10152 ahd_dmamap_sync(ahd
, ahd
->shared_data_dmat
,
10153 ahd
->shared_data_dmamap
,
10154 ahd_targetcmd_offset(ahd
, ahd
->tqinfifonext
),
10155 sizeof(struct target_cmd
),
10156 BUS_DMASYNC_PREREAD
);
10157 ahd
->tqinfifonext
++;
10160 * Lazily update our position in the target mode incoming
10161 * command queue as seen by the sequencer.
10163 if ((ahd
->tqinfifonext
& (HOST_TQINPOS
- 1)) == 1) {
10166 hs_mailbox
= ahd_inb(ahd
, HS_MAILBOX
);
10167 hs_mailbox
&= ~HOST_TQINPOS
;
10168 hs_mailbox
|= ahd
->tqinfifonext
& HOST_TQINPOS
;
10169 ahd_outb(ahd
, HS_MAILBOX
, hs_mailbox
);
10175 ahd_handle_target_cmd(struct ahd_softc
*ahd
, struct target_cmd
*cmd
)
10177 struct ahd_tmode_tstate
*tstate
;
10178 struct ahd_tmode_lstate
*lstate
;
10179 struct ccb_accept_tio
*atio
;
10185 initiator
= SCSIID_TARGET(ahd
, cmd
->scsiid
);
10186 target
= SCSIID_OUR_ID(cmd
->scsiid
);
10187 lun
= (cmd
->identify
& MSG_IDENTIFY_LUNMASK
);
10190 tstate
= ahd
->enabled_targets
[target
];
10192 if (tstate
!= NULL
)
10193 lstate
= tstate
->enabled_luns
[lun
];
10196 * Commands for disabled luns go to the black hole driver.
10198 if (lstate
== NULL
)
10199 lstate
= ahd
->black_hole
;
10201 atio
= (struct ccb_accept_tio
*)SLIST_FIRST(&lstate
->accept_tios
);
10202 if (atio
== NULL
) {
10203 ahd
->flags
|= AHD_TQINFIFO_BLOCKED
;
10205 * Wait for more ATIOs from the peripheral driver for this lun.
10209 ahd
->flags
&= ~AHD_TQINFIFO_BLOCKED
;
10211 if ((ahd_debug
& AHD_SHOW_TQIN
) != 0)
10212 kprintf("Incoming command from %d for %d:%d%s\n",
10213 initiator
, target
, lun
,
10214 lstate
== ahd
->black_hole
? "(Black Holed)" : "");
10216 SLIST_REMOVE_HEAD(&lstate
->accept_tios
, sim_links
.sle
);
10218 if (lstate
== ahd
->black_hole
) {
10219 /* Fill in the wildcards */
10220 atio
->ccb_h
.target_id
= target
;
10221 atio
->ccb_h
.target_lun
= lun
;
10225 * Package it up and send it off to
10226 * whomever has this lun enabled.
10228 atio
->sense_len
= 0;
10229 atio
->init_id
= initiator
;
10230 if (byte
[0] != 0xFF) {
10231 /* Tag was included */
10232 atio
->tag_action
= *byte
++;
10233 atio
->tag_id
= *byte
++;
10234 atio
->ccb_h
.flags
= CAM_TAG_ACTION_VALID
;
10236 atio
->ccb_h
.flags
= 0;
10240 /* Okay. Now determine the cdb size based on the command code */
10241 switch (*byte
>> CMD_GROUP_CODE_SHIFT
) {
10247 atio
->cdb_len
= 10;
10250 atio
->cdb_len
= 16;
10253 atio
->cdb_len
= 12;
10257 /* Only copy the opcode. */
10259 kprintf("Reserved or VU command code type encountered\n");
10263 memcpy(atio
->cdb_io
.cdb_bytes
, byte
, atio
->cdb_len
);
10265 atio
->ccb_h
.status
|= CAM_CDB_RECVD
;
10267 if ((cmd
->identify
& MSG_IDENTIFY_DISCFLAG
) == 0) {
10269 * We weren't allowed to disconnect.
10270 * We're hanging on the bus until a
10271 * continue target I/O comes in response
10272 * to this accept tio.
10275 if ((ahd_debug
& AHD_SHOW_TQIN
) != 0)
10276 kprintf("Received Immediate Command %d:%d:%d - %p\n",
10277 initiator
, target
, lun
, ahd
->pending_device
);
10279 ahd
->pending_device
= lstate
;
10280 ahd_freeze_ccb((union ccb
*)atio
);
10281 atio
->ccb_h
.flags
|= CAM_DIS_DISCONNECT
;
10283 xpt_done((union ccb
*)atio
);