sys/boot/common/isapnp.h

   1 /*
   2  * Copyright (c) 1996, Sujal M. Patel
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Sujal M. Patel
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  * $FreeBSD: src/sys/boot/common/isapnp.h,v 1.7 2002/03/20 07:59:37 alfred Exp $
  33  */
  34
  35 #ifndef _BOOT_COMMON_ISAPNP_H_
  36 #define _BOOT_COMMON_ISAPNP_H_
  37
  38 /* Maximum Number of PnP Devices.  8 should be plenty */
  39 #define MAX_PNP_CARDS 8
  40
  41 /* Static ports to access PnP state machine */
  42 #ifndef _KERNEL
  43 #define _PNP_ADDRESS            0x279
  44 #define _PNP_WRITE_DATA         0xa79
  45 #endif
  46
  47 /* PnP Registers.  Write to ADDRESS and then use WRITE/READ_DATA */
  48 #define SET_RD_DATA             0x00
  49         /***
  50         Writing to this location modifies the address of the port used for
  51         reading from the Plug and Play ISA cards.   Bits[7:0] become I/O
  52         read port address bits[9:2].  Reads from this register are ignored.
  53         ***/
  54
  55 #define SERIAL_ISOLATION        0x01
  56         /***
  57         A read to this register causes a Plug and Play cards in the Isolation
  58         state to compare one bit of the boards ID.
  59         This register is read only.
  60         ***/
  61
  62 #define CONFIG_CONTROL          0x02
  63         /***
  64         Bit[2]  Reset CSN to 0
  65         Bit[1]  Return to the Wait for Key state
  66         Bit[0]  Reset all logical devices and restore configuration
  67                 registers to their power-up values.
  68
  69         A write to bit[0] of this register performs a reset function on
  70         all logical devices.  This resets the contents of configuration
  71         registers to  their default state.  All card's logical devices
  72         enter their default state and the CSN is preserved.
  73
  74         A write to bit[1] of this register causes all cards to enter the
  75         Wait for Key state but all CSNs are preserved and logical devices
  76         are not affected.
  77
  78         A write to bit[2] of this register causes all cards to reset their
  79         CSN to zero .
  80
  81         This register is write-only.  The values are not sticky, that is,
  82         hardware will automatically clear them and there is no need for
  83         software to clear the bits.
  84         ***/
  85
  86 #define WAKE                    0x03
  87         /***
  88         A write to this port will cause all cards that have a CSN that
  89         matches the write data[7:0] to go from the Sleep state to the either
  90         the Isolation state if the write data for this command is zero or
  91         the Config state if the write data is not zero.  Additionally, the
  92         pointer to the byte-serial device is reset.  This register is
  93         writeonly.
  94         ***/
  95
  96 #define RESOURCE_DATA           0x04
  97         /***
  98         A read from this address reads the next byte of resource information.
  99         The Status register must be polled until bit[0] is set before this
 100         register may be read.  This register is read only.
 101         ***/
 102
 103 #define STATUS                  0x05
 104         /***
 105         Bit[0] when set indicates it is okay to read the next data byte
 106         from the Resource Data register.  This register is readonly.
 107         ***/
 108
 109 #define SET_CSN                 0x06
 110         /***
 111         A write to this port sets a card's CSN.  The CSN is a value uniquely
 112         assigned to each ISA card after the serial identification process
 113         so that each card may be individually selected during a Wake[CSN]
 114         command. This register is read/write.
 115         ***/
 116
 117 #define SET_LDN                 0x07
 118         /***
 119         Selects the current logical device.  All reads and writes of memory,
 120         I/O, interrupt and DMA configuration information access the registers
 121         of the logical device written here.  In addition, the I/O Range
 122         Check and Activate  commands operate only on the selected logical
 123         device.  This register is read/write. If a card has only 1 logical
 124         device, this location should be a read-only value of 0x00.
 125         ***/
 126
 127 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
 128 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
 129
 130 #define ACTIVATE                0x30
 131         /***
 132         For each logical device there is one activate register that controls
 133         whether or not the logical device is active on the ISA bus.  Bit[0],
 134         if set, activates the logical device.  Bits[7:1] are reserved and
 135         must return 0 on reads.  This is a read/write register. Before a
 136         logical device is activated, I/O range check must be disabled.
 137         ***/
 138
 139 #define IO_RANGE_CHECK          0x31
 140         /***
 141         This register is used to perform a conflict check on the I/O port
 142         range programmed for use by a logical device.
 143
 144         Bit[7:2]  Reserved and must return 0 on reads
 145         Bit[1]    Enable I/O Range check, if set then I/O Range Check
 146         is enabled. I/O range check is only valid when the logical
 147         device is inactive.
 148
 149         Bit[0], if set, forces the logical device to respond to I/O reads
 150         of the logical device's assigned I/O range with a 0x55 when I/O
 151         range check is in operation.  If clear, the logical device drives
 152         0xAA.  This register is read/write.
 153         ***/
 154
 155 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
 156 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
 157
 158 #define MEM_CONFIG              0x40
 159         /***
 160         Four memory resource registers per range, four ranges.
 161         Fill with 0 if no ranges are enabled.
 162
 163         Offset 0:       RW Memory base address bits[23:16]
 164         Offset 1:       RW Memory base address bits[15:8]
 165         Offset 2:       Memory control
 166             Bit[1] specifies 8/16-bit control.  This bit is set to indicate
 167             16-bit memory, and cleared to indicate 8-bit memory.
 168             Bit[0], if cleared, indicates the next field can be used as a range
 169             length for decode (implies range length and base alignment of memory
 170             descriptor are equal).
 171             Bit[0], if set, indicates the next field is the upper limit for
 172             the address. -  - Bit[0] is read-only.
 173         Offset 3:       RW upper limit or range len, bits[23:16]
 174         Offset 4:       RW upper limit or range len, bits[15:8]
 175         Offset 5-Offset 7: filler, unused.
 176         ***/
 177
 178 #define IO_CONFIG_BASE          0x60
 179         /***
 180         Eight ranges, two bytes per range.
 181         Offset 0:               I/O port base address bits[15:8]
 182         Offset 1:               I/O port base address bits[7:0]
 183         ***/
 184
 185 #define IRQ_CONFIG              0x70
 186         /***
 187         Two entries, two bytes per entry.
 188         Offset 0:       RW interrupt level (1..15, 0=unused).
 189         Offset 1:       Bit[1]: level(1:hi, 0:low),
 190                         Bit[0]: type (1:level, 0:edge)
 191                 byte 1 can be readonly if 1 type of int is used.
 192         ***/
 193
 194 #define DRQ_CONFIG              0x74
 195         /***
 196         Two entries, one byte per entry. Bits[2:0] select
 197         which DMA channel is in use for DMA 0.  Zero selects DMA channel
 198         0, seven selects DMA channel 7. DMA channel 4, the cascade channel
 199         is used to indicate no DMA channel is active.
 200         ***/
 201
 202 /*** 32-bit memory accesses are at 0x76 ***/
 203
 204 /* Macros to parse Resource IDs */
 205 #define PNP_RES_TYPE(a)         (a >> 7)
 206 #define PNP_SRES_NUM(a)         (a >> 3)
 207 #define PNP_SRES_LEN(a)         (a & 0x07)
 208 #define PNP_LRES_NUM(a)         (a & 0x7f)
 209
 210 /* Small Resource Item names */
 211 #define PNP_VERSION             0x1
 212 #define LOG_DEVICE_ID           0x2
 213 #define COMP_DEVICE_ID          0x3
 214 #define IRQ_FORMAT              0x4
 215 #define DMA_FORMAT              0x5
 216 #define START_DEPEND_FUNC       0x6
 217 #define END_DEPEND_FUNC         0x7
 218 #define IO_PORT_DESC            0x8
 219 #define FIXED_IO_PORT_DESC      0x9
 220 #define SM_RES_RESERVED         0xa-0xd
 221 #define SM_VENDOR_DEFINED       0xe
 222 #define END_TAG                 0xf
 223
 224 /* Large Resource Item names */
 225 #define MEMORY_RANGE_DESC       0x1
 226 #define ID_STRING_ANSI          0x2
 227 #define ID_STRING_UNICODE       0x3
 228 #define LG_VENDOR_DEFINED       0x4
 229 #define _32BIT_MEM_RANGE_DESC   0x5
 230 #define _32BIT_FIXED_LOC_DESC   0x6
 231 #define LG_RES_RESERVED         0x7-0x7f
 232
 233 /*
 234  * pnp_cinfo contains Configuration Information. They are used
 235  * to communicate to the device driver the actual configuration
 236  * of the device.
 237  */
 238 struct pnp_cinfo {
 239         u_int vendor_id;        /* board id */
 240         u_int serial;           /* Board's Serial Number */
 241         u_long flags;           /* OS-reserved flags */
 242         u_char csn;             /* assigned Card Select Number */
 243         u_char ldn;             /* Logical Device Number */
 244         u_char enable;          /* pnp enable */
 245         u_char irq[2];          /* IRQ Number */
 246         u_char irq_type[2];     /* IRQ Type */
 247         u_char drq[2];
 248         u_short port[8];        /* The Base Address of the Port */
 249         struct {
 250                 u_long base;    /* Memory Base Address */
 251                 int control;    /* Memory Control Register */
 252                 u_long range;   /* Memory Range *OR* Upper Limit */
 253         } mem[4];
 254 };
 255
 256 #ifdef _KERNEL
 257
 258 struct pnp_device {
 259     char *pd_name;
 260     char * (*pd_probe ) (u_long csn, u_long vendor_id);
 261     void (*pd_attach ) (u_long csn, u_long vend_id, char * name,
 262         struct isa_device *dev);
 263     u_long      *pd_count;
 264     u_int *imask ;
 265 };
 266
 267 struct _pnp_id {
 268     u_long vendor_id;
 269     u_long serial;
 270     u_char checksum;
 271 } ;
 272
 273 struct pnp_dlist_node {
 274     struct pnp_device *pnp;
 275     struct isa_device dev;
 276     struct pnp_dlist_node *next;
 277 };
 278
 279 typedef struct _pnp_id pnp_id;
 280 extern pnp_id pnp_devices[MAX_PNP_CARDS];
 281
 282 /*
 283  * these two functions are for use in drivers
 284  */
 285 int read_pnp_parms(struct pnp_cinfo *d, int ldn);
 286 int write_pnp_parms(struct pnp_cinfo *d, int ldn);
 287 int enable_pnp_card(void);
 288
 289 /*
 290  * used by autoconfigure to actually probe and attach drivers
 291  */
 292 void pnp_configure(void);
 293
 294 #endif /* _KERNEL */
 295
 296 #endif /* !_BOOT_COMMON_ISAPNP_H_ */