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ahci - Add quirks for Marvell devices
[dragonfly.git] / sys / dev / disk / ahci / ahci_attach.c
blobff4df34c71e1ad766d6b959a4d64a0a529c05b26
1 /*
2 * (MPSAFE)
3 *
4 * Copyright (c) 2006 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 *
19 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
20 *
21 * This code is derived from software contributed to The DragonFly Project
22 * by Matthew Dillon <dillon@backplane.com>
23 *
24 * Redistribution and use in source and binary forms, with or without
25 * modification, are permitted provided that the following conditions
26 * are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in
32 * the documentation and/or other materials provided with the
33 * distribution.
34 * 3. Neither the name of The DragonFly Project nor the names of its
35 * contributors may be used to endorse or promote products derived
36 * from this software without specific, prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
41 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
42 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
43 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
44 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
45 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
46 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
48 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
49 * SUCH DAMAGE.
50 *
51 * $OpenBSD: ahci.c,v 1.147 2009/02/16 21:19:07 miod Exp $
52 */
53
54 #include "ahci.h"
55
56 static int ahci_vt8251_attach(device_t);
57 static int ahci_ati_sb600_attach(device_t);
58 static int ahci_nvidia_mcp_attach(device_t);
59 static int ahci_pci_attach(device_t);
60 static int ahci_pci_detach(device_t);
61
62 static const struct ahci_device ahci_devices[] = {
63 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
64 ahci_vt8251_attach, ahci_pci_detach, "ViaTech-VT8251-SATA" },
65 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA,
66 ahci_ati_sb600_attach, ahci_pci_detach, "ATI-SB600-SATA" },
67 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
68 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP65-SATA" },
69 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
70 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP67-SATA" },
71 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
72 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP77-SATA" },
73 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
74 ahci_nvidia_mcp_attach, ahci_pci_detach, "NVidia-MCP79-SATA" },
75 { 0, 0,
76 ahci_pci_attach, ahci_pci_detach, "AHCI-PCI-SATA" }
77 };
78
79 struct ahci_pciid {
80 uint16_t ahci_vid;
81 uint16_t ahci_did;
82 int ahci_rev;
83 };
84
85 static const struct ahci_pciid ahci_msi_blacklist[] = {
86 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA, -1 },
87 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_AHCI, -1 },
88
89 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121, -1 },
90 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145, -1 },
91
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa1 },
93 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa1 },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa1 },
95 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa1 },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa1 },
97 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa1 },
98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa1 },
99 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa1 },
100
101 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1, 0xa2 },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2, 0xa2 },
103 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3, 0xa2 },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4, 0xa2 },
105 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_5, 0xa2 },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_6, 0xa2 },
107 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_7, 0xa2 },
108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_8, 0xa2 }
109 };
110
111 static int ahci_msi_enable = 1;
112 TUNABLE_INT("hw.ahci.msi.enable", &ahci_msi_enable);
113
114 /*
115 * Match during probe and attach. The device does not yet have a softc.
116 */
117 const struct ahci_device *
118 ahci_lookup_device(device_t dev)
119 {
120 const struct ahci_device *ad;
121 u_int16_t vendor = pci_get_vendor(dev);
122 u_int16_t product = pci_get_device(dev);
123 u_int8_t class = pci_get_class(dev);
124 u_int8_t subclass = pci_get_subclass(dev);
125 u_int8_t progif = pci_read_config(dev, PCIR_PROGIF, 1);
126 int is_ahci;
127
128 /*
129 * Generally speaking if the pci device does not identify as
130 * AHCI we skip it.
131 */
132 if (class == PCIC_STORAGE && subclass == PCIS_STORAGE_SATA &&
133 progif == PCIP_STORAGE_SATA_AHCI_1_0) {
134 is_ahci = 1;
135 } else {
136 is_ahci = 0;
137 }
138
139 for (ad = &ahci_devices[0]; ad->ad_vendor; ++ad) {
140 if (ad->ad_vendor == vendor && ad->ad_product == product)
141 return (ad);
142 }
143
144 /*
145 * Last ad is the default match if the PCI device matches SATA.
146 */
147 if (is_ahci == 0)
148 ad = NULL;
149 return (ad);
150 }
151
152 /*
153 * Attach functions. They all eventually fall through to ahci_pci_attach().
154 */
155 static int
156 ahci_vt8251_attach(device_t dev)
157 {
158 struct ahci_softc *sc = device_get_softc(dev);
159
160 sc->sc_flags |= AHCI_F_NO_NCQ;
161 return (ahci_pci_attach(dev));
162 }
163
164 static int
165 ahci_ati_sb600_attach(device_t dev)
166 {
167 struct ahci_softc *sc = device_get_softc(dev);
168 pcireg_t magic;
169 u_int8_t subclass = pci_get_subclass(dev);
170 u_int8_t revid;
171
172 if (subclass == PCIS_STORAGE_IDE) {
173 revid = pci_read_config(dev, PCIR_REVID, 1);
174 magic = pci_read_config(dev, AHCI_PCI_ATI_SB600_MAGIC, 4);
175 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC,
176 magic | AHCI_PCI_ATI_SB600_LOCKED, 4);
177 pci_write_config(dev, PCIR_REVID,
178 (PCIC_STORAGE << 24) |
179 (PCIS_STORAGE_SATA << 16) |
180 (PCIP_STORAGE_SATA_AHCI_1_0 << 8) |
181 revid, 4);
182 pci_write_config(dev, AHCI_PCI_ATI_SB600_MAGIC, magic, 4);
183 }
184
185 sc->sc_flags |= AHCI_F_IGN_FR;
186 return (ahci_pci_attach(dev));
187 }
188
189 static int
190 ahci_nvidia_mcp_attach(device_t dev)
191 {
192 struct ahci_softc *sc = device_get_softc(dev);
193
194 sc->sc_flags |= AHCI_F_IGN_FR;
195 return (ahci_pci_attach(dev));
196 }
197
198 static int
199 ahci_pci_attach(device_t dev)
200 {
201 struct ahci_softc *sc = device_get_softc(dev);
202 struct ahci_port *ap;
203 const char *gen;
204 uint16_t vid, did;
205 u_int32_t pi, reg;
206 u_int32_t cap, cap2;
207 u_int32_t chip;
208 u_int irq_flags;
209 bus_addr_t addr;
210 int i, error, msi_enable, rev, fbs;
211 char revbuf[32];
212
213 if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
214 device_printf(dev, "BIOS disabled PCI interrupt, "
215 "re-enabling\n");
216 pci_write_config(dev, PCIR_COMMAND,
217 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
218 }
219
220 /*
221 * Chip quirks. Sigh. The AHCI spec is not in the least confusing
222 * when it comes to how the FR and CR bits work, but some AHCI
223 * chipsets (aka Marvell) either don't have the bits at all or they
224 * implement them poorly.
225 */
226 chip = ((uint16_t)pci_get_device(dev) << 16) |
227 (uint16_t)pci_get_vendor(dev);
228
229 switch(chip) {
230 case 0x91721b4b:
231 device_printf(dev,
232 "Enable 88SE9172 workarounds for broken chip\n");
233 sc->sc_flags |= AHCI_F_IGN_FR;
234 sc->sc_flags |= AHCI_F_IGN_CR;
235 break;
236 case 0x92301b4b:
237 device_printf(dev,
238 "Enable 88SE9230 workarounds for broken chip\n");
239 sc->sc_flags |= AHCI_F_CYCLE_FR;
240 break;
241 }
242
243 sc->sc_dev = dev;
244
245 /*
246 * Map the AHCI controller's IRQ and BAR(5) (hardware registers)
247 */
248 msi_enable = ahci_msi_enable;
249
250 vid = pci_get_vendor(dev);
251 did = pci_get_device(dev);
252 rev = pci_get_revid(dev);
253 for (i = 0; i < NELEM(ahci_msi_blacklist); ++i) {
254 const struct ahci_pciid *id = &ahci_msi_blacklist[i];
255
256 if (vid == id->ahci_vid && did == id->ahci_did) {
257 if (id->ahci_rev < 0 || id->ahci_rev == rev) {
258 msi_enable = 0;
259 break;
260 }
261 }
262 }
263
264 sc->sc_irq_type = pci_alloc_1intr(dev, msi_enable,
265 &sc->sc_rid_irq, &irq_flags);
266
267 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_rid_irq,
268 irq_flags);
269 if (sc->sc_irq == NULL) {
270 device_printf(dev, "unable to map interrupt\n");
271 ahci_pci_detach(dev);
272 return (ENXIO);
273 }
274
275 /*
276 * When mapping the register window store the tag and handle
277 * separately so we can use the tag with per-port bus handle
278 * sub-spaces.
279 */
280 sc->sc_rid_regs = PCIR_BAR(5);
281 sc->sc_regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
282 &sc->sc_rid_regs, RF_ACTIVE);
283 if (sc->sc_regs == NULL) {
284 device_printf(dev, "unable to map registers\n");
285 ahci_pci_detach(dev);
286 return (ENXIO);
287 }
288 sc->sc_iot = rman_get_bustag(sc->sc_regs);
289 sc->sc_ioh = rman_get_bushandle(sc->sc_regs);
290
291 /*
292 * Initialize the chipset and then set the interrupt vector up
293 */
294 error = ahci_init(sc);
295 if (error) {
296 ahci_pci_detach(dev);
297 return (ENXIO);
298 }
299
300 /*
301 * Get the AHCI capabilities and max number of concurrent
302 * command tags and set up the DMA tags. Adjust the saved
303 * sc_cap according to override flags.
304 */
305 cap = sc->sc_cap = ahci_read(sc, AHCI_REG_CAP);
306 if (sc->sc_flags & AHCI_F_NO_NCQ)
307 sc->sc_cap &= ~AHCI_REG_CAP_SNCQ;
308 if (sc->sc_flags & AHCI_F_FORCE_FBSS)
309 sc->sc_cap |= AHCI_REG_CAP_FBSS;
310
311 /*
312 * We assume at least 4 commands.
313 */
314 sc->sc_ncmds = AHCI_REG_CAP_NCS(cap);
315 if (sc->sc_ncmds < 4) {
316 device_printf(dev, "NCS must probe a value >= 4\n");
317 ahci_pci_detach(dev);
318 return (ENXIO);
319 }
320
321 addr = (cap & AHCI_REG_CAP_S64A) ?
322 BUS_SPACE_MAXADDR : BUS_SPACE_MAXADDR_32BIT;
323
324 /*
325 * DMA tags for allocation of DMA memory buffers, lists, and so
326 * forth. These are typically per-port.
327 *
328 * When FIS-based switching is supported we need a rfis for
329 * each target (4K total). The spec also requires 4K alignment
330 * for this case.
331 */
332 fbs = (cap & AHCI_REG_CAP_FBSS) ? 16 : 1;
333 error = 0;
334
335 sc->sc_rfis_size = sizeof(struct ahci_rfis) * fbs;
336
337 error += bus_dma_tag_create(
338 NULL, /* parent tag */
339 sc->sc_rfis_size, /* alignment */
340 PAGE_SIZE, /* boundary */
341 addr, /* loaddr? */
342 BUS_SPACE_MAXADDR, /* hiaddr */
343 NULL, /* filter */
344 NULL, /* filterarg */
345 sc->sc_rfis_size, /* [max]size */
346 1, /* maxsegs */
347 sc->sc_rfis_size, /* maxsegsz */
348 0, /* flags */
349 &sc->sc_tag_rfis); /* return tag */
350
351 sc->sc_cmdlist_size = sc->sc_ncmds * sizeof(struct ahci_cmd_hdr);
352
353 error += bus_dma_tag_create(
354 NULL, /* parent tag */
355 32, /* alignment */
356 4096 * 1024, /* boundary */
357 addr, /* loaddr? */
358 BUS_SPACE_MAXADDR, /* hiaddr */
359 NULL, /* filter */
360 NULL, /* filterarg */
361 sc->sc_cmdlist_size,
362 1, /* maxsegs */
363 sc->sc_cmdlist_size,
364 0, /* flags */
365 &sc->sc_tag_cmdh); /* return tag */
366
367 /*
368 * NOTE: ahci_cmd_table is sized to a power of 2
369 */
370 error += bus_dma_tag_create(
371 NULL, /* parent tag */
372 sizeof(struct ahci_cmd_table), /* alignment */
373 4096 * 1024, /* boundary */
374 addr, /* loaddr? */
375 BUS_SPACE_MAXADDR, /* hiaddr */
376 NULL, /* filter */
377 NULL, /* filterarg */
378 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
379 1, /* maxsegs */
380 sc->sc_ncmds * sizeof(struct ahci_cmd_table),
381 0, /* flags */
382 &sc->sc_tag_cmdt); /* return tag */
383
384 /*
385 * The data tag is used for later dmamaps and not immediately
386 * allocated.
387 */
388 error += bus_dma_tag_create(
389 NULL, /* parent tag */
390 4, /* alignment */
391 0, /* boundary */
392 addr, /* loaddr? */
393 BUS_SPACE_MAXADDR, /* hiaddr */
394 NULL, /* filter */
395 NULL, /* filterarg */
396 4096 * 1024, /* maxiosize */
397 AHCI_MAX_PRDT, /* maxsegs */
398 65536, /* maxsegsz */
399 0, /* flags */
400 &sc->sc_tag_data); /* return tag */
401
402 if (error) {
403 device_printf(dev, "unable to create dma tags\n");
404 ahci_pci_detach(dev);
405 return (ENXIO);
406 }
407
408 switch (cap & AHCI_REG_CAP_ISS) {
409 case AHCI_REG_CAP_ISS_G1:
410 gen = "1 (1.5Gbps)";
411 break;
412 case AHCI_REG_CAP_ISS_G2:
413 gen = "2 (3Gbps)";
414 break;
415 case AHCI_REG_CAP_ISS_G3:
416 gen = "3 (6Gbps)";
417 break;
418 default:
419 gen = "unknown";
420 break;
421 }
422
423 /* check the revision */
424 reg = ahci_read(sc, AHCI_REG_VS);
425
426 if (reg & 0x0000FF) {
427 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d.%d",
428 (reg >> 16), (uint8_t)(reg >> 8), (uint8_t)reg);
429 } else {
430 ksnprintf(revbuf, sizeof(revbuf), "AHCI %d.%d",
431 (reg >> 16), (uint8_t)(reg >> 8));
432 }
433 sc->sc_vers = reg;
434
435 if (reg >= AHCI_REG_VS_1_3) {
436 cap2 = ahci_read(sc, AHCI_REG_CAP2);
437 device_printf(dev,
438 "%s cap 0x%b cap2 0x%b, %d ports, "
439 "%d tags/port, gen %s\n",
440 revbuf,
441 cap, AHCI_FMT_CAP,
442 cap2, AHCI_FMT_CAP2,
443 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
444 } else {
445 cap2 = 0;
446 device_printf(dev,
447 "%s cap 0x%b, %d ports, "
448 "%d tags/port, gen %s\n",
449 revbuf,
450 cap, AHCI_FMT_CAP,
451 AHCI_REG_CAP_NP(cap), sc->sc_ncmds, gen);
452 }
453 sc->sc_cap2 = cap2;
454
455 pi = ahci_read(sc, AHCI_REG_PI);
456 DPRINTF(AHCI_D_VERBOSE, "%s: ports implemented: 0x%08x\n",
457 DEVNAME(sc), pi);
458
459 sc->sc_ipm_disable = AHCI_PREG_SCTL_IPM_NOPARTIAL |
460 AHCI_PREG_SCTL_IPM_NOSLUMBER;
461 if (sc->sc_cap2 & AHCI_REG_CAP2_SDS)
462 sc->sc_ipm_disable |= AHCI_PREG_SCTL_IPM_NODEVSLP;
463
464 #ifdef AHCI_COALESCE
465 /* Naive coalescing support - enable for all ports. */
466 if (cap & AHCI_REG_CAP_CCCS) {
467 u_int16_t ccc_timeout = 20;
468 u_int8_t ccc_numcomplete = 12;
469 u_int32_t ccc_ctl;
470
471 /* disable coalescing during reconfiguration. */
472 ccc_ctl = ahci_read(sc, AHCI_REG_CCC_CTL);
473 ccc_ctl &= ~0x00000001;
474 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
475
476 sc->sc_ccc_mask = 1 << AHCI_REG_CCC_CTL_INT(ccc_ctl);
477 if (pi & sc->sc_ccc_mask) {
478 /* A conflict with the implemented port list? */
479 printf("%s: coalescing interrupt/implemented port list "
480 "conflict, PI: %08x, ccc_mask: %08x\n",
481 DEVNAME(sc), pi, sc->sc_ccc_mask);
482 sc->sc_ccc_mask = 0;
483 goto noccc;
484 }
485
486 /* ahci_port_start will enable each port when it starts. */
487 sc->sc_ccc_ports = pi;
488 sc->sc_ccc_ports_cur = 0;
489
490 /* program thresholds and enable overall coalescing. */
491 ccc_ctl &= ~0xffffff00;
492 ccc_ctl |= (ccc_timeout << 16) | (ccc_numcomplete << 8);
493 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl);
494 ahci_write(sc, AHCI_REG_CCC_PORTS, 0);
495 ahci_write(sc, AHCI_REG_CCC_CTL, ccc_ctl | 1);
496 }
497 noccc:
498 #endif
499 /*
500 * Allocate per-port resources
501 *
502 * Ignore attach errors, leave the port intact for
503 * rescan and continue the loop.
504 *
505 * All ports are attached in parallel but the CAM scan-bus
506 * is held up until all ports are attached so we get a deterministic
507 * order.
508 */
509 for (i = 0; error == 0 && i < AHCI_MAX_PORTS; i++) {
510 if ((pi & (1 << i)) == 0) {
511 /* dont allocate stuff if the port isnt implemented */
512 continue;
513 }
514 error = ahci_port_alloc(sc, i);
515 }
516
517 /*
518 * Setup the interrupt vector and enable interrupts. Note that
519 * since the irq may be shared we do not set it up until we are
520 * ready to go.
521 */
522 if (error == 0) {
523 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
524 ahci_intr, sc,
525 &sc->sc_irq_handle, NULL);
526 }
527
528 if (error) {
529 device_printf(dev, "unable to install interrupt\n");
530 ahci_pci_detach(dev);
531 return (ENXIO);
532 }
533
534 /*
535 * Before marking the sc as good, which allows the interrupt
536 * subsystem to operate on the ports, wait for all the port threads
537 * to get past their initial pre-probe init. Otherwise an interrupt
538 * may try to process the port before it has been initialized.
539 */
540 for (i = 0; i < AHCI_MAX_PORTS; i++) {
541 if ((ap = sc->sc_ports[i]) != NULL) {
542 while (ap->ap_signal & AP_SIGF_THREAD_SYNC)
543 tsleep(&ap->ap_signal, 0, "ahprb1", hz);
544 }
545 }
546
547 /*
548 * Master interrupt enable, and call ahci_intr() in case we race
549 * our AHCI_F_INT_GOOD flag.
550 */
551 crit_enter();
552 ahci_write(sc, AHCI_REG_GHC, AHCI_REG_GHC_AE | AHCI_REG_GHC_IE);
553 sc->sc_flags |= AHCI_F_INT_GOOD;
554 crit_exit();
555 ahci_intr(sc);
556
557 /*
558 * All ports are probing in parallel. Wait for them to finish
559 * and then issue the cam attachment and bus scan serially so
560 * the 'da' assignments are deterministic.
561 */
562 for (i = 0; i < AHCI_MAX_PORTS; i++) {
563 if ((ap = sc->sc_ports[i]) != NULL) {
564 while (ap->ap_signal & AP_SIGF_INIT)
565 tsleep(&ap->ap_signal, 0, "ahprb2", hz);
566 ahci_os_lock_port(ap);
567 if (ahci_cam_attach(ap) == 0) {
568 ahci_cam_changed(ap, NULL, -1);
569 ahci_os_unlock_port(ap);
570 while ((ap->ap_flags & AP_F_SCAN_COMPLETED) == 0) {
571 tsleep(&ap->ap_flags, 0, "ahprb2", hz);
572 }
573 } else {
574 ahci_os_unlock_port(ap);
575 }
576 }
577 }
578
579 return(0);
580 }
581
582 /*
583 * Device unload / detachment
584 */
585 static int
586 ahci_pci_detach(device_t dev)
587 {
588 struct ahci_softc *sc = device_get_softc(dev);
589 struct ahci_port *ap;
590 int i;
591
592 /*
593 * Disable the controller and de-register the interrupt, if any.
594 *
595 * XXX interlock last interrupt?
596 */
597 sc->sc_flags &= ~AHCI_F_INT_GOOD;
598 if (sc->sc_regs)
599 ahci_write(sc, AHCI_REG_GHC, 0);
600
601 if (sc->sc_irq_handle) {
602 bus_teardown_intr(dev, sc->sc_irq, sc->sc_irq_handle);
603 sc->sc_irq_handle = NULL;
604 }
605
606 /*
607 * Free port structures and DMA memory
608 */
609 for (i = 0; i < AHCI_MAX_PORTS; i++) {
610 ap = sc->sc_ports[i];
611 if (ap) {
612 ahci_cam_detach(ap);
613 ahci_port_free(sc, i);
614 }
615 }
616
617 /*
618 * Clean up the bus space
619 */
620 if (sc->sc_irq) {
621 bus_release_resource(dev, SYS_RES_IRQ,
622 sc->sc_rid_irq, sc->sc_irq);
623 sc->sc_irq = NULL;
624 }
625
626 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI)
627 pci_release_msi(dev);
628
629 if (sc->sc_regs) {
630 bus_release_resource(dev, SYS_RES_MEMORY,
631 sc->sc_rid_regs, sc->sc_regs);
632 sc->sc_regs = NULL;
633 }
634
635 if (sc->sc_tag_rfis) {
636 bus_dma_tag_destroy(sc->sc_tag_rfis);
637 sc->sc_tag_rfis = NULL;
638 }
639 if (sc->sc_tag_cmdh) {
640 bus_dma_tag_destroy(sc->sc_tag_cmdh);
641 sc->sc_tag_cmdh = NULL;
642 }
643 if (sc->sc_tag_cmdt) {
644 bus_dma_tag_destroy(sc->sc_tag_cmdt);
645 sc->sc_tag_cmdt = NULL;
646 }
647 if (sc->sc_tag_data) {
648 bus_dma_tag_destroy(sc->sc_tag_data);
649 sc->sc_tag_data = NULL;
650 }
651
652 return (0);
653 }
DragonFly BSD