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kernel - Rewrite the callout_*() API
[dragonfly.git] / sys / dev / disk / nata / chipsets / ata-intel.c
blob3cc9695f588c136da734bbe6ec5b28eddb91f6ff
1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /* local prototypes */
28 static int ata_intel_chipinit(device_t dev);
29 static int ata_intel_allocate(device_t dev);
30 static void ata_intel_reset(device_t dev);
31 static void ata_intel_old_setmode(device_t dev, int mode);
32 static void ata_intel_new_setmode(device_t dev, int mode);
33 static void ata_intel_sata_setmode(device_t dev, int mode);
34 static int ata_intel_31244_allocate(device_t dev);
35 static int ata_intel_31244_status(device_t dev);
36 static void ata_intel_31244_tf_write(struct ata_request *request);
37 static void ata_intel_31244_reset(device_t dev);
38
39 /* misc defines */
40 #define INTEL_AHCI 1
41
42 /*
43 * Intel chipset support functions
44 */
45 int
46 ata_intel_ident(device_t dev)
47 {
48 struct ata_pci_controller *ctlr = device_get_softc(dev);
49 static const struct ata_chip_id ids[] =
50 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" },
51 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" },
52 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" },
53 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
54 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
55 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" },
56 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" },
57 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" },
58 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" },
59 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" },
60 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" },
61 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" },
62 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" },
63 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" },
64 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" },
65 { ATA_I82801EB_S1, 0, 0, 2, ATA_SA150, "ICH5" },
66 { ATA_I82801EB_R1, 0, 0, 2, ATA_SA150, "ICH5" },
67 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" },
68 { ATA_I6300ESB_S1, 0, 0, 2, ATA_SA150, "6300ESB" },
69 { ATA_I6300ESB_R1, 0, 0, 2, ATA_SA150, "6300ESB" },
70 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
71 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
72 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
73 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
74 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
75 { ATA_I82801GB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
76 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
77 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
78 { ATA_I82801GBM_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
79 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
80 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
81 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
82 { ATA_I63XXESB2_S1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
83 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
84 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
85 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
86 { ATA_I82801HB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
87 { ATA_I82801HB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
88 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
89 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
90 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
91 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
92 { ATA_I82801HBM_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
93 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
94 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
95 { ATA_I82801IB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
96 { ATA_I82801IB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
97 { ATA_I82801IB_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
98 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
99 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
100 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
101 { ATA_I82801JIB_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
102 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
103 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
104 { ATA_I82801JIB_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
105 { ATA_I82801JD_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
106 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
107 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
108 { ATA_I82801JD_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
109 { ATA_I82801JI_S1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
110 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
111 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
112 { ATA_I82801JI_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
113 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
114 { 0, 0, 0, 0, 0, 0}};
115
116 if (pci_get_vendor(dev) != ATA_INTEL_ID)
117 return ENXIO;
118
119 if (!(ctlr->chip = ata_match_chip(dev, ids)))
120 return ENXIO;
121
122 ata_set_desc(dev);
123 ctlr->chipinit = ata_intel_chipinit;
124 return 0;
125 }
126
127 static int
128 ata_intel_chipinit(device_t dev)
129 {
130 struct ata_pci_controller *ctlr = device_get_softc(dev);
131
132 if (ata_setup_interrupt(dev, ata_generic_intr))
133 return ENXIO;
134
135 /* good old PIIX needs special treatment (not implemented) */
136 if (ctlr->chip->chipid == ATA_I82371FB) {
137 ctlr->setmode = ata_intel_old_setmode;
138 }
139
140 /* the intel 31244 needs special care if in DPA mode */
141 else if (ctlr->chip->chipid == ATA_I31244) {
142 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
143 ctlr->r_type2 = SYS_RES_MEMORY;
144 ctlr->r_rid2 = PCIR_BAR(0);
145 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
146 &ctlr->r_rid2,
147 RF_ACTIVE))) {
148 ata_teardown_interrupt(dev);
149 return ENXIO;
150 }
151 ctlr->channels = 4;
152 ctlr->allocate = ata_intel_31244_allocate;
153 ctlr->reset = ata_intel_31244_reset;
154 }
155 ctlr->setmode = ata_sata_setmode;
156 }
157
158 /* non SATA intel chips goes here */
159 else if (ctlr->chip->max_dma < ATA_SA150) {
160 ctlr->channels = ctlr->chip->cfg2;
161 ctlr->allocate = ata_intel_allocate;
162 ctlr->setmode = ata_intel_new_setmode;
163 }
164
165 /* SATA parts can be either compat or AHCI */
166 else {
167 /* force all ports active "the legacy way" */
168 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
169
170 ctlr->allocate = ata_intel_allocate;
171 ctlr->reset = ata_intel_reset;
172
173 /*
174 * if we have AHCI capability and AHCI or RAID mode enabled
175 * in BIOS we try for AHCI mode
176 */
177 if ((ctlr->chip->cfg1 == INTEL_AHCI) &&
178 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
179 (ata_ahci_chipinit(dev) != ENXIO))
180 return 0;
181
182 /* if BAR(5) is IO it should point to SATA interface registers */
183 ctlr->r_type2 = SYS_RES_IOPORT;
184 ctlr->r_rid2 = PCIR_BAR(5);
185 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
186 &ctlr->r_rid2, RF_ACTIVE)))
187 ctlr->setmode = ata_intel_sata_setmode;
188 else
189 ctlr->setmode = ata_sata_setmode;
190
191 /* enable PCI interrupt */
192 pci_write_config(dev, PCIR_COMMAND,
193 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
194 }
195 return 0;
196 }
197
198 static int
199 ata_intel_allocate(device_t dev)
200 {
201 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
202 struct ata_channel *ch = device_get_softc(dev);
203
204 /* setup the usual register normal pci style */
205 if (ata_pci_allocate(dev))
206 return ENXIO;
207
208 /* if r_res2 is valid it points to SATA interface registers */
209 if (ctlr->r_res2) {
210 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
211 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
212 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
213 ch->r_io[ATA_IDX_DATA].offset = 0x04;
214 }
215
216 ch->flags |= ATA_ALWAYS_DMASTAT;
217 return 0;
218 }
219
220 static void
221 ata_intel_reset(device_t dev)
222 {
223 device_t parent = device_get_parent(dev);
224 struct ata_pci_controller *ctlr = device_get_softc(parent);
225 struct ata_channel *ch = device_get_softc(dev);
226 int mask, timeout;
227
228 /* ICH6 & ICH7 in compat mode has 4 SATA ports as master/slave on 2 ch's */
229 if (ctlr->chip->cfg1) {
230 mask = (0x0005 << ch->unit);
231 }
232 else {
233 /* ICH5 in compat mode has SATA ports as master/slave on 1 channel */
234 if (pci_read_config(parent, 0x90, 1) & 0x04)
235 mask = 0x0003;
236 else {
237 mask = (0x0001 << ch->unit);
238 /* XXX SOS should be in intel_allocate if we grow it */
239 ch->flags |= ATA_NO_SLAVE;
240 }
241 }
242 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) & ~mask, 2);
243 DELAY(10);
244 pci_write_config(parent, 0x92, pci_read_config(parent, 0x92, 2) | mask, 2);
245
246 /* wait up to 1 sec for "connect well" */
247 for (timeout = 0; timeout < 100 ; timeout++) {
248 if (((pci_read_config(parent, 0x92, 2) & (mask << 4)) == (mask << 4)) &&
249 (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
250 break;
251 ata_udelay(10000);
252 }
253 ata_generic_reset(dev);
254 }
255
256 static void
257 ata_intel_old_setmode(device_t dev, int mode)
258 {
259 /* NOT YET */
260 }
261
262 static void
263 ata_intel_new_setmode(device_t dev, int mode)
264 {
265 device_t gparent = GRANDPARENT(dev);
266 struct ata_pci_controller *ctlr = device_get_softc(gparent);
267 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
268 struct ata_device *atadev = device_get_softc(dev);
269 int devno = (ch->unit << 1) + atadev->unit;
270 u_int32_t reg40 = pci_read_config(gparent, 0x40, 4);
271 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
272 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
273 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
274 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
275 u_int32_t mask40 = 0, new40 = 0;
276 u_int8_t mask44 = 0, new44 = 0;
277 int error;
278 static const uint8_t timings[] =
279 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23,
280 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
281 /* PIO0 PIO1 PIO2 PIO3 PIO4 WDMA0 WDMA1 WDMA2 */
282 /* UDMA0 UDMA1 UDMA2 UDMA3 UDMA4 UDMA5 UDMA6 */
283 static const uint8_t utimings[] =
284 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
285
286 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
287
288 if ( mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
289 ata_print_cable(dev, "controller");
290 mode = ATA_UDMA2;
291 }
292
293 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
294
295 if (bootverbose)
296 device_printf(dev, "%ssetting %s on %s chip\n",
297 (error) ? "FAILURE " : "",
298 ata_mode2str(mode), ctlr->chip->text);
299 if (!error) {
300 if (mode >= ATA_UDMA0) {
301 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
302 pci_write_config(gparent, 0x4a,
303 (reg4a & ~(0x3 << (devno << 2))) |
304 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
305 }
306 else {
307 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
308 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
309 }
310 reg54 |= 0x0400; /* set vendor specific bit */
311 if (mode >= ATA_UDMA3)
312 reg54 |= (0x1 << devno);
313 else
314 reg54 &= ~(0x1 << devno);
315 if (mode >= ATA_UDMA5)
316 reg54 |= (0x1000 << devno);
317 else
318 reg54 &= ~(0x1000 << devno);
319
320 pci_write_config(gparent, 0x54, reg54, 2);
321
322 reg40 &= ~0x00ff00ff;
323 reg40 |= 0x40774077;
324
325 /* Modify reg40 according to the table */
326 if (atadev->unit == ATA_MASTER) {
327 mask40 = 0x3300;
328 new40 = timings[ata_mode2idx(mode)] << 8;
329 }
330 else {
331 mask44 = 0x0f;
332 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
333 (timings[ata_mode2idx(mode)] & 0x03);
334 }
335
336 /* Primary or Secondary controller */
337 if (ch->unit) {
338 mask40 <<= 16;
339 new40 <<= 16;
340 mask44 <<= 4;
341 new44 <<= 4;
342 }
343 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
344 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
345
346 atadev->mode = mode;
347 }
348 }
349
350 static void
351 ata_intel_sata_setmode(device_t dev, int mode)
352 {
353 struct ata_device *atadev = device_get_softc(dev);
354
355 if (atadev->param.satacapabilities != 0x0000 &&
356 atadev->param.satacapabilities != 0xffff) {
357
358 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
359 int devno = (ch->unit << 1) + atadev->unit;
360
361 /* on some drives we need to set the transfer mode */
362 ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0,
363 ata_limit_mode(dev, mode, ATA_UDMA6));
364
365 /* set ATA_SSTATUS register offset */
366 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, devno * 0x100);
367
368 /* query SATA STATUS for the speed */
369 if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) ==
370 ATA_SS_CONWELL_GEN2)
371 atadev->mode = ATA_SA300;
372 else
373 atadev->mode = ATA_SA150;
374 }
375 else {
376 mode = ata_limit_mode(dev, mode, ATA_UDMA5);
377 if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode))
378 atadev->mode = mode;
379 }
380 }
381
382 static int
383 ata_intel_31244_allocate(device_t dev)
384 {
385 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
386 struct ata_channel *ch = device_get_softc(dev);
387 int i;
388 int ch_offset;
389
390 ch_offset = 0x200 + ch->unit * 0x200;
391
392 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
393 ch->r_io[i].res = ctlr->r_res2;
394
395 /* setup ATA registers */
396 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
397 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
398 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
399 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
400 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
401 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
402 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
403 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
404 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
405 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
406 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
407 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
408
409 /* setup DMA registers */
410 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
411 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
412 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
413
414 /* setup SATA registers */
415 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
416 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
417 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
418
419 ch->flags |= ATA_NO_SLAVE;
420 ata_pci_hw(dev);
421 ch->hw.status = ata_intel_31244_status;
422 ch->hw.tf_write = ata_intel_31244_tf_write;
423
424 /* enable PHY state change interrupt */
425 ATA_OUTL(ctlr->r_res2, 0x4,
426 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
427 return 0;
428 }
429
430 static int
431 ata_intel_31244_status(device_t dev)
432 {
433 /* do we have any PHY events ? */
434 ata_sata_phy_check_events(dev);
435
436 /* any drive action to take care of ? */
437 return ata_pci_status(dev);
438 }
439
440 static void
441 ata_intel_31244_tf_write(struct ata_request *request)
442 {
443 struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
444 struct ata_device *atadev = device_get_softc(request->dev);
445
446 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
447 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
448 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
449 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
450 (request->u.ata.lba & 0x00ff));
451 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
452 ((request->u.ata.lba >> 8) & 0x00ff));
453 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
454 ((request->u.ata.lba >> 16) & 0x00ff));
455 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit));
456 }
457 else {
458 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
459 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
460 if (atadev->flags & ATA_D_USE_CHS) {
461 int heads, sectors;
462
463 if (atadev->param.atavalid & ATA_FLAG_54_58) {
464 heads = atadev->param.current_heads;
465 sectors = atadev->param.current_sectors;
466 }
467 else {
468 heads = atadev->param.heads;
469 sectors = atadev->param.sectors;
470 }
471 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
472 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
473 (request->u.ata.lba / (sectors * heads)));
474 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
475 (request->u.ata.lba / (sectors * heads)) >> 8);
476 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) |
477 (((request->u.ata.lba% (sectors * heads)) /
478 sectors) & 0xf));
479 }
480 else {
481 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
482 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
483 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
484 ATA_IDX_OUTB(ch, ATA_DRIVE,
485 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) |
486 ((request->u.ata.lba >> 24) & 0x0f));
487 }
488 }
489 }
490
491 static void
492 ata_intel_31244_reset(device_t dev)
493 {
494 if (ata_sata_phy_reset(dev))
495 ata_generic_reset(dev);
496 }
DragonFly BSD