sys/dev/disk/nata/chipsets/ata-ati.c

   1 /*-
   2  * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification, immediately at the beginning of the file.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26
  27 /* local prototypes */
  28 static int ata_ati_chipinit(device_t dev);
  29 static void ata_ati_setmode(device_t dev, int mode);
  30
  31 /* misc defines */
  32 #undef SII_MEMIO
  33 #define SII_MEMIO       1       /* must match ata_siliconimage.c's definition */
  34 #define SII_BUG         0x04    /* must match ata_siliconimage.c's definition */
  35
  36 #define ATI_SATA        SII_MEMIO
  37 #define ATI_PATA        0x02
  38 #define ATI_AHCI        0x04
  39
  40 /*
  41  * ATI chipset support functions
  42  */
  43 int
  44 ata_ati_ident(device_t dev)
  45 {
  46     struct ata_pci_controller *ctlr = device_get_softc(dev);
  47     static const struct ata_chip_id ids[] =
  48     {{ ATA_ATI_IXP200,    0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" },
  49      { ATA_ATI_IXP300,    0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" },
  50      { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" },
  51      { ATA_ATI_IXP400,    0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" },
  52      { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" },
  53      { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" },
  54      { ATA_ATI_IXP600,    0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" },
  55      { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" },
  56      { ATA_ATI_IXP600_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" },
  57      { ATA_ATI_IXP700,    0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" },
  58      { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
  59      { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
  60      { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
  61      { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" },
  62      { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
  63      { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" },
  64      { 0, 0, 0, 0, 0, 0}};
  65
  66     if (pci_get_vendor(dev) != ATA_ATI_ID)
  67         return ENXIO;
  68
  69     if (!(ctlr->chip = ata_match_chip(dev, ids)))
  70         return ENXIO;
  71
  72     ata_set_desc(dev);
  73
  74     switch (ctlr->chip->cfg1) {
  75     case ATI_PATA:
  76         ctlr->chipinit = ata_ati_chipinit;
  77         break;
  78     case ATI_SATA:
  79         /*
  80          * the ATI SATA controller is actually a SiI 3112 controller
  81          */
  82         ctlr->chipinit = ata_sii_chipinit;
  83         break;
  84     case ATI_AHCI:
  85         if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
  86                 ctlr->chipinit = ata_ahci_chipinit;
  87         else
  88                 ctlr->chipinit = ata_ati_chipinit;
  89         break;
  90     }
  91     return 0;
  92 }
  93
  94 static int
  95 ata_ati_chipinit(device_t dev)
  96 {
  97     struct ata_pci_controller *ctlr = device_get_softc(dev);
  98
  99     if (ata_setup_interrupt(dev, ata_generic_intr))
 100         return ENXIO;
 101
 102     /* IXP600 & IXP700 only have 1 PATA channel */
 103     if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
 104         (ctlr->chip->chipid == ATA_ATI_IXP700))
 105         ctlr->channels = 1;
 106
 107     /* The SB600 needs special treatment. */
 108     if (ctlr->chip->cfg1 & ATI_AHCI) {
 109         /* Check if the chip is configured as an AHCI part. */
 110         if ((pci_get_subclass(dev) == PCIS_STORAGE_SATA) &&
 111             (pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_STORAGE_SATA_AHCI_1_0)) {
 112             ctlr->setmode = ata_sata_setmode;
 113             if (ata_ahci_chipinit(dev) != ENXIO)
 114                 return 0;
 115         }
 116     }
 117
 118     ctlr->setmode = ata_ati_setmode;
 119     return 0;
 120 }
 121
 122 static void
 123 ata_ati_setmode(device_t dev, int mode)
 124 {
 125         device_t gparent = GRANDPARENT(dev);
 126         struct ata_pci_controller *ctlr = device_get_softc(gparent);
 127         struct ata_channel *ch = device_get_softc(device_get_parent(dev));
 128         struct ata_device *atadev = device_get_softc(dev);
 129         int devno = (ch->unit << 1) + atadev->unit;
 130         int offset = (devno ^ 0x01) << 3;
 131         int error;
 132         int piomode;
 133         static const uint8_t piotimings[] =
 134                             { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
 135                               0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
 136         static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
 137
 138     mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
 139
 140     mode = ata_check_80pin(dev, mode);
 141
 142     error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
 143
 144     if (bootverbose)
 145         device_printf(dev, "%ssetting %s on %s chip\n",
 146                       (error) ? "FAILURE " : "",
 147                       ata_mode2str(mode), ctlr->chip->text);
 148     if (!error) {
 149         if (mode >= ATA_UDMA0) {
 150             /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
 151             pci_write_config(gparent, 0x56,
 152                              (pci_read_config(gparent, 0x56, 2) &
 153                               ~(0xf << (devno << 2))) |
 154                              ((mode & ATA_MODE_MASK) << (devno << 2)), 2);
 155             pci_write_config(gparent, 0x54,
 156                              pci_read_config(gparent, 0x54, 1) |
 157                              (0x01 << devno), 1);
 158             pci_write_config(gparent, 0x44,
 159                              (pci_read_config(gparent, 0x44, 4) &
 160                               ~(0xff << offset)) |
 161                              (dmatimings[2] << offset), 4);
 162             piomode = ATA_PIO4;
 163         } else if (mode >= ATA_WDMA0) {
 164             /* Disable UDMA, set WDMA mode and timings, calculate PIO. */
 165             pci_write_config(gparent, 0x54,
 166                              pci_read_config(gparent, 0x54, 1) &
 167                               ~(0x01 << devno), 1);
 168             pci_write_config(gparent, 0x44,
 169                              (pci_read_config(gparent, 0x44, 4) &
 170                               ~(0xff << offset)) |
 171                              (dmatimings[mode & ATA_MODE_MASK] << offset), 4);
 172             piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
 173                 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
 174         } else {
 175             /* Disable UDMA, set requested PIO. */
 176             pci_write_config(gparent, 0x54,
 177                              pci_read_config(gparent, 0x54, 1) &
 178                              ~(0x01 << devno), 1);
 179             piomode = mode;
 180         }
 181         /* Set PIO mode and timings, calculated above. */
 182         pci_write_config(gparent, 0x4a,
 183                          (pci_read_config(gparent, 0x4a, 2) &
 184                           ~(0xf << (devno << 2))) |
 185                          ((piomode - ATA_PIO0) << (devno<<2)),2);
 186         pci_write_config(gparent, 0x40,
 187                          (pci_read_config(gparent, 0x40, 4) &
 188                           ~(0xff << offset)) |
 189                          (piotimings[ata_mode2idx(piomode)] << offset), 4);
 190         atadev->mode = mode;
 191     }
 192 }