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HAMMER 60I/Many: Mirroring
[dragonfly.git] / sys / platform / pc32 / include / cronyx.h
blob21e5a48c2c5e22b8f9da857a104331dda9c9d97f
1 /*
2 * Defines for Cronyx-Sigma adapter driver.
3 *
4 * Copyright (C) 1994 Cronyx Ltd.
5 * Author: Serge Vakulenko, <vak@zebub.msk.su>
6 *
7 * This software is distributed with NO WARRANTIES, not even the implied
8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
9 *
10 * Authors grant any other persons or organizations permission to use
11 * or modify this software as long as this message is kept with the software,
12 * all derivative works or modified versions.
13 *
14 * Version 1.9, Wed Oct 4 18:58:15 MSK 1995
15 *
16 * $FreeBSD: src/sys/i386/include/cronyx.h,v 1.9 1999/12/29 04:33:00 peter Exp $
17 * $DragonFly: src/sys/platform/pc32/include/cronyx.h,v 1.3 2003/06/28 04:16:03 dillon Exp $
18 */
19
20 #ifndef _MACHINE_CRONYX_H_
21 #define _MACHINE_CRONYX_H_
22
23 /*
24 * Asynchronous channel mode -------------------------------------------------
25 */
26
27 /* Parity */
28 #define PAR_EVEN 0 /* even parity */
29 #define PAR_ODD 1 /* odd parity */
30
31 /* Parity mode */
32 #define PARM_NOPAR 0 /* no parity */
33 #define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */
34 #define PARM_NORMAL 2 /* normal parity */
35
36 /* Flow control transparency mode */
37 #define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */
38 #define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */
39
40 /* Stop bit length */
41 #define STOPB_1 2 /* 1 stop bit */
42 #define STOPB_15 3 /* 1.5 stop bits */
43 #define STOPB_2 4 /* 2 stop bits */
44
45 /* Action on break condition */
46 #define BRK_INTR 0 /* generate an exception interrupt */
47 #define BRK_NULL 1 /* translate to a NULL character */
48 #define BRK_RESERVED 2 /* reserved */
49 #define BRK_DISCARD 3 /* discard character */
50
51 /* Parity/framing error actions */
52 #define PERR_INTR 0 /* generate an exception interrupt */
53 #define PERR_NULL 1 /* translate to a NULL character */
54 #define PERR_IGNORE 2 /* ignore error; char passed as good data */
55 #define PERR_DISCARD 3 /* discard error character */
56 #define PERR_FFNULL 5 /* translate to FF NULL char */
57
58 typedef struct { /* async channel option register 1 */
59 unsigned charlen : 4; /* character length, 5..8 */
60 unsigned ignpar : 1; /* ignore parity */
61 unsigned parmode : 2; /* parity mode */
62 unsigned parity : 1; /* parity */
63 } cx_cor1_async_t;
64
65 typedef struct { /* async channel option register 2 */
66 unsigned dsrae : 1; /* DSR automatic enable */
67 unsigned ctsae : 1; /* CTS automatic enable */
68 unsigned rtsao : 1; /* RTS automatic output enable */
69 unsigned rlm : 1; /* remote loopback mode enable */
70 unsigned zero : 1;
71 unsigned etc : 1; /* embedded transmitter cmd enable */
72 unsigned ixon : 1; /* in-band XON/XOFF enable */
73 unsigned ixany : 1; /* XON on any character */
74 } cx_cor2_async_t;
75
76 typedef struct { /* async channel option register 3 */
77 unsigned stopb : 3; /* stop bit length */
78 unsigned zero : 1;
79 unsigned scde : 1; /* special char detection enable */
80 unsigned flowct : 1; /* flow control transparency mode */
81 unsigned rngde : 1; /* range detect enable */
82 unsigned escde : 1; /* extended spec. char detect enable */
83 } cx_cor3_async_t;
84
85 typedef struct { /* async channel option register 6 */
86 unsigned parerr : 3; /* parity/framing error actions */
87 unsigned brk : 2; /* action on break condition */
88 unsigned inlcr : 1; /* translate NL to CR on input */
89 unsigned icrnl : 1; /* translate CR to NL on input */
90 unsigned igncr : 1; /* discard CR on input */
91 } cx_cor6_async_t;
92
93 typedef struct { /* async channel option register 7 */
94 unsigned ocrnl : 1; /* translate CR to NL on output */
95 unsigned onlcr : 1; /* translate NL to CR on output */
96 unsigned zero : 3;
97 unsigned fcerr : 1; /* process flow ctl err chars enable */
98 unsigned lnext : 1; /* LNext option enable */
99 unsigned istrip : 1; /* strip 8-bit on input */
100 } cx_cor7_async_t;
101
102 typedef struct { /* async channel options */
103 cx_cor1_async_t cor1; /* channel option register 1 */
104 cx_cor2_async_t cor2; /* channel option register 2 */
105 cx_cor3_async_t cor3; /* option register 3 */
106 cx_cor6_async_t cor6; /* channel option register 6 */
107 cx_cor7_async_t cor7; /* channel option register 7 */
108 unsigned char schr1; /* special character register 1 (XON) */
109 unsigned char schr2; /* special character register 2 (XOFF) */
110 unsigned char schr3; /* special character register 3 */
111 unsigned char schr4; /* special character register 4 */
112 unsigned char scrl; /* special character range low */
113 unsigned char scrh; /* special character range high */
114 unsigned char lnxt; /* LNext character */
115 } cx_opt_async_t;
116
117 /*
118 * HDLC channel mode ---------------------------------------------------------
119 */
120 /* Address field length option */
121 #define AFLO_1OCT 0 /* address field is 1 octet in length */
122 #define AFLO_2OCT 1 /* address field is 2 octet in length */
123
124 /* Clear detect for X.21 data transfer phase */
125 #define CLRDET_DISABLE 0 /* clear detect disabled */
126 #define CLRDET_ENABLE 1 /* clear detect enabled */
127
128 /* Addressing mode */
129 #define ADMODE_NOADDR 0 /* no address */
130 #define ADMODE_4_1 1 /* 4 * 1 byte */
131 #define ADMODE_2_2 2 /* 2 * 2 byte */
132
133 /* FCS append */
134 #define FCS_NOTPASS 0 /* receive CRC is not passed to the host */
135 #define FCS_PASS 1 /* receive CRC is passed to the host */
136
137 /* CRC modes */
138 #define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */
139 #define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */
140
141 /* Send sync pattern */
142 #define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */
143 #define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */
144
145 /* FCS preset */
146 #define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */
147 #define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */
148
149 /* idle mode */
150 #define IDLE_FLAG 0 /* idle in flag */
151 #define IDLE_MARK 1 /* idle in mark */
152
153 /* CRC polynomial select */
154 #define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */
155 #define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */
156
157 typedef struct { /* hdlc channel option register 1 */
158 unsigned ifflags : 4; /* number of inter-frame flags sent */
159 unsigned admode : 2; /* addressing mode */
160 unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */
161 unsigned aflo : 1; /* address field length option */
162 } cx_cor1_hdlc_t;
163
164 typedef struct { /* hdlc channel option register 2 */
165 unsigned dsrae : 1; /* DSR automatic enable */
166 unsigned ctsae : 1; /* CTS automatic enable */
167 unsigned rtsao : 1; /* RTS automatic output enable */
168 unsigned zero1 : 1;
169 unsigned crcninv : 1; /* CRC inversion option */
170 unsigned zero2 : 1;
171 unsigned fcsapd : 1; /* FCS append */
172 unsigned zero3 : 1;
173 } cx_cor2_hdlc_t;
174
175 typedef struct { /* hdlc channel option register 3 */
176 unsigned padcnt : 3; /* pad character count */
177 unsigned idle : 1; /* idle mode */
178 unsigned nofcs : 1; /* FCS disable */
179 unsigned fcspre : 1; /* FCS preset */
180 unsigned syncpat : 1; /* send sync pattern */
181 unsigned sndpad : 1; /* send pad characters before flag enable */
182 } cx_cor3_hdlc_t;
183
184 typedef struct { /* hdlc channel options */
185 cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */
186 cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */
187 cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */
188 unsigned char rfar1; /* receive frame address register 1 */
189 unsigned char rfar2; /* receive frame address register 2 */
190 unsigned char rfar3; /* receive frame address register 3 */
191 unsigned char rfar4; /* receive frame address register 4 */
192 unsigned char cpsr; /* CRC polynomial select */
193 } cx_opt_hdlc_t;
194
195 /*
196 * BISYNC channel mode -------------------------------------------------------
197 */
198
199 /* Longitudinal redundancy check */
200 #define BCC_CRC16 0 /* CRC16 is used for BCC */
201 #define BCC_LRC 1 /* LRC is used for BCC */
202
203 /* Send pad pattern */
204 #define PAD_AA 0 /* send AAh as pad character */
205 #define PAD_55 1 /* send 55h as pad character */
206
207 typedef struct { /* channel option register 1 */
208 unsigned charlen : 4; /* character length, 5..8 */
209 unsigned ignpar : 1; /* ignore parity */
210 unsigned parmode : 2; /* parity mode */
211 unsigned parity : 1; /* parity */
212 } cx_cor1_bisync_t;
213
214 typedef struct { /* channel option register 2 */
215 unsigned syns : 4; /* number of extra SYN chars before a frame */
216 unsigned crcninv : 1; /* CRC inversion option */
217 unsigned ebcdic : 1; /* use EBCDIC as char set (instead of ASCII) */
218 unsigned bcc : 1; /* BCC append enable */
219 unsigned lrc : 1; /* longitudinal redundancy check */
220 } cx_cor2_bisync_t;
221
222 typedef struct { /* channel option register 3 */
223 unsigned padcnt : 3; /* pad character count */
224 unsigned idle : 1; /* idle mode */
225 unsigned nofcs : 1; /* FCS disable */
226 unsigned fcspre : 1; /* FCS preset */
227 unsigned padpat : 1; /* send pad pattern */
228 unsigned sndpad : 1; /* send pad characters before SYN enable */
229 } cx_cor3_bisync_t;
230
231 typedef struct { /* channel option register 6 */
232 unsigned char specterm; /* special termination character */
233 } cx_cor6_bisync_t;
234
235 typedef struct { /* bisync channel options */
236 cx_cor1_bisync_t cor1; /* channel option register 1 */
237 cx_cor2_bisync_t cor2; /* channel option register 2 */
238 cx_cor3_bisync_t cor3; /* channel option register 3 */
239 cx_cor6_bisync_t cor6; /* channel option register 6 */
240 unsigned char cpsr; /* CRC polynomial select */
241 } cx_opt_bisync_t;
242
243 /*
244 * X.21 channel mode ---------------------------------------------------------
245 */
246
247 /* The number of SYN chars on receive */
248 #define X21SYN_2 0 /* two SYN characters are required */
249 #define X21SYN_1 1 /* one SYN character is required */
250
251 typedef struct { /* channel option register 1 */
252 unsigned charlen : 4; /* character length, 5..8 */
253 unsigned ignpar : 1; /* ignore parity */
254 unsigned parmode : 2; /* parity mode */
255 unsigned parity : 1; /* parity */
256 } cx_cor1_x21_t;
257
258 typedef struct { /* channel option register 2 */
259 unsigned zero1 : 5;
260 unsigned etc : 1; /* embedded transmitter command enable */
261 unsigned zero2 : 2;
262 } cx_cor2_x21_t;
263
264 typedef struct { /* channel option register 3 */
265 unsigned zero : 4;
266 unsigned scde : 1; /* special character detect enable */
267 unsigned stripsyn : 1; /* treat SYN chars as special condition */
268 unsigned ssde : 1; /* steady state detect enable */
269 unsigned syn : 1; /* the number of SYN chars on receive */
270 } cx_cor3_x21_t;
271
272 typedef struct { /* channel option register 6 */
273 unsigned char synchar; /* syn character */
274 } cx_cor6_x21_t;
275
276 typedef struct { /* x21 channel options */
277 cx_cor1_x21_t cor1; /* channel option register 1 */
278 cx_cor2_x21_t cor2; /* channel option register 2 */
279 cx_cor3_x21_t cor3; /* channel option register 3 */
280 cx_cor6_x21_t cor6; /* channel option register 6 */
281 unsigned char schr1; /* special character register 1 */
282 unsigned char schr2; /* special character register 2 */
283 unsigned char schr3; /* special character register 3 */
284 } cx_opt_x21_t;
285
286 /*
287 * CD2400 channel state structure --------------------------------------------
288 */
289
290 /* Signal encoding */
291 #define ENCOD_NRZ 0 /* NRZ mode */
292 #define ENCOD_NRZI 1 /* NRZI mode */
293 #define ENCOD_MANCHESTER 2 /* Manchester mode */
294
295 /* Clock source */
296 #define CLK_0 0 /* clock 0 */
297 #define CLK_1 1 /* clock 1 */
298 #define CLK_2 2 /* clock 2 */
299 #define CLK_3 3 /* clock 3 */
300 #define CLK_4 4 /* clock 4 */
301 #define CLK_EXT 6 /* external clock */
302 #define CLK_RCV 7 /* receive clock */
303
304 /* Channel type */
305 #define T_NONE 0 /* no channel */
306 #define T_ASYNC 1 /* pure asynchronous RS-232 channel */
307 #define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */
308 #define T_SYNC_V35 3 /* pure synchronous V.35 channel */
309 #define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */
310 #define T_UNIV_RS232 5 /* sync/async RS-232 channel */
311 #define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */
312 #define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */
313
314 typedef enum { /* channel mode */
315 M_ASYNC, /* asynchronous mode */
316 M_HDLC, /* HDLC mode */
317 M_BISYNC, /* BISYNC mode */
318 M_X21 /* X.21 mode */
319 } cx_chan_mode_t;
320
321 typedef struct { /* channel option register 4 */
322 unsigned thr : 4; /* FIFO threshold */
323 unsigned zero : 1;
324 unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */
325 unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */
326 unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */
327 } cx_cor4_t;
328
329 typedef struct { /* channel option register 5 */
330 unsigned rx_thr : 4; /* receive flow control FIFO threshold */
331 unsigned zero : 1;
332 unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */
333 unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */
334 unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */
335 } cx_cor5_t;
336
337 typedef struct { /* receive clock option register */
338 unsigned clk : 3; /* receive clock source */
339 unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */
340 unsigned dpll : 1; /* DPLL enable */
341 unsigned zero : 1;
342 unsigned tlval : 1; /* transmit line value */
343 } cx_rcor_t;
344
345 typedef struct { /* transmit clock option register */
346 unsigned zero1 : 1;
347 unsigned llm : 1; /* local loopback mode */
348 unsigned zero2 : 1;
349 unsigned ext1x : 1; /* external 1x clock mode */
350 unsigned zero3 : 1;
351 unsigned clk : 3; /* transmit clock source */
352 } cx_tcor_t;
353
354 typedef struct {
355 cx_cor4_t cor4; /* channel option register 4 */
356 cx_cor5_t cor5; /* channel option register 5 */
357 cx_rcor_t rcor; /* receive clock option register */
358 cx_tcor_t tcor; /* transmit clock option register */
359 } cx_chan_opt_t;
360
361 typedef enum { /* line break mode */
362 BRK_IDLE, /* normal line mode */
363 BRK_SEND, /* start sending break */
364 BRK_STOP /* stop sending break */
365 } cx_break_t;
366
367 typedef struct {
368 unsigned cisco : 1; /* cisco mode */
369 unsigned keepalive : 1; /* keepalive enable */
370 unsigned ext : 1; /* use external ppp implementation */
371 unsigned lock : 1; /* channel locked for use by driver */
372 unsigned norts : 1; /* disable automatic RTS control */
373 } cx_soft_opt_t;
374
375 #define NCHIP 4 /* the number of controllers per board */
376 #define NCHAN 16 /* the number of channels on the board */
377
378 typedef struct {
379 unsigned char board; /* adapter number, 0..2 */
380 unsigned char channel; /* channel number, 0..15 */
381 unsigned char type; /* channel type (read only) */
382 unsigned char iftype; /* chan0 interface RS-232/RS-449/V.35 */
383 unsigned long rxbaud; /* receiver speed */
384 unsigned long txbaud; /* transmitter speed */
385 cx_chan_mode_t mode; /* channel mode */
386 cx_chan_opt_t opt; /* common channel options */
387 cx_opt_async_t aopt; /* async mode options */
388 cx_opt_hdlc_t hopt; /* hdlc mode options */
389 cx_opt_bisync_t bopt; /* bisync mode options */
390 cx_opt_x21_t xopt; /* x.21 mode options */
391 cx_soft_opt_t sopt; /* software options and state flags */
392 char master[16]; /* master interface name or \0 */
393 } cx_options_t; /* user settable options */
394
395 typedef struct _chan_t {
396 unsigned char type; /* channel type */
397 unsigned char num; /* channel number, 0..15 */
398 struct _board_t *board; /* board pointer */
399 struct _chip_t *chip; /* controller pointer */
400 struct _stat_t *stat; /* statistics */
401 unsigned long rxbaud; /* receiver speed */
402 unsigned long txbaud; /* transmitter speed */
403 cx_chan_mode_t mode; /* channel mode */
404 cx_chan_opt_t opt; /* common channel options */
405 cx_opt_async_t aopt; /* async mode options */
406 cx_opt_hdlc_t hopt; /* hdlc mode options */
407 cx_opt_bisync_t bopt; /* bisync mode options */
408 cx_opt_x21_t xopt; /* x.21 mode options */
409 unsigned char *arbuf; /* receiver A dma buffer */
410 unsigned char *brbuf; /* receiver B dma buffer */
411 unsigned char *atbuf; /* transmitter A dma buffer */
412 unsigned char *btbuf; /* transmitter B dma buffer */
413 unsigned long arphys; /* receiver A phys address */
414 unsigned long brphys; /* receiver B phys address */
415 unsigned long atphys; /* transmitter A phys address */
416 unsigned long btphys; /* transmitter B phys address */
417 unsigned char dtr; /* DTR signal value */
418 unsigned char rts; /* RTS signal value */
419 #ifdef _KERNEL
420 struct tty *ttyp; /* tty structure pointer */
421 struct ifnet *ifp; /* network interface data */
422 struct ifnet *master; /* master interface, or ==ifp */
423 struct _chan_t *slaveq; /* slave queue pointer, or NULL */
424 cx_soft_opt_t sopt; /* software options and state flags */
425 cx_break_t brk; /* line break mode */
426 #ifdef __bsdi__
427 struct ttydevice_tmp *ttydev; /* tty statistics structure */
428 #endif
429 #endif
430 } cx_chan_t;
431
432 typedef struct _chip_t {
433 unsigned short port; /* base port address, or 0 if no chip */
434 unsigned char num; /* controller number, 0..3 */
435 struct _board_t *board; /* board pointer */
436 unsigned long oscfreq; /* oscillator frequency in Hz */
437 } cx_chip_t;
438
439 typedef struct _stat_t {
440 unsigned char board; /* adapter number, 0..2 */
441 unsigned char channel; /* channel number, 0..15 */
442 unsigned long rintr; /* receive interrupts */
443 unsigned long tintr; /* transmit interrupts */
444 unsigned long mintr; /* modem interrupts */
445 unsigned long ibytes; /* input bytes */
446 unsigned long ipkts; /* input packets */
447 unsigned long ierrs; /* input errors */
448 unsigned long obytes; /* output bytes */
449 unsigned long opkts; /* output packets */
450 unsigned long oerrs; /* output errors */
451 } cx_stat_t;
452
453 typedef struct _board_t {
454 unsigned short port; /* base board port, 0..3f0 */
455 unsigned short num; /* board number, 0..2 */
456 unsigned char irq; /* interrupt request {3 5 7 10 11 12 15} */
457 unsigned char dma; /* DMA request {5 6 7} */
458 unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */
459 unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */
460 unsigned short bcr0; /* BCR0 image */
461 unsigned short bcr0b; /* BCR0b image */
462 unsigned short bcr1; /* BCR1 image */
463 unsigned short bcr1b; /* BCR1b image */
464 cx_chip_t chip[NCHIP]; /* controller structures */
465 cx_chan_t chan[NCHAN]; /* channel structures */
466 cx_stat_t stat[NCHAN]; /* channel statistics */
467 char name[16]; /* board version name */
468 unsigned char nuniv; /* number of universal channels */
469 unsigned char nsync; /* number of sync. channels */
470 unsigned char nasync; /* number of async. channels */
471 } cx_board_t;
472
473 #define CX_SPEED_DFLT 9600
474
475 #ifdef _KERNEL
476 int cx_probe_board (int port);
477 void cx_init (cx_board_t *b, int num, int port, int irq, int dma);
478 void cx_setup_board (cx_board_t *b);
479 void cx_setup_chan (cx_chan_t *c);
480 void cx_chan_dtr (cx_chan_t *c, int on);
481 void cx_chan_rts (cx_chan_t *c, int on);
482 void cx_cmd (int base, int cmd);
483 int cx_chan_cd (cx_chan_t *c);
484 void cx_clock (long hz, long ba, int *clk, int *div);
485 #endif
486
487 #define CXIOCGETMODE _IOWR('x', 1, cx_options_t) /* get channel options */
488 #define CXIOCSETMODE _IOW('x', 2, cx_options_t) /* set channel options */
489 #define CXIOCGETSTAT _IOWR('x', 3, cx_stat_t) /* get channel stats */
490
491 #endif
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