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HAMMER 60I/Many: Mirroring
[dragonfly.git] / sys / dev / netif / sr / if_sr.c
blob96ec7e50fe45c2f6d783b9eac944d9bfe04d833e
1 /*
2 * Copyright (c) 1996 - 2001 John Hay.
3 * Copyright (c) 1996 SDL Communications, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
31 * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.24 2008/03/07 11:34:19 sephe Exp $
32 */
33
34 /*
35 * Programming assumptions and other issues.
36 *
37 * Only a 16K window will be used.
38 *
39 * The descriptors of a DMA channel will fit in a 16K memory window.
40 *
41 * The buffers of a transmit DMA channel will fit in a 16K memory window.
42 *
43 * When interface is going up, handshaking is set and it is only cleared
44 * when the interface is down'ed.
45 *
46 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
47 * internal/external clock, etc.....
48 *
49 */
50
51 #include "opt_netgraph.h"
52 #ifdef NETGRAPH
53 #include "if_sr.h"
54 #endif /* NETGRAPH */
55
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/kernel.h>
59 #include <sys/malloc.h>
60 #include <sys/mbuf.h>
61 #include <sys/sockio.h>
62 #include <sys/socket.h>
63 #include <sys/thread2.h>
64 #include <sys/bus.h>
65 #include <sys/rman.h>
66
67 #include <net/if.h>
68 #ifdef NETGRAPH
69 #include <sys/syslog.h>
70 #else /* NETGRAPH */
71 #include <net/sppp/if_sppp.h>
72
73 #include <net/bpf.h>
74 #endif /* NETGRAPH */
75
76 #include <machine/md_var.h>
77
78 #include "../ic_layer/hd64570.h"
79 #include "if_srregs.h"
80
81 #ifdef NETGRAPH
82 #include <netgraph/ng_message.h>
83 #include <netgraph/netgraph.h>
84 #endif /* NETGRAPH */
85 /* #define USE_MODEMCK */
86
87 #ifndef BUGGY
88 #define BUGGY 0
89 #endif
90
91 #ifndef NETGRAPH
92 #define PPP_HEADER_LEN 4
93 #endif /* NETGRAPH */
94
95 static int next_sc_unit = 0;
96 #ifndef NETGRAPH
97 #ifdef USE_MODEMCK
98 static int sr_watcher = 0;
99 #endif
100 #endif /* NETGRAPH */
101
102 /*
103 * Define the software interface for the card... There is one for
104 * every channel (port).
105 */
106 struct sr_softc {
107 #ifndef NETGRAPH
108 struct sppp ifsppp; /* PPP service w/in system */
109 #endif /* NETGRAPH */
110 struct sr_hardc *hc; /* card-level information */
111
112 int unit; /* With regard to all sr devices */
113 int subunit; /* With regard to this card */
114
115 struct buf_block {
116 u_int txdesc; /* DPRAM offset */
117 u_int txstart;/* DPRAM offset */
118 u_int txend; /* DPRAM offset */
119 u_int txtail; /* # of 1st free gran */
120 u_int txmax; /* # of free grans */
121 u_int txeda; /* err descr addr */
122 } block[SR_TX_BLOCKS];
123
124 char xmit_busy; /* Transmitter is busy */
125 char txb_inuse; /* # of tx grans in use */
126 u_int txb_new; /* ndx to new buffer */
127 u_int txb_next_tx; /* ndx to next gran rdy tx */
128
129 u_int rxdesc; /* DPRAM offset */
130 u_int rxstart; /* DPRAM offset */
131 u_int rxend; /* DPRAM offset */
132 u_int rxhind; /* ndx to the hd of rx bufrs */
133 u_int rxmax; /* # of avail grans */
134
135 u_int clk_cfg; /* Clock configuration */
136
137 int scachan; /* channel # on card */
138 #ifdef NETGRAPH
139 int running; /* something is attached so we are running */
140 int dcd; /* do we have dcd? */
141 /* ---netgraph bits --- */
142 char nodename[NG_NODESIZ]; /* store our node name */
143 int datahooks; /* number of data hooks attached */
144 node_p node; /* netgraph node */
145 hook_p hook; /* data hook */
146 hook_p debug_hook;
147 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
148 struct ifqueue xmitq; /* transmit queue */
149 int flags; /* state */
150 #define SCF_RUNNING 0x01 /* board is active */
151 #define SCF_OACTIVE 0x02 /* output is active */
152 int out_dog; /* watchdog cycles output count-down */
153 struct callout sr_timer; /* timeout(9) handle */
154 u_long inbytes, outbytes; /* stats */
155 u_long lastinbytes, lastoutbytes; /* a second ago */
156 u_long inrate, outrate; /* highest rate seen */
157 u_long inlast; /* last input N secs ago */
158 u_long out_deficit; /* output since last input */
159 u_long oerrors, ierrors[6];
160 u_long opackets, ipackets;
161 #endif /* NETGRAPH */
162 };
163
164 #ifdef NETGRAPH
165 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
166 #define QUITE_A_WHILE 300 /* 5 MINUTES */
167 #define LOTS_OF_PACKETS 100
168 #endif /* NETGRAPH */
169
170 /*
171 * Baud Rate table for Sync Mode.
172 * Each entry consists of 3 elements:
173 * Baud Rate (x100) , TMC, BR
174 *
175 * Baud Rate = FCLK / TMC / 2^BR
176 * Baud table for Crystal freq. of 9.8304 Mhz
177 */
178 #ifdef N2_TEST_SPEED
179 struct rate_line {
180 int target; /* target rate/100 */
181 int tmc_reg; /* TMC register value */
182 int br_reg; /* BR (BaudRateClk) selector */
183 } n2_rates[] = {
184 /* Baudx100 TMC BR */
185 { 3, 128, 8 },
186 { 6, 128, 7 },
187 { 12, 128, 6 },
188 { 24, 128, 5 },
189 { 48, 128, 4 },
190 { 96, 128, 3 },
191 { 192, 128, 2 },
192 { 384, 128, 1 },
193 { 560, 88, 1 },
194 { 640, 77, 1 },
195 { 1280, 38, 1 },
196 { 2560, 19, 1 },
197 { 5120, 10, 1 },
198 { 10000, 5, 1 },
199 { 15000, 3, 1 },
200 { 25000, 2, 1 },
201 { 50000, 1, 1 },
202 { 0, 0, 0 }
203 };
204
205 int sr_test_speed[] = {
206 N2_TEST_SPEED,
207 N2_TEST_SPEED
208 };
209
210 int etc0vals[] = {
211 SR_MCR_ETC0, /* ISA channel 0 */
212 SR_MCR_ETC1, /* ISA channel 1 */
213 SR_FECR_ETC0, /* PCI channel 0 */
214 SR_FECR_ETC1 /* PCI channel 1 */
215 };
216 #endif
217
218 devclass_t sr_devclass;
219 #ifndef NETGRAPH
220 DECLARE_DUMMY_MODULE(if_sr);
221 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
222 #else
223 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
224 #endif
225
226 static void srintr(void *arg);
227 static void sr_xmit(struct sr_softc *sc);
228 #ifndef NETGRAPH
229 static void srstart(struct ifnet *ifp);
230 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data,
231 struct ucred *);
232 static void srwatchdog(struct ifnet *ifp);
233 #else
234 static void srstart(struct sr_softc *sc);
235 static void srwatchdog(struct sr_softc *sc);
236 #endif /* NETGRAPH */
237 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
238 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
239 static void sr_eat_packet(struct sr_softc *sc, int single);
240 static void sr_get_packets(struct sr_softc *sc);
241
242 static void sr_up(struct sr_softc *sc);
243 static void sr_down(struct sr_softc *sc);
244 static void src_init(struct sr_hardc *hc);
245 static void sr_init_sca(struct sr_hardc *hc);
246 static void sr_init_msci(struct sr_softc *sc);
247 static void sr_init_rx_dmac(struct sr_softc *sc);
248 static void sr_init_tx_dmac(struct sr_softc *sc);
249 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr);
250 static void sr_msci_intr(struct sr_hardc *hc, u_char isr);
251 static void sr_timer_intr(struct sr_hardc *hc, u_char isr);
252 #ifndef NETGRAPH
253 #ifdef USE_MODEMCK
254 static void sr_modemck(void *x);
255 #endif
256 #else
257 static void sr_modemck(struct sr_softc *x);
258 #endif /* NETGRAPH */
259
260 #ifdef NETGRAPH
261 static void ngsr_watchdog_frame(void * arg);
262 static void ngsr_init(void* ignored);
263
264 static ng_constructor_t ngsr_constructor;
265 static ng_rcvmsg_t ngsr_rcvmsg;
266 static ng_shutdown_t ngsr_rmnode;
267 static ng_newhook_t ngsr_newhook;
268 /*static ng_findhook_t ngsr_findhook; */
269 static ng_connect_t ngsr_connect;
270 static ng_rcvdata_t ngsr_rcvdata;
271 static ng_disconnect_t ngsr_disconnect;
272
273 static struct ng_type typestruct = {
274 NG_VERSION,
275 NG_SR_NODE_TYPE,
276 NULL,
277 ngsr_constructor,
278 ngsr_rcvmsg,
279 ngsr_rmnode,
280 ngsr_newhook,
281 NULL,
282 ngsr_connect,
283 ngsr_rcvdata,
284 ngsr_rcvdata,
285 ngsr_disconnect,
286 NULL
287 };
288
289 static int ngsr_done_init = 0;
290 #endif /* NETGRAPH */
291
292 /*
293 * Register the ports on the adapter.
294 * Fill in the info for each port.
295 #ifndef NETGRAPH
296 * Attach each port to sppp and bpf.
297 #endif
298 */
299 int
300 sr_attach(device_t device)
301 {
302 int intf_sw, pndx;
303 u_int32_t flags;
304 u_int fecr, *fecrp;
305 struct sr_hardc *hc;
306 struct sr_softc *sc;
307 #ifndef NETGRAPH
308 struct ifnet *ifp;
309 #endif /* NETGRAPH */
310 int unit; /* index: channel w/in card */
311
312 hc = (struct sr_hardc *)device_get_softc(device);
313 MALLOC(sc, struct sr_softc *,
314 hc->numports * sizeof(struct sr_softc),
315 M_DEVBUF, M_WAITOK | M_ZERO);
316 hc->sc = sc;
317
318 /*
319 * Get the TX clock direction and configuration. The default is a
320 * single external clock which is used by RX and TX.
321 */
322 switch(hc->cardtype) {
323 case SR_CRD_N2:
324 flags = device_get_flags(device);
325 #ifdef N2_TEST_SPEED
326 if (sr_test_speed[0] > 0)
327 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
328 else
329 #endif
330 if (flags & SR_FLAGS_0_CLK_MSK)
331 hc->sc[0].clk_cfg =
332 (flags & SR_FLAGS_0_CLK_MSK)
333 >> SR_FLAGS_CLK_SHFT;
334
335 if (hc->numports == 2)
336 #ifdef N2_TEST_SPEED
337 if (sr_test_speed[1] > 0)
338 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
339 else
340 #endif
341 if (flags & SR_FLAGS_1_CLK_MSK)
342 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
343 >> (SR_FLAGS_CLK_SHFT +
344 SR_FLAGS_CLK_CHAN_SHFT);
345 break;
346 case SR_CRD_N2PCI:
347 fecrp = (u_int *)(hc->sca_base + SR_FECR);
348 fecr = *fecrp;
349 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
350 switch (pndx) {
351 case 1:
352 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
353 break;
354 case 0:
355 default:
356 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
357 }
358
359 #ifdef N2_TEST_SPEED
360 if (sr_test_speed[pndx] > 0)
361 sc->clk_cfg = SR_FLAGS_INT_CLK;
362 else
363 #endif
364 switch (intf_sw) {
365 default:
366 case SR_FE_ID_RS232:
367 case SR_FE_ID_HSSI:
368 case SR_FE_ID_RS422:
369 case SR_FE_ID_TEST:
370 break;
371
372 case SR_FE_ID_V35:
373 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
374 break;
375
376 case SR_FE_ID_X21:
377 sc->clk_cfg = SR_FLAGS_EXT_CLK;
378 break;
379 }
380 }
381 sc = hc->sc;
382 break;
383 }
384
385 /*
386 * Report Card configuration information before we start configuring
387 * each channel on the card...
388 */
389 kprintf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
390 hc->cunit, hc->memsize / 1024, hc->mempages,
391 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
392
393 src_init(hc);
394 sr_init_sca(hc);
395
396 if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
397 0, srintr, hc,
398 &hc->intr_cookie, NULL) != 0)
399 goto errexit;
400
401 /*
402 * Now configure each port on the card.
403 */
404 for (unit = 0; unit < hc->numports; sc++, unit++) {
405 sc->hc = hc;
406 sc->subunit = unit;
407 sc->unit = next_sc_unit;
408 next_sc_unit++;
409 sc->scachan = unit % NCHAN;
410
411 sr_init_rx_dmac(sc);
412 sr_init_tx_dmac(sc);
413 sr_init_msci(sc);
414
415 kprintf("sr%d: Adapter %d, port %d.\n",
416 sc->unit, hc->cunit, sc->subunit);
417
418 #ifndef NETGRAPH
419 ifp = &sc->ifsppp.pp_if;
420 ifp->if_softc = sc;
421 if_initname(ifp, "sr", sc->unit);
422 ifp->if_mtu = PP_MTU;
423 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
424 ifp->if_ioctl = srioctl;
425 ifp->if_start = srstart;
426 ifp->if_watchdog = srwatchdog;
427
428 sc->ifsppp.pp_flags = PP_KEEPALIVE;
429 sppp_attach((struct ifnet *)&sc->ifsppp);
430 if_attach(ifp, NULL);
431
432 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
433 #else /* NETGRAPH */
434 /*
435 * we have found a node, make sure our 'type' is availabe.
436 */
437 if (ngsr_done_init == 0) ngsr_init(NULL);
438 if (ng_make_node_common(&typestruct, &sc->node) != 0)
439 goto errexit;
440 sc->node->private = sc;
441 callout_init(&sc->sr_timer);
442 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
443 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
444 ksprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
445 if (ng_name_node(sc->node, sc->nodename)) {
446 ng_rmnode(sc->node);
447 ng_unref(sc->node);
448 return (0);
449 }
450 sc->running = 0;
451 #endif /* NETGRAPH */
452 }
453
454 if (hc->mempages)
455 SRC_SET_OFF(hc->iobase);
456
457 return (0);
458
459 errexit:
460 sr_deallocate_resources(device);
461 return (ENXIO);
462 }
463
464 int
465 sr_detach(device_t device)
466 {
467 device_t parent = device_get_parent(device);
468 struct sr_hardc *hc = device_get_softc(device);
469
470 if (hc->intr_cookie != NULL) {
471 if (BUS_TEARDOWN_INTR(parent, device,
472 hc->res_irq, hc->intr_cookie) != 0) {
473 kprintf("intr teardown failed.. continuing\n");
474 }
475 hc->intr_cookie = NULL;
476 }
477
478 /* XXX Stop the DMA. */
479
480 /*
481 * deallocate any system resources we may have
482 * allocated on behalf of this driver.
483 */
484 FREE(hc->sc, M_DEVBUF);
485 hc->sc = NULL;
486 hc->mem_start = NULL;
487 return (sr_deallocate_resources(device));
488 }
489
490 int
491 sr_allocate_ioport(device_t device, int rid, u_long size)
492 {
493 struct sr_hardc *hc = device_get_softc(device);
494
495 hc->rid_ioport = rid;
496 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
497 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
498 if (hc->res_ioport == NULL) {
499 goto errexit;
500 }
501 return (0);
502
503 errexit:
504 sr_deallocate_resources(device);
505 return (ENXIO);
506 }
507
508 int
509 sr_allocate_irq(device_t device, int rid, u_long size)
510 {
511 struct sr_hardc *hc = device_get_softc(device);
512
513 hc->rid_irq = rid;
514 hc->res_irq = bus_alloc_resource_any(device, SYS_RES_IRQ,
515 &hc->rid_irq, RF_SHAREABLE|RF_ACTIVE);
516 if (hc->res_irq == NULL) {
517 goto errexit;
518 }
519 return (0);
520
521 errexit:
522 sr_deallocate_resources(device);
523 return (ENXIO);
524 }
525
526 int
527 sr_allocate_memory(device_t device, int rid, u_long size)
528 {
529 struct sr_hardc *hc = device_get_softc(device);
530
531 hc->rid_memory = rid;
532 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
533 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
534 if (hc->res_memory == NULL) {
535 goto errexit;
536 }
537 return (0);
538
539 errexit:
540 sr_deallocate_resources(device);
541 return (ENXIO);
542 }
543
544 int
545 sr_allocate_plx_memory(device_t device, int rid, u_long size)
546 {
547 struct sr_hardc *hc = device_get_softc(device);
548
549 hc->rid_plx_memory = rid;
550 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
551 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
552 if (hc->res_plx_memory == NULL) {
553 goto errexit;
554 }
555 return (0);
556
557 errexit:
558 sr_deallocate_resources(device);
559 return (ENXIO);
560 }
561
562 int
563 sr_deallocate_resources(device_t device)
564 {
565 struct sr_hardc *hc = device_get_softc(device);
566
567 if (hc->res_irq != 0) {
568 bus_deactivate_resource(device, SYS_RES_IRQ,
569 hc->rid_irq, hc->res_irq);
570 bus_release_resource(device, SYS_RES_IRQ,
571 hc->rid_irq, hc->res_irq);
572 hc->res_irq = 0;
573 }
574 if (hc->res_ioport != 0) {
575 bus_deactivate_resource(device, SYS_RES_IOPORT,
576 hc->rid_ioport, hc->res_ioport);
577 bus_release_resource(device, SYS_RES_IOPORT,
578 hc->rid_ioport, hc->res_ioport);
579 hc->res_ioport = 0;
580 }
581 if (hc->res_memory != 0) {
582 bus_deactivate_resource(device, SYS_RES_MEMORY,
583 hc->rid_memory, hc->res_memory);
584 bus_release_resource(device, SYS_RES_MEMORY,
585 hc->rid_memory, hc->res_memory);
586 hc->res_memory = 0;
587 }
588 if (hc->res_plx_memory != 0) {
589 bus_deactivate_resource(device, SYS_RES_MEMORY,
590 hc->rid_plx_memory, hc->res_plx_memory);
591 bus_release_resource(device, SYS_RES_MEMORY,
592 hc->rid_plx_memory, hc->res_plx_memory);
593 hc->res_plx_memory = 0;
594 }
595 return (0);
596 }
597
598 /*
599 * N2 Interrupt Service Routine
600 *
601 * First figure out which SCA gave the interrupt.
602 * Process it.
603 * See if there is other interrupts pending.
604 * Repeat until there no interrupts remain.
605 */
606 static void
607 srintr(void *arg)
608 {
609 struct sr_hardc *hc = (struct sr_hardc *)arg;
610 sca_regs *sca = hc->sca; /* MSCI register tree */
611 u_char isr0, isr1, isr2; /* interrupt statii captured */
612
613 #if BUGGY > 1
614 kprintf("sr: srintr_hc(hc=%08x)\n", hc);
615 #endif
616
617 /*
618 * Since multiple interfaces may share this interrupt, we must loop
619 * until no interrupts are still pending service.
620 */
621 while (1) {
622 /*
623 * Read all three interrupt status registers from the N2
624 * card...
625 */
626 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
627 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
628 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
629
630 /*
631 * If all three registers returned 0, we've finished
632 * processing interrupts from this device, so we can quit
633 * this loop...
634 */
635 if ((isr0 | isr1 | isr2) == 0)
636 break;
637
638 #if BUGGY > 2
639 kprintf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
640 #ifndef NETGRAPH
641 unit, isr0, isr1, isr2);
642 #else
643 hc->cunit, isr0, isr1, isr2);
644 #endif /* NETGRAPH */
645 #endif
646
647 /*
648 * Now we can dispatch the interrupts. Since we don't expect
649 * either MSCI or timer interrupts, we'll test for DMA
650 * interrupts first...
651 */
652 if (isr1) /* DMA-initiated interrupt */
653 sr_dmac_intr(hc, isr1);
654
655 if (isr0) /* serial part IRQ? */
656 sr_msci_intr(hc, isr0);
657
658 if (isr2) /* timer-initiated interrupt */
659 sr_timer_intr(hc, isr2);
660 }
661 }
662
663 /*
664 * This will only start the transmitter. It is assumed that the data
665 * is already there.
666 * It is normally called from srstart() or sr_dmac_intr().
667 */
668 static void
669 sr_xmit(struct sr_softc *sc)
670 {
671 u_short cda_value; /* starting descriptor */
672 u_short eda_value; /* ending descriptor */
673 struct sr_hardc *hc;
674 #ifndef NETGRAPH
675 struct ifnet *ifp; /* O/S Network Services */
676 #endif /* NETGRAPH */
677 dmac_channel *dmac; /* DMA channel registers */
678
679 #if BUGGY > 0
680 kprintf("sr: sr_xmit( sc=%08x)\n", sc);
681 #endif
682
683 hc = sc->hc;
684 #ifndef NETGRAPH
685 ifp = &sc->ifsppp.pp_if;
686 #endif /* NETGRAPH */
687 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
688
689 /*
690 * Get the starting and ending addresses of the chain to be
691 * transmitted and pass these on to the DMA engine on-chip.
692 */
693 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
694 cda_value &= 0x00ffff;
695 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
696 eda_value &= 0x00ffff;
697
698 SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
699 SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
700
701 /*
702 * Now we'll let the DMA status register know about this change
703 */
704 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
705
706 sc->xmit_busy = 1; /* mark transmitter busy */
707
708 #if BUGGY > 2
709 kprintf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n",
710 sc->unit, cda_value, eda_value,
711 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
712 #endif
713
714 sc->txb_next_tx++; /* update next transmit seq# */
715
716 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */
717 sc->txb_next_tx = 0;
718
719 #ifndef NETGRAPH
720 /*
721 * Finally, we'll set a timout (which will start srwatchdog())
722 * within the O/S network services layer...
723 */
724 ifp->if_timer = 2; /* Value in seconds. */
725 #else
726 /*
727 * Don't time out for a while.
728 */
729 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
730 #endif /* NETGRAPH */
731 }
732
733 /*
734 * This function will be called from the upper level when a user add a
735 * packet to be send, and from the interrupt handler after a finished
736 * transmit.
737 *
738 * This function only place the data in the oncard buffers. It does not
739 * start the transmition. sr_xmit() does that.
740 *
741 * Transmitter idle state is indicated by the IFF_OACTIVE flag.
742 * The function that clears that should ensure that the transmitter
743 * and its DMA is in a "good" idle state.
744 */
745 #ifndef NETGRAPH
746 static void
747 srstart(struct ifnet *ifp)
748 {
749 struct sr_softc *sc; /* channel control structure */
750 #else
751 static void
752 srstart(struct sr_softc *sc)
753 {
754 #endif /* NETGRAPH */
755 struct sr_hardc *hc; /* card control/config block */
756 int len; /* total length of a packet */
757 int pkts; /* packets placed in DPRAM */
758 int tlen; /* working length of pkt */
759 u_int i;
760 struct mbuf *mtx; /* message buffer from O/S */
761 u_char *txdata; /* buffer address in DPRAM */
762 sca_descriptor *txdesc; /* working descriptor pointr */
763 struct buf_block *blkp;
764
765 #ifndef NETGRAPH
766 #if BUGGY > 0
767 kprintf("sr: srstart( ifp=%08x)\n", ifp);
768 #endif
769 sc = ifp->if_softc;
770 if ((ifp->if_flags & IFF_RUNNING) == 0)
771 return;
772 #endif /* NETGRAPH */
773 hc = sc->hc;
774 /*
775 * It is OK to set the memory window outside the loop because all tx
776 * buffers and descriptors are assumed to be in the same 16K window.
777 */
778 if (hc->mempages) {
779 SRC_SET_ON(hc->iobase);
780 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
781 }
782
783 /*
784 * Loop to place packets into DPRAM.
785 *
786 * We stay in this loop until there is nothing in
787 * the TX queue left or the tx buffers are full.
788 */
789 top_srstart:
790
791 /*
792 * See if we have space for more packets.
793 */
794 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */
795 #ifndef NETGRAPH
796 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
797 #else
798 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
799 #endif /* NETGRAPH */
800
801 if (hc->mempages)
802 SRC_SET_OFF(hc->iobase);
803
804 #if BUGGY > 9
805 kprintf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
806 sc->unit, sc->txb_inuse);
807 #endif
808 return;
809 }
810 /*
811 * OK, the card can take more traffic. Let's see if there's any
812 * pending from the system...
813 *
814 * NOTE:
815 * The architecture of the networking interface doesn't
816 * actually call us like 'write()', providing an address. We get
817 * started, a lot like a disk strategy routine, and we actually call
818 * back out to the system to get traffic to send...
819 *
820 * NOTE:
821 * If we were gonna run through another layer, we would use a
822 * dispatch table to select the service we're getting a packet
823 * from...
824 */
825 #ifndef NETGRAPH
826 mtx = sppp_dequeue(ifp);
827 #else /* NETGRAPH */
828 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
829 if (mtx == NULL) {
830 IF_DEQUEUE(&sc->xmitq, mtx);
831 }
832 #endif /* NETGRAPH */
833 if (!mtx) {
834 if (hc->mempages)
835 SRC_SET_OFF(hc->iobase);
836 return;
837 }
838 /*
839 * OK, we got a packet from the network services of the O/S. Now we
840 * can move it into the DPRAM (under control of the descriptors) and
841 * fire it off...
842 */
843 pkts = 0;
844 i = 0; /* counts # of granules used */
845
846 blkp = &sc->block[sc->txb_new]; /* address of free granule */
847 txdesc = (sca_descriptor *)
848 (hc->mem_start + (blkp->txdesc & hc->winmsk));
849
850 txdata = (u_char *)(hc->mem_start
851 + (blkp->txstart & hc->winmsk));
852
853 /*
854 * Now we'll try to install as many packets as possible into the
855 * card's DP RAM buffers.
856 */
857 for (;;) { /* perform actual copy of packet */
858 len = mtx->m_pkthdr.len; /* length of message */
859
860 #if BUGGY > 1
861 kprintf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
862 sc->unit, mtx, len);
863 #endif
864
865 #ifndef NETGRAPH
866 BPF_MTAP(ifp, mtx);
867 #else /* NETGRAPH */
868 sc->outbytes += len;
869 #endif /* NETGRAPH */
870
871 /*
872 * We can perform a straight copy because the tranmit
873 * buffers won't wrap.
874 */
875 m_copydata(mtx, 0, len, txdata);
876
877 /*
878 * Now we know how big the message is gonna be. We must now
879 * construct the descriptors to drive this message out...
880 */
881 tlen = len;
882 while (tlen > SR_BUF_SIZ) { /* loop for full granules */
883 txdesc->stat = 0; /* reset bits */
884 txdesc->len = SR_BUF_SIZ; /* size of granule */
885 tlen -= SR_BUF_SIZ;
886
887 txdesc++; /* move to next dscr */
888 txdata += SR_BUF_SIZ; /* adjust data addr */
889 i++;
890 }
891
892 /*
893 * This section handles the setting of the final piece of a
894 * message.
895 */
896 txdesc->stat = SCA_DESC_EOM;
897 txdesc->len = tlen;
898 pkts++;
899
900 /*
901 * prepare for subsequent packets (if any)
902 */
903 txdesc++;
904 txdata += SR_BUF_SIZ; /* next mem granule */
905 i++; /* count of granules */
906
907 /*
908 * OK, we've now placed the message into the DPRAM where it
909 * can be transmitted. We'll now release the message memory
910 * and update the statistics...
911 */
912 m_freem(mtx);
913 #ifndef NETGRAPH
914 ++sc->ifsppp.pp_if.if_opackets;
915 #else /* NETGRAPH */
916 sc->opackets++;
917 #endif /* NETGRAPH */
918
919 /*
920 * Check if we have space for another packet. XXX This is
921 * hardcoded. A packet can't be larger than 3 buffers (3 x
922 * 512).
923 */
924 if ((i + 3) >= blkp->txmax) { /* enough remains? */
925 #if BUGGY > 9
926 kprintf("sr%d.srstart: i=%d (%d pkts); card full.\n",
927 sc->unit, i, pkts);
928 #endif
929 break;
930 }
931 /*
932 * We'll pull the next message to be sent (if any)
933 */
934 #ifndef NETGRAPH
935 mtx = sppp_dequeue(ifp);
936 #else /* NETGRAPH */
937 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
938 if (mtx == NULL) {
939 IF_DEQUEUE(&sc->xmitq, mtx);
940 }
941 #endif /* NETGRAPH */
942 if (!mtx) { /* no message? We're done! */
943 #if BUGGY > 9
944 kprintf("sr%d.srstart: pending=0, pkts=%d\n",
945 sc->unit, pkts);
946 #endif
947 break;
948 }
949 }
950
951 blkp->txtail = i; /* record next free granule */
952
953 /*
954 * Mark the last descriptor, so that the SCA know where to stop.
955 */
956 txdesc--; /* back up to last descriptor in list */
957 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */
958
959 /*
960 * Now we'll reset the transmit granule's descriptor address so we
961 * can record this in the structure and fire it off w/ the DMA
962 * processor of the serial chip...
963 */
964 txdesc = (sca_descriptor *)blkp->txdesc;
965 blkp->txeda = (u_short)((u_int)&txdesc[i]);
966
967 sc->txb_inuse++; /* update inuse status */
968 sc->txb_new++; /* new traffic wuz added */
969
970 if (sc->txb_new == SR_TX_BLOCKS)
971 sc->txb_new = 0;
972
973 /*
974 * If the tranmitter wasn't marked as "busy" we will force it to be
975 * started...
976 */
977 if (sc->xmit_busy == 0) {
978 sr_xmit(sc);
979 #if BUGGY > 9
980 kprintf("sr%d.srstart: called sr_xmit()\n", sc->unit);
981 #endif
982 }
983 goto top_srstart;
984 }
985
986 #ifndef NETGRAPH
987 /*
988 * Handle ioctl's at the device level, though we *will* call up
989 * a layer...
990 */
991 #if BUGGY > 2
992 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
993 #endif
994
995 static int
996 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
997 {
998 int error, was_up, should_be_up;
999 struct sr_softc *sc = ifp->if_softc;
1000
1001 #if BUGGY > 0
1002 kprintf("%s: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1003 ifp->if_xname, ifp, cmd, data);
1004 #endif
1005
1006 was_up = ifp->if_flags & IFF_RUNNING;
1007
1008 error = sppp_ioctl(ifp, cmd, data);
1009
1010 #if BUGGY > 1
1011 kprintf("%s: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1012 ifp->if_xname, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1013 #endif
1014
1015 if (error)
1016 return error;
1017
1018 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1019 #if BUGGY > 2
1020 if (bug_splats[sc->unit]++ < 2) {
1021 kprintf("sr(%d).if_addrheads = %08x\n",
1022 sc->unit, ifp->if_addrheads);
1023 kprintf("sr(%d).if_bpf = %08x\n",
1024 sc->unit, ifp->if_bpf);
1025 kprintf("sr(%d).if_init = %08x\n",
1026 sc->unit, ifp->if_init);
1027 kprintf("sr(%d).if_output = %08x\n",
1028 sc->unit, ifp->if_output);
1029 kprintf("sr(%d).if_start = %08x\n",
1030 sc->unit, ifp->if_start);
1031 kprintf("sr(%d).if_done = %08x\n",
1032 sc->unit, ifp->if_done);
1033 kprintf("sr(%d).if_ioctl = %08x\n",
1034 sc->unit, ifp->if_ioctl);
1035 kprintf("sr(%d).if_reset = %08x\n",
1036 sc->unit, ifp->if_reset);
1037 kprintf("sr(%d).if_watchdog = %08x\n",
1038 sc->unit, ifp->if_watchdog);
1039 }
1040 #endif
1041 return 0;
1042 }
1043
1044 crit_enter();
1045
1046 should_be_up = ifp->if_flags & IFF_RUNNING;
1047
1048 if (!was_up && should_be_up) {
1049 /*
1050 * Interface should be up -- start it.
1051 */
1052 sr_up(sc);
1053 srstart(ifp);
1054
1055 /*
1056 * XXX Clear the IFF_UP flag so that the link will only go
1057 * up after sppp lcp and ipcp negotiation.
1058 */
1059 /* ifp->if_flags &= ~IFF_UP; */
1060 } else if (was_up && !should_be_up) {
1061 /*
1062 * Interface should be down -- stop it.
1063 */
1064 sr_down(sc);
1065 sppp_flush(ifp);
1066 }
1067
1068 crit_exit();
1069
1070 return 0;
1071 }
1072 #endif /* NETGRAPH */
1073
1074 /*
1075 * This is to catch lost tx interrupts.
1076 */
1077 static void
1078 #ifndef NETGRAPH
1079 srwatchdog(struct ifnet *ifp)
1080 #else
1081 srwatchdog(struct sr_softc *sc)
1082 #endif /* NETGRAPH */
1083 {
1084 int got_st0, got_st1, got_st3, got_dsr;
1085 #ifndef NETGRAPH
1086 struct sr_softc *sc = ifp->if_softc;
1087 #endif /* NETGRAPH */
1088 struct sr_hardc *hc = sc->hc;
1089 msci_channel *msci = &hc->sca->msci[sc->scachan];
1090 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1091
1092 #if BUGGY > 0
1093 #ifndef NETGRAPH
1094 kprintf("srwatchdog(unit=%d)\n", unit);
1095 #else
1096 kprintf("srwatchdog(unit=%d)\n", sc->unit);
1097 #endif /* NETGRAPH */
1098 #endif
1099
1100 #ifndef NETGRAPH
1101 if (!(ifp->if_flags & IFF_RUNNING))
1102 return;
1103
1104 ifp->if_oerrors++; /* update output error count */
1105 #else /* NETGRAPH */
1106 sc->oerrors++; /* update output error count */
1107 #endif /* NETGRAPH */
1108
1109 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1110 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1111 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1112 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1113
1114 #ifndef NETGRAPH
1115 #if 0
1116 if (ifp->if_flags & IFF_DEBUG)
1117 #endif
1118 kprintf("sr%d: transmit failed, "
1119 #else /* NETGRAPH */
1120 kprintf("sr%d: transmit failed, "
1121 #endif /* NETGRAPH */
1122 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1123 sc->unit,
1124 got_st0, got_st1, got_st3, got_dsr);
1125
1126 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1127 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1128 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1129 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1130 }
1131 sc->xmit_busy = 0;
1132 #ifndef NETGRAPH
1133 ifp->if_flags &= ~IFF_OACTIVE;
1134 #else
1135 /*ifp->if_flags &= ~IFF_OACTIVE; */
1136 #endif /* NETGRAPH */
1137
1138 if (sc->txb_inuse && --sc->txb_inuse)
1139 sr_xmit(sc);
1140
1141 #ifndef NETGRAPH
1142 srstart(ifp); /* restart transmitter */
1143 #else
1144 srstart(sc); /* restart transmitter */
1145 #endif /* NETGRAPH */
1146 }
1147
1148 static void
1149 sr_up(struct sr_softc *sc)
1150 {
1151 u_int *fecrp;
1152 struct sr_hardc *hc = sc->hc;
1153 sca_regs *sca = hc->sca;
1154 msci_channel *msci = &sca->msci[sc->scachan];
1155
1156 #if BUGGY > 0
1157 kprintf("sr_up(sc=%08x)\n", sc);
1158 #endif
1159
1160 /*
1161 * Enable transmitter and receiver. Raise DTR and RTS. Enable
1162 * interrupts.
1163 *
1164 * XXX What about using AUTO mode in msci->md0 ???
1165 */
1166 SRC_PUT8(hc->sca_base, msci->ctl,
1167 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1168
1169 if (sc->scachan == 0)
1170 switch (hc->cardtype) {
1171 case SR_CRD_N2:
1172 outb(hc->iobase + SR_MCR,
1173 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1174 break;
1175 case SR_CRD_N2PCI:
1176 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1177 *fecrp &= ~SR_FECR_DTR0;
1178 break;
1179 }
1180 else
1181 switch (hc->cardtype) {
1182 case SR_CRD_N2:
1183 outb(hc->iobase + SR_MCR,
1184 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1185 break;
1186 case SR_CRD_N2PCI:
1187 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1188 *fecrp &= ~SR_FECR_DTR1;
1189 break;
1190 }
1191
1192 if (sc->scachan == 0) {
1193 SRC_PUT8(hc->sca_base, sca->ier0,
1194 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1195 SRC_PUT8(hc->sca_base, sca->ier1,
1196 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1197 } else {
1198 SRC_PUT8(hc->sca_base, sca->ier0,
1199 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1200 SRC_PUT8(hc->sca_base, sca->ier1,
1201 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1202 }
1203
1204 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1205 inb(hc->iobase); /* XXX slow it down a bit. */
1206 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1207
1208 #ifndef NETGRAPH
1209 #ifdef USE_MODEMCK
1210 if (sr_watcher == 0)
1211 sr_modemck(NULL);
1212 #endif
1213 #else /* NETGRAPH */
1214 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
1215 sc->running = 1;
1216 #endif /* NETGRAPH */
1217 }
1218
1219 static void
1220 sr_down(struct sr_softc *sc)
1221 {
1222 u_int *fecrp;
1223 struct sr_hardc *hc = sc->hc;
1224 sca_regs *sca = hc->sca;
1225 msci_channel *msci = &sca->msci[sc->scachan];
1226
1227 #if BUGGY > 0
1228 kprintf("sr_down(sc=%08x)\n", sc);
1229 #endif
1230 #ifdef NETGRAPH
1231 callout_stop(&sc->sr_timer);
1232 sc->running = 0;
1233 #endif /* NETGRAPH */
1234
1235 /*
1236 * Disable transmitter and receiver. Lower DTR and RTS. Disable
1237 * interrupts.
1238 */
1239 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1240 inb(hc->iobase); /* XXX slow it down a bit. */
1241 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1242
1243 SRC_PUT8(hc->sca_base, msci->ctl,
1244 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1245
1246 if (sc->scachan == 0)
1247 switch (hc->cardtype) {
1248 case SR_CRD_N2:
1249 outb(hc->iobase + SR_MCR,
1250 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1251 break;
1252 case SR_CRD_N2PCI:
1253 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1254 *fecrp |= SR_FECR_DTR0;
1255 break;
1256 }
1257 else
1258 switch (hc->cardtype) {
1259 case SR_CRD_N2:
1260 outb(hc->iobase + SR_MCR,
1261 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1262 break;
1263 case SR_CRD_N2PCI:
1264 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1265 *fecrp |= SR_FECR_DTR1;
1266 break;
1267 }
1268
1269 if (sc->scachan == 0) {
1270 SRC_PUT8(hc->sca_base, sca->ier0,
1271 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1272 SRC_PUT8(hc->sca_base, sca->ier1,
1273 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1274 } else {
1275 SRC_PUT8(hc->sca_base, sca->ier0,
1276 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1277 SRC_PUT8(hc->sca_base, sca->ier1,
1278 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1279 }
1280 }
1281
1282 /*
1283 * Initialize the card, allocate memory for the sr_softc structures
1284 * and fill in the pointers.
1285 */
1286 static void
1287 src_init(struct sr_hardc *hc)
1288 {
1289 struct sr_softc *sc = hc->sc;
1290 int x;
1291 u_int chanmem;
1292 u_int bufmem;
1293 u_int next;
1294 u_int descneeded;
1295
1296 #if BUGGY > 0
1297 kprintf("src_init(hc=%08x)\n", hc);
1298 #endif
1299
1300 chanmem = hc->memsize / hc->numports;
1301 next = 0;
1302
1303 for (x = 0; x < hc->numports; x++, sc++) {
1304 int blk;
1305
1306 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1307 sc->block[blk].txdesc = next;
1308 bufmem = (16 * 1024) / SR_TX_BLOCKS;
1309 descneeded = bufmem / SR_BUF_SIZ;
1310
1311 sc->block[blk].txstart = sc->block[blk].txdesc
1312 + ((((descneeded * sizeof(sca_descriptor))
1313 / SR_BUF_SIZ) + 1)
1314 * SR_BUF_SIZ);
1315
1316 sc->block[blk].txend = next + bufmem;
1317 sc->block[blk].txmax =
1318 (sc->block[blk].txend - sc->block[blk].txstart)
1319 / SR_BUF_SIZ;
1320 next += bufmem;
1321
1322 #if BUGGY > 2
1323 kprintf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1324 sc->unit, blk,
1325 sc->block[blk].txdesc, sc->block[blk].txstart);
1326 #endif
1327 }
1328
1329 sc->rxdesc = next;
1330 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1331 descneeded = bufmem / SR_BUF_SIZ;
1332 sc->rxstart = sc->rxdesc +
1333 ((((descneeded * sizeof(sca_descriptor)) /
1334 SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1335 sc->rxend = next + bufmem;
1336 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1337 next += bufmem;
1338 }
1339 }
1340
1341 /*
1342 * The things done here are channel independent.
1343 *
1344 * Configure the sca waitstates.
1345 * Configure the global interrupt registers.
1346 * Enable master dma enable.
1347 */
1348 static void
1349 sr_init_sca(struct sr_hardc *hc)
1350 {
1351 sca_regs *sca = hc->sca;
1352
1353 #if BUGGY > 0
1354 kprintf("sr_init_sca(hc=%08x)\n", hc);
1355 #endif
1356
1357 /*
1358 * Do the wait registers. Set everything to 0 wait states.
1359 */
1360 SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1361 SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1362 SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1363 SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1364 SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1365
1366 /*
1367 * Configure the interrupt registers. Most are cleared until the
1368 * interface is configured.
1369 */
1370 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */
1371 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */
1372 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */
1373 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr
1374 * ack */
1375 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1376 SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1377
1378 /*
1379 * Configure the timers. XXX Later
1380 */
1381
1382 /*
1383 * Set the DMA channel priority to rotate between all four channels.
1384 *
1385 * Enable all dma channels.
1386 */
1387 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1388 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1389 }
1390
1391 /*
1392 * Configure the msci
1393 *
1394 * NOTE: The serial port configuration is hardcoded at the moment.
1395 */
1396 static void
1397 sr_init_msci(struct sr_softc *sc)
1398 {
1399 int portndx; /* on-board port number */
1400 u_int mcr_v; /* contents of modem control */
1401 u_int *fecrp; /* pointer for PCI's MCR i/o */
1402 struct sr_hardc *hc = sc->hc;
1403 msci_channel *msci = &hc->sca->msci[sc->scachan];
1404 #ifdef N2_TEST_SPEED
1405 int br_v; /* contents for BR divisor */
1406 int etcndx; /* index into ETC table */
1407 int fifo_v, gotspeed; /* final tabled speed found */
1408 int tmc_v; /* timer control register */
1409 int wanted; /* speed (bitrate) wanted... */
1410 struct rate_line *rtp;
1411 #endif
1412
1413 portndx = sc->scachan;
1414
1415 #if BUGGY > 0
1416 kprintf("sr: sr_init_msci( sc=%08x)\n", sc);
1417 #endif
1418
1419 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1420 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1421 SCA_MD0_CRC_CCITT |
1422 SCA_MD0_CRC_ENABLE |
1423 SCA_MD0_MODE_HDLC);
1424 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1425 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1426
1427 /*
1428 * According to the manual I should give a reset after changing the
1429 * mode registers.
1430 */
1431 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1432 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1433 SCA_CTL_UDRNC |
1434 SCA_CTL_RTS);
1435
1436 /*
1437 * XXX Later we will have to support different clock settings.
1438 */
1439 switch (sc->clk_cfg) {
1440 default:
1441 #if BUGGY > 0
1442 kprintf("sr%: clk_cfg=%08x, selected default clock.\n",
1443 portndx, sc->clk_cfg);
1444 #endif
1445 /* FALLTHROUGH */
1446 case SR_FLAGS_EXT_CLK:
1447 /*
1448 * For now all interfaces are programmed to use the RX clock
1449 * for the TX clock.
1450 */
1451
1452 #if BUGGY > 0
1453 kprintf("sr%d: External Clock Selected.\n", portndx);
1454 #endif
1455
1456 SRC_PUT8(hc->sca_base, msci->rxs,
1457 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1458 SRC_PUT8(hc->sca_base, msci->txs,
1459 SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1460 break;
1461
1462 case SR_FLAGS_EXT_SEP_CLK:
1463 #if BUGGY > 0
1464 kprintf("sr%d: Split Clocking Selected.\n", portndx);
1465 #endif
1466
1467 SRC_PUT8(hc->sca_base, msci->rxs,
1468 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1469 SRC_PUT8(hc->sca_base, msci->txs,
1470 SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1471 break;
1472
1473 case SR_FLAGS_INT_CLK:
1474 #if BUGGY > 0
1475 kprintf("sr%d: Internal Clocking selected.\n", portndx);
1476 #endif
1477
1478 /*
1479 * XXX I do need some code to set the baud rate here!
1480 */
1481 #ifdef N2_TEST_SPEED
1482 switch (hc->cardtype) {
1483 case SR_CRD_N2PCI:
1484 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1485 mcr_v = *fecrp;
1486 etcndx = 2;
1487 break;
1488 case SR_CRD_N2:
1489 default:
1490 mcr_v = inb(hc->iobase + SR_MCR);
1491 etcndx = 0;
1492 }
1493
1494 fifo_v = 0x10; /* stolen from Linux version */
1495
1496 /*
1497 * search for appropriate speed in table, don't calc it:
1498 */
1499 wanted = sr_test_speed[portndx];
1500 rtp = &n2_rates[0]; /* point to first table item */
1501
1502 while ((rtp->target > 0) /* search table for speed */
1503 &&(rtp->target != wanted))
1504 rtp++;
1505
1506 /*
1507 * We've searched the table for a matching speed. If we've
1508 * found the correct rate line, we'll get the pre-calc'd
1509 * values for the TMC and baud rate divisor for subsequent
1510 * use...
1511 */
1512 if (rtp->target > 0) { /* use table-provided values */
1513 gotspeed = wanted;
1514 tmc_v = rtp->tmc_reg;
1515 br_v = rtp->br_reg;
1516 } else { /* otherwise assume 1MBit comm rate */
1517 gotspeed = 10000;
1518 tmc_v = 5;
1519 br_v = 1;
1520 }
1521
1522 /*
1523 * Now we mask in the enable clock output for the MCR:
1524 */
1525 mcr_v |= etc0vals[etcndx + portndx];
1526
1527 /*
1528 * Now we'll program the registers with these speed- related
1529 * contents...
1530 */
1531 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1532 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1533 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1534 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1535
1536 switch (hc->cardtype) {
1537 case SR_CRD_N2PCI:
1538 *fecrp = mcr_v;
1539 break;
1540 case SR_CRD_N2:
1541 default:
1542 outb(hc->iobase + SR_MCR, mcr_v);
1543 }
1544
1545 #if BUGGY > 0
1546 if (wanted != gotspeed)
1547 kprintf("sr%d: Speed wanted=%d, found=%d\n",
1548 wanted, gotspeed);
1549
1550 kprintf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1551 portndx, gotspeed, tmc_v, br_v);
1552 #endif
1553 #else
1554 SRC_PUT8(hc->sca_base, msci->rxs,
1555 SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1556 SRC_PUT8(hc->sca_base, msci->txs,
1557 SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1558
1559 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1560
1561 if (portndx == 0)
1562 switch (hc->cardtype) {
1563 case SR_CRD_N2PCI:
1564 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1565 *fecrp |= SR_FECR_ETC0;
1566 break;
1567 case SR_CRD_N2:
1568 default:
1569 mcr_v = inb(hc->iobase + SR_MCR);
1570 mcr_v |= SR_MCR_ETC0;
1571 outb(hc->iobase + SR_MCR, mcr_v);
1572 }
1573 else
1574 switch (hc->cardtype) {
1575 case SR_CRD_N2:
1576 mcr_v = inb(hc->iobase + SR_MCR);
1577 mcr_v |= SR_MCR_ETC1;
1578 outb(hc->iobase + SR_MCR, mcr_v);
1579 break;
1580 case SR_CRD_N2PCI:
1581 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1582 *fecrp |= SR_FECR_ETC1;
1583 break;
1584 }
1585 #endif
1586 }
1587
1588 /*
1589 * XXX Disable all interrupts for now. I think if you are using the
1590 * dmac you don't use these interrupts.
1591 */
1592 SRC_PUT8(hc->sca_base, msci->ie0, 0);
1593 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1594 SRC_PUT8(hc->sca_base, msci->ie2, 0);
1595 SRC_PUT8(hc->sca_base, msci->fie, 0);
1596
1597 SRC_PUT8(hc->sca_base, msci->sa0, 0);
1598 SRC_PUT8(hc->sca_base, msci->sa1, 0);
1599
1600 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */
1601
1602 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1603 SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1604 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1605 }
1606
1607 /*
1608 * Configure the rx dma controller.
1609 */
1610 static void
1611 sr_init_rx_dmac(struct sr_softc *sc)
1612 {
1613 struct sr_hardc *hc;
1614 dmac_channel *dmac;
1615 sca_descriptor *rxd;
1616 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1617
1618 #if BUGGY > 0
1619 kprintf("sr_init_rx_dmac(sc=%08x)\n", sc);
1620 #endif
1621
1622 hc = sc->hc;
1623 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1624
1625 if (hc->mempages)
1626 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1627
1628 /*
1629 * This phase initializes the contents of the descriptor table
1630 * needed to construct a circular buffer...
1631 */
1632 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1633 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1634
1635 for (rxbuf = sc->rxstart;
1636 rxbuf < sc->rxend;
1637 rxbuf += SR_BUF_SIZ, rxd++) {
1638 /*
1639 * construct the circular chain...
1640 */
1641 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1642 rxd->cp = (u_short)(rxda & 0xffff);
1643
1644 /*
1645 * set the on-card buffer address...
1646 */
1647 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1648 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1649
1650 rxd->len = 0; /* bytes resident w/in granule */
1651 rxd->stat = 0xff; /* The sca write here when finished */
1652 }
1653
1654 /*
1655 * heal the chain so that the last entry points to the first...
1656 */
1657 rxd--;
1658 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1659
1660 /*
1661 * reset the reception handler's index...
1662 */
1663 sc->rxhind = 0;
1664
1665 /*
1666 * We'll now configure the receiver's DMA logic...
1667 */
1668 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */
1669 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1670
1671 /* XXX maybe also SCA_DMR_CNTE */
1672 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1673 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1674
1675 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1676 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1677
1678 SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1679 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1680
1681 rxd = (sca_descriptor *)sc->rxstart;
1682
1683 SRC_PUT16(hc->sca_base, dmac->eda,
1684 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1685
1686 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1687
1688
1689 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */
1690 }
1691
1692 /*
1693 * Configure the TX DMA descriptors.
1694 * Initialize the needed values and chain the descriptors.
1695 */
1696 static void
1697 sr_init_tx_dmac(struct sr_softc *sc)
1698 {
1699 int blk;
1700 u_int txbuf, txda, txda_d;
1701 struct sr_hardc *hc;
1702 sca_descriptor *txd;
1703 dmac_channel *dmac;
1704 struct buf_block *blkp;
1705 u_int x;
1706 u_int sarb_v;
1707
1708 #if BUGGY > 0
1709 kprintf("sr_init_tx_dmac(sc=%08x)\n", sc);
1710 #endif
1711
1712 hc = sc->hc;
1713 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1714
1715 if (hc->mempages)
1716 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1717
1718 /*
1719 * Initialize the array of descriptors for transmission
1720 */
1721 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1722 blkp = &sc->block[blk];
1723 txd = (sca_descriptor *)(hc->mem_start
1724 + (blkp->txdesc & hc->winmsk));
1725 txda_d = (u_int) hc->mem_start
1726 - (blkp->txdesc & ~hc->winmsk);
1727
1728 x = 0;
1729 txbuf = blkp->txstart;
1730 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1731 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1732 txd->cp = (u_short)(txda & 0xffff);
1733
1734 txd->bp = (u_short)((txbuf + hc->mem_pstart)
1735 & 0xffff);
1736 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1737 & 0xff);
1738 txd->len = 0;
1739 txd->stat = 0;
1740 x++;
1741 }
1742
1743 txd--;
1744 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1745 & 0xffff);
1746
1747 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1748 }
1749
1750 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */
1751 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1752 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1753 SRC_PUT8(hc->sca_base, dmac->dir,
1754 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1755
1756 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1757 sarb_v &= 0x00ff;
1758
1759 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1760 }
1761
1762 /*
1763 * Look through the descriptors to see if there is a complete packet
1764 * available. Stop if we get to where the sca is busy.
1765 *
1766 * Return the length and status of the packet.
1767 * Return nonzero if there is a packet available.
1768 *
1769 * NOTE:
1770 * It seems that we get the interrupt a bit early. The updateing of
1771 * descriptor values is not always completed when this is called.
1772 */
1773 static int
1774 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1775 {
1776 int granules; /* count of granules in pkt */
1777 int wki, wko;
1778 struct sr_hardc *hc;
1779 sca_descriptor *rxdesc; /* current descriptor */
1780 sca_descriptor *endp; /* ending descriptor */
1781 sca_descriptor *cda; /* starting descriptor */
1782
1783 hc = sc->hc; /* get card's information */
1784
1785 /*
1786 * set up starting descriptor by pulling that info from the DMA half
1787 * of the HD chip...
1788 */
1789 wki = DMAC_RXCH(sc->scachan);
1790 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1791
1792 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1793
1794 #if BUGGY > 1
1795 kprintf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1796 wki, wko, cda);
1797 #endif
1798
1799 /*
1800 * open the appropriate memory window and set our expectations...
1801 */
1802 if (hc->mempages) {
1803 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1804 SRC_SET_ON(hc->iobase);
1805 }
1806 rxdesc = (sca_descriptor *)
1807 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1808 endp = rxdesc;
1809 rxdesc = &rxdesc[sc->rxhind];
1810 endp = &endp[sc->rxmax];
1811
1812 *len = 0; /* reset result total length */
1813 granules = 0; /* reset count of granules */
1814
1815 /*
1816 * This loop will scan descriptors, but it *will* puke up if we wrap
1817 * around to our starting point...
1818 */
1819 while (rxdesc != cda) {
1820 *len += rxdesc->len; /* increment result length */
1821 granules++;
1822
1823 /*
1824 * If we hit a valid packet's completion we'll know we've
1825 * got a live one, and that we can deliver the packet.
1826 * Since we're only allowed to report a packet available,
1827 * somebody else does that...
1828 */
1829 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */
1830 *rxstat = rxdesc->stat; /* return closing */
1831 #if BUGGY > 0
1832 kprintf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1833 sc->unit, *len, *rxstat, granules);
1834 #endif
1835 return 1; /* indicate success */
1836 }
1837 /*
1838 * OK, this packet take up multiple granules. Move on to
1839 * the next descriptor so we can consider it...
1840 */
1841 rxdesc++;
1842
1843 if (rxdesc == endp) /* recognize & act on wrap point */
1844 rxdesc = (sca_descriptor *)
1845 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1846 }
1847
1848 /*
1849 * Nothing found in the DPRAM. Let the caller know...
1850 */
1851 *len = 0;
1852 *rxstat = 0;
1853
1854 return 0;
1855 }
1856
1857 /*
1858 * Copy a packet from the on card memory into a provided mbuf.
1859 * Take into account that buffers wrap and that a packet may
1860 * be larger than a buffer.
1861 */
1862 static void
1863 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1864 {
1865 struct sr_hardc *hc;
1866 sca_descriptor *rxdesc;
1867 u_int rxdata;
1868 u_int rxmax;
1869 u_int off = 0;
1870 u_int tlen;
1871
1872 #if BUGGY > 0
1873 kprintf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1874 m, sc, len);
1875 #endif
1876
1877 hc = sc->hc;
1878
1879 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1880 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1881
1882 rxdesc = (sca_descriptor *)
1883 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1884 rxdesc = &rxdesc[sc->rxhind];
1885
1886 /*
1887 * Using the count of bytes in the received packet, we decrement it
1888 * for each granule (controller by an SCA descriptor) to control the
1889 * looping...
1890 */
1891 while (len) {
1892 /*
1893 * tlen gets the length of *this* granule... ...which is
1894 * then copied to the target buffer.
1895 */
1896 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1897
1898 if (hc->mempages)
1899 SRC_SET_MEM(hc->iobase, rxdata);
1900
1901 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1902 mtod(m, caddr_t) +off,
1903 tlen);
1904
1905 off += tlen;
1906 len -= tlen;
1907
1908 /*
1909 * now, return to the descriptor's window in DPRAM and reset
1910 * the descriptor we've just suctioned...
1911 */
1912 if (hc->mempages)
1913 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1914
1915 rxdesc->len = 0;
1916 rxdesc->stat = 0xff;
1917
1918 /*
1919 * Move on to the next granule. If we've any remaining
1920 * bytes to process we'll just continue in our loop...
1921 */
1922 rxdata += SR_BUF_SIZ;
1923 rxdesc++;
1924
1925 if (rxdata == rxmax) { /* handle the wrap point */
1926 rxdata = sc->rxstart;
1927 rxdesc = (sca_descriptor *)
1928 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1929 }
1930 }
1931 }
1932
1933 /*
1934 * If single is set, just eat a packet. Otherwise eat everything up to
1935 * where cda points. Update pointers to point to the next packet.
1936 *
1937 * This handles "flushing" of a packet as received...
1938 *
1939 * If the "single" parameter is zero, all pending reeceive traffic will
1940 * be flushed out of existence. A non-zero value will only drop the
1941 * *next* (currently) pending packet...
1942 */
1943 static void
1944 sr_eat_packet(struct sr_softc *sc, int single)
1945 {
1946 struct sr_hardc *hc;
1947 sca_descriptor *rxdesc; /* current descriptor being eval'd */
1948 sca_descriptor *endp; /* last descriptor in chain */
1949 sca_descriptor *cda; /* current start point */
1950 u_int loopcnt = 0; /* count of packets flushed ??? */
1951 u_char stat; /* captured status byte from descr */
1952
1953 hc = sc->hc;
1954 cda = (sca_descriptor *)(hc->mem_start +
1955 (SRC_GET16(hc->sca_base,
1956 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1957 hc->winmsk));
1958
1959 /*
1960 * loop until desc->stat == (0xff || EOM) Clear the status and
1961 * length in the descriptor. Increment the descriptor.
1962 */
1963 if (hc->mempages)
1964 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1965
1966 rxdesc = (sca_descriptor *)
1967 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1968 endp = rxdesc;
1969 rxdesc = &rxdesc[sc->rxhind];
1970 endp = &endp[sc->rxmax];
1971
1972 /*
1973 * allow loop, but abort it if we wrap completely...
1974 */
1975 while (rxdesc != cda) {
1976 loopcnt++;
1977
1978 if (loopcnt > sc->rxmax) {
1979 kprintf("sr%d: eat pkt %d loop, cda %x, "
1980 "rxdesc %x, stat %x.\n",
1981 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1982 rxdesc->stat);
1983 break;
1984 }
1985 stat = rxdesc->stat;
1986
1987 rxdesc->len = 0;
1988 rxdesc->stat = 0xff;
1989
1990 rxdesc++;
1991 sc->rxhind++;
1992
1993 if (rxdesc == endp) {
1994 rxdesc = (sca_descriptor *)
1995 (hc->mem_start + (sc->rxdesc & hc->winmsk));
1996 sc->rxhind = 0;
1997 }
1998 if (single && (stat == SCA_DESC_EOM))
1999 break;
2000 }
2001
2002 /*
2003 * Update the eda to the previous descriptor.
2004 */
2005 rxdesc = (sca_descriptor *)sc->rxdesc;
2006 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2007
2008 SRC_PUT16(hc->sca_base,
2009 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2010 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2011 }
2012
2013 /*
2014 * While there is packets available in the rx buffer, read them out
2015 * into mbufs and ship them off.
2016 */
2017 static void
2018 sr_get_packets(struct sr_softc *sc)
2019 {
2020 u_char rxstat; /* acquired status byte */
2021 int i;
2022 int pkts; /* count of packets found */
2023 int rxndx; /* rcv buffer index */
2024 int tries; /* settling time counter */
2025 u_int len; /* length of pending packet */
2026 struct sr_hardc *hc; /* card-level information */
2027 sca_descriptor *rxdesc; /* descriptor in memory */
2028 #ifndef NETGRAPH
2029 struct ifnet *ifp; /* network intf ctl table */
2030 #endif /* NETGRAPH */
2031 struct mbuf *m = NULL; /* message buffer */
2032
2033 #if BUGGY > 0
2034 kprintf("sr_get_packets(sc=%08x)\n", sc);
2035 #endif
2036
2037 hc = sc->hc;
2038 #ifndef NETGRAPH
2039 ifp = &sc->ifsppp.pp_if;
2040 #endif /* NETGRAPH */
2041
2042 if (hc->mempages) {
2043 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2044 SRC_SET_ON(hc->iobase); /* enable shared memory */
2045 }
2046 pkts = 0; /* reset count of found packets */
2047
2048 /*
2049 * for each complete packet in the receiving pool, process each
2050 * packet...
2051 */
2052 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */
2053 /*
2054 * I have seen situations where we got the interrupt but the
2055 * status value wasn't deposited. This code should allow
2056 * the status byte's value to settle...
2057 */
2058
2059 tries = 5;
2060
2061 while ((rxstat == 0x00ff)
2062 && --tries)
2063 sr_packet_avail(sc, &len, &rxstat);
2064
2065 #if BUGGY > 1
2066 kprintf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2067 len, rxstat);
2068 #endif
2069
2070 pkts++;
2071 #ifdef NETGRAPH
2072 sc->inbytes += len;
2073 sc->inlast = 0;
2074 #endif /* NETGRAPH */
2075
2076 /*
2077 * OK, we've settled the incoming message status. We can now
2078 * process it...
2079 */
2080 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2081 #if BUGGY > 1
2082 kprintf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2083 sc->unit, rxstat, len);
2084 #endif
2085
2086 MGETHDR(m, MB_DONTWAIT, MT_DATA);
2087 if (m == NULL) {
2088 /*
2089 * eat (flush) packet if get mbuf fail!!
2090 */
2091 sr_eat_packet(sc, 1);
2092 continue;
2093 }
2094 /*
2095 * construct control information for pass-off
2096 */
2097 #ifndef NETGRAPH
2098 m->m_pkthdr.rcvif = ifp;
2099 #else
2100 m->m_pkthdr.rcvif = NULL;
2101 #endif /* NETGRAPH */
2102 m->m_pkthdr.len = m->m_len = len;
2103 if (len > MHLEN) {
2104 MCLGET(m, MB_DONTWAIT);
2105 if ((m->m_flags & M_EXT) == 0) {
2106 /*
2107 * We couldn't get a big enough
2108 * message packet, so we'll send the
2109 * packet to /dev/null...
2110 */
2111 m_freem(m);
2112 sr_eat_packet(sc, 1);
2113 continue;
2114 }
2115 }
2116 /*
2117 * OK, we've got a good message buffer. Now we can
2118 * copy the received message into it
2119 */
2120 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */
2121
2122 #ifndef NETGRAPH
2123 BPF_MTAP(ifp, m);
2124
2125 #if BUGGY > 3
2126 {
2127 u_char *bp;
2128
2129 bp = (u_char *)m;
2130 kprintf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2131 sc->unit,
2132 bp[0], bp[1], bp[2],
2133 bp[4], bp[5], bp[6]);
2134 }
2135 #endif
2136 sppp_input(ifp, m);
2137 ifp->if_ipackets++;
2138
2139 #else /* NETGRAPH */
2140 #if BUGGY > 3
2141 {
2142 u_char *bp;
2143
2144 bp = mtod(m,u_char *);
2145 kprintf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2146 sc->unit,
2147 bp[0], bp[1], bp[2],
2148 bp[4], bp[5], bp[6]);
2149 kprintf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2150 bp[6], bp[7], bp[8],
2151 bp[9], bp[10], bp[11]);
2152 }
2153 #endif
2154 ng_queue_data(sc->hook, m, NULL);
2155 sc->ipackets++;
2156 #endif /* NETGRAPH */
2157 /*
2158 * Update the eda to the previous descriptor.
2159 */
2160 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2161 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2162
2163 rxdesc = (sca_descriptor *)sc->rxdesc;
2164 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2165 rxdesc = &rxdesc[rxndx];
2166
2167 SRC_PUT16(hc->sca_base,
2168 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2169 (u_short)((u_int)(rxdesc + hc->mem_pstart)
2170 & 0xffff));
2171
2172 } else {
2173 int got_st3, got_cda, got_eda;
2174 int tries = 5;
2175
2176 while ((rxstat == 0xff) && --tries)
2177 sr_packet_avail(sc, &len, &rxstat);
2178
2179 /*
2180 * It look like we get an interrupt early
2181 * sometimes and then the status is not
2182 * filled in yet.
2183 */
2184 if (tries && (tries != 5))
2185 continue;
2186
2187 /*
2188 * This chunk of code handles the error packets.
2189 * We'll log them for posterity...
2190 */
2191 sr_eat_packet(sc, 1);
2192
2193 #ifndef NETGRAPH
2194 ifp->if_ierrors++;
2195 #else
2196 sc->ierrors[0]++;
2197 #endif /* NETGRAPH */
2198
2199 got_st3 = SRC_GET8(hc->sca_base,
2200 hc->sca->msci[sc->scachan].st3);
2201 got_cda = SRC_GET16(hc->sca_base,
2202 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2203 got_eda = SRC_GET16(hc->sca_base,
2204 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2205
2206 #if BUGGY > 0
2207 kprintf("sr%d: Receive error chan %d, "
2208 "stat %02x, msci st3 %02x,"
2209 "rxhind %d, cda %04x, eda %04x.\n",
2210 sc->unit, sc->scachan, rxstat,
2211 got_st3, sc->rxhind, got_cda, got_eda);
2212 #endif
2213 }
2214 }
2215
2216 #if BUGGY > 0
2217 kprintf("sr%d: sr_get_packets() found %d packet(s)\n",
2218 sc->unit, pkts);
2219 #endif
2220
2221 if (hc->mempages)
2222 SRC_SET_OFF(hc->iobase);
2223 }
2224
2225 /*
2226 * All DMA interrupts come here.
2227 *
2228 * Each channel has two interrupts.
2229 * Interrupt A for errors and Interrupt B for normal stuff like end
2230 * of transmit or receive dmas.
2231 */
2232 static void
2233 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2234 {
2235 u_char dsr; /* contents of DMA Stat Reg */
2236 u_char dotxstart; /* enables for tranmit part */
2237 int mch; /* channel being processed */
2238 struct sr_softc *sc; /* channel's softc structure */
2239 sca_regs *sca = hc->sca;
2240 dmac_channel *dmac; /* dma structure of chip */
2241
2242 #if BUGGY > 0
2243 kprintf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2244 #endif
2245
2246 mch = 0; /* assume chan0 on card */
2247 dotxstart = isr1; /* copy for xmitter starts */
2248
2249 /*
2250 * Shortcut if there is no interrupts for dma channel 0 or 1.
2251 * Skip processing for channel 0 if no incoming hit
2252 */
2253 if ((isr1 & 0x0F) == 0) {
2254 mch = 1;
2255 isr1 >>= 4;
2256 }
2257 do {
2258 sc = &hc->sc[mch];
2259
2260 /*
2261 * Transmit channel - DMA Status Register Evaluation
2262 */
2263 if (isr1 & 0x0C) {
2264 dmac = &sca->dmac[DMAC_TXCH(mch)];
2265
2266 /*
2267 * get the DMA Status Register contents and write
2268 * back to reset interrupt...
2269 */
2270 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2271 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2272
2273 /*
2274 * Check for (& process) a Counter overflow
2275 */
2276 if (dsr & SCA_DSR_COF) {
2277 kprintf("sr%d: TX DMA Counter overflow, "
2278 "txpacket no %lu.\n",
2279 #ifndef NETGRAPH
2280 sc->unit, sc->ifsppp.pp_if.if_opackets);
2281 sc->ifsppp.pp_if.if_oerrors++;
2282 #else
2283 sc->unit, sc->opackets);
2284 sc->oerrors++;
2285 #endif /* NETGRAPH */
2286 }
2287 /*
2288 * Check for (& process) a Buffer overflow
2289 */
2290 if (dsr & SCA_DSR_BOF) {
2291 kprintf("sr%d: TX DMA Buffer overflow, "
2292 "txpacket no %lu, dsr %02x, "
2293 "cda %04x, eda %04x.\n",
2294 #ifndef NETGRAPH
2295 sc->unit, sc->ifsppp.pp_if.if_opackets,
2296 #else
2297 sc->unit, sc->opackets,
2298 #endif /* NETGRAPH */
2299 dsr,
2300 SRC_GET16(hc->sca_base, dmac->cda),
2301 SRC_GET16(hc->sca_base, dmac->eda));
2302 #ifndef NETGRAPH
2303 sc->ifsppp.pp_if.if_oerrors++;
2304 #else
2305 sc->oerrors++;
2306 #endif /* NETGRAPH */
2307 }
2308 /*
2309 * Check for (& process) an End of Transfer (OK)
2310 */
2311 if (dsr & SCA_DSR_EOT) {
2312 /*
2313 * This should be the most common case.
2314 *
2315 * Clear the IFF_OACTIVE flag.
2316 *
2317 * Call srstart to start a new transmit if
2318 * there is data to transmit.
2319 */
2320 #if BUGGY > 0
2321 kprintf("sr%d: TX Completed OK\n", sc->unit);
2322 #endif
2323 sc->xmit_busy = 0;
2324 #ifndef NETGRAPH
2325 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2326 sc->ifsppp.pp_if.if_timer = 0;
2327 #else
2328 /* XXX may need to mark tx inactive? */
2329 sc->out_deficit++;
2330 sc->out_dog = DOG_HOLDOFF;
2331 #endif /* NETGRAPH */
2332
2333 if (sc->txb_inuse && --sc->txb_inuse)
2334 sr_xmit(sc);
2335 }
2336 }
2337 /*
2338 * Receive channel processing of DMA Status Register
2339 */
2340 if (isr1 & 0x03) {
2341 dmac = &sca->dmac[DMAC_RXCH(mch)];
2342
2343 dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2344 SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2345
2346 /*
2347 * End of frame processing (MSG OK?)
2348 */
2349 if (dsr & SCA_DSR_EOM) {
2350 #if BUGGY > 0
2351 int tt, ind;
2352
2353 #ifndef NETGRAPH
2354 tt = sc->ifsppp.pp_if.if_ipackets;
2355 #else /* NETGRAPH */
2356 tt = sc->ipackets;
2357 #endif /* NETGRAPH */
2358 ind = sc->rxhind;
2359 #endif
2360
2361 sr_get_packets(sc);
2362 #if BUGGY > 0
2363 #ifndef NETGRAPH
2364 if (tt == sc->ifsppp.pp_if.if_ipackets)
2365 #else /* NETGRAPH */
2366 if (tt == sc->ipackets)
2367 #endif /* NETGRAPH */
2368 {
2369 sca_descriptor *rxdesc;
2370 int i;
2371
2372 kprintf("SR: RXINTR isr1 %x, dsr %x, "
2373 "no data %d pkts, orxind %d.\n",
2374 dotxstart, dsr, tt, ind);
2375 kprintf("SR: rxdesc %x, rxstart %x, "
2376 "rxend %x, rxhind %d, "
2377 "rxmax %d.\n",
2378 sc->rxdesc, sc->rxstart,
2379 sc->rxend, sc->rxhind,
2380 sc->rxmax);
2381 kprintf("SR: cda %x, eda %x.\n",
2382 SRC_GET16(hc->sca_base, dmac->cda),
2383 SRC_GET16(hc->sca_base, dmac->eda));
2384
2385 if (hc->mempages) {
2386 SRC_SET_ON(hc->iobase);
2387 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2388 }
2389 rxdesc = (sca_descriptor *)
2390 (hc->mem_start +
2391 (sc->rxdesc & hc->winmsk));
2392 rxdesc = &rxdesc[sc->rxhind];
2393
2394 for (i = 0; i < 3; i++, rxdesc++)
2395 kprintf("SR: rxdesc->stat %x, "
2396 "len %d.\n",
2397 rxdesc->stat,
2398 rxdesc->len);
2399
2400 if (hc->mempages)
2401 SRC_SET_OFF(hc->iobase);
2402 }
2403 #endif /* BUGGY */
2404 }
2405 /*
2406 * Check for Counter overflow
2407 */
2408 if (dsr & SCA_DSR_COF) {
2409 kprintf("sr%d: RX DMA Counter overflow, "
2410 "rxpkts %lu.\n",
2411 #ifndef NETGRAPH
2412 sc->unit, sc->ifsppp.pp_if.if_ipackets);
2413 sc->ifsppp.pp_if.if_ierrors++;
2414 #else /* NETGRAPH */
2415 sc->unit, sc->ipackets);
2416 sc->ierrors[1]++;
2417 #endif /* NETGRAPH */
2418 }
2419 /*
2420 * Check for Buffer overflow
2421 */
2422 if (dsr & SCA_DSR_BOF) {
2423 kprintf("sr%d: RX DMA Buffer overflow, "
2424 "rxpkts %lu, rxind %d, "
2425 "cda %x, eda %x, dsr %x.\n",
2426 #ifndef NETGRAPH
2427 sc->unit, sc->ifsppp.pp_if.if_ipackets,
2428 #else /* NETGRAPH */
2429 sc->unit, sc->ipackets,
2430 #endif /* NETGRAPH */
2431 sc->rxhind,
2432 SRC_GET16(hc->sca_base, dmac->cda),
2433 SRC_GET16(hc->sca_base, dmac->eda),
2434 dsr);
2435
2436 /*
2437 * Make sure we eat as many as possible.
2438 * Then get the system running again.
2439 */
2440 if (hc->mempages)
2441 SRC_SET_ON(hc->iobase);
2442
2443 sr_eat_packet(sc, 0);
2444 #ifndef NETGRAPH
2445 sc->ifsppp.pp_if.if_ierrors++;
2446 #else /* NETGRAPH */
2447 sc->ierrors[2]++;
2448 #endif /* NETGRAPH */
2449
2450 SRC_PUT8(hc->sca_base,
2451 sca->msci[mch].cmd,
2452 SCA_CMD_RXMSGREJ);
2453
2454 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2455
2456 #if BUGGY > 0
2457 kprintf("sr%d: RX DMA Buffer overflow, "
2458 "rxpkts %lu, rxind %d, "
2459 "cda %x, eda %x, dsr %x. After\n",
2460 sc->unit,
2461 #ifndef NETGRAPH
2462 sc->ipackets,
2463 #else /* NETGRAPH */
2464 sc->ifsppp.pp_if.if_ipackets,
2465 #endif /* NETGRAPH */
2466 sc->rxhind,
2467 SRC_GET16(hc->sca_base, dmac->cda),
2468 SRC_GET16(hc->sca_base, dmac->eda),
2469 SRC_GET8(hc->sca_base, dmac->dsr));
2470 #endif
2471
2472 if (hc->mempages)
2473 SRC_SET_OFF(hc->iobase);
2474 }
2475 /*
2476 * End of Transfer
2477 */
2478 if (dsr & SCA_DSR_EOT) {
2479 /*
2480 * If this happen, it means that we are
2481 * receiving faster than what the processor
2482 * can handle.
2483 *
2484 * XXX We should enable the dma again.
2485 */
2486 kprintf("sr%d: RX End of xfer, rxpkts %lu.\n",
2487 sc->unit,
2488 #ifndef NETGRAPH
2489 sc->ifsppp.pp_if.if_ipackets);
2490 sc->ifsppp.pp_if.if_ierrors++;
2491 #else
2492 sc->ipackets);
2493 sc->ierrors[3]++;
2494 #endif /* NETGRAPH */
2495 }
2496 }
2497 isr1 >>= 4; /* process next half of ISR */
2498 mch++; /* and move to next channel */
2499 } while ((mch < NCHAN) && isr1); /* loop for each chn */
2500
2501 /*
2502 * Now that we have done all the urgent things, see if we can fill
2503 * the transmit buffers.
2504 */
2505 for (mch = 0; mch < NCHAN; mch++) {
2506 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2507 sc = &hc->sc[mch];
2508 #ifndef NETGRAPH
2509 srstart(&sc->ifsppp.pp_if);
2510 #else
2511 srstart(sc);
2512 #endif /* NETGRAPH */
2513 }
2514 dotxstart >>= 4;/* shift for next channel */
2515 }
2516 }
2517 #ifndef NETGRAPH
2518 #ifdef USE_MODEMCK
2519 /*
2520 * Perform timeout on an FR channel
2521 *
2522 * Establish a periodic check of open N2 ports; If
2523 * a port is open/active, its DCD state is checked
2524 * and a loss of DCD is recognized (and eventually
2525 * processed).
2526 */
2527 static void
2528 sr_modemck(void *arg)
2529 {
2530 int card; /* card index in table */
2531 int cards; /* card list index */
2532 int mch; /* channel on card */
2533 u_char dcd_v; /* Data Carrier Detect */
2534 u_char got_st0; /* contents of ST0 */
2535 u_char got_st1; /* contents of ST1 */
2536 u_char got_st2; /* contents of ST2 */
2537 u_char got_st3; /* contents of ST3 */
2538 struct sr_hardc *hc; /* card's configuration */
2539 struct sr_hardc *Card[16];/* up to 16 cards in system */
2540 struct sr_softc *sc; /* channel's softc structure */
2541 struct ifnet *ifp; /* interface control table */
2542 msci_channel *msci; /* regs specific to channel */
2543
2544 crit_enter();
2545
2546 #if 0
2547 if (sr_opens == 0) { /* count of "up" channels */
2548 sr_watcher = 0; /* indicate no watcher */
2549
2550 crit_exit();
2551
2552 return;
2553 }
2554 #endif
2555
2556 sr_watcher = 1; /* mark that we're online */
2557
2558 /*
2559 * Now we'll need a list of cards to process. Since we can handle
2560 * both ISA and PCI cards (and I didn't think of making this logic
2561 * global YET) we'll generate a single table of card table
2562 * addresses.
2563 */
2564 cards = 0;
2565
2566 for (card = 0; card < NSR; card++) {
2567 hc = &sr_hardc[card];
2568
2569 if (hc->sc == (void *)0)
2570 continue;
2571
2572 Card[cards++] = hc;
2573 }
2574
2575 hc = sr_hardc_pci;
2576
2577 while (hc) {
2578 Card[cards++] = hc;
2579 hc = hc->next;
2580 }
2581
2582 /*
2583 * OK, we've got work we can do. Let's do it... (Please note that
2584 * this code _only_ deals w/ ISA cards)
2585 */
2586 for (card = 0; card < cards; card++) {
2587 hc = Card[card];/* get card table */
2588
2589 for (mch = 0; mch < hc->numports; mch++) {
2590 sc = &hc->sc[mch];
2591
2592 ifp = &sc->ifsppp.pp_if;
2593
2594 /*
2595 * if this channel isn't "up", skip it
2596 */
2597 if ((ifp->if_flags & IFF_UP) == 0)
2598 continue;
2599
2600 /*
2601 * OK, now we can go looking at this channel's
2602 * actual register contents...
2603 */
2604 msci = &hc->sca->msci[sc->scachan];
2605
2606 /*
2607 * OK, now we'll look into the actual status of this
2608 * channel...
2609 *
2610 * I suck in more registers than strictly needed
2611 */
2612 got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2613 got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2614 got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2615 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2616
2617 /*
2618 * We want to see if the DCD signal is up (DCD is
2619 * true if zero)
2620 */
2621 dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2622
2623 if (dcd_v == 0)
2624 kprintf("sr%d: DCD lost\n", sc->unit);
2625 }
2626 }
2627
2628 /*
2629 * OK, now set up for the next modem signal checking pass...
2630 */
2631 timeout(sr_modemck, NULL, hz);
2632
2633 crit_exit();
2634 }
2635 #endif
2636 #else /* NETGRAPH */
2637 /*
2638 * If a port is open/active, it's DCD state is checked
2639 * and a loss of DCD is recognized (and eventually processed?).
2640 */
2641 static void
2642 sr_modemck(struct sr_softc *sc )
2643 {
2644 u_char got_st3; /* contents of ST3 */
2645 struct sr_hardc *hc = sc->hc; /* card's configuration */
2646 msci_channel *msci; /* regs specific to channel */
2647
2648 crit_enter();
2649
2650 if (sc->running == 0) {
2651 crit_exit();
2652 return;
2653 }
2654
2655 /*
2656 * OK, now we can go looking at this channel's register contents...
2657 */
2658 msci = &hc->sca->msci[sc->scachan];
2659 got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2660
2661 /*
2662 * We want to see if the DCD signal is up (DCD is true if zero)
2663 */
2664 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2665
2666 crit_exit();
2667 }
2668
2669 #endif /* NETGRAPH */
2670 static void
2671 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2672 {
2673 kprintf("src%d: SRINTR: MSCI\n", hc->cunit);
2674 }
2675
2676 static void
2677 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2678 {
2679 kprintf("src%d: SRINTR: TIMER\n", hc->cunit);
2680 }
2681
2682 #ifdef NETGRAPH
2683 /*****************************************
2684 * Device timeout/watchdog routine.
2685 * called once per second.
2686 * checks to see that if activity was expected, that it hapenned.
2687 * At present we only look to see if expected output was completed.
2688 */
2689 static void
2690 ngsr_watchdog_frame(void * arg)
2691 {
2692 struct sr_softc * sc = arg;
2693 int speed;
2694
2695 crit_enter();
2696
2697 if (sc->running == 0) {
2698 crit_enter();
2699 return; /* if we are not running let timeouts die */
2700 }
2701 /*
2702 * calculate the apparent throughputs
2703 * XXX a real hack
2704 */
2705
2706 speed = sc->inbytes - sc->lastinbytes;
2707 sc->lastinbytes = sc->inbytes;
2708 if ( sc->inrate < speed )
2709 sc->inrate = speed;
2710 speed = sc->outbytes - sc->lastoutbytes;
2711 sc->lastoutbytes = sc->outbytes;
2712 if ( sc->outrate < speed )
2713 sc->outrate = speed;
2714 sc->inlast++;
2715
2716 crit_exit();
2717
2718 if ((sc->inlast > QUITE_A_WHILE)
2719 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2720 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2721
2722 crit_enter();
2723
2724 sr_down(sc);
2725 sr_up(sc);
2726 sc->inlast = sc->out_deficit = 0;
2727
2728 crit_exit();
2729 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2730 if (sc->out_dog == 0) {
2731 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2732 sc->unit);
2733
2734 crit_enter();
2735
2736 srwatchdog(sc);
2737 #if 0
2738 sr_down(sc);
2739 sr_up(sc);
2740 #endif
2741
2742 crit_exit();
2743
2744 sc->inlast = sc->out_deficit = 0;
2745 } else {
2746 sc->out_dog--;
2747 }
2748 }
2749 sr_modemck(sc); /* update the DCD status */
2750 callout_reset(&sc->sr_timer, hz, ngsr_watchdog_frame, sc);
2751 }
2752
2753 /***********************************************************************
2754 * This section contains the methods for the Netgraph interface
2755 ***********************************************************************/
2756 /*
2757 * It is not possible or allowable to create a node of this type.
2758 * If the hardware exists, it will already have created it.
2759 */
2760 static int
2761 ngsr_constructor(node_p *nodep)
2762 {
2763 return (EINVAL);
2764 }
2765
2766 /*
2767 * give our ok for a hook to be added...
2768 * If we are not running this should kick the device into life.
2769 * The hook's private info points to our stash of info about that
2770 * channel.
2771 */
2772 static int
2773 ngsr_newhook(node_p node, hook_p hook, const char *name)
2774 {
2775 struct sr_softc * sc = node->private;
2776
2777 /*
2778 * check if it's our friend the debug hook
2779 */
2780 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2781 hook->private = NULL; /* paranoid */
2782 sc->debug_hook = hook;
2783 return (0);
2784 }
2785
2786 /*
2787 * Check for raw mode hook.
2788 */
2789 if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2790 return (EINVAL);
2791 }
2792 hook->private = sc;
2793 sc->hook = hook;
2794 sc->datahooks++;
2795 sr_up(sc);
2796 return (0);
2797 }
2798
2799 /*
2800 * incoming messages.
2801 * Just respond to the generic TEXT_STATUS message
2802 */
2803 static int
2804 ngsr_rcvmsg(node_p node,
2805 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2806 {
2807 struct sr_softc * sc;
2808 int error = 0;
2809
2810 sc = node->private;
2811 switch (msg->header.typecookie) {
2812 case NG_SR_COOKIE:
2813 error = EINVAL;
2814 break;
2815 case NGM_GENERIC_COOKIE:
2816 switch(msg->header.cmd) {
2817 case NGM_TEXT_STATUS: {
2818 char *arg;
2819 int pos = 0;
2820 int resplen = sizeof(struct ng_mesg) + 512;
2821 MALLOC(*resp, struct ng_mesg *, resplen,
2822 M_NETGRAPH, M_INTWAIT | M_ZERO);
2823 if (*resp == NULL) {
2824 error = ENOMEM;
2825 break;
2826 }
2827 arg = (*resp)->data;
2828
2829 /*
2830 * Put in the throughput information.
2831 */
2832 pos = ksprintf(arg, "%ld bytes in, %ld bytes out\n"
2833 "highest rate seen: %ld B/S in, %ld B/S out\n",
2834 sc->inbytes, sc->outbytes,
2835 sc->inrate, sc->outrate);
2836 pos += ksprintf(arg + pos,
2837 "%ld output errors\n",
2838 sc->oerrors);
2839 pos += ksprintf(arg + pos,
2840 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2841 sc->ierrors[0],
2842 sc->ierrors[1],
2843 sc->ierrors[2],
2844 sc->ierrors[3],
2845 sc->ierrors[4],
2846 sc->ierrors[5]);
2847
2848 (*resp)->header.version = NG_VERSION;
2849 (*resp)->header.arglen = strlen(arg) + 1;
2850 (*resp)->header.token = msg->header.token;
2851 (*resp)->header.typecookie = NG_SR_COOKIE;
2852 (*resp)->header.cmd = msg->header.cmd;
2853 strlcpy((*resp)->header.cmdstr, "status",
2854 NG_CMDSTRSIZ);
2855 }
2856 break;
2857 default:
2858 error = EINVAL;
2859 break;
2860 }
2861 break;
2862 default:
2863 error = EINVAL;
2864 break;
2865 }
2866 kfree(msg, M_NETGRAPH);
2867 return (error);
2868 }
2869
2870 /*
2871 * get data from another node and transmit it to the correct channel
2872 */
2873 static int
2874 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2875 {
2876 int error = 0;
2877 struct sr_softc * sc = hook->node->private;
2878 struct ifqueue *xmitq_p;
2879
2880 /*
2881 * data doesn't come in from just anywhere (e.g control hook)
2882 */
2883 if ( hook->private == NULL) {
2884 error = ENETDOWN;
2885 goto bad;
2886 }
2887
2888 /*
2889 * Now queue the data for when it can be sent
2890 */
2891 if (meta && meta->priority > 0) {
2892 xmitq_p = (&sc->xmitq_hipri);
2893 } else {
2894 xmitq_p = (&sc->xmitq);
2895 }
2896
2897 crit_enter();
2898
2899 if (IF_QFULL(xmitq_p)) {
2900 IF_DROP(xmitq_p);
2901
2902 crit_exit();
2903
2904 error = ENOBUFS;
2905 goto bad;
2906 }
2907 IF_ENQUEUE(xmitq_p, m);
2908 srstart(sc);
2909
2910 crit_exit();
2911
2912 return (0);
2913
2914 bad:
2915 /*
2916 * It was an error case.
2917 * check if we need to free the mbuf, and then return the error
2918 */
2919 NG_FREE_DATA(m, meta);
2920 return (error);
2921 }
2922
2923 /*
2924 * do local shutdown processing..
2925 * this node will refuse to go away, unless the hardware says to..
2926 * don't unref the node, or remove our name. just clear our links up.
2927 */
2928 static int
2929 ngsr_rmnode(node_p node)
2930 {
2931 struct sr_softc * sc = node->private;
2932
2933 sr_down(sc);
2934 ng_cutlinks(node);
2935 node->flags &= ~NG_INVALID; /* bounce back to life */
2936 return (0);
2937 }
2938
2939 /* already linked */
2940 static int
2941 ngsr_connect(hook_p hook)
2942 {
2943 /* be really amiable and just say "YUP that's OK by me! " */
2944 return (0);
2945 }
2946
2947 /*
2948 * notify on hook disconnection (destruction)
2949 *
2950 * Invalidate the private data associated with this dlci.
2951 * For this type, removal of the last link resets tries to destroy the node.
2952 * As the device still exists, the shutdown method will not actually
2953 * destroy the node, but reset the device and leave it 'fresh' :)
2954 *
2955 * The node removal code will remove all references except that owned by the
2956 * driver.
2957 */
2958 static int
2959 ngsr_disconnect(hook_p hook)
2960 {
2961 struct sr_softc * sc = hook->node->private;
2962 /*
2963 * If it's the data hook, then free resources etc.
2964 */
2965 if (hook->private) {
2966 crit_enter();
2967
2968 sc->datahooks--;
2969 if (sc->datahooks == 0)
2970 sr_down(sc);
2971
2972 crit_exit();
2973 } else {
2974 sc->debug_hook = NULL;
2975 }
2976 return (0);
2977 }
2978
2979 /*
2980 * called during bootup
2981 * or LKM loading to put this type into the list of known modules
2982 */
2983 static void
2984 ngsr_init(void *ignored)
2985 {
2986 if (ng_newtype(&typestruct))
2987 kprintf("ngsr install failed\n");
2988 ngsr_done_init = 1;
2989 }
2990 #endif /* NETGRAPH */
2991
2992 /*
2993 ********************************* END ************************************
2994 */
DragonFly BSD